drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static char get_active_flag(struct drm_i915_gem_object *obj)
  93 {
  94         return obj->active ? '*' : ' ';
  95 }
  96
  97 static char get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         return obj->pin_display ? 'p' : ' ';
 100 }
 101
 102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
 103 {
 104         switch (obj->tiling_mode) {
 105         default:
 106         case I915_TILING_NONE: return ' ';
 107         case I915_TILING_X: return 'X';
 108         case I915_TILING_Y: return 'Y';
 109         }
 110 }
 111
 112 static char get_global_flag(struct drm_i915_gem_object *obj)
 113 {
 114         return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
 115 }
 116
 117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->mapping ? 'M' : ' ';
 120 }
 121
 122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 123 {
 124         u64 size = 0;
 125         struct i915_vma *vma;
 126
 127         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 128                 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
 129                         size += vma->node.size;
 130         }
 131
 132         return size;
 133 }
 134
 135 static void
 136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 137 {
 138         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 139         struct intel_engine_cs *engine;
 140         struct i915_vma *vma;
 141         int pin_count = 0;
 142         enum intel_engine_id id;
 143
 144         lockdep_assert_held(&obj->base.dev->struct_mutex);
 145
 146         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 147                    &obj->base,
 148                    get_active_flag(obj),
 149                    get_pin_flag(obj),
 150                    get_tiling_flag(obj),
 151                    get_global_flag(obj),
 152                    get_pin_mapped_flag(obj),
 153                    obj->base.size / 1024,
 154                    obj->base.read_domains,
 155                    obj->base.write_domain);
 156         for_each_engine_id(engine, dev_priv, id)
 157                 seq_printf(m, "%x ",
 158                                 i915_gem_request_get_seqno(obj->last_read_req[id]));
 159         seq_printf(m, "] %x %x%s%s%s",
 160                    i915_gem_request_get_seqno(obj->last_write_req),
 161                    i915_gem_request_get_seqno(obj->last_fenced_req),
 162                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 163                    obj->dirty ? " dirty" : "",
 164                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 165         if (obj->base.name)
 166                 seq_printf(m, " (name: %d)", obj->base.name);
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (vma->pin_count > 0)
 169                         pin_count++;
 170         }
 171         seq_printf(m, " (pinned x %d)", pin_count);
 172         if (obj->pin_display)
 173                 seq_printf(m, " (display)");
 174         if (obj->fence_reg != I915_FENCE_REG_NONE)
 175                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 176         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 177                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 178                            vma->is_ggtt ? "g" : "pp",
 179                            vma->node.start, vma->node.size);
 180                 if (vma->is_ggtt)
 181                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 182                 seq_puts(m, ")");
 183         }
 184         if (obj->stolen)
 185                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 186         if (obj->pin_display || obj->fault_mappable) {
 187                 char s[3], *t = s;
 188                 if (obj->pin_display)
 189                         *t++ = 'p';
 190                 if (obj->fault_mappable)
 191                         *t++ = 'f';
 192                 *t = '\0';
 193                 seq_printf(m, " (%s mappable)", s);
 194         }
 195         if (obj->last_write_req != NULL)
 196                 seq_printf(m, " (%s)",
 197                            i915_gem_request_get_engine(obj->last_write_req)->name);
 198         if (obj->frontbuffer_bits)
 199                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 200 }
 201
 202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 203 {
 204         struct drm_info_node *node = m->private;
 205         uintptr_t list = (uintptr_t) node->info_ent->data;
 206         struct list_head *head;
 207         struct drm_device *dev = node->minor->dev;
 208         struct drm_i915_private *dev_priv = to_i915(dev);
 209         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 210         struct i915_vma *vma;
 211         u64 total_obj_size, total_gtt_size;
 212         int count, ret;
 213
 214         ret = mutex_lock_interruptible(&dev->struct_mutex);
 215         if (ret)
 216                 return ret;
 217
 218         /* FIXME: the user of this interface might want more than just GGTT */
 219         switch (list) {
 220         case ACTIVE_LIST:
 221                 seq_puts(m, "Active:\n");
 222                 head = &ggtt->base.active_list;
 223                 break;
 224         case INACTIVE_LIST:
 225                 seq_puts(m, "Inactive:\n");
 226                 head = &ggtt->base.inactive_list;
 227                 break;
 228         default:
 229                 mutex_unlock(&dev->struct_mutex);
 230                 return -EINVAL;
 231         }
 232
 233         total_obj_size = total_gtt_size = count = 0;
 234         list_for_each_entry(vma, head, vm_link) {
 235                 seq_printf(m, "   ");
 236                 describe_obj(m, vma->obj);
 237                 seq_printf(m, "\n");
 238                 total_obj_size += vma->obj->base.size;
 239                 total_gtt_size += vma->node.size;
 240                 count++;
 241         }
 242         mutex_unlock(&dev->struct_mutex);
 243
 244         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 245                    count, total_obj_size, total_gtt_size);
 246         return 0;
 247 }
 248
 249 static int obj_rank_by_stolen(void *priv,
 250                               struct list_head *A, struct list_head *B)
 251 {
 252         struct drm_i915_gem_object *a =
 253                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 254         struct drm_i915_gem_object *b =
 255                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 256
 257         if (a->stolen->start < b->stolen->start)
 258                 return -1;
 259         if (a->stolen->start > b->stolen->start)
 260                 return 1;
 261         return 0;
 262 }
 263
 264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 265 {
 266         struct drm_info_node *node = m->private;
 267         struct drm_device *dev = node->minor->dev;
 268         struct drm_i915_private *dev_priv = to_i915(dev);
 269         struct drm_i915_gem_object *obj;
 270         u64 total_obj_size, total_gtt_size;
 271         LIST_HEAD(stolen);
 272         int count, ret;
 273
 274         ret = mutex_lock_interruptible(&dev->struct_mutex);
 275         if (ret)
 276                 return ret;
 277
 278         total_obj_size = total_gtt_size = count = 0;
 279         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 280                 if (obj->stolen == NULL)
 281                         continue;
 282
 283                 list_add(&obj->obj_exec_link, &stolen);
 284
 285                 total_obj_size += obj->base.size;
 286                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 287                 count++;
 288         }
 289         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 290                 if (obj->stolen == NULL)
 291                         continue;
 292
 293                 list_add(&obj->obj_exec_link, &stolen);
 294
 295                 total_obj_size += obj->base.size;
 296                 count++;
 297         }
 298         list_sort(NULL, &stolen, obj_rank_by_stolen);
 299         seq_puts(m, "Stolen:\n");
 300         while (!list_empty(&stolen)) {
 301                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 302                 seq_puts(m, "   ");
 303                 describe_obj(m, obj);
 304                 seq_putc(m, '\n');
 305                 list_del_init(&obj->obj_exec_link);
 306         }
 307         mutex_unlock(&dev->struct_mutex);
 308
 309         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 310                    count, total_obj_size, total_gtt_size);
 311         return 0;
 312 }
 313
 314 #define count_objects(list, member) do { \
 315         list_for_each_entry(obj, list, member) { \
 316                 size += i915_gem_obj_total_ggtt_size(obj); \
 317                 ++count; \
 318                 if (obj->map_and_fenceable) { \
 319                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 320                         ++mappable_count; \
 321                 } \
 322         } \
 323 } while (0)
 324
 325 struct file_stats {
 326         struct drm_i915_file_private *file_priv;
 327         unsigned long count;
 328         u64 total, unbound;
 329         u64 global, shared;
 330         u64 active, inactive;
 331 };
 332
 333 static int per_file_stats(int id, void *ptr, void *data)
 334 {
 335         struct drm_i915_gem_object *obj = ptr;
 336         struct file_stats *stats = data;
 337         struct i915_vma *vma;
 338
 339         stats->count++;
 340         stats->total += obj->base.size;
 341
 342         if (obj->base.name || obj->base.dma_buf)
 343                 stats->shared += obj->base.size;
 344
 345         if (USES_FULL_PPGTT(obj->base.dev)) {
 346                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
 347                         struct i915_hw_ppgtt *ppgtt;
 348
 349                         if (!drm_mm_node_allocated(&vma->node))
 350                                 continue;
 351
 352                         if (vma->is_ggtt) {
 353                                 stats->global += obj->base.size;
 354                                 continue;
 355                         }
 356
 357                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 358                         if (ppgtt->file_priv != stats->file_priv)
 359                                 continue;
 360
 361                         if (obj->active) /* XXX per-vma statistic */
 362                                 stats->active += obj->base.size;
 363                         else
 364                                 stats->inactive += obj->base.size;
 365
 366                         return 0;
 367                 }
 368         } else {
 369                 if (i915_gem_obj_ggtt_bound(obj)) {
 370                         stats->global += obj->base.size;
 371                         if (obj->active)
 372                                 stats->active += obj->base.size;
 373                         else
 374                                 stats->inactive += obj->base.size;
 375                         return 0;
 376                 }
 377         }
 378
 379         if (!list_empty(&obj->global_list))
 380                 stats->unbound += obj->base.size;
 381
 382         return 0;
 383 }
 384
 385 #define print_file_stats(m, name, stats) do { \
 386         if (stats.count) \
 387                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 388                            name, \
 389                            stats.count, \
 390                            stats.total, \
 391                            stats.active, \
 392                            stats.inactive, \
 393                            stats.global, \
 394                            stats.shared, \
 395                            stats.unbound); \
 396 } while (0)
 397
 398 static void print_batch_pool_stats(struct seq_file *m,
 399                                    struct drm_i915_private *dev_priv)
 400 {
 401         struct drm_i915_gem_object *obj;
 402         struct file_stats stats;
 403         struct intel_engine_cs *engine;
 404         int j;
 405
 406         memset(&stats, 0, sizeof(stats));
 407
 408         for_each_engine(engine, dev_priv) {
 409                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 410                         list_for_each_entry(obj,
 411                                             &engine->batch_pool.cache_list[j],
 412                                             batch_pool_link)
 413                                 per_file_stats(0, obj, &stats);
 414                 }
 415         }
 416
 417         print_file_stats(m, "[k]batch pool", stats);
 418 }
 419
 420 static int per_file_ctx_stats(int id, void *ptr, void *data)
 421 {
 422         struct i915_gem_context *ctx = ptr;
 423         int n;
 424
 425         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 426                 if (ctx->engine[n].state)
 427                         per_file_stats(0, ctx->engine[n].state, data);
 428                 if (ctx->engine[n].ringbuf)
 429                         per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
 430         }
 431
 432         return 0;
 433 }
 434
 435 static void print_context_stats(struct seq_file *m,
 436                                 struct drm_i915_private *dev_priv)
 437 {
 438         struct file_stats stats;
 439         struct drm_file *file;
 440
 441         memset(&stats, 0, sizeof(stats));
 442
 443         mutex_lock(&dev_priv->drm.struct_mutex);
 444         if (dev_priv->kernel_context)
 445                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 446
 447         list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
 448                 struct drm_i915_file_private *fpriv = file->driver_priv;
 449                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 450         }
 451         mutex_unlock(&dev_priv->drm.struct_mutex);
 452
 453         print_file_stats(m, "[k]contexts", stats);
 454 }
 455
 456 #define count_vmas(list, member) do { \
 457         list_for_each_entry(vma, list, member) { \
 458                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 459                 ++count; \
 460                 if (vma->obj->map_and_fenceable) { \
 461                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 462                         ++mappable_count; \
 463                 } \
 464         } \
 465 } while (0)
 466
 467 static int i915_gem_object_info(struct seq_file *m, void* data)
 468 {
 469         struct drm_info_node *node = m->private;
 470         struct drm_device *dev = node->minor->dev;
 471         struct drm_i915_private *dev_priv = to_i915(dev);
 472         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 473         u32 count, mappable_count, purgeable_count;
 474         u64 size, mappable_size, purgeable_size;
 475         unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
 476         u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
 477         struct drm_i915_gem_object *obj;
 478         struct drm_file *file;
 479         struct i915_vma *vma;
 480         int ret;
 481
 482         ret = mutex_lock_interruptible(&dev->struct_mutex);
 483         if (ret)
 484                 return ret;
 485
 486         seq_printf(m, "%u objects, %zu bytes\n",
 487                    dev_priv->mm.object_count,
 488                    dev_priv->mm.object_memory);
 489
 490         size = count = mappable_size = mappable_count = 0;
 491         count_objects(&dev_priv->mm.bound_list, global_list);
 492         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 493                    count, mappable_count, size, mappable_size);
 494
 495         size = count = mappable_size = mappable_count = 0;
 496         count_vmas(&ggtt->base.active_list, vm_link);
 497         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 498                    count, mappable_count, size, mappable_size);
 499
 500         size = count = mappable_size = mappable_count = 0;
 501         count_vmas(&ggtt->base.inactive_list, vm_link);
 502         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 503                    count, mappable_count, size, mappable_size);
 504
 505         size = count = purgeable_size = purgeable_count = 0;
 506         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 507                 size += obj->base.size, ++count;
 508                 if (obj->madv == I915_MADV_DONTNEED)
 509                         purgeable_size += obj->base.size, ++purgeable_count;
 510                 if (obj->mapping) {
 511                         pin_mapped_count++;
 512                         pin_mapped_size += obj->base.size;
 513                         if (obj->pages_pin_count == 0) {
 514                                 pin_mapped_purgeable_count++;
 515                                 pin_mapped_purgeable_size += obj->base.size;
 516                         }
 517                 }
 518         }
 519         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 520
 521         size = count = mappable_size = mappable_count = 0;
 522         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 523                 if (obj->fault_mappable) {
 524                         size += i915_gem_obj_ggtt_size(obj);
 525                         ++count;
 526                 }
 527                 if (obj->pin_display) {
 528                         mappable_size += i915_gem_obj_ggtt_size(obj);
 529                         ++mappable_count;
 530                 }
 531                 if (obj->madv == I915_MADV_DONTNEED) {
 532                         purgeable_size += obj->base.size;
 533                         ++purgeable_count;
 534                 }
 535                 if (obj->mapping) {
 536                         pin_mapped_count++;
 537                         pin_mapped_size += obj->base.size;
 538                         if (obj->pages_pin_count == 0) {
 539                                 pin_mapped_purgeable_count++;
 540                                 pin_mapped_purgeable_size += obj->base.size;
 541                         }
 542                 }
 543         }
 544         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 545                    purgeable_count, purgeable_size);
 546         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 547                    mappable_count, mappable_size);
 548         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 549                    count, size);
 550         seq_printf(m,
 551                    "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
 552                    pin_mapped_count, pin_mapped_purgeable_count,
 553                    pin_mapped_size, pin_mapped_purgeable_size);
 554
 555         seq_printf(m, "%llu [%llu] gtt total\n",
 556                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 557
 558         seq_putc(m, '\n');
 559         print_batch_pool_stats(m, dev_priv);
 560         mutex_unlock(&dev->struct_mutex);
 561
 562         mutex_lock(&dev->filelist_mutex);
 563         print_context_stats(m, dev_priv);
 564         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 565                 struct file_stats stats;
 566                 struct task_struct *task;
 567
 568                 memset(&stats, 0, sizeof(stats));
 569                 stats.file_priv = file->driver_priv;
 570                 spin_lock(&file->table_lock);
 571                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 572                 spin_unlock(&file->table_lock);
 573                 /*
 574                  * Although we have a valid reference on file->pid, that does
 575                  * not guarantee that the task_struct who called get_pid() is
 576                  * still alive (e.g. get_pid(current) => fork() => exit()).
 577                  * Therefore, we need to protect this ->comm access using RCU.
 578                  */
 579                 rcu_read_lock();
 580                 task = pid_task(file->pid, PIDTYPE_PID);
 581                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 582                 rcu_read_unlock();
 583         }
 584         mutex_unlock(&dev->filelist_mutex);
 585
 586         return 0;
 587 }
 588
 589 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 590 {
 591         struct drm_info_node *node = m->private;
 592         struct drm_device *dev = node->minor->dev;
 593         uintptr_t list = (uintptr_t) node->info_ent->data;
 594         struct drm_i915_private *dev_priv = to_i915(dev);
 595         struct drm_i915_gem_object *obj;
 596         u64 total_obj_size, total_gtt_size;
 597         int count, ret;
 598
 599         ret = mutex_lock_interruptible(&dev->struct_mutex);
 600         if (ret)
 601                 return ret;
 602
 603         total_obj_size = total_gtt_size = count = 0;
 604         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 605                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 606                         continue;
 607
 608                 seq_puts(m, "   ");
 609                 describe_obj(m, obj);
 610                 seq_putc(m, '\n');
 611                 total_obj_size += obj->base.size;
 612                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 613                 count++;
 614         }
 615
 616         mutex_unlock(&dev->struct_mutex);
 617
 618         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 619                    count, total_obj_size, total_gtt_size);
 620
 621         return 0;
 622 }
 623
 624 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 625 {
 626         struct drm_info_node *node = m->private;
 627         struct drm_device *dev = node->minor->dev;
 628         struct drm_i915_private *dev_priv = to_i915(dev);
 629         struct intel_crtc *crtc;
 630         int ret;
 631
 632         ret = mutex_lock_interruptible(&dev->struct_mutex);
 633         if (ret)
 634                 return ret;
 635
 636         for_each_intel_crtc(dev, crtc) {
 637                 const char pipe = pipe_name(crtc->pipe);
 638                 const char plane = plane_name(crtc->plane);
 639                 struct intel_flip_work *work;
 640
 641                 spin_lock_irq(&dev->event_lock);
 642                 work = crtc->flip_work;
 643                 if (work == NULL) {
 644                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 645                                    pipe, plane);
 646                 } else {
 647                         u32 pending;
 648                         u32 addr;
 649
 650                         pending = atomic_read(&work->pending);
 651                         if (pending) {
 652                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 653                                            pipe, plane);
 654                         } else {
 655                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 656                                            pipe, plane);
 657                         }
 658                         if (work->flip_queued_req) {
 659                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 660
 661                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 662                                            engine->name,
 663                                            i915_gem_request_get_seqno(work->flip_queued_req),
 664                                            dev_priv->next_seqno,
 665                                            intel_engine_get_seqno(engine),
 666                                            i915_gem_request_completed(work->flip_queued_req));
 667                         } else
 668                                 seq_printf(m, "Flip not associated with any ring\n");
 669                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 670                                    work->flip_queued_vblank,
 671                                    work->flip_ready_vblank,
 672                                    intel_crtc_get_vblank_counter(crtc));
 673                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 674
 675                         if (INTEL_INFO(dev)->gen >= 4)
 676                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 677                         else
 678                                 addr = I915_READ(DSPADDR(crtc->plane));
 679                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 680
 681                         if (work->pending_flip_obj) {
 682                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 683                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 684                         }
 685                 }
 686                 spin_unlock_irq(&dev->event_lock);
 687         }
 688
 689         mutex_unlock(&dev->struct_mutex);
 690
 691         return 0;
 692 }
 693
 694 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 695 {
 696         struct drm_info_node *node = m->private;
 697         struct drm_device *dev = node->minor->dev;
 698         struct drm_i915_private *dev_priv = to_i915(dev);
 699         struct drm_i915_gem_object *obj;
 700         struct intel_engine_cs *engine;
 701         int total = 0;
 702         int ret, j;
 703
 704         ret = mutex_lock_interruptible(&dev->struct_mutex);
 705         if (ret)
 706                 return ret;
 707
 708         for_each_engine(engine, dev_priv) {
 709                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 710                         int count;
 711
 712                         count = 0;
 713                         list_for_each_entry(obj,
 714                                             &engine->batch_pool.cache_list[j],
 715                                             batch_pool_link)
 716                                 count++;
 717                         seq_printf(m, "%s cache[%d]: %d objects\n",
 718                                    engine->name, j, count);
 719
 720                         list_for_each_entry(obj,
 721                                             &engine->batch_pool.cache_list[j],
 722                                             batch_pool_link) {
 723                                 seq_puts(m, "   ");
 724                                 describe_obj(m, obj);
 725                                 seq_putc(m, '\n');
 726                         }
 727
 728                         total += count;
 729                 }
 730         }
 731
 732         seq_printf(m, "total: %d\n", total);
 733
 734         mutex_unlock(&dev->struct_mutex);
 735
 736         return 0;
 737 }
 738
 739 static int i915_gem_request_info(struct seq_file *m, void *data)
 740 {
 741         struct drm_info_node *node = m->private;
 742         struct drm_device *dev = node->minor->dev;
 743         struct drm_i915_private *dev_priv = to_i915(dev);
 744         struct intel_engine_cs *engine;
 745         struct drm_i915_gem_request *req;
 746         int ret, any;
 747
 748         ret = mutex_lock_interruptible(&dev->struct_mutex);
 749         if (ret)
 750                 return ret;
 751
 752         any = 0;
 753         for_each_engine(engine, dev_priv) {
 754                 int count;
 755
 756                 count = 0;
 757                 list_for_each_entry(req, &engine->request_list, list)
 758                         count++;
 759                 if (count == 0)
 760                         continue;
 761
 762                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 763                 list_for_each_entry(req, &engine->request_list, list) {
 764                         struct task_struct *task;
 765
 766                         rcu_read_lock();
 767                         task = NULL;
 768                         if (req->pid)
 769                                 task = pid_task(req->pid, PIDTYPE_PID);
 770                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 771                                    req->fence.seqno,
 772                                    (int) (jiffies - req->emitted_jiffies),
 773                                    task ? task->comm : "<unknown>",
 774                                    task ? task->pid : -1);
 775                         rcu_read_unlock();
 776                 }
 777
 778                 any++;
 779         }
 780         mutex_unlock(&dev->struct_mutex);
 781
 782         if (any == 0)
 783                 seq_puts(m, "No requests\n");
 784
 785         return 0;
 786 }
 787
 788 static void i915_ring_seqno_info(struct seq_file *m,
 789                                  struct intel_engine_cs *engine)
 790 {
 791         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 792         struct rb_node *rb;
 793
 794         seq_printf(m, "Current sequence (%s): %x\n",
 795                    engine->name, intel_engine_get_seqno(engine));
 796         seq_printf(m, "Current user interrupts (%s): %lx\n",
 797                    engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
 798
 799         spin_lock(&b->lock);
 800         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 801                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 802
 803                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 804                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 805         }
 806         spin_unlock(&b->lock);
 807 }
 808
 809 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 810 {
 811         struct drm_info_node *node = m->private;
 812         struct drm_device *dev = node->minor->dev;
 813         struct drm_i915_private *dev_priv = to_i915(dev);
 814         struct intel_engine_cs *engine;
 815         int ret;
 816
 817         ret = mutex_lock_interruptible(&dev->struct_mutex);
 818         if (ret)
 819                 return ret;
 820         intel_runtime_pm_get(dev_priv);
 821
 822         for_each_engine(engine, dev_priv)
 823                 i915_ring_seqno_info(m, engine);
 824
 825         intel_runtime_pm_put(dev_priv);
 826         mutex_unlock(&dev->struct_mutex);
 827
 828         return 0;
 829 }
 830
 831
 832 static int i915_interrupt_info(struct seq_file *m, void *data)
 833 {
 834         struct drm_info_node *node = m->private;
 835         struct drm_device *dev = node->minor->dev;
 836         struct drm_i915_private *dev_priv = to_i915(dev);
 837         struct intel_engine_cs *engine;
 838         int ret, i, pipe;
 839
 840         ret = mutex_lock_interruptible(&dev->struct_mutex);
 841         if (ret)
 842                 return ret;
 843         intel_runtime_pm_get(dev_priv);
 844
 845         if (IS_CHERRYVIEW(dev)) {
 846                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 847                            I915_READ(GEN8_MASTER_IRQ));
 848
 849                 seq_printf(m, "Display IER:\t%08x\n",
 850                            I915_READ(VLV_IER));
 851                 seq_printf(m, "Display IIR:\t%08x\n",
 852                            I915_READ(VLV_IIR));
 853                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 854                            I915_READ(VLV_IIR_RW));
 855                 seq_printf(m, "Display IMR:\t%08x\n",
 856                            I915_READ(VLV_IMR));
 857                 for_each_pipe(dev_priv, pipe)
 858                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 859                                    pipe_name(pipe),
 860                                    I915_READ(PIPESTAT(pipe)));
 861
 862                 seq_printf(m, "Port hotplug:\t%08x\n",
 863                            I915_READ(PORT_HOTPLUG_EN));
 864                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 865                            I915_READ(VLV_DPFLIPSTAT));
 866                 seq_printf(m, "DPINVGTT:\t%08x\n",
 867                            I915_READ(DPINVGTT));
 868
 869                 for (i = 0; i < 4; i++) {
 870                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 871                                    i, I915_READ(GEN8_GT_IMR(i)));
 872                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 873                                    i, I915_READ(GEN8_GT_IIR(i)));
 874                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 875                                    i, I915_READ(GEN8_GT_IER(i)));
 876                 }
 877
 878                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 879                            I915_READ(GEN8_PCU_IMR));
 880                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 881                            I915_READ(GEN8_PCU_IIR));
 882                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 883                            I915_READ(GEN8_PCU_IER));
 884         } else if (INTEL_INFO(dev)->gen >= 8) {
 885                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 886                            I915_READ(GEN8_MASTER_IRQ));
 887
 888                 for (i = 0; i < 4; i++) {
 889                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 890                                    i, I915_READ(GEN8_GT_IMR(i)));
 891                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 892                                    i, I915_READ(GEN8_GT_IIR(i)));
 893                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 894                                    i, I915_READ(GEN8_GT_IER(i)));
 895                 }
 896
 897                 for_each_pipe(dev_priv, pipe) {
 898                         enum intel_display_power_domain power_domain;
 899
 900                         power_domain = POWER_DOMAIN_PIPE(pipe);
 901                         if (!intel_display_power_get_if_enabled(dev_priv,
 902                                                                 power_domain)) {
 903                                 seq_printf(m, "Pipe %c power disabled\n",
 904                                            pipe_name(pipe));
 905                                 continue;
 906                         }
 907                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 908                                    pipe_name(pipe),
 909                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 910                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 911                                    pipe_name(pipe),
 912                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 913                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 914                                    pipe_name(pipe),
 915                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 916
 917                         intel_display_power_put(dev_priv, power_domain);
 918                 }
 919
 920                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 921                            I915_READ(GEN8_DE_PORT_IMR));
 922                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 923                            I915_READ(GEN8_DE_PORT_IIR));
 924                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 925                            I915_READ(GEN8_DE_PORT_IER));
 926
 927                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 928                            I915_READ(GEN8_DE_MISC_IMR));
 929                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 930                            I915_READ(GEN8_DE_MISC_IIR));
 931                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 932                            I915_READ(GEN8_DE_MISC_IER));
 933
 934                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 935                            I915_READ(GEN8_PCU_IMR));
 936                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 937                            I915_READ(GEN8_PCU_IIR));
 938                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 939                            I915_READ(GEN8_PCU_IER));
 940         } else if (IS_VALLEYVIEW(dev)) {
 941                 seq_printf(m, "Display IER:\t%08x\n",
 942                            I915_READ(VLV_IER));
 943                 seq_printf(m, "Display IIR:\t%08x\n",
 944                            I915_READ(VLV_IIR));
 945                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 946                            I915_READ(VLV_IIR_RW));
 947                 seq_printf(m, "Display IMR:\t%08x\n",
 948                            I915_READ(VLV_IMR));
 949                 for_each_pipe(dev_priv, pipe)
 950                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 951                                    pipe_name(pipe),
 952                                    I915_READ(PIPESTAT(pipe)));
 953
 954                 seq_printf(m, "Master IER:\t%08x\n",
 955                            I915_READ(VLV_MASTER_IER));
 956
 957                 seq_printf(m, "Render IER:\t%08x\n",
 958                            I915_READ(GTIER));
 959                 seq_printf(m, "Render IIR:\t%08x\n",
 960                            I915_READ(GTIIR));
 961                 seq_printf(m, "Render IMR:\t%08x\n",
 962                            I915_READ(GTIMR));
 963
 964                 seq_printf(m, "PM IER:\t\t%08x\n",
 965                            I915_READ(GEN6_PMIER));
 966                 seq_printf(m, "PM IIR:\t\t%08x\n",
 967                            I915_READ(GEN6_PMIIR));
 968                 seq_printf(m, "PM IMR:\t\t%08x\n",
 969                            I915_READ(GEN6_PMIMR));
 970
 971                 seq_printf(m, "Port hotplug:\t%08x\n",
 972                            I915_READ(PORT_HOTPLUG_EN));
 973                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 974                            I915_READ(VLV_DPFLIPSTAT));
 975                 seq_printf(m, "DPINVGTT:\t%08x\n",
 976                            I915_READ(DPINVGTT));
 977
 978         } else if (!HAS_PCH_SPLIT(dev)) {
 979                 seq_printf(m, "Interrupt enable:    %08x\n",
 980                            I915_READ(IER));
 981                 seq_printf(m, "Interrupt identity:  %08x\n",
 982                            I915_READ(IIR));
 983                 seq_printf(m, "Interrupt mask:      %08x\n",
 984                            I915_READ(IMR));
 985                 for_each_pipe(dev_priv, pipe)
 986                         seq_printf(m, "Pipe %c stat:         %08x\n",
 987                                    pipe_name(pipe),
 988                                    I915_READ(PIPESTAT(pipe)));
 989         } else {
 990                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 991                            I915_READ(DEIER));
 992                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 993                            I915_READ(DEIIR));
 994                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 995                            I915_READ(DEIMR));
 996                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 997                            I915_READ(SDEIER));
 998                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 999                            I915_READ(SDEIIR));
1000                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
1001                            I915_READ(SDEIMR));
1002                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
1003                            I915_READ(GTIER));
1004                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
1005                            I915_READ(GTIIR));
1006                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
1007                            I915_READ(GTIMR));
1008         }
1009         for_each_engine(engine, dev_priv) {
1010                 if (INTEL_INFO(dev)->gen >= 6) {
1011                         seq_printf(m,
1012                                    "Graphics Interrupt mask (%s):       %08x\n",
1013                                    engine->name, I915_READ_IMR(engine));
1014                 }
1015                 i915_ring_seqno_info(m, engine);
1016         }
1017         intel_runtime_pm_put(dev_priv);
1018         mutex_unlock(&dev->struct_mutex);
1019
1020         return 0;
1021 }
1022
1023 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1024 {
1025         struct drm_info_node *node = m->private;
1026         struct drm_device *dev = node->minor->dev;
1027         struct drm_i915_private *dev_priv = to_i915(dev);
1028         int i, ret;
1029
1030         ret = mutex_lock_interruptible(&dev->struct_mutex);
1031         if (ret)
1032                 return ret;
1033
1034         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1035         for (i = 0; i < dev_priv->num_fence_regs; i++) {
1036                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1037
1038                 seq_printf(m, "Fence %d, pin count = %d, object = ",
1039                            i, dev_priv->fence_regs[i].pin_count);
1040                 if (obj == NULL)
1041                         seq_puts(m, "unused");
1042                 else
1043                         describe_obj(m, obj);
1044                 seq_putc(m, '\n');
1045         }
1046
1047         mutex_unlock(&dev->struct_mutex);
1048         return 0;
1049 }
1050
1051 static int i915_hws_info(struct seq_file *m, void *data)
1052 {
1053         struct drm_info_node *node = m->private;
1054         struct drm_device *dev = node->minor->dev;
1055         struct drm_i915_private *dev_priv = to_i915(dev);
1056         struct intel_engine_cs *engine;
1057         const u32 *hws;
1058         int i;
1059
1060         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1061         hws = engine->status_page.page_addr;
1062         if (hws == NULL)
1063                 return 0;
1064
1065         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1066                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1067                            i * 4,
1068                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1069         }
1070         return 0;
1071 }
1072
1073 static ssize_t
1074 i915_error_state_write(struct file *filp,
1075                        const char __user *ubuf,
1076                        size_t cnt,
1077                        loff_t *ppos)
1078 {
1079         struct i915_error_state_file_priv *error_priv = filp->private_data;
1080         struct drm_device *dev = error_priv->dev;
1081         int ret;
1082
1083         DRM_DEBUG_DRIVER("Resetting error state\n");
1084
1085         ret = mutex_lock_interruptible(&dev->struct_mutex);
1086         if (ret)
1087                 return ret;
1088
1089         i915_destroy_error_state(dev);
1090         mutex_unlock(&dev->struct_mutex);
1091
1092         return cnt;
1093 }
1094
1095 static int i915_error_state_open(struct inode *inode, struct file *file)
1096 {
1097         struct drm_device *dev = inode->i_private;
1098         struct i915_error_state_file_priv *error_priv;
1099
1100         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1101         if (!error_priv)
1102                 return -ENOMEM;
1103
1104         error_priv->dev = dev;
1105
1106         i915_error_state_get(dev, error_priv);
1107
1108         file->private_data = error_priv;
1109
1110         return 0;
1111 }
1112
1113 static int i915_error_state_release(struct inode *inode, struct file *file)
1114 {
1115         struct i915_error_state_file_priv *error_priv = file->private_data;
1116
1117         i915_error_state_put(error_priv);
1118         kfree(error_priv);
1119
1120         return 0;
1121 }
1122
1123 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1124                                      size_t count, loff_t *pos)
1125 {
1126         struct i915_error_state_file_priv *error_priv = file->private_data;
1127         struct drm_i915_error_state_buf error_str;
1128         loff_t tmp_pos = 0;
1129         ssize_t ret_count = 0;
1130         int ret;
1131
1132         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1133         if (ret)
1134                 return ret;
1135
1136         ret = i915_error_state_to_str(&error_str, error_priv);
1137         if (ret)
1138                 goto out;
1139
1140         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1141                                             error_str.buf,
1142                                             error_str.bytes);
1143
1144         if (ret_count < 0)
1145                 ret = ret_count;
1146         else
1147                 *pos = error_str.start + ret_count;
1148 out:
1149         i915_error_state_buf_release(&error_str);
1150         return ret ?: ret_count;
1151 }
1152
1153 static const struct file_operations i915_error_state_fops = {
1154         .owner = THIS_MODULE,
1155         .open = i915_error_state_open,
1156         .read = i915_error_state_read,
1157         .write = i915_error_state_write,
1158         .llseek = default_llseek,
1159         .release = i915_error_state_release,
1160 };
1161
1162 static int
1163 i915_next_seqno_get(void *data, u64 *val)
1164 {
1165         struct drm_device *dev = data;
1166         struct drm_i915_private *dev_priv = to_i915(dev);
1167         int ret;
1168
1169         ret = mutex_lock_interruptible(&dev->struct_mutex);
1170         if (ret)
1171                 return ret;
1172
1173         *val = dev_priv->next_seqno;
1174         mutex_unlock(&dev->struct_mutex);
1175
1176         return 0;
1177 }
1178
1179 static int
1180 i915_next_seqno_set(void *data, u64 val)
1181 {
1182         struct drm_device *dev = data;
1183         int ret;
1184
1185         ret = mutex_lock_interruptible(&dev->struct_mutex);
1186         if (ret)
1187                 return ret;
1188
1189         ret = i915_gem_set_seqno(dev, val);
1190         mutex_unlock(&dev->struct_mutex);
1191
1192         return ret;
1193 }
1194
1195 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1196                         i915_next_seqno_get, i915_next_seqno_set,
1197                         "0x%llx\n");
1198
1199 static int i915_frequency_info(struct seq_file *m, void *unused)
1200 {
1201         struct drm_info_node *node = m->private;
1202         struct drm_device *dev = node->minor->dev;
1203         struct drm_i915_private *dev_priv = to_i915(dev);
1204         int ret = 0;
1205
1206         intel_runtime_pm_get(dev_priv);
1207
1208         if (IS_GEN5(dev)) {
1209                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1210                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1211
1212                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1213                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1214                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1215                            MEMSTAT_VID_SHIFT);
1216                 seq_printf(m, "Current P-state: %d\n",
1217                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1218         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1219                 u32 freq_sts;
1220
1221                 mutex_lock(&dev_priv->rps.hw_lock);
1222                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1223                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1224                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1225
1226                 seq_printf(m, "actual GPU freq: %d MHz\n",
1227                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1228
1229                 seq_printf(m, "current GPU freq: %d MHz\n",
1230                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1231
1232                 seq_printf(m, "max GPU freq: %d MHz\n",
1233                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1234
1235                 seq_printf(m, "min GPU freq: %d MHz\n",
1236                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1237
1238                 seq_printf(m, "idle GPU freq: %d MHz\n",
1239                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1240
1241                 seq_printf(m,
1242                            "efficient (RPe) frequency: %d MHz\n",
1243                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1244                 mutex_unlock(&dev_priv->rps.hw_lock);
1245         } else if (INTEL_INFO(dev)->gen >= 6) {
1246                 u32 rp_state_limits;
1247                 u32 gt_perf_status;
1248                 u32 rp_state_cap;
1249                 u32 rpmodectl, rpinclimit, rpdeclimit;
1250                 u32 rpstat, cagf, reqf;
1251                 u32 rpupei, rpcurup, rpprevup;
1252                 u32 rpdownei, rpcurdown, rpprevdown;
1253                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1254                 int max_freq;
1255
1256                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1257                 if (IS_BROXTON(dev)) {
1258                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1259                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1260                 } else {
1261                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1262                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1263                 }
1264
1265                 /* RPSTAT1 is in the GT power well */
1266                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1267                 if (ret)
1268                         goto out;
1269
1270                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1271
1272                 reqf = I915_READ(GEN6_RPNSWREQ);
1273                 if (IS_GEN9(dev))
1274                         reqf >>= 23;
1275                 else {
1276                         reqf &= ~GEN6_TURBO_DISABLE;
1277                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1278                                 reqf >>= 24;
1279                         else
1280                                 reqf >>= 25;
1281                 }
1282                 reqf = intel_gpu_freq(dev_priv, reqf);
1283
1284                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1285                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1286                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1287
1288                 rpstat = I915_READ(GEN6_RPSTAT1);
1289                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1290                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1291                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1292                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1293                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1294                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1295                 if (IS_GEN9(dev))
1296                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1297                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1298                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1299                 else
1300                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1301                 cagf = intel_gpu_freq(dev_priv, cagf);
1302
1303                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1304                 mutex_unlock(&dev->struct_mutex);
1305
1306                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1307                         pm_ier = I915_READ(GEN6_PMIER);
1308                         pm_imr = I915_READ(GEN6_PMIMR);
1309                         pm_isr = I915_READ(GEN6_PMISR);
1310                         pm_iir = I915_READ(GEN6_PMIIR);
1311                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1312                 } else {
1313                         pm_ier = I915_READ(GEN8_GT_IER(2));
1314                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1315                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1316                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1317                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1318                 }
1319                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1320                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1321                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1322                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1323                 seq_printf(m, "Render p-state ratio: %d\n",
1324                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1325                 seq_printf(m, "Render p-state VID: %d\n",
1326                            gt_perf_status & 0xff);
1327                 seq_printf(m, "Render p-state limit: %d\n",
1328                            rp_state_limits & 0xff);
1329                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1330                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1331                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1332                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1333                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1334                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1335                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1336                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1337                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1338                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1339                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1340                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1341                 seq_printf(m, "Up threshold: %d%%\n",
1342                            dev_priv->rps.up_threshold);
1343
1344                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1345                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1346                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1347                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1348                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1349                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1350                 seq_printf(m, "Down threshold: %d%%\n",
1351                            dev_priv->rps.down_threshold);
1352
1353                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1354                             rp_state_cap >> 16) & 0xff;
1355                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1356                              GEN9_FREQ_SCALER : 1);
1357                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1358                            intel_gpu_freq(dev_priv, max_freq));
1359
1360                 max_freq = (rp_state_cap & 0xff00) >> 8;
1361                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1362                              GEN9_FREQ_SCALER : 1);
1363                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1364                            intel_gpu_freq(dev_priv, max_freq));
1365
1366                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1367                             rp_state_cap >> 0) & 0xff;
1368                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1369                              GEN9_FREQ_SCALER : 1);
1370                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1371                            intel_gpu_freq(dev_priv, max_freq));
1372                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1373                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1374
1375                 seq_printf(m, "Current freq: %d MHz\n",
1376                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1377                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1378                 seq_printf(m, "Idle freq: %d MHz\n",
1379                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1380                 seq_printf(m, "Min freq: %d MHz\n",
1381                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1382                 seq_printf(m, "Boost freq: %d MHz\n",
1383                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1384                 seq_printf(m, "Max freq: %d MHz\n",
1385                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1386                 seq_printf(m,
1387                            "efficient (RPe) frequency: %d MHz\n",
1388                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1389         } else {
1390                 seq_puts(m, "no P-state info available\n");
1391         }
1392
1393         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1394         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1395         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1396
1397 out:
1398         intel_runtime_pm_put(dev_priv);
1399         return ret;
1400 }
1401
1402 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1403 {
1404         struct drm_info_node *node = m->private;
1405         struct drm_device *dev = node->minor->dev;
1406         struct drm_i915_private *dev_priv = to_i915(dev);
1407         struct intel_engine_cs *engine;
1408         u64 acthd[I915_NUM_ENGINES];
1409         u32 seqno[I915_NUM_ENGINES];
1410         u32 instdone[I915_NUM_INSTDONE_REG];
1411         enum intel_engine_id id;
1412         int j;
1413
1414         if (!i915.enable_hangcheck) {
1415                 seq_printf(m, "Hangcheck disabled\n");
1416                 return 0;
1417         }
1418
1419         intel_runtime_pm_get(dev_priv);
1420
1421         for_each_engine_id(engine, dev_priv, id) {
1422                 acthd[id] = intel_ring_get_active_head(engine);
1423                 seqno[id] = intel_engine_get_seqno(engine);
1424         }
1425
1426         i915_get_extra_instdone(dev_priv, instdone);
1427
1428         intel_runtime_pm_put(dev_priv);
1429
1430         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1431                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1432                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1433                                             jiffies));
1434         } else
1435                 seq_printf(m, "Hangcheck inactive\n");
1436
1437         for_each_engine_id(engine, dev_priv, id) {
1438                 seq_printf(m, "%s:\n", engine->name);
1439                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1440                            engine->hangcheck.seqno,
1441                            seqno[id],
1442                            engine->last_submitted_seqno);
1443                 seq_printf(m, "\twaiters? %d\n",
1444                            intel_engine_has_waiter(engine));
1445                 seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
1446                            engine->hangcheck.user_interrupts,
1447                            READ_ONCE(engine->breadcrumbs.irq_wakeups));
1448                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1449                            (long long)engine->hangcheck.acthd,
1450                            (long long)acthd[id]);
1451                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1452                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1453
1454                 if (engine->id == RCS) {
1455                         seq_puts(m, "\tinstdone read =");
1456
1457                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1458                                 seq_printf(m, " 0x%08x", instdone[j]);
1459
1460                         seq_puts(m, "\n\tinstdone accu =");
1461
1462                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1463                                 seq_printf(m, " 0x%08x",
1464                                            engine->hangcheck.instdone[j]);
1465
1466                         seq_puts(m, "\n");
1467                 }
1468         }
1469
1470         return 0;
1471 }
1472
1473 static int ironlake_drpc_info(struct seq_file *m)
1474 {
1475         struct drm_info_node *node = m->private;
1476         struct drm_device *dev = node->minor->dev;
1477         struct drm_i915_private *dev_priv = to_i915(dev);
1478         u32 rgvmodectl, rstdbyctl;
1479         u16 crstandvid;
1480         int ret;
1481
1482         ret = mutex_lock_interruptible(&dev->struct_mutex);
1483         if (ret)
1484                 return ret;
1485         intel_runtime_pm_get(dev_priv);
1486
1487         rgvmodectl = I915_READ(MEMMODECTL);
1488         rstdbyctl = I915_READ(RSTDBYCTL);
1489         crstandvid = I915_READ16(CRSTANDVID);
1490
1491         intel_runtime_pm_put(dev_priv);
1492         mutex_unlock(&dev->struct_mutex);
1493
1494         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1495         seq_printf(m, "Boost freq: %d\n",
1496                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1497                    MEMMODE_BOOST_FREQ_SHIFT);
1498         seq_printf(m, "HW control enabled: %s\n",
1499                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1500         seq_printf(m, "SW control enabled: %s\n",
1501                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1502         seq_printf(m, "Gated voltage change: %s\n",
1503                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1504         seq_printf(m, "Starting frequency: P%d\n",
1505                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1506         seq_printf(m, "Max P-state: P%d\n",
1507                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1508         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1509         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1510         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1511         seq_printf(m, "Render standby enabled: %s\n",
1512                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1513         seq_puts(m, "Current RS state: ");
1514         switch (rstdbyctl & RSX_STATUS_MASK) {
1515         case RSX_STATUS_ON:
1516                 seq_puts(m, "on\n");
1517                 break;
1518         case RSX_STATUS_RC1:
1519                 seq_puts(m, "RC1\n");
1520                 break;
1521         case RSX_STATUS_RC1E:
1522                 seq_puts(m, "RC1E\n");
1523                 break;
1524         case RSX_STATUS_RS1:
1525                 seq_puts(m, "RS1\n");
1526                 break;
1527         case RSX_STATUS_RS2:
1528                 seq_puts(m, "RS2 (RC6)\n");
1529                 break;
1530         case RSX_STATUS_RS3:
1531                 seq_puts(m, "RC3 (RC6+)\n");
1532                 break;
1533         default:
1534                 seq_puts(m, "unknown\n");
1535                 break;
1536         }
1537
1538         return 0;
1539 }
1540
1541 static int i915_forcewake_domains(struct seq_file *m, void *data)
1542 {
1543         struct drm_info_node *node = m->private;
1544         struct drm_device *dev = node->minor->dev;
1545         struct drm_i915_private *dev_priv = to_i915(dev);
1546         struct intel_uncore_forcewake_domain *fw_domain;
1547
1548         spin_lock_irq(&dev_priv->uncore.lock);
1549         for_each_fw_domain(fw_domain, dev_priv) {
1550                 seq_printf(m, "%s.wake_count = %u\n",
1551                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1552                            fw_domain->wake_count);
1553         }
1554         spin_unlock_irq(&dev_priv->uncore.lock);
1555
1556         return 0;
1557 }
1558
1559 static int vlv_drpc_info(struct seq_file *m)
1560 {
1561         struct drm_info_node *node = m->private;
1562         struct drm_device *dev = node->minor->dev;
1563         struct drm_i915_private *dev_priv = to_i915(dev);
1564         u32 rpmodectl1, rcctl1, pw_status;
1565
1566         intel_runtime_pm_get(dev_priv);
1567
1568         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1569         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1570         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1571
1572         intel_runtime_pm_put(dev_priv);
1573
1574         seq_printf(m, "Video Turbo Mode: %s\n",
1575                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1576         seq_printf(m, "Turbo enabled: %s\n",
1577                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1578         seq_printf(m, "HW control enabled: %s\n",
1579                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1580         seq_printf(m, "SW control enabled: %s\n",
1581                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1582                           GEN6_RP_MEDIA_SW_MODE));
1583         seq_printf(m, "RC6 Enabled: %s\n",
1584                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1585                                         GEN6_RC_CTL_EI_MODE(1))));
1586         seq_printf(m, "Render Power Well: %s\n",
1587                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1588         seq_printf(m, "Media Power Well: %s\n",
1589                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1590
1591         seq_printf(m, "Render RC6 residency since boot: %u\n",
1592                    I915_READ(VLV_GT_RENDER_RC6));
1593         seq_printf(m, "Media RC6 residency since boot: %u\n",
1594                    I915_READ(VLV_GT_MEDIA_RC6));
1595
1596         return i915_forcewake_domains(m, NULL);
1597 }
1598
1599 static int gen6_drpc_info(struct seq_file *m)
1600 {
1601         struct drm_info_node *node = m->private;
1602         struct drm_device *dev = node->minor->dev;
1603         struct drm_i915_private *dev_priv = to_i915(dev);
1604         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1605         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1606         unsigned forcewake_count;
1607         int count = 0, ret;
1608
1609         ret = mutex_lock_interruptible(&dev->struct_mutex);
1610         if (ret)
1611                 return ret;
1612         intel_runtime_pm_get(dev_priv);
1613
1614         spin_lock_irq(&dev_priv->uncore.lock);
1615         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1616         spin_unlock_irq(&dev_priv->uncore.lock);
1617
1618         if (forcewake_count) {
1619                 seq_puts(m, "RC information inaccurate because somebody "
1620                             "holds a forcewake reference \n");
1621         } else {
1622                 /* NB: we cannot use forcewake, else we read the wrong values */
1623                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1624                         udelay(10);
1625                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1626         }
1627
1628         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1629         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1630
1631         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1632         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1633         if (INTEL_INFO(dev)->gen >= 9) {
1634                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1635                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1636         }
1637         mutex_unlock(&dev->struct_mutex);
1638         mutex_lock(&dev_priv->rps.hw_lock);
1639         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1640         mutex_unlock(&dev_priv->rps.hw_lock);
1641
1642         intel_runtime_pm_put(dev_priv);
1643
1644         seq_printf(m, "Video Turbo Mode: %s\n",
1645                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1646         seq_printf(m, "HW control enabled: %s\n",
1647                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1648         seq_printf(m, "SW control enabled: %s\n",
1649                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1650                           GEN6_RP_MEDIA_SW_MODE));
1651         seq_printf(m, "RC1e Enabled: %s\n",
1652                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1653         seq_printf(m, "RC6 Enabled: %s\n",
1654                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1655         if (INTEL_INFO(dev)->gen >= 9) {
1656                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1657                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1658                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1659                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1660         }
1661         seq_printf(m, "Deep RC6 Enabled: %s\n",
1662                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1663         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1664                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1665         seq_puts(m, "Current RC state: ");
1666         switch (gt_core_status & GEN6_RCn_MASK) {
1667         case GEN6_RC0:
1668                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1669                         seq_puts(m, "Core Power Down\n");
1670                 else
1671                         seq_puts(m, "on\n");
1672                 break;
1673         case GEN6_RC3:
1674                 seq_puts(m, "RC3\n");
1675                 break;
1676         case GEN6_RC6:
1677                 seq_puts(m, "RC6\n");
1678                 break;
1679         case GEN6_RC7:
1680                 seq_puts(m, "RC7\n");
1681                 break;
1682         default:
1683                 seq_puts(m, "Unknown\n");
1684                 break;
1685         }
1686
1687         seq_printf(m, "Core Power Down: %s\n",
1688                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1689         if (INTEL_INFO(dev)->gen >= 9) {
1690                 seq_printf(m, "Render Power Well: %s\n",
1691                         (gen9_powergate_status &
1692                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1693                 seq_printf(m, "Media Power Well: %s\n",
1694                         (gen9_powergate_status &
1695                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1696         }
1697
1698         /* Not exactly sure what this is */
1699         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1700                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1701         seq_printf(m, "RC6 residency since boot: %u\n",
1702                    I915_READ(GEN6_GT_GFX_RC6));
1703         seq_printf(m, "RC6+ residency since boot: %u\n",
1704                    I915_READ(GEN6_GT_GFX_RC6p));
1705         seq_printf(m, "RC6++ residency since boot: %u\n",
1706                    I915_READ(GEN6_GT_GFX_RC6pp));
1707
1708         seq_printf(m, "RC6   voltage: %dmV\n",
1709                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1710         seq_printf(m, "RC6+  voltage: %dmV\n",
1711                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1712         seq_printf(m, "RC6++ voltage: %dmV\n",
1713                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1714         return i915_forcewake_domains(m, NULL);
1715 }
1716
1717 static int i915_drpc_info(struct seq_file *m, void *unused)
1718 {
1719         struct drm_info_node *node = m->private;
1720         struct drm_device *dev = node->minor->dev;
1721
1722         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1723                 return vlv_drpc_info(m);
1724         else if (INTEL_INFO(dev)->gen >= 6)
1725                 return gen6_drpc_info(m);
1726         else
1727                 return ironlake_drpc_info(m);
1728 }
1729
1730 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1731 {
1732         struct drm_info_node *node = m->private;
1733         struct drm_device *dev = node->minor->dev;
1734         struct drm_i915_private *dev_priv = to_i915(dev);
1735
1736         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1737                    dev_priv->fb_tracking.busy_bits);
1738
1739         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1740                    dev_priv->fb_tracking.flip_bits);
1741
1742         return 0;
1743 }
1744
1745 static int i915_fbc_status(struct seq_file *m, void *unused)
1746 {
1747         struct drm_info_node *node = m->private;
1748         struct drm_device *dev = node->minor->dev;
1749         struct drm_i915_private *dev_priv = to_i915(dev);
1750
1751         if (!HAS_FBC(dev)) {
1752                 seq_puts(m, "FBC unsupported on this chipset\n");
1753                 return 0;
1754         }
1755
1756         intel_runtime_pm_get(dev_priv);
1757         mutex_lock(&dev_priv->fbc.lock);
1758
1759         if (intel_fbc_is_active(dev_priv))
1760                 seq_puts(m, "FBC enabled\n");
1761         else
1762                 seq_printf(m, "FBC disabled: %s\n",
1763                            dev_priv->fbc.no_fbc_reason);
1764
1765         if (INTEL_INFO(dev_priv)->gen >= 7)
1766                 seq_printf(m, "Compressing: %s\n",
1767                            yesno(I915_READ(FBC_STATUS2) &
1768                                  FBC_COMPRESSION_MASK));
1769
1770         mutex_unlock(&dev_priv->fbc.lock);
1771         intel_runtime_pm_put(dev_priv);
1772
1773         return 0;
1774 }
1775
1776 static int i915_fbc_fc_get(void *data, u64 *val)
1777 {
1778         struct drm_device *dev = data;
1779         struct drm_i915_private *dev_priv = to_i915(dev);
1780
1781         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1782                 return -ENODEV;
1783
1784         *val = dev_priv->fbc.false_color;
1785
1786         return 0;
1787 }
1788
1789 static int i915_fbc_fc_set(void *data, u64 val)
1790 {
1791         struct drm_device *dev = data;
1792         struct drm_i915_private *dev_priv = to_i915(dev);
1793         u32 reg;
1794
1795         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1796                 return -ENODEV;
1797
1798         mutex_lock(&dev_priv->fbc.lock);
1799
1800         reg = I915_READ(ILK_DPFC_CONTROL);
1801         dev_priv->fbc.false_color = val;
1802
1803         I915_WRITE(ILK_DPFC_CONTROL, val ?
1804                    (reg | FBC_CTL_FALSE_COLOR) :
1805                    (reg & ~FBC_CTL_FALSE_COLOR));
1806
1807         mutex_unlock(&dev_priv->fbc.lock);
1808         return 0;
1809 }
1810
1811 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1812                         i915_fbc_fc_get, i915_fbc_fc_set,
1813                         "%llu\n");
1814
1815 static int i915_ips_status(struct seq_file *m, void *unused)
1816 {
1817         struct drm_info_node *node = m->private;
1818         struct drm_device *dev = node->minor->dev;
1819         struct drm_i915_private *dev_priv = to_i915(dev);
1820
1821         if (!HAS_IPS(dev)) {
1822                 seq_puts(m, "not supported\n");
1823                 return 0;
1824         }
1825
1826         intel_runtime_pm_get(dev_priv);
1827
1828         seq_printf(m, "Enabled by kernel parameter: %s\n",
1829                    yesno(i915.enable_ips));
1830
1831         if (INTEL_INFO(dev)->gen >= 8) {
1832                 seq_puts(m, "Currently: unknown\n");
1833         } else {
1834                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1835                         seq_puts(m, "Currently: enabled\n");
1836                 else
1837                         seq_puts(m, "Currently: disabled\n");
1838         }
1839
1840         intel_runtime_pm_put(dev_priv);
1841
1842         return 0;
1843 }
1844
1845 static int i915_sr_status(struct seq_file *m, void *unused)
1846 {
1847         struct drm_info_node *node = m->private;
1848         struct drm_device *dev = node->minor->dev;
1849         struct drm_i915_private *dev_priv = to_i915(dev);
1850         bool sr_enabled = false;
1851
1852         intel_runtime_pm_get(dev_priv);
1853
1854         if (HAS_PCH_SPLIT(dev))
1855                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1856         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1857                  IS_I945G(dev) || IS_I945GM(dev))
1858                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1859         else if (IS_I915GM(dev))
1860                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1861         else if (IS_PINEVIEW(dev))
1862                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1863         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1864                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1865
1866         intel_runtime_pm_put(dev_priv);
1867
1868         seq_printf(m, "self-refresh: %s\n",
1869                    sr_enabled ? "enabled" : "disabled");
1870
1871         return 0;
1872 }
1873
1874 static int i915_emon_status(struct seq_file *m, void *unused)
1875 {
1876         struct drm_info_node *node = m->private;
1877         struct drm_device *dev = node->minor->dev;
1878         struct drm_i915_private *dev_priv = to_i915(dev);
1879         unsigned long temp, chipset, gfx;
1880         int ret;
1881
1882         if (!IS_GEN5(dev))
1883                 return -ENODEV;
1884
1885         ret = mutex_lock_interruptible(&dev->struct_mutex);
1886         if (ret)
1887                 return ret;
1888
1889         temp = i915_mch_val(dev_priv);
1890         chipset = i915_chipset_val(dev_priv);
1891         gfx = i915_gfx_val(dev_priv);
1892         mutex_unlock(&dev->struct_mutex);
1893
1894         seq_printf(m, "GMCH temp: %ld\n", temp);
1895         seq_printf(m, "Chipset power: %ld\n", chipset);
1896         seq_printf(m, "GFX power: %ld\n", gfx);
1897         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1898
1899         return 0;
1900 }
1901
1902 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1903 {
1904         struct drm_info_node *node = m->private;
1905         struct drm_device *dev = node->minor->dev;
1906         struct drm_i915_private *dev_priv = to_i915(dev);
1907         int ret = 0;
1908         int gpu_freq, ia_freq;
1909         unsigned int max_gpu_freq, min_gpu_freq;
1910
1911         if (!HAS_CORE_RING_FREQ(dev)) {
1912                 seq_puts(m, "unsupported on this chipset\n");
1913                 return 0;
1914         }
1915
1916         intel_runtime_pm_get(dev_priv);
1917
1918         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1919         if (ret)
1920                 goto out;
1921
1922         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1923                 /* Convert GT frequency to 50 HZ units */
1924                 min_gpu_freq =
1925                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1926                 max_gpu_freq =
1927                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1928         } else {
1929                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1930                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1931         }
1932
1933         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1934
1935         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1936                 ia_freq = gpu_freq;
1937                 sandybridge_pcode_read(dev_priv,
1938                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1939                                        &ia_freq);
1940                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1941                            intel_gpu_freq(dev_priv, (gpu_freq *
1942                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1943                                  GEN9_FREQ_SCALER : 1))),
1944                            ((ia_freq >> 0) & 0xff) * 100,
1945                            ((ia_freq >> 8) & 0xff) * 100);
1946         }
1947
1948         mutex_unlock(&dev_priv->rps.hw_lock);
1949
1950 out:
1951         intel_runtime_pm_put(dev_priv);
1952         return ret;
1953 }
1954
1955 static int i915_opregion(struct seq_file *m, void *unused)
1956 {
1957         struct drm_info_node *node = m->private;
1958         struct drm_device *dev = node->minor->dev;
1959         struct drm_i915_private *dev_priv = to_i915(dev);
1960         struct intel_opregion *opregion = &dev_priv->opregion;
1961         int ret;
1962
1963         ret = mutex_lock_interruptible(&dev->struct_mutex);
1964         if (ret)
1965                 goto out;
1966
1967         if (opregion->header)
1968                 seq_write(m, opregion->header, OPREGION_SIZE);
1969
1970         mutex_unlock(&dev->struct_mutex);
1971
1972 out:
1973         return 0;
1974 }
1975
1976 static int i915_vbt(struct seq_file *m, void *unused)
1977 {
1978         struct drm_info_node *node = m->private;
1979         struct drm_device *dev = node->minor->dev;
1980         struct drm_i915_private *dev_priv = to_i915(dev);
1981         struct intel_opregion *opregion = &dev_priv->opregion;
1982
1983         if (opregion->vbt)
1984                 seq_write(m, opregion->vbt, opregion->vbt_size);
1985
1986         return 0;
1987 }
1988
1989 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1990 {
1991         struct drm_info_node *node = m->private;
1992         struct drm_device *dev = node->minor->dev;
1993         struct intel_framebuffer *fbdev_fb = NULL;
1994         struct drm_framebuffer *drm_fb;
1995         int ret;
1996
1997         ret = mutex_lock_interruptible(&dev->struct_mutex);
1998         if (ret)
1999                 return ret;
2000
2001 #ifdef CONFIG_DRM_FBDEV_EMULATION
2002         if (to_i915(dev)->fbdev) {
2003                 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
2004
2005                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2006                            fbdev_fb->base.width,
2007                            fbdev_fb->base.height,
2008                            fbdev_fb->base.depth,
2009                            fbdev_fb->base.bits_per_pixel,
2010                            fbdev_fb->base.modifier[0],
2011                            drm_framebuffer_read_refcount(&fbdev_fb->base));
2012                 describe_obj(m, fbdev_fb->obj);
2013                 seq_putc(m, '\n');
2014         }
2015 #endif
2016
2017         mutex_lock(&dev->mode_config.fb_lock);
2018         drm_for_each_fb(drm_fb, dev) {
2019                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2020                 if (fb == fbdev_fb)
2021                         continue;
2022
2023                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2024                            fb->base.width,
2025                            fb->base.height,
2026                            fb->base.depth,
2027                            fb->base.bits_per_pixel,
2028                            fb->base.modifier[0],
2029                            drm_framebuffer_read_refcount(&fb->base));
2030                 describe_obj(m, fb->obj);
2031                 seq_putc(m, '\n');
2032         }
2033         mutex_unlock(&dev->mode_config.fb_lock);
2034         mutex_unlock(&dev->struct_mutex);
2035
2036         return 0;
2037 }
2038
2039 static void describe_ctx_ringbuf(struct seq_file *m,
2040                                  struct intel_ringbuffer *ringbuf)
2041 {
2042         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2043                    ringbuf->space, ringbuf->head, ringbuf->tail,
2044                    ringbuf->last_retired_head);
2045 }
2046
2047 static int i915_context_status(struct seq_file *m, void *unused)
2048 {
2049         struct drm_info_node *node = m->private;
2050         struct drm_device *dev = node->minor->dev;
2051         struct drm_i915_private *dev_priv = to_i915(dev);
2052         struct intel_engine_cs *engine;
2053         struct i915_gem_context *ctx;
2054         int ret;
2055
2056         ret = mutex_lock_interruptible(&dev->struct_mutex);
2057         if (ret)
2058                 return ret;
2059
2060         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2061                 seq_printf(m, "HW context %u ", ctx->hw_id);
2062                 if (IS_ERR(ctx->file_priv)) {
2063                         seq_puts(m, "(deleted) ");
2064                 } else if (ctx->file_priv) {
2065                         struct pid *pid = ctx->file_priv->file->pid;
2066                         struct task_struct *task;
2067
2068                         task = get_pid_task(pid, PIDTYPE_PID);
2069                         if (task) {
2070                                 seq_printf(m, "(%s [%d]) ",
2071                                            task->comm, task->pid);
2072                                 put_task_struct(task);
2073                         }
2074                 } else {
2075                         seq_puts(m, "(kernel) ");
2076                 }
2077
2078                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2079                 seq_putc(m, '\n');
2080
2081                 for_each_engine(engine, dev_priv) {
2082                         struct intel_context *ce = &ctx->engine[engine->id];
2083
2084                         seq_printf(m, "%s: ", engine->name);
2085                         seq_putc(m, ce->initialised ? 'I' : 'i');
2086                         if (ce->state)
2087                                 describe_obj(m, ce->state);
2088                         if (ce->ringbuf)
2089                                 describe_ctx_ringbuf(m, ce->ringbuf);
2090                         seq_putc(m, '\n');
2091                 }
2092
2093                 seq_putc(m, '\n');
2094         }
2095
2096         mutex_unlock(&dev->struct_mutex);
2097
2098         return 0;
2099 }
2100
2101 static void i915_dump_lrc_obj(struct seq_file *m,
2102                               struct i915_gem_context *ctx,
2103                               struct intel_engine_cs *engine)
2104 {
2105         struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2106         struct page *page;
2107         uint32_t *reg_state;
2108         int j;
2109         unsigned long ggtt_offset = 0;
2110
2111         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2112
2113         if (ctx_obj == NULL) {
2114                 seq_puts(m, "\tNot allocated\n");
2115                 return;
2116         }
2117
2118         if (!i915_gem_obj_ggtt_bound(ctx_obj))
2119                 seq_puts(m, "\tNot bound in GGTT\n");
2120         else
2121                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2122
2123         if (i915_gem_object_get_pages(ctx_obj)) {
2124                 seq_puts(m, "\tFailed to get pages for context object\n");
2125                 return;
2126         }
2127
2128         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2129         if (!WARN_ON(page == NULL)) {
2130                 reg_state = kmap_atomic(page);
2131
2132                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2133                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2134                                    ggtt_offset + 4096 + (j * 4),
2135                                    reg_state[j], reg_state[j + 1],
2136                                    reg_state[j + 2], reg_state[j + 3]);
2137                 }
2138                 kunmap_atomic(reg_state);
2139         }
2140
2141         seq_putc(m, '\n');
2142 }
2143
2144 static int i915_dump_lrc(struct seq_file *m, void *unused)
2145 {
2146         struct drm_info_node *node = (struct drm_info_node *) m->private;
2147         struct drm_device *dev = node->minor->dev;
2148         struct drm_i915_private *dev_priv = to_i915(dev);
2149         struct intel_engine_cs *engine;
2150         struct i915_gem_context *ctx;
2151         int ret;
2152
2153         if (!i915.enable_execlists) {
2154                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2155                 return 0;
2156         }
2157
2158         ret = mutex_lock_interruptible(&dev->struct_mutex);
2159         if (ret)
2160                 return ret;
2161
2162         list_for_each_entry(ctx, &dev_priv->context_list, link)
2163                 for_each_engine(engine, dev_priv)
2164                         i915_dump_lrc_obj(m, ctx, engine);
2165
2166         mutex_unlock(&dev->struct_mutex);
2167
2168         return 0;
2169 }
2170
2171 static int i915_execlists(struct seq_file *m, void *data)
2172 {
2173         struct drm_info_node *node = (struct drm_info_node *)m->private;
2174         struct drm_device *dev = node->minor->dev;
2175         struct drm_i915_private *dev_priv = to_i915(dev);
2176         struct intel_engine_cs *engine;
2177         u32 status_pointer;
2178         u8 read_pointer;
2179         u8 write_pointer;
2180         u32 status;
2181         u32 ctx_id;
2182         struct list_head *cursor;
2183         int i, ret;
2184
2185         if (!i915.enable_execlists) {
2186                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2187                 return 0;
2188         }
2189
2190         ret = mutex_lock_interruptible(&dev->struct_mutex);
2191         if (ret)
2192                 return ret;
2193
2194         intel_runtime_pm_get(dev_priv);
2195
2196         for_each_engine(engine, dev_priv) {
2197                 struct drm_i915_gem_request *head_req = NULL;
2198                 int count = 0;
2199
2200                 seq_printf(m, "%s\n", engine->name);
2201
2202                 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2203                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2204                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2205                            status, ctx_id);
2206
2207                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2208                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2209
2210                 read_pointer = engine->next_context_status_buffer;
2211                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2212                 if (read_pointer > write_pointer)
2213                         write_pointer += GEN8_CSB_ENTRIES;
2214                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2215                            read_pointer, write_pointer);
2216
2217                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2218                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2219                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2220
2221                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2222                                    i, status, ctx_id);
2223                 }
2224
2225                 spin_lock_bh(&engine->execlist_lock);
2226                 list_for_each(cursor, &engine->execlist_queue)
2227                         count++;
2228                 head_req = list_first_entry_or_null(&engine->execlist_queue,
2229                                                     struct drm_i915_gem_request,
2230                                                     execlist_link);
2231                 spin_unlock_bh(&engine->execlist_lock);
2232
2233                 seq_printf(m, "\t%d requests in queue\n", count);
2234                 if (head_req) {
2235                         seq_printf(m, "\tHead request context: %u\n",
2236                                    head_req->ctx->hw_id);
2237                         seq_printf(m, "\tHead request tail: %u\n",
2238                                    head_req->tail);
2239                 }
2240
2241                 seq_putc(m, '\n');
2242         }
2243
2244         intel_runtime_pm_put(dev_priv);
2245         mutex_unlock(&dev->struct_mutex);
2246
2247         return 0;
2248 }
2249
2250 static const char *swizzle_string(unsigned swizzle)
2251 {
2252         switch (swizzle) {
2253         case I915_BIT_6_SWIZZLE_NONE:
2254                 return "none";
2255         case I915_BIT_6_SWIZZLE_9:
2256                 return "bit9";
2257         case I915_BIT_6_SWIZZLE_9_10:
2258                 return "bit9/bit10";
2259         case I915_BIT_6_SWIZZLE_9_11:
2260                 return "bit9/bit11";
2261         case I915_BIT_6_SWIZZLE_9_10_11:
2262                 return "bit9/bit10/bit11";
2263         case I915_BIT_6_SWIZZLE_9_17:
2264                 return "bit9/bit17";
2265         case I915_BIT_6_SWIZZLE_9_10_17:
2266                 return "bit9/bit10/bit17";
2267         case I915_BIT_6_SWIZZLE_UNKNOWN:
2268                 return "unknown";
2269         }
2270
2271         return "bug";
2272 }
2273
2274 static int i915_swizzle_info(struct seq_file *m, void *data)
2275 {
2276         struct drm_info_node *node = m->private;
2277         struct drm_device *dev = node->minor->dev;
2278         struct drm_i915_private *dev_priv = to_i915(dev);
2279         int ret;
2280
2281         ret = mutex_lock_interruptible(&dev->struct_mutex);
2282         if (ret)
2283                 return ret;
2284         intel_runtime_pm_get(dev_priv);
2285
2286         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2287                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2288         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2289                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2290
2291         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2292                 seq_printf(m, "DDC = 0x%08x\n",
2293                            I915_READ(DCC));
2294                 seq_printf(m, "DDC2 = 0x%08x\n",
2295                            I915_READ(DCC2));
2296                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2297                            I915_READ16(C0DRB3));
2298                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2299                            I915_READ16(C1DRB3));
2300         } else if (INTEL_INFO(dev)->gen >= 6) {
2301                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2302                            I915_READ(MAD_DIMM_C0));
2303                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2304                            I915_READ(MAD_DIMM_C1));
2305                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2306                            I915_READ(MAD_DIMM_C2));
2307                 seq_printf(m, "TILECTL = 0x%08x\n",
2308                            I915_READ(TILECTL));
2309                 if (INTEL_INFO(dev)->gen >= 8)
2310                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2311                                    I915_READ(GAMTARBMODE));
2312                 else
2313                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2314                                    I915_READ(ARB_MODE));
2315                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2316                            I915_READ(DISP_ARB_CTL));
2317         }
2318
2319         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2320                 seq_puts(m, "L-shaped memory detected\n");
2321
2322         intel_runtime_pm_put(dev_priv);
2323         mutex_unlock(&dev->struct_mutex);
2324
2325         return 0;
2326 }
2327
2328 static int per_file_ctx(int id, void *ptr, void *data)
2329 {
2330         struct i915_gem_context *ctx = ptr;
2331         struct seq_file *m = data;
2332         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2333
2334         if (!ppgtt) {
2335                 seq_printf(m, "  no ppgtt for context %d\n",
2336                            ctx->user_handle);
2337                 return 0;
2338         }
2339
2340         if (i915_gem_context_is_default(ctx))
2341                 seq_puts(m, "  default context:\n");
2342         else
2343                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2344         ppgtt->debug_dump(ppgtt, m);
2345
2346         return 0;
2347 }
2348
2349 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2350 {
2351         struct drm_i915_private *dev_priv = to_i915(dev);
2352         struct intel_engine_cs *engine;
2353         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2354         int i;
2355
2356         if (!ppgtt)
2357                 return;
2358
2359         for_each_engine(engine, dev_priv) {
2360                 seq_printf(m, "%s\n", engine->name);
2361                 for (i = 0; i < 4; i++) {
2362                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2363                         pdp <<= 32;
2364                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2365                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2366                 }
2367         }
2368 }
2369
2370 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2371 {
2372         struct drm_i915_private *dev_priv = to_i915(dev);
2373         struct intel_engine_cs *engine;
2374
2375         if (IS_GEN6(dev_priv))
2376                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2377
2378         for_each_engine(engine, dev_priv) {
2379                 seq_printf(m, "%s\n", engine->name);
2380                 if (IS_GEN7(dev_priv))
2381                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2382                                    I915_READ(RING_MODE_GEN7(engine)));
2383                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2384                            I915_READ(RING_PP_DIR_BASE(engine)));
2385                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2386                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2387                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2388                            I915_READ(RING_PP_DIR_DCLV(engine)));
2389         }
2390         if (dev_priv->mm.aliasing_ppgtt) {
2391                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2392
2393                 seq_puts(m, "aliasing PPGTT:\n");
2394                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2395
2396                 ppgtt->debug_dump(ppgtt, m);
2397         }
2398
2399         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2400 }
2401
2402 static int i915_ppgtt_info(struct seq_file *m, void *data)
2403 {
2404         struct drm_info_node *node = m->private;
2405         struct drm_device *dev = node->minor->dev;
2406         struct drm_i915_private *dev_priv = to_i915(dev);
2407         struct drm_file *file;
2408
2409         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2410         if (ret)
2411                 return ret;
2412         intel_runtime_pm_get(dev_priv);
2413
2414         if (INTEL_INFO(dev)->gen >= 8)
2415                 gen8_ppgtt_info(m, dev);
2416         else if (INTEL_INFO(dev)->gen >= 6)
2417                 gen6_ppgtt_info(m, dev);
2418
2419         mutex_lock(&dev->filelist_mutex);
2420         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2421                 struct drm_i915_file_private *file_priv = file->driver_priv;
2422                 struct task_struct *task;
2423
2424                 task = get_pid_task(file->pid, PIDTYPE_PID);
2425                 if (!task) {
2426                         ret = -ESRCH;
2427                         goto out_unlock;
2428                 }
2429                 seq_printf(m, "\nproc: %s\n", task->comm);
2430                 put_task_struct(task);
2431                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2432                              (void *)(unsigned long)m);
2433         }
2434 out_unlock:
2435         mutex_unlock(&dev->filelist_mutex);
2436
2437         intel_runtime_pm_put(dev_priv);
2438         mutex_unlock(&dev->struct_mutex);
2439
2440         return ret;
2441 }
2442
2443 static int count_irq_waiters(struct drm_i915_private *i915)
2444 {
2445         struct intel_engine_cs *engine;
2446         int count = 0;
2447
2448         for_each_engine(engine, i915)
2449                 count += intel_engine_has_waiter(engine);
2450
2451         return count;
2452 }
2453
2454 static int i915_rps_boost_info(struct seq_file *m, void *data)
2455 {
2456         struct drm_info_node *node = m->private;
2457         struct drm_device *dev = node->minor->dev;
2458         struct drm_i915_private *dev_priv = to_i915(dev);
2459         struct drm_file *file;
2460
2461         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2462         seq_printf(m, "GPU busy? %s [%x]\n",
2463                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2464         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2465         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2466                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2467                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2468                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2469                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2470                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2471
2472         mutex_lock(&dev->filelist_mutex);
2473         spin_lock(&dev_priv->rps.client_lock);
2474         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2475                 struct drm_i915_file_private *file_priv = file->driver_priv;
2476                 struct task_struct *task;
2477
2478                 rcu_read_lock();
2479                 task = pid_task(file->pid, PIDTYPE_PID);
2480                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2481                            task ? task->comm : "<unknown>",
2482                            task ? task->pid : -1,
2483                            file_priv->rps.boosts,
2484                            list_empty(&file_priv->rps.link) ? "" : ", active");
2485                 rcu_read_unlock();
2486         }
2487         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2488         spin_unlock(&dev_priv->rps.client_lock);
2489         mutex_unlock(&dev->filelist_mutex);
2490
2491         return 0;
2492 }
2493
2494 static int i915_llc(struct seq_file *m, void *data)
2495 {
2496         struct drm_info_node *node = m->private;
2497         struct drm_device *dev = node->minor->dev;
2498         struct drm_i915_private *dev_priv = to_i915(dev);
2499         const bool edram = INTEL_GEN(dev_priv) > 8;
2500
2501         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2502         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2503                    intel_uncore_edram_size(dev_priv)/1024/1024);
2504
2505         return 0;
2506 }
2507
2508 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2509 {
2510         struct drm_info_node *node = m->private;
2511         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2512         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2513         u32 tmp, i;
2514
2515         if (!HAS_GUC_UCODE(dev_priv))
2516                 return 0;
2517
2518         seq_printf(m, "GuC firmware status:\n");
2519         seq_printf(m, "\tpath: %s\n",
2520                 guc_fw->guc_fw_path);
2521         seq_printf(m, "\tfetch: %s\n",
2522                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2523         seq_printf(m, "\tload: %s\n",
2524                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2525         seq_printf(m, "\tversion wanted: %d.%d\n",
2526                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2527         seq_printf(m, "\tversion found: %d.%d\n",
2528                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2529         seq_printf(m, "\theader: offset is %d; size = %d\n",
2530                 guc_fw->header_offset, guc_fw->header_size);
2531         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2532                 guc_fw->ucode_offset, guc_fw->ucode_size);
2533         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2534                 guc_fw->rsa_offset, guc_fw->rsa_size);
2535
2536         tmp = I915_READ(GUC_STATUS);
2537
2538         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2539         seq_printf(m, "\tBootrom status = 0x%x\n",
2540                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2541         seq_printf(m, "\tuKernel status = 0x%x\n",
2542                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2543         seq_printf(m, "\tMIA Core status = 0x%x\n",
2544                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2545         seq_puts(m, "\nScratch registers:\n");
2546         for (i = 0; i < 16; i++)
2547                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2548
2549         return 0;
2550 }
2551
2552 static void i915_guc_client_info(struct seq_file *m,
2553                                  struct drm_i915_private *dev_priv,
2554                                  struct i915_guc_client *client)
2555 {
2556         struct intel_engine_cs *engine;
2557         uint64_t tot = 0;
2558
2559         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2560                 client->priority, client->ctx_index, client->proc_desc_offset);
2561         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2562                 client->doorbell_id, client->doorbell_offset, client->cookie);
2563         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2564                 client->wq_size, client->wq_offset, client->wq_tail);
2565
2566         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2567         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2568         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2569         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2570
2571         for_each_engine(engine, dev_priv) {
2572                 seq_printf(m, "\tSubmissions: %llu %s\n",
2573                                 client->submissions[engine->id],
2574                                 engine->name);
2575                 tot += client->submissions[engine->id];
2576         }
2577         seq_printf(m, "\tTotal: %llu\n", tot);
2578 }
2579
2580 static int i915_guc_info(struct seq_file *m, void *data)
2581 {
2582         struct drm_info_node *node = m->private;
2583         struct drm_device *dev = node->minor->dev;
2584         struct drm_i915_private *dev_priv = to_i915(dev);
2585         struct intel_guc guc;
2586         struct i915_guc_client client = {};
2587         struct intel_engine_cs *engine;
2588         u64 total = 0;
2589
2590         if (!HAS_GUC_SCHED(dev_priv))
2591                 return 0;
2592
2593         if (mutex_lock_interruptible(&dev->struct_mutex))
2594                 return 0;
2595
2596         /* Take a local copy of the GuC data, so we can dump it at leisure */
2597         guc = dev_priv->guc;
2598         if (guc.execbuf_client)
2599                 client = *guc.execbuf_client;
2600
2601         mutex_unlock(&dev->struct_mutex);
2602
2603         seq_printf(m, "Doorbell map:\n");
2604         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2605         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2606
2607         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2608         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2609         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2610         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2611         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2612
2613         seq_printf(m, "\nGuC submissions:\n");
2614         for_each_engine(engine, dev_priv) {
2615                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2616                         engine->name, guc.submissions[engine->id],
2617                         guc.last_seqno[engine->id]);
2618                 total += guc.submissions[engine->id];
2619         }
2620         seq_printf(m, "\t%s: %llu\n", "Total", total);
2621
2622         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2623         i915_guc_client_info(m, dev_priv, &client);
2624
2625         /* Add more as required ... */
2626
2627         return 0;
2628 }
2629
2630 static int i915_guc_log_dump(struct seq_file *m, void *data)
2631 {
2632         struct drm_info_node *node = m->private;
2633         struct drm_device *dev = node->minor->dev;
2634         struct drm_i915_private *dev_priv = to_i915(dev);
2635         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2636         u32 *log;
2637         int i = 0, pg;
2638
2639         if (!log_obj)
2640                 return 0;
2641
2642         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2643                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2644
2645                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2646                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2647                                    *(log + i), *(log + i + 1),
2648                                    *(log + i + 2), *(log + i + 3));
2649
2650                 kunmap_atomic(log);
2651         }
2652
2653         seq_putc(m, '\n');
2654
2655         return 0;
2656 }
2657
2658 static int i915_edp_psr_status(struct seq_file *m, void *data)
2659 {
2660         struct drm_info_node *node = m->private;
2661         struct drm_device *dev = node->minor->dev;
2662         struct drm_i915_private *dev_priv = to_i915(dev);
2663         u32 psrperf = 0;
2664         u32 stat[3];
2665         enum pipe pipe;
2666         bool enabled = false;
2667
2668         if (!HAS_PSR(dev)) {
2669                 seq_puts(m, "PSR not supported\n");
2670                 return 0;
2671         }
2672
2673         intel_runtime_pm_get(dev_priv);
2674
2675         mutex_lock(&dev_priv->psr.lock);
2676         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2677         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2678         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2679         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2680         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2681                    dev_priv->psr.busy_frontbuffer_bits);
2682         seq_printf(m, "Re-enable work scheduled: %s\n",
2683                    yesno(work_busy(&dev_priv->psr.work.work)));
2684
2685         if (HAS_DDI(dev))
2686                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2687         else {
2688                 for_each_pipe(dev_priv, pipe) {
2689                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2690                                 VLV_EDP_PSR_CURR_STATE_MASK;
2691                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2692                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2693                                 enabled = true;
2694                 }
2695         }
2696
2697         seq_printf(m, "Main link in standby mode: %s\n",
2698                    yesno(dev_priv->psr.link_standby));
2699
2700         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2701
2702         if (!HAS_DDI(dev))
2703                 for_each_pipe(dev_priv, pipe) {
2704                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2705                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2706                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2707                 }
2708         seq_puts(m, "\n");
2709
2710         /*
2711          * VLV/CHV PSR has no kind of performance counter
2712          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2713          */
2714         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2715                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2716                         EDP_PSR_PERF_CNT_MASK;
2717
2718                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2719         }
2720         mutex_unlock(&dev_priv->psr.lock);
2721
2722         intel_runtime_pm_put(dev_priv);
2723         return 0;
2724 }
2725
2726 static int i915_sink_crc(struct seq_file *m, void *data)
2727 {
2728         struct drm_info_node *node = m->private;
2729         struct drm_device *dev = node->minor->dev;
2730         struct intel_connector *connector;
2731         struct intel_dp *intel_dp = NULL;
2732         int ret;
2733         u8 crc[6];
2734
2735         drm_modeset_lock_all(dev);
2736         for_each_intel_connector(dev, connector) {
2737                 struct drm_crtc *crtc;
2738
2739                 if (!connector->base.state->best_encoder)
2740                         continue;
2741
2742                 crtc = connector->base.state->crtc;
2743                 if (!crtc->state->active)
2744                         continue;
2745
2746                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2747                         continue;
2748
2749                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2750
2751                 ret = intel_dp_sink_crc(intel_dp, crc);
2752                 if (ret)
2753                         goto out;
2754
2755                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2756                            crc[0], crc[1], crc[2],
2757                            crc[3], crc[4], crc[5]);
2758                 goto out;
2759         }
2760         ret = -ENODEV;
2761 out:
2762         drm_modeset_unlock_all(dev);
2763         return ret;
2764 }
2765
2766 static int i915_energy_uJ(struct seq_file *m, void *data)
2767 {
2768         struct drm_info_node *node = m->private;
2769         struct drm_device *dev = node->minor->dev;
2770         struct drm_i915_private *dev_priv = to_i915(dev);
2771         u64 power;
2772         u32 units;
2773
2774         if (INTEL_INFO(dev)->gen < 6)
2775                 return -ENODEV;
2776
2777         intel_runtime_pm_get(dev_priv);
2778
2779         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2780         power = (power & 0x1f00) >> 8;
2781         units = 1000000 / (1 << power); /* convert to uJ */
2782         power = I915_READ(MCH_SECP_NRG_STTS);
2783         power *= units;
2784
2785         intel_runtime_pm_put(dev_priv);
2786
2787         seq_printf(m, "%llu", (long long unsigned)power);
2788
2789         return 0;
2790 }
2791
2792 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2793 {
2794         struct drm_info_node *node = m->private;
2795         struct drm_device *dev = node->minor->dev;
2796         struct drm_i915_private *dev_priv = to_i915(dev);
2797
2798         if (!HAS_RUNTIME_PM(dev_priv))
2799                 seq_puts(m, "Runtime power management not supported\n");
2800
2801         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2802         seq_printf(m, "IRQs disabled: %s\n",
2803                    yesno(!intel_irqs_enabled(dev_priv)));
2804 #ifdef CONFIG_PM
2805         seq_printf(m, "Usage count: %d\n",
2806                    atomic_read(&dev->dev->power.usage_count));
2807 #else
2808         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2809 #endif
2810         seq_printf(m, "PCI device power state: %s [%d]\n",
2811                    pci_power_name(dev_priv->drm.pdev->current_state),
2812                    dev_priv->drm.pdev->current_state);
2813
2814         return 0;
2815 }
2816
2817 static int i915_power_domain_info(struct seq_file *m, void *unused)
2818 {
2819         struct drm_info_node *node = m->private;
2820         struct drm_device *dev = node->minor->dev;
2821         struct drm_i915_private *dev_priv = to_i915(dev);
2822         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2823         int i;
2824
2825         mutex_lock(&power_domains->lock);
2826
2827         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2828         for (i = 0; i < power_domains->power_well_count; i++) {
2829                 struct i915_power_well *power_well;
2830                 enum intel_display_power_domain power_domain;
2831
2832                 power_well = &power_domains->power_wells[i];
2833                 seq_printf(m, "%-25s %d\n", power_well->name,
2834                            power_well->count);
2835
2836                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2837                      power_domain++) {
2838                         if (!(BIT(power_domain) & power_well->domains))
2839                                 continue;
2840
2841                         seq_printf(m, "  %-23s %d\n",
2842                                  intel_display_power_domain_str(power_domain),
2843                                  power_domains->domain_use_count[power_domain]);
2844                 }
2845         }
2846
2847         mutex_unlock(&power_domains->lock);
2848
2849         return 0;
2850 }
2851
2852 static int i915_dmc_info(struct seq_file *m, void *unused)
2853 {
2854         struct drm_info_node *node = m->private;
2855         struct drm_device *dev = node->minor->dev;
2856         struct drm_i915_private *dev_priv = to_i915(dev);
2857         struct intel_csr *csr;
2858
2859         if (!HAS_CSR(dev)) {
2860                 seq_puts(m, "not supported\n");
2861                 return 0;
2862         }
2863
2864         csr = &dev_priv->csr;
2865
2866         intel_runtime_pm_get(dev_priv);
2867
2868         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2869         seq_printf(m, "path: %s\n", csr->fw_path);
2870
2871         if (!csr->dmc_payload)
2872                 goto out;
2873
2874         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2875                    CSR_VERSION_MINOR(csr->version));
2876
2877         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2878                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2879                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2880                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2881                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2882         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2883                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2884                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2885         }
2886
2887 out:
2888         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2889         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2890         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2891
2892         intel_runtime_pm_put(dev_priv);
2893
2894         return 0;
2895 }
2896
2897 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2898                                  struct drm_display_mode *mode)
2899 {
2900         int i;
2901
2902         for (i = 0; i < tabs; i++)
2903                 seq_putc(m, '\t');
2904
2905         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2906                    mode->base.id, mode->name,
2907                    mode->vrefresh, mode->clock,
2908                    mode->hdisplay, mode->hsync_start,
2909                    mode->hsync_end, mode->htotal,
2910                    mode->vdisplay, mode->vsync_start,
2911                    mode->vsync_end, mode->vtotal,
2912                    mode->type, mode->flags);
2913 }
2914
2915 static void intel_encoder_info(struct seq_file *m,
2916                                struct intel_crtc *intel_crtc,
2917                                struct intel_encoder *intel_encoder)
2918 {
2919         struct drm_info_node *node = m->private;
2920         struct drm_device *dev = node->minor->dev;
2921         struct drm_crtc *crtc = &intel_crtc->base;
2922         struct intel_connector *intel_connector;
2923         struct drm_encoder *encoder;
2924
2925         encoder = &intel_encoder->base;
2926         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2927                    encoder->base.id, encoder->name);
2928         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2929                 struct drm_connector *connector = &intel_connector->base;
2930                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2931                            connector->base.id,
2932                            connector->name,
2933                            drm_get_connector_status_name(connector->status));
2934                 if (connector->status == connector_status_connected) {
2935                         struct drm_display_mode *mode = &crtc->mode;
2936                         seq_printf(m, ", mode:\n");
2937                         intel_seq_print_mode(m, 2, mode);
2938                 } else {
2939                         seq_putc(m, '\n');
2940                 }
2941         }
2942 }
2943
2944 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2945 {
2946         struct drm_info_node *node = m->private;
2947         struct drm_device *dev = node->minor->dev;
2948         struct drm_crtc *crtc = &intel_crtc->base;
2949         struct intel_encoder *intel_encoder;
2950         struct drm_plane_state *plane_state = crtc->primary->state;
2951         struct drm_framebuffer *fb = plane_state->fb;
2952
2953         if (fb)
2954                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2955                            fb->base.id, plane_state->src_x >> 16,
2956                            plane_state->src_y >> 16, fb->width, fb->height);
2957         else
2958                 seq_puts(m, "\tprimary plane disabled\n");
2959         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2960                 intel_encoder_info(m, intel_crtc, intel_encoder);
2961 }
2962
2963 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2964 {
2965         struct drm_display_mode *mode = panel->fixed_mode;
2966
2967         seq_printf(m, "\tfixed mode:\n");
2968         intel_seq_print_mode(m, 2, mode);
2969 }
2970
2971 static void intel_dp_info(struct seq_file *m,
2972                           struct intel_connector *intel_connector)
2973 {
2974         struct intel_encoder *intel_encoder = intel_connector->encoder;
2975         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2976
2977         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2978         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2979         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2980                 intel_panel_info(m, &intel_connector->panel);
2981 }
2982
2983 static void intel_hdmi_info(struct seq_file *m,
2984                             struct intel_connector *intel_connector)
2985 {
2986         struct intel_encoder *intel_encoder = intel_connector->encoder;
2987         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2988
2989         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2990 }
2991
2992 static void intel_lvds_info(struct seq_file *m,
2993                             struct intel_connector *intel_connector)
2994 {
2995         intel_panel_info(m, &intel_connector->panel);
2996 }
2997
2998 static void intel_connector_info(struct seq_file *m,
2999                                  struct drm_connector *connector)
3000 {
3001         struct intel_connector *intel_connector = to_intel_connector(connector);
3002         struct intel_encoder *intel_encoder = intel_connector->encoder;
3003         struct drm_display_mode *mode;
3004
3005         seq_printf(m, "connector %d: type %s, status: %s\n",
3006                    connector->base.id, connector->name,
3007                    drm_get_connector_status_name(connector->status));
3008         if (connector->status == connector_status_connected) {
3009                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3010                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3011                            connector->display_info.width_mm,
3012                            connector->display_info.height_mm);
3013                 seq_printf(m, "\tsubpixel order: %s\n",
3014                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3015                 seq_printf(m, "\tCEA rev: %d\n",
3016                            connector->display_info.cea_rev);
3017         }
3018
3019         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3020                 return;
3021
3022         switch (connector->connector_type) {
3023         case DRM_MODE_CONNECTOR_DisplayPort:
3024         case DRM_MODE_CONNECTOR_eDP:
3025                 intel_dp_info(m, intel_connector);
3026                 break;
3027         case DRM_MODE_CONNECTOR_LVDS:
3028                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3029                         intel_lvds_info(m, intel_connector);
3030                 break;
3031         case DRM_MODE_CONNECTOR_HDMIA:
3032                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3033                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3034                         intel_hdmi_info(m, intel_connector);
3035                 break;
3036         default:
3037                 break;
3038         }
3039
3040         seq_printf(m, "\tmodes:\n");
3041         list_for_each_entry(mode, &connector->modes, head)
3042                 intel_seq_print_mode(m, 2, mode);
3043 }
3044
3045 static bool cursor_active(struct drm_device *dev, int pipe)
3046 {
3047         struct drm_i915_private *dev_priv = to_i915(dev);
3048         u32 state;
3049
3050         if (IS_845G(dev) || IS_I865G(dev))
3051                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3052         else
3053                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3054
3055         return state;
3056 }
3057
3058 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3059 {
3060         struct drm_i915_private *dev_priv = to_i915(dev);
3061         u32 pos;
3062
3063         pos = I915_READ(CURPOS(pipe));
3064
3065         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3066         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3067                 *x = -*x;
3068
3069         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3070         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3071                 *y = -*y;
3072
3073         return cursor_active(dev, pipe);
3074 }
3075
3076 static const char *plane_type(enum drm_plane_type type)
3077 {
3078         switch (type) {
3079         case DRM_PLANE_TYPE_OVERLAY:
3080                 return "OVL";
3081         case DRM_PLANE_TYPE_PRIMARY:
3082                 return "PRI";
3083         case DRM_PLANE_TYPE_CURSOR:
3084                 return "CUR";
3085         /*
3086          * Deliberately omitting default: to generate compiler warnings
3087          * when a new drm_plane_type gets added.
3088          */
3089         }
3090
3091         return "unknown";
3092 }
3093
3094 static const char *plane_rotation(unsigned int rotation)
3095 {
3096         static char buf[48];
3097         /*
3098          * According to doc only one DRM_ROTATE_ is allowed but this
3099          * will print them all to visualize if the values are misused
3100          */
3101         snprintf(buf, sizeof(buf),
3102                  "%s%s%s%s%s%s(0x%08x)",
3103                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3104                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3105                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3106                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3107                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3108                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3109                  rotation);
3110
3111         return buf;
3112 }
3113
3114 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3115 {
3116         struct drm_info_node *node = m->private;
3117         struct drm_device *dev = node->minor->dev;
3118         struct intel_plane *intel_plane;
3119
3120         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3121                 struct drm_plane_state *state;
3122                 struct drm_plane *plane = &intel_plane->base;
3123
3124                 if (!plane->state) {
3125                         seq_puts(m, "plane->state is NULL!\n");
3126                         continue;
3127                 }
3128
3129                 state = plane->state;
3130
3131                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3132                            plane->base.id,
3133                            plane_type(intel_plane->base.type),
3134                            state->crtc_x, state->crtc_y,
3135                            state->crtc_w, state->crtc_h,
3136                            (state->src_x >> 16),
3137                            ((state->src_x & 0xffff) * 15625) >> 10,
3138                            (state->src_y >> 16),
3139                            ((state->src_y & 0xffff) * 15625) >> 10,
3140                            (state->src_w >> 16),
3141                            ((state->src_w & 0xffff) * 15625) >> 10,
3142                            (state->src_h >> 16),
3143                            ((state->src_h & 0xffff) * 15625) >> 10,
3144                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3145                            plane_rotation(state->rotation));
3146         }
3147 }
3148
3149 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3150 {
3151         struct intel_crtc_state *pipe_config;
3152         int num_scalers = intel_crtc->num_scalers;
3153         int i;
3154
3155         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3156
3157         /* Not all platformas have a scaler */
3158         if (num_scalers) {
3159                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3160                            num_scalers,
3161                            pipe_config->scaler_state.scaler_users,
3162                            pipe_config->scaler_state.scaler_id);
3163
3164                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3165                         struct intel_scaler *sc =
3166                                         &pipe_config->scaler_state.scalers[i];
3167
3168                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3169                                    i, yesno(sc->in_use), sc->mode);
3170                 }
3171                 seq_puts(m, "\n");
3172         } else {
3173                 seq_puts(m, "\tNo scalers available on this platform\n");
3174         }
3175 }
3176
3177 static int i915_display_info(struct seq_file *m, void *unused)
3178 {
3179         struct drm_info_node *node = m->private;
3180         struct drm_device *dev = node->minor->dev;
3181         struct drm_i915_private *dev_priv = to_i915(dev);
3182         struct intel_crtc *crtc;
3183         struct drm_connector *connector;
3184
3185         intel_runtime_pm_get(dev_priv);
3186         drm_modeset_lock_all(dev);
3187         seq_printf(m, "CRTC info\n");
3188         seq_printf(m, "---------\n");
3189         for_each_intel_crtc(dev, crtc) {
3190                 bool active;
3191                 struct intel_crtc_state *pipe_config;
3192                 int x, y;
3193
3194                 pipe_config = to_intel_crtc_state(crtc->base.state);
3195
3196                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3197                            crtc->base.base.id, pipe_name(crtc->pipe),
3198                            yesno(pipe_config->base.active),
3199                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3200                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3201
3202                 if (pipe_config->base.active) {
3203                         intel_crtc_info(m, crtc);
3204
3205                         active = cursor_position(dev, crtc->pipe, &x, &y);
3206                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3207                                    yesno(crtc->cursor_base),
3208                                    x, y, crtc->base.cursor->state->crtc_w,
3209                                    crtc->base.cursor->state->crtc_h,
3210                                    crtc->cursor_addr, yesno(active));
3211                         intel_scaler_info(m, crtc);
3212                         intel_plane_info(m, crtc);
3213                 }
3214
3215                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3216                            yesno(!crtc->cpu_fifo_underrun_disabled),
3217                            yesno(!crtc->pch_fifo_underrun_disabled));
3218         }
3219
3220         seq_printf(m, "\n");
3221         seq_printf(m, "Connector info\n");
3222         seq_printf(m, "--------------\n");
3223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3224                 intel_connector_info(m, connector);
3225         }
3226         drm_modeset_unlock_all(dev);
3227         intel_runtime_pm_put(dev_priv);
3228
3229         return 0;
3230 }
3231
3232 static int i915_semaphore_status(struct seq_file *m, void *unused)
3233 {
3234         struct drm_info_node *node = (struct drm_info_node *) m->private;
3235         struct drm_device *dev = node->minor->dev;
3236         struct drm_i915_private *dev_priv = to_i915(dev);
3237         struct intel_engine_cs *engine;
3238         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3239         enum intel_engine_id id;
3240         int j, ret;
3241
3242         if (!i915.semaphores) {
3243                 seq_puts(m, "Semaphores are disabled\n");
3244                 return 0;
3245         }
3246
3247         ret = mutex_lock_interruptible(&dev->struct_mutex);
3248         if (ret)
3249                 return ret;
3250         intel_runtime_pm_get(dev_priv);
3251
3252         if (IS_BROADWELL(dev)) {
3253                 struct page *page;
3254                 uint64_t *seqno;
3255
3256                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3257
3258                 seqno = (uint64_t *)kmap_atomic(page);
3259                 for_each_engine_id(engine, dev_priv, id) {
3260                         uint64_t offset;
3261
3262                         seq_printf(m, "%s\n", engine->name);
3263
3264                         seq_puts(m, "  Last signal:");
3265                         for (j = 0; j < num_rings; j++) {
3266                                 offset = id * I915_NUM_ENGINES + j;
3267                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3268                                            seqno[offset], offset * 8);
3269                         }
3270                         seq_putc(m, '\n');
3271
3272                         seq_puts(m, "  Last wait:  ");
3273                         for (j = 0; j < num_rings; j++) {
3274                                 offset = id + (j * I915_NUM_ENGINES);
3275                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3276                                            seqno[offset], offset * 8);
3277                         }
3278                         seq_putc(m, '\n');
3279
3280                 }
3281                 kunmap_atomic(seqno);
3282         } else {
3283                 seq_puts(m, "  Last signal:");
3284                 for_each_engine(engine, dev_priv)
3285                         for (j = 0; j < num_rings; j++)
3286                                 seq_printf(m, "0x%08x\n",
3287                                            I915_READ(engine->semaphore.mbox.signal[j]));
3288                 seq_putc(m, '\n');
3289         }
3290
3291         seq_puts(m, "\nSync seqno:\n");
3292         for_each_engine(engine, dev_priv) {
3293                 for (j = 0; j < num_rings; j++)
3294                         seq_printf(m, "  0x%08x ",
3295                                    engine->semaphore.sync_seqno[j]);
3296                 seq_putc(m, '\n');
3297         }
3298         seq_putc(m, '\n');
3299
3300         intel_runtime_pm_put(dev_priv);
3301         mutex_unlock(&dev->struct_mutex);
3302         return 0;
3303 }
3304
3305 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3306 {
3307         struct drm_info_node *node = (struct drm_info_node *) m->private;
3308         struct drm_device *dev = node->minor->dev;
3309         struct drm_i915_private *dev_priv = to_i915(dev);
3310         int i;
3311
3312         drm_modeset_lock_all(dev);
3313         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3314                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3315
3316                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3317                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3318                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3319                 seq_printf(m, " tracked hardware state:\n");
3320                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3321                 seq_printf(m, " dpll_md: 0x%08x\n",
3322                            pll->config.hw_state.dpll_md);
3323                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3324                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3325                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3326         }
3327         drm_modeset_unlock_all(dev);
3328
3329         return 0;
3330 }
3331
3332 static int i915_wa_registers(struct seq_file *m, void *unused)
3333 {
3334         int i;
3335         int ret;
3336         struct intel_engine_cs *engine;
3337         struct drm_info_node *node = (struct drm_info_node *) m->private;
3338         struct drm_device *dev = node->minor->dev;
3339         struct drm_i915_private *dev_priv = to_i915(dev);
3340         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3341         enum intel_engine_id id;
3342
3343         ret = mutex_lock_interruptible(&dev->struct_mutex);
3344         if (ret)
3345                 return ret;
3346
3347         intel_runtime_pm_get(dev_priv);
3348
3349         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3350         for_each_engine_id(engine, dev_priv, id)
3351                 seq_printf(m, "HW whitelist count for %s: %d\n",
3352                            engine->name, workarounds->hw_whitelist_count[id]);
3353         for (i = 0; i < workarounds->count; ++i) {
3354                 i915_reg_t addr;
3355                 u32 mask, value, read;
3356                 bool ok;
3357
3358                 addr = workarounds->reg[i].addr;
3359                 mask = workarounds->reg[i].mask;
3360                 value = workarounds->reg[i].value;
3361                 read = I915_READ(addr);
3362                 ok = (value & mask) == (read & mask);
3363                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3364                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3365         }
3366
3367         intel_runtime_pm_put(dev_priv);
3368         mutex_unlock(&dev->struct_mutex);
3369
3370         return 0;
3371 }
3372
3373 static int i915_ddb_info(struct seq_file *m, void *unused)
3374 {
3375         struct drm_info_node *node = m->private;
3376         struct drm_device *dev = node->minor->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct skl_ddb_allocation *ddb;
3379         struct skl_ddb_entry *entry;
3380         enum pipe pipe;
3381         int plane;
3382
3383         if (INTEL_INFO(dev)->gen < 9)
3384                 return 0;
3385
3386         drm_modeset_lock_all(dev);
3387
3388         ddb = &dev_priv->wm.skl_hw.ddb;
3389
3390         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3391
3392         for_each_pipe(dev_priv, pipe) {
3393                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3394
3395                 for_each_plane(dev_priv, pipe, plane) {
3396                         entry = &ddb->plane[pipe][plane];
3397                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3398                                    entry->start, entry->end,
3399                                    skl_ddb_entry_size(entry));
3400                 }
3401
3402                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3403                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3404                            entry->end, skl_ddb_entry_size(entry));
3405         }
3406
3407         drm_modeset_unlock_all(dev);
3408
3409         return 0;
3410 }
3411
3412 static void drrs_status_per_crtc(struct seq_file *m,
3413                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3414 {
3415         struct drm_i915_private *dev_priv = to_i915(dev);
3416         struct i915_drrs *drrs = &dev_priv->drrs;
3417         int vrefresh = 0;
3418         struct drm_connector *connector;
3419
3420         drm_for_each_connector(connector, dev) {
3421                 if (connector->state->crtc != &intel_crtc->base)
3422                         continue;
3423
3424                 seq_printf(m, "%s:\n", connector->name);
3425         }
3426
3427         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3428                 seq_puts(m, "\tVBT: DRRS_type: Static");
3429         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3430                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3431         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3432                 seq_puts(m, "\tVBT: DRRS_type: None");
3433         else
3434                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3435
3436         seq_puts(m, "\n\n");
3437
3438         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3439                 struct intel_panel *panel;
3440
3441                 mutex_lock(&drrs->mutex);
3442                 /* DRRS Supported */
3443                 seq_puts(m, "\tDRRS Supported: Yes\n");
3444
3445                 /* disable_drrs() will make drrs->dp NULL */
3446                 if (!drrs->dp) {
3447                         seq_puts(m, "Idleness DRRS: Disabled");
3448                         mutex_unlock(&drrs->mutex);
3449                         return;
3450                 }
3451
3452                 panel = &drrs->dp->attached_connector->panel;
3453                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3454                                         drrs->busy_frontbuffer_bits);
3455
3456                 seq_puts(m, "\n\t\t");
3457                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3458                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3459                         vrefresh = panel->fixed_mode->vrefresh;
3460                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3461                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3462                         vrefresh = panel->downclock_mode->vrefresh;
3463                 } else {
3464                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3465                                                 drrs->refresh_rate_type);
3466                         mutex_unlock(&drrs->mutex);
3467                         return;
3468                 }
3469                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3470
3471                 seq_puts(m, "\n\t\t");
3472                 mutex_unlock(&drrs->mutex);
3473         } else {
3474                 /* DRRS not supported. Print the VBT parameter*/
3475                 seq_puts(m, "\tDRRS Supported : No");
3476         }
3477         seq_puts(m, "\n");
3478 }
3479
3480 static int i915_drrs_status(struct seq_file *m, void *unused)
3481 {
3482         struct drm_info_node *node = m->private;
3483         struct drm_device *dev = node->minor->dev;
3484         struct intel_crtc *intel_crtc;
3485         int active_crtc_cnt = 0;
3486
3487         drm_modeset_lock_all(dev);
3488         for_each_intel_crtc(dev, intel_crtc) {
3489                 if (intel_crtc->base.state->active) {
3490                         active_crtc_cnt++;
3491                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3492
3493                         drrs_status_per_crtc(m, dev, intel_crtc);
3494                 }
3495         }
3496         drm_modeset_unlock_all(dev);
3497
3498         if (!active_crtc_cnt)
3499                 seq_puts(m, "No active crtc found\n");
3500
3501         return 0;
3502 }
3503
3504 struct pipe_crc_info {
3505         const char *name;
3506         struct drm_device *dev;
3507         enum pipe pipe;
3508 };
3509
3510 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3511 {
3512         struct drm_info_node *node = (struct drm_info_node *) m->private;
3513         struct drm_device *dev = node->minor->dev;
3514         struct intel_encoder *intel_encoder;
3515         struct intel_digital_port *intel_dig_port;
3516         struct drm_connector *connector;
3517
3518         drm_modeset_lock_all(dev);
3519         drm_for_each_connector(connector, dev) {
3520                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3521                         continue;
3522
3523                 intel_encoder = intel_attached_encoder(connector);
3524                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3525                         continue;
3526
3527                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3528                 if (!intel_dig_port->dp.can_mst)
3529                         continue;
3530
3531                 seq_printf(m, "MST Source Port %c\n",
3532                            port_name(intel_dig_port->port));
3533                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3534         }
3535         drm_modeset_unlock_all(dev);
3536         return 0;
3537 }
3538
3539 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3540 {
3541         struct pipe_crc_info *info = inode->i_private;
3542         struct drm_i915_private *dev_priv = to_i915(info->dev);
3543         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3544
3545         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3546                 return -ENODEV;
3547
3548         spin_lock_irq(&pipe_crc->lock);
3549
3550         if (pipe_crc->opened) {
3551                 spin_unlock_irq(&pipe_crc->lock);
3552                 return -EBUSY; /* already open */
3553         }
3554
3555         pipe_crc->opened = true;
3556         filep->private_data = inode->i_private;
3557
3558         spin_unlock_irq(&pipe_crc->lock);
3559
3560         return 0;
3561 }
3562
3563 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3564 {
3565         struct pipe_crc_info *info = inode->i_private;
3566         struct drm_i915_private *dev_priv = to_i915(info->dev);
3567         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3568
3569         spin_lock_irq(&pipe_crc->lock);
3570         pipe_crc->opened = false;
3571         spin_unlock_irq(&pipe_crc->lock);
3572
3573         return 0;
3574 }
3575
3576 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3577 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3578 /* account for \'0' */
3579 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3580
3581 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3582 {
3583         assert_spin_locked(&pipe_crc->lock);
3584         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3585                         INTEL_PIPE_CRC_ENTRIES_NR);
3586 }
3587
3588 static ssize_t
3589 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3590                    loff_t *pos)
3591 {
3592         struct pipe_crc_info *info = filep->private_data;
3593         struct drm_device *dev = info->dev;
3594         struct drm_i915_private *dev_priv = to_i915(dev);
3595         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3596         char buf[PIPE_CRC_BUFFER_LEN];
3597         int n_entries;
3598         ssize_t bytes_read;
3599
3600         /*
3601          * Don't allow user space to provide buffers not big enough to hold
3602          * a line of data.
3603          */
3604         if (count < PIPE_CRC_LINE_LEN)
3605                 return -EINVAL;
3606
3607         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3608                 return 0;
3609
3610         /* nothing to read */
3611         spin_lock_irq(&pipe_crc->lock);
3612         while (pipe_crc_data_count(pipe_crc) == 0) {
3613                 int ret;
3614
3615                 if (filep->f_flags & O_NONBLOCK) {
3616                         spin_unlock_irq(&pipe_crc->lock);
3617                         return -EAGAIN;
3618                 }
3619
3620                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3621                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3622                 if (ret) {
3623                         spin_unlock_irq(&pipe_crc->lock);
3624                         return ret;
3625                 }
3626         }
3627
3628         /* We now have one or more entries to read */
3629         n_entries = count / PIPE_CRC_LINE_LEN;
3630
3631         bytes_read = 0;
3632         while (n_entries > 0) {
3633                 struct intel_pipe_crc_entry *entry =
3634                         &pipe_crc->entries[pipe_crc->tail];
3635                 int ret;
3636
3637                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3638                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3639                         break;
3640
3641                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3642                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3643
3644                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3645                                        "%8u %8x %8x %8x %8x %8x\n",
3646                                        entry->frame, entry->crc[0],
3647                                        entry->crc[1], entry->crc[2],
3648                                        entry->crc[3], entry->crc[4]);
3649
3650                 spin_unlock_irq(&pipe_crc->lock);
3651
3652                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3653                 if (ret == PIPE_CRC_LINE_LEN)
3654                         return -EFAULT;
3655
3656                 user_buf += PIPE_CRC_LINE_LEN;
3657                 n_entries--;
3658
3659                 spin_lock_irq(&pipe_crc->lock);
3660         }
3661
3662         spin_unlock_irq(&pipe_crc->lock);
3663
3664         return bytes_read;
3665 }
3666
3667 static const struct file_operations i915_pipe_crc_fops = {
3668         .owner = THIS_MODULE,
3669         .open = i915_pipe_crc_open,
3670         .read = i915_pipe_crc_read,
3671         .release = i915_pipe_crc_release,
3672 };
3673
3674 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3675         {
3676                 .name = "i915_pipe_A_crc",
3677                 .pipe = PIPE_A,
3678         },
3679         {
3680                 .name = "i915_pipe_B_crc",
3681                 .pipe = PIPE_B,
3682         },
3683         {
3684                 .name = "i915_pipe_C_crc",
3685                 .pipe = PIPE_C,
3686         },
3687 };
3688
3689 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3690                                 enum pipe pipe)
3691 {
3692         struct drm_device *dev = minor->dev;
3693         struct dentry *ent;
3694         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3695
3696         info->dev = dev;
3697         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3698                                   &i915_pipe_crc_fops);
3699         if (!ent)
3700                 return -ENOMEM;
3701
3702         return drm_add_fake_info_node(minor, ent, info);
3703 }
3704
3705 static const char * const pipe_crc_sources[] = {
3706         "none",
3707         "plane1",
3708         "plane2",
3709         "pf",
3710         "pipe",
3711         "TV",
3712         "DP-B",
3713         "DP-C",
3714         "DP-D",
3715         "auto",
3716 };
3717
3718 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3719 {
3720         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3721         return pipe_crc_sources[source];
3722 }
3723
3724 static int display_crc_ctl_show(struct seq_file *m, void *data)
3725 {
3726         struct drm_device *dev = m->private;
3727         struct drm_i915_private *dev_priv = to_i915(dev);
3728         int i;
3729
3730         for (i = 0; i < I915_MAX_PIPES; i++)
3731                 seq_printf(m, "%c %s\n", pipe_name(i),
3732                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3733
3734         return 0;
3735 }
3736
3737 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3738 {
3739         struct drm_device *dev = inode->i_private;
3740
3741         return single_open(file, display_crc_ctl_show, dev);
3742 }
3743
3744 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3745                                  uint32_t *val)
3746 {
3747         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3748                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3749
3750         switch (*source) {
3751         case INTEL_PIPE_CRC_SOURCE_PIPE:
3752                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3753                 break;
3754         case INTEL_PIPE_CRC_SOURCE_NONE:
3755                 *val = 0;
3756                 break;
3757         default:
3758                 return -EINVAL;
3759         }
3760
3761         return 0;
3762 }
3763
3764 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3765                                      enum intel_pipe_crc_source *source)
3766 {
3767         struct intel_encoder *encoder;
3768         struct intel_crtc *crtc;
3769         struct intel_digital_port *dig_port;
3770         int ret = 0;
3771
3772         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3773
3774         drm_modeset_lock_all(dev);
3775         for_each_intel_encoder(dev, encoder) {
3776                 if (!encoder->base.crtc)
3777                         continue;
3778
3779                 crtc = to_intel_crtc(encoder->base.crtc);
3780
3781                 if (crtc->pipe != pipe)
3782                         continue;
3783
3784                 switch (encoder->type) {
3785                 case INTEL_OUTPUT_TVOUT:
3786                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3787                         break;
3788                 case INTEL_OUTPUT_DP:
3789                 case INTEL_OUTPUT_EDP:
3790                         dig_port = enc_to_dig_port(&encoder->base);
3791                         switch (dig_port->port) {
3792                         case PORT_B:
3793                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3794                                 break;
3795                         case PORT_C:
3796                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3797                                 break;
3798                         case PORT_D:
3799                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3800                                 break;
3801                         default:
3802                                 WARN(1, "nonexisting DP port %c\n",
3803                                      port_name(dig_port->port));
3804                                 break;
3805                         }
3806                         break;
3807                 default:
3808                         break;
3809                 }
3810         }
3811         drm_modeset_unlock_all(dev);
3812
3813         return ret;
3814 }
3815
3816 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3817                                 enum pipe pipe,
3818                                 enum intel_pipe_crc_source *source,
3819                                 uint32_t *val)
3820 {
3821         struct drm_i915_private *dev_priv = to_i915(dev);
3822         bool need_stable_symbols = false;
3823
3824         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3825                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3826                 if (ret)
3827                         return ret;
3828         }
3829
3830         switch (*source) {
3831         case INTEL_PIPE_CRC_SOURCE_PIPE:
3832                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3833                 break;
3834         case INTEL_PIPE_CRC_SOURCE_DP_B:
3835                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3836                 need_stable_symbols = true;
3837                 break;
3838         case INTEL_PIPE_CRC_SOURCE_DP_C:
3839                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3840                 need_stable_symbols = true;
3841                 break;
3842         case INTEL_PIPE_CRC_SOURCE_DP_D:
3843                 if (!IS_CHERRYVIEW(dev))
3844                         return -EINVAL;
3845                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3846                 need_stable_symbols = true;
3847                 break;
3848         case INTEL_PIPE_CRC_SOURCE_NONE:
3849                 *val = 0;
3850                 break;
3851         default:
3852                 return -EINVAL;
3853         }
3854
3855         /*
3856          * When the pipe CRC tap point is after the transcoders we need
3857          * to tweak symbol-level features to produce a deterministic series of
3858          * symbols for a given frame. We need to reset those features only once
3859          * a frame (instead of every nth symbol):
3860          *   - DC-balance: used to ensure a better clock recovery from the data
3861          *     link (SDVO)
3862          *   - DisplayPort scrambling: used for EMI reduction
3863          */
3864         if (need_stable_symbols) {
3865                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3866
3867                 tmp |= DC_BALANCE_RESET_VLV;
3868                 switch (pipe) {
3869                 case PIPE_A:
3870                         tmp |= PIPE_A_SCRAMBLE_RESET;
3871                         break;
3872                 case PIPE_B:
3873                         tmp |= PIPE_B_SCRAMBLE_RESET;
3874                         break;
3875                 case PIPE_C:
3876                         tmp |= PIPE_C_SCRAMBLE_RESET;
3877                         break;
3878                 default:
3879                         return -EINVAL;
3880                 }
3881                 I915_WRITE(PORT_DFT2_G4X, tmp);
3882         }
3883
3884         return 0;
3885 }
3886
3887 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3888                                  enum pipe pipe,
3889                                  enum intel_pipe_crc_source *source,
3890                                  uint32_t *val)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(dev);
3893         bool need_stable_symbols = false;
3894
3895         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3896                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3897                 if (ret)
3898                         return ret;
3899         }
3900
3901         switch (*source) {
3902         case INTEL_PIPE_CRC_SOURCE_PIPE:
3903                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3904                 break;
3905         case INTEL_PIPE_CRC_SOURCE_TV:
3906                 if (!SUPPORTS_TV(dev))
3907                         return -EINVAL;
3908                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3909                 break;
3910         case INTEL_PIPE_CRC_SOURCE_DP_B:
3911                 if (!IS_G4X(dev))
3912                         return -EINVAL;
3913                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3914                 need_stable_symbols = true;
3915                 break;
3916         case INTEL_PIPE_CRC_SOURCE_DP_C:
3917                 if (!IS_G4X(dev))
3918                         return -EINVAL;
3919                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3920                 need_stable_symbols = true;
3921                 break;
3922         case INTEL_PIPE_CRC_SOURCE_DP_D:
3923                 if (!IS_G4X(dev))
3924                         return -EINVAL;
3925                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3926                 need_stable_symbols = true;
3927                 break;
3928         case INTEL_PIPE_CRC_SOURCE_NONE:
3929                 *val = 0;
3930                 break;
3931         default:
3932                 return -EINVAL;
3933         }
3934
3935         /*
3936          * When the pipe CRC tap point is after the transcoders we need
3937          * to tweak symbol-level features to produce a deterministic series of
3938          * symbols for a given frame. We need to reset those features only once
3939          * a frame (instead of every nth symbol):
3940          *   - DC-balance: used to ensure a better clock recovery from the data
3941          *     link (SDVO)
3942          *   - DisplayPort scrambling: used for EMI reduction
3943          */
3944         if (need_stable_symbols) {
3945                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3946
3947                 WARN_ON(!IS_G4X(dev));
3948
3949                 I915_WRITE(PORT_DFT_I9XX,
3950                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3951
3952                 if (pipe == PIPE_A)
3953                         tmp |= PIPE_A_SCRAMBLE_RESET;
3954                 else
3955                         tmp |= PIPE_B_SCRAMBLE_RESET;
3956
3957                 I915_WRITE(PORT_DFT2_G4X, tmp);
3958         }
3959
3960         return 0;
3961 }
3962
3963 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3964                                          enum pipe pipe)
3965 {
3966         struct drm_i915_private *dev_priv = to_i915(dev);
3967         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3968
3969         switch (pipe) {
3970         case PIPE_A:
3971                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3972                 break;
3973         case PIPE_B:
3974                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3975                 break;
3976         case PIPE_C:
3977                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3978                 break;
3979         default:
3980                 return;
3981         }
3982         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3983                 tmp &= ~DC_BALANCE_RESET_VLV;
3984         I915_WRITE(PORT_DFT2_G4X, tmp);
3985
3986 }
3987
3988 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3989                                          enum pipe pipe)
3990 {
3991         struct drm_i915_private *dev_priv = to_i915(dev);
3992         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3993
3994         if (pipe == PIPE_A)
3995                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3996         else
3997                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3998         I915_WRITE(PORT_DFT2_G4X, tmp);
3999
4000         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4001                 I915_WRITE(PORT_DFT_I9XX,
4002                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4003         }
4004 }
4005
4006 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4007                                 uint32_t *val)
4008 {
4009         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4010                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4011
4012         switch (*source) {
4013         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4014                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4015                 break;
4016         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4017                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4018                 break;
4019         case INTEL_PIPE_CRC_SOURCE_PIPE:
4020                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4021                 break;
4022         case INTEL_PIPE_CRC_SOURCE_NONE:
4023                 *val = 0;
4024                 break;
4025         default:
4026                 return -EINVAL;
4027         }
4028
4029         return 0;
4030 }
4031
4032 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4033 {
4034         struct drm_i915_private *dev_priv = to_i915(dev);
4035         struct intel_crtc *crtc =
4036                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4037         struct intel_crtc_state *pipe_config;
4038         struct drm_atomic_state *state;
4039         int ret = 0;
4040
4041         drm_modeset_lock_all(dev);
4042         state = drm_atomic_state_alloc(dev);
4043         if (!state) {
4044                 ret = -ENOMEM;
4045                 goto out;
4046         }
4047
4048         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4049         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4050         if (IS_ERR(pipe_config)) {
4051                 ret = PTR_ERR(pipe_config);
4052                 goto out;
4053         }
4054
4055         pipe_config->pch_pfit.force_thru = enable;
4056         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4057             pipe_config->pch_pfit.enabled != enable)
4058                 pipe_config->base.connectors_changed = true;
4059
4060         ret = drm_atomic_commit(state);
4061 out:
4062         drm_modeset_unlock_all(dev);
4063         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4064         if (ret)
4065                 drm_atomic_state_free(state);
4066 }
4067
4068 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4069                                 enum pipe pipe,
4070                                 enum intel_pipe_crc_source *source,
4071                                 uint32_t *val)
4072 {
4073         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4074                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4075
4076         switch (*source) {
4077         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4078                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4079                 break;
4080         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4081                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4082                 break;
4083         case INTEL_PIPE_CRC_SOURCE_PF:
4084                 if (IS_HASWELL(dev) && pipe == PIPE_A)
4085                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
4086
4087                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4088                 break;
4089         case INTEL_PIPE_CRC_SOURCE_NONE:
4090                 *val = 0;
4091                 break;
4092         default:
4093                 return -EINVAL;
4094         }
4095
4096         return 0;
4097 }
4098
4099 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4100                                enum intel_pipe_crc_source source)
4101 {
4102         struct drm_i915_private *dev_priv = to_i915(dev);
4103         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4104         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4105                                                                         pipe));
4106         enum intel_display_power_domain power_domain;
4107         u32 val = 0; /* shut up gcc */
4108         int ret;
4109
4110         if (pipe_crc->source == source)
4111                 return 0;
4112
4113         /* forbid changing the source without going back to 'none' */
4114         if (pipe_crc->source && source)
4115                 return -EINVAL;
4116
4117         power_domain = POWER_DOMAIN_PIPE(pipe);
4118         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4119                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4120                 return -EIO;
4121         }
4122
4123         if (IS_GEN2(dev))
4124                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4125         else if (INTEL_INFO(dev)->gen < 5)
4126                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4127         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4128                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4129         else if (IS_GEN5(dev) || IS_GEN6(dev))
4130                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4131         else
4132                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4133
4134         if (ret != 0)
4135                 goto out;
4136
4137         /* none -> real source transition */
4138         if (source) {
4139                 struct intel_pipe_crc_entry *entries;
4140
4141                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4142                                  pipe_name(pipe), pipe_crc_source_name(source));
4143
4144                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4145                                   sizeof(pipe_crc->entries[0]),
4146                                   GFP_KERNEL);
4147                 if (!entries) {
4148                         ret = -ENOMEM;
4149                         goto out;
4150                 }
4151
4152                 /*
4153                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4154                  * enabled and disabled dynamically based on package C states,
4155                  * user space can't make reliable use of the CRCs, so let's just
4156                  * completely disable it.
4157                  */
4158                 hsw_disable_ips(crtc);
4159
4160                 spin_lock_irq(&pipe_crc->lock);
4161                 kfree(pipe_crc->entries);
4162                 pipe_crc->entries = entries;
4163                 pipe_crc->head = 0;
4164                 pipe_crc->tail = 0;
4165                 spin_unlock_irq(&pipe_crc->lock);
4166         }
4167
4168         pipe_crc->source = source;
4169
4170         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4171         POSTING_READ(PIPE_CRC_CTL(pipe));
4172
4173         /* real source -> none transition */
4174         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4175                 struct intel_pipe_crc_entry *entries;
4176                 struct intel_crtc *crtc =
4177                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4178
4179                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4180                                  pipe_name(pipe));
4181
4182                 drm_modeset_lock(&crtc->base.mutex, NULL);
4183                 if (crtc->base.state->active)
4184                         intel_wait_for_vblank(dev, pipe);
4185                 drm_modeset_unlock(&crtc->base.mutex);
4186
4187                 spin_lock_irq(&pipe_crc->lock);
4188                 entries = pipe_crc->entries;
4189                 pipe_crc->entries = NULL;
4190                 pipe_crc->head = 0;
4191                 pipe_crc->tail = 0;
4192                 spin_unlock_irq(&pipe_crc->lock);
4193
4194                 kfree(entries);
4195
4196                 if (IS_G4X(dev))
4197                         g4x_undo_pipe_scramble_reset(dev, pipe);
4198                 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4199                         vlv_undo_pipe_scramble_reset(dev, pipe);
4200                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4201                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4202
4203                 hsw_enable_ips(crtc);
4204         }
4205
4206         ret = 0;
4207
4208 out:
4209         intel_display_power_put(dev_priv, power_domain);
4210
4211         return ret;
4212 }
4213
4214 /*
4215  * Parse pipe CRC command strings:
4216  *   command: wsp* object wsp+ name wsp+ source wsp*
4217  *   object: 'pipe'
4218  *   name: (A | B | C)
4219  *   source: (none | plane1 | plane2 | pf)
4220  *   wsp: (#0x20 | #0x9 | #0xA)+
4221  *
4222  * eg.:
4223  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4224  *  "pipe A none"    ->  Stop CRC
4225  */
4226 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4227 {
4228         int n_words = 0;
4229
4230         while (*buf) {
4231                 char *end;
4232
4233                 /* skip leading white space */
4234                 buf = skip_spaces(buf);
4235                 if (!*buf)
4236                         break;  /* end of buffer */
4237
4238                 /* find end of word */
4239                 for (end = buf; *end && !isspace(*end); end++)
4240                         ;
4241
4242                 if (n_words == max_words) {
4243                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4244                                          max_words);
4245                         return -EINVAL; /* ran out of words[] before bytes */
4246                 }
4247
4248                 if (*end)
4249                         *end++ = '\0';
4250                 words[n_words++] = buf;
4251                 buf = end;
4252         }
4253
4254         return n_words;
4255 }
4256
4257 enum intel_pipe_crc_object {
4258         PIPE_CRC_OBJECT_PIPE,
4259 };
4260
4261 static const char * const pipe_crc_objects[] = {
4262         "pipe",
4263 };
4264
4265 static int
4266 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4267 {
4268         int i;
4269
4270         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4271                 if (!strcmp(buf, pipe_crc_objects[i])) {
4272                         *o = i;
4273                         return 0;
4274                     }
4275
4276         return -EINVAL;
4277 }
4278
4279 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4280 {
4281         const char name = buf[0];
4282
4283         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4284                 return -EINVAL;
4285
4286         *pipe = name - 'A';
4287
4288         return 0;
4289 }
4290
4291 static int
4292 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4293 {
4294         int i;
4295
4296         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4297                 if (!strcmp(buf, pipe_crc_sources[i])) {
4298                         *s = i;
4299                         return 0;
4300                     }
4301
4302         return -EINVAL;
4303 }
4304
4305 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4306 {
4307 #define N_WORDS 3
4308         int n_words;
4309         char *words[N_WORDS];
4310         enum pipe pipe;
4311         enum intel_pipe_crc_object object;
4312         enum intel_pipe_crc_source source;
4313
4314         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4315         if (n_words != N_WORDS) {
4316                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4317                                  N_WORDS);
4318                 return -EINVAL;
4319         }
4320
4321         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4322                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4323                 return -EINVAL;
4324         }
4325
4326         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4327                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4328                 return -EINVAL;
4329         }
4330
4331         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4332                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4333                 return -EINVAL;
4334         }
4335
4336         return pipe_crc_set_source(dev, pipe, source);
4337 }
4338
4339 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4340                                      size_t len, loff_t *offp)
4341 {
4342         struct seq_file *m = file->private_data;
4343         struct drm_device *dev = m->private;
4344         char *tmpbuf;
4345         int ret;
4346
4347         if (len == 0)
4348                 return 0;
4349
4350         if (len > PAGE_SIZE - 1) {
4351                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4352                                  PAGE_SIZE);
4353                 return -E2BIG;
4354         }
4355
4356         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4357         if (!tmpbuf)
4358                 return -ENOMEM;
4359
4360         if (copy_from_user(tmpbuf, ubuf, len)) {
4361                 ret = -EFAULT;
4362                 goto out;
4363         }
4364         tmpbuf[len] = '\0';
4365
4366         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4367
4368 out:
4369         kfree(tmpbuf);
4370         if (ret < 0)
4371                 return ret;
4372
4373         *offp += len;
4374         return len;
4375 }
4376
4377 static const struct file_operations i915_display_crc_ctl_fops = {
4378         .owner = THIS_MODULE,
4379         .open = display_crc_ctl_open,
4380         .read = seq_read,
4381         .llseek = seq_lseek,
4382         .release = single_release,
4383         .write = display_crc_ctl_write
4384 };
4385
4386 static ssize_t i915_displayport_test_active_write(struct file *file,
4387                                             const char __user *ubuf,
4388                                             size_t len, loff_t *offp)
4389 {
4390         char *input_buffer;
4391         int status = 0;
4392         struct drm_device *dev;
4393         struct drm_connector *connector;
4394         struct list_head *connector_list;
4395         struct intel_dp *intel_dp;
4396         int val = 0;
4397
4398         dev = ((struct seq_file *)file->private_data)->private;
4399
4400         connector_list = &dev->mode_config.connector_list;
4401
4402         if (len == 0)
4403                 return 0;
4404
4405         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4406         if (!input_buffer)
4407                 return -ENOMEM;
4408
4409         if (copy_from_user(input_buffer, ubuf, len)) {
4410                 status = -EFAULT;
4411                 goto out;
4412         }
4413
4414         input_buffer[len] = '\0';
4415         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4416
4417         list_for_each_entry(connector, connector_list, head) {
4418
4419                 if (connector->connector_type !=
4420                     DRM_MODE_CONNECTOR_DisplayPort)
4421                         continue;
4422
4423                 if (connector->status == connector_status_connected &&
4424                     connector->encoder != NULL) {
4425                         intel_dp = enc_to_intel_dp(connector->encoder);
4426                         status = kstrtoint(input_buffer, 10, &val);
4427                         if (status < 0)
4428                                 goto out;
4429                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4430                         /* To prevent erroneous activation of the compliance
4431                          * testing code, only accept an actual value of 1 here
4432                          */
4433                         if (val == 1)
4434                                 intel_dp->compliance_test_active = 1;
4435                         else
4436                                 intel_dp->compliance_test_active = 0;
4437                 }
4438         }
4439 out:
4440         kfree(input_buffer);
4441         if (status < 0)
4442                 return status;
4443
4444         *offp += len;
4445         return len;
4446 }
4447
4448 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4449 {
4450         struct drm_device *dev = m->private;
4451         struct drm_connector *connector;
4452         struct list_head *connector_list = &dev->mode_config.connector_list;
4453         struct intel_dp *intel_dp;
4454
4455         list_for_each_entry(connector, connector_list, head) {
4456
4457                 if (connector->connector_type !=
4458                     DRM_MODE_CONNECTOR_DisplayPort)
4459                         continue;
4460
4461                 if (connector->status == connector_status_connected &&
4462                     connector->encoder != NULL) {
4463                         intel_dp = enc_to_intel_dp(connector->encoder);
4464                         if (intel_dp->compliance_test_active)
4465                                 seq_puts(m, "1");
4466                         else
4467                                 seq_puts(m, "0");
4468                 } else
4469                         seq_puts(m, "0");
4470         }
4471
4472         return 0;
4473 }
4474
4475 static int i915_displayport_test_active_open(struct inode *inode,
4476                                        struct file *file)
4477 {
4478         struct drm_device *dev = inode->i_private;
4479
4480         return single_open(file, i915_displayport_test_active_show, dev);
4481 }
4482
4483 static const struct file_operations i915_displayport_test_active_fops = {
4484         .owner = THIS_MODULE,
4485         .open = i915_displayport_test_active_open,
4486         .read = seq_read,
4487         .llseek = seq_lseek,
4488         .release = single_release,
4489         .write = i915_displayport_test_active_write
4490 };
4491
4492 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4493 {
4494         struct drm_device *dev = m->private;
4495         struct drm_connector *connector;
4496         struct list_head *connector_list = &dev->mode_config.connector_list;
4497         struct intel_dp *intel_dp;
4498
4499         list_for_each_entry(connector, connector_list, head) {
4500
4501                 if (connector->connector_type !=
4502                     DRM_MODE_CONNECTOR_DisplayPort)
4503                         continue;
4504
4505                 if (connector->status == connector_status_connected &&
4506                     connector->encoder != NULL) {
4507                         intel_dp = enc_to_intel_dp(connector->encoder);
4508                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4509                 } else
4510                         seq_puts(m, "0");
4511         }
4512
4513         return 0;
4514 }
4515 static int i915_displayport_test_data_open(struct inode *inode,
4516                                        struct file *file)
4517 {
4518         struct drm_device *dev = inode->i_private;
4519
4520         return single_open(file, i915_displayport_test_data_show, dev);
4521 }
4522
4523 static const struct file_operations i915_displayport_test_data_fops = {
4524         .owner = THIS_MODULE,
4525         .open = i915_displayport_test_data_open,
4526         .read = seq_read,
4527         .llseek = seq_lseek,
4528         .release = single_release
4529 };
4530
4531 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4532 {
4533         struct drm_device *dev = m->private;
4534         struct drm_connector *connector;
4535         struct list_head *connector_list = &dev->mode_config.connector_list;
4536         struct intel_dp *intel_dp;
4537
4538         list_for_each_entry(connector, connector_list, head) {
4539
4540                 if (connector->connector_type !=
4541                     DRM_MODE_CONNECTOR_DisplayPort)
4542                         continue;
4543
4544                 if (connector->status == connector_status_connected &&
4545                     connector->encoder != NULL) {
4546                         intel_dp = enc_to_intel_dp(connector->encoder);
4547                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4548                 } else
4549                         seq_puts(m, "0");
4550         }
4551
4552         return 0;
4553 }
4554
4555 static int i915_displayport_test_type_open(struct inode *inode,
4556                                        struct file *file)
4557 {
4558         struct drm_device *dev = inode->i_private;
4559
4560         return single_open(file, i915_displayport_test_type_show, dev);
4561 }
4562
4563 static const struct file_operations i915_displayport_test_type_fops = {
4564         .owner = THIS_MODULE,
4565         .open = i915_displayport_test_type_open,
4566         .read = seq_read,
4567         .llseek = seq_lseek,
4568         .release = single_release
4569 };
4570
4571 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4572 {
4573         struct drm_device *dev = m->private;
4574         int level;
4575         int num_levels;
4576
4577         if (IS_CHERRYVIEW(dev))
4578                 num_levels = 3;
4579         else if (IS_VALLEYVIEW(dev))
4580                 num_levels = 1;
4581         else
4582                 num_levels = ilk_wm_max_level(dev) + 1;
4583
4584         drm_modeset_lock_all(dev);
4585
4586         for (level = 0; level < num_levels; level++) {
4587                 unsigned int latency = wm[level];
4588
4589                 /*
4590                  * - WM1+ latency values in 0.5us units
4591                  * - latencies are in us on gen9/vlv/chv
4592                  */
4593                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4594                     IS_CHERRYVIEW(dev))
4595                         latency *= 10;
4596                 else if (level > 0)
4597                         latency *= 5;
4598
4599                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4600                            level, wm[level], latency / 10, latency % 10);
4601         }
4602
4603         drm_modeset_unlock_all(dev);
4604 }
4605
4606 static int pri_wm_latency_show(struct seq_file *m, void *data)
4607 {
4608         struct drm_device *dev = m->private;
4609         struct drm_i915_private *dev_priv = to_i915(dev);
4610         const uint16_t *latencies;
4611
4612         if (INTEL_INFO(dev)->gen >= 9)
4613                 latencies = dev_priv->wm.skl_latency;
4614         else
4615                 latencies = to_i915(dev)->wm.pri_latency;
4616
4617         wm_latency_show(m, latencies);
4618
4619         return 0;
4620 }
4621
4622 static int spr_wm_latency_show(struct seq_file *m, void *data)
4623 {
4624         struct drm_device *dev = m->private;
4625         struct drm_i915_private *dev_priv = to_i915(dev);
4626         const uint16_t *latencies;
4627
4628         if (INTEL_INFO(dev)->gen >= 9)
4629                 latencies = dev_priv->wm.skl_latency;
4630         else
4631                 latencies = to_i915(dev)->wm.spr_latency;
4632
4633         wm_latency_show(m, latencies);
4634
4635         return 0;
4636 }
4637
4638 static int cur_wm_latency_show(struct seq_file *m, void *data)
4639 {
4640         struct drm_device *dev = m->private;
4641         struct drm_i915_private *dev_priv = to_i915(dev);
4642         const uint16_t *latencies;
4643
4644         if (INTEL_INFO(dev)->gen >= 9)
4645                 latencies = dev_priv->wm.skl_latency;
4646         else
4647                 latencies = to_i915(dev)->wm.cur_latency;
4648
4649         wm_latency_show(m, latencies);
4650
4651         return 0;
4652 }
4653
4654 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4655 {
4656         struct drm_device *dev = inode->i_private;
4657
4658         if (INTEL_INFO(dev)->gen < 5)
4659                 return -ENODEV;
4660
4661         return single_open(file, pri_wm_latency_show, dev);
4662 }
4663
4664 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4665 {
4666         struct drm_device *dev = inode->i_private;
4667
4668         if (HAS_GMCH_DISPLAY(dev))
4669                 return -ENODEV;
4670
4671         return single_open(file, spr_wm_latency_show, dev);
4672 }
4673
4674 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4675 {
4676         struct drm_device *dev = inode->i_private;
4677
4678         if (HAS_GMCH_DISPLAY(dev))
4679                 return -ENODEV;
4680
4681         return single_open(file, cur_wm_latency_show, dev);
4682 }
4683
4684 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4685                                 size_t len, loff_t *offp, uint16_t wm[8])
4686 {
4687         struct seq_file *m = file->private_data;
4688         struct drm_device *dev = m->private;
4689         uint16_t new[8] = { 0 };
4690         int num_levels;
4691         int level;
4692         int ret;
4693         char tmp[32];
4694
4695         if (IS_CHERRYVIEW(dev))
4696                 num_levels = 3;
4697         else if (IS_VALLEYVIEW(dev))
4698                 num_levels = 1;
4699         else
4700                 num_levels = ilk_wm_max_level(dev) + 1;
4701
4702         if (len >= sizeof(tmp))
4703                 return -EINVAL;
4704
4705         if (copy_from_user(tmp, ubuf, len))
4706                 return -EFAULT;
4707
4708         tmp[len] = '\0';
4709
4710         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4711                      &new[0], &new[1], &new[2], &new[3],
4712                      &new[4], &new[5], &new[6], &new[7]);
4713         if (ret != num_levels)
4714                 return -EINVAL;
4715
4716         drm_modeset_lock_all(dev);
4717
4718         for (level = 0; level < num_levels; level++)
4719                 wm[level] = new[level];
4720
4721         drm_modeset_unlock_all(dev);
4722
4723         return len;
4724 }
4725
4726
4727 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4728                                     size_t len, loff_t *offp)
4729 {
4730         struct seq_file *m = file->private_data;
4731         struct drm_device *dev = m->private;
4732         struct drm_i915_private *dev_priv = to_i915(dev);
4733         uint16_t *latencies;
4734
4735         if (INTEL_INFO(dev)->gen >= 9)
4736                 latencies = dev_priv->wm.skl_latency;
4737         else
4738                 latencies = to_i915(dev)->wm.pri_latency;
4739
4740         return wm_latency_write(file, ubuf, len, offp, latencies);
4741 }
4742
4743 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4744                                     size_t len, loff_t *offp)
4745 {
4746         struct seq_file *m = file->private_data;
4747         struct drm_device *dev = m->private;
4748         struct drm_i915_private *dev_priv = to_i915(dev);
4749         uint16_t *latencies;
4750
4751         if (INTEL_INFO(dev)->gen >= 9)
4752                 latencies = dev_priv->wm.skl_latency;
4753         else
4754                 latencies = to_i915(dev)->wm.spr_latency;
4755
4756         return wm_latency_write(file, ubuf, len, offp, latencies);
4757 }
4758
4759 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4760                                     size_t len, loff_t *offp)
4761 {
4762         struct seq_file *m = file->private_data;
4763         struct drm_device *dev = m->private;
4764         struct drm_i915_private *dev_priv = to_i915(dev);
4765         uint16_t *latencies;
4766
4767         if (INTEL_INFO(dev)->gen >= 9)
4768                 latencies = dev_priv->wm.skl_latency;
4769         else
4770                 latencies = to_i915(dev)->wm.cur_latency;
4771
4772         return wm_latency_write(file, ubuf, len, offp, latencies);
4773 }
4774
4775 static const struct file_operations i915_pri_wm_latency_fops = {
4776         .owner = THIS_MODULE,
4777         .open = pri_wm_latency_open,
4778         .read = seq_read,
4779         .llseek = seq_lseek,
4780         .release = single_release,
4781         .write = pri_wm_latency_write
4782 };
4783
4784 static const struct file_operations i915_spr_wm_latency_fops = {
4785         .owner = THIS_MODULE,
4786         .open = spr_wm_latency_open,
4787         .read = seq_read,
4788         .llseek = seq_lseek,
4789         .release = single_release,
4790         .write = spr_wm_latency_write
4791 };
4792
4793 static const struct file_operations i915_cur_wm_latency_fops = {
4794         .owner = THIS_MODULE,
4795         .open = cur_wm_latency_open,
4796         .read = seq_read,
4797         .llseek = seq_lseek,
4798         .release = single_release,
4799         .write = cur_wm_latency_write
4800 };
4801
4802 static int
4803 i915_wedged_get(void *data, u64 *val)
4804 {
4805         struct drm_device *dev = data;
4806         struct drm_i915_private *dev_priv = to_i915(dev);
4807
4808         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4809
4810         return 0;
4811 }
4812
4813 static int
4814 i915_wedged_set(void *data, u64 val)
4815 {
4816         struct drm_device *dev = data;
4817         struct drm_i915_private *dev_priv = to_i915(dev);
4818
4819         /*
4820          * There is no safeguard against this debugfs entry colliding
4821          * with the hangcheck calling same i915_handle_error() in
4822          * parallel, causing an explosion. For now we assume that the
4823          * test harness is responsible enough not to inject gpu hangs
4824          * while it is writing to 'i915_wedged'
4825          */
4826
4827         if (i915_reset_in_progress(&dev_priv->gpu_error))
4828                 return -EAGAIN;
4829
4830         intel_runtime_pm_get(dev_priv);
4831
4832         i915_handle_error(dev_priv, val,
4833                           "Manually setting wedged to %llu", val);
4834
4835         intel_runtime_pm_put(dev_priv);
4836
4837         return 0;
4838 }
4839
4840 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4841                         i915_wedged_get, i915_wedged_set,
4842                         "%llu\n");
4843
4844 static int
4845 i915_ring_missed_irq_get(void *data, u64 *val)
4846 {
4847         struct drm_device *dev = data;
4848         struct drm_i915_private *dev_priv = to_i915(dev);
4849
4850         *val = dev_priv->gpu_error.missed_irq_rings;
4851         return 0;
4852 }
4853
4854 static int
4855 i915_ring_missed_irq_set(void *data, u64 val)
4856 {
4857         struct drm_device *dev = data;
4858         struct drm_i915_private *dev_priv = to_i915(dev);
4859         int ret;
4860
4861         /* Lock against concurrent debugfs callers */
4862         ret = mutex_lock_interruptible(&dev->struct_mutex);
4863         if (ret)
4864                 return ret;
4865         dev_priv->gpu_error.missed_irq_rings = val;
4866         mutex_unlock(&dev->struct_mutex);
4867
4868         return 0;
4869 }
4870
4871 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4872                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4873                         "0x%08llx\n");
4874
4875 static int
4876 i915_ring_test_irq_get(void *data, u64 *val)
4877 {
4878         struct drm_device *dev = data;
4879         struct drm_i915_private *dev_priv = to_i915(dev);
4880
4881         *val = dev_priv->gpu_error.test_irq_rings;
4882
4883         return 0;
4884 }
4885
4886 static int
4887 i915_ring_test_irq_set(void *data, u64 val)
4888 {
4889         struct drm_device *dev = data;
4890         struct drm_i915_private *dev_priv = to_i915(dev);
4891
4892         val &= INTEL_INFO(dev_priv)->ring_mask;
4893         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4894         dev_priv->gpu_error.test_irq_rings = val;
4895
4896         return 0;
4897 }
4898
4899 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4900                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4901                         "0x%08llx\n");
4902
4903 #define DROP_UNBOUND 0x1
4904 #define DROP_BOUND 0x2
4905 #define DROP_RETIRE 0x4
4906 #define DROP_ACTIVE 0x8
4907 #define DROP_ALL (DROP_UNBOUND | \
4908                   DROP_BOUND | \
4909                   DROP_RETIRE | \
4910                   DROP_ACTIVE)
4911 static int
4912 i915_drop_caches_get(void *data, u64 *val)
4913 {
4914         *val = DROP_ALL;
4915
4916         return 0;
4917 }
4918
4919 static int
4920 i915_drop_caches_set(void *data, u64 val)
4921 {
4922         struct drm_device *dev = data;
4923         struct drm_i915_private *dev_priv = to_i915(dev);
4924         int ret;
4925
4926         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4927
4928         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4929          * on ioctls on -EAGAIN. */
4930         ret = mutex_lock_interruptible(&dev->struct_mutex);
4931         if (ret)
4932                 return ret;
4933
4934         if (val & DROP_ACTIVE) {
4935                 ret = i915_gem_wait_for_idle(dev_priv);
4936                 if (ret)
4937                         goto unlock;
4938         }
4939
4940         if (val & (DROP_RETIRE | DROP_ACTIVE))
4941                 i915_gem_retire_requests(dev_priv);
4942
4943         if (val & DROP_BOUND)
4944                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4945
4946         if (val & DROP_UNBOUND)
4947                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4948
4949 unlock:
4950         mutex_unlock(&dev->struct_mutex);
4951
4952         return ret;
4953 }
4954
4955 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4956                         i915_drop_caches_get, i915_drop_caches_set,
4957                         "0x%08llx\n");
4958
4959 static int
4960 i915_max_freq_get(void *data, u64 *val)
4961 {
4962         struct drm_device *dev = data;
4963         struct drm_i915_private *dev_priv = to_i915(dev);
4964
4965         if (INTEL_INFO(dev)->gen < 6)
4966                 return -ENODEV;
4967
4968         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4969         return 0;
4970 }
4971
4972 static int
4973 i915_max_freq_set(void *data, u64 val)
4974 {
4975         struct drm_device *dev = data;
4976         struct drm_i915_private *dev_priv = to_i915(dev);
4977         u32 hw_max, hw_min;
4978         int ret;
4979
4980         if (INTEL_INFO(dev)->gen < 6)
4981                 return -ENODEV;
4982
4983         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4984
4985         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4986         if (ret)
4987                 return ret;
4988
4989         /*
4990          * Turbo will still be enabled, but won't go above the set value.
4991          */
4992         val = intel_freq_opcode(dev_priv, val);
4993
4994         hw_max = dev_priv->rps.max_freq;
4995         hw_min = dev_priv->rps.min_freq;
4996
4997         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4998                 mutex_unlock(&dev_priv->rps.hw_lock);
4999                 return -EINVAL;
5000         }
5001
5002         dev_priv->rps.max_freq_softlimit = val;
5003
5004         intel_set_rps(dev_priv, val);
5005
5006         mutex_unlock(&dev_priv->rps.hw_lock);
5007
5008         return 0;
5009 }
5010
5011 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5012                         i915_max_freq_get, i915_max_freq_set,
5013                         "%llu\n");
5014
5015 static int
5016 i915_min_freq_get(void *data, u64 *val)
5017 {
5018         struct drm_device *dev = data;
5019         struct drm_i915_private *dev_priv = to_i915(dev);
5020
5021         if (INTEL_GEN(dev_priv) < 6)
5022                 return -ENODEV;
5023
5024         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5025         return 0;
5026 }
5027
5028 static int
5029 i915_min_freq_set(void *data, u64 val)
5030 {
5031         struct drm_device *dev = data;
5032         struct drm_i915_private *dev_priv = to_i915(dev);
5033         u32 hw_max, hw_min;
5034         int ret;
5035
5036         if (INTEL_GEN(dev_priv) < 6)
5037                 return -ENODEV;
5038
5039         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5040
5041         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5042         if (ret)
5043                 return ret;
5044
5045         /*
5046          * Turbo will still be enabled, but won't go below the set value.
5047          */
5048         val = intel_freq_opcode(dev_priv, val);
5049
5050         hw_max = dev_priv->rps.max_freq;
5051         hw_min = dev_priv->rps.min_freq;
5052
5053         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5054                 mutex_unlock(&dev_priv->rps.hw_lock);
5055                 return -EINVAL;
5056         }
5057
5058         dev_priv->rps.min_freq_softlimit = val;
5059
5060         intel_set_rps(dev_priv, val);
5061
5062         mutex_unlock(&dev_priv->rps.hw_lock);
5063
5064         return 0;
5065 }
5066
5067 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5068                         i915_min_freq_get, i915_min_freq_set,
5069                         "%llu\n");
5070
5071 static int
5072 i915_cache_sharing_get(void *data, u64 *val)
5073 {
5074         struct drm_device *dev = data;
5075         struct drm_i915_private *dev_priv = to_i915(dev);
5076         u32 snpcr;
5077         int ret;
5078
5079         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5080                 return -ENODEV;
5081
5082         ret = mutex_lock_interruptible(&dev->struct_mutex);
5083         if (ret)
5084                 return ret;
5085         intel_runtime_pm_get(dev_priv);
5086
5087         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5088
5089         intel_runtime_pm_put(dev_priv);
5090         mutex_unlock(&dev_priv->drm.struct_mutex);
5091
5092         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5093
5094         return 0;
5095 }
5096
5097 static int
5098 i915_cache_sharing_set(void *data, u64 val)
5099 {
5100         struct drm_device *dev = data;
5101         struct drm_i915_private *dev_priv = to_i915(dev);
5102         u32 snpcr;
5103
5104         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5105                 return -ENODEV;
5106
5107         if (val > 3)
5108                 return -EINVAL;
5109
5110         intel_runtime_pm_get(dev_priv);
5111         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5112
5113         /* Update the cache sharing policy here as well */
5114         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5115         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5116         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5117         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5118
5119         intel_runtime_pm_put(dev_priv);
5120         return 0;
5121 }
5122
5123 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5124                         i915_cache_sharing_get, i915_cache_sharing_set,
5125                         "%llu\n");
5126
5127 struct sseu_dev_status {
5128         unsigned int slice_total;
5129         unsigned int subslice_total;
5130         unsigned int subslice_per_slice;
5131         unsigned int eu_total;
5132         unsigned int eu_per_subslice;
5133 };
5134
5135 static void cherryview_sseu_device_status(struct drm_device *dev,
5136                                           struct sseu_dev_status *stat)
5137 {
5138         struct drm_i915_private *dev_priv = to_i915(dev);
5139         int ss_max = 2;
5140         int ss;
5141         u32 sig1[ss_max], sig2[ss_max];
5142
5143         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5144         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5145         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5146         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5147
5148         for (ss = 0; ss < ss_max; ss++) {
5149                 unsigned int eu_cnt;
5150
5151                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5152                         /* skip disabled subslice */
5153                         continue;
5154
5155                 stat->slice_total = 1;
5156                 stat->subslice_per_slice++;
5157                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5158                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5159                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5160                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5161                 stat->eu_total += eu_cnt;
5162                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5163         }
5164         stat->subslice_total = stat->subslice_per_slice;
5165 }
5166
5167 static void gen9_sseu_device_status(struct drm_device *dev,
5168                                     struct sseu_dev_status *stat)
5169 {
5170         struct drm_i915_private *dev_priv = to_i915(dev);
5171         int s_max = 3, ss_max = 4;
5172         int s, ss;
5173         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5174
5175         /* BXT has a single slice and at most 3 subslices. */
5176         if (IS_BROXTON(dev)) {
5177                 s_max = 1;
5178                 ss_max = 3;
5179         }
5180
5181         for (s = 0; s < s_max; s++) {
5182                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5183                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5184                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5185         }
5186
5187         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5188                      GEN9_PGCTL_SSA_EU19_ACK |
5189                      GEN9_PGCTL_SSA_EU210_ACK |
5190                      GEN9_PGCTL_SSA_EU311_ACK;
5191         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5192                      GEN9_PGCTL_SSB_EU19_ACK |
5193                      GEN9_PGCTL_SSB_EU210_ACK |
5194                      GEN9_PGCTL_SSB_EU311_ACK;
5195
5196         for (s = 0; s < s_max; s++) {
5197                 unsigned int ss_cnt = 0;
5198
5199                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5200                         /* skip disabled slice */
5201                         continue;
5202
5203                 stat->slice_total++;
5204
5205                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5206                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5207
5208                 for (ss = 0; ss < ss_max; ss++) {
5209                         unsigned int eu_cnt;
5210
5211                         if (IS_BROXTON(dev) &&
5212                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5213                                 /* skip disabled subslice */
5214                                 continue;
5215
5216                         if (IS_BROXTON(dev))
5217                                 ss_cnt++;
5218
5219                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5220                                                eu_mask[ss%2]);
5221                         stat->eu_total += eu_cnt;
5222                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5223                                                     eu_cnt);
5224                 }
5225
5226                 stat->subslice_total += ss_cnt;
5227                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5228                                                ss_cnt);
5229         }
5230 }
5231
5232 static void broadwell_sseu_device_status(struct drm_device *dev,
5233                                          struct sseu_dev_status *stat)
5234 {
5235         struct drm_i915_private *dev_priv = to_i915(dev);
5236         int s;
5237         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5238
5239         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5240
5241         if (stat->slice_total) {
5242                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5243                 stat->subslice_total = stat->slice_total *
5244                                        stat->subslice_per_slice;
5245                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5246                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5247
5248                 /* subtract fused off EU(s) from enabled slice(s) */
5249                 for (s = 0; s < stat->slice_total; s++) {
5250                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5251
5252                         stat->eu_total -= hweight8(subslice_7eu);
5253                 }
5254         }
5255 }
5256
5257 static int i915_sseu_status(struct seq_file *m, void *unused)
5258 {
5259         struct drm_info_node *node = (struct drm_info_node *) m->private;
5260         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5261         struct drm_device *dev = &dev_priv->drm;
5262         struct sseu_dev_status stat;
5263
5264         if (INTEL_INFO(dev)->gen < 8)
5265                 return -ENODEV;
5266
5267         seq_puts(m, "SSEU Device Info\n");
5268         seq_printf(m, "  Available Slice Total: %u\n",
5269                    INTEL_INFO(dev)->slice_total);
5270         seq_printf(m, "  Available Subslice Total: %u\n",
5271                    INTEL_INFO(dev)->subslice_total);
5272         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5273                    INTEL_INFO(dev)->subslice_per_slice);
5274         seq_printf(m, "  Available EU Total: %u\n",
5275                    INTEL_INFO(dev)->eu_total);
5276         seq_printf(m, "  Available EU Per Subslice: %u\n",
5277                    INTEL_INFO(dev)->eu_per_subslice);
5278         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5279         if (HAS_POOLED_EU(dev))
5280                 seq_printf(m, "  Min EU in pool: %u\n",
5281                            INTEL_INFO(dev)->min_eu_in_pool);
5282         seq_printf(m, "  Has Slice Power Gating: %s\n",
5283                    yesno(INTEL_INFO(dev)->has_slice_pg));
5284         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5285                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5286         seq_printf(m, "  Has EU Power Gating: %s\n",
5287                    yesno(INTEL_INFO(dev)->has_eu_pg));
5288
5289         seq_puts(m, "SSEU Device Status\n");
5290         memset(&stat, 0, sizeof(stat));
5291
5292         intel_runtime_pm_get(dev_priv);
5293
5294         if (IS_CHERRYVIEW(dev)) {
5295                 cherryview_sseu_device_status(dev, &stat);
5296         } else if (IS_BROADWELL(dev)) {
5297                 broadwell_sseu_device_status(dev, &stat);
5298         } else if (INTEL_INFO(dev)->gen >= 9) {
5299                 gen9_sseu_device_status(dev, &stat);
5300         }
5301
5302         intel_runtime_pm_put(dev_priv);
5303
5304         seq_printf(m, "  Enabled Slice Total: %u\n",
5305                    stat.slice_total);
5306         seq_printf(m, "  Enabled Subslice Total: %u\n",
5307                    stat.subslice_total);
5308         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5309                    stat.subslice_per_slice);
5310         seq_printf(m, "  Enabled EU Total: %u\n",
5311                    stat.eu_total);
5312         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5313                    stat.eu_per_subslice);
5314
5315         return 0;
5316 }
5317
5318 static int i915_forcewake_open(struct inode *inode, struct file *file)
5319 {
5320         struct drm_device *dev = inode->i_private;
5321         struct drm_i915_private *dev_priv = to_i915(dev);
5322
5323         if (INTEL_INFO(dev)->gen < 6)
5324                 return 0;
5325
5326         intel_runtime_pm_get(dev_priv);
5327         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5328
5329         return 0;
5330 }
5331
5332 static int i915_forcewake_release(struct inode *inode, struct file *file)
5333 {
5334         struct drm_device *dev = inode->i_private;
5335         struct drm_i915_private *dev_priv = to_i915(dev);
5336
5337         if (INTEL_INFO(dev)->gen < 6)
5338                 return 0;
5339
5340         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5341         intel_runtime_pm_put(dev_priv);
5342
5343         return 0;
5344 }
5345
5346 static const struct file_operations i915_forcewake_fops = {
5347         .owner = THIS_MODULE,
5348         .open = i915_forcewake_open,
5349         .release = i915_forcewake_release,
5350 };
5351
5352 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5353 {
5354         struct drm_device *dev = minor->dev;
5355         struct dentry *ent;
5356
5357         ent = debugfs_create_file("i915_forcewake_user",
5358                                   S_IRUSR,
5359                                   root, dev,
5360                                   &i915_forcewake_fops);
5361         if (!ent)
5362                 return -ENOMEM;
5363
5364         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5365 }
5366
5367 static int i915_debugfs_create(struct dentry *root,
5368                                struct drm_minor *minor,
5369                                const char *name,
5370                                const struct file_operations *fops)
5371 {
5372         struct drm_device *dev = minor->dev;
5373         struct dentry *ent;
5374
5375         ent = debugfs_create_file(name,
5376                                   S_IRUGO | S_IWUSR,
5377                                   root, dev,
5378                                   fops);
5379         if (!ent)
5380                 return -ENOMEM;
5381
5382         return drm_add_fake_info_node(minor, ent, fops);
5383 }
5384
5385 static const struct drm_info_list i915_debugfs_list[] = {
5386         {"i915_capabilities", i915_capabilities, 0},
5387         {"i915_gem_objects", i915_gem_object_info, 0},
5388         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5389         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5390         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5391         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5392         {"i915_gem_stolen", i915_gem_stolen_list_info },
5393         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5394         {"i915_gem_request", i915_gem_request_info, 0},
5395         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5396         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5397         {"i915_gem_interrupt", i915_interrupt_info, 0},
5398         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5399         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5400         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5401         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5402         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5403         {"i915_guc_info", i915_guc_info, 0},
5404         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5405         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5406         {"i915_frequency_info", i915_frequency_info, 0},
5407         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5408         {"i915_drpc_info", i915_drpc_info, 0},
5409         {"i915_emon_status", i915_emon_status, 0},
5410         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5411         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5412         {"i915_fbc_status", i915_fbc_status, 0},
5413         {"i915_ips_status", i915_ips_status, 0},
5414         {"i915_sr_status", i915_sr_status, 0},
5415         {"i915_opregion", i915_opregion, 0},
5416         {"i915_vbt", i915_vbt, 0},
5417         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5418         {"i915_context_status", i915_context_status, 0},
5419         {"i915_dump_lrc", i915_dump_lrc, 0},
5420         {"i915_execlists", i915_execlists, 0},
5421         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5422         {"i915_swizzle_info", i915_swizzle_info, 0},
5423         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5424         {"i915_llc", i915_llc, 0},
5425         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5426         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5427         {"i915_energy_uJ", i915_energy_uJ, 0},
5428         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5429         {"i915_power_domain_info", i915_power_domain_info, 0},
5430         {"i915_dmc_info", i915_dmc_info, 0},
5431         {"i915_display_info", i915_display_info, 0},
5432         {"i915_semaphore_status", i915_semaphore_status, 0},
5433         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5434         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5435         {"i915_wa_registers", i915_wa_registers, 0},
5436         {"i915_ddb_info", i915_ddb_info, 0},
5437         {"i915_sseu_status", i915_sseu_status, 0},
5438         {"i915_drrs_status", i915_drrs_status, 0},
5439         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5440 };
5441 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5442
5443 static const struct i915_debugfs_files {
5444         const char *name;
5445         const struct file_operations *fops;
5446 } i915_debugfs_files[] = {
5447         {"i915_wedged", &i915_wedged_fops},
5448         {"i915_max_freq", &i915_max_freq_fops},
5449         {"i915_min_freq", &i915_min_freq_fops},
5450         {"i915_cache_sharing", &i915_cache_sharing_fops},
5451         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5452         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5453         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5454         {"i915_error_state", &i915_error_state_fops},
5455         {"i915_next_seqno", &i915_next_seqno_fops},
5456         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5457         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5458         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5459         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5460         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5461         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5462         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5463         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5464 };
5465
5466 void intel_display_crc_init(struct drm_device *dev)
5467 {
5468         struct drm_i915_private *dev_priv = to_i915(dev);
5469         enum pipe pipe;
5470
5471         for_each_pipe(dev_priv, pipe) {
5472                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5473
5474                 pipe_crc->opened = false;
5475                 spin_lock_init(&pipe_crc->lock);
5476                 init_waitqueue_head(&pipe_crc->wq);
5477         }
5478 }
5479
5480 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5481 {
5482         struct drm_minor *minor = dev_priv->drm.primary;
5483         int ret, i;
5484
5485         ret = i915_forcewake_create(minor->debugfs_root, minor);
5486         if (ret)
5487                 return ret;
5488
5489         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5490                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5491                 if (ret)
5492                         return ret;
5493         }
5494
5495         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5496                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5497                                           i915_debugfs_files[i].name,
5498                                           i915_debugfs_files[i].fops);
5499                 if (ret)
5500                         return ret;
5501         }
5502
5503         return drm_debugfs_create_files(i915_debugfs_list,
5504                                         I915_DEBUGFS_ENTRIES,
5505                                         minor->debugfs_root, minor);
5506 }
5507
5508 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5509 {
5510         struct drm_minor *minor = dev_priv->drm.primary;
5511         int i;
5512
5513         drm_debugfs_remove_files(i915_debugfs_list,
5514                                  I915_DEBUGFS_ENTRIES, minor);
5515
5516         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5517                                  1, minor);
5518
5519         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5520                 struct drm_info_list *info_list =
5521                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5522
5523                 drm_debugfs_remove_files(info_list, 1, minor);
5524         }
5525
5526         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5527                 struct drm_info_list *info_list =
5528                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5529
5530                 drm_debugfs_remove_files(info_list, 1, minor);
5531         }
5532 }
5533
5534 struct dpcd_block {
5535         /* DPCD dump start address. */
5536         unsigned int offset;
5537         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5538         unsigned int end;
5539         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5540         size_t size;
5541         /* Only valid for eDP. */
5542         bool edp;
5543 };
5544
5545 static const struct dpcd_block i915_dpcd_debug[] = {
5546         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5547         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5548         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5549         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5550         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5551         { .offset = DP_SET_POWER },
5552         { .offset = DP_EDP_DPCD_REV },
5553         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5554         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5555         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5556 };
5557
5558 static int i915_dpcd_show(struct seq_file *m, void *data)
5559 {
5560         struct drm_connector *connector = m->private;
5561         struct intel_dp *intel_dp =
5562                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5563         uint8_t buf[16];
5564         ssize_t err;
5565         int i;
5566
5567         if (connector->status != connector_status_connected)
5568                 return -ENODEV;
5569
5570         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5571                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5572                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5573
5574                 if (b->edp &&
5575                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5576                         continue;
5577
5578                 /* low tech for now */
5579                 if (WARN_ON(size > sizeof(buf)))
5580                         continue;
5581
5582                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5583                 if (err <= 0) {
5584                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5585                                   size, b->offset, err);
5586                         continue;
5587                 }
5588
5589                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5590         }
5591
5592         return 0;
5593 }
5594
5595 static int i915_dpcd_open(struct inode *inode, struct file *file)
5596 {
5597         return single_open(file, i915_dpcd_show, inode->i_private);
5598 }
5599
5600 static const struct file_operations i915_dpcd_fops = {
5601         .owner = THIS_MODULE,
5602         .open = i915_dpcd_open,
5603         .read = seq_read,
5604         .llseek = seq_lseek,
5605         .release = single_release,
5606 };
5607
5608 /**
5609  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5610  * @connector: pointer to a registered drm_connector
5611  *
5612  * Cleanup will be done by drm_connector_unregister() through a call to
5613  * drm_debugfs_connector_remove().
5614  *
5615  * Returns 0 on success, negative error codes on error.
5616  */
5617 int i915_debugfs_connector_add(struct drm_connector *connector)
5618 {
5619         struct dentry *root = connector->debugfs_entry;
5620
5621         /* The connector must have been registered beforehands. */
5622         if (!root)
5623                 return -ENODEV;
5624
5625         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5626             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5627                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5628                                     &i915_dpcd_fops);
5629
5630         return 0;
5631 }