2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/debugfs.h>
30 #include <linux/sort.h>
31 #include <linux/sched/mm.h>
32 #include "intel_drv.h"
33 #include "intel_guc_submission.h"
35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
37 return to_i915(node->minor->dev);
40 static int i915_capabilities(struct seq_file *m, void *data)
42 struct drm_i915_private *dev_priv = node_to_i915(m->private);
43 const struct intel_device_info *info = INTEL_INFO(dev_priv);
44 struct drm_printer p = drm_seq_file_printer(m);
46 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
47 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
48 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
50 intel_device_info_dump_flags(info, &p);
51 intel_device_info_dump_runtime(info, &p);
52 intel_driver_caps_print(&dev_priv->caps, &p);
54 kernel_param_lock(THIS_MODULE);
55 i915_params_dump(&i915_modparams, &p);
56 kernel_param_unlock(THIS_MODULE);
61 static char get_active_flag(struct drm_i915_gem_object *obj)
63 return i915_gem_object_is_active(obj) ? '*' : ' ';
66 static char get_pin_flag(struct drm_i915_gem_object *obj)
68 return obj->pin_global ? 'p' : ' ';
71 static char get_tiling_flag(struct drm_i915_gem_object *obj)
73 switch (i915_gem_object_get_tiling(obj)) {
75 case I915_TILING_NONE: return ' ';
76 case I915_TILING_X: return 'X';
77 case I915_TILING_Y: return 'Y';
81 static char get_global_flag(struct drm_i915_gem_object *obj)
83 return obj->userfault_count ? 'g' : ' ';
86 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
88 return obj->mm.mapping ? 'M' : ' ';
91 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
96 for_each_ggtt_vma(vma, obj) {
97 if (drm_mm_node_allocated(&vma->node))
98 size += vma->node.size;
105 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
109 switch (page_sizes) {
112 case I915_GTT_PAGE_SIZE_4K:
114 case I915_GTT_PAGE_SIZE_64K:
116 case I915_GTT_PAGE_SIZE_2M:
122 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
123 x += snprintf(buf + x, len - x, "2M, ");
124 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
125 x += snprintf(buf + x, len - x, "64K, ");
126 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
127 x += snprintf(buf + x, len - x, "4K, ");
135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
138 struct intel_engine_cs *engine;
139 struct i915_vma *vma;
140 unsigned int frontbuffer_bits;
143 lockdep_assert_held(&obj->base.dev->struct_mutex);
145 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
147 get_active_flag(obj),
149 get_tiling_flag(obj),
150 get_global_flag(obj),
151 get_pin_mapped_flag(obj),
152 obj->base.size / 1024,
155 i915_cache_level_str(dev_priv, obj->cache_level),
156 obj->mm.dirty ? " dirty" : "",
157 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
159 seq_printf(m, " (name: %d)", obj->base.name);
160 list_for_each_entry(vma, &obj->vma_list, obj_link) {
161 if (i915_vma_is_pinned(vma))
164 seq_printf(m, " (pinned x %d)", pin_count);
166 seq_printf(m, " (global)");
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (!drm_mm_node_allocated(&vma->node))
171 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
172 i915_vma_is_ggtt(vma) ? "g" : "pp",
173 vma->node.start, vma->node.size,
174 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
175 if (i915_vma_is_ggtt(vma)) {
176 switch (vma->ggtt_view.type) {
177 case I915_GGTT_VIEW_NORMAL:
178 seq_puts(m, ", normal");
181 case I915_GGTT_VIEW_PARTIAL:
182 seq_printf(m, ", partial [%08llx+%x]",
183 vma->ggtt_view.partial.offset << PAGE_SHIFT,
184 vma->ggtt_view.partial.size << PAGE_SHIFT);
187 case I915_GGTT_VIEW_ROTATED:
188 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
189 vma->ggtt_view.rotated.plane[0].width,
190 vma->ggtt_view.rotated.plane[0].height,
191 vma->ggtt_view.rotated.plane[0].stride,
192 vma->ggtt_view.rotated.plane[0].offset,
193 vma->ggtt_view.rotated.plane[1].width,
194 vma->ggtt_view.rotated.plane[1].height,
195 vma->ggtt_view.rotated.plane[1].stride,
196 vma->ggtt_view.rotated.plane[1].offset);
200 MISSING_CASE(vma->ggtt_view.type);
205 seq_printf(m, " , fence: %d%s",
207 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
211 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
213 engine = i915_gem_object_last_write_engine(obj);
215 seq_printf(m, " (%s)", engine->name);
217 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
218 if (frontbuffer_bits)
219 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
222 static int obj_rank_by_stolen(const void *A, const void *B)
224 const struct drm_i915_gem_object *a =
225 *(const struct drm_i915_gem_object **)A;
226 const struct drm_i915_gem_object *b =
227 *(const struct drm_i915_gem_object **)B;
229 if (a->stolen->start < b->stolen->start)
231 if (a->stolen->start > b->stolen->start)
236 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
238 struct drm_i915_private *dev_priv = node_to_i915(m->private);
239 struct drm_device *dev = &dev_priv->drm;
240 struct drm_i915_gem_object **objects;
241 struct drm_i915_gem_object *obj;
242 u64 total_obj_size, total_gtt_size;
243 unsigned long total, count, n;
246 total = READ_ONCE(dev_priv->mm.object_count);
247 objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
251 ret = mutex_lock_interruptible(&dev->struct_mutex);
255 total_obj_size = total_gtt_size = count = 0;
257 spin_lock(&dev_priv->mm.obj_lock);
258 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
262 if (obj->stolen == NULL)
265 objects[count++] = obj;
266 total_obj_size += obj->base.size;
267 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
270 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
274 if (obj->stolen == NULL)
277 objects[count++] = obj;
278 total_obj_size += obj->base.size;
280 spin_unlock(&dev_priv->mm.obj_lock);
282 sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
284 seq_puts(m, "Stolen:\n");
285 for (n = 0; n < count; n++) {
287 describe_obj(m, objects[n]);
290 seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
291 count, total_obj_size, total_gtt_size);
293 mutex_unlock(&dev->struct_mutex);
300 struct drm_i915_file_private *file_priv;
304 u64 active, inactive;
307 static int per_file_stats(int id, void *ptr, void *data)
309 struct drm_i915_gem_object *obj = ptr;
310 struct file_stats *stats = data;
311 struct i915_vma *vma;
313 lockdep_assert_held(&obj->base.dev->struct_mutex);
316 stats->total += obj->base.size;
317 if (!obj->bind_count)
318 stats->unbound += obj->base.size;
319 if (obj->base.name || obj->base.dma_buf)
320 stats->shared += obj->base.size;
322 list_for_each_entry(vma, &obj->vma_list, obj_link) {
323 if (!drm_mm_node_allocated(&vma->node))
326 if (i915_vma_is_ggtt(vma)) {
327 stats->global += vma->node.size;
329 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
331 if (ppgtt->base.file != stats->file_priv)
335 if (i915_vma_is_active(vma))
336 stats->active += vma->node.size;
338 stats->inactive += vma->node.size;
344 #define print_file_stats(m, name, stats) do { \
346 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
357 static void print_batch_pool_stats(struct seq_file *m,
358 struct drm_i915_private *dev_priv)
360 struct drm_i915_gem_object *obj;
361 struct file_stats stats;
362 struct intel_engine_cs *engine;
363 enum intel_engine_id id;
366 memset(&stats, 0, sizeof(stats));
368 for_each_engine(engine, dev_priv, id) {
369 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
370 list_for_each_entry(obj,
371 &engine->batch_pool.cache_list[j],
373 per_file_stats(0, obj, &stats);
377 print_file_stats(m, "[k]batch pool", stats);
380 static int per_file_ctx_stats(int id, void *ptr, void *data)
382 struct i915_gem_context *ctx = ptr;
385 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
386 if (ctx->engine[n].state)
387 per_file_stats(0, ctx->engine[n].state->obj, data);
388 if (ctx->engine[n].ring)
389 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
395 static void print_context_stats(struct seq_file *m,
396 struct drm_i915_private *dev_priv)
398 struct drm_device *dev = &dev_priv->drm;
399 struct file_stats stats;
400 struct drm_file *file;
402 memset(&stats, 0, sizeof(stats));
404 mutex_lock(&dev->struct_mutex);
405 if (dev_priv->kernel_context)
406 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
408 list_for_each_entry(file, &dev->filelist, lhead) {
409 struct drm_i915_file_private *fpriv = file->driver_priv;
410 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
412 mutex_unlock(&dev->struct_mutex);
414 print_file_stats(m, "[k]contexts", stats);
417 static int i915_gem_object_info(struct seq_file *m, void *data)
419 struct drm_i915_private *dev_priv = node_to_i915(m->private);
420 struct drm_device *dev = &dev_priv->drm;
421 struct i915_ggtt *ggtt = &dev_priv->ggtt;
422 u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
423 u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
424 struct drm_i915_gem_object *obj;
425 unsigned int page_sizes = 0;
426 struct drm_file *file;
430 ret = mutex_lock_interruptible(&dev->struct_mutex);
434 seq_printf(m, "%u objects, %llu bytes\n",
435 dev_priv->mm.object_count,
436 dev_priv->mm.object_memory);
439 mapped_size = mapped_count = 0;
440 purgeable_size = purgeable_count = 0;
441 huge_size = huge_count = 0;
443 spin_lock(&dev_priv->mm.obj_lock);
444 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
445 size += obj->base.size;
448 if (obj->mm.madv == I915_MADV_DONTNEED) {
449 purgeable_size += obj->base.size;
453 if (obj->mm.mapping) {
455 mapped_size += obj->base.size;
458 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
460 huge_size += obj->base.size;
461 page_sizes |= obj->mm.page_sizes.sg;
464 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
466 size = count = dpy_size = dpy_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
468 size += obj->base.size;
471 if (obj->pin_global) {
472 dpy_size += obj->base.size;
476 if (obj->mm.madv == I915_MADV_DONTNEED) {
477 purgeable_size += obj->base.size;
481 if (obj->mm.mapping) {
483 mapped_size += obj->base.size;
486 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
488 huge_size += obj->base.size;
489 page_sizes |= obj->mm.page_sizes.sg;
492 spin_unlock(&dev_priv->mm.obj_lock);
494 seq_printf(m, "%u bound objects, %llu bytes\n",
496 seq_printf(m, "%u purgeable objects, %llu bytes\n",
497 purgeable_count, purgeable_size);
498 seq_printf(m, "%u mapped objects, %llu bytes\n",
499 mapped_count, mapped_size);
500 seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
502 stringify_page_sizes(page_sizes, buf, sizeof(buf)),
504 seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
505 dpy_count, dpy_size);
507 seq_printf(m, "%llu [%pa] gtt total\n",
508 ggtt->base.total, &ggtt->mappable_end);
509 seq_printf(m, "Supported page sizes: %s\n",
510 stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
514 print_batch_pool_stats(m, dev_priv);
515 mutex_unlock(&dev->struct_mutex);
517 mutex_lock(&dev->filelist_mutex);
518 print_context_stats(m, dev_priv);
519 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
520 struct file_stats stats;
521 struct drm_i915_file_private *file_priv = file->driver_priv;
522 struct i915_request *request;
523 struct task_struct *task;
525 mutex_lock(&dev->struct_mutex);
527 memset(&stats, 0, sizeof(stats));
528 stats.file_priv = file->driver_priv;
529 spin_lock(&file->table_lock);
530 idr_for_each(&file->object_idr, per_file_stats, &stats);
531 spin_unlock(&file->table_lock);
533 * Although we have a valid reference on file->pid, that does
534 * not guarantee that the task_struct who called get_pid() is
535 * still alive (e.g. get_pid(current) => fork() => exit()).
536 * Therefore, we need to protect this ->comm access using RCU.
538 request = list_first_entry_or_null(&file_priv->mm.request_list,
542 task = pid_task(request && request->ctx->pid ?
543 request->ctx->pid : file->pid,
545 print_file_stats(m, task ? task->comm : "<unknown>", stats);
548 mutex_unlock(&dev->struct_mutex);
550 mutex_unlock(&dev->filelist_mutex);
555 static int i915_gem_gtt_info(struct seq_file *m, void *data)
557 struct drm_info_node *node = m->private;
558 struct drm_i915_private *dev_priv = node_to_i915(node);
559 struct drm_device *dev = &dev_priv->drm;
560 struct drm_i915_gem_object **objects;
561 struct drm_i915_gem_object *obj;
562 u64 total_obj_size, total_gtt_size;
563 unsigned long nobject, n;
566 nobject = READ_ONCE(dev_priv->mm.object_count);
567 objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
576 spin_lock(&dev_priv->mm.obj_lock);
577 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
578 objects[count++] = obj;
579 if (count == nobject)
582 spin_unlock(&dev_priv->mm.obj_lock);
584 total_obj_size = total_gtt_size = 0;
585 for (n = 0; n < count; n++) {
589 describe_obj(m, obj);
591 total_obj_size += obj->base.size;
592 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
595 mutex_unlock(&dev->struct_mutex);
597 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
598 count, total_obj_size, total_gtt_size);
604 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
606 struct drm_i915_private *dev_priv = node_to_i915(m->private);
607 struct drm_device *dev = &dev_priv->drm;
608 struct drm_i915_gem_object *obj;
609 struct intel_engine_cs *engine;
610 enum intel_engine_id id;
614 ret = mutex_lock_interruptible(&dev->struct_mutex);
618 for_each_engine(engine, dev_priv, id) {
619 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
623 list_for_each_entry(obj,
624 &engine->batch_pool.cache_list[j],
627 seq_printf(m, "%s cache[%d]: %d objects\n",
628 engine->name, j, count);
630 list_for_each_entry(obj,
631 &engine->batch_pool.cache_list[j],
634 describe_obj(m, obj);
642 seq_printf(m, "total: %d\n", total);
644 mutex_unlock(&dev->struct_mutex);
649 static void gen8_display_interrupt_info(struct seq_file *m)
651 struct drm_i915_private *dev_priv = node_to_i915(m->private);
654 for_each_pipe(dev_priv, pipe) {
655 enum intel_display_power_domain power_domain;
657 power_domain = POWER_DOMAIN_PIPE(pipe);
658 if (!intel_display_power_get_if_enabled(dev_priv,
660 seq_printf(m, "Pipe %c power disabled\n",
664 seq_printf(m, "Pipe %c IMR:\t%08x\n",
666 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
667 seq_printf(m, "Pipe %c IIR:\t%08x\n",
669 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
670 seq_printf(m, "Pipe %c IER:\t%08x\n",
672 I915_READ(GEN8_DE_PIPE_IER(pipe)));
674 intel_display_power_put(dev_priv, power_domain);
677 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
678 I915_READ(GEN8_DE_PORT_IMR));
679 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
680 I915_READ(GEN8_DE_PORT_IIR));
681 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
682 I915_READ(GEN8_DE_PORT_IER));
684 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
685 I915_READ(GEN8_DE_MISC_IMR));
686 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
687 I915_READ(GEN8_DE_MISC_IIR));
688 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
689 I915_READ(GEN8_DE_MISC_IER));
691 seq_printf(m, "PCU interrupt mask:\t%08x\n",
692 I915_READ(GEN8_PCU_IMR));
693 seq_printf(m, "PCU interrupt identity:\t%08x\n",
694 I915_READ(GEN8_PCU_IIR));
695 seq_printf(m, "PCU interrupt enable:\t%08x\n",
696 I915_READ(GEN8_PCU_IER));
699 static int i915_interrupt_info(struct seq_file *m, void *data)
701 struct drm_i915_private *dev_priv = node_to_i915(m->private);
702 struct intel_engine_cs *engine;
703 enum intel_engine_id id;
706 intel_runtime_pm_get(dev_priv);
708 if (IS_CHERRYVIEW(dev_priv)) {
709 seq_printf(m, "Master Interrupt Control:\t%08x\n",
710 I915_READ(GEN8_MASTER_IRQ));
712 seq_printf(m, "Display IER:\t%08x\n",
714 seq_printf(m, "Display IIR:\t%08x\n",
716 seq_printf(m, "Display IIR_RW:\t%08x\n",
717 I915_READ(VLV_IIR_RW));
718 seq_printf(m, "Display IMR:\t%08x\n",
720 for_each_pipe(dev_priv, pipe) {
721 enum intel_display_power_domain power_domain;
723 power_domain = POWER_DOMAIN_PIPE(pipe);
724 if (!intel_display_power_get_if_enabled(dev_priv,
726 seq_printf(m, "Pipe %c power disabled\n",
731 seq_printf(m, "Pipe %c stat:\t%08x\n",
733 I915_READ(PIPESTAT(pipe)));
735 intel_display_power_put(dev_priv, power_domain);
738 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
739 seq_printf(m, "Port hotplug:\t%08x\n",
740 I915_READ(PORT_HOTPLUG_EN));
741 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
742 I915_READ(VLV_DPFLIPSTAT));
743 seq_printf(m, "DPINVGTT:\t%08x\n",
744 I915_READ(DPINVGTT));
745 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
747 for (i = 0; i < 4; i++) {
748 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
749 i, I915_READ(GEN8_GT_IMR(i)));
750 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
751 i, I915_READ(GEN8_GT_IIR(i)));
752 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
753 i, I915_READ(GEN8_GT_IER(i)));
756 seq_printf(m, "PCU interrupt mask:\t%08x\n",
757 I915_READ(GEN8_PCU_IMR));
758 seq_printf(m, "PCU interrupt identity:\t%08x\n",
759 I915_READ(GEN8_PCU_IIR));
760 seq_printf(m, "PCU interrupt enable:\t%08x\n",
761 I915_READ(GEN8_PCU_IER));
762 } else if (INTEL_GEN(dev_priv) >= 11) {
763 seq_printf(m, "Master Interrupt Control: %08x\n",
764 I915_READ(GEN11_GFX_MSTR_IRQ));
766 seq_printf(m, "Render/Copy Intr Enable: %08x\n",
767 I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
768 seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
769 I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
770 seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
771 I915_READ(GEN11_GUC_SG_INTR_ENABLE));
772 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
773 I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
774 seq_printf(m, "Crypto Intr Enable:\t %08x\n",
775 I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
776 seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
777 I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
779 seq_printf(m, "Display Interrupt Control:\t%08x\n",
780 I915_READ(GEN11_DISPLAY_INT_CTL));
782 gen8_display_interrupt_info(m);
783 } else if (INTEL_GEN(dev_priv) >= 8) {
784 seq_printf(m, "Master Interrupt Control:\t%08x\n",
785 I915_READ(GEN8_MASTER_IRQ));
787 for (i = 0; i < 4; i++) {
788 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
789 i, I915_READ(GEN8_GT_IMR(i)));
790 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
791 i, I915_READ(GEN8_GT_IIR(i)));
792 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
793 i, I915_READ(GEN8_GT_IER(i)));
796 gen8_display_interrupt_info(m);
797 } else if (IS_VALLEYVIEW(dev_priv)) {
798 seq_printf(m, "Display IER:\t%08x\n",
800 seq_printf(m, "Display IIR:\t%08x\n",
802 seq_printf(m, "Display IIR_RW:\t%08x\n",
803 I915_READ(VLV_IIR_RW));
804 seq_printf(m, "Display IMR:\t%08x\n",
806 for_each_pipe(dev_priv, pipe) {
807 enum intel_display_power_domain power_domain;
809 power_domain = POWER_DOMAIN_PIPE(pipe);
810 if (!intel_display_power_get_if_enabled(dev_priv,
812 seq_printf(m, "Pipe %c power disabled\n",
817 seq_printf(m, "Pipe %c stat:\t%08x\n",
819 I915_READ(PIPESTAT(pipe)));
820 intel_display_power_put(dev_priv, power_domain);
823 seq_printf(m, "Master IER:\t%08x\n",
824 I915_READ(VLV_MASTER_IER));
826 seq_printf(m, "Render IER:\t%08x\n",
828 seq_printf(m, "Render IIR:\t%08x\n",
830 seq_printf(m, "Render IMR:\t%08x\n",
833 seq_printf(m, "PM IER:\t\t%08x\n",
834 I915_READ(GEN6_PMIER));
835 seq_printf(m, "PM IIR:\t\t%08x\n",
836 I915_READ(GEN6_PMIIR));
837 seq_printf(m, "PM IMR:\t\t%08x\n",
838 I915_READ(GEN6_PMIMR));
840 seq_printf(m, "Port hotplug:\t%08x\n",
841 I915_READ(PORT_HOTPLUG_EN));
842 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
843 I915_READ(VLV_DPFLIPSTAT));
844 seq_printf(m, "DPINVGTT:\t%08x\n",
845 I915_READ(DPINVGTT));
847 } else if (!HAS_PCH_SPLIT(dev_priv)) {
848 seq_printf(m, "Interrupt enable: %08x\n",
850 seq_printf(m, "Interrupt identity: %08x\n",
852 seq_printf(m, "Interrupt mask: %08x\n",
854 for_each_pipe(dev_priv, pipe)
855 seq_printf(m, "Pipe %c stat: %08x\n",
857 I915_READ(PIPESTAT(pipe)));
859 seq_printf(m, "North Display Interrupt enable: %08x\n",
861 seq_printf(m, "North Display Interrupt identity: %08x\n",
863 seq_printf(m, "North Display Interrupt mask: %08x\n",
865 seq_printf(m, "South Display Interrupt enable: %08x\n",
867 seq_printf(m, "South Display Interrupt identity: %08x\n",
869 seq_printf(m, "South Display Interrupt mask: %08x\n",
871 seq_printf(m, "Graphics Interrupt enable: %08x\n",
873 seq_printf(m, "Graphics Interrupt identity: %08x\n",
875 seq_printf(m, "Graphics Interrupt mask: %08x\n",
879 if (INTEL_GEN(dev_priv) >= 11) {
880 seq_printf(m, "RCS Intr Mask:\t %08x\n",
881 I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
882 seq_printf(m, "BCS Intr Mask:\t %08x\n",
883 I915_READ(GEN11_BCS_RSVD_INTR_MASK));
884 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
885 I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
886 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
887 I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
888 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
889 I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
890 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
891 I915_READ(GEN11_GUC_SG_INTR_MASK));
892 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
893 I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
894 seq_printf(m, "Crypto Intr Mask:\t %08x\n",
895 I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
896 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
897 I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
899 } else if (INTEL_GEN(dev_priv) >= 6) {
900 for_each_engine(engine, dev_priv, id) {
902 "Graphics Interrupt mask (%s): %08x\n",
903 engine->name, I915_READ_IMR(engine));
907 intel_runtime_pm_put(dev_priv);
912 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
914 struct drm_i915_private *dev_priv = node_to_i915(m->private);
915 struct drm_device *dev = &dev_priv->drm;
918 ret = mutex_lock_interruptible(&dev->struct_mutex);
922 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
923 for (i = 0; i < dev_priv->num_fence_regs; i++) {
924 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
926 seq_printf(m, "Fence %d, pin count = %d, object = ",
927 i, dev_priv->fence_regs[i].pin_count);
929 seq_puts(m, "unused");
931 describe_obj(m, vma->obj);
935 mutex_unlock(&dev->struct_mutex);
939 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
940 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
941 size_t count, loff_t *pos)
943 struct i915_gpu_state *error = file->private_data;
944 struct drm_i915_error_state_buf str;
951 ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
955 ret = i915_error_state_to_str(&str, error);
960 ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
964 *pos = str.start + ret;
966 i915_error_state_buf_release(&str);
970 static int gpu_state_release(struct inode *inode, struct file *file)
972 i915_gpu_state_put(file->private_data);
976 static int i915_gpu_info_open(struct inode *inode, struct file *file)
978 struct drm_i915_private *i915 = inode->i_private;
979 struct i915_gpu_state *gpu;
981 intel_runtime_pm_get(i915);
982 gpu = i915_capture_gpu_state(i915);
983 intel_runtime_pm_put(i915);
987 file->private_data = gpu;
991 static const struct file_operations i915_gpu_info_fops = {
992 .owner = THIS_MODULE,
993 .open = i915_gpu_info_open,
994 .read = gpu_state_read,
995 .llseek = default_llseek,
996 .release = gpu_state_release,
1000 i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1005 struct i915_gpu_state *error = filp->private_data;
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011 i915_reset_error_state(error->i915);
1016 static int i915_error_state_open(struct inode *inode, struct file *file)
1018 file->private_data = i915_first_error_state(inode->i_private);
1022 static const struct file_operations i915_error_state_fops = {
1023 .owner = THIS_MODULE,
1024 .open = i915_error_state_open,
1025 .read = gpu_state_read,
1026 .write = i915_error_state_write,
1027 .llseek = default_llseek,
1028 .release = gpu_state_release,
1033 i915_next_seqno_set(void *data, u64 val)
1035 struct drm_i915_private *dev_priv = data;
1036 struct drm_device *dev = &dev_priv->drm;
1039 ret = mutex_lock_interruptible(&dev->struct_mutex);
1043 intel_runtime_pm_get(dev_priv);
1044 ret = i915_gem_set_global_seqno(dev, val);
1045 intel_runtime_pm_put(dev_priv);
1047 mutex_unlock(&dev->struct_mutex);
1052 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1053 NULL, i915_next_seqno_set,
1056 static int i915_frequency_info(struct seq_file *m, void *unused)
1058 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1059 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1062 intel_runtime_pm_get(dev_priv);
1064 if (IS_GEN5(dev_priv)) {
1065 u16 rgvswctl = I915_READ16(MEMSWCTL);
1066 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1068 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1069 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1070 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1072 seq_printf(m, "Current P-state: %d\n",
1073 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1074 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1075 u32 rpmodectl, freq_sts;
1077 mutex_lock(&dev_priv->pcu_lock);
1079 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1080 seq_printf(m, "Video Turbo Mode: %s\n",
1081 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1082 seq_printf(m, "HW control enabled: %s\n",
1083 yesno(rpmodectl & GEN6_RP_ENABLE));
1084 seq_printf(m, "SW control enabled: %s\n",
1085 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1086 GEN6_RP_MEDIA_SW_MODE));
1088 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1089 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1090 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1092 seq_printf(m, "actual GPU freq: %d MHz\n",
1093 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1095 seq_printf(m, "current GPU freq: %d MHz\n",
1096 intel_gpu_freq(dev_priv, rps->cur_freq));
1098 seq_printf(m, "max GPU freq: %d MHz\n",
1099 intel_gpu_freq(dev_priv, rps->max_freq));
1101 seq_printf(m, "min GPU freq: %d MHz\n",
1102 intel_gpu_freq(dev_priv, rps->min_freq));
1104 seq_printf(m, "idle GPU freq: %d MHz\n",
1105 intel_gpu_freq(dev_priv, rps->idle_freq));
1108 "efficient (RPe) frequency: %d MHz\n",
1109 intel_gpu_freq(dev_priv, rps->efficient_freq));
1110 mutex_unlock(&dev_priv->pcu_lock);
1111 } else if (INTEL_GEN(dev_priv) >= 6) {
1112 u32 rp_state_limits;
1115 u32 rpmodectl, rpinclimit, rpdeclimit;
1116 u32 rpstat, cagf, reqf;
1117 u32 rpupei, rpcurup, rpprevup;
1118 u32 rpdownei, rpcurdown, rpprevdown;
1119 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1122 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1123 if (IS_GEN9_LP(dev_priv)) {
1124 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1125 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1127 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1128 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1131 /* RPSTAT1 is in the GT power well */
1132 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1134 reqf = I915_READ(GEN6_RPNSWREQ);
1135 if (INTEL_GEN(dev_priv) >= 9)
1138 reqf &= ~GEN6_TURBO_DISABLE;
1139 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1144 reqf = intel_gpu_freq(dev_priv, reqf);
1146 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1147 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1148 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1150 rpstat = I915_READ(GEN6_RPSTAT1);
1151 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1152 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1153 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1154 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1155 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1156 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1157 cagf = intel_gpu_freq(dev_priv,
1158 intel_get_cagf(dev_priv, rpstat));
1160 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1162 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1163 pm_ier = I915_READ(GEN6_PMIER);
1164 pm_imr = I915_READ(GEN6_PMIMR);
1165 pm_isr = I915_READ(GEN6_PMISR);
1166 pm_iir = I915_READ(GEN6_PMIIR);
1167 pm_mask = I915_READ(GEN6_PMINTRMSK);
1169 pm_ier = I915_READ(GEN8_GT_IER(2));
1170 pm_imr = I915_READ(GEN8_GT_IMR(2));
1171 pm_isr = I915_READ(GEN8_GT_ISR(2));
1172 pm_iir = I915_READ(GEN8_GT_IIR(2));
1173 pm_mask = I915_READ(GEN6_PMINTRMSK);
1175 seq_printf(m, "Video Turbo Mode: %s\n",
1176 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1177 seq_printf(m, "HW control enabled: %s\n",
1178 yesno(rpmodectl & GEN6_RP_ENABLE));
1179 seq_printf(m, "SW control enabled: %s\n",
1180 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1181 GEN6_RP_MEDIA_SW_MODE));
1182 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1183 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1184 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1185 rps->pm_intrmsk_mbz);
1186 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1187 seq_printf(m, "Render p-state ratio: %d\n",
1188 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1189 seq_printf(m, "Render p-state VID: %d\n",
1190 gt_perf_status & 0xff);
1191 seq_printf(m, "Render p-state limit: %d\n",
1192 rp_state_limits & 0xff);
1193 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1194 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1195 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1196 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1197 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1198 seq_printf(m, "CAGF: %dMHz\n", cagf);
1199 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1200 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1201 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1202 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1203 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1204 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1205 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1207 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1208 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1209 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1210 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1211 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1212 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1213 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1215 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1216 rp_state_cap >> 16) & 0xff;
1217 max_freq *= (IS_GEN9_BC(dev_priv) ||
1218 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1219 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1220 intel_gpu_freq(dev_priv, max_freq));
1222 max_freq = (rp_state_cap & 0xff00) >> 8;
1223 max_freq *= (IS_GEN9_BC(dev_priv) ||
1224 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1225 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1226 intel_gpu_freq(dev_priv, max_freq));
1228 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1229 rp_state_cap >> 0) & 0xff;
1230 max_freq *= (IS_GEN9_BC(dev_priv) ||
1231 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1232 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1233 intel_gpu_freq(dev_priv, max_freq));
1234 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1235 intel_gpu_freq(dev_priv, rps->max_freq));
1237 seq_printf(m, "Current freq: %d MHz\n",
1238 intel_gpu_freq(dev_priv, rps->cur_freq));
1239 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1240 seq_printf(m, "Idle freq: %d MHz\n",
1241 intel_gpu_freq(dev_priv, rps->idle_freq));
1242 seq_printf(m, "Min freq: %d MHz\n",
1243 intel_gpu_freq(dev_priv, rps->min_freq));
1244 seq_printf(m, "Boost freq: %d MHz\n",
1245 intel_gpu_freq(dev_priv, rps->boost_freq));
1246 seq_printf(m, "Max freq: %d MHz\n",
1247 intel_gpu_freq(dev_priv, rps->max_freq));
1249 "efficient (RPe) frequency: %d MHz\n",
1250 intel_gpu_freq(dev_priv, rps->efficient_freq));
1252 seq_puts(m, "no P-state info available\n");
1255 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1256 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1257 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1259 intel_runtime_pm_put(dev_priv);
1263 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1265 struct intel_instdone *instdone)
1270 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1271 instdone->instdone);
1273 if (INTEL_GEN(dev_priv) <= 3)
1276 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1277 instdone->slice_common);
1279 if (INTEL_GEN(dev_priv) <= 6)
1282 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1283 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1284 slice, subslice, instdone->sampler[slice][subslice]);
1286 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1287 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1288 slice, subslice, instdone->row[slice][subslice]);
1291 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1293 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1294 struct intel_engine_cs *engine;
1295 u64 acthd[I915_NUM_ENGINES];
1296 u32 seqno[I915_NUM_ENGINES];
1297 struct intel_instdone instdone;
1298 enum intel_engine_id id;
1300 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1301 seq_puts(m, "Wedged\n");
1302 if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1303 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1304 if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1305 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1306 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1307 seq_puts(m, "Waiter holding struct mutex\n");
1308 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1309 seq_puts(m, "struct_mutex blocked for reset\n");
1311 if (!i915_modparams.enable_hangcheck) {
1312 seq_puts(m, "Hangcheck disabled\n");
1316 intel_runtime_pm_get(dev_priv);
1318 for_each_engine(engine, dev_priv, id) {
1319 acthd[id] = intel_engine_get_active_head(engine);
1320 seqno[id] = intel_engine_get_seqno(engine);
1323 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1325 intel_runtime_pm_put(dev_priv);
1327 if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1328 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1329 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1331 else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1332 seq_puts(m, "Hangcheck active, work pending\n");
1334 seq_puts(m, "Hangcheck inactive\n");
1336 seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1338 for_each_engine(engine, dev_priv, id) {
1339 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1342 seq_printf(m, "%s:\n", engine->name);
1343 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1344 engine->hangcheck.seqno, seqno[id],
1345 intel_engine_last_submit(engine),
1346 engine->timeline->inflight_seqnos);
1347 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1348 yesno(intel_engine_has_waiter(engine)),
1349 yesno(test_bit(engine->id,
1350 &dev_priv->gpu_error.missed_irq_rings)),
1351 yesno(engine->hangcheck.stalled));
1353 spin_lock_irq(&b->rb_lock);
1354 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1355 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1357 seq_printf(m, "\t%s [%d] waiting for %x\n",
1358 w->tsk->comm, w->tsk->pid, w->seqno);
1360 spin_unlock_irq(&b->rb_lock);
1362 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1363 (long long)engine->hangcheck.acthd,
1364 (long long)acthd[id]);
1365 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1366 hangcheck_action_to_str(engine->hangcheck.action),
1367 engine->hangcheck.action,
1368 jiffies_to_msecs(jiffies -
1369 engine->hangcheck.action_timestamp));
1371 if (engine->id == RCS) {
1372 seq_puts(m, "\tinstdone read =\n");
1374 i915_instdone_info(dev_priv, m, &instdone);
1376 seq_puts(m, "\tinstdone accu =\n");
1378 i915_instdone_info(dev_priv, m,
1379 &engine->hangcheck.instdone);
1386 static int i915_reset_info(struct seq_file *m, void *unused)
1388 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1389 struct i915_gpu_error *error = &dev_priv->gpu_error;
1390 struct intel_engine_cs *engine;
1391 enum intel_engine_id id;
1393 seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1395 for_each_engine(engine, dev_priv, id) {
1396 seq_printf(m, "%s = %u\n", engine->name,
1397 i915_reset_engine_count(error, engine));
1403 static int ironlake_drpc_info(struct seq_file *m)
1405 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1406 u32 rgvmodectl, rstdbyctl;
1409 rgvmodectl = I915_READ(MEMMODECTL);
1410 rstdbyctl = I915_READ(RSTDBYCTL);
1411 crstandvid = I915_READ16(CRSTANDVID);
1413 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1414 seq_printf(m, "Boost freq: %d\n",
1415 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1416 MEMMODE_BOOST_FREQ_SHIFT);
1417 seq_printf(m, "HW control enabled: %s\n",
1418 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1419 seq_printf(m, "SW control enabled: %s\n",
1420 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1421 seq_printf(m, "Gated voltage change: %s\n",
1422 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1423 seq_printf(m, "Starting frequency: P%d\n",
1424 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1425 seq_printf(m, "Max P-state: P%d\n",
1426 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1427 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1428 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1429 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1430 seq_printf(m, "Render standby enabled: %s\n",
1431 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1432 seq_puts(m, "Current RS state: ");
1433 switch (rstdbyctl & RSX_STATUS_MASK) {
1435 seq_puts(m, "on\n");
1437 case RSX_STATUS_RC1:
1438 seq_puts(m, "RC1\n");
1440 case RSX_STATUS_RC1E:
1441 seq_puts(m, "RC1E\n");
1443 case RSX_STATUS_RS1:
1444 seq_puts(m, "RS1\n");
1446 case RSX_STATUS_RS2:
1447 seq_puts(m, "RS2 (RC6)\n");
1449 case RSX_STATUS_RS3:
1450 seq_puts(m, "RC3 (RC6+)\n");
1453 seq_puts(m, "unknown\n");
1460 static int i915_forcewake_domains(struct seq_file *m, void *data)
1462 struct drm_i915_private *i915 = node_to_i915(m->private);
1463 struct intel_uncore_forcewake_domain *fw_domain;
1466 seq_printf(m, "user.bypass_count = %u\n",
1467 i915->uncore.user_forcewake.count);
1469 for_each_fw_domain(fw_domain, i915, tmp)
1470 seq_printf(m, "%s.wake_count = %u\n",
1471 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1472 READ_ONCE(fw_domain->wake_count));
1477 static void print_rc6_res(struct seq_file *m,
1479 const i915_reg_t reg)
1481 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1483 seq_printf(m, "%s %u (%llu us)\n",
1484 title, I915_READ(reg),
1485 intel_rc6_residency_us(dev_priv, reg));
1488 static int vlv_drpc_info(struct seq_file *m)
1490 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1491 u32 rcctl1, pw_status;
1493 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1494 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1496 seq_printf(m, "RC6 Enabled: %s\n",
1497 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1498 GEN6_RC_CTL_EI_MODE(1))));
1499 seq_printf(m, "Render Power Well: %s\n",
1500 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1501 seq_printf(m, "Media Power Well: %s\n",
1502 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1504 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1505 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1507 return i915_forcewake_domains(m, NULL);
1510 static int gen6_drpc_info(struct seq_file *m)
1512 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1513 u32 gt_core_status, rcctl1, rc6vids = 0;
1514 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1516 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1517 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1519 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1520 if (INTEL_GEN(dev_priv) >= 9) {
1521 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1522 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1525 if (INTEL_GEN(dev_priv) <= 7) {
1526 mutex_lock(&dev_priv->pcu_lock);
1527 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
1529 mutex_unlock(&dev_priv->pcu_lock);
1532 seq_printf(m, "RC1e Enabled: %s\n",
1533 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1534 seq_printf(m, "RC6 Enabled: %s\n",
1535 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1536 if (INTEL_GEN(dev_priv) >= 9) {
1537 seq_printf(m, "Render Well Gating Enabled: %s\n",
1538 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1539 seq_printf(m, "Media Well Gating Enabled: %s\n",
1540 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1542 seq_printf(m, "Deep RC6 Enabled: %s\n",
1543 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1544 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1545 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1546 seq_puts(m, "Current RC state: ");
1547 switch (gt_core_status & GEN6_RCn_MASK) {
1549 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1550 seq_puts(m, "Core Power Down\n");
1552 seq_puts(m, "on\n");
1555 seq_puts(m, "RC3\n");
1558 seq_puts(m, "RC6\n");
1561 seq_puts(m, "RC7\n");
1564 seq_puts(m, "Unknown\n");
1568 seq_printf(m, "Core Power Down: %s\n",
1569 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1570 if (INTEL_GEN(dev_priv) >= 9) {
1571 seq_printf(m, "Render Power Well: %s\n",
1572 (gen9_powergate_status &
1573 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1574 seq_printf(m, "Media Power Well: %s\n",
1575 (gen9_powergate_status &
1576 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1579 /* Not exactly sure what this is */
1580 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1581 GEN6_GT_GFX_RC6_LOCKED);
1582 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1583 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1584 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1586 if (INTEL_GEN(dev_priv) <= 7) {
1587 seq_printf(m, "RC6 voltage: %dmV\n",
1588 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589 seq_printf(m, "RC6+ voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591 seq_printf(m, "RC6++ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1595 return i915_forcewake_domains(m, NULL);
1598 static int i915_drpc_info(struct seq_file *m, void *unused)
1600 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1603 intel_runtime_pm_get(dev_priv);
1605 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1606 err = vlv_drpc_info(m);
1607 else if (INTEL_GEN(dev_priv) >= 6)
1608 err = gen6_drpc_info(m);
1610 err = ironlake_drpc_info(m);
1612 intel_runtime_pm_put(dev_priv);
1617 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1619 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1621 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1622 dev_priv->fb_tracking.busy_bits);
1624 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1625 dev_priv->fb_tracking.flip_bits);
1630 static int i915_fbc_status(struct seq_file *m, void *unused)
1632 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1633 struct intel_fbc *fbc = &dev_priv->fbc;
1635 if (!HAS_FBC(dev_priv))
1638 intel_runtime_pm_get(dev_priv);
1639 mutex_lock(&fbc->lock);
1641 if (intel_fbc_is_active(dev_priv))
1642 seq_puts(m, "FBC enabled\n");
1644 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1646 if (fbc->work.scheduled)
1647 seq_printf(m, "FBC worker scheduled on vblank %llu, now %llu\n",
1648 fbc->work.scheduled_vblank,
1649 drm_crtc_vblank_count(&fbc->crtc->base));
1651 if (intel_fbc_is_active(dev_priv)) {
1654 if (INTEL_GEN(dev_priv) >= 8)
1655 mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1656 else if (INTEL_GEN(dev_priv) >= 7)
1657 mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1658 else if (INTEL_GEN(dev_priv) >= 5)
1659 mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1660 else if (IS_G4X(dev_priv))
1661 mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1663 mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1664 FBC_STAT_COMPRESSED);
1666 seq_printf(m, "Compressing: %s\n", yesno(mask));
1669 mutex_unlock(&fbc->lock);
1670 intel_runtime_pm_put(dev_priv);
1675 static int i915_fbc_false_color_get(void *data, u64 *val)
1677 struct drm_i915_private *dev_priv = data;
1679 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1682 *val = dev_priv->fbc.false_color;
1687 static int i915_fbc_false_color_set(void *data, u64 val)
1689 struct drm_i915_private *dev_priv = data;
1692 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1695 mutex_lock(&dev_priv->fbc.lock);
1697 reg = I915_READ(ILK_DPFC_CONTROL);
1698 dev_priv->fbc.false_color = val;
1700 I915_WRITE(ILK_DPFC_CONTROL, val ?
1701 (reg | FBC_CTL_FALSE_COLOR) :
1702 (reg & ~FBC_CTL_FALSE_COLOR));
1704 mutex_unlock(&dev_priv->fbc.lock);
1708 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1709 i915_fbc_false_color_get, i915_fbc_false_color_set,
1712 static int i915_ips_status(struct seq_file *m, void *unused)
1714 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1716 if (!HAS_IPS(dev_priv))
1719 intel_runtime_pm_get(dev_priv);
1721 seq_printf(m, "Enabled by kernel parameter: %s\n",
1722 yesno(i915_modparams.enable_ips));
1724 if (INTEL_GEN(dev_priv) >= 8) {
1725 seq_puts(m, "Currently: unknown\n");
1727 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1728 seq_puts(m, "Currently: enabled\n");
1730 seq_puts(m, "Currently: disabled\n");
1733 intel_runtime_pm_put(dev_priv);
1738 static int i915_sr_status(struct seq_file *m, void *unused)
1740 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1741 bool sr_enabled = false;
1743 intel_runtime_pm_get(dev_priv);
1744 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1746 if (INTEL_GEN(dev_priv) >= 9)
1747 /* no global SR status; inspect per-plane WM */;
1748 else if (HAS_PCH_SPLIT(dev_priv))
1749 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1750 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1751 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1752 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1753 else if (IS_I915GM(dev_priv))
1754 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1755 else if (IS_PINEVIEW(dev_priv))
1756 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1757 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1758 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1760 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1761 intel_runtime_pm_put(dev_priv);
1763 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1768 static int i915_emon_status(struct seq_file *m, void *unused)
1770 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1771 struct drm_device *dev = &dev_priv->drm;
1772 unsigned long temp, chipset, gfx;
1775 if (!IS_GEN5(dev_priv))
1778 ret = mutex_lock_interruptible(&dev->struct_mutex);
1782 temp = i915_mch_val(dev_priv);
1783 chipset = i915_chipset_val(dev_priv);
1784 gfx = i915_gfx_val(dev_priv);
1785 mutex_unlock(&dev->struct_mutex);
1787 seq_printf(m, "GMCH temp: %ld\n", temp);
1788 seq_printf(m, "Chipset power: %ld\n", chipset);
1789 seq_printf(m, "GFX power: %ld\n", gfx);
1790 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1795 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1797 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1798 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1799 unsigned int max_gpu_freq, min_gpu_freq;
1800 int gpu_freq, ia_freq;
1803 if (!HAS_LLC(dev_priv))
1806 intel_runtime_pm_get(dev_priv);
1808 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1812 min_gpu_freq = rps->min_freq;
1813 max_gpu_freq = rps->max_freq;
1814 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1815 /* Convert GT frequency to 50 HZ units */
1816 min_gpu_freq /= GEN9_FREQ_SCALER;
1817 max_gpu_freq /= GEN9_FREQ_SCALER;
1820 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1822 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1824 sandybridge_pcode_read(dev_priv,
1825 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1827 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1828 intel_gpu_freq(dev_priv, (gpu_freq *
1829 (IS_GEN9_BC(dev_priv) ||
1830 IS_CANNONLAKE(dev_priv) ?
1831 GEN9_FREQ_SCALER : 1))),
1832 ((ia_freq >> 0) & 0xff) * 100,
1833 ((ia_freq >> 8) & 0xff) * 100);
1836 mutex_unlock(&dev_priv->pcu_lock);
1839 intel_runtime_pm_put(dev_priv);
1843 static int i915_opregion(struct seq_file *m, void *unused)
1845 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1846 struct drm_device *dev = &dev_priv->drm;
1847 struct intel_opregion *opregion = &dev_priv->opregion;
1850 ret = mutex_lock_interruptible(&dev->struct_mutex);
1854 if (opregion->header)
1855 seq_write(m, opregion->header, OPREGION_SIZE);
1857 mutex_unlock(&dev->struct_mutex);
1863 static int i915_vbt(struct seq_file *m, void *unused)
1865 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1868 seq_write(m, opregion->vbt, opregion->vbt_size);
1873 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1875 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1876 struct drm_device *dev = &dev_priv->drm;
1877 struct intel_framebuffer *fbdev_fb = NULL;
1878 struct drm_framebuffer *drm_fb;
1881 ret = mutex_lock_interruptible(&dev->struct_mutex);
1885 #ifdef CONFIG_DRM_FBDEV_EMULATION
1886 if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1887 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1889 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1890 fbdev_fb->base.width,
1891 fbdev_fb->base.height,
1892 fbdev_fb->base.format->depth,
1893 fbdev_fb->base.format->cpp[0] * 8,
1894 fbdev_fb->base.modifier,
1895 drm_framebuffer_read_refcount(&fbdev_fb->base));
1896 describe_obj(m, fbdev_fb->obj);
1901 mutex_lock(&dev->mode_config.fb_lock);
1902 drm_for_each_fb(drm_fb, dev) {
1903 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1907 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910 fb->base.format->depth,
1911 fb->base.format->cpp[0] * 8,
1913 drm_framebuffer_read_refcount(&fb->base));
1914 describe_obj(m, fb->obj);
1917 mutex_unlock(&dev->mode_config.fb_lock);
1918 mutex_unlock(&dev->struct_mutex);
1923 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1925 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
1926 ring->space, ring->head, ring->tail, ring->emit);
1929 static int i915_context_status(struct seq_file *m, void *unused)
1931 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1932 struct drm_device *dev = &dev_priv->drm;
1933 struct intel_engine_cs *engine;
1934 struct i915_gem_context *ctx;
1935 enum intel_engine_id id;
1938 ret = mutex_lock_interruptible(&dev->struct_mutex);
1942 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1943 seq_printf(m, "HW context %u ", ctx->hw_id);
1945 struct task_struct *task;
1947 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1949 seq_printf(m, "(%s [%d]) ",
1950 task->comm, task->pid);
1951 put_task_struct(task);
1953 } else if (IS_ERR(ctx->file_priv)) {
1954 seq_puts(m, "(deleted) ");
1956 seq_puts(m, "(kernel) ");
1959 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1962 for_each_engine(engine, dev_priv, id) {
1963 struct intel_context *ce = &ctx->engine[engine->id];
1965 seq_printf(m, "%s: ", engine->name);
1967 describe_obj(m, ce->state->obj);
1969 describe_ctx_ring(m, ce->ring);
1976 mutex_unlock(&dev->struct_mutex);
1981 static const char *swizzle_string(unsigned swizzle)
1984 case I915_BIT_6_SWIZZLE_NONE:
1986 case I915_BIT_6_SWIZZLE_9:
1988 case I915_BIT_6_SWIZZLE_9_10:
1989 return "bit9/bit10";
1990 case I915_BIT_6_SWIZZLE_9_11:
1991 return "bit9/bit11";
1992 case I915_BIT_6_SWIZZLE_9_10_11:
1993 return "bit9/bit10/bit11";
1994 case I915_BIT_6_SWIZZLE_9_17:
1995 return "bit9/bit17";
1996 case I915_BIT_6_SWIZZLE_9_10_17:
1997 return "bit9/bit10/bit17";
1998 case I915_BIT_6_SWIZZLE_UNKNOWN:
2005 static int i915_swizzle_info(struct seq_file *m, void *data)
2007 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2009 intel_runtime_pm_get(dev_priv);
2011 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2012 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2013 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2014 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2016 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2017 seq_printf(m, "DDC = 0x%08x\n",
2019 seq_printf(m, "DDC2 = 0x%08x\n",
2021 seq_printf(m, "C0DRB3 = 0x%04x\n",
2022 I915_READ16(C0DRB3));
2023 seq_printf(m, "C1DRB3 = 0x%04x\n",
2024 I915_READ16(C1DRB3));
2025 } else if (INTEL_GEN(dev_priv) >= 6) {
2026 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2027 I915_READ(MAD_DIMM_C0));
2028 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2029 I915_READ(MAD_DIMM_C1));
2030 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2031 I915_READ(MAD_DIMM_C2));
2032 seq_printf(m, "TILECTL = 0x%08x\n",
2033 I915_READ(TILECTL));
2034 if (INTEL_GEN(dev_priv) >= 8)
2035 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2036 I915_READ(GAMTARBMODE));
2038 seq_printf(m, "ARB_MODE = 0x%08x\n",
2039 I915_READ(ARB_MODE));
2040 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2041 I915_READ(DISP_ARB_CTL));
2044 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2045 seq_puts(m, "L-shaped memory detected\n");
2047 intel_runtime_pm_put(dev_priv);
2052 static int per_file_ctx(int id, void *ptr, void *data)
2054 struct i915_gem_context *ctx = ptr;
2055 struct seq_file *m = data;
2056 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2059 seq_printf(m, " no ppgtt for context %d\n",
2064 if (i915_gem_context_is_default(ctx))
2065 seq_puts(m, " default context:\n");
2067 seq_printf(m, " context %d:\n", ctx->user_handle);
2068 ppgtt->debug_dump(ppgtt, m);
2073 static void gen8_ppgtt_info(struct seq_file *m,
2074 struct drm_i915_private *dev_priv)
2076 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2077 struct intel_engine_cs *engine;
2078 enum intel_engine_id id;
2084 for_each_engine(engine, dev_priv, id) {
2085 seq_printf(m, "%s\n", engine->name);
2086 for (i = 0; i < 4; i++) {
2087 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2089 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2090 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2095 static void gen6_ppgtt_info(struct seq_file *m,
2096 struct drm_i915_private *dev_priv)
2098 struct intel_engine_cs *engine;
2099 enum intel_engine_id id;
2101 if (IS_GEN6(dev_priv))
2102 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2104 for_each_engine(engine, dev_priv, id) {
2105 seq_printf(m, "%s\n", engine->name);
2106 if (IS_GEN7(dev_priv))
2107 seq_printf(m, "GFX_MODE: 0x%08x\n",
2108 I915_READ(RING_MODE_GEN7(engine)));
2109 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2110 I915_READ(RING_PP_DIR_BASE(engine)));
2111 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2112 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2113 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2114 I915_READ(RING_PP_DIR_DCLV(engine)));
2116 if (dev_priv->mm.aliasing_ppgtt) {
2117 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2119 seq_puts(m, "aliasing PPGTT:\n");
2120 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2122 ppgtt->debug_dump(ppgtt, m);
2125 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2128 static int i915_ppgtt_info(struct seq_file *m, void *data)
2130 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2131 struct drm_device *dev = &dev_priv->drm;
2132 struct drm_file *file;
2135 mutex_lock(&dev->filelist_mutex);
2136 ret = mutex_lock_interruptible(&dev->struct_mutex);
2140 intel_runtime_pm_get(dev_priv);
2142 if (INTEL_GEN(dev_priv) >= 8)
2143 gen8_ppgtt_info(m, dev_priv);
2144 else if (INTEL_GEN(dev_priv) >= 6)
2145 gen6_ppgtt_info(m, dev_priv);
2147 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2148 struct drm_i915_file_private *file_priv = file->driver_priv;
2149 struct task_struct *task;
2151 task = get_pid_task(file->pid, PIDTYPE_PID);
2156 seq_printf(m, "\nproc: %s\n", task->comm);
2157 put_task_struct(task);
2158 idr_for_each(&file_priv->context_idr, per_file_ctx,
2159 (void *)(unsigned long)m);
2163 intel_runtime_pm_put(dev_priv);
2164 mutex_unlock(&dev->struct_mutex);
2166 mutex_unlock(&dev->filelist_mutex);
2170 static int count_irq_waiters(struct drm_i915_private *i915)
2172 struct intel_engine_cs *engine;
2173 enum intel_engine_id id;
2176 for_each_engine(engine, i915, id)
2177 count += intel_engine_has_waiter(engine);
2182 static const char *rps_power_to_str(unsigned int power)
2184 static const char * const strings[] = {
2185 [LOW_POWER] = "low power",
2186 [BETWEEN] = "mixed",
2187 [HIGH_POWER] = "high power",
2190 if (power >= ARRAY_SIZE(strings) || !strings[power])
2193 return strings[power];
2196 static int i915_rps_boost_info(struct seq_file *m, void *data)
2198 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2199 struct drm_device *dev = &dev_priv->drm;
2200 struct intel_rps *rps = &dev_priv->gt_pm.rps;
2201 struct drm_file *file;
2203 seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2204 seq_printf(m, "GPU busy? %s [%d requests]\n",
2205 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2206 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2207 seq_printf(m, "Boosts outstanding? %d\n",
2208 atomic_read(&rps->num_waiters));
2209 seq_printf(m, "Frequency requested %d\n",
2210 intel_gpu_freq(dev_priv, rps->cur_freq));
2211 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2212 intel_gpu_freq(dev_priv, rps->min_freq),
2213 intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2214 intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2215 intel_gpu_freq(dev_priv, rps->max_freq));
2216 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2217 intel_gpu_freq(dev_priv, rps->idle_freq),
2218 intel_gpu_freq(dev_priv, rps->efficient_freq),
2219 intel_gpu_freq(dev_priv, rps->boost_freq));
2221 mutex_lock(&dev->filelist_mutex);
2222 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2223 struct drm_i915_file_private *file_priv = file->driver_priv;
2224 struct task_struct *task;
2227 task = pid_task(file->pid, PIDTYPE_PID);
2228 seq_printf(m, "%s [%d]: %d boosts\n",
2229 task ? task->comm : "<unknown>",
2230 task ? task->pid : -1,
2231 atomic_read(&file_priv->rps_client.boosts));
2234 seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2235 atomic_read(&rps->boosts));
2236 mutex_unlock(&dev->filelist_mutex);
2238 if (INTEL_GEN(dev_priv) >= 6 &&
2240 dev_priv->gt.active_requests) {
2242 u32 rpdown, rpdownei;
2244 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2245 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2246 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2247 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2248 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2249 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2251 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2252 rps_power_to_str(rps->power));
2253 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2254 rpup && rpupei ? 100 * rpup / rpupei : 0,
2256 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2257 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2258 rps->down_threshold);
2260 seq_puts(m, "\nRPS Autotuning inactive\n");
2266 static int i915_llc(struct seq_file *m, void *data)
2268 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2269 const bool edram = INTEL_GEN(dev_priv) > 8;
2271 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2272 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2273 intel_uncore_edram_size(dev_priv)/1024/1024);
2278 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2280 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2281 struct drm_printer p;
2283 if (!HAS_HUC(dev_priv))
2286 p = drm_seq_file_printer(m);
2287 intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2289 intel_runtime_pm_get(dev_priv);
2290 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2291 intel_runtime_pm_put(dev_priv);
2296 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2298 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2299 struct drm_printer p;
2302 if (!HAS_GUC(dev_priv))
2305 p = drm_seq_file_printer(m);
2306 intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2308 intel_runtime_pm_get(dev_priv);
2310 tmp = I915_READ(GUC_STATUS);
2312 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2313 seq_printf(m, "\tBootrom status = 0x%x\n",
2314 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2315 seq_printf(m, "\tuKernel status = 0x%x\n",
2316 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2317 seq_printf(m, "\tMIA Core status = 0x%x\n",
2318 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2319 seq_puts(m, "\nScratch registers:\n");
2320 for (i = 0; i < 16; i++)
2321 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2323 intel_runtime_pm_put(dev_priv);
2328 static void i915_guc_log_info(struct seq_file *m,
2329 struct drm_i915_private *dev_priv)
2331 struct intel_guc *guc = &dev_priv->guc;
2333 seq_puts(m, "\nGuC logging stats:\n");
2335 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2336 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2337 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2339 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2340 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2341 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2343 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2344 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2345 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2347 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2348 guc->log.flush_interrupt_count);
2350 seq_printf(m, "\tCapture miss count: %u\n",
2351 guc->log.capture_miss_count);
2354 static void i915_guc_client_info(struct seq_file *m,
2355 struct drm_i915_private *dev_priv,
2356 struct intel_guc_client *client)
2358 struct intel_engine_cs *engine;
2359 enum intel_engine_id id;
2362 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2363 client->priority, client->stage_id, client->proc_desc_offset);
2364 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2365 client->doorbell_id, client->doorbell_offset);
2367 for_each_engine(engine, dev_priv, id) {
2368 u64 submissions = client->submissions[id];
2370 seq_printf(m, "\tSubmissions: %llu %s\n",
2371 submissions, engine->name);
2373 seq_printf(m, "\tTotal: %llu\n", tot);
2376 static int i915_guc_info(struct seq_file *m, void *data)
2378 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2379 const struct intel_guc *guc = &dev_priv->guc;
2381 if (!USES_GUC_SUBMISSION(dev_priv))
2384 GEM_BUG_ON(!guc->execbuf_client);
2386 seq_printf(m, "Doorbell map:\n");
2387 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2388 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2390 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2391 i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2392 if (guc->preempt_client) {
2393 seq_printf(m, "\nGuC preempt client @ %p:\n",
2394 guc->preempt_client);
2395 i915_guc_client_info(m, dev_priv, guc->preempt_client);
2398 i915_guc_log_info(m, dev_priv);
2400 /* Add more as required ... */
2405 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2407 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2408 const struct intel_guc *guc = &dev_priv->guc;
2409 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2410 struct intel_guc_client *client = guc->execbuf_client;
2414 if (!USES_GUC_SUBMISSION(dev_priv))
2417 for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2418 struct intel_engine_cs *engine;
2420 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2423 seq_printf(m, "GuC stage descriptor %u:\n", index);
2424 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2425 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2426 seq_printf(m, "\tPriority: %d\n", desc->priority);
2427 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2428 seq_printf(m, "\tEngines used: 0x%x\n",
2429 desc->engines_used);
2430 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2431 desc->db_trigger_phy,
2432 desc->db_trigger_cpu,
2433 desc->db_trigger_uk);
2434 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2435 desc->process_desc);
2436 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2437 desc->wq_addr, desc->wq_size);
2440 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2441 u32 guc_engine_id = engine->guc_id;
2442 struct guc_execlist_context *lrc =
2443 &desc->lrc[guc_engine_id];
2445 seq_printf(m, "\t%s LRC:\n", engine->name);
2446 seq_printf(m, "\t\tContext desc: 0x%x\n",
2448 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2449 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2450 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2451 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2459 static int i915_guc_log_dump(struct seq_file *m, void *data)
2461 struct drm_info_node *node = m->private;
2462 struct drm_i915_private *dev_priv = node_to_i915(node);
2463 bool dump_load_err = !!node->info_ent->data;
2464 struct drm_i915_gem_object *obj = NULL;
2468 if (!HAS_GUC(dev_priv))
2472 obj = dev_priv->guc.load_err_log;
2473 else if (dev_priv->guc.log.vma)
2474 obj = dev_priv->guc.log.vma->obj;
2479 log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2481 DRM_DEBUG("Failed to pin object\n");
2482 seq_puts(m, "(log data unaccessible)\n");
2483 return PTR_ERR(log);
2486 for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2487 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2488 *(log + i), *(log + i + 1),
2489 *(log + i + 2), *(log + i + 3));
2493 i915_gem_object_unpin_map(obj);
2498 static int i915_guc_log_control_get(void *data, u64 *val)
2500 struct drm_i915_private *dev_priv = data;
2502 if (!HAS_GUC(dev_priv))
2505 if (!dev_priv->guc.log.vma)
2508 *val = i915_modparams.guc_log_level;
2513 static int i915_guc_log_control_set(void *data, u64 val)
2515 struct drm_i915_private *dev_priv = data;
2517 if (!HAS_GUC(dev_priv))
2520 return intel_guc_log_control(&dev_priv->guc, val);
2523 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2524 i915_guc_log_control_get, i915_guc_log_control_set,
2527 static const char *psr2_live_status(u32 val)
2529 static const char * const live_status[] = {
2543 val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2544 if (val < ARRAY_SIZE(live_status))
2545 return live_status[val];
2550 static int i915_edp_psr_status(struct seq_file *m, void *data)
2552 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2556 bool enabled = false;
2559 if (!HAS_PSR(dev_priv))
2562 sink_support = dev_priv->psr.sink_support;
2563 seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
2567 intel_runtime_pm_get(dev_priv);
2569 mutex_lock(&dev_priv->psr.lock);
2570 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2571 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2572 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2573 dev_priv->psr.busy_frontbuffer_bits);
2574 seq_printf(m, "Re-enable work scheduled: %s\n",
2575 yesno(work_busy(&dev_priv->psr.work.work)));
2577 if (HAS_DDI(dev_priv)) {
2578 if (dev_priv->psr.psr2_support)
2579 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2581 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2583 for_each_pipe(dev_priv, pipe) {
2584 enum transcoder cpu_transcoder =
2585 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2586 enum intel_display_power_domain power_domain;
2588 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2589 if (!intel_display_power_get_if_enabled(dev_priv,
2593 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2594 VLV_EDP_PSR_CURR_STATE_MASK;
2595 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2596 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2599 intel_display_power_put(dev_priv, power_domain);
2603 seq_printf(m, "Main link in standby mode: %s\n",
2604 yesno(dev_priv->psr.link_standby));
2606 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2608 if (!HAS_DDI(dev_priv))
2609 for_each_pipe(dev_priv, pipe) {
2610 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2611 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2612 seq_printf(m, " pipe %c", pipe_name(pipe));
2617 * VLV/CHV PSR has no kind of performance counter
2618 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2620 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2621 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2622 EDP_PSR_PERF_CNT_MASK;
2624 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2626 if (dev_priv->psr.psr2_support) {
2627 u32 psr2 = I915_READ(EDP_PSR2_STATUS);
2629 seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
2630 psr2, psr2_live_status(psr2));
2632 mutex_unlock(&dev_priv->psr.lock);
2634 intel_runtime_pm_put(dev_priv);
2638 static int i915_sink_crc(struct seq_file *m, void *data)
2640 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2641 struct drm_device *dev = &dev_priv->drm;
2642 struct intel_connector *connector;
2643 struct drm_connector_list_iter conn_iter;
2644 struct intel_dp *intel_dp = NULL;
2645 struct drm_modeset_acquire_ctx ctx;
2649 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2651 drm_connector_list_iter_begin(dev, &conn_iter);
2653 for_each_intel_connector_iter(connector, &conn_iter) {
2654 struct drm_crtc *crtc;
2655 struct drm_connector_state *state;
2656 struct intel_crtc_state *crtc_state;
2658 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2662 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2666 state = connector->base.state;
2667 if (!state->best_encoder)
2671 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2675 crtc_state = to_intel_crtc_state(crtc->state);
2676 if (!crtc_state->base.active)
2680 * We need to wait for all crtc updates to complete, to make
2681 * sure any pending modesets and plane updates are completed.
2683 if (crtc_state->base.commit) {
2684 ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
2690 intel_dp = enc_to_intel_dp(state->best_encoder);
2692 ret = intel_dp_sink_crc(intel_dp, crtc_state, crc);
2696 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2697 crc[0], crc[1], crc[2],
2698 crc[3], crc[4], crc[5]);
2702 if (ret == -EDEADLK) {
2703 ret = drm_modeset_backoff(&ctx);
2711 drm_connector_list_iter_end(&conn_iter);
2712 drm_modeset_drop_locks(&ctx);
2713 drm_modeset_acquire_fini(&ctx);
2718 static int i915_energy_uJ(struct seq_file *m, void *data)
2720 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2721 unsigned long long power;
2724 if (INTEL_GEN(dev_priv) < 6)
2727 intel_runtime_pm_get(dev_priv);
2729 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2730 intel_runtime_pm_put(dev_priv);
2734 units = (power & 0x1f00) >> 8;
2735 power = I915_READ(MCH_SECP_NRG_STTS);
2736 power = (1000000 * power) >> units; /* convert to uJ */
2738 intel_runtime_pm_put(dev_priv);
2740 seq_printf(m, "%llu", power);
2745 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2747 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2748 struct pci_dev *pdev = dev_priv->drm.pdev;
2750 if (!HAS_RUNTIME_PM(dev_priv))
2751 seq_puts(m, "Runtime power management not supported\n");
2753 seq_printf(m, "GPU idle: %s (epoch %u)\n",
2754 yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
2755 seq_printf(m, "IRQs disabled: %s\n",
2756 yesno(!intel_irqs_enabled(dev_priv)));
2758 seq_printf(m, "Usage count: %d\n",
2759 atomic_read(&dev_priv->drm.dev->power.usage_count));
2761 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2763 seq_printf(m, "PCI device power state: %s [%d]\n",
2764 pci_power_name(pdev->current_state),
2765 pdev->current_state);
2770 static int i915_power_domain_info(struct seq_file *m, void *unused)
2772 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2773 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2776 mutex_lock(&power_domains->lock);
2778 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2779 for (i = 0; i < power_domains->power_well_count; i++) {
2780 struct i915_power_well *power_well;
2781 enum intel_display_power_domain power_domain;
2783 power_well = &power_domains->power_wells[i];
2784 seq_printf(m, "%-25s %d\n", power_well->name,
2787 for_each_power_domain(power_domain, power_well->domains)
2788 seq_printf(m, " %-23s %d\n",
2789 intel_display_power_domain_str(power_domain),
2790 power_domains->domain_use_count[power_domain]);
2793 mutex_unlock(&power_domains->lock);
2798 static int i915_dmc_info(struct seq_file *m, void *unused)
2800 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2801 struct intel_csr *csr;
2803 if (!HAS_CSR(dev_priv))
2806 csr = &dev_priv->csr;
2808 intel_runtime_pm_get(dev_priv);
2810 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2811 seq_printf(m, "path: %s\n", csr->fw_path);
2813 if (!csr->dmc_payload)
2816 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2817 CSR_VERSION_MINOR(csr->version));
2819 if (IS_KABYLAKE(dev_priv) ||
2820 (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2821 seq_printf(m, "DC3 -> DC5 count: %d\n",
2822 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2823 seq_printf(m, "DC5 -> DC6 count: %d\n",
2824 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2825 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2826 seq_printf(m, "DC3 -> DC5 count: %d\n",
2827 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2831 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2832 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2833 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2835 intel_runtime_pm_put(dev_priv);
2840 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2841 struct drm_display_mode *mode)
2845 for (i = 0; i < tabs; i++)
2848 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2849 mode->base.id, mode->name,
2850 mode->vrefresh, mode->clock,
2851 mode->hdisplay, mode->hsync_start,
2852 mode->hsync_end, mode->htotal,
2853 mode->vdisplay, mode->vsync_start,
2854 mode->vsync_end, mode->vtotal,
2855 mode->type, mode->flags);
2858 static void intel_encoder_info(struct seq_file *m,
2859 struct intel_crtc *intel_crtc,
2860 struct intel_encoder *intel_encoder)
2862 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2863 struct drm_device *dev = &dev_priv->drm;
2864 struct drm_crtc *crtc = &intel_crtc->base;
2865 struct intel_connector *intel_connector;
2866 struct drm_encoder *encoder;
2868 encoder = &intel_encoder->base;
2869 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2870 encoder->base.id, encoder->name);
2871 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2872 struct drm_connector *connector = &intel_connector->base;
2873 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2876 drm_get_connector_status_name(connector->status));
2877 if (connector->status == connector_status_connected) {
2878 struct drm_display_mode *mode = &crtc->mode;
2879 seq_printf(m, ", mode:\n");
2880 intel_seq_print_mode(m, 2, mode);
2887 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2889 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2890 struct drm_device *dev = &dev_priv->drm;
2891 struct drm_crtc *crtc = &intel_crtc->base;
2892 struct intel_encoder *intel_encoder;
2893 struct drm_plane_state *plane_state = crtc->primary->state;
2894 struct drm_framebuffer *fb = plane_state->fb;
2897 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2898 fb->base.id, plane_state->src_x >> 16,
2899 plane_state->src_y >> 16, fb->width, fb->height);
2901 seq_puts(m, "\tprimary plane disabled\n");
2902 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2903 intel_encoder_info(m, intel_crtc, intel_encoder);
2906 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2908 struct drm_display_mode *mode = panel->fixed_mode;
2910 seq_printf(m, "\tfixed mode:\n");
2911 intel_seq_print_mode(m, 2, mode);
2914 static void intel_dp_info(struct seq_file *m,
2915 struct intel_connector *intel_connector)
2917 struct intel_encoder *intel_encoder = intel_connector->encoder;
2918 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2920 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2921 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2922 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2923 intel_panel_info(m, &intel_connector->panel);
2925 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2929 static void intel_dp_mst_info(struct seq_file *m,
2930 struct intel_connector *intel_connector)
2932 struct intel_encoder *intel_encoder = intel_connector->encoder;
2933 struct intel_dp_mst_encoder *intel_mst =
2934 enc_to_mst(&intel_encoder->base);
2935 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2936 struct intel_dp *intel_dp = &intel_dig_port->dp;
2937 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2938 intel_connector->port);
2940 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2943 static void intel_hdmi_info(struct seq_file *m,
2944 struct intel_connector *intel_connector)
2946 struct intel_encoder *intel_encoder = intel_connector->encoder;
2947 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2949 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2952 static void intel_lvds_info(struct seq_file *m,
2953 struct intel_connector *intel_connector)
2955 intel_panel_info(m, &intel_connector->panel);
2958 static void intel_connector_info(struct seq_file *m,
2959 struct drm_connector *connector)
2961 struct intel_connector *intel_connector = to_intel_connector(connector);
2962 struct intel_encoder *intel_encoder = intel_connector->encoder;
2963 struct drm_display_mode *mode;
2965 seq_printf(m, "connector %d: type %s, status: %s\n",
2966 connector->base.id, connector->name,
2967 drm_get_connector_status_name(connector->status));
2968 if (connector->status == connector_status_connected) {
2969 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2970 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2971 connector->display_info.width_mm,
2972 connector->display_info.height_mm);
2973 seq_printf(m, "\tsubpixel order: %s\n",
2974 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2975 seq_printf(m, "\tCEA rev: %d\n",
2976 connector->display_info.cea_rev);
2982 switch (connector->connector_type) {
2983 case DRM_MODE_CONNECTOR_DisplayPort:
2984 case DRM_MODE_CONNECTOR_eDP:
2985 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2986 intel_dp_mst_info(m, intel_connector);
2988 intel_dp_info(m, intel_connector);
2990 case DRM_MODE_CONNECTOR_LVDS:
2991 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2992 intel_lvds_info(m, intel_connector);
2994 case DRM_MODE_CONNECTOR_HDMIA:
2995 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2996 intel_encoder->type == INTEL_OUTPUT_DDI)
2997 intel_hdmi_info(m, intel_connector);
3003 seq_printf(m, "\tmodes:\n");
3004 list_for_each_entry(mode, &connector->modes, head)
3005 intel_seq_print_mode(m, 2, mode);
3008 static const char *plane_type(enum drm_plane_type type)
3011 case DRM_PLANE_TYPE_OVERLAY:
3013 case DRM_PLANE_TYPE_PRIMARY:
3015 case DRM_PLANE_TYPE_CURSOR:
3018 * Deliberately omitting default: to generate compiler warnings
3019 * when a new drm_plane_type gets added.
3026 static const char *plane_rotation(unsigned int rotation)
3028 static char buf[48];
3030 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3031 * will print them all to visualize if the values are misused
3033 snprintf(buf, sizeof(buf),
3034 "%s%s%s%s%s%s(0x%08x)",
3035 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3036 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3037 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3038 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3039 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3040 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3046 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3048 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3049 struct drm_device *dev = &dev_priv->drm;
3050 struct intel_plane *intel_plane;
3052 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3053 struct drm_plane_state *state;
3054 struct drm_plane *plane = &intel_plane->base;
3055 struct drm_format_name_buf format_name;
3057 if (!plane->state) {
3058 seq_puts(m, "plane->state is NULL!\n");
3062 state = plane->state;
3065 drm_get_format_name(state->fb->format->format,
3068 sprintf(format_name.str, "N/A");
3071 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3073 plane_type(intel_plane->base.type),
3074 state->crtc_x, state->crtc_y,
3075 state->crtc_w, state->crtc_h,
3076 (state->src_x >> 16),
3077 ((state->src_x & 0xffff) * 15625) >> 10,
3078 (state->src_y >> 16),
3079 ((state->src_y & 0xffff) * 15625) >> 10,
3080 (state->src_w >> 16),
3081 ((state->src_w & 0xffff) * 15625) >> 10,
3082 (state->src_h >> 16),
3083 ((state->src_h & 0xffff) * 15625) >> 10,
3085 plane_rotation(state->rotation));
3089 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3091 struct intel_crtc_state *pipe_config;
3092 int num_scalers = intel_crtc->num_scalers;
3095 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3097 /* Not all platformas have a scaler */
3099 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3101 pipe_config->scaler_state.scaler_users,
3102 pipe_config->scaler_state.scaler_id);
3104 for (i = 0; i < num_scalers; i++) {
3105 struct intel_scaler *sc =
3106 &pipe_config->scaler_state.scalers[i];
3108 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3109 i, yesno(sc->in_use), sc->mode);
3113 seq_puts(m, "\tNo scalers available on this platform\n");
3117 static int i915_display_info(struct seq_file *m, void *unused)
3119 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3120 struct drm_device *dev = &dev_priv->drm;
3121 struct intel_crtc *crtc;
3122 struct drm_connector *connector;
3123 struct drm_connector_list_iter conn_iter;
3125 intel_runtime_pm_get(dev_priv);
3126 seq_printf(m, "CRTC info\n");
3127 seq_printf(m, "---------\n");
3128 for_each_intel_crtc(dev, crtc) {
3129 struct intel_crtc_state *pipe_config;
3131 drm_modeset_lock(&crtc->base.mutex, NULL);
3132 pipe_config = to_intel_crtc_state(crtc->base.state);
3134 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3135 crtc->base.base.id, pipe_name(crtc->pipe),
3136 yesno(pipe_config->base.active),
3137 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3138 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3140 if (pipe_config->base.active) {
3141 struct intel_plane *cursor =
3142 to_intel_plane(crtc->base.cursor);
3144 intel_crtc_info(m, crtc);
3146 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3147 yesno(cursor->base.state->visible),
3148 cursor->base.state->crtc_x,
3149 cursor->base.state->crtc_y,
3150 cursor->base.state->crtc_w,
3151 cursor->base.state->crtc_h,
3152 cursor->cursor.base);
3153 intel_scaler_info(m, crtc);
3154 intel_plane_info(m, crtc);
3157 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3158 yesno(!crtc->cpu_fifo_underrun_disabled),
3159 yesno(!crtc->pch_fifo_underrun_disabled));
3160 drm_modeset_unlock(&crtc->base.mutex);
3163 seq_printf(m, "\n");
3164 seq_printf(m, "Connector info\n");
3165 seq_printf(m, "--------------\n");
3166 mutex_lock(&dev->mode_config.mutex);
3167 drm_connector_list_iter_begin(dev, &conn_iter);
3168 drm_for_each_connector_iter(connector, &conn_iter)
3169 intel_connector_info(m, connector);
3170 drm_connector_list_iter_end(&conn_iter);
3171 mutex_unlock(&dev->mode_config.mutex);
3173 intel_runtime_pm_put(dev_priv);
3178 static int i915_engine_info(struct seq_file *m, void *unused)
3180 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3181 struct intel_engine_cs *engine;
3182 enum intel_engine_id id;
3183 struct drm_printer p;
3185 intel_runtime_pm_get(dev_priv);
3187 seq_printf(m, "GT awake? %s (epoch %u)\n",
3188 yesno(dev_priv->gt.awake), dev_priv->gt.epoch);
3189 seq_printf(m, "Global active requests: %d\n",
3190 dev_priv->gt.active_requests);
3191 seq_printf(m, "CS timestamp frequency: %u kHz\n",
3192 dev_priv->info.cs_timestamp_frequency_khz);
3194 p = drm_seq_file_printer(m);
3195 for_each_engine(engine, dev_priv, id)
3196 intel_engine_dump(engine, &p, "%s\n", engine->name);
3198 intel_runtime_pm_put(dev_priv);
3203 static int i915_rcs_topology(struct seq_file *m, void *unused)
3205 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3206 struct drm_printer p = drm_seq_file_printer(m);
3208 intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
3213 static int i915_shrinker_info(struct seq_file *m, void *unused)
3215 struct drm_i915_private *i915 = node_to_i915(m->private);
3217 seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3218 seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3223 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3225 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3226 struct drm_device *dev = &dev_priv->drm;
3229 drm_modeset_lock_all(dev);
3230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3231 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3233 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3234 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3235 pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3236 seq_printf(m, " tracked hardware state:\n");
3237 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
3238 seq_printf(m, " dpll_md: 0x%08x\n",
3239 pll->state.hw_state.dpll_md);
3240 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
3241 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
3242 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
3244 drm_modeset_unlock_all(dev);
3249 static int i915_wa_registers(struct seq_file *m, void *unused)
3253 struct intel_engine_cs *engine;
3254 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3255 struct drm_device *dev = &dev_priv->drm;
3256 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3257 enum intel_engine_id id;
3259 ret = mutex_lock_interruptible(&dev->struct_mutex);
3263 intel_runtime_pm_get(dev_priv);
3265 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3266 for_each_engine(engine, dev_priv, id)
3267 seq_printf(m, "HW whitelist count for %s: %d\n",
3268 engine->name, workarounds->hw_whitelist_count[id]);
3269 for (i = 0; i < workarounds->count; ++i) {
3271 u32 mask, value, read;
3274 addr = workarounds->reg[i].addr;
3275 mask = workarounds->reg[i].mask;
3276 value = workarounds->reg[i].value;
3277 read = I915_READ(addr);
3278 ok = (value & mask) == (read & mask);
3279 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3280 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3283 intel_runtime_pm_put(dev_priv);
3284 mutex_unlock(&dev->struct_mutex);
3289 static int i915_ipc_status_show(struct seq_file *m, void *data)
3291 struct drm_i915_private *dev_priv = m->private;
3293 seq_printf(m, "Isochronous Priority Control: %s\n",
3294 yesno(dev_priv->ipc_enabled));
3298 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3300 struct drm_i915_private *dev_priv = inode->i_private;
3302 if (!HAS_IPC(dev_priv))
3305 return single_open(file, i915_ipc_status_show, dev_priv);
3308 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3309 size_t len, loff_t *offp)
3311 struct seq_file *m = file->private_data;
3312 struct drm_i915_private *dev_priv = m->private;
3316 ret = kstrtobool_from_user(ubuf, len, &enable);
3320 intel_runtime_pm_get(dev_priv);
3321 if (!dev_priv->ipc_enabled && enable)
3322 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3323 dev_priv->wm.distrust_bios_wm = true;
3324 dev_priv->ipc_enabled = enable;
3325 intel_enable_ipc(dev_priv);
3326 intel_runtime_pm_put(dev_priv);
3331 static const struct file_operations i915_ipc_status_fops = {
3332 .owner = THIS_MODULE,
3333 .open = i915_ipc_status_open,
3335 .llseek = seq_lseek,
3336 .release = single_release,
3337 .write = i915_ipc_status_write
3340 static int i915_ddb_info(struct seq_file *m, void *unused)
3342 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3343 struct drm_device *dev = &dev_priv->drm;
3344 struct skl_ddb_allocation *ddb;
3345 struct skl_ddb_entry *entry;
3349 if (INTEL_GEN(dev_priv) < 9)
3352 drm_modeset_lock_all(dev);
3354 ddb = &dev_priv->wm.skl_hw.ddb;
3356 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3358 for_each_pipe(dev_priv, pipe) {
3359 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3361 for_each_universal_plane(dev_priv, pipe, plane) {
3362 entry = &ddb->plane[pipe][plane];
3363 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3364 entry->start, entry->end,
3365 skl_ddb_entry_size(entry));
3368 entry = &ddb->plane[pipe][PLANE_CURSOR];
3369 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3370 entry->end, skl_ddb_entry_size(entry));
3373 drm_modeset_unlock_all(dev);
3378 static void drrs_status_per_crtc(struct seq_file *m,
3379 struct drm_device *dev,
3380 struct intel_crtc *intel_crtc)
3382 struct drm_i915_private *dev_priv = to_i915(dev);
3383 struct i915_drrs *drrs = &dev_priv->drrs;
3385 struct drm_connector *connector;
3386 struct drm_connector_list_iter conn_iter;
3388 drm_connector_list_iter_begin(dev, &conn_iter);
3389 drm_for_each_connector_iter(connector, &conn_iter) {
3390 if (connector->state->crtc != &intel_crtc->base)
3393 seq_printf(m, "%s:\n", connector->name);
3395 drm_connector_list_iter_end(&conn_iter);
3397 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3398 seq_puts(m, "\tVBT: DRRS_type: Static");
3399 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3400 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3401 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3402 seq_puts(m, "\tVBT: DRRS_type: None");
3404 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3406 seq_puts(m, "\n\n");
3408 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3409 struct intel_panel *panel;
3411 mutex_lock(&drrs->mutex);
3412 /* DRRS Supported */
3413 seq_puts(m, "\tDRRS Supported: Yes\n");
3415 /* disable_drrs() will make drrs->dp NULL */
3417 seq_puts(m, "Idleness DRRS: Disabled\n");
3418 if (dev_priv->psr.enabled)
3420 "\tAs PSR is enabled, DRRS is not enabled\n");
3421 mutex_unlock(&drrs->mutex);
3425 panel = &drrs->dp->attached_connector->panel;
3426 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3427 drrs->busy_frontbuffer_bits);
3429 seq_puts(m, "\n\t\t");
3430 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3431 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3432 vrefresh = panel->fixed_mode->vrefresh;
3433 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3434 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3435 vrefresh = panel->downclock_mode->vrefresh;
3437 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3438 drrs->refresh_rate_type);
3439 mutex_unlock(&drrs->mutex);
3442 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3444 seq_puts(m, "\n\t\t");
3445 mutex_unlock(&drrs->mutex);
3447 /* DRRS not supported. Print the VBT parameter*/
3448 seq_puts(m, "\tDRRS Supported : No");
3453 static int i915_drrs_status(struct seq_file *m, void *unused)
3455 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3456 struct drm_device *dev = &dev_priv->drm;
3457 struct intel_crtc *intel_crtc;
3458 int active_crtc_cnt = 0;
3460 drm_modeset_lock_all(dev);
3461 for_each_intel_crtc(dev, intel_crtc) {
3462 if (intel_crtc->base.state->active) {
3464 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3466 drrs_status_per_crtc(m, dev, intel_crtc);
3469 drm_modeset_unlock_all(dev);
3471 if (!active_crtc_cnt)
3472 seq_puts(m, "No active crtc found\n");
3477 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3479 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3480 struct drm_device *dev = &dev_priv->drm;
3481 struct intel_encoder *intel_encoder;
3482 struct intel_digital_port *intel_dig_port;
3483 struct drm_connector *connector;
3484 struct drm_connector_list_iter conn_iter;
3486 drm_connector_list_iter_begin(dev, &conn_iter);
3487 drm_for_each_connector_iter(connector, &conn_iter) {
3488 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3491 intel_encoder = intel_attached_encoder(connector);
3492 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3495 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3496 if (!intel_dig_port->dp.can_mst)
3499 seq_printf(m, "MST Source Port %c\n",
3500 port_name(intel_dig_port->base.port));
3501 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3503 drm_connector_list_iter_end(&conn_iter);
3508 static ssize_t i915_displayport_test_active_write(struct file *file,
3509 const char __user *ubuf,
3510 size_t len, loff_t *offp)
3514 struct drm_device *dev;
3515 struct drm_connector *connector;
3516 struct drm_connector_list_iter conn_iter;
3517 struct intel_dp *intel_dp;
3520 dev = ((struct seq_file *)file->private_data)->private;
3525 input_buffer = memdup_user_nul(ubuf, len);
3526 if (IS_ERR(input_buffer))
3527 return PTR_ERR(input_buffer);
3529 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3531 drm_connector_list_iter_begin(dev, &conn_iter);
3532 drm_for_each_connector_iter(connector, &conn_iter) {
3533 struct intel_encoder *encoder;
3535 if (connector->connector_type !=
3536 DRM_MODE_CONNECTOR_DisplayPort)
3539 encoder = to_intel_encoder(connector->encoder);
3540 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3543 if (encoder && connector->status == connector_status_connected) {
3544 intel_dp = enc_to_intel_dp(&encoder->base);
3545 status = kstrtoint(input_buffer, 10, &val);
3548 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3549 /* To prevent erroneous activation of the compliance
3550 * testing code, only accept an actual value of 1 here
3553 intel_dp->compliance.test_active = 1;
3555 intel_dp->compliance.test_active = 0;
3558 drm_connector_list_iter_end(&conn_iter);
3559 kfree(input_buffer);
3567 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3569 struct drm_device *dev = m->private;
3570 struct drm_connector *connector;
3571 struct drm_connector_list_iter conn_iter;
3572 struct intel_dp *intel_dp;
3574 drm_connector_list_iter_begin(dev, &conn_iter);
3575 drm_for_each_connector_iter(connector, &conn_iter) {
3576 struct intel_encoder *encoder;
3578 if (connector->connector_type !=
3579 DRM_MODE_CONNECTOR_DisplayPort)
3582 encoder = to_intel_encoder(connector->encoder);
3583 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3586 if (encoder && connector->status == connector_status_connected) {
3587 intel_dp = enc_to_intel_dp(&encoder->base);
3588 if (intel_dp->compliance.test_active)
3595 drm_connector_list_iter_end(&conn_iter);
3600 static int i915_displayport_test_active_open(struct inode *inode,
3603 struct drm_i915_private *dev_priv = inode->i_private;
3605 return single_open(file, i915_displayport_test_active_show,
3609 static const struct file_operations i915_displayport_test_active_fops = {
3610 .owner = THIS_MODULE,
3611 .open = i915_displayport_test_active_open,
3613 .llseek = seq_lseek,
3614 .release = single_release,
3615 .write = i915_displayport_test_active_write
3618 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3620 struct drm_device *dev = m->private;
3621 struct drm_connector *connector;
3622 struct drm_connector_list_iter conn_iter;
3623 struct intel_dp *intel_dp;
3625 drm_connector_list_iter_begin(dev, &conn_iter);
3626 drm_for_each_connector_iter(connector, &conn_iter) {
3627 struct intel_encoder *encoder;
3629 if (connector->connector_type !=
3630 DRM_MODE_CONNECTOR_DisplayPort)
3633 encoder = to_intel_encoder(connector->encoder);
3634 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3637 if (encoder && connector->status == connector_status_connected) {
3638 intel_dp = enc_to_intel_dp(&encoder->base);
3639 if (intel_dp->compliance.test_type ==
3640 DP_TEST_LINK_EDID_READ)
3641 seq_printf(m, "%lx",
3642 intel_dp->compliance.test_data.edid);
3643 else if (intel_dp->compliance.test_type ==
3644 DP_TEST_LINK_VIDEO_PATTERN) {
3645 seq_printf(m, "hdisplay: %d\n",
3646 intel_dp->compliance.test_data.hdisplay);
3647 seq_printf(m, "vdisplay: %d\n",
3648 intel_dp->compliance.test_data.vdisplay);
3649 seq_printf(m, "bpc: %u\n",
3650 intel_dp->compliance.test_data.bpc);
3655 drm_connector_list_iter_end(&conn_iter);
3659 static int i915_displayport_test_data_open(struct inode *inode,
3662 struct drm_i915_private *dev_priv = inode->i_private;
3664 return single_open(file, i915_displayport_test_data_show,
3668 static const struct file_operations i915_displayport_test_data_fops = {
3669 .owner = THIS_MODULE,
3670 .open = i915_displayport_test_data_open,
3672 .llseek = seq_lseek,
3673 .release = single_release
3676 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3678 struct drm_device *dev = m->private;
3679 struct drm_connector *connector;
3680 struct drm_connector_list_iter conn_iter;
3681 struct intel_dp *intel_dp;
3683 drm_connector_list_iter_begin(dev, &conn_iter);
3684 drm_for_each_connector_iter(connector, &conn_iter) {
3685 struct intel_encoder *encoder;
3687 if (connector->connector_type !=
3688 DRM_MODE_CONNECTOR_DisplayPort)
3691 encoder = to_intel_encoder(connector->encoder);
3692 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3695 if (encoder && connector->status == connector_status_connected) {
3696 intel_dp = enc_to_intel_dp(&encoder->base);
3697 seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3701 drm_connector_list_iter_end(&conn_iter);
3706 static int i915_displayport_test_type_open(struct inode *inode,
3709 struct drm_i915_private *dev_priv = inode->i_private;
3711 return single_open(file, i915_displayport_test_type_show,
3715 static const struct file_operations i915_displayport_test_type_fops = {
3716 .owner = THIS_MODULE,
3717 .open = i915_displayport_test_type_open,
3719 .llseek = seq_lseek,
3720 .release = single_release
3723 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3725 struct drm_i915_private *dev_priv = m->private;
3726 struct drm_device *dev = &dev_priv->drm;
3730 if (IS_CHERRYVIEW(dev_priv))
3732 else if (IS_VALLEYVIEW(dev_priv))
3734 else if (IS_G4X(dev_priv))
3737 num_levels = ilk_wm_max_level(dev_priv) + 1;
3739 drm_modeset_lock_all(dev);
3741 for (level = 0; level < num_levels; level++) {
3742 unsigned int latency = wm[level];
3745 * - WM1+ latency values in 0.5us units
3746 * - latencies are in us on gen9/vlv/chv
3748 if (INTEL_GEN(dev_priv) >= 9 ||
3749 IS_VALLEYVIEW(dev_priv) ||
3750 IS_CHERRYVIEW(dev_priv) ||
3756 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3757 level, wm[level], latency / 10, latency % 10);
3760 drm_modeset_unlock_all(dev);
3763 static int pri_wm_latency_show(struct seq_file *m, void *data)
3765 struct drm_i915_private *dev_priv = m->private;
3766 const uint16_t *latencies;
3768 if (INTEL_GEN(dev_priv) >= 9)
3769 latencies = dev_priv->wm.skl_latency;
3771 latencies = dev_priv->wm.pri_latency;
3773 wm_latency_show(m, latencies);
3778 static int spr_wm_latency_show(struct seq_file *m, void *data)
3780 struct drm_i915_private *dev_priv = m->private;
3781 const uint16_t *latencies;
3783 if (INTEL_GEN(dev_priv) >= 9)
3784 latencies = dev_priv->wm.skl_latency;
3786 latencies = dev_priv->wm.spr_latency;
3788 wm_latency_show(m, latencies);
3793 static int cur_wm_latency_show(struct seq_file *m, void *data)
3795 struct drm_i915_private *dev_priv = m->private;
3796 const uint16_t *latencies;
3798 if (INTEL_GEN(dev_priv) >= 9)
3799 latencies = dev_priv->wm.skl_latency;
3801 latencies = dev_priv->wm.cur_latency;
3803 wm_latency_show(m, latencies);
3808 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3810 struct drm_i915_private *dev_priv = inode->i_private;
3812 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3815 return single_open(file, pri_wm_latency_show, dev_priv);
3818 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3820 struct drm_i915_private *dev_priv = inode->i_private;
3822 if (HAS_GMCH_DISPLAY(dev_priv))
3825 return single_open(file, spr_wm_latency_show, dev_priv);
3828 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3830 struct drm_i915_private *dev_priv = inode->i_private;
3832 if (HAS_GMCH_DISPLAY(dev_priv))
3835 return single_open(file, cur_wm_latency_show, dev_priv);
3838 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3839 size_t len, loff_t *offp, uint16_t wm[8])
3841 struct seq_file *m = file->private_data;
3842 struct drm_i915_private *dev_priv = m->private;
3843 struct drm_device *dev = &dev_priv->drm;
3844 uint16_t new[8] = { 0 };
3850 if (IS_CHERRYVIEW(dev_priv))
3852 else if (IS_VALLEYVIEW(dev_priv))
3854 else if (IS_G4X(dev_priv))
3857 num_levels = ilk_wm_max_level(dev_priv) + 1;
3859 if (len >= sizeof(tmp))
3862 if (copy_from_user(tmp, ubuf, len))
3867 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3868 &new[0], &new[1], &new[2], &new[3],
3869 &new[4], &new[5], &new[6], &new[7]);
3870 if (ret != num_levels)
3873 drm_modeset_lock_all(dev);
3875 for (level = 0; level < num_levels; level++)
3876 wm[level] = new[level];
3878 drm_modeset_unlock_all(dev);
3884 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3885 size_t len, loff_t *offp)
3887 struct seq_file *m = file->private_data;
3888 struct drm_i915_private *dev_priv = m->private;
3889 uint16_t *latencies;
3891 if (INTEL_GEN(dev_priv) >= 9)
3892 latencies = dev_priv->wm.skl_latency;
3894 latencies = dev_priv->wm.pri_latency;
3896 return wm_latency_write(file, ubuf, len, offp, latencies);
3899 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3900 size_t len, loff_t *offp)
3902 struct seq_file *m = file->private_data;
3903 struct drm_i915_private *dev_priv = m->private;
3904 uint16_t *latencies;
3906 if (INTEL_GEN(dev_priv) >= 9)
3907 latencies = dev_priv->wm.skl_latency;
3909 latencies = dev_priv->wm.spr_latency;
3911 return wm_latency_write(file, ubuf, len, offp, latencies);
3914 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3915 size_t len, loff_t *offp)
3917 struct seq_file *m = file->private_data;
3918 struct drm_i915_private *dev_priv = m->private;
3919 uint16_t *latencies;
3921 if (INTEL_GEN(dev_priv) >= 9)
3922 latencies = dev_priv->wm.skl_latency;
3924 latencies = dev_priv->wm.cur_latency;
3926 return wm_latency_write(file, ubuf, len, offp, latencies);
3929 static const struct file_operations i915_pri_wm_latency_fops = {
3930 .owner = THIS_MODULE,
3931 .open = pri_wm_latency_open,
3933 .llseek = seq_lseek,
3934 .release = single_release,
3935 .write = pri_wm_latency_write
3938 static const struct file_operations i915_spr_wm_latency_fops = {
3939 .owner = THIS_MODULE,
3940 .open = spr_wm_latency_open,
3942 .llseek = seq_lseek,
3943 .release = single_release,
3944 .write = spr_wm_latency_write
3947 static const struct file_operations i915_cur_wm_latency_fops = {
3948 .owner = THIS_MODULE,
3949 .open = cur_wm_latency_open,
3951 .llseek = seq_lseek,
3952 .release = single_release,
3953 .write = cur_wm_latency_write
3957 i915_wedged_get(void *data, u64 *val)
3959 struct drm_i915_private *dev_priv = data;
3961 *val = i915_terminally_wedged(&dev_priv->gpu_error);
3967 i915_wedged_set(void *data, u64 val)
3969 struct drm_i915_private *i915 = data;
3970 struct intel_engine_cs *engine;
3974 * There is no safeguard against this debugfs entry colliding
3975 * with the hangcheck calling same i915_handle_error() in
3976 * parallel, causing an explosion. For now we assume that the
3977 * test harness is responsible enough not to inject gpu hangs
3978 * while it is writing to 'i915_wedged'
3981 if (i915_reset_backoff(&i915->gpu_error))
3984 for_each_engine_masked(engine, i915, val, tmp) {
3985 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
3986 engine->hangcheck.stalled = true;
3989 i915_handle_error(i915, val, "Manually set wedged engine mask = %llx",
3992 wait_on_bit(&i915->gpu_error.flags,
3994 TASK_UNINTERRUPTIBLE);
3999 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4000 i915_wedged_get, i915_wedged_set,
4004 fault_irq_set(struct drm_i915_private *i915,
4010 err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4014 err = i915_gem_wait_for_idle(i915,
4016 I915_WAIT_INTERRUPTIBLE);
4021 mutex_unlock(&i915->drm.struct_mutex);
4023 /* Flush idle worker to disarm irq */
4024 drain_delayed_work(&i915->gt.idle_work);
4029 mutex_unlock(&i915->drm.struct_mutex);
4034 i915_ring_missed_irq_get(void *data, u64 *val)
4036 struct drm_i915_private *dev_priv = data;
4038 *val = dev_priv->gpu_error.missed_irq_rings;
4043 i915_ring_missed_irq_set(void *data, u64 val)
4045 struct drm_i915_private *i915 = data;
4047 return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4050 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4051 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4055 i915_ring_test_irq_get(void *data, u64 *val)
4057 struct drm_i915_private *dev_priv = data;
4059 *val = dev_priv->gpu_error.test_irq_rings;
4065 i915_ring_test_irq_set(void *data, u64 val)
4067 struct drm_i915_private *i915 = data;
4069 val &= INTEL_INFO(i915)->ring_mask;
4070 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4072 return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4075 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4076 i915_ring_test_irq_get, i915_ring_test_irq_set,
4079 #define DROP_UNBOUND BIT(0)
4080 #define DROP_BOUND BIT(1)
4081 #define DROP_RETIRE BIT(2)
4082 #define DROP_ACTIVE BIT(3)
4083 #define DROP_FREED BIT(4)
4084 #define DROP_SHRINK_ALL BIT(5)
4085 #define DROP_IDLE BIT(6)
4086 #define DROP_ALL (DROP_UNBOUND | \
4094 i915_drop_caches_get(void *data, u64 *val)
4102 i915_drop_caches_set(void *data, u64 val)
4104 struct drm_i915_private *dev_priv = data;
4105 struct drm_device *dev = &dev_priv->drm;
4108 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4109 val, val & DROP_ALL);
4111 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4112 * on ioctls on -EAGAIN. */
4113 if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4114 ret = mutex_lock_interruptible(&dev->struct_mutex);
4118 if (val & DROP_ACTIVE)
4119 ret = i915_gem_wait_for_idle(dev_priv,
4120 I915_WAIT_INTERRUPTIBLE |
4123 if (val & DROP_RETIRE)
4124 i915_retire_requests(dev_priv);
4126 mutex_unlock(&dev->struct_mutex);
4129 fs_reclaim_acquire(GFP_KERNEL);
4130 if (val & DROP_BOUND)
4131 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4133 if (val & DROP_UNBOUND)
4134 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4136 if (val & DROP_SHRINK_ALL)
4137 i915_gem_shrink_all(dev_priv);
4138 fs_reclaim_release(GFP_KERNEL);
4140 if (val & DROP_IDLE)
4141 drain_delayed_work(&dev_priv->gt.idle_work);
4143 if (val & DROP_FREED)
4144 i915_gem_drain_freed_objects(dev_priv);
4149 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4150 i915_drop_caches_get, i915_drop_caches_set,
4154 i915_max_freq_get(void *data, u64 *val)
4156 struct drm_i915_private *dev_priv = data;
4158 if (INTEL_GEN(dev_priv) < 6)
4161 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4166 i915_max_freq_set(void *data, u64 val)
4168 struct drm_i915_private *dev_priv = data;
4169 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4173 if (INTEL_GEN(dev_priv) < 6)
4176 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4178 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4183 * Turbo will still be enabled, but won't go above the set value.
4185 val = intel_freq_opcode(dev_priv, val);
4187 hw_max = rps->max_freq;
4188 hw_min = rps->min_freq;
4190 if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4191 mutex_unlock(&dev_priv->pcu_lock);
4195 rps->max_freq_softlimit = val;
4197 if (intel_set_rps(dev_priv, val))
4198 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4200 mutex_unlock(&dev_priv->pcu_lock);
4205 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4206 i915_max_freq_get, i915_max_freq_set,
4210 i915_min_freq_get(void *data, u64 *val)
4212 struct drm_i915_private *dev_priv = data;
4214 if (INTEL_GEN(dev_priv) < 6)
4217 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4222 i915_min_freq_set(void *data, u64 val)
4224 struct drm_i915_private *dev_priv = data;
4225 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4229 if (INTEL_GEN(dev_priv) < 6)
4232 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4234 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4239 * Turbo will still be enabled, but won't go below the set value.
4241 val = intel_freq_opcode(dev_priv, val);
4243 hw_max = rps->max_freq;
4244 hw_min = rps->min_freq;
4247 val > hw_max || val > rps->max_freq_softlimit) {
4248 mutex_unlock(&dev_priv->pcu_lock);
4252 rps->min_freq_softlimit = val;
4254 if (intel_set_rps(dev_priv, val))
4255 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4257 mutex_unlock(&dev_priv->pcu_lock);
4262 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4263 i915_min_freq_get, i915_min_freq_set,
4267 i915_cache_sharing_get(void *data, u64 *val)
4269 struct drm_i915_private *dev_priv = data;
4272 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4275 intel_runtime_pm_get(dev_priv);
4277 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4279 intel_runtime_pm_put(dev_priv);
4281 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4287 i915_cache_sharing_set(void *data, u64 val)
4289 struct drm_i915_private *dev_priv = data;
4292 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4298 intel_runtime_pm_get(dev_priv);
4299 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4301 /* Update the cache sharing policy here as well */
4302 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4303 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4304 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4305 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4307 intel_runtime_pm_put(dev_priv);
4311 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4312 i915_cache_sharing_get, i915_cache_sharing_set,
4315 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4316 struct sseu_dev_info *sseu)
4320 u32 sig1[ss_max], sig2[ss_max];
4322 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4323 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4324 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4325 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4327 for (ss = 0; ss < ss_max; ss++) {
4328 unsigned int eu_cnt;
4330 if (sig1[ss] & CHV_SS_PG_ENABLE)
4331 /* skip disabled subslice */
4334 sseu->slice_mask = BIT(0);
4335 sseu->subslice_mask[0] |= BIT(ss);
4336 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4337 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4338 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4339 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4340 sseu->eu_total += eu_cnt;
4341 sseu->eu_per_subslice = max_t(unsigned int,
4342 sseu->eu_per_subslice, eu_cnt);
4346 static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
4347 struct sseu_dev_info *sseu)
4349 const struct intel_device_info *info = INTEL_INFO(dev_priv);
4351 u32 s_reg[info->sseu.max_slices];
4352 u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
4354 for (s = 0; s < info->sseu.max_slices; s++) {
4356 * FIXME: Valid SS Mask respects the spec and read
4357 * only valid bits for those registers, excluding reserverd
4358 * although this seems wrong because it would leave many
4359 * subslices without ACK.
4361 s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
4362 GEN10_PGCTL_VALID_SS_MASK(s);
4363 eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
4364 eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
4367 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4368 GEN9_PGCTL_SSA_EU19_ACK |
4369 GEN9_PGCTL_SSA_EU210_ACK |
4370 GEN9_PGCTL_SSA_EU311_ACK;
4371 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4372 GEN9_PGCTL_SSB_EU19_ACK |
4373 GEN9_PGCTL_SSB_EU210_ACK |
4374 GEN9_PGCTL_SSB_EU311_ACK;
4376 for (s = 0; s < info->sseu.max_slices; s++) {
4377 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4378 /* skip disabled slice */
4381 sseu->slice_mask |= BIT(s);
4382 sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
4384 for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4385 unsigned int eu_cnt;
4387 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4388 /* skip disabled subslice */
4391 eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
4393 sseu->eu_total += eu_cnt;
4394 sseu->eu_per_subslice = max_t(unsigned int,
4395 sseu->eu_per_subslice,
4401 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4402 struct sseu_dev_info *sseu)
4404 const struct intel_device_info *info = INTEL_INFO(dev_priv);
4406 u32 s_reg[info->sseu.max_slices];
4407 u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
4409 for (s = 0; s < info->sseu.max_slices; s++) {
4410 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4411 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4412 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4415 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4416 GEN9_PGCTL_SSA_EU19_ACK |
4417 GEN9_PGCTL_SSA_EU210_ACK |
4418 GEN9_PGCTL_SSA_EU311_ACK;
4419 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4420 GEN9_PGCTL_SSB_EU19_ACK |
4421 GEN9_PGCTL_SSB_EU210_ACK |
4422 GEN9_PGCTL_SSB_EU311_ACK;
4424 for (s = 0; s < info->sseu.max_slices; s++) {
4425 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4426 /* skip disabled slice */
4429 sseu->slice_mask |= BIT(s);
4431 if (IS_GEN9_BC(dev_priv))
4432 sseu->subslice_mask[s] =
4433 INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4435 for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4436 unsigned int eu_cnt;
4438 if (IS_GEN9_LP(dev_priv)) {
4439 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4440 /* skip disabled subslice */
4443 sseu->subslice_mask[s] |= BIT(ss);
4446 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4448 sseu->eu_total += eu_cnt;
4449 sseu->eu_per_subslice = max_t(unsigned int,
4450 sseu->eu_per_subslice,
4456 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4457 struct sseu_dev_info *sseu)
4459 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4462 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4464 if (sseu->slice_mask) {
4465 sseu->eu_per_subslice =
4466 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4467 for (s = 0; s < fls(sseu->slice_mask); s++) {
4468 sseu->subslice_mask[s] =
4469 INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4471 sseu->eu_total = sseu->eu_per_subslice *
4472 sseu_subslice_total(sseu);
4474 /* subtract fused off EU(s) from enabled slice(s) */
4475 for (s = 0; s < fls(sseu->slice_mask); s++) {
4477 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4479 sseu->eu_total -= hweight8(subslice_7eu);
4484 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4485 const struct sseu_dev_info *sseu)
4487 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4488 const char *type = is_available_info ? "Available" : "Enabled";
4491 seq_printf(m, " %s Slice Mask: %04x\n", type,
4493 seq_printf(m, " %s Slice Total: %u\n", type,
4494 hweight8(sseu->slice_mask));
4495 seq_printf(m, " %s Subslice Total: %u\n", type,
4496 sseu_subslice_total(sseu));
4497 for (s = 0; s < fls(sseu->slice_mask); s++) {
4498 seq_printf(m, " %s Slice%i subslices: %u\n", type,
4499 s, hweight8(sseu->subslice_mask[s]));
4501 seq_printf(m, " %s EU Total: %u\n", type,
4503 seq_printf(m, " %s EU Per Subslice: %u\n", type,
4504 sseu->eu_per_subslice);
4506 if (!is_available_info)
4509 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4510 if (HAS_POOLED_EU(dev_priv))
4511 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
4513 seq_printf(m, " Has Slice Power Gating: %s\n",
4514 yesno(sseu->has_slice_pg));
4515 seq_printf(m, " Has Subslice Power Gating: %s\n",
4516 yesno(sseu->has_subslice_pg));
4517 seq_printf(m, " Has EU Power Gating: %s\n",
4518 yesno(sseu->has_eu_pg));
4521 static int i915_sseu_status(struct seq_file *m, void *unused)
4523 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4524 struct sseu_dev_info sseu;
4526 if (INTEL_GEN(dev_priv) < 8)
4529 seq_puts(m, "SSEU Device Info\n");
4530 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4532 seq_puts(m, "SSEU Device Status\n");
4533 memset(&sseu, 0, sizeof(sseu));
4534 sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
4535 sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
4536 sseu.max_eus_per_subslice =
4537 INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
4539 intel_runtime_pm_get(dev_priv);
4541 if (IS_CHERRYVIEW(dev_priv)) {
4542 cherryview_sseu_device_status(dev_priv, &sseu);
4543 } else if (IS_BROADWELL(dev_priv)) {
4544 broadwell_sseu_device_status(dev_priv, &sseu);
4545 } else if (IS_GEN9(dev_priv)) {
4546 gen9_sseu_device_status(dev_priv, &sseu);
4547 } else if (INTEL_GEN(dev_priv) >= 10) {
4548 gen10_sseu_device_status(dev_priv, &sseu);
4551 intel_runtime_pm_put(dev_priv);
4553 i915_print_sseu_info(m, false, &sseu);
4558 static int i915_forcewake_open(struct inode *inode, struct file *file)
4560 struct drm_i915_private *i915 = inode->i_private;
4562 if (INTEL_GEN(i915) < 6)
4565 intel_runtime_pm_get(i915);
4566 intel_uncore_forcewake_user_get(i915);
4571 static int i915_forcewake_release(struct inode *inode, struct file *file)
4573 struct drm_i915_private *i915 = inode->i_private;
4575 if (INTEL_GEN(i915) < 6)
4578 intel_uncore_forcewake_user_put(i915);
4579 intel_runtime_pm_put(i915);
4584 static const struct file_operations i915_forcewake_fops = {
4585 .owner = THIS_MODULE,
4586 .open = i915_forcewake_open,
4587 .release = i915_forcewake_release,
4590 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4592 struct drm_i915_private *dev_priv = m->private;
4593 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4595 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4596 seq_printf(m, "Detected: %s\n",
4597 yesno(delayed_work_pending(&hotplug->reenable_work)));
4602 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4603 const char __user *ubuf, size_t len,
4606 struct seq_file *m = file->private_data;
4607 struct drm_i915_private *dev_priv = m->private;
4608 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4609 unsigned int new_threshold;
4614 if (len >= sizeof(tmp))
4617 if (copy_from_user(tmp, ubuf, len))
4622 /* Strip newline, if any */
4623 newline = strchr(tmp, '\n');
4627 if (strcmp(tmp, "reset") == 0)
4628 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4629 else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4632 if (new_threshold > 0)
4633 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4636 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4638 spin_lock_irq(&dev_priv->irq_lock);
4639 hotplug->hpd_storm_threshold = new_threshold;
4640 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4642 hotplug->stats[i].count = 0;
4643 spin_unlock_irq(&dev_priv->irq_lock);
4645 /* Re-enable hpd immediately if we were in an irq storm */
4646 flush_delayed_work(&dev_priv->hotplug.reenable_work);
4651 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4653 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4656 static const struct file_operations i915_hpd_storm_ctl_fops = {
4657 .owner = THIS_MODULE,
4658 .open = i915_hpd_storm_ctl_open,
4660 .llseek = seq_lseek,
4661 .release = single_release,
4662 .write = i915_hpd_storm_ctl_write
4665 static int i915_drrs_ctl_set(void *data, u64 val)
4667 struct drm_i915_private *dev_priv = data;
4668 struct drm_device *dev = &dev_priv->drm;
4669 struct intel_crtc *intel_crtc;
4670 struct intel_encoder *encoder;
4671 struct intel_dp *intel_dp;
4673 if (INTEL_GEN(dev_priv) < 7)
4676 drm_modeset_lock_all(dev);
4677 for_each_intel_crtc(dev, intel_crtc) {
4678 if (!intel_crtc->base.state->active ||
4679 !intel_crtc->config->has_drrs)
4682 for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
4683 if (encoder->type != INTEL_OUTPUT_EDP)
4686 DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
4687 val ? "en" : "dis", val);
4689 intel_dp = enc_to_intel_dp(&encoder->base);
4691 intel_edp_drrs_enable(intel_dp,
4692 intel_crtc->config);
4694 intel_edp_drrs_disable(intel_dp,
4695 intel_crtc->config);
4698 drm_modeset_unlock_all(dev);
4703 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
4705 static const struct drm_info_list i915_debugfs_list[] = {
4706 {"i915_capabilities", i915_capabilities, 0},
4707 {"i915_gem_objects", i915_gem_object_info, 0},
4708 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4709 {"i915_gem_stolen", i915_gem_stolen_list_info },
4710 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4711 {"i915_gem_interrupt", i915_interrupt_info, 0},
4712 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4713 {"i915_guc_info", i915_guc_info, 0},
4714 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4715 {"i915_guc_log_dump", i915_guc_log_dump, 0},
4716 {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4717 {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4718 {"i915_huc_load_status", i915_huc_load_status_info, 0},
4719 {"i915_frequency_info", i915_frequency_info, 0},
4720 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4721 {"i915_reset_info", i915_reset_info, 0},
4722 {"i915_drpc_info", i915_drpc_info, 0},
4723 {"i915_emon_status", i915_emon_status, 0},
4724 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4725 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4726 {"i915_fbc_status", i915_fbc_status, 0},
4727 {"i915_ips_status", i915_ips_status, 0},
4728 {"i915_sr_status", i915_sr_status, 0},
4729 {"i915_opregion", i915_opregion, 0},
4730 {"i915_vbt", i915_vbt, 0},
4731 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4732 {"i915_context_status", i915_context_status, 0},
4733 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4734 {"i915_swizzle_info", i915_swizzle_info, 0},
4735 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4736 {"i915_llc", i915_llc, 0},
4737 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4738 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4739 {"i915_energy_uJ", i915_energy_uJ, 0},
4740 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4741 {"i915_power_domain_info", i915_power_domain_info, 0},
4742 {"i915_dmc_info", i915_dmc_info, 0},
4743 {"i915_display_info", i915_display_info, 0},
4744 {"i915_engine_info", i915_engine_info, 0},
4745 {"i915_rcs_topology", i915_rcs_topology, 0},
4746 {"i915_shrinker_info", i915_shrinker_info, 0},
4747 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4748 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4749 {"i915_wa_registers", i915_wa_registers, 0},
4750 {"i915_ddb_info", i915_ddb_info, 0},
4751 {"i915_sseu_status", i915_sseu_status, 0},
4752 {"i915_drrs_status", i915_drrs_status, 0},
4753 {"i915_rps_boost_info", i915_rps_boost_info, 0},
4755 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4757 static const struct i915_debugfs_files {
4759 const struct file_operations *fops;
4760 } i915_debugfs_files[] = {
4761 {"i915_wedged", &i915_wedged_fops},
4762 {"i915_max_freq", &i915_max_freq_fops},
4763 {"i915_min_freq", &i915_min_freq_fops},
4764 {"i915_cache_sharing", &i915_cache_sharing_fops},
4765 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4766 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4767 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4768 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4769 {"i915_error_state", &i915_error_state_fops},
4770 {"i915_gpu_info", &i915_gpu_info_fops},
4772 {"i915_next_seqno", &i915_next_seqno_fops},
4773 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4774 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4775 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4776 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4777 {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4778 {"i915_dp_test_data", &i915_displayport_test_data_fops},
4779 {"i915_dp_test_type", &i915_displayport_test_type_fops},
4780 {"i915_dp_test_active", &i915_displayport_test_active_fops},
4781 {"i915_guc_log_control", &i915_guc_log_control_fops},
4782 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4783 {"i915_ipc_status", &i915_ipc_status_fops},
4784 {"i915_drrs_ctl", &i915_drrs_ctl_fops}
4787 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4789 struct drm_minor *minor = dev_priv->drm.primary;
4793 ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4794 minor->debugfs_root, to_i915(minor->dev),
4795 &i915_forcewake_fops);
4799 ret = intel_pipe_crc_create(minor);
4803 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4804 ent = debugfs_create_file(i915_debugfs_files[i].name,
4806 minor->debugfs_root,
4807 to_i915(minor->dev),
4808 i915_debugfs_files[i].fops);
4813 return drm_debugfs_create_files(i915_debugfs_list,
4814 I915_DEBUGFS_ENTRIES,
4815 minor->debugfs_root, minor);
4819 /* DPCD dump start address. */
4820 unsigned int offset;
4821 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4823 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4825 /* Only valid for eDP. */
4829 static const struct dpcd_block i915_dpcd_debug[] = {
4830 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4831 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4832 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4833 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4834 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4835 { .offset = DP_SET_POWER },
4836 { .offset = DP_EDP_DPCD_REV },
4837 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4838 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4839 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4842 static int i915_dpcd_show(struct seq_file *m, void *data)
4844 struct drm_connector *connector = m->private;
4845 struct intel_dp *intel_dp =
4846 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4851 if (connector->status != connector_status_connected)
4854 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4855 const struct dpcd_block *b = &i915_dpcd_debug[i];
4856 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4859 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4862 /* low tech for now */
4863 if (WARN_ON(size > sizeof(buf)))
4866 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4868 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4869 size, b->offset, err);
4873 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4879 static int i915_dpcd_open(struct inode *inode, struct file *file)
4881 return single_open(file, i915_dpcd_show, inode->i_private);
4884 static const struct file_operations i915_dpcd_fops = {
4885 .owner = THIS_MODULE,
4886 .open = i915_dpcd_open,
4888 .llseek = seq_lseek,
4889 .release = single_release,
4892 static int i915_panel_show(struct seq_file *m, void *data)
4894 struct drm_connector *connector = m->private;
4895 struct intel_dp *intel_dp =
4896 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4898 if (connector->status != connector_status_connected)
4901 seq_printf(m, "Panel power up delay: %d\n",
4902 intel_dp->panel_power_up_delay);
4903 seq_printf(m, "Panel power down delay: %d\n",
4904 intel_dp->panel_power_down_delay);
4905 seq_printf(m, "Backlight on delay: %d\n",
4906 intel_dp->backlight_on_delay);
4907 seq_printf(m, "Backlight off delay: %d\n",
4908 intel_dp->backlight_off_delay);
4913 static int i915_panel_open(struct inode *inode, struct file *file)
4915 return single_open(file, i915_panel_show, inode->i_private);
4918 static const struct file_operations i915_panel_fops = {
4919 .owner = THIS_MODULE,
4920 .open = i915_panel_open,
4922 .llseek = seq_lseek,
4923 .release = single_release,
4927 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4928 * @connector: pointer to a registered drm_connector
4930 * Cleanup will be done by drm_connector_unregister() through a call to
4931 * drm_debugfs_connector_remove().
4933 * Returns 0 on success, negative error codes on error.
4935 int i915_debugfs_connector_add(struct drm_connector *connector)
4937 struct dentry *root = connector->debugfs_entry;
4939 /* The connector must have been registered beforehands. */
4943 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4944 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4945 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4946 connector, &i915_dpcd_fops);
4948 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4949 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4950 connector, &i915_panel_fops);