drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include <linux/sched/mm.h>
  32 #include "intel_drv.h"
  33 #include "intel_guc_submission.h"
  34
  35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  36 {
  37         return to_i915(node->minor->dev);
  38 }
  39
  40 static int i915_capabilities(struct seq_file *m, void *data)
  41 {
  42         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  43         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  44         struct drm_printer p = drm_seq_file_printer(m);
  45
  46         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  47         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  48         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  49
  50         intel_device_info_dump_flags(info, &p);
  51         intel_device_info_dump_runtime(info, &p);
  52         intel_driver_caps_print(&dev_priv->caps, &p);
  53
  54         kernel_param_lock(THIS_MODULE);
  55         i915_params_dump(&i915_modparams, &p);
  56         kernel_param_unlock(THIS_MODULE);
  57
  58         return 0;
  59 }
  60
  61 static char get_active_flag(struct drm_i915_gem_object *obj)
  62 {
  63         return i915_gem_object_is_active(obj) ? '*' : ' ';
  64 }
  65
  66 static char get_pin_flag(struct drm_i915_gem_object *obj)
  67 {
  68         return obj->pin_global ? 'p' : ' ';
  69 }
  70
  71 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  72 {
  73         switch (i915_gem_object_get_tiling(obj)) {
  74         default:
  75         case I915_TILING_NONE: return ' ';
  76         case I915_TILING_X: return 'X';
  77         case I915_TILING_Y: return 'Y';
  78         }
  79 }
  80
  81 static char get_global_flag(struct drm_i915_gem_object *obj)
  82 {
  83         return obj->userfault_count ? 'g' : ' ';
  84 }
  85
  86 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
  87 {
  88         return obj->mm.mapping ? 'M' : ' ';
  89 }
  90
  91 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
  92 {
  93         u64 size = 0;
  94         struct i915_vma *vma;
  95
  96         for_each_ggtt_vma(vma, obj) {
  97                 if (drm_mm_node_allocated(&vma->node))
  98                         size += vma->node.size;
  99         }
 100
 101         return size;
 102 }
 103
 104 static const char *
 105 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
 106 {
 107         size_t x = 0;
 108
 109         switch (page_sizes) {
 110         case 0:
 111                 return "";
 112         case I915_GTT_PAGE_SIZE_4K:
 113                 return "4K";
 114         case I915_GTT_PAGE_SIZE_64K:
 115                 return "64K";
 116         case I915_GTT_PAGE_SIZE_2M:
 117                 return "2M";
 118         default:
 119                 if (!buf)
 120                         return "M";
 121
 122                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 123                         x += snprintf(buf + x, len - x, "2M, ");
 124                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 125                         x += snprintf(buf + x, len - x, "64K, ");
 126                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 127                         x += snprintf(buf + x, len - x, "4K, ");
 128                 buf[x-2] = '\0';
 129
 130                 return buf;
 131         }
 132 }
 133
 134 static void
 135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 138         struct intel_engine_cs *engine;
 139         struct i915_vma *vma;
 140         unsigned int frontbuffer_bits;
 141         int pin_count = 0;
 142
 143         lockdep_assert_held(&obj->base.dev->struct_mutex);
 144
 145         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 146                    &obj->base,
 147                    get_active_flag(obj),
 148                    get_pin_flag(obj),
 149                    get_tiling_flag(obj),
 150                    get_global_flag(obj),
 151                    get_pin_mapped_flag(obj),
 152                    obj->base.size / 1024,
 153                    obj->base.read_domains,
 154                    obj->base.write_domain,
 155                    i915_cache_level_str(dev_priv, obj->cache_level),
 156                    obj->mm.dirty ? " dirty" : "",
 157                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 158         if (obj->base.name)
 159                 seq_printf(m, " (name: %d)", obj->base.name);
 160         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 161                 if (i915_vma_is_pinned(vma))
 162                         pin_count++;
 163         }
 164         seq_printf(m, " (pinned x %d)", pin_count);
 165         if (obj->pin_global)
 166                 seq_printf(m, " (global)");
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (!drm_mm_node_allocated(&vma->node))
 169                         continue;
 170
 171                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 172                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 173                            vma->node.start, vma->node.size,
 174                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 175                 if (i915_vma_is_ggtt(vma)) {
 176                         switch (vma->ggtt_view.type) {
 177                         case I915_GGTT_VIEW_NORMAL:
 178                                 seq_puts(m, ", normal");
 179                                 break;
 180
 181                         case I915_GGTT_VIEW_PARTIAL:
 182                                 seq_printf(m, ", partial [%08llx+%x]",
 183                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 184                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 185                                 break;
 186
 187                         case I915_GGTT_VIEW_ROTATED:
 188                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 189                                            vma->ggtt_view.rotated.plane[0].width,
 190                                            vma->ggtt_view.rotated.plane[0].height,
 191                                            vma->ggtt_view.rotated.plane[0].stride,
 192                                            vma->ggtt_view.rotated.plane[0].offset,
 193                                            vma->ggtt_view.rotated.plane[1].width,
 194                                            vma->ggtt_view.rotated.plane[1].height,
 195                                            vma->ggtt_view.rotated.plane[1].stride,
 196                                            vma->ggtt_view.rotated.plane[1].offset);
 197                                 break;
 198
 199                         default:
 200                                 MISSING_CASE(vma->ggtt_view.type);
 201                                 break;
 202                         }
 203                 }
 204                 if (vma->fence)
 205                         seq_printf(m, " , fence: %d%s",
 206                                    vma->fence->id,
 207                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 208                 seq_puts(m, ")");
 209         }
 210         if (obj->stolen)
 211                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 212
 213         engine = i915_gem_object_last_write_engine(obj);
 214         if (engine)
 215                 seq_printf(m, " (%s)", engine->name);
 216
 217         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 218         if (frontbuffer_bits)
 219                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 220 }
 221
 222 static int obj_rank_by_stolen(const void *A, const void *B)
 223 {
 224         const struct drm_i915_gem_object *a =
 225                 *(const struct drm_i915_gem_object **)A;
 226         const struct drm_i915_gem_object *b =
 227                 *(const struct drm_i915_gem_object **)B;
 228
 229         if (a->stolen->start < b->stolen->start)
 230                 return -1;
 231         if (a->stolen->start > b->stolen->start)
 232                 return 1;
 233         return 0;
 234 }
 235
 236 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 237 {
 238         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 239         struct drm_device *dev = &dev_priv->drm;
 240         struct drm_i915_gem_object **objects;
 241         struct drm_i915_gem_object *obj;
 242         u64 total_obj_size, total_gtt_size;
 243         unsigned long total, count, n;
 244         int ret;
 245
 246         total = READ_ONCE(dev_priv->mm.object_count);
 247         objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
 248         if (!objects)
 249                 return -ENOMEM;
 250
 251         ret = mutex_lock_interruptible(&dev->struct_mutex);
 252         if (ret)
 253                 goto out;
 254
 255         total_obj_size = total_gtt_size = count = 0;
 256
 257         spin_lock(&dev_priv->mm.obj_lock);
 258         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 259                 if (count == total)
 260                         break;
 261
 262                 if (obj->stolen == NULL)
 263                         continue;
 264
 265                 objects[count++] = obj;
 266                 total_obj_size += obj->base.size;
 267                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 268
 269         }
 270         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 271                 if (count == total)
 272                         break;
 273
 274                 if (obj->stolen == NULL)
 275                         continue;
 276
 277                 objects[count++] = obj;
 278                 total_obj_size += obj->base.size;
 279         }
 280         spin_unlock(&dev_priv->mm.obj_lock);
 281
 282         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 283
 284         seq_puts(m, "Stolen:\n");
 285         for (n = 0; n < count; n++) {
 286                 seq_puts(m, "   ");
 287                 describe_obj(m, objects[n]);
 288                 seq_putc(m, '\n');
 289         }
 290         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 291                    count, total_obj_size, total_gtt_size);
 292
 293         mutex_unlock(&dev->struct_mutex);
 294 out:
 295         kvfree(objects);
 296         return ret;
 297 }
 298
 299 struct file_stats {
 300         struct drm_i915_file_private *file_priv;
 301         unsigned long count;
 302         u64 total, unbound;
 303         u64 global, shared;
 304         u64 active, inactive;
 305 };
 306
 307 static int per_file_stats(int id, void *ptr, void *data)
 308 {
 309         struct drm_i915_gem_object *obj = ptr;
 310         struct file_stats *stats = data;
 311         struct i915_vma *vma;
 312
 313         lockdep_assert_held(&obj->base.dev->struct_mutex);
 314
 315         stats->count++;
 316         stats->total += obj->base.size;
 317         if (!obj->bind_count)
 318                 stats->unbound += obj->base.size;
 319         if (obj->base.name || obj->base.dma_buf)
 320                 stats->shared += obj->base.size;
 321
 322         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 323                 if (!drm_mm_node_allocated(&vma->node))
 324                         continue;
 325
 326                 if (i915_vma_is_ggtt(vma)) {
 327                         stats->global += vma->node.size;
 328                 } else {
 329                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 330
 331                         if (ppgtt->base.file != stats->file_priv)
 332                                 continue;
 333                 }
 334
 335                 if (i915_vma_is_active(vma))
 336                         stats->active += vma->node.size;
 337                 else
 338                         stats->inactive += vma->node.size;
 339         }
 340
 341         return 0;
 342 }
 343
 344 #define print_file_stats(m, name, stats) do { \
 345         if (stats.count) \
 346                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 347                            name, \
 348                            stats.count, \
 349                            stats.total, \
 350                            stats.active, \
 351                            stats.inactive, \
 352                            stats.global, \
 353                            stats.shared, \
 354                            stats.unbound); \
 355 } while (0)
 356
 357 static void print_batch_pool_stats(struct seq_file *m,
 358                                    struct drm_i915_private *dev_priv)
 359 {
 360         struct drm_i915_gem_object *obj;
 361         struct file_stats stats;
 362         struct intel_engine_cs *engine;
 363         enum intel_engine_id id;
 364         int j;
 365
 366         memset(&stats, 0, sizeof(stats));
 367
 368         for_each_engine(engine, dev_priv, id) {
 369                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 370                         list_for_each_entry(obj,
 371                                             &engine->batch_pool.cache_list[j],
 372                                             batch_pool_link)
 373                                 per_file_stats(0, obj, &stats);
 374                 }
 375         }
 376
 377         print_file_stats(m, "[k]batch pool", stats);
 378 }
 379
 380 static int per_file_ctx_stats(int id, void *ptr, void *data)
 381 {
 382         struct i915_gem_context *ctx = ptr;
 383         int n;
 384
 385         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 386                 if (ctx->engine[n].state)
 387                         per_file_stats(0, ctx->engine[n].state->obj, data);
 388                 if (ctx->engine[n].ring)
 389                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 390         }
 391
 392         return 0;
 393 }
 394
 395 static void print_context_stats(struct seq_file *m,
 396                                 struct drm_i915_private *dev_priv)
 397 {
 398         struct drm_device *dev = &dev_priv->drm;
 399         struct file_stats stats;
 400         struct drm_file *file;
 401
 402         memset(&stats, 0, sizeof(stats));
 403
 404         mutex_lock(&dev->struct_mutex);
 405         if (dev_priv->kernel_context)
 406                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 407
 408         list_for_each_entry(file, &dev->filelist, lhead) {
 409                 struct drm_i915_file_private *fpriv = file->driver_priv;
 410                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 411         }
 412         mutex_unlock(&dev->struct_mutex);
 413
 414         print_file_stats(m, "[k]contexts", stats);
 415 }
 416
 417 static int i915_gem_object_info(struct seq_file *m, void *data)
 418 {
 419         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 420         struct drm_device *dev = &dev_priv->drm;
 421         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 422         u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
 423         u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
 424         struct drm_i915_gem_object *obj;
 425         unsigned int page_sizes = 0;
 426         struct drm_file *file;
 427         char buf[80];
 428         int ret;
 429
 430         ret = mutex_lock_interruptible(&dev->struct_mutex);
 431         if (ret)
 432                 return ret;
 433
 434         seq_printf(m, "%u objects, %llu bytes\n",
 435                    dev_priv->mm.object_count,
 436                    dev_priv->mm.object_memory);
 437
 438         size = count = 0;
 439         mapped_size = mapped_count = 0;
 440         purgeable_size = purgeable_count = 0;
 441         huge_size = huge_count = 0;
 442
 443         spin_lock(&dev_priv->mm.obj_lock);
 444         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 445                 size += obj->base.size;
 446                 ++count;
 447
 448                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 449                         purgeable_size += obj->base.size;
 450                         ++purgeable_count;
 451                 }
 452
 453                 if (obj->mm.mapping) {
 454                         mapped_count++;
 455                         mapped_size += obj->base.size;
 456                 }
 457
 458                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 459                         huge_count++;
 460                         huge_size += obj->base.size;
 461                         page_sizes |= obj->mm.page_sizes.sg;
 462                 }
 463         }
 464         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 465
 466         size = count = dpy_size = dpy_count = 0;
 467         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 468                 size += obj->base.size;
 469                 ++count;
 470
 471                 if (obj->pin_global) {
 472                         dpy_size += obj->base.size;
 473                         ++dpy_count;
 474                 }
 475
 476                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 477                         purgeable_size += obj->base.size;
 478                         ++purgeable_count;
 479                 }
 480
 481                 if (obj->mm.mapping) {
 482                         mapped_count++;
 483                         mapped_size += obj->base.size;
 484                 }
 485
 486                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 487                         huge_count++;
 488                         huge_size += obj->base.size;
 489                         page_sizes |= obj->mm.page_sizes.sg;
 490                 }
 491         }
 492         spin_unlock(&dev_priv->mm.obj_lock);
 493
 494         seq_printf(m, "%u bound objects, %llu bytes\n",
 495                    count, size);
 496         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 497                    purgeable_count, purgeable_size);
 498         seq_printf(m, "%u mapped objects, %llu bytes\n",
 499                    mapped_count, mapped_size);
 500         seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
 501                    huge_count,
 502                    stringify_page_sizes(page_sizes, buf, sizeof(buf)),
 503                    huge_size);
 504         seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
 505                    dpy_count, dpy_size);
 506
 507         seq_printf(m, "%llu [%pa] gtt total\n",
 508                    ggtt->base.total, &ggtt->mappable_end);
 509         seq_printf(m, "Supported page sizes: %s\n",
 510                    stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
 511                                         buf, sizeof(buf)));
 512
 513         seq_putc(m, '\n');
 514         print_batch_pool_stats(m, dev_priv);
 515         mutex_unlock(&dev->struct_mutex);
 516
 517         mutex_lock(&dev->filelist_mutex);
 518         print_context_stats(m, dev_priv);
 519         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 520                 struct file_stats stats;
 521                 struct drm_i915_file_private *file_priv = file->driver_priv;
 522                 struct drm_i915_gem_request *request;
 523                 struct task_struct *task;
 524
 525                 mutex_lock(&dev->struct_mutex);
 526
 527                 memset(&stats, 0, sizeof(stats));
 528                 stats.file_priv = file->driver_priv;
 529                 spin_lock(&file->table_lock);
 530                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 531                 spin_unlock(&file->table_lock);
 532                 /*
 533                  * Although we have a valid reference on file->pid, that does
 534                  * not guarantee that the task_struct who called get_pid() is
 535                  * still alive (e.g. get_pid(current) => fork() => exit()).
 536                  * Therefore, we need to protect this ->comm access using RCU.
 537                  */
 538                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 539                                                    struct drm_i915_gem_request,
 540                                                    client_link);
 541                 rcu_read_lock();
 542                 task = pid_task(request && request->ctx->pid ?
 543                                 request->ctx->pid : file->pid,
 544                                 PIDTYPE_PID);
 545                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 546                 rcu_read_unlock();
 547
 548                 mutex_unlock(&dev->struct_mutex);
 549         }
 550         mutex_unlock(&dev->filelist_mutex);
 551
 552         return 0;
 553 }
 554
 555 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 556 {
 557         struct drm_info_node *node = m->private;
 558         struct drm_i915_private *dev_priv = node_to_i915(node);
 559         struct drm_device *dev = &dev_priv->drm;
 560         struct drm_i915_gem_object **objects;
 561         struct drm_i915_gem_object *obj;
 562         u64 total_obj_size, total_gtt_size;
 563         unsigned long nobject, n;
 564         int count, ret;
 565
 566         nobject = READ_ONCE(dev_priv->mm.object_count);
 567         objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
 568         if (!objects)
 569                 return -ENOMEM;
 570
 571         ret = mutex_lock_interruptible(&dev->struct_mutex);
 572         if (ret)
 573                 return ret;
 574
 575         count = 0;
 576         spin_lock(&dev_priv->mm.obj_lock);
 577         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 578                 objects[count++] = obj;
 579                 if (count == nobject)
 580                         break;
 581         }
 582         spin_unlock(&dev_priv->mm.obj_lock);
 583
 584         total_obj_size = total_gtt_size = 0;
 585         for (n = 0;  n < count; n++) {
 586                 obj = objects[n];
 587
 588                 seq_puts(m, "   ");
 589                 describe_obj(m, obj);
 590                 seq_putc(m, '\n');
 591                 total_obj_size += obj->base.size;
 592                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 593         }
 594
 595         mutex_unlock(&dev->struct_mutex);
 596
 597         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 598                    count, total_obj_size, total_gtt_size);
 599         kvfree(objects);
 600
 601         return 0;
 602 }
 603
 604 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 605 {
 606         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 607         struct drm_device *dev = &dev_priv->drm;
 608         struct drm_i915_gem_object *obj;
 609         struct intel_engine_cs *engine;
 610         enum intel_engine_id id;
 611         int total = 0;
 612         int ret, j;
 613
 614         ret = mutex_lock_interruptible(&dev->struct_mutex);
 615         if (ret)
 616                 return ret;
 617
 618         for_each_engine(engine, dev_priv, id) {
 619                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 620                         int count;
 621
 622                         count = 0;
 623                         list_for_each_entry(obj,
 624                                             &engine->batch_pool.cache_list[j],
 625                                             batch_pool_link)
 626                                 count++;
 627                         seq_printf(m, "%s cache[%d]: %d objects\n",
 628                                    engine->name, j, count);
 629
 630                         list_for_each_entry(obj,
 631                                             &engine->batch_pool.cache_list[j],
 632                                             batch_pool_link) {
 633                                 seq_puts(m, "   ");
 634                                 describe_obj(m, obj);
 635                                 seq_putc(m, '\n');
 636                         }
 637
 638                         total += count;
 639                 }
 640         }
 641
 642         seq_printf(m, "total: %d\n", total);
 643
 644         mutex_unlock(&dev->struct_mutex);
 645
 646         return 0;
 647 }
 648
 649 static int i915_interrupt_info(struct seq_file *m, void *data)
 650 {
 651         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 652         struct intel_engine_cs *engine;
 653         enum intel_engine_id id;
 654         int i, pipe;
 655
 656         intel_runtime_pm_get(dev_priv);
 657
 658         if (IS_CHERRYVIEW(dev_priv)) {
 659                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 660                            I915_READ(GEN8_MASTER_IRQ));
 661
 662                 seq_printf(m, "Display IER:\t%08x\n",
 663                            I915_READ(VLV_IER));
 664                 seq_printf(m, "Display IIR:\t%08x\n",
 665                            I915_READ(VLV_IIR));
 666                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 667                            I915_READ(VLV_IIR_RW));
 668                 seq_printf(m, "Display IMR:\t%08x\n",
 669                            I915_READ(VLV_IMR));
 670                 for_each_pipe(dev_priv, pipe) {
 671                         enum intel_display_power_domain power_domain;
 672
 673                         power_domain = POWER_DOMAIN_PIPE(pipe);
 674                         if (!intel_display_power_get_if_enabled(dev_priv,
 675                                                                 power_domain)) {
 676                                 seq_printf(m, "Pipe %c power disabled\n",
 677                                            pipe_name(pipe));
 678                                 continue;
 679                         }
 680
 681                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 682                                    pipe_name(pipe),
 683                                    I915_READ(PIPESTAT(pipe)));
 684
 685                         intel_display_power_put(dev_priv, power_domain);
 686                 }
 687
 688                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 689                 seq_printf(m, "Port hotplug:\t%08x\n",
 690                            I915_READ(PORT_HOTPLUG_EN));
 691                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 692                            I915_READ(VLV_DPFLIPSTAT));
 693                 seq_printf(m, "DPINVGTT:\t%08x\n",
 694                            I915_READ(DPINVGTT));
 695                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 696
 697                 for (i = 0; i < 4; i++) {
 698                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 699                                    i, I915_READ(GEN8_GT_IMR(i)));
 700                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 701                                    i, I915_READ(GEN8_GT_IIR(i)));
 702                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 703                                    i, I915_READ(GEN8_GT_IER(i)));
 704                 }
 705
 706                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 707                            I915_READ(GEN8_PCU_IMR));
 708                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 709                            I915_READ(GEN8_PCU_IIR));
 710                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 711                            I915_READ(GEN8_PCU_IER));
 712         } else if (INTEL_GEN(dev_priv) >= 8) {
 713                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 714                            I915_READ(GEN8_MASTER_IRQ));
 715
 716                 for (i = 0; i < 4; i++) {
 717                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 718                                    i, I915_READ(GEN8_GT_IMR(i)));
 719                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 720                                    i, I915_READ(GEN8_GT_IIR(i)));
 721                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 722                                    i, I915_READ(GEN8_GT_IER(i)));
 723                 }
 724
 725                 for_each_pipe(dev_priv, pipe) {
 726                         enum intel_display_power_domain power_domain;
 727
 728                         power_domain = POWER_DOMAIN_PIPE(pipe);
 729                         if (!intel_display_power_get_if_enabled(dev_priv,
 730                                                                 power_domain)) {
 731                                 seq_printf(m, "Pipe %c power disabled\n",
 732                                            pipe_name(pipe));
 733                                 continue;
 734                         }
 735                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 736                                    pipe_name(pipe),
 737                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 738                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 739                                    pipe_name(pipe),
 740                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 741                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 742                                    pipe_name(pipe),
 743                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 744
 745                         intel_display_power_put(dev_priv, power_domain);
 746                 }
 747
 748                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 749                            I915_READ(GEN8_DE_PORT_IMR));
 750                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 751                            I915_READ(GEN8_DE_PORT_IIR));
 752                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 753                            I915_READ(GEN8_DE_PORT_IER));
 754
 755                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 756                            I915_READ(GEN8_DE_MISC_IMR));
 757                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 758                            I915_READ(GEN8_DE_MISC_IIR));
 759                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 760                            I915_READ(GEN8_DE_MISC_IER));
 761
 762                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 763                            I915_READ(GEN8_PCU_IMR));
 764                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 765                            I915_READ(GEN8_PCU_IIR));
 766                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 767                            I915_READ(GEN8_PCU_IER));
 768         } else if (IS_VALLEYVIEW(dev_priv)) {
 769                 seq_printf(m, "Display IER:\t%08x\n",
 770                            I915_READ(VLV_IER));
 771                 seq_printf(m, "Display IIR:\t%08x\n",
 772                            I915_READ(VLV_IIR));
 773                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 774                            I915_READ(VLV_IIR_RW));
 775                 seq_printf(m, "Display IMR:\t%08x\n",
 776                            I915_READ(VLV_IMR));
 777                 for_each_pipe(dev_priv, pipe) {
 778                         enum intel_display_power_domain power_domain;
 779
 780                         power_domain = POWER_DOMAIN_PIPE(pipe);
 781                         if (!intel_display_power_get_if_enabled(dev_priv,
 782                                                                 power_domain)) {
 783                                 seq_printf(m, "Pipe %c power disabled\n",
 784                                            pipe_name(pipe));
 785                                 continue;
 786                         }
 787
 788                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 789                                    pipe_name(pipe),
 790                                    I915_READ(PIPESTAT(pipe)));
 791                         intel_display_power_put(dev_priv, power_domain);
 792                 }
 793
 794                 seq_printf(m, "Master IER:\t%08x\n",
 795                            I915_READ(VLV_MASTER_IER));
 796
 797                 seq_printf(m, "Render IER:\t%08x\n",
 798                            I915_READ(GTIER));
 799                 seq_printf(m, "Render IIR:\t%08x\n",
 800                            I915_READ(GTIIR));
 801                 seq_printf(m, "Render IMR:\t%08x\n",
 802                            I915_READ(GTIMR));
 803
 804                 seq_printf(m, "PM IER:\t\t%08x\n",
 805                            I915_READ(GEN6_PMIER));
 806                 seq_printf(m, "PM IIR:\t\t%08x\n",
 807                            I915_READ(GEN6_PMIIR));
 808                 seq_printf(m, "PM IMR:\t\t%08x\n",
 809                            I915_READ(GEN6_PMIMR));
 810
 811                 seq_printf(m, "Port hotplug:\t%08x\n",
 812                            I915_READ(PORT_HOTPLUG_EN));
 813                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 814                            I915_READ(VLV_DPFLIPSTAT));
 815                 seq_printf(m, "DPINVGTT:\t%08x\n",
 816                            I915_READ(DPINVGTT));
 817
 818         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 819                 seq_printf(m, "Interrupt enable:    %08x\n",
 820                            I915_READ(IER));
 821                 seq_printf(m, "Interrupt identity:  %08x\n",
 822                            I915_READ(IIR));
 823                 seq_printf(m, "Interrupt mask:      %08x\n",
 824                            I915_READ(IMR));
 825                 for_each_pipe(dev_priv, pipe)
 826                         seq_printf(m, "Pipe %c stat:         %08x\n",
 827                                    pipe_name(pipe),
 828                                    I915_READ(PIPESTAT(pipe)));
 829         } else {
 830                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 831                            I915_READ(DEIER));
 832                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 833                            I915_READ(DEIIR));
 834                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 835                            I915_READ(DEIMR));
 836                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 837                            I915_READ(SDEIER));
 838                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 839                            I915_READ(SDEIIR));
 840                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 841                            I915_READ(SDEIMR));
 842                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 843                            I915_READ(GTIER));
 844                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 845                            I915_READ(GTIIR));
 846                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 847                            I915_READ(GTIMR));
 848         }
 849         if (INTEL_GEN(dev_priv) >= 6) {
 850                 for_each_engine(engine, dev_priv, id) {
 851                         seq_printf(m,
 852                                    "Graphics Interrupt mask (%s):       %08x\n",
 853                                    engine->name, I915_READ_IMR(engine));
 854                 }
 855         }
 856         intel_runtime_pm_put(dev_priv);
 857
 858         return 0;
 859 }
 860
 861 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 862 {
 863         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 864         struct drm_device *dev = &dev_priv->drm;
 865         int i, ret;
 866
 867         ret = mutex_lock_interruptible(&dev->struct_mutex);
 868         if (ret)
 869                 return ret;
 870
 871         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 872         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 873                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 874
 875                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 876                            i, dev_priv->fence_regs[i].pin_count);
 877                 if (!vma)
 878                         seq_puts(m, "unused");
 879                 else
 880                         describe_obj(m, vma->obj);
 881                 seq_putc(m, '\n');
 882         }
 883
 884         mutex_unlock(&dev->struct_mutex);
 885         return 0;
 886 }
 887
 888 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 889 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 890                               size_t count, loff_t *pos)
 891 {
 892         struct i915_gpu_state *error = file->private_data;
 893         struct drm_i915_error_state_buf str;
 894         ssize_t ret;
 895         loff_t tmp;
 896
 897         if (!error)
 898                 return 0;
 899
 900         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 901         if (ret)
 902                 return ret;
 903
 904         ret = i915_error_state_to_str(&str, error);
 905         if (ret)
 906                 goto out;
 907
 908         tmp = 0;
 909         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 910         if (ret < 0)
 911                 goto out;
 912
 913         *pos = str.start + ret;
 914 out:
 915         i915_error_state_buf_release(&str);
 916         return ret;
 917 }
 918
 919 static int gpu_state_release(struct inode *inode, struct file *file)
 920 {
 921         i915_gpu_state_put(file->private_data);
 922         return 0;
 923 }
 924
 925 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 926 {
 927         struct drm_i915_private *i915 = inode->i_private;
 928         struct i915_gpu_state *gpu;
 929
 930         intel_runtime_pm_get(i915);
 931         gpu = i915_capture_gpu_state(i915);
 932         intel_runtime_pm_put(i915);
 933         if (!gpu)
 934                 return -ENOMEM;
 935
 936         file->private_data = gpu;
 937         return 0;
 938 }
 939
 940 static const struct file_operations i915_gpu_info_fops = {
 941         .owner = THIS_MODULE,
 942         .open = i915_gpu_info_open,
 943         .read = gpu_state_read,
 944         .llseek = default_llseek,
 945         .release = gpu_state_release,
 946 };
 947
 948 static ssize_t
 949 i915_error_state_write(struct file *filp,
 950                        const char __user *ubuf,
 951                        size_t cnt,
 952                        loff_t *ppos)
 953 {
 954         struct i915_gpu_state *error = filp->private_data;
 955
 956         if (!error)
 957                 return 0;
 958
 959         DRM_DEBUG_DRIVER("Resetting error state\n");
 960         i915_reset_error_state(error->i915);
 961
 962         return cnt;
 963 }
 964
 965 static int i915_error_state_open(struct inode *inode, struct file *file)
 966 {
 967         file->private_data = i915_first_error_state(inode->i_private);
 968         return 0;
 969 }
 970
 971 static const struct file_operations i915_error_state_fops = {
 972         .owner = THIS_MODULE,
 973         .open = i915_error_state_open,
 974         .read = gpu_state_read,
 975         .write = i915_error_state_write,
 976         .llseek = default_llseek,
 977         .release = gpu_state_release,
 978 };
 979 #endif
 980
 981 static int
 982 i915_next_seqno_set(void *data, u64 val)
 983 {
 984         struct drm_i915_private *dev_priv = data;
 985         struct drm_device *dev = &dev_priv->drm;
 986         int ret;
 987
 988         ret = mutex_lock_interruptible(&dev->struct_mutex);
 989         if (ret)
 990                 return ret;
 991
 992         intel_runtime_pm_get(dev_priv);
 993         ret = i915_gem_set_global_seqno(dev, val);
 994         intel_runtime_pm_put(dev_priv);
 995
 996         mutex_unlock(&dev->struct_mutex);
 997
 998         return ret;
 999 }
1000
1001 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1002                         NULL, i915_next_seqno_set,
1003                         "0x%llx\n");
1004
1005 static int i915_frequency_info(struct seq_file *m, void *unused)
1006 {
1007         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1008         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1009         int ret = 0;
1010
1011         intel_runtime_pm_get(dev_priv);
1012
1013         if (IS_GEN5(dev_priv)) {
1014                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1015                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1016
1017                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1018                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1019                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1020                            MEMSTAT_VID_SHIFT);
1021                 seq_printf(m, "Current P-state: %d\n",
1022                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1023         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1024                 u32 rpmodectl, freq_sts;
1025
1026                 mutex_lock(&dev_priv->pcu_lock);
1027
1028                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1029                 seq_printf(m, "Video Turbo Mode: %s\n",
1030                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1031                 seq_printf(m, "HW control enabled: %s\n",
1032                            yesno(rpmodectl & GEN6_RP_ENABLE));
1033                 seq_printf(m, "SW control enabled: %s\n",
1034                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1035                                   GEN6_RP_MEDIA_SW_MODE));
1036
1037                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1038                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1039                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1040
1041                 seq_printf(m, "actual GPU freq: %d MHz\n",
1042                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1043
1044                 seq_printf(m, "current GPU freq: %d MHz\n",
1045                            intel_gpu_freq(dev_priv, rps->cur_freq));
1046
1047                 seq_printf(m, "max GPU freq: %d MHz\n",
1048                            intel_gpu_freq(dev_priv, rps->max_freq));
1049
1050                 seq_printf(m, "min GPU freq: %d MHz\n",
1051                            intel_gpu_freq(dev_priv, rps->min_freq));
1052
1053                 seq_printf(m, "idle GPU freq: %d MHz\n",
1054                            intel_gpu_freq(dev_priv, rps->idle_freq));
1055
1056                 seq_printf(m,
1057                            "efficient (RPe) frequency: %d MHz\n",
1058                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1059                 mutex_unlock(&dev_priv->pcu_lock);
1060         } else if (INTEL_GEN(dev_priv) >= 6) {
1061                 u32 rp_state_limits;
1062                 u32 gt_perf_status;
1063                 u32 rp_state_cap;
1064                 u32 rpmodectl, rpinclimit, rpdeclimit;
1065                 u32 rpstat, cagf, reqf;
1066                 u32 rpupei, rpcurup, rpprevup;
1067                 u32 rpdownei, rpcurdown, rpprevdown;
1068                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1069                 int max_freq;
1070
1071                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1072                 if (IS_GEN9_LP(dev_priv)) {
1073                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1074                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1075                 } else {
1076                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1077                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1078                 }
1079
1080                 /* RPSTAT1 is in the GT power well */
1081                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1082
1083                 reqf = I915_READ(GEN6_RPNSWREQ);
1084                 if (INTEL_GEN(dev_priv) >= 9)
1085                         reqf >>= 23;
1086                 else {
1087                         reqf &= ~GEN6_TURBO_DISABLE;
1088                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1089                                 reqf >>= 24;
1090                         else
1091                                 reqf >>= 25;
1092                 }
1093                 reqf = intel_gpu_freq(dev_priv, reqf);
1094
1095                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1096                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1097                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1098
1099                 rpstat = I915_READ(GEN6_RPSTAT1);
1100                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1101                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1102                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1103                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1104                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1105                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1106                 cagf = intel_gpu_freq(dev_priv,
1107                                       intel_get_cagf(dev_priv, rpstat));
1108
1109                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1110
1111                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1112                         pm_ier = I915_READ(GEN6_PMIER);
1113                         pm_imr = I915_READ(GEN6_PMIMR);
1114                         pm_isr = I915_READ(GEN6_PMISR);
1115                         pm_iir = I915_READ(GEN6_PMIIR);
1116                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1117                 } else {
1118                         pm_ier = I915_READ(GEN8_GT_IER(2));
1119                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1120                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1121                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1122                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1123                 }
1124                 seq_printf(m, "Video Turbo Mode: %s\n",
1125                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1126                 seq_printf(m, "HW control enabled: %s\n",
1127                            yesno(rpmodectl & GEN6_RP_ENABLE));
1128                 seq_printf(m, "SW control enabled: %s\n",
1129                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1130                                   GEN6_RP_MEDIA_SW_MODE));
1131                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1132                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1133                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1134                            rps->pm_intrmsk_mbz);
1135                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1136                 seq_printf(m, "Render p-state ratio: %d\n",
1137                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1138                 seq_printf(m, "Render p-state VID: %d\n",
1139                            gt_perf_status & 0xff);
1140                 seq_printf(m, "Render p-state limit: %d\n",
1141                            rp_state_limits & 0xff);
1142                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1143                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1144                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1145                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1146                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1147                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1148                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1149                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1150                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1151                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1152                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1153                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1154                 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1155
1156                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1157                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1158                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1159                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1160                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1161                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1162                 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1163
1164                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1165                             rp_state_cap >> 16) & 0xff;
1166                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1167                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1168                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1169                            intel_gpu_freq(dev_priv, max_freq));
1170
1171                 max_freq = (rp_state_cap & 0xff00) >> 8;
1172                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1173                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1174                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1175                            intel_gpu_freq(dev_priv, max_freq));
1176
1177                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1178                             rp_state_cap >> 0) & 0xff;
1179                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1180                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1181                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1182                            intel_gpu_freq(dev_priv, max_freq));
1183                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1184                            intel_gpu_freq(dev_priv, rps->max_freq));
1185
1186                 seq_printf(m, "Current freq: %d MHz\n",
1187                            intel_gpu_freq(dev_priv, rps->cur_freq));
1188                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1189                 seq_printf(m, "Idle freq: %d MHz\n",
1190                            intel_gpu_freq(dev_priv, rps->idle_freq));
1191                 seq_printf(m, "Min freq: %d MHz\n",
1192                            intel_gpu_freq(dev_priv, rps->min_freq));
1193                 seq_printf(m, "Boost freq: %d MHz\n",
1194                            intel_gpu_freq(dev_priv, rps->boost_freq));
1195                 seq_printf(m, "Max freq: %d MHz\n",
1196                            intel_gpu_freq(dev_priv, rps->max_freq));
1197                 seq_printf(m,
1198                            "efficient (RPe) frequency: %d MHz\n",
1199                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1200         } else {
1201                 seq_puts(m, "no P-state info available\n");
1202         }
1203
1204         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1205         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1206         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1207
1208         intel_runtime_pm_put(dev_priv);
1209         return ret;
1210 }
1211
1212 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1213                                struct seq_file *m,
1214                                struct intel_instdone *instdone)
1215 {
1216         int slice;
1217         int subslice;
1218
1219         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1220                    instdone->instdone);
1221
1222         if (INTEL_GEN(dev_priv) <= 3)
1223                 return;
1224
1225         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1226                    instdone->slice_common);
1227
1228         if (INTEL_GEN(dev_priv) <= 6)
1229                 return;
1230
1231         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1232                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1233                            slice, subslice, instdone->sampler[slice][subslice]);
1234
1235         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1236                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1237                            slice, subslice, instdone->row[slice][subslice]);
1238 }
1239
1240 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1241 {
1242         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1243         struct intel_engine_cs *engine;
1244         u64 acthd[I915_NUM_ENGINES];
1245         u32 seqno[I915_NUM_ENGINES];
1246         struct intel_instdone instdone;
1247         enum intel_engine_id id;
1248
1249         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1250                 seq_puts(m, "Wedged\n");
1251         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1252                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1253         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1254                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1255         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1256                 seq_puts(m, "Waiter holding struct mutex\n");
1257         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1258                 seq_puts(m, "struct_mutex blocked for reset\n");
1259
1260         if (!i915_modparams.enable_hangcheck) {
1261                 seq_puts(m, "Hangcheck disabled\n");
1262                 return 0;
1263         }
1264
1265         intel_runtime_pm_get(dev_priv);
1266
1267         for_each_engine(engine, dev_priv, id) {
1268                 acthd[id] = intel_engine_get_active_head(engine);
1269                 seqno[id] = intel_engine_get_seqno(engine);
1270         }
1271
1272         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1273
1274         intel_runtime_pm_put(dev_priv);
1275
1276         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1277                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1278                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1279                                             jiffies));
1280         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1281                 seq_puts(m, "Hangcheck active, work pending\n");
1282         else
1283                 seq_puts(m, "Hangcheck inactive\n");
1284
1285         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1286
1287         for_each_engine(engine, dev_priv, id) {
1288                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1289                 struct rb_node *rb;
1290
1291                 seq_printf(m, "%s:\n", engine->name);
1292                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1293                            engine->hangcheck.seqno, seqno[id],
1294                            intel_engine_last_submit(engine),
1295                            engine->timeline->inflight_seqnos);
1296                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1297                            yesno(intel_engine_has_waiter(engine)),
1298                            yesno(test_bit(engine->id,
1299                                           &dev_priv->gpu_error.missed_irq_rings)),
1300                            yesno(engine->hangcheck.stalled));
1301
1302                 spin_lock_irq(&b->rb_lock);
1303                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1304                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1305
1306                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1307                                    w->tsk->comm, w->tsk->pid, w->seqno);
1308                 }
1309                 spin_unlock_irq(&b->rb_lock);
1310
1311                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1312                            (long long)engine->hangcheck.acthd,
1313                            (long long)acthd[id]);
1314                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1315                            hangcheck_action_to_str(engine->hangcheck.action),
1316                            engine->hangcheck.action,
1317                            jiffies_to_msecs(jiffies -
1318                                             engine->hangcheck.action_timestamp));
1319
1320                 if (engine->id == RCS) {
1321                         seq_puts(m, "\tinstdone read =\n");
1322
1323                         i915_instdone_info(dev_priv, m, &instdone);
1324
1325                         seq_puts(m, "\tinstdone accu =\n");
1326
1327                         i915_instdone_info(dev_priv, m,
1328                                            &engine->hangcheck.instdone);
1329                 }
1330         }
1331
1332         return 0;
1333 }
1334
1335 static int i915_reset_info(struct seq_file *m, void *unused)
1336 {
1337         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1338         struct i915_gpu_error *error = &dev_priv->gpu_error;
1339         struct intel_engine_cs *engine;
1340         enum intel_engine_id id;
1341
1342         seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1343
1344         for_each_engine(engine, dev_priv, id) {
1345                 seq_printf(m, "%s = %u\n", engine->name,
1346                            i915_reset_engine_count(error, engine));
1347         }
1348
1349         return 0;
1350 }
1351
1352 static int ironlake_drpc_info(struct seq_file *m)
1353 {
1354         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1355         u32 rgvmodectl, rstdbyctl;
1356         u16 crstandvid;
1357
1358         rgvmodectl = I915_READ(MEMMODECTL);
1359         rstdbyctl = I915_READ(RSTDBYCTL);
1360         crstandvid = I915_READ16(CRSTANDVID);
1361
1362         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1363         seq_printf(m, "Boost freq: %d\n",
1364                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1365                    MEMMODE_BOOST_FREQ_SHIFT);
1366         seq_printf(m, "HW control enabled: %s\n",
1367                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1368         seq_printf(m, "SW control enabled: %s\n",
1369                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1370         seq_printf(m, "Gated voltage change: %s\n",
1371                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1372         seq_printf(m, "Starting frequency: P%d\n",
1373                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1374         seq_printf(m, "Max P-state: P%d\n",
1375                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1376         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1377         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1378         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1379         seq_printf(m, "Render standby enabled: %s\n",
1380                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1381         seq_puts(m, "Current RS state: ");
1382         switch (rstdbyctl & RSX_STATUS_MASK) {
1383         case RSX_STATUS_ON:
1384                 seq_puts(m, "on\n");
1385                 break;
1386         case RSX_STATUS_RC1:
1387                 seq_puts(m, "RC1\n");
1388                 break;
1389         case RSX_STATUS_RC1E:
1390                 seq_puts(m, "RC1E\n");
1391                 break;
1392         case RSX_STATUS_RS1:
1393                 seq_puts(m, "RS1\n");
1394                 break;
1395         case RSX_STATUS_RS2:
1396                 seq_puts(m, "RS2 (RC6)\n");
1397                 break;
1398         case RSX_STATUS_RS3:
1399                 seq_puts(m, "RC3 (RC6+)\n");
1400                 break;
1401         default:
1402                 seq_puts(m, "unknown\n");
1403                 break;
1404         }
1405
1406         return 0;
1407 }
1408
1409 static int i915_forcewake_domains(struct seq_file *m, void *data)
1410 {
1411         struct drm_i915_private *i915 = node_to_i915(m->private);
1412         struct intel_uncore_forcewake_domain *fw_domain;
1413         unsigned int tmp;
1414
1415         seq_printf(m, "user.bypass_count = %u\n",
1416                    i915->uncore.user_forcewake.count);
1417
1418         for_each_fw_domain(fw_domain, i915, tmp)
1419                 seq_printf(m, "%s.wake_count = %u\n",
1420                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1421                            READ_ONCE(fw_domain->wake_count));
1422
1423         return 0;
1424 }
1425
1426 static void print_rc6_res(struct seq_file *m,
1427                           const char *title,
1428                           const i915_reg_t reg)
1429 {
1430         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1431
1432         seq_printf(m, "%s %u (%llu us)\n",
1433                    title, I915_READ(reg),
1434                    intel_rc6_residency_us(dev_priv, reg));
1435 }
1436
1437 static int vlv_drpc_info(struct seq_file *m)
1438 {
1439         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1440         u32 rcctl1, pw_status;
1441
1442         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1443         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1444
1445         seq_printf(m, "RC6 Enabled: %s\n",
1446                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1447                                         GEN6_RC_CTL_EI_MODE(1))));
1448         seq_printf(m, "Render Power Well: %s\n",
1449                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1450         seq_printf(m, "Media Power Well: %s\n",
1451                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1452
1453         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1454         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1455
1456         return i915_forcewake_domains(m, NULL);
1457 }
1458
1459 static int gen6_drpc_info(struct seq_file *m)
1460 {
1461         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1462         u32 gt_core_status, rcctl1, rc6vids = 0;
1463         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1464
1465         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1466         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1467
1468         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469         if (INTEL_GEN(dev_priv) >= 9) {
1470                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1471                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1472         }
1473
1474         mutex_lock(&dev_priv->pcu_lock);
1475         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1476         mutex_unlock(&dev_priv->pcu_lock);
1477
1478         seq_printf(m, "RC1e Enabled: %s\n",
1479                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1480         seq_printf(m, "RC6 Enabled: %s\n",
1481                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1482         if (INTEL_GEN(dev_priv) >= 9) {
1483                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1484                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1485                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1486                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1487         }
1488         seq_printf(m, "Deep RC6 Enabled: %s\n",
1489                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1490         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1491                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1492         seq_puts(m, "Current RC state: ");
1493         switch (gt_core_status & GEN6_RCn_MASK) {
1494         case GEN6_RC0:
1495                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1496                         seq_puts(m, "Core Power Down\n");
1497                 else
1498                         seq_puts(m, "on\n");
1499                 break;
1500         case GEN6_RC3:
1501                 seq_puts(m, "RC3\n");
1502                 break;
1503         case GEN6_RC6:
1504                 seq_puts(m, "RC6\n");
1505                 break;
1506         case GEN6_RC7:
1507                 seq_puts(m, "RC7\n");
1508                 break;
1509         default:
1510                 seq_puts(m, "Unknown\n");
1511                 break;
1512         }
1513
1514         seq_printf(m, "Core Power Down: %s\n",
1515                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1516         if (INTEL_GEN(dev_priv) >= 9) {
1517                 seq_printf(m, "Render Power Well: %s\n",
1518                         (gen9_powergate_status &
1519                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1520                 seq_printf(m, "Media Power Well: %s\n",
1521                         (gen9_powergate_status &
1522                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1523         }
1524
1525         /* Not exactly sure what this is */
1526         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1527                       GEN6_GT_GFX_RC6_LOCKED);
1528         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1529         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1530         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1531
1532         seq_printf(m, "RC6   voltage: %dmV\n",
1533                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1534         seq_printf(m, "RC6+  voltage: %dmV\n",
1535                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1536         seq_printf(m, "RC6++ voltage: %dmV\n",
1537                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1538         return i915_forcewake_domains(m, NULL);
1539 }
1540
1541 static int i915_drpc_info(struct seq_file *m, void *unused)
1542 {
1543         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1544         int err;
1545
1546         intel_runtime_pm_get(dev_priv);
1547
1548         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1549                 err = vlv_drpc_info(m);
1550         else if (INTEL_GEN(dev_priv) >= 6)
1551                 err = gen6_drpc_info(m);
1552         else
1553                 err = ironlake_drpc_info(m);
1554
1555         intel_runtime_pm_put(dev_priv);
1556
1557         return err;
1558 }
1559
1560 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1561 {
1562         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1563
1564         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1565                    dev_priv->fb_tracking.busy_bits);
1566
1567         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1568                    dev_priv->fb_tracking.flip_bits);
1569
1570         return 0;
1571 }
1572
1573 static int i915_fbc_status(struct seq_file *m, void *unused)
1574 {
1575         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1576         struct intel_fbc *fbc = &dev_priv->fbc;
1577
1578         if (!HAS_FBC(dev_priv))
1579                 return -ENODEV;
1580
1581         intel_runtime_pm_get(dev_priv);
1582         mutex_lock(&fbc->lock);
1583
1584         if (intel_fbc_is_active(dev_priv))
1585                 seq_puts(m, "FBC enabled\n");
1586         else
1587                 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1588
1589         if (fbc->work.scheduled)
1590                 seq_printf(m, "FBC worker scheduled on vblank %u, now %llu\n",
1591                            fbc->work.scheduled_vblank,
1592                            drm_crtc_vblank_count(&fbc->crtc->base));
1593
1594         if (intel_fbc_is_active(dev_priv)) {
1595                 u32 mask;
1596
1597                 if (INTEL_GEN(dev_priv) >= 8)
1598                         mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1599                 else if (INTEL_GEN(dev_priv) >= 7)
1600                         mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1601                 else if (INTEL_GEN(dev_priv) >= 5)
1602                         mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1603                 else if (IS_G4X(dev_priv))
1604                         mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1605                 else
1606                         mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1607                                                         FBC_STAT_COMPRESSED);
1608
1609                 seq_printf(m, "Compressing: %s\n", yesno(mask));
1610         }
1611
1612         mutex_unlock(&fbc->lock);
1613         intel_runtime_pm_put(dev_priv);
1614
1615         return 0;
1616 }
1617
1618 static int i915_fbc_false_color_get(void *data, u64 *val)
1619 {
1620         struct drm_i915_private *dev_priv = data;
1621
1622         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1623                 return -ENODEV;
1624
1625         *val = dev_priv->fbc.false_color;
1626
1627         return 0;
1628 }
1629
1630 static int i915_fbc_false_color_set(void *data, u64 val)
1631 {
1632         struct drm_i915_private *dev_priv = data;
1633         u32 reg;
1634
1635         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1636                 return -ENODEV;
1637
1638         mutex_lock(&dev_priv->fbc.lock);
1639
1640         reg = I915_READ(ILK_DPFC_CONTROL);
1641         dev_priv->fbc.false_color = val;
1642
1643         I915_WRITE(ILK_DPFC_CONTROL, val ?
1644                    (reg | FBC_CTL_FALSE_COLOR) :
1645                    (reg & ~FBC_CTL_FALSE_COLOR));
1646
1647         mutex_unlock(&dev_priv->fbc.lock);
1648         return 0;
1649 }
1650
1651 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1652                         i915_fbc_false_color_get, i915_fbc_false_color_set,
1653                         "%llu\n");
1654
1655 static int i915_ips_status(struct seq_file *m, void *unused)
1656 {
1657         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1658
1659         if (!HAS_IPS(dev_priv))
1660                 return -ENODEV;
1661
1662         intel_runtime_pm_get(dev_priv);
1663
1664         seq_printf(m, "Enabled by kernel parameter: %s\n",
1665                    yesno(i915_modparams.enable_ips));
1666
1667         if (INTEL_GEN(dev_priv) >= 8) {
1668                 seq_puts(m, "Currently: unknown\n");
1669         } else {
1670                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1671                         seq_puts(m, "Currently: enabled\n");
1672                 else
1673                         seq_puts(m, "Currently: disabled\n");
1674         }
1675
1676         intel_runtime_pm_put(dev_priv);
1677
1678         return 0;
1679 }
1680
1681 static int i915_sr_status(struct seq_file *m, void *unused)
1682 {
1683         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1684         bool sr_enabled = false;
1685
1686         intel_runtime_pm_get(dev_priv);
1687         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1688
1689         if (INTEL_GEN(dev_priv) >= 9)
1690                 /* no global SR status; inspect per-plane WM */;
1691         else if (HAS_PCH_SPLIT(dev_priv))
1692                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1693         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1694                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1695                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1696         else if (IS_I915GM(dev_priv))
1697                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1698         else if (IS_PINEVIEW(dev_priv))
1699                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1700         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1701                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1702
1703         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1704         intel_runtime_pm_put(dev_priv);
1705
1706         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1707
1708         return 0;
1709 }
1710
1711 static int i915_emon_status(struct seq_file *m, void *unused)
1712 {
1713         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1714         struct drm_device *dev = &dev_priv->drm;
1715         unsigned long temp, chipset, gfx;
1716         int ret;
1717
1718         if (!IS_GEN5(dev_priv))
1719                 return -ENODEV;
1720
1721         ret = mutex_lock_interruptible(&dev->struct_mutex);
1722         if (ret)
1723                 return ret;
1724
1725         temp = i915_mch_val(dev_priv);
1726         chipset = i915_chipset_val(dev_priv);
1727         gfx = i915_gfx_val(dev_priv);
1728         mutex_unlock(&dev->struct_mutex);
1729
1730         seq_printf(m, "GMCH temp: %ld\n", temp);
1731         seq_printf(m, "Chipset power: %ld\n", chipset);
1732         seq_printf(m, "GFX power: %ld\n", gfx);
1733         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1734
1735         return 0;
1736 }
1737
1738 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1739 {
1740         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1741         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1742         int ret = 0;
1743         int gpu_freq, ia_freq;
1744         unsigned int max_gpu_freq, min_gpu_freq;
1745
1746         if (!HAS_LLC(dev_priv))
1747                 return -ENODEV;
1748
1749         intel_runtime_pm_get(dev_priv);
1750
1751         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1752         if (ret)
1753                 goto out;
1754
1755         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1756                 /* Convert GT frequency to 50 HZ units */
1757                 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1758                 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1759         } else {
1760                 min_gpu_freq = rps->min_freq_softlimit;
1761                 max_gpu_freq = rps->max_freq_softlimit;
1762         }
1763
1764         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1765
1766         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1767                 ia_freq = gpu_freq;
1768                 sandybridge_pcode_read(dev_priv,
1769                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1770                                        &ia_freq);
1771                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1772                            intel_gpu_freq(dev_priv, (gpu_freq *
1773                                                      (IS_GEN9_BC(dev_priv) ||
1774                                                       IS_CANNONLAKE(dev_priv) ?
1775                                                       GEN9_FREQ_SCALER : 1))),
1776                            ((ia_freq >> 0) & 0xff) * 100,
1777                            ((ia_freq >> 8) & 0xff) * 100);
1778         }
1779
1780         mutex_unlock(&dev_priv->pcu_lock);
1781
1782 out:
1783         intel_runtime_pm_put(dev_priv);
1784         return ret;
1785 }
1786
1787 static int i915_opregion(struct seq_file *m, void *unused)
1788 {
1789         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1790         struct drm_device *dev = &dev_priv->drm;
1791         struct intel_opregion *opregion = &dev_priv->opregion;
1792         int ret;
1793
1794         ret = mutex_lock_interruptible(&dev->struct_mutex);
1795         if (ret)
1796                 goto out;
1797
1798         if (opregion->header)
1799                 seq_write(m, opregion->header, OPREGION_SIZE);
1800
1801         mutex_unlock(&dev->struct_mutex);
1802
1803 out:
1804         return 0;
1805 }
1806
1807 static int i915_vbt(struct seq_file *m, void *unused)
1808 {
1809         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1810
1811         if (opregion->vbt)
1812                 seq_write(m, opregion->vbt, opregion->vbt_size);
1813
1814         return 0;
1815 }
1816
1817 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1818 {
1819         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1820         struct drm_device *dev = &dev_priv->drm;
1821         struct intel_framebuffer *fbdev_fb = NULL;
1822         struct drm_framebuffer *drm_fb;
1823         int ret;
1824
1825         ret = mutex_lock_interruptible(&dev->struct_mutex);
1826         if (ret)
1827                 return ret;
1828
1829 #ifdef CONFIG_DRM_FBDEV_EMULATION
1830         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1831                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1832
1833                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1834                            fbdev_fb->base.width,
1835                            fbdev_fb->base.height,
1836                            fbdev_fb->base.format->depth,
1837                            fbdev_fb->base.format->cpp[0] * 8,
1838                            fbdev_fb->base.modifier,
1839                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1840                 describe_obj(m, fbdev_fb->obj);
1841                 seq_putc(m, '\n');
1842         }
1843 #endif
1844
1845         mutex_lock(&dev->mode_config.fb_lock);
1846         drm_for_each_fb(drm_fb, dev) {
1847                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1848                 if (fb == fbdev_fb)
1849                         continue;
1850
1851                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1852                            fb->base.width,
1853                            fb->base.height,
1854                            fb->base.format->depth,
1855                            fb->base.format->cpp[0] * 8,
1856                            fb->base.modifier,
1857                            drm_framebuffer_read_refcount(&fb->base));
1858                 describe_obj(m, fb->obj);
1859                 seq_putc(m, '\n');
1860         }
1861         mutex_unlock(&dev->mode_config.fb_lock);
1862         mutex_unlock(&dev->struct_mutex);
1863
1864         return 0;
1865 }
1866
1867 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1868 {
1869         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1870                    ring->space, ring->head, ring->tail);
1871 }
1872
1873 static int i915_context_status(struct seq_file *m, void *unused)
1874 {
1875         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1876         struct drm_device *dev = &dev_priv->drm;
1877         struct intel_engine_cs *engine;
1878         struct i915_gem_context *ctx;
1879         enum intel_engine_id id;
1880         int ret;
1881
1882         ret = mutex_lock_interruptible(&dev->struct_mutex);
1883         if (ret)
1884                 return ret;
1885
1886         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1887                 seq_printf(m, "HW context %u ", ctx->hw_id);
1888                 if (ctx->pid) {
1889                         struct task_struct *task;
1890
1891                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1892                         if (task) {
1893                                 seq_printf(m, "(%s [%d]) ",
1894                                            task->comm, task->pid);
1895                                 put_task_struct(task);
1896                         }
1897                 } else if (IS_ERR(ctx->file_priv)) {
1898                         seq_puts(m, "(deleted) ");
1899                 } else {
1900                         seq_puts(m, "(kernel) ");
1901                 }
1902
1903                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1904                 seq_putc(m, '\n');
1905
1906                 for_each_engine(engine, dev_priv, id) {
1907                         struct intel_context *ce = &ctx->engine[engine->id];
1908
1909                         seq_printf(m, "%s: ", engine->name);
1910                         if (ce->state)
1911                                 describe_obj(m, ce->state->obj);
1912                         if (ce->ring)
1913                                 describe_ctx_ring(m, ce->ring);
1914                         seq_putc(m, '\n');
1915                 }
1916
1917                 seq_putc(m, '\n');
1918         }
1919
1920         mutex_unlock(&dev->struct_mutex);
1921
1922         return 0;
1923 }
1924
1925 static const char *swizzle_string(unsigned swizzle)
1926 {
1927         switch (swizzle) {
1928         case I915_BIT_6_SWIZZLE_NONE:
1929                 return "none";
1930         case I915_BIT_6_SWIZZLE_9:
1931                 return "bit9";
1932         case I915_BIT_6_SWIZZLE_9_10:
1933                 return "bit9/bit10";
1934         case I915_BIT_6_SWIZZLE_9_11:
1935                 return "bit9/bit11";
1936         case I915_BIT_6_SWIZZLE_9_10_11:
1937                 return "bit9/bit10/bit11";
1938         case I915_BIT_6_SWIZZLE_9_17:
1939                 return "bit9/bit17";
1940         case I915_BIT_6_SWIZZLE_9_10_17:
1941                 return "bit9/bit10/bit17";
1942         case I915_BIT_6_SWIZZLE_UNKNOWN:
1943                 return "unknown";
1944         }
1945
1946         return "bug";
1947 }
1948
1949 static int i915_swizzle_info(struct seq_file *m, void *data)
1950 {
1951         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1952
1953         intel_runtime_pm_get(dev_priv);
1954
1955         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1956                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1957         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1958                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1959
1960         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
1961                 seq_printf(m, "DDC = 0x%08x\n",
1962                            I915_READ(DCC));
1963                 seq_printf(m, "DDC2 = 0x%08x\n",
1964                            I915_READ(DCC2));
1965                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1966                            I915_READ16(C0DRB3));
1967                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1968                            I915_READ16(C1DRB3));
1969         } else if (INTEL_GEN(dev_priv) >= 6) {
1970                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1971                            I915_READ(MAD_DIMM_C0));
1972                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1973                            I915_READ(MAD_DIMM_C1));
1974                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1975                            I915_READ(MAD_DIMM_C2));
1976                 seq_printf(m, "TILECTL = 0x%08x\n",
1977                            I915_READ(TILECTL));
1978                 if (INTEL_GEN(dev_priv) >= 8)
1979                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1980                                    I915_READ(GAMTARBMODE));
1981                 else
1982                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1983                                    I915_READ(ARB_MODE));
1984                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1985                            I915_READ(DISP_ARB_CTL));
1986         }
1987
1988         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
1989                 seq_puts(m, "L-shaped memory detected\n");
1990
1991         intel_runtime_pm_put(dev_priv);
1992
1993         return 0;
1994 }
1995
1996 static int per_file_ctx(int id, void *ptr, void *data)
1997 {
1998         struct i915_gem_context *ctx = ptr;
1999         struct seq_file *m = data;
2000         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2001
2002         if (!ppgtt) {
2003                 seq_printf(m, "  no ppgtt for context %d\n",
2004                            ctx->user_handle);
2005                 return 0;
2006         }
2007
2008         if (i915_gem_context_is_default(ctx))
2009                 seq_puts(m, "  default context:\n");
2010         else
2011                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2012         ppgtt->debug_dump(ppgtt, m);
2013
2014         return 0;
2015 }
2016
2017 static void gen8_ppgtt_info(struct seq_file *m,
2018                             struct drm_i915_private *dev_priv)
2019 {
2020         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2021         struct intel_engine_cs *engine;
2022         enum intel_engine_id id;
2023         int i;
2024
2025         if (!ppgtt)
2026                 return;
2027
2028         for_each_engine(engine, dev_priv, id) {
2029                 seq_printf(m, "%s\n", engine->name);
2030                 for (i = 0; i < 4; i++) {
2031                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2032                         pdp <<= 32;
2033                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2034                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2035                 }
2036         }
2037 }
2038
2039 static void gen6_ppgtt_info(struct seq_file *m,
2040                             struct drm_i915_private *dev_priv)
2041 {
2042         struct intel_engine_cs *engine;
2043         enum intel_engine_id id;
2044
2045         if (IS_GEN6(dev_priv))
2046                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2047
2048         for_each_engine(engine, dev_priv, id) {
2049                 seq_printf(m, "%s\n", engine->name);
2050                 if (IS_GEN7(dev_priv))
2051                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2052                                    I915_READ(RING_MODE_GEN7(engine)));
2053                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2054                            I915_READ(RING_PP_DIR_BASE(engine)));
2055                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2056                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2057                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2058                            I915_READ(RING_PP_DIR_DCLV(engine)));
2059         }
2060         if (dev_priv->mm.aliasing_ppgtt) {
2061                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2062
2063                 seq_puts(m, "aliasing PPGTT:\n");
2064                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2065
2066                 ppgtt->debug_dump(ppgtt, m);
2067         }
2068
2069         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2070 }
2071
2072 static int i915_ppgtt_info(struct seq_file *m, void *data)
2073 {
2074         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2075         struct drm_device *dev = &dev_priv->drm;
2076         struct drm_file *file;
2077         int ret;
2078
2079         mutex_lock(&dev->filelist_mutex);
2080         ret = mutex_lock_interruptible(&dev->struct_mutex);
2081         if (ret)
2082                 goto out_unlock;
2083
2084         intel_runtime_pm_get(dev_priv);
2085
2086         if (INTEL_GEN(dev_priv) >= 8)
2087                 gen8_ppgtt_info(m, dev_priv);
2088         else if (INTEL_GEN(dev_priv) >= 6)
2089                 gen6_ppgtt_info(m, dev_priv);
2090
2091         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2092                 struct drm_i915_file_private *file_priv = file->driver_priv;
2093                 struct task_struct *task;
2094
2095                 task = get_pid_task(file->pid, PIDTYPE_PID);
2096                 if (!task) {
2097                         ret = -ESRCH;
2098                         goto out_rpm;
2099                 }
2100                 seq_printf(m, "\nproc: %s\n", task->comm);
2101                 put_task_struct(task);
2102                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2103                              (void *)(unsigned long)m);
2104         }
2105
2106 out_rpm:
2107         intel_runtime_pm_put(dev_priv);
2108         mutex_unlock(&dev->struct_mutex);
2109 out_unlock:
2110         mutex_unlock(&dev->filelist_mutex);
2111         return ret;
2112 }
2113
2114 static int count_irq_waiters(struct drm_i915_private *i915)
2115 {
2116         struct intel_engine_cs *engine;
2117         enum intel_engine_id id;
2118         int count = 0;
2119
2120         for_each_engine(engine, i915, id)
2121                 count += intel_engine_has_waiter(engine);
2122
2123         return count;
2124 }
2125
2126 static const char *rps_power_to_str(unsigned int power)
2127 {
2128         static const char * const strings[] = {
2129                 [LOW_POWER] = "low power",
2130                 [BETWEEN] = "mixed",
2131                 [HIGH_POWER] = "high power",
2132         };
2133
2134         if (power >= ARRAY_SIZE(strings) || !strings[power])
2135                 return "unknown";
2136
2137         return strings[power];
2138 }
2139
2140 static int i915_rps_boost_info(struct seq_file *m, void *data)
2141 {
2142         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2143         struct drm_device *dev = &dev_priv->drm;
2144         struct intel_rps *rps = &dev_priv->gt_pm.rps;
2145         struct drm_file *file;
2146
2147         seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2148         seq_printf(m, "GPU busy? %s [%d requests]\n",
2149                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2150         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2151         seq_printf(m, "Boosts outstanding? %d\n",
2152                    atomic_read(&rps->num_waiters));
2153         seq_printf(m, "Frequency requested %d\n",
2154                    intel_gpu_freq(dev_priv, rps->cur_freq));
2155         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2156                    intel_gpu_freq(dev_priv, rps->min_freq),
2157                    intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2158                    intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2159                    intel_gpu_freq(dev_priv, rps->max_freq));
2160         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2161                    intel_gpu_freq(dev_priv, rps->idle_freq),
2162                    intel_gpu_freq(dev_priv, rps->efficient_freq),
2163                    intel_gpu_freq(dev_priv, rps->boost_freq));
2164
2165         mutex_lock(&dev->filelist_mutex);
2166         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2167                 struct drm_i915_file_private *file_priv = file->driver_priv;
2168                 struct task_struct *task;
2169
2170                 rcu_read_lock();
2171                 task = pid_task(file->pid, PIDTYPE_PID);
2172                 seq_printf(m, "%s [%d]: %d boosts\n",
2173                            task ? task->comm : "<unknown>",
2174                            task ? task->pid : -1,
2175                            atomic_read(&file_priv->rps_client.boosts));
2176                 rcu_read_unlock();
2177         }
2178         seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2179                    atomic_read(&rps->boosts));
2180         mutex_unlock(&dev->filelist_mutex);
2181
2182         if (INTEL_GEN(dev_priv) >= 6 &&
2183             rps->enabled &&
2184             dev_priv->gt.active_requests) {
2185                 u32 rpup, rpupei;
2186                 u32 rpdown, rpdownei;
2187
2188                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2189                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2190                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2191                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2192                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2193                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2194
2195                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2196                            rps_power_to_str(rps->power));
2197                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2198                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2199                            rps->up_threshold);
2200                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2201                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2202                            rps->down_threshold);
2203         } else {
2204                 seq_puts(m, "\nRPS Autotuning inactive\n");
2205         }
2206
2207         return 0;
2208 }
2209
2210 static int i915_llc(struct seq_file *m, void *data)
2211 {
2212         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2213         const bool edram = INTEL_GEN(dev_priv) > 8;
2214
2215         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2216         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2217                    intel_uncore_edram_size(dev_priv)/1024/1024);
2218
2219         return 0;
2220 }
2221
2222 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2223 {
2224         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2225         struct drm_printer p;
2226
2227         if (!HAS_HUC(dev_priv))
2228                 return -ENODEV;
2229
2230         p = drm_seq_file_printer(m);
2231         intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2232
2233         intel_runtime_pm_get(dev_priv);
2234         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2235         intel_runtime_pm_put(dev_priv);
2236
2237         return 0;
2238 }
2239
2240 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2241 {
2242         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2243         struct drm_printer p;
2244         u32 tmp, i;
2245
2246         if (!HAS_GUC(dev_priv))
2247                 return -ENODEV;
2248
2249         p = drm_seq_file_printer(m);
2250         intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2251
2252         intel_runtime_pm_get(dev_priv);
2253
2254         tmp = I915_READ(GUC_STATUS);
2255
2256         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2257         seq_printf(m, "\tBootrom status = 0x%x\n",
2258                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2259         seq_printf(m, "\tuKernel status = 0x%x\n",
2260                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2261         seq_printf(m, "\tMIA Core status = 0x%x\n",
2262                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2263         seq_puts(m, "\nScratch registers:\n");
2264         for (i = 0; i < 16; i++)
2265                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2266
2267         intel_runtime_pm_put(dev_priv);
2268
2269         return 0;
2270 }
2271
2272 static void i915_guc_log_info(struct seq_file *m,
2273                               struct drm_i915_private *dev_priv)
2274 {
2275         struct intel_guc *guc = &dev_priv->guc;
2276
2277         seq_puts(m, "\nGuC logging stats:\n");
2278
2279         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2280                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2281                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2282
2283         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2284                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2285                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2286
2287         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2288                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2289                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2290
2291         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2292                    guc->log.flush_interrupt_count);
2293
2294         seq_printf(m, "\tCapture miss count: %u\n",
2295                    guc->log.capture_miss_count);
2296 }
2297
2298 static void i915_guc_client_info(struct seq_file *m,
2299                                  struct drm_i915_private *dev_priv,
2300                                  struct intel_guc_client *client)
2301 {
2302         struct intel_engine_cs *engine;
2303         enum intel_engine_id id;
2304         uint64_t tot = 0;
2305
2306         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2307                 client->priority, client->stage_id, client->proc_desc_offset);
2308         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2309                 client->doorbell_id, client->doorbell_offset);
2310
2311         for_each_engine(engine, dev_priv, id) {
2312                 u64 submissions = client->submissions[id];
2313                 tot += submissions;
2314                 seq_printf(m, "\tSubmissions: %llu %s\n",
2315                                 submissions, engine->name);
2316         }
2317         seq_printf(m, "\tTotal: %llu\n", tot);
2318 }
2319
2320 static int i915_guc_info(struct seq_file *m, void *data)
2321 {
2322         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2323         const struct intel_guc *guc = &dev_priv->guc;
2324
2325         if (!USES_GUC_SUBMISSION(dev_priv))
2326                 return -ENODEV;
2327
2328         GEM_BUG_ON(!guc->execbuf_client);
2329
2330         seq_printf(m, "Doorbell map:\n");
2331         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2332         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2333
2334         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2335         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2336         if (guc->preempt_client) {
2337                 seq_printf(m, "\nGuC preempt client @ %p:\n",
2338                            guc->preempt_client);
2339                 i915_guc_client_info(m, dev_priv, guc->preempt_client);
2340         }
2341
2342         i915_guc_log_info(m, dev_priv);
2343
2344         /* Add more as required ... */
2345
2346         return 0;
2347 }
2348
2349 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2350 {
2351         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2352         const struct intel_guc *guc = &dev_priv->guc;
2353         struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2354         struct intel_guc_client *client = guc->execbuf_client;
2355         unsigned int tmp;
2356         int index;
2357
2358         if (!USES_GUC_SUBMISSION(dev_priv))
2359                 return -ENODEV;
2360
2361         for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2362                 struct intel_engine_cs *engine;
2363
2364                 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2365                         continue;
2366
2367                 seq_printf(m, "GuC stage descriptor %u:\n", index);
2368                 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2369                 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2370                 seq_printf(m, "\tPriority: %d\n", desc->priority);
2371                 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2372                 seq_printf(m, "\tEngines used: 0x%x\n",
2373                            desc->engines_used);
2374                 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2375                            desc->db_trigger_phy,
2376                            desc->db_trigger_cpu,
2377                            desc->db_trigger_uk);
2378                 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2379                            desc->process_desc);
2380                 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2381                            desc->wq_addr, desc->wq_size);
2382                 seq_putc(m, '\n');
2383
2384                 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2385                         u32 guc_engine_id = engine->guc_id;
2386                         struct guc_execlist_context *lrc =
2387                                                 &desc->lrc[guc_engine_id];
2388
2389                         seq_printf(m, "\t%s LRC:\n", engine->name);
2390                         seq_printf(m, "\t\tContext desc: 0x%x\n",
2391                                    lrc->context_desc);
2392                         seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2393                         seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2394                         seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2395                         seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2396                         seq_putc(m, '\n');
2397                 }
2398         }
2399
2400         return 0;
2401 }
2402
2403 static int i915_guc_log_dump(struct seq_file *m, void *data)
2404 {
2405         struct drm_info_node *node = m->private;
2406         struct drm_i915_private *dev_priv = node_to_i915(node);
2407         bool dump_load_err = !!node->info_ent->data;
2408         struct drm_i915_gem_object *obj = NULL;
2409         u32 *log;
2410         int i = 0;
2411
2412         if (!HAS_GUC(dev_priv))
2413                 return -ENODEV;
2414
2415         if (dump_load_err)
2416                 obj = dev_priv->guc.load_err_log;
2417         else if (dev_priv->guc.log.vma)
2418                 obj = dev_priv->guc.log.vma->obj;
2419
2420         if (!obj)
2421                 return 0;
2422
2423         log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2424         if (IS_ERR(log)) {
2425                 DRM_DEBUG("Failed to pin object\n");
2426                 seq_puts(m, "(log data unaccessible)\n");
2427                 return PTR_ERR(log);
2428         }
2429
2430         for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2431                 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2432                            *(log + i), *(log + i + 1),
2433                            *(log + i + 2), *(log + i + 3));
2434
2435         seq_putc(m, '\n');
2436
2437         i915_gem_object_unpin_map(obj);
2438
2439         return 0;
2440 }
2441
2442 static int i915_guc_log_control_get(void *data, u64 *val)
2443 {
2444         struct drm_i915_private *dev_priv = data;
2445
2446         if (!HAS_GUC(dev_priv))
2447                 return -ENODEV;
2448
2449         if (!dev_priv->guc.log.vma)
2450                 return -EINVAL;
2451
2452         *val = i915_modparams.guc_log_level;
2453
2454         return 0;
2455 }
2456
2457 static int i915_guc_log_control_set(void *data, u64 val)
2458 {
2459         struct drm_i915_private *dev_priv = data;
2460
2461         if (!HAS_GUC(dev_priv))
2462                 return -ENODEV;
2463
2464         return intel_guc_log_control(&dev_priv->guc, val);
2465 }
2466
2467 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2468                         i915_guc_log_control_get, i915_guc_log_control_set,
2469                         "%lld\n");
2470
2471 static const char *psr2_live_status(u32 val)
2472 {
2473         static const char * const live_status[] = {
2474                 "IDLE",
2475                 "CAPTURE",
2476                 "CAPTURE_FS",
2477                 "SLEEP",
2478                 "BUFON_FW",
2479                 "ML_UP",
2480                 "SU_STANDBY",
2481                 "FAST_SLEEP",
2482                 "DEEP_SLEEP",
2483                 "BUF_ON",
2484                 "TG_ON"
2485         };
2486
2487         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2488         if (val < ARRAY_SIZE(live_status))
2489                 return live_status[val];
2490
2491         return "unknown";
2492 }
2493
2494 static int i915_edp_psr_status(struct seq_file *m, void *data)
2495 {
2496         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2497         u32 psrperf = 0;
2498         u32 stat[3];
2499         enum pipe pipe;
2500         bool enabled = false;
2501         bool sink_support;
2502
2503         if (!HAS_PSR(dev_priv))
2504                 return -ENODEV;
2505
2506         sink_support = dev_priv->psr.sink_support;
2507         seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
2508         if (!sink_support)
2509                 return 0;
2510
2511         intel_runtime_pm_get(dev_priv);
2512
2513         mutex_lock(&dev_priv->psr.lock);
2514         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2515         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2516         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2517                    dev_priv->psr.busy_frontbuffer_bits);
2518         seq_printf(m, "Re-enable work scheduled: %s\n",
2519                    yesno(work_busy(&dev_priv->psr.work.work)));
2520
2521         if (HAS_DDI(dev_priv)) {
2522                 if (dev_priv->psr.psr2_support)
2523                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2524                 else
2525                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2526         } else {
2527                 for_each_pipe(dev_priv, pipe) {
2528                         enum transcoder cpu_transcoder =
2529                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2530                         enum intel_display_power_domain power_domain;
2531
2532                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2533                         if (!intel_display_power_get_if_enabled(dev_priv,
2534                                                                 power_domain))
2535                                 continue;
2536
2537                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2538                                 VLV_EDP_PSR_CURR_STATE_MASK;
2539                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2540                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2541                                 enabled = true;
2542
2543                         intel_display_power_put(dev_priv, power_domain);
2544                 }
2545         }
2546
2547         seq_printf(m, "Main link in standby mode: %s\n",
2548                    yesno(dev_priv->psr.link_standby));
2549
2550         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2551
2552         if (!HAS_DDI(dev_priv))
2553                 for_each_pipe(dev_priv, pipe) {
2554                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2555                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2556                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2557                 }
2558         seq_puts(m, "\n");
2559
2560         /*
2561          * VLV/CHV PSR has no kind of performance counter
2562          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2563          */
2564         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2565                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2566                         EDP_PSR_PERF_CNT_MASK;
2567
2568                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2569         }
2570         if (dev_priv->psr.psr2_support) {
2571                 u32 psr2 = I915_READ(EDP_PSR2_STATUS);
2572
2573                 seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
2574                            psr2, psr2_live_status(psr2));
2575         }
2576         mutex_unlock(&dev_priv->psr.lock);
2577
2578         intel_runtime_pm_put(dev_priv);
2579         return 0;
2580 }
2581
2582 static int i915_sink_crc(struct seq_file *m, void *data)
2583 {
2584         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2585         struct drm_device *dev = &dev_priv->drm;
2586         struct intel_connector *connector;
2587         struct drm_connector_list_iter conn_iter;
2588         struct intel_dp *intel_dp = NULL;
2589         struct drm_modeset_acquire_ctx ctx;
2590         int ret;
2591         u8 crc[6];
2592
2593         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2594
2595         drm_connector_list_iter_begin(dev, &conn_iter);
2596
2597         for_each_intel_connector_iter(connector, &conn_iter) {
2598                 struct drm_crtc *crtc;
2599                 struct drm_connector_state *state;
2600                 struct intel_crtc_state *crtc_state;
2601
2602                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2603                         continue;
2604
2605 retry:
2606                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2607                 if (ret)
2608                         goto err;
2609
2610                 state = connector->base.state;
2611                 if (!state->best_encoder)
2612                         continue;
2613
2614                 crtc = state->crtc;
2615                 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2616                 if (ret)
2617                         goto err;
2618
2619                 crtc_state = to_intel_crtc_state(crtc->state);
2620                 if (!crtc_state->base.active)
2621                         continue;
2622
2623                 /*
2624                  * We need to wait for all crtc updates to complete, to make
2625                  * sure any pending modesets and plane updates are completed.
2626                  */
2627                 if (crtc_state->base.commit) {
2628                         ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
2629
2630                         if (ret)
2631                                 goto err;
2632                 }
2633
2634                 intel_dp = enc_to_intel_dp(state->best_encoder);
2635
2636                 ret = intel_dp_sink_crc(intel_dp, crtc_state, crc);
2637                 if (ret)
2638                         goto err;
2639
2640                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2641                            crc[0], crc[1], crc[2],
2642                            crc[3], crc[4], crc[5]);
2643                 goto out;
2644
2645 err:
2646                 if (ret == -EDEADLK) {
2647                         ret = drm_modeset_backoff(&ctx);
2648                         if (!ret)
2649                                 goto retry;
2650                 }
2651                 goto out;
2652         }
2653         ret = -ENODEV;
2654 out:
2655         drm_connector_list_iter_end(&conn_iter);
2656         drm_modeset_drop_locks(&ctx);
2657         drm_modeset_acquire_fini(&ctx);
2658
2659         return ret;
2660 }
2661
2662 static int i915_energy_uJ(struct seq_file *m, void *data)
2663 {
2664         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2665         unsigned long long power;
2666         u32 units;
2667
2668         if (INTEL_GEN(dev_priv) < 6)
2669                 return -ENODEV;
2670
2671         intel_runtime_pm_get(dev_priv);
2672
2673         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2674                 intel_runtime_pm_put(dev_priv);
2675                 return -ENODEV;
2676         }
2677
2678         units = (power & 0x1f00) >> 8;
2679         power = I915_READ(MCH_SECP_NRG_STTS);
2680         power = (1000000 * power) >> units; /* convert to uJ */
2681
2682         intel_runtime_pm_put(dev_priv);
2683
2684         seq_printf(m, "%llu", power);
2685
2686         return 0;
2687 }
2688
2689 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2690 {
2691         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2692         struct pci_dev *pdev = dev_priv->drm.pdev;
2693
2694         if (!HAS_RUNTIME_PM(dev_priv))
2695                 seq_puts(m, "Runtime power management not supported\n");
2696
2697         seq_printf(m, "GPU idle: %s (epoch %u)\n",
2698                    yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
2699         seq_printf(m, "IRQs disabled: %s\n",
2700                    yesno(!intel_irqs_enabled(dev_priv)));
2701 #ifdef CONFIG_PM
2702         seq_printf(m, "Usage count: %d\n",
2703                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2704 #else
2705         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2706 #endif
2707         seq_printf(m, "PCI device power state: %s [%d]\n",
2708                    pci_power_name(pdev->current_state),
2709                    pdev->current_state);
2710
2711         return 0;
2712 }
2713
2714 static int i915_power_domain_info(struct seq_file *m, void *unused)
2715 {
2716         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2717         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2718         int i;
2719
2720         mutex_lock(&power_domains->lock);
2721
2722         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2723         for (i = 0; i < power_domains->power_well_count; i++) {
2724                 struct i915_power_well *power_well;
2725                 enum intel_display_power_domain power_domain;
2726
2727                 power_well = &power_domains->power_wells[i];
2728                 seq_printf(m, "%-25s %d\n", power_well->name,
2729                            power_well->count);
2730
2731                 for_each_power_domain(power_domain, power_well->domains)
2732                         seq_printf(m, "  %-23s %d\n",
2733                                  intel_display_power_domain_str(power_domain),
2734                                  power_domains->domain_use_count[power_domain]);
2735         }
2736
2737         mutex_unlock(&power_domains->lock);
2738
2739         return 0;
2740 }
2741
2742 static int i915_dmc_info(struct seq_file *m, void *unused)
2743 {
2744         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2745         struct intel_csr *csr;
2746
2747         if (!HAS_CSR(dev_priv))
2748                 return -ENODEV;
2749
2750         csr = &dev_priv->csr;
2751
2752         intel_runtime_pm_get(dev_priv);
2753
2754         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2755         seq_printf(m, "path: %s\n", csr->fw_path);
2756
2757         if (!csr->dmc_payload)
2758                 goto out;
2759
2760         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2761                    CSR_VERSION_MINOR(csr->version));
2762
2763         if (IS_KABYLAKE(dev_priv) ||
2764             (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2765                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2766                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2767                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2768                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2769         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2770                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2771                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2772         }
2773
2774 out:
2775         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2776         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2777         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2778
2779         intel_runtime_pm_put(dev_priv);
2780
2781         return 0;
2782 }
2783
2784 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2785                                  struct drm_display_mode *mode)
2786 {
2787         int i;
2788
2789         for (i = 0; i < tabs; i++)
2790                 seq_putc(m, '\t');
2791
2792         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2793                    mode->base.id, mode->name,
2794                    mode->vrefresh, mode->clock,
2795                    mode->hdisplay, mode->hsync_start,
2796                    mode->hsync_end, mode->htotal,
2797                    mode->vdisplay, mode->vsync_start,
2798                    mode->vsync_end, mode->vtotal,
2799                    mode->type, mode->flags);
2800 }
2801
2802 static void intel_encoder_info(struct seq_file *m,
2803                                struct intel_crtc *intel_crtc,
2804                                struct intel_encoder *intel_encoder)
2805 {
2806         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2807         struct drm_device *dev = &dev_priv->drm;
2808         struct drm_crtc *crtc = &intel_crtc->base;
2809         struct intel_connector *intel_connector;
2810         struct drm_encoder *encoder;
2811
2812         encoder = &intel_encoder->base;
2813         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2814                    encoder->base.id, encoder->name);
2815         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2816                 struct drm_connector *connector = &intel_connector->base;
2817                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2818                            connector->base.id,
2819                            connector->name,
2820                            drm_get_connector_status_name(connector->status));
2821                 if (connector->status == connector_status_connected) {
2822                         struct drm_display_mode *mode = &crtc->mode;
2823                         seq_printf(m, ", mode:\n");
2824                         intel_seq_print_mode(m, 2, mode);
2825                 } else {
2826                         seq_putc(m, '\n');
2827                 }
2828         }
2829 }
2830
2831 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2832 {
2833         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2834         struct drm_device *dev = &dev_priv->drm;
2835         struct drm_crtc *crtc = &intel_crtc->base;
2836         struct intel_encoder *intel_encoder;
2837         struct drm_plane_state *plane_state = crtc->primary->state;
2838         struct drm_framebuffer *fb = plane_state->fb;
2839
2840         if (fb)
2841                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2842                            fb->base.id, plane_state->src_x >> 16,
2843                            plane_state->src_y >> 16, fb->width, fb->height);
2844         else
2845                 seq_puts(m, "\tprimary plane disabled\n");
2846         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2847                 intel_encoder_info(m, intel_crtc, intel_encoder);
2848 }
2849
2850 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2851 {
2852         struct drm_display_mode *mode = panel->fixed_mode;
2853
2854         seq_printf(m, "\tfixed mode:\n");
2855         intel_seq_print_mode(m, 2, mode);
2856 }
2857
2858 static void intel_dp_info(struct seq_file *m,
2859                           struct intel_connector *intel_connector)
2860 {
2861         struct intel_encoder *intel_encoder = intel_connector->encoder;
2862         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2863
2864         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2865         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2866         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2867                 intel_panel_info(m, &intel_connector->panel);
2868
2869         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2870                                 &intel_dp->aux);
2871 }
2872
2873 static void intel_dp_mst_info(struct seq_file *m,
2874                           struct intel_connector *intel_connector)
2875 {
2876         struct intel_encoder *intel_encoder = intel_connector->encoder;
2877         struct intel_dp_mst_encoder *intel_mst =
2878                 enc_to_mst(&intel_encoder->base);
2879         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2880         struct intel_dp *intel_dp = &intel_dig_port->dp;
2881         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2882                                         intel_connector->port);
2883
2884         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2885 }
2886
2887 static void intel_hdmi_info(struct seq_file *m,
2888                             struct intel_connector *intel_connector)
2889 {
2890         struct intel_encoder *intel_encoder = intel_connector->encoder;
2891         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2892
2893         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2894 }
2895
2896 static void intel_lvds_info(struct seq_file *m,
2897                             struct intel_connector *intel_connector)
2898 {
2899         intel_panel_info(m, &intel_connector->panel);
2900 }
2901
2902 static void intel_connector_info(struct seq_file *m,
2903                                  struct drm_connector *connector)
2904 {
2905         struct intel_connector *intel_connector = to_intel_connector(connector);
2906         struct intel_encoder *intel_encoder = intel_connector->encoder;
2907         struct drm_display_mode *mode;
2908
2909         seq_printf(m, "connector %d: type %s, status: %s\n",
2910                    connector->base.id, connector->name,
2911                    drm_get_connector_status_name(connector->status));
2912         if (connector->status == connector_status_connected) {
2913                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2914                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2915                            connector->display_info.width_mm,
2916                            connector->display_info.height_mm);
2917                 seq_printf(m, "\tsubpixel order: %s\n",
2918                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2919                 seq_printf(m, "\tCEA rev: %d\n",
2920                            connector->display_info.cea_rev);
2921         }
2922
2923         if (!intel_encoder)
2924                 return;
2925
2926         switch (connector->connector_type) {
2927         case DRM_MODE_CONNECTOR_DisplayPort:
2928         case DRM_MODE_CONNECTOR_eDP:
2929                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2930                         intel_dp_mst_info(m, intel_connector);
2931                 else
2932                         intel_dp_info(m, intel_connector);
2933                 break;
2934         case DRM_MODE_CONNECTOR_LVDS:
2935                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2936                         intel_lvds_info(m, intel_connector);
2937                 break;
2938         case DRM_MODE_CONNECTOR_HDMIA:
2939                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2940                     intel_encoder->type == INTEL_OUTPUT_DDI)
2941                         intel_hdmi_info(m, intel_connector);
2942                 break;
2943         default:
2944                 break;
2945         }
2946
2947         seq_printf(m, "\tmodes:\n");
2948         list_for_each_entry(mode, &connector->modes, head)
2949                 intel_seq_print_mode(m, 2, mode);
2950 }
2951
2952 static const char *plane_type(enum drm_plane_type type)
2953 {
2954         switch (type) {
2955         case DRM_PLANE_TYPE_OVERLAY:
2956                 return "OVL";
2957         case DRM_PLANE_TYPE_PRIMARY:
2958                 return "PRI";
2959         case DRM_PLANE_TYPE_CURSOR:
2960                 return "CUR";
2961         /*
2962          * Deliberately omitting default: to generate compiler warnings
2963          * when a new drm_plane_type gets added.
2964          */
2965         }
2966
2967         return "unknown";
2968 }
2969
2970 static const char *plane_rotation(unsigned int rotation)
2971 {
2972         static char buf[48];
2973         /*
2974          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
2975          * will print them all to visualize if the values are misused
2976          */
2977         snprintf(buf, sizeof(buf),
2978                  "%s%s%s%s%s%s(0x%08x)",
2979                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
2980                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
2981                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
2982                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
2983                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
2984                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
2985                  rotation);
2986
2987         return buf;
2988 }
2989
2990 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2991 {
2992         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2993         struct drm_device *dev = &dev_priv->drm;
2994         struct intel_plane *intel_plane;
2995
2996         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2997                 struct drm_plane_state *state;
2998                 struct drm_plane *plane = &intel_plane->base;
2999                 struct drm_format_name_buf format_name;
3000
3001                 if (!plane->state) {
3002                         seq_puts(m, "plane->state is NULL!\n");
3003                         continue;
3004                 }
3005
3006                 state = plane->state;
3007
3008                 if (state->fb) {
3009                         drm_get_format_name(state->fb->format->format,
3010                                             &format_name);
3011                 } else {
3012                         sprintf(format_name.str, "N/A");
3013                 }
3014
3015                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3016                            plane->base.id,
3017                            plane_type(intel_plane->base.type),
3018                            state->crtc_x, state->crtc_y,
3019                            state->crtc_w, state->crtc_h,
3020                            (state->src_x >> 16),
3021                            ((state->src_x & 0xffff) * 15625) >> 10,
3022                            (state->src_y >> 16),
3023                            ((state->src_y & 0xffff) * 15625) >> 10,
3024                            (state->src_w >> 16),
3025                            ((state->src_w & 0xffff) * 15625) >> 10,
3026                            (state->src_h >> 16),
3027                            ((state->src_h & 0xffff) * 15625) >> 10,
3028                            format_name.str,
3029                            plane_rotation(state->rotation));
3030         }
3031 }
3032
3033 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3034 {
3035         struct intel_crtc_state *pipe_config;
3036         int num_scalers = intel_crtc->num_scalers;
3037         int i;
3038
3039         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3040
3041         /* Not all platformas have a scaler */
3042         if (num_scalers) {
3043                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3044                            num_scalers,
3045                            pipe_config->scaler_state.scaler_users,
3046                            pipe_config->scaler_state.scaler_id);
3047
3048                 for (i = 0; i < num_scalers; i++) {
3049                         struct intel_scaler *sc =
3050                                         &pipe_config->scaler_state.scalers[i];
3051
3052                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3053                                    i, yesno(sc->in_use), sc->mode);
3054                 }
3055                 seq_puts(m, "\n");
3056         } else {
3057                 seq_puts(m, "\tNo scalers available on this platform\n");
3058         }
3059 }
3060
3061 static int i915_display_info(struct seq_file *m, void *unused)
3062 {
3063         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3064         struct drm_device *dev = &dev_priv->drm;
3065         struct intel_crtc *crtc;
3066         struct drm_connector *connector;
3067         struct drm_connector_list_iter conn_iter;
3068
3069         intel_runtime_pm_get(dev_priv);
3070         seq_printf(m, "CRTC info\n");
3071         seq_printf(m, "---------\n");
3072         for_each_intel_crtc(dev, crtc) {
3073                 struct intel_crtc_state *pipe_config;
3074
3075                 drm_modeset_lock(&crtc->base.mutex, NULL);
3076                 pipe_config = to_intel_crtc_state(crtc->base.state);
3077
3078                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3079                            crtc->base.base.id, pipe_name(crtc->pipe),
3080                            yesno(pipe_config->base.active),
3081                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3082                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3083
3084                 if (pipe_config->base.active) {
3085                         struct intel_plane *cursor =
3086                                 to_intel_plane(crtc->base.cursor);
3087
3088                         intel_crtc_info(m, crtc);
3089
3090                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3091                                    yesno(cursor->base.state->visible),
3092                                    cursor->base.state->crtc_x,
3093                                    cursor->base.state->crtc_y,
3094                                    cursor->base.state->crtc_w,
3095                                    cursor->base.state->crtc_h,
3096                                    cursor->cursor.base);
3097                         intel_scaler_info(m, crtc);
3098                         intel_plane_info(m, crtc);
3099                 }
3100
3101                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3102                            yesno(!crtc->cpu_fifo_underrun_disabled),
3103                            yesno(!crtc->pch_fifo_underrun_disabled));
3104                 drm_modeset_unlock(&crtc->base.mutex);
3105         }
3106
3107         seq_printf(m, "\n");
3108         seq_printf(m, "Connector info\n");
3109         seq_printf(m, "--------------\n");
3110         mutex_lock(&dev->mode_config.mutex);
3111         drm_connector_list_iter_begin(dev, &conn_iter);
3112         drm_for_each_connector_iter(connector, &conn_iter)
3113                 intel_connector_info(m, connector);
3114         drm_connector_list_iter_end(&conn_iter);
3115         mutex_unlock(&dev->mode_config.mutex);
3116
3117         intel_runtime_pm_put(dev_priv);
3118
3119         return 0;
3120 }
3121
3122 static int i915_engine_info(struct seq_file *m, void *unused)
3123 {
3124         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3125         struct intel_engine_cs *engine;
3126         enum intel_engine_id id;
3127         struct drm_printer p;
3128
3129         intel_runtime_pm_get(dev_priv);
3130
3131         seq_printf(m, "GT awake? %s (epoch %u)\n",
3132                    yesno(dev_priv->gt.awake), dev_priv->gt.epoch);
3133         seq_printf(m, "Global active requests: %d\n",
3134                    dev_priv->gt.active_requests);
3135         seq_printf(m, "CS timestamp frequency: %u kHz\n",
3136                    dev_priv->info.cs_timestamp_frequency_khz);
3137
3138         p = drm_seq_file_printer(m);
3139         for_each_engine(engine, dev_priv, id)
3140                 intel_engine_dump(engine, &p, "%s\n", engine->name);
3141
3142         intel_runtime_pm_put(dev_priv);
3143
3144         return 0;
3145 }
3146
3147 static int i915_shrinker_info(struct seq_file *m, void *unused)
3148 {
3149         struct drm_i915_private *i915 = node_to_i915(m->private);
3150
3151         seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3152         seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3153
3154         return 0;
3155 }
3156
3157 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3158 {
3159         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3160         struct drm_device *dev = &dev_priv->drm;
3161         int i;
3162
3163         drm_modeset_lock_all(dev);
3164         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3165                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3166
3167                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3168                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3169                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3170                 seq_printf(m, " tracked hardware state:\n");
3171                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3172                 seq_printf(m, " dpll_md: 0x%08x\n",
3173                            pll->state.hw_state.dpll_md);
3174                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3175                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3176                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3177         }
3178         drm_modeset_unlock_all(dev);
3179
3180         return 0;
3181 }
3182
3183 static int i915_wa_registers(struct seq_file *m, void *unused)
3184 {
3185         int i;
3186         int ret;
3187         struct intel_engine_cs *engine;
3188         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3189         struct drm_device *dev = &dev_priv->drm;
3190         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3191         enum intel_engine_id id;
3192
3193         ret = mutex_lock_interruptible(&dev->struct_mutex);
3194         if (ret)
3195                 return ret;
3196
3197         intel_runtime_pm_get(dev_priv);
3198
3199         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3200         for_each_engine(engine, dev_priv, id)
3201                 seq_printf(m, "HW whitelist count for %s: %d\n",
3202                            engine->name, workarounds->hw_whitelist_count[id]);
3203         for (i = 0; i < workarounds->count; ++i) {
3204                 i915_reg_t addr;
3205                 u32 mask, value, read;
3206                 bool ok;
3207
3208                 addr = workarounds->reg[i].addr;
3209                 mask = workarounds->reg[i].mask;
3210                 value = workarounds->reg[i].value;
3211                 read = I915_READ(addr);
3212                 ok = (value & mask) == (read & mask);
3213                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3214                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3215         }
3216
3217         intel_runtime_pm_put(dev_priv);
3218         mutex_unlock(&dev->struct_mutex);
3219
3220         return 0;
3221 }
3222
3223 static int i915_ipc_status_show(struct seq_file *m, void *data)
3224 {
3225         struct drm_i915_private *dev_priv = m->private;
3226
3227         seq_printf(m, "Isochronous Priority Control: %s\n",
3228                         yesno(dev_priv->ipc_enabled));
3229         return 0;
3230 }
3231
3232 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3233 {
3234         struct drm_i915_private *dev_priv = inode->i_private;
3235
3236         if (!HAS_IPC(dev_priv))
3237                 return -ENODEV;
3238
3239         return single_open(file, i915_ipc_status_show, dev_priv);
3240 }
3241
3242 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3243                                      size_t len, loff_t *offp)
3244 {
3245         struct seq_file *m = file->private_data;
3246         struct drm_i915_private *dev_priv = m->private;
3247         int ret;
3248         bool enable;
3249
3250         ret = kstrtobool_from_user(ubuf, len, &enable);
3251         if (ret < 0)
3252                 return ret;
3253
3254         intel_runtime_pm_get(dev_priv);
3255         if (!dev_priv->ipc_enabled && enable)
3256                 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3257         dev_priv->wm.distrust_bios_wm = true;
3258         dev_priv->ipc_enabled = enable;
3259         intel_enable_ipc(dev_priv);
3260         intel_runtime_pm_put(dev_priv);
3261
3262         return len;
3263 }
3264
3265 static const struct file_operations i915_ipc_status_fops = {
3266         .owner = THIS_MODULE,
3267         .open = i915_ipc_status_open,
3268         .read = seq_read,
3269         .llseek = seq_lseek,
3270         .release = single_release,
3271         .write = i915_ipc_status_write
3272 };
3273
3274 static int i915_ddb_info(struct seq_file *m, void *unused)
3275 {
3276         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3277         struct drm_device *dev = &dev_priv->drm;
3278         struct skl_ddb_allocation *ddb;
3279         struct skl_ddb_entry *entry;
3280         enum pipe pipe;
3281         int plane;
3282
3283         if (INTEL_GEN(dev_priv) < 9)
3284                 return -ENODEV;
3285
3286         drm_modeset_lock_all(dev);
3287
3288         ddb = &dev_priv->wm.skl_hw.ddb;
3289
3290         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3291
3292         for_each_pipe(dev_priv, pipe) {
3293                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3294
3295                 for_each_universal_plane(dev_priv, pipe, plane) {
3296                         entry = &ddb->plane[pipe][plane];
3297                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3298                                    entry->start, entry->end,
3299                                    skl_ddb_entry_size(entry));
3300                 }
3301
3302                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3303                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3304                            entry->end, skl_ddb_entry_size(entry));
3305         }
3306
3307         drm_modeset_unlock_all(dev);
3308
3309         return 0;
3310 }
3311
3312 static void drrs_status_per_crtc(struct seq_file *m,
3313                                  struct drm_device *dev,
3314                                  struct intel_crtc *intel_crtc)
3315 {
3316         struct drm_i915_private *dev_priv = to_i915(dev);
3317         struct i915_drrs *drrs = &dev_priv->drrs;
3318         int vrefresh = 0;
3319         struct drm_connector *connector;
3320         struct drm_connector_list_iter conn_iter;
3321
3322         drm_connector_list_iter_begin(dev, &conn_iter);
3323         drm_for_each_connector_iter(connector, &conn_iter) {
3324                 if (connector->state->crtc != &intel_crtc->base)
3325                         continue;
3326
3327                 seq_printf(m, "%s:\n", connector->name);
3328         }
3329         drm_connector_list_iter_end(&conn_iter);
3330
3331         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3332                 seq_puts(m, "\tVBT: DRRS_type: Static");
3333         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3334                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3335         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3336                 seq_puts(m, "\tVBT: DRRS_type: None");
3337         else
3338                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3339
3340         seq_puts(m, "\n\n");
3341
3342         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3343                 struct intel_panel *panel;
3344
3345                 mutex_lock(&drrs->mutex);
3346                 /* DRRS Supported */
3347                 seq_puts(m, "\tDRRS Supported: Yes\n");
3348
3349                 /* disable_drrs() will make drrs->dp NULL */
3350                 if (!drrs->dp) {
3351                         seq_puts(m, "Idleness DRRS: Disabled\n");
3352                         if (dev_priv->psr.enabled)
3353                                 seq_puts(m,
3354                                 "\tAs PSR is enabled, DRRS is not enabled\n");
3355                         mutex_unlock(&drrs->mutex);
3356                         return;
3357                 }
3358
3359                 panel = &drrs->dp->attached_connector->panel;
3360                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3361                                         drrs->busy_frontbuffer_bits);
3362
3363                 seq_puts(m, "\n\t\t");
3364                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3365                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3366                         vrefresh = panel->fixed_mode->vrefresh;
3367                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3368                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3369                         vrefresh = panel->downclock_mode->vrefresh;
3370                 } else {
3371                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3372                                                 drrs->refresh_rate_type);
3373                         mutex_unlock(&drrs->mutex);
3374                         return;
3375                 }
3376                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3377
3378                 seq_puts(m, "\n\t\t");
3379                 mutex_unlock(&drrs->mutex);
3380         } else {
3381                 /* DRRS not supported. Print the VBT parameter*/
3382                 seq_puts(m, "\tDRRS Supported : No");
3383         }
3384         seq_puts(m, "\n");
3385 }
3386
3387 static int i915_drrs_status(struct seq_file *m, void *unused)
3388 {
3389         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3390         struct drm_device *dev = &dev_priv->drm;
3391         struct intel_crtc *intel_crtc;
3392         int active_crtc_cnt = 0;
3393
3394         drm_modeset_lock_all(dev);
3395         for_each_intel_crtc(dev, intel_crtc) {
3396                 if (intel_crtc->base.state->active) {
3397                         active_crtc_cnt++;
3398                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3399
3400                         drrs_status_per_crtc(m, dev, intel_crtc);
3401                 }
3402         }
3403         drm_modeset_unlock_all(dev);
3404
3405         if (!active_crtc_cnt)
3406                 seq_puts(m, "No active crtc found\n");
3407
3408         return 0;
3409 }
3410
3411 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3412 {
3413         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3414         struct drm_device *dev = &dev_priv->drm;
3415         struct intel_encoder *intel_encoder;
3416         struct intel_digital_port *intel_dig_port;
3417         struct drm_connector *connector;
3418         struct drm_connector_list_iter conn_iter;
3419
3420         drm_connector_list_iter_begin(dev, &conn_iter);
3421         drm_for_each_connector_iter(connector, &conn_iter) {
3422                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3423                         continue;
3424
3425                 intel_encoder = intel_attached_encoder(connector);
3426                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3427                         continue;
3428
3429                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3430                 if (!intel_dig_port->dp.can_mst)
3431                         continue;
3432
3433                 seq_printf(m, "MST Source Port %c\n",
3434                            port_name(intel_dig_port->base.port));
3435                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3436         }
3437         drm_connector_list_iter_end(&conn_iter);
3438
3439         return 0;
3440 }
3441
3442 static ssize_t i915_displayport_test_active_write(struct file *file,
3443                                                   const char __user *ubuf,
3444                                                   size_t len, loff_t *offp)
3445 {
3446         char *input_buffer;
3447         int status = 0;
3448         struct drm_device *dev;
3449         struct drm_connector *connector;
3450         struct drm_connector_list_iter conn_iter;
3451         struct intel_dp *intel_dp;
3452         int val = 0;
3453
3454         dev = ((struct seq_file *)file->private_data)->private;
3455
3456         if (len == 0)
3457                 return 0;
3458
3459         input_buffer = memdup_user_nul(ubuf, len);
3460         if (IS_ERR(input_buffer))
3461                 return PTR_ERR(input_buffer);
3462
3463         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3464
3465         drm_connector_list_iter_begin(dev, &conn_iter);
3466         drm_for_each_connector_iter(connector, &conn_iter) {
3467                 struct intel_encoder *encoder;
3468
3469                 if (connector->connector_type !=
3470                     DRM_MODE_CONNECTOR_DisplayPort)
3471                         continue;
3472
3473                 encoder = to_intel_encoder(connector->encoder);
3474                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3475                         continue;
3476
3477                 if (encoder && connector->status == connector_status_connected) {
3478                         intel_dp = enc_to_intel_dp(&encoder->base);
3479                         status = kstrtoint(input_buffer, 10, &val);
3480                         if (status < 0)
3481                                 break;
3482                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3483                         /* To prevent erroneous activation of the compliance
3484                          * testing code, only accept an actual value of 1 here
3485                          */
3486                         if (val == 1)
3487                                 intel_dp->compliance.test_active = 1;
3488                         else
3489                                 intel_dp->compliance.test_active = 0;
3490                 }
3491         }
3492         drm_connector_list_iter_end(&conn_iter);
3493         kfree(input_buffer);
3494         if (status < 0)
3495                 return status;
3496
3497         *offp += len;
3498         return len;
3499 }
3500
3501 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3502 {
3503         struct drm_device *dev = m->private;
3504         struct drm_connector *connector;
3505         struct drm_connector_list_iter conn_iter;
3506         struct intel_dp *intel_dp;
3507
3508         drm_connector_list_iter_begin(dev, &conn_iter);
3509         drm_for_each_connector_iter(connector, &conn_iter) {
3510                 struct intel_encoder *encoder;
3511
3512                 if (connector->connector_type !=
3513                     DRM_MODE_CONNECTOR_DisplayPort)
3514                         continue;
3515
3516                 encoder = to_intel_encoder(connector->encoder);
3517                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3518                         continue;
3519
3520                 if (encoder && connector->status == connector_status_connected) {
3521                         intel_dp = enc_to_intel_dp(&encoder->base);
3522                         if (intel_dp->compliance.test_active)
3523                                 seq_puts(m, "1");
3524                         else
3525                                 seq_puts(m, "0");
3526                 } else
3527                         seq_puts(m, "0");
3528         }
3529         drm_connector_list_iter_end(&conn_iter);
3530
3531         return 0;
3532 }
3533
3534 static int i915_displayport_test_active_open(struct inode *inode,
3535                                              struct file *file)
3536 {
3537         struct drm_i915_private *dev_priv = inode->i_private;
3538
3539         return single_open(file, i915_displayport_test_active_show,
3540                            &dev_priv->drm);
3541 }
3542
3543 static const struct file_operations i915_displayport_test_active_fops = {
3544         .owner = THIS_MODULE,
3545         .open = i915_displayport_test_active_open,
3546         .read = seq_read,
3547         .llseek = seq_lseek,
3548         .release = single_release,
3549         .write = i915_displayport_test_active_write
3550 };
3551
3552 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3553 {
3554         struct drm_device *dev = m->private;
3555         struct drm_connector *connector;
3556         struct drm_connector_list_iter conn_iter;
3557         struct intel_dp *intel_dp;
3558
3559         drm_connector_list_iter_begin(dev, &conn_iter);
3560         drm_for_each_connector_iter(connector, &conn_iter) {
3561                 struct intel_encoder *encoder;
3562
3563                 if (connector->connector_type !=
3564                     DRM_MODE_CONNECTOR_DisplayPort)
3565                         continue;
3566
3567                 encoder = to_intel_encoder(connector->encoder);
3568                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3569                         continue;
3570
3571                 if (encoder && connector->status == connector_status_connected) {
3572                         intel_dp = enc_to_intel_dp(&encoder->base);
3573                         if (intel_dp->compliance.test_type ==
3574                             DP_TEST_LINK_EDID_READ)
3575                                 seq_printf(m, "%lx",
3576                                            intel_dp->compliance.test_data.edid);
3577                         else if (intel_dp->compliance.test_type ==
3578                                  DP_TEST_LINK_VIDEO_PATTERN) {
3579                                 seq_printf(m, "hdisplay: %d\n",
3580                                            intel_dp->compliance.test_data.hdisplay);
3581                                 seq_printf(m, "vdisplay: %d\n",
3582                                            intel_dp->compliance.test_data.vdisplay);
3583                                 seq_printf(m, "bpc: %u\n",
3584                                            intel_dp->compliance.test_data.bpc);
3585                         }
3586                 } else
3587                         seq_puts(m, "0");
3588         }
3589         drm_connector_list_iter_end(&conn_iter);
3590
3591         return 0;
3592 }
3593 static int i915_displayport_test_data_open(struct inode *inode,
3594                                            struct file *file)
3595 {
3596         struct drm_i915_private *dev_priv = inode->i_private;
3597
3598         return single_open(file, i915_displayport_test_data_show,
3599                            &dev_priv->drm);
3600 }
3601
3602 static const struct file_operations i915_displayport_test_data_fops = {
3603         .owner = THIS_MODULE,
3604         .open = i915_displayport_test_data_open,
3605         .read = seq_read,
3606         .llseek = seq_lseek,
3607         .release = single_release
3608 };
3609
3610 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3611 {
3612         struct drm_device *dev = m->private;
3613         struct drm_connector *connector;
3614         struct drm_connector_list_iter conn_iter;
3615         struct intel_dp *intel_dp;
3616
3617         drm_connector_list_iter_begin(dev, &conn_iter);
3618         drm_for_each_connector_iter(connector, &conn_iter) {
3619                 struct intel_encoder *encoder;
3620
3621                 if (connector->connector_type !=
3622                     DRM_MODE_CONNECTOR_DisplayPort)
3623                         continue;
3624
3625                 encoder = to_intel_encoder(connector->encoder);
3626                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3627                         continue;
3628
3629                 if (encoder && connector->status == connector_status_connected) {
3630                         intel_dp = enc_to_intel_dp(&encoder->base);
3631                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3632                 } else
3633                         seq_puts(m, "0");
3634         }
3635         drm_connector_list_iter_end(&conn_iter);
3636
3637         return 0;
3638 }
3639
3640 static int i915_displayport_test_type_open(struct inode *inode,
3641                                        struct file *file)
3642 {
3643         struct drm_i915_private *dev_priv = inode->i_private;
3644
3645         return single_open(file, i915_displayport_test_type_show,
3646                            &dev_priv->drm);
3647 }
3648
3649 static const struct file_operations i915_displayport_test_type_fops = {
3650         .owner = THIS_MODULE,
3651         .open = i915_displayport_test_type_open,
3652         .read = seq_read,
3653         .llseek = seq_lseek,
3654         .release = single_release
3655 };
3656
3657 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3658 {
3659         struct drm_i915_private *dev_priv = m->private;
3660         struct drm_device *dev = &dev_priv->drm;
3661         int level;
3662         int num_levels;
3663
3664         if (IS_CHERRYVIEW(dev_priv))
3665                 num_levels = 3;
3666         else if (IS_VALLEYVIEW(dev_priv))
3667                 num_levels = 1;
3668         else if (IS_G4X(dev_priv))
3669                 num_levels = 3;
3670         else
3671                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3672
3673         drm_modeset_lock_all(dev);
3674
3675         for (level = 0; level < num_levels; level++) {
3676                 unsigned int latency = wm[level];
3677
3678                 /*
3679                  * - WM1+ latency values in 0.5us units
3680                  * - latencies are in us on gen9/vlv/chv
3681                  */
3682                 if (INTEL_GEN(dev_priv) >= 9 ||
3683                     IS_VALLEYVIEW(dev_priv) ||
3684                     IS_CHERRYVIEW(dev_priv) ||
3685                     IS_G4X(dev_priv))
3686                         latency *= 10;
3687                 else if (level > 0)
3688                         latency *= 5;
3689
3690                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3691                            level, wm[level], latency / 10, latency % 10);
3692         }
3693
3694         drm_modeset_unlock_all(dev);
3695 }
3696
3697 static int pri_wm_latency_show(struct seq_file *m, void *data)
3698 {
3699         struct drm_i915_private *dev_priv = m->private;
3700         const uint16_t *latencies;
3701
3702         if (INTEL_GEN(dev_priv) >= 9)
3703                 latencies = dev_priv->wm.skl_latency;
3704         else
3705                 latencies = dev_priv->wm.pri_latency;
3706
3707         wm_latency_show(m, latencies);
3708
3709         return 0;
3710 }
3711
3712 static int spr_wm_latency_show(struct seq_file *m, void *data)
3713 {
3714         struct drm_i915_private *dev_priv = m->private;
3715         const uint16_t *latencies;
3716
3717         if (INTEL_GEN(dev_priv) >= 9)
3718                 latencies = dev_priv->wm.skl_latency;
3719         else
3720                 latencies = dev_priv->wm.spr_latency;
3721
3722         wm_latency_show(m, latencies);
3723
3724         return 0;
3725 }
3726
3727 static int cur_wm_latency_show(struct seq_file *m, void *data)
3728 {
3729         struct drm_i915_private *dev_priv = m->private;
3730         const uint16_t *latencies;
3731
3732         if (INTEL_GEN(dev_priv) >= 9)
3733                 latencies = dev_priv->wm.skl_latency;
3734         else
3735                 latencies = dev_priv->wm.cur_latency;
3736
3737         wm_latency_show(m, latencies);
3738
3739         return 0;
3740 }
3741
3742 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3743 {
3744         struct drm_i915_private *dev_priv = inode->i_private;
3745
3746         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3747                 return -ENODEV;
3748
3749         return single_open(file, pri_wm_latency_show, dev_priv);
3750 }
3751
3752 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3753 {
3754         struct drm_i915_private *dev_priv = inode->i_private;
3755
3756         if (HAS_GMCH_DISPLAY(dev_priv))
3757                 return -ENODEV;
3758
3759         return single_open(file, spr_wm_latency_show, dev_priv);
3760 }
3761
3762 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3763 {
3764         struct drm_i915_private *dev_priv = inode->i_private;
3765
3766         if (HAS_GMCH_DISPLAY(dev_priv))
3767                 return -ENODEV;
3768
3769         return single_open(file, cur_wm_latency_show, dev_priv);
3770 }
3771
3772 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3773                                 size_t len, loff_t *offp, uint16_t wm[8])
3774 {
3775         struct seq_file *m = file->private_data;
3776         struct drm_i915_private *dev_priv = m->private;
3777         struct drm_device *dev = &dev_priv->drm;
3778         uint16_t new[8] = { 0 };
3779         int num_levels;
3780         int level;
3781         int ret;
3782         char tmp[32];
3783
3784         if (IS_CHERRYVIEW(dev_priv))
3785                 num_levels = 3;
3786         else if (IS_VALLEYVIEW(dev_priv))
3787                 num_levels = 1;
3788         else if (IS_G4X(dev_priv))
3789                 num_levels = 3;
3790         else
3791                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3792
3793         if (len >= sizeof(tmp))
3794                 return -EINVAL;
3795
3796         if (copy_from_user(tmp, ubuf, len))
3797                 return -EFAULT;
3798
3799         tmp[len] = '\0';
3800
3801         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3802                      &new[0], &new[1], &new[2], &new[3],
3803                      &new[4], &new[5], &new[6], &new[7]);
3804         if (ret != num_levels)
3805                 return -EINVAL;
3806
3807         drm_modeset_lock_all(dev);
3808
3809         for (level = 0; level < num_levels; level++)
3810                 wm[level] = new[level];
3811
3812         drm_modeset_unlock_all(dev);
3813
3814         return len;
3815 }
3816
3817
3818 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3819                                     size_t len, loff_t *offp)
3820 {
3821         struct seq_file *m = file->private_data;
3822         struct drm_i915_private *dev_priv = m->private;
3823         uint16_t *latencies;
3824
3825         if (INTEL_GEN(dev_priv) >= 9)
3826                 latencies = dev_priv->wm.skl_latency;
3827         else
3828                 latencies = dev_priv->wm.pri_latency;
3829
3830         return wm_latency_write(file, ubuf, len, offp, latencies);
3831 }
3832
3833 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3834                                     size_t len, loff_t *offp)
3835 {
3836         struct seq_file *m = file->private_data;
3837         struct drm_i915_private *dev_priv = m->private;
3838         uint16_t *latencies;
3839
3840         if (INTEL_GEN(dev_priv) >= 9)
3841                 latencies = dev_priv->wm.skl_latency;
3842         else
3843                 latencies = dev_priv->wm.spr_latency;
3844
3845         return wm_latency_write(file, ubuf, len, offp, latencies);
3846 }
3847
3848 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3849                                     size_t len, loff_t *offp)
3850 {
3851         struct seq_file *m = file->private_data;
3852         struct drm_i915_private *dev_priv = m->private;
3853         uint16_t *latencies;
3854
3855         if (INTEL_GEN(dev_priv) >= 9)
3856                 latencies = dev_priv->wm.skl_latency;
3857         else
3858                 latencies = dev_priv->wm.cur_latency;
3859
3860         return wm_latency_write(file, ubuf, len, offp, latencies);
3861 }
3862
3863 static const struct file_operations i915_pri_wm_latency_fops = {
3864         .owner = THIS_MODULE,
3865         .open = pri_wm_latency_open,
3866         .read = seq_read,
3867         .llseek = seq_lseek,
3868         .release = single_release,
3869         .write = pri_wm_latency_write
3870 };
3871
3872 static const struct file_operations i915_spr_wm_latency_fops = {
3873         .owner = THIS_MODULE,
3874         .open = spr_wm_latency_open,
3875         .read = seq_read,
3876         .llseek = seq_lseek,
3877         .release = single_release,
3878         .write = spr_wm_latency_write
3879 };
3880
3881 static const struct file_operations i915_cur_wm_latency_fops = {
3882         .owner = THIS_MODULE,
3883         .open = cur_wm_latency_open,
3884         .read = seq_read,
3885         .llseek = seq_lseek,
3886         .release = single_release,
3887         .write = cur_wm_latency_write
3888 };
3889
3890 static int
3891 i915_wedged_get(void *data, u64 *val)
3892 {
3893         struct drm_i915_private *dev_priv = data;
3894
3895         *val = i915_terminally_wedged(&dev_priv->gpu_error);
3896
3897         return 0;
3898 }
3899
3900 static int
3901 i915_wedged_set(void *data, u64 val)
3902 {
3903         struct drm_i915_private *i915 = data;
3904         struct intel_engine_cs *engine;
3905         unsigned int tmp;
3906
3907         /*
3908          * There is no safeguard against this debugfs entry colliding
3909          * with the hangcheck calling same i915_handle_error() in
3910          * parallel, causing an explosion. For now we assume that the
3911          * test harness is responsible enough not to inject gpu hangs
3912          * while it is writing to 'i915_wedged'
3913          */
3914
3915         if (i915_reset_backoff(&i915->gpu_error))
3916                 return -EAGAIN;
3917
3918         for_each_engine_masked(engine, i915, val, tmp) {
3919                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
3920                 engine->hangcheck.stalled = true;
3921         }
3922
3923         i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
3924
3925         wait_on_bit(&i915->gpu_error.flags,
3926                     I915_RESET_HANDOFF,
3927                     TASK_UNINTERRUPTIBLE);
3928
3929         return 0;
3930 }
3931
3932 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3933                         i915_wedged_get, i915_wedged_set,
3934                         "%llu\n");
3935
3936 static int
3937 fault_irq_set(struct drm_i915_private *i915,
3938               unsigned long *irq,
3939               unsigned long val)
3940 {
3941         int err;
3942
3943         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
3944         if (err)
3945                 return err;
3946
3947         err = i915_gem_wait_for_idle(i915,
3948                                      I915_WAIT_LOCKED |
3949                                      I915_WAIT_INTERRUPTIBLE);
3950         if (err)
3951                 goto err_unlock;
3952
3953         *irq = val;
3954         mutex_unlock(&i915->drm.struct_mutex);
3955
3956         /* Flush idle worker to disarm irq */
3957         drain_delayed_work(&i915->gt.idle_work);
3958
3959         return 0;
3960
3961 err_unlock:
3962         mutex_unlock(&i915->drm.struct_mutex);
3963         return err;
3964 }
3965
3966 static int
3967 i915_ring_missed_irq_get(void *data, u64 *val)
3968 {
3969         struct drm_i915_private *dev_priv = data;
3970
3971         *val = dev_priv->gpu_error.missed_irq_rings;
3972         return 0;
3973 }
3974
3975 static int
3976 i915_ring_missed_irq_set(void *data, u64 val)
3977 {
3978         struct drm_i915_private *i915 = data;
3979
3980         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
3981 }
3982
3983 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3984                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3985                         "0x%08llx\n");
3986
3987 static int
3988 i915_ring_test_irq_get(void *data, u64 *val)
3989 {
3990         struct drm_i915_private *dev_priv = data;
3991
3992         *val = dev_priv->gpu_error.test_irq_rings;
3993
3994         return 0;
3995 }
3996
3997 static int
3998 i915_ring_test_irq_set(void *data, u64 val)
3999 {
4000         struct drm_i915_private *i915 = data;
4001
4002         val &= INTEL_INFO(i915)->ring_mask;
4003         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4004
4005         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4006 }
4007
4008 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4009                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4010                         "0x%08llx\n");
4011
4012 #define DROP_UNBOUND    BIT(0)
4013 #define DROP_BOUND      BIT(1)
4014 #define DROP_RETIRE     BIT(2)
4015 #define DROP_ACTIVE     BIT(3)
4016 #define DROP_FREED      BIT(4)
4017 #define DROP_SHRINK_ALL BIT(5)
4018 #define DROP_IDLE       BIT(6)
4019 #define DROP_ALL (DROP_UNBOUND  | \
4020                   DROP_BOUND    | \
4021                   DROP_RETIRE   | \
4022                   DROP_ACTIVE   | \
4023                   DROP_FREED    | \
4024                   DROP_SHRINK_ALL |\
4025                   DROP_IDLE)
4026 static int
4027 i915_drop_caches_get(void *data, u64 *val)
4028 {
4029         *val = DROP_ALL;
4030
4031         return 0;
4032 }
4033
4034 static int
4035 i915_drop_caches_set(void *data, u64 val)
4036 {
4037         struct drm_i915_private *dev_priv = data;
4038         struct drm_device *dev = &dev_priv->drm;
4039         int ret = 0;
4040
4041         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4042                   val, val & DROP_ALL);
4043
4044         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4045          * on ioctls on -EAGAIN. */
4046         if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4047                 ret = mutex_lock_interruptible(&dev->struct_mutex);
4048                 if (ret)
4049                         return ret;
4050
4051                 if (val & DROP_ACTIVE)
4052                         ret = i915_gem_wait_for_idle(dev_priv,
4053                                                      I915_WAIT_INTERRUPTIBLE |
4054                                                      I915_WAIT_LOCKED);
4055
4056                 if (val & DROP_RETIRE)
4057                         i915_gem_retire_requests(dev_priv);
4058
4059                 mutex_unlock(&dev->struct_mutex);
4060         }
4061
4062         fs_reclaim_acquire(GFP_KERNEL);
4063         if (val & DROP_BOUND)
4064                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4065
4066         if (val & DROP_UNBOUND)
4067                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4068
4069         if (val & DROP_SHRINK_ALL)
4070                 i915_gem_shrink_all(dev_priv);
4071         fs_reclaim_release(GFP_KERNEL);
4072
4073         if (val & DROP_IDLE)
4074                 drain_delayed_work(&dev_priv->gt.idle_work);
4075
4076         if (val & DROP_FREED) {
4077                 synchronize_rcu();
4078                 i915_gem_drain_freed_objects(dev_priv);
4079         }
4080
4081         return ret;
4082 }
4083
4084 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4085                         i915_drop_caches_get, i915_drop_caches_set,
4086                         "0x%08llx\n");
4087
4088 static int
4089 i915_max_freq_get(void *data, u64 *val)
4090 {
4091         struct drm_i915_private *dev_priv = data;
4092
4093         if (INTEL_GEN(dev_priv) < 6)
4094                 return -ENODEV;
4095
4096         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4097         return 0;
4098 }
4099
4100 static int
4101 i915_max_freq_set(void *data, u64 val)
4102 {
4103         struct drm_i915_private *dev_priv = data;
4104         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4105         u32 hw_max, hw_min;
4106         int ret;
4107
4108         if (INTEL_GEN(dev_priv) < 6)
4109                 return -ENODEV;
4110
4111         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4112
4113         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4114         if (ret)
4115                 return ret;
4116
4117         /*
4118          * Turbo will still be enabled, but won't go above the set value.
4119          */
4120         val = intel_freq_opcode(dev_priv, val);
4121
4122         hw_max = rps->max_freq;
4123         hw_min = rps->min_freq;
4124
4125         if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4126                 mutex_unlock(&dev_priv->pcu_lock);
4127                 return -EINVAL;
4128         }
4129
4130         rps->max_freq_softlimit = val;
4131
4132         if (intel_set_rps(dev_priv, val))
4133                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4134
4135         mutex_unlock(&dev_priv->pcu_lock);
4136
4137         return 0;
4138 }
4139
4140 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4141                         i915_max_freq_get, i915_max_freq_set,
4142                         "%llu\n");
4143
4144 static int
4145 i915_min_freq_get(void *data, u64 *val)
4146 {
4147         struct drm_i915_private *dev_priv = data;
4148
4149         if (INTEL_GEN(dev_priv) < 6)
4150                 return -ENODEV;
4151
4152         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4153         return 0;
4154 }
4155
4156 static int
4157 i915_min_freq_set(void *data, u64 val)
4158 {
4159         struct drm_i915_private *dev_priv = data;
4160         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4161         u32 hw_max, hw_min;
4162         int ret;
4163
4164         if (INTEL_GEN(dev_priv) < 6)
4165                 return -ENODEV;
4166
4167         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4168
4169         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4170         if (ret)
4171                 return ret;
4172
4173         /*
4174          * Turbo will still be enabled, but won't go below the set value.
4175          */
4176         val = intel_freq_opcode(dev_priv, val);
4177
4178         hw_max = rps->max_freq;
4179         hw_min = rps->min_freq;
4180
4181         if (val < hw_min ||
4182             val > hw_max || val > rps->max_freq_softlimit) {
4183                 mutex_unlock(&dev_priv->pcu_lock);
4184                 return -EINVAL;
4185         }
4186
4187         rps->min_freq_softlimit = val;
4188
4189         if (intel_set_rps(dev_priv, val))
4190                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4191
4192         mutex_unlock(&dev_priv->pcu_lock);
4193
4194         return 0;
4195 }
4196
4197 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4198                         i915_min_freq_get, i915_min_freq_set,
4199                         "%llu\n");
4200
4201 static int
4202 i915_cache_sharing_get(void *data, u64 *val)
4203 {
4204         struct drm_i915_private *dev_priv = data;
4205         u32 snpcr;
4206
4207         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4208                 return -ENODEV;
4209
4210         intel_runtime_pm_get(dev_priv);
4211
4212         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4213
4214         intel_runtime_pm_put(dev_priv);
4215
4216         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4217
4218         return 0;
4219 }
4220
4221 static int
4222 i915_cache_sharing_set(void *data, u64 val)
4223 {
4224         struct drm_i915_private *dev_priv = data;
4225         u32 snpcr;
4226
4227         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4228                 return -ENODEV;
4229
4230         if (val > 3)
4231                 return -EINVAL;
4232
4233         intel_runtime_pm_get(dev_priv);
4234         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4235
4236         /* Update the cache sharing policy here as well */
4237         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4238         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4239         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4240         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4241
4242         intel_runtime_pm_put(dev_priv);
4243         return 0;
4244 }
4245
4246 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4247                         i915_cache_sharing_get, i915_cache_sharing_set,
4248                         "%llu\n");
4249
4250 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4251                                           struct sseu_dev_info *sseu)
4252 {
4253         int ss_max = 2;
4254         int ss;
4255         u32 sig1[ss_max], sig2[ss_max];
4256
4257         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4258         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4259         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4260         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4261
4262         for (ss = 0; ss < ss_max; ss++) {
4263                 unsigned int eu_cnt;
4264
4265                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4266                         /* skip disabled subslice */
4267                         continue;
4268
4269                 sseu->slice_mask = BIT(0);
4270                 sseu->subslice_mask |= BIT(ss);
4271                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4272                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4273                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4274                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4275                 sseu->eu_total += eu_cnt;
4276                 sseu->eu_per_subslice = max_t(unsigned int,
4277                                               sseu->eu_per_subslice, eu_cnt);
4278         }
4279 }
4280
4281 static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
4282                                      struct sseu_dev_info *sseu)
4283 {
4284         const struct intel_device_info *info = INTEL_INFO(dev_priv);
4285         int s_max = 6, ss_max = 4;
4286         int s, ss;
4287         u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
4288
4289         for (s = 0; s < s_max; s++) {
4290                 /*
4291                  * FIXME: Valid SS Mask respects the spec and read
4292                  * only valid bits for those registers, excluding reserverd
4293                  * although this seems wrong because it would leave many
4294                  * subslices without ACK.
4295                  */
4296                 s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
4297                         GEN10_PGCTL_VALID_SS_MASK(s);
4298                 eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
4299                 eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
4300         }
4301
4302         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4303                      GEN9_PGCTL_SSA_EU19_ACK |
4304                      GEN9_PGCTL_SSA_EU210_ACK |
4305                      GEN9_PGCTL_SSA_EU311_ACK;
4306         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4307                      GEN9_PGCTL_SSB_EU19_ACK |
4308                      GEN9_PGCTL_SSB_EU210_ACK |
4309                      GEN9_PGCTL_SSB_EU311_ACK;
4310
4311         for (s = 0; s < s_max; s++) {
4312                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4313                         /* skip disabled slice */
4314                         continue;
4315
4316                 sseu->slice_mask |= BIT(s);
4317                 sseu->subslice_mask = info->sseu.subslice_mask;
4318
4319                 for (ss = 0; ss < ss_max; ss++) {
4320                         unsigned int eu_cnt;
4321
4322                         if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4323                                 /* skip disabled subslice */
4324                                 continue;
4325
4326                         eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
4327                                                eu_mask[ss % 2]);
4328                         sseu->eu_total += eu_cnt;
4329                         sseu->eu_per_subslice = max_t(unsigned int,
4330                                                       sseu->eu_per_subslice,
4331                                                       eu_cnt);
4332                 }
4333         }
4334 }
4335
4336 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4337                                     struct sseu_dev_info *sseu)
4338 {
4339         int s_max = 3, ss_max = 4;
4340         int s, ss;
4341         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4342
4343         /* BXT has a single slice and at most 3 subslices. */
4344         if (IS_GEN9_LP(dev_priv)) {
4345                 s_max = 1;
4346                 ss_max = 3;
4347         }
4348
4349         for (s = 0; s < s_max; s++) {
4350                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4351                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4352                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4353         }
4354
4355         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4356                      GEN9_PGCTL_SSA_EU19_ACK |
4357                      GEN9_PGCTL_SSA_EU210_ACK |
4358                      GEN9_PGCTL_SSA_EU311_ACK;
4359         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4360                      GEN9_PGCTL_SSB_EU19_ACK |
4361                      GEN9_PGCTL_SSB_EU210_ACK |
4362                      GEN9_PGCTL_SSB_EU311_ACK;
4363
4364         for (s = 0; s < s_max; s++) {
4365                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4366                         /* skip disabled slice */
4367                         continue;
4368
4369                 sseu->slice_mask |= BIT(s);
4370
4371                 if (IS_GEN9_BC(dev_priv))
4372                         sseu->subslice_mask =
4373                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4374
4375                 for (ss = 0; ss < ss_max; ss++) {
4376                         unsigned int eu_cnt;
4377
4378                         if (IS_GEN9_LP(dev_priv)) {
4379                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4380                                         /* skip disabled subslice */
4381                                         continue;
4382
4383                                 sseu->subslice_mask |= BIT(ss);
4384                         }
4385
4386                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4387                                                eu_mask[ss%2]);
4388                         sseu->eu_total += eu_cnt;
4389                         sseu->eu_per_subslice = max_t(unsigned int,
4390                                                       sseu->eu_per_subslice,
4391                                                       eu_cnt);
4392                 }
4393         }
4394 }
4395
4396 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4397                                          struct sseu_dev_info *sseu)
4398 {
4399         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4400         int s;
4401
4402         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4403
4404         if (sseu->slice_mask) {
4405                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4406                 sseu->eu_per_subslice =
4407                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4408                 sseu->eu_total = sseu->eu_per_subslice *
4409                                  sseu_subslice_total(sseu);
4410
4411                 /* subtract fused off EU(s) from enabled slice(s) */
4412                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4413                         u8 subslice_7eu =
4414                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4415
4416                         sseu->eu_total -= hweight8(subslice_7eu);
4417                 }
4418         }
4419 }
4420
4421 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4422                                  const struct sseu_dev_info *sseu)
4423 {
4424         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4425         const char *type = is_available_info ? "Available" : "Enabled";
4426
4427         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4428                    sseu->slice_mask);
4429         seq_printf(m, "  %s Slice Total: %u\n", type,
4430                    hweight8(sseu->slice_mask));
4431         seq_printf(m, "  %s Subslice Total: %u\n", type,
4432                    sseu_subslice_total(sseu));
4433         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4434                    sseu->subslice_mask);
4435         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4436                    hweight8(sseu->subslice_mask));
4437         seq_printf(m, "  %s EU Total: %u\n", type,
4438                    sseu->eu_total);
4439         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4440                    sseu->eu_per_subslice);
4441
4442         if (!is_available_info)
4443                 return;
4444
4445         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4446         if (HAS_POOLED_EU(dev_priv))
4447                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4448
4449         seq_printf(m, "  Has Slice Power Gating: %s\n",
4450                    yesno(sseu->has_slice_pg));
4451         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4452                    yesno(sseu->has_subslice_pg));
4453         seq_printf(m, "  Has EU Power Gating: %s\n",
4454                    yesno(sseu->has_eu_pg));
4455 }
4456
4457 static int i915_sseu_status(struct seq_file *m, void *unused)
4458 {
4459         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4460         struct sseu_dev_info sseu;
4461
4462         if (INTEL_GEN(dev_priv) < 8)
4463                 return -ENODEV;
4464
4465         seq_puts(m, "SSEU Device Info\n");
4466         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4467
4468         seq_puts(m, "SSEU Device Status\n");
4469         memset(&sseu, 0, sizeof(sseu));
4470
4471         intel_runtime_pm_get(dev_priv);
4472
4473         if (IS_CHERRYVIEW(dev_priv)) {
4474                 cherryview_sseu_device_status(dev_priv, &sseu);
4475         } else if (IS_BROADWELL(dev_priv)) {
4476                 broadwell_sseu_device_status(dev_priv, &sseu);
4477         } else if (IS_GEN9(dev_priv)) {
4478                 gen9_sseu_device_status(dev_priv, &sseu);
4479         } else if (INTEL_GEN(dev_priv) >= 10) {
4480                 gen10_sseu_device_status(dev_priv, &sseu);
4481         }
4482
4483         intel_runtime_pm_put(dev_priv);
4484
4485         i915_print_sseu_info(m, false, &sseu);
4486
4487         return 0;
4488 }
4489
4490 static int i915_forcewake_open(struct inode *inode, struct file *file)
4491 {
4492         struct drm_i915_private *i915 = inode->i_private;
4493
4494         if (INTEL_GEN(i915) < 6)
4495                 return 0;
4496
4497         intel_runtime_pm_get(i915);
4498         intel_uncore_forcewake_user_get(i915);
4499
4500         return 0;
4501 }
4502
4503 static int i915_forcewake_release(struct inode *inode, struct file *file)
4504 {
4505         struct drm_i915_private *i915 = inode->i_private;
4506
4507         if (INTEL_GEN(i915) < 6)
4508                 return 0;
4509
4510         intel_uncore_forcewake_user_put(i915);
4511         intel_runtime_pm_put(i915);
4512
4513         return 0;
4514 }
4515
4516 static const struct file_operations i915_forcewake_fops = {
4517         .owner = THIS_MODULE,
4518         .open = i915_forcewake_open,
4519         .release = i915_forcewake_release,
4520 };
4521
4522 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4523 {
4524         struct drm_i915_private *dev_priv = m->private;
4525         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4526
4527         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4528         seq_printf(m, "Detected: %s\n",
4529                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4530
4531         return 0;
4532 }
4533
4534 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4535                                         const char __user *ubuf, size_t len,
4536                                         loff_t *offp)
4537 {
4538         struct seq_file *m = file->private_data;
4539         struct drm_i915_private *dev_priv = m->private;
4540         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4541         unsigned int new_threshold;
4542         int i;
4543         char *newline;
4544         char tmp[16];
4545
4546         if (len >= sizeof(tmp))
4547                 return -EINVAL;
4548
4549         if (copy_from_user(tmp, ubuf, len))
4550                 return -EFAULT;
4551
4552         tmp[len] = '\0';
4553
4554         /* Strip newline, if any */
4555         newline = strchr(tmp, '\n');
4556         if (newline)
4557                 *newline = '\0';
4558
4559         if (strcmp(tmp, "reset") == 0)
4560                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4561         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4562                 return -EINVAL;
4563
4564         if (new_threshold > 0)
4565                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4566                               new_threshold);
4567         else
4568                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4569
4570         spin_lock_irq(&dev_priv->irq_lock);
4571         hotplug->hpd_storm_threshold = new_threshold;
4572         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4573         for_each_hpd_pin(i)
4574                 hotplug->stats[i].count = 0;
4575         spin_unlock_irq(&dev_priv->irq_lock);
4576
4577         /* Re-enable hpd immediately if we were in an irq storm */
4578         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4579
4580         return len;
4581 }
4582
4583 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4584 {
4585         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4586 }
4587
4588 static const struct file_operations i915_hpd_storm_ctl_fops = {
4589         .owner = THIS_MODULE,
4590         .open = i915_hpd_storm_ctl_open,
4591         .read = seq_read,
4592         .llseek = seq_lseek,
4593         .release = single_release,
4594         .write = i915_hpd_storm_ctl_write
4595 };
4596
4597 static int i915_drrs_ctl_set(void *data, u64 val)
4598 {
4599         struct drm_i915_private *dev_priv = data;
4600         struct drm_device *dev = &dev_priv->drm;
4601         struct intel_crtc *intel_crtc;
4602         struct intel_encoder *encoder;
4603         struct intel_dp *intel_dp;
4604
4605         if (INTEL_GEN(dev_priv) < 7)
4606                 return -ENODEV;
4607
4608         drm_modeset_lock_all(dev);
4609         for_each_intel_crtc(dev, intel_crtc) {
4610                 if (!intel_crtc->base.state->active ||
4611                                         !intel_crtc->config->has_drrs)
4612                         continue;
4613
4614                 for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
4615                         if (encoder->type != INTEL_OUTPUT_EDP)
4616                                 continue;
4617
4618                         DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
4619                                                 val ? "en" : "dis", val);
4620
4621                         intel_dp = enc_to_intel_dp(&encoder->base);
4622                         if (val)
4623                                 intel_edp_drrs_enable(intel_dp,
4624                                                         intel_crtc->config);
4625                         else
4626                                 intel_edp_drrs_disable(intel_dp,
4627                                                         intel_crtc->config);
4628                 }
4629         }
4630         drm_modeset_unlock_all(dev);
4631
4632         return 0;
4633 }
4634
4635 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
4636
4637 static const struct drm_info_list i915_debugfs_list[] = {
4638         {"i915_capabilities", i915_capabilities, 0},
4639         {"i915_gem_objects", i915_gem_object_info, 0},
4640         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4641         {"i915_gem_stolen", i915_gem_stolen_list_info },
4642         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4643         {"i915_gem_interrupt", i915_interrupt_info, 0},
4644         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4645         {"i915_guc_info", i915_guc_info, 0},
4646         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4647         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4648         {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4649         {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4650         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4651         {"i915_frequency_info", i915_frequency_info, 0},
4652         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4653         {"i915_reset_info", i915_reset_info, 0},
4654         {"i915_drpc_info", i915_drpc_info, 0},
4655         {"i915_emon_status", i915_emon_status, 0},
4656         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4657         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4658         {"i915_fbc_status", i915_fbc_status, 0},
4659         {"i915_ips_status", i915_ips_status, 0},
4660         {"i915_sr_status", i915_sr_status, 0},
4661         {"i915_opregion", i915_opregion, 0},
4662         {"i915_vbt", i915_vbt, 0},
4663         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4664         {"i915_context_status", i915_context_status, 0},
4665         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4666         {"i915_swizzle_info", i915_swizzle_info, 0},
4667         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4668         {"i915_llc", i915_llc, 0},
4669         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4670         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4671         {"i915_energy_uJ", i915_energy_uJ, 0},
4672         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4673         {"i915_power_domain_info", i915_power_domain_info, 0},
4674         {"i915_dmc_info", i915_dmc_info, 0},
4675         {"i915_display_info", i915_display_info, 0},
4676         {"i915_engine_info", i915_engine_info, 0},
4677         {"i915_shrinker_info", i915_shrinker_info, 0},
4678         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4679         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4680         {"i915_wa_registers", i915_wa_registers, 0},
4681         {"i915_ddb_info", i915_ddb_info, 0},
4682         {"i915_sseu_status", i915_sseu_status, 0},
4683         {"i915_drrs_status", i915_drrs_status, 0},
4684         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4685 };
4686 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4687
4688 static const struct i915_debugfs_files {
4689         const char *name;
4690         const struct file_operations *fops;
4691 } i915_debugfs_files[] = {
4692         {"i915_wedged", &i915_wedged_fops},
4693         {"i915_max_freq", &i915_max_freq_fops},
4694         {"i915_min_freq", &i915_min_freq_fops},
4695         {"i915_cache_sharing", &i915_cache_sharing_fops},
4696         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4697         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4698         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4699 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4700         {"i915_error_state", &i915_error_state_fops},
4701         {"i915_gpu_info", &i915_gpu_info_fops},
4702 #endif
4703         {"i915_next_seqno", &i915_next_seqno_fops},
4704         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4705         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4706         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4707         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4708         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4709         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4710         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4711         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4712         {"i915_guc_log_control", &i915_guc_log_control_fops},
4713         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4714         {"i915_ipc_status", &i915_ipc_status_fops},
4715         {"i915_drrs_ctl", &i915_drrs_ctl_fops}
4716 };
4717
4718 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4719 {
4720         struct drm_minor *minor = dev_priv->drm.primary;
4721         struct dentry *ent;
4722         int ret, i;
4723
4724         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4725                                   minor->debugfs_root, to_i915(minor->dev),
4726                                   &i915_forcewake_fops);
4727         if (!ent)
4728                 return -ENOMEM;
4729
4730         ret = intel_pipe_crc_create(minor);
4731         if (ret)
4732                 return ret;
4733
4734         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4735                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4736                                           S_IRUGO | S_IWUSR,
4737                                           minor->debugfs_root,
4738                                           to_i915(minor->dev),
4739                                           i915_debugfs_files[i].fops);
4740                 if (!ent)
4741                         return -ENOMEM;
4742         }
4743
4744         return drm_debugfs_create_files(i915_debugfs_list,
4745                                         I915_DEBUGFS_ENTRIES,
4746                                         minor->debugfs_root, minor);
4747 }
4748
4749 struct dpcd_block {
4750         /* DPCD dump start address. */
4751         unsigned int offset;
4752         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4753         unsigned int end;
4754         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4755         size_t size;
4756         /* Only valid for eDP. */
4757         bool edp;
4758 };
4759
4760 static const struct dpcd_block i915_dpcd_debug[] = {
4761         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4762         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4763         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4764         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4765         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4766         { .offset = DP_SET_POWER },
4767         { .offset = DP_EDP_DPCD_REV },
4768         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4769         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4770         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4771 };
4772
4773 static int i915_dpcd_show(struct seq_file *m, void *data)
4774 {
4775         struct drm_connector *connector = m->private;
4776         struct intel_dp *intel_dp =
4777                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4778         uint8_t buf[16];
4779         ssize_t err;
4780         int i;
4781
4782         if (connector->status != connector_status_connected)
4783                 return -ENODEV;
4784
4785         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4786                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4787                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4788
4789                 if (b->edp &&
4790                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4791                         continue;
4792
4793                 /* low tech for now */
4794                 if (WARN_ON(size > sizeof(buf)))
4795                         continue;
4796
4797                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4798                 if (err <= 0) {
4799                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4800                                   size, b->offset, err);
4801                         continue;
4802                 }
4803
4804                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4805         }
4806
4807         return 0;
4808 }
4809
4810 static int i915_dpcd_open(struct inode *inode, struct file *file)
4811 {
4812         return single_open(file, i915_dpcd_show, inode->i_private);
4813 }
4814
4815 static const struct file_operations i915_dpcd_fops = {
4816         .owner = THIS_MODULE,
4817         .open = i915_dpcd_open,
4818         .read = seq_read,
4819         .llseek = seq_lseek,
4820         .release = single_release,
4821 };
4822
4823 static int i915_panel_show(struct seq_file *m, void *data)
4824 {
4825         struct drm_connector *connector = m->private;
4826         struct intel_dp *intel_dp =
4827                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4828
4829         if (connector->status != connector_status_connected)
4830                 return -ENODEV;
4831
4832         seq_printf(m, "Panel power up delay: %d\n",
4833                    intel_dp->panel_power_up_delay);
4834         seq_printf(m, "Panel power down delay: %d\n",
4835                    intel_dp->panel_power_down_delay);
4836         seq_printf(m, "Backlight on delay: %d\n",
4837                    intel_dp->backlight_on_delay);
4838         seq_printf(m, "Backlight off delay: %d\n",
4839                    intel_dp->backlight_off_delay);
4840
4841         return 0;
4842 }
4843
4844 static int i915_panel_open(struct inode *inode, struct file *file)
4845 {
4846         return single_open(file, i915_panel_show, inode->i_private);
4847 }
4848
4849 static const struct file_operations i915_panel_fops = {
4850         .owner = THIS_MODULE,
4851         .open = i915_panel_open,
4852         .read = seq_read,
4853         .llseek = seq_lseek,
4854         .release = single_release,
4855 };
4856
4857 /**
4858  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4859  * @connector: pointer to a registered drm_connector
4860  *
4861  * Cleanup will be done by drm_connector_unregister() through a call to
4862  * drm_debugfs_connector_remove().
4863  *
4864  * Returns 0 on success, negative error codes on error.
4865  */
4866 int i915_debugfs_connector_add(struct drm_connector *connector)
4867 {
4868         struct dentry *root = connector->debugfs_entry;
4869
4870         /* The connector must have been registered beforehands. */
4871         if (!root)
4872                 return -ENODEV;
4873
4874         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4875             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4876                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4877                                     connector, &i915_dpcd_fops);
4878
4879         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4880                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4881                                     connector, &i915_panel_fops);
4882
4883         return 0;
4884 }