2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor *minor,
56 struct drm_info_node *node;
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 node->info_ent = (void *) key;
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
75 static int i915_capabilities(struct seq_file *m, void *data)
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
102 switch (obj->tiling_mode) {
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
118 struct i915_vma *vma;
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
134 struct i915_vma *vma;
138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 obj->active ? "*" : " ",
142 get_tiling_flag(obj),
143 get_global_flag(obj),
144 obj->base.size / 1024,
145 obj->base.read_domains,
146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 seq_printf(m, " (name: %d)", obj->base.name);
158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
159 if (vma->pin_count > 0)
162 seq_printf(m, " (pinned x %d)", pin_count);
163 if (obj->pin_display)
164 seq_printf(m, " (display)");
165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
180 if (obj->pin_display)
182 if (obj->fault_mappable)
185 seq_printf(m, " (%s mappable)", s);
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_ring(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
217 /* FIXME: the user of this interface might want more than just GGTT */
220 seq_puts(m, "Active:\n");
221 head = &vm->active_list;
224 seq_puts(m, "Inactive:\n");
225 head = &vm->inactive_list;
228 mutex_unlock(&dev->struct_mutex);
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, mm_list) {
235 describe_obj(m, vma->obj);
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
241 mutex_unlock(&dev->struct_mutex);
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
256 if (a->stolen->start < b->stolen->start)
258 if (a->stolen->start > b->stolen->start)
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
282 list_add(&obj->obj_exec_link, &stolen);
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
292 list_add(&obj->obj_exec_link, &stolen);
294 total_obj_size += obj->base.size;
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 describe_obj(m, obj);
304 list_del_init(&obj->obj_exec_link);
306 mutex_unlock(&dev->struct_mutex);
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
325 struct drm_i915_file_private *file_priv;
329 u64 active, inactive;
332 static int per_file_stats(int id, void *ptr, void *data)
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
339 stats->total += obj->base.size;
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
348 if (!drm_mm_node_allocated(&vma->node))
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
363 stats->inactive += obj->base.size;
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
371 stats->active += obj->base.size;
373 stats->inactive += obj->base.size;
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
384 #define print_file_stats(m, name, stats) do { \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *ring;
405 memset(&stats, 0, sizeof(stats));
407 for_each_ring(ring, dev_priv, i) {
408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
412 per_file_stats(0, obj, &stats);
416 print_file_stats(m, "[k]batch pool", stats);
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
430 static int i915_gem_object_info(struct seq_file *m, void* data)
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 u32 count, mappable_count, purgeable_count;
436 u64 size, mappable_size, purgeable_size;
437 struct drm_i915_gem_object *obj;
438 struct i915_address_space *vm = &dev_priv->gtt.base;
439 struct drm_file *file;
440 struct i915_vma *vma;
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&vm->active_list, mm_list);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&vm->inactive_list, mm_list);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 dev_priv->gtt.base.total,
498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
501 print_batch_pool_stats(m, dev_priv);
502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
504 struct task_struct *task;
506 memset(&stats, 0, sizeof(stats));
507 stats.file_priv = file->driver_priv;
508 spin_lock(&file->table_lock);
509 idr_for_each(&file->object_idr, per_file_stats, &stats);
510 spin_unlock(&file->table_lock);
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
518 task = pid_task(file->pid, PIDTYPE_PID);
519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
523 mutex_unlock(&dev->struct_mutex);
528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
530 struct drm_info_node *node = m->private;
531 struct drm_device *dev = node->minor->dev;
532 uintptr_t list = (uintptr_t) node->info_ent->data;
533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
535 u64 total_obj_size, total_gtt_size;
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
542 total_obj_size = total_gtt_size = count = 0;
543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
548 describe_obj(m, obj);
550 total_obj_size += obj->base.size;
551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
555 mutex_unlock(&dev->struct_mutex);
557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count, total_obj_size, total_gtt_size);
563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
565 struct drm_info_node *node = m->private;
566 struct drm_device *dev = node->minor->dev;
567 struct drm_i915_private *dev_priv = dev->dev_private;
568 struct intel_crtc *crtc;
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
575 for_each_intel_crtc(dev, crtc) {
576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
578 struct intel_unpin_work *work;
580 spin_lock_irq(&dev->event_lock);
581 work = crtc->unpin_work;
583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
601 i915_gem_request_get_seqno(work->flip_queued_req),
602 dev_priv->next_seqno,
603 ring->get_seqno(ring, true),
604 i915_gem_request_completed(work->flip_queued_req, true));
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
610 drm_crtc_vblank_count(&crtc->base));
611 if (work->enable_stall_check)
612 seq_puts(m, "Stall check enabled, ");
614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
623 if (work->pending_flip_obj) {
624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
628 spin_unlock_irq(&dev->event_lock);
631 mutex_unlock(&dev->struct_mutex);
636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
642 struct intel_engine_cs *ring;
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 for_each_ring(ring, dev_priv, i) {
651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
666 describe_obj(m, obj);
674 seq_printf(m, "total: %d\n", total);
676 mutex_unlock(&dev->struct_mutex);
681 static int i915_gem_request_info(struct seq_file *m, void *data)
683 struct drm_info_node *node = m->private;
684 struct drm_device *dev = node->minor->dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 struct intel_engine_cs *ring;
687 struct drm_i915_gem_request *req;
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
695 for_each_ring(ring, dev_priv, i) {
699 list_for_each_entry(req, &ring->request_list, list)
704 seq_printf(m, "%s requests: %d\n", ring->name, count);
705 list_for_each_entry(req, &ring->request_list, list) {
706 struct task_struct *task;
711 task = pid_task(req->pid, PIDTYPE_PID);
712 seq_printf(m, " %x @ %d: %s [%d]\n",
714 (int) (jiffies - req->emitted_jiffies),
715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
722 mutex_unlock(&dev->struct_mutex);
725 seq_puts(m, "No requests\n");
730 static void i915_ring_seqno_info(struct seq_file *m,
731 struct intel_engine_cs *ring)
733 if (ring->get_seqno) {
734 seq_printf(m, "Current sequence (%s): %x\n",
735 ring->name, ring->get_seqno(ring, false));
739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_engine_cs *ring;
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
750 intel_runtime_pm_get(dev_priv);
752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
755 intel_runtime_pm_put(dev_priv);
756 mutex_unlock(&dev->struct_mutex);
762 static int i915_interrupt_info(struct seq_file *m, void *data)
764 struct drm_info_node *node = m->private;
765 struct drm_device *dev = node->minor->dev;
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_engine_cs *ring;
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
773 intel_runtime_pm_get(dev_priv);
775 if (IS_CHERRYVIEW(dev)) {
776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
779 seq_printf(m, "Display IER:\t%08x\n",
781 seq_printf(m, "Display IIR:\t%08x\n",
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
787 for_each_pipe(dev_priv, pipe)
788 seq_printf(m, "Pipe %c stat:\t%08x\n",
790 I915_READ(PIPESTAT(pipe)));
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
827 for_each_pipe(dev_priv, pipe) {
828 if (!intel_display_power_is_enabled(dev_priv,
829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
840 seq_printf(m, "Pipe %c IER:\t%08x\n",
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
866 seq_printf(m, "Display IER:\t%08x\n",
868 seq_printf(m, "Display IIR:\t%08x\n",
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
874 for_each_pipe(dev_priv, pipe)
875 seq_printf(m, "Pipe %c stat:\t%08x\n",
877 I915_READ(PIPESTAT(pipe)));
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
882 seq_printf(m, "Render IER:\t%08x\n",
884 seq_printf(m, "Render IIR:\t%08x\n",
886 seq_printf(m, "Render IMR:\t%08x\n",
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
903 } else if (!HAS_PCH_SPLIT(dev)) {
904 seq_printf(m, "Interrupt enable: %08x\n",
906 seq_printf(m, "Interrupt identity: %08x\n",
908 seq_printf(m, "Interrupt mask: %08x\n",
910 for_each_pipe(dev_priv, pipe)
911 seq_printf(m, "Pipe %c stat: %08x\n",
913 I915_READ(PIPESTAT(pipe)));
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
934 for_each_ring(ring, dev_priv, i) {
935 if (INTEL_INFO(dev)->gen >= 6) {
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
940 i915_ring_seqno_info(m, ring);
942 intel_runtime_pm_put(dev_priv);
943 mutex_unlock(&dev->struct_mutex);
948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
950 struct drm_info_node *node = m->private;
951 struct drm_device *dev = node->minor->dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
960 for (i = 0; i < dev_priv->num_fence_regs; i++) {
961 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
963 seq_printf(m, "Fence %d, pin count = %d, object = ",
964 i, dev_priv->fence_regs[i].pin_count);
966 seq_puts(m, "unused");
968 describe_obj(m, obj);
972 mutex_unlock(&dev->struct_mutex);
976 static int i915_hws_info(struct seq_file *m, void *data)
978 struct drm_info_node *node = m->private;
979 struct drm_device *dev = node->minor->dev;
980 struct drm_i915_private *dev_priv = dev->dev_private;
981 struct intel_engine_cs *ring;
985 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
986 hws = ring->status_page.page_addr;
990 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
991 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
993 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
999 i915_error_state_write(struct file *filp,
1000 const char __user *ubuf,
1004 struct i915_error_state_file_priv *error_priv = filp->private_data;
1005 struct drm_device *dev = error_priv->dev;
1008 DRM_DEBUG_DRIVER("Resetting error state\n");
1010 ret = mutex_lock_interruptible(&dev->struct_mutex);
1014 i915_destroy_error_state(dev);
1015 mutex_unlock(&dev->struct_mutex);
1020 static int i915_error_state_open(struct inode *inode, struct file *file)
1022 struct drm_device *dev = inode->i_private;
1023 struct i915_error_state_file_priv *error_priv;
1025 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029 error_priv->dev = dev;
1031 i915_error_state_get(dev, error_priv);
1033 file->private_data = error_priv;
1038 static int i915_error_state_release(struct inode *inode, struct file *file)
1040 struct i915_error_state_file_priv *error_priv = file->private_data;
1042 i915_error_state_put(error_priv);
1048 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1049 size_t count, loff_t *pos)
1051 struct i915_error_state_file_priv *error_priv = file->private_data;
1052 struct drm_i915_error_state_buf error_str;
1054 ssize_t ret_count = 0;
1057 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061 ret = i915_error_state_to_str(&error_str, error_priv);
1065 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1072 *pos = error_str.start + ret_count;
1074 i915_error_state_buf_release(&error_str);
1075 return ret ?: ret_count;
1078 static const struct file_operations i915_error_state_fops = {
1079 .owner = THIS_MODULE,
1080 .open = i915_error_state_open,
1081 .read = i915_error_state_read,
1082 .write = i915_error_state_write,
1083 .llseek = default_llseek,
1084 .release = i915_error_state_release,
1088 i915_next_seqno_get(void *data, u64 *val)
1090 struct drm_device *dev = data;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 *val = dev_priv->next_seqno;
1099 mutex_unlock(&dev->struct_mutex);
1105 i915_next_seqno_set(void *data, u64 val)
1107 struct drm_device *dev = data;
1110 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 ret = i915_gem_set_seqno(dev, val);
1115 mutex_unlock(&dev->struct_mutex);
1120 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1121 i915_next_seqno_get, i915_next_seqno_set,
1124 static int i915_frequency_info(struct seq_file *m, void *unused)
1126 struct drm_info_node *node = m->private;
1127 struct drm_device *dev = node->minor->dev;
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1131 intel_runtime_pm_get(dev_priv);
1133 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136 u16 rgvswctl = I915_READ16(MEMSWCTL);
1137 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1139 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1140 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1141 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1143 seq_printf(m, "Current P-state: %d\n",
1144 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1145 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1146 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1147 u32 rp_state_limits;
1150 u32 rpmodectl, rpinclimit, rpdeclimit;
1151 u32 rpstat, cagf, reqf;
1152 u32 rpupei, rpcurup, rpprevup;
1153 u32 rpdownei, rpcurdown, rpprevdown;
1154 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1157 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1158 if (IS_BROXTON(dev)) {
1159 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1160 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1162 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1163 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166 /* RPSTAT1 is in the GT power well */
1167 ret = mutex_lock_interruptible(&dev->struct_mutex);
1171 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1173 reqf = I915_READ(GEN6_RPNSWREQ);
1177 reqf &= ~GEN6_TURBO_DISABLE;
1178 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1183 reqf = intel_gpu_freq(dev_priv, reqf);
1185 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1186 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1187 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1189 rpstat = I915_READ(GEN6_RPSTAT1);
1190 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1191 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1192 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1193 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1194 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1195 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1197 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1198 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1199 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1201 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1202 cagf = intel_gpu_freq(dev_priv, cagf);
1204 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1205 mutex_unlock(&dev->struct_mutex);
1207 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1208 pm_ier = I915_READ(GEN6_PMIER);
1209 pm_imr = I915_READ(GEN6_PMIMR);
1210 pm_isr = I915_READ(GEN6_PMISR);
1211 pm_iir = I915_READ(GEN6_PMIIR);
1212 pm_mask = I915_READ(GEN6_PMINTRMSK);
1214 pm_ier = I915_READ(GEN8_GT_IER(2));
1215 pm_imr = I915_READ(GEN8_GT_IMR(2));
1216 pm_isr = I915_READ(GEN8_GT_ISR(2));
1217 pm_iir = I915_READ(GEN8_GT_IIR(2));
1218 pm_mask = I915_READ(GEN6_PMINTRMSK);
1220 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1221 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1222 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1223 seq_printf(m, "Render p-state ratio: %d\n",
1224 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1225 seq_printf(m, "Render p-state VID: %d\n",
1226 gt_perf_status & 0xff);
1227 seq_printf(m, "Render p-state limit: %d\n",
1228 rp_state_limits & 0xff);
1229 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1230 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1231 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1232 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1233 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1234 seq_printf(m, "CAGF: %dMHz\n", cagf);
1235 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1236 GEN6_CURICONT_MASK);
1237 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1238 GEN6_CURBSYTAVG_MASK);
1239 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1240 GEN6_CURBSYTAVG_MASK);
1241 seq_printf(m, "Up threshold: %d%%\n",
1242 dev_priv->rps.up_threshold);
1244 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1246 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1247 GEN6_CURBSYTAVG_MASK);
1248 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1249 GEN6_CURBSYTAVG_MASK);
1250 seq_printf(m, "Down threshold: %d%%\n",
1251 dev_priv->rps.down_threshold);
1253 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1254 rp_state_cap >> 16) & 0xff;
1255 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1256 GEN9_FREQ_SCALER : 1);
1257 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1258 intel_gpu_freq(dev_priv, max_freq));
1260 max_freq = (rp_state_cap & 0xff00) >> 8;
1261 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1262 GEN9_FREQ_SCALER : 1);
1263 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264 intel_gpu_freq(dev_priv, max_freq));
1266 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267 rp_state_cap >> 0) & 0xff;
1268 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1269 GEN9_FREQ_SCALER : 1);
1270 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1271 intel_gpu_freq(dev_priv, max_freq));
1272 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1275 seq_printf(m, "Current freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1277 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1278 seq_printf(m, "Idle freq: %d MHz\n",
1279 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1280 seq_printf(m, "Min freq: %d MHz\n",
1281 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1282 seq_printf(m, "Max freq: %d MHz\n",
1283 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1285 "efficient (RPe) frequency: %d MHz\n",
1286 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1287 } else if (IS_VALLEYVIEW(dev)) {
1290 mutex_lock(&dev_priv->rps.hw_lock);
1291 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1292 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1293 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1295 seq_printf(m, "actual GPU freq: %d MHz\n",
1296 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1298 seq_printf(m, "current GPU freq: %d MHz\n",
1299 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1301 seq_printf(m, "max GPU freq: %d MHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1304 seq_printf(m, "min GPU freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1307 seq_printf(m, "idle GPU freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1311 "efficient (RPe) frequency: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1313 mutex_unlock(&dev_priv->rps.hw_lock);
1315 seq_puts(m, "no P-state info available\n");
1318 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1319 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1320 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323 intel_runtime_pm_put(dev_priv);
1327 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329 struct drm_info_node *node = m->private;
1330 struct drm_device *dev = node->minor->dev;
1331 struct drm_i915_private *dev_priv = dev->dev_private;
1332 struct intel_engine_cs *ring;
1333 u64 acthd[I915_NUM_RINGS];
1334 u32 seqno[I915_NUM_RINGS];
1337 if (!i915.enable_hangcheck) {
1338 seq_printf(m, "Hangcheck disabled\n");
1342 intel_runtime_pm_get(dev_priv);
1344 for_each_ring(ring, dev_priv, i) {
1345 seqno[i] = ring->get_seqno(ring, false);
1346 acthd[i] = intel_ring_get_active_head(ring);
1349 intel_runtime_pm_put(dev_priv);
1351 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1352 seq_printf(m, "Hangcheck active, fires in %dms\n",
1353 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1356 seq_printf(m, "Hangcheck inactive\n");
1358 for_each_ring(ring, dev_priv, i) {
1359 seq_printf(m, "%s:\n", ring->name);
1360 seq_printf(m, "\tseqno = %x [current %x]\n",
1361 ring->hangcheck.seqno, seqno[i]);
1362 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1363 (long long)ring->hangcheck.acthd,
1364 (long long)acthd[i]);
1365 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1366 (long long)ring->hangcheck.max_acthd);
1367 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1368 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1374 static int ironlake_drpc_info(struct seq_file *m)
1376 struct drm_info_node *node = m->private;
1377 struct drm_device *dev = node->minor->dev;
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379 u32 rgvmodectl, rstdbyctl;
1383 ret = mutex_lock_interruptible(&dev->struct_mutex);
1386 intel_runtime_pm_get(dev_priv);
1388 rgvmodectl = I915_READ(MEMMODECTL);
1389 rstdbyctl = I915_READ(RSTDBYCTL);
1390 crstandvid = I915_READ16(CRSTANDVID);
1392 intel_runtime_pm_put(dev_priv);
1393 mutex_unlock(&dev->struct_mutex);
1395 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1396 seq_printf(m, "Boost freq: %d\n",
1397 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1398 MEMMODE_BOOST_FREQ_SHIFT);
1399 seq_printf(m, "HW control enabled: %s\n",
1400 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1401 seq_printf(m, "SW control enabled: %s\n",
1402 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1403 seq_printf(m, "Gated voltage change: %s\n",
1404 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1405 seq_printf(m, "Starting frequency: P%d\n",
1406 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1407 seq_printf(m, "Max P-state: P%d\n",
1408 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1409 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1410 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1411 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1412 seq_printf(m, "Render standby enabled: %s\n",
1413 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1414 seq_puts(m, "Current RS state: ");
1415 switch (rstdbyctl & RSX_STATUS_MASK) {
1417 seq_puts(m, "on\n");
1419 case RSX_STATUS_RC1:
1420 seq_puts(m, "RC1\n");
1422 case RSX_STATUS_RC1E:
1423 seq_puts(m, "RC1E\n");
1425 case RSX_STATUS_RS1:
1426 seq_puts(m, "RS1\n");
1428 case RSX_STATUS_RS2:
1429 seq_puts(m, "RS2 (RC6)\n");
1431 case RSX_STATUS_RS3:
1432 seq_puts(m, "RC3 (RC6+)\n");
1435 seq_puts(m, "unknown\n");
1442 static int i915_forcewake_domains(struct seq_file *m, void *data)
1444 struct drm_info_node *node = m->private;
1445 struct drm_device *dev = node->minor->dev;
1446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 struct intel_uncore_forcewake_domain *fw_domain;
1450 spin_lock_irq(&dev_priv->uncore.lock);
1451 for_each_fw_domain(fw_domain, dev_priv, i) {
1452 seq_printf(m, "%s.wake_count = %u\n",
1453 intel_uncore_forcewake_domain_to_str(i),
1454 fw_domain->wake_count);
1456 spin_unlock_irq(&dev_priv->uncore.lock);
1461 static int vlv_drpc_info(struct seq_file *m)
1463 struct drm_info_node *node = m->private;
1464 struct drm_device *dev = node->minor->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 u32 rpmodectl1, rcctl1, pw_status;
1468 intel_runtime_pm_get(dev_priv);
1470 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1471 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1472 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1474 intel_runtime_pm_put(dev_priv);
1476 seq_printf(m, "Video Turbo Mode: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1478 seq_printf(m, "Turbo enabled: %s\n",
1479 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1480 seq_printf(m, "HW control enabled: %s\n",
1481 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1482 seq_printf(m, "SW control enabled: %s\n",
1483 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1484 GEN6_RP_MEDIA_SW_MODE));
1485 seq_printf(m, "RC6 Enabled: %s\n",
1486 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1487 GEN6_RC_CTL_EI_MODE(1))));
1488 seq_printf(m, "Render Power Well: %s\n",
1489 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1490 seq_printf(m, "Media Power Well: %s\n",
1491 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1493 seq_printf(m, "Render RC6 residency since boot: %u\n",
1494 I915_READ(VLV_GT_RENDER_RC6));
1495 seq_printf(m, "Media RC6 residency since boot: %u\n",
1496 I915_READ(VLV_GT_MEDIA_RC6));
1498 return i915_forcewake_domains(m, NULL);
1501 static int gen6_drpc_info(struct seq_file *m)
1503 struct drm_info_node *node = m->private;
1504 struct drm_device *dev = node->minor->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1507 unsigned forcewake_count;
1510 ret = mutex_lock_interruptible(&dev->struct_mutex);
1513 intel_runtime_pm_get(dev_priv);
1515 spin_lock_irq(&dev_priv->uncore.lock);
1516 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1517 spin_unlock_irq(&dev_priv->uncore.lock);
1519 if (forcewake_count) {
1520 seq_puts(m, "RC information inaccurate because somebody "
1521 "holds a forcewake reference \n");
1523 /* NB: we cannot use forcewake, else we read the wrong values */
1524 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1526 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1529 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1530 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1532 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1533 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1534 mutex_unlock(&dev->struct_mutex);
1535 mutex_lock(&dev_priv->rps.hw_lock);
1536 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1537 mutex_unlock(&dev_priv->rps.hw_lock);
1539 intel_runtime_pm_put(dev_priv);
1541 seq_printf(m, "Video Turbo Mode: %s\n",
1542 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1543 seq_printf(m, "HW control enabled: %s\n",
1544 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1545 seq_printf(m, "SW control enabled: %s\n",
1546 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1547 GEN6_RP_MEDIA_SW_MODE));
1548 seq_printf(m, "RC1e Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1550 seq_printf(m, "RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1552 seq_printf(m, "Deep RC6 Enabled: %s\n",
1553 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1554 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1555 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1556 seq_puts(m, "Current RC state: ");
1557 switch (gt_core_status & GEN6_RCn_MASK) {
1559 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1560 seq_puts(m, "Core Power Down\n");
1562 seq_puts(m, "on\n");
1565 seq_puts(m, "RC3\n");
1568 seq_puts(m, "RC6\n");
1571 seq_puts(m, "RC7\n");
1574 seq_puts(m, "Unknown\n");
1578 seq_printf(m, "Core Power Down: %s\n",
1579 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1581 /* Not exactly sure what this is */
1582 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1584 seq_printf(m, "RC6 residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6));
1586 seq_printf(m, "RC6+ residency since boot: %u\n",
1587 I915_READ(GEN6_GT_GFX_RC6p));
1588 seq_printf(m, "RC6++ residency since boot: %u\n",
1589 I915_READ(GEN6_GT_GFX_RC6pp));
1591 seq_printf(m, "RC6 voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1593 seq_printf(m, "RC6+ voltage: %dmV\n",
1594 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1595 seq_printf(m, "RC6++ voltage: %dmV\n",
1596 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1600 static int i915_drpc_info(struct seq_file *m, void *unused)
1602 struct drm_info_node *node = m->private;
1603 struct drm_device *dev = node->minor->dev;
1605 if (IS_VALLEYVIEW(dev))
1606 return vlv_drpc_info(m);
1607 else if (INTEL_INFO(dev)->gen >= 6)
1608 return gen6_drpc_info(m);
1610 return ironlake_drpc_info(m);
1613 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1615 struct drm_info_node *node = m->private;
1616 struct drm_device *dev = node->minor->dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1619 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1620 dev_priv->fb_tracking.busy_bits);
1622 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1623 dev_priv->fb_tracking.flip_bits);
1628 static int i915_fbc_status(struct seq_file *m, void *unused)
1630 struct drm_info_node *node = m->private;
1631 struct drm_device *dev = node->minor->dev;
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1634 if (!HAS_FBC(dev)) {
1635 seq_puts(m, "FBC unsupported on this chipset\n");
1639 intel_runtime_pm_get(dev_priv);
1640 mutex_lock(&dev_priv->fbc.lock);
1642 if (intel_fbc_enabled(dev_priv))
1643 seq_puts(m, "FBC enabled\n");
1645 seq_printf(m, "FBC disabled: %s\n",
1646 dev_priv->fbc.no_fbc_reason);
1648 if (INTEL_INFO(dev_priv)->gen >= 7)
1649 seq_printf(m, "Compressing: %s\n",
1650 yesno(I915_READ(FBC_STATUS2) &
1651 FBC_COMPRESSION_MASK));
1653 mutex_unlock(&dev_priv->fbc.lock);
1654 intel_runtime_pm_put(dev_priv);
1659 static int i915_fbc_fc_get(void *data, u64 *val)
1661 struct drm_device *dev = data;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1664 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1667 *val = dev_priv->fbc.false_color;
1672 static int i915_fbc_fc_set(void *data, u64 val)
1674 struct drm_device *dev = data;
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1678 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1681 mutex_lock(&dev_priv->fbc.lock);
1683 reg = I915_READ(ILK_DPFC_CONTROL);
1684 dev_priv->fbc.false_color = val;
1686 I915_WRITE(ILK_DPFC_CONTROL, val ?
1687 (reg | FBC_CTL_FALSE_COLOR) :
1688 (reg & ~FBC_CTL_FALSE_COLOR));
1690 mutex_unlock(&dev_priv->fbc.lock);
1694 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1695 i915_fbc_fc_get, i915_fbc_fc_set,
1698 static int i915_ips_status(struct seq_file *m, void *unused)
1700 struct drm_info_node *node = m->private;
1701 struct drm_device *dev = node->minor->dev;
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1704 if (!HAS_IPS(dev)) {
1705 seq_puts(m, "not supported\n");
1709 intel_runtime_pm_get(dev_priv);
1711 seq_printf(m, "Enabled by kernel parameter: %s\n",
1712 yesno(i915.enable_ips));
1714 if (INTEL_INFO(dev)->gen >= 8) {
1715 seq_puts(m, "Currently: unknown\n");
1717 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1718 seq_puts(m, "Currently: enabled\n");
1720 seq_puts(m, "Currently: disabled\n");
1723 intel_runtime_pm_put(dev_priv);
1728 static int i915_sr_status(struct seq_file *m, void *unused)
1730 struct drm_info_node *node = m->private;
1731 struct drm_device *dev = node->minor->dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 bool sr_enabled = false;
1735 intel_runtime_pm_get(dev_priv);
1737 if (HAS_PCH_SPLIT(dev))
1738 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1739 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1740 IS_I945G(dev) || IS_I945GM(dev))
1741 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1742 else if (IS_I915GM(dev))
1743 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1744 else if (IS_PINEVIEW(dev))
1745 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1746 else if (IS_VALLEYVIEW(dev))
1747 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1749 intel_runtime_pm_put(dev_priv);
1751 seq_printf(m, "self-refresh: %s\n",
1752 sr_enabled ? "enabled" : "disabled");
1757 static int i915_emon_status(struct seq_file *m, void *unused)
1759 struct drm_info_node *node = m->private;
1760 struct drm_device *dev = node->minor->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 unsigned long temp, chipset, gfx;
1768 ret = mutex_lock_interruptible(&dev->struct_mutex);
1772 temp = i915_mch_val(dev_priv);
1773 chipset = i915_chipset_val(dev_priv);
1774 gfx = i915_gfx_val(dev_priv);
1775 mutex_unlock(&dev->struct_mutex);
1777 seq_printf(m, "GMCH temp: %ld\n", temp);
1778 seq_printf(m, "Chipset power: %ld\n", chipset);
1779 seq_printf(m, "GFX power: %ld\n", gfx);
1780 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1785 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1787 struct drm_info_node *node = m->private;
1788 struct drm_device *dev = node->minor->dev;
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1791 int gpu_freq, ia_freq;
1792 unsigned int max_gpu_freq, min_gpu_freq;
1794 if (!HAS_CORE_RING_FREQ(dev)) {
1795 seq_puts(m, "unsupported on this chipset\n");
1799 intel_runtime_pm_get(dev_priv);
1801 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1803 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1807 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1808 /* Convert GT frequency to 50 HZ units */
1810 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1812 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1814 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1815 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1818 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1820 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1822 sandybridge_pcode_read(dev_priv,
1823 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1825 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1826 intel_gpu_freq(dev_priv, (gpu_freq *
1827 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1828 GEN9_FREQ_SCALER : 1))),
1829 ((ia_freq >> 0) & 0xff) * 100,
1830 ((ia_freq >> 8) & 0xff) * 100);
1833 mutex_unlock(&dev_priv->rps.hw_lock);
1836 intel_runtime_pm_put(dev_priv);
1840 static int i915_opregion(struct seq_file *m, void *unused)
1842 struct drm_info_node *node = m->private;
1843 struct drm_device *dev = node->minor->dev;
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 struct intel_opregion *opregion = &dev_priv->opregion;
1846 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1852 ret = mutex_lock_interruptible(&dev->struct_mutex);
1856 if (opregion->header) {
1857 memcpy(data, opregion->header, OPREGION_SIZE);
1858 seq_write(m, data, OPREGION_SIZE);
1861 mutex_unlock(&dev->struct_mutex);
1868 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1870 struct drm_info_node *node = m->private;
1871 struct drm_device *dev = node->minor->dev;
1872 struct intel_framebuffer *fbdev_fb = NULL;
1873 struct drm_framebuffer *drm_fb;
1875 #ifdef CONFIG_DRM_FBDEV_EMULATION
1876 if (to_i915(dev)->fbdev) {
1877 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1879 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880 fbdev_fb->base.width,
1881 fbdev_fb->base.height,
1882 fbdev_fb->base.depth,
1883 fbdev_fb->base.bits_per_pixel,
1884 fbdev_fb->base.modifier[0],
1885 atomic_read(&fbdev_fb->base.refcount.refcount));
1886 describe_obj(m, fbdev_fb->obj);
1891 mutex_lock(&dev->mode_config.fb_lock);
1892 drm_for_each_fb(drm_fb, dev) {
1893 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1897 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901 fb->base.bits_per_pixel,
1902 fb->base.modifier[0],
1903 atomic_read(&fb->base.refcount.refcount));
1904 describe_obj(m, fb->obj);
1907 mutex_unlock(&dev->mode_config.fb_lock);
1912 static void describe_ctx_ringbuf(struct seq_file *m,
1913 struct intel_ringbuffer *ringbuf)
1915 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1916 ringbuf->space, ringbuf->head, ringbuf->tail,
1917 ringbuf->last_retired_head);
1920 static int i915_context_status(struct seq_file *m, void *unused)
1922 struct drm_info_node *node = m->private;
1923 struct drm_device *dev = node->minor->dev;
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 struct intel_engine_cs *ring;
1926 struct intel_context *ctx;
1929 ret = mutex_lock_interruptible(&dev->struct_mutex);
1933 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1934 if (!i915.enable_execlists &&
1935 ctx->legacy_hw_ctx.rcs_state == NULL)
1938 seq_puts(m, "HW context ");
1939 describe_ctx(m, ctx);
1940 for_each_ring(ring, dev_priv, i) {
1941 if (ring->default_context == ctx)
1942 seq_printf(m, "(default context %s) ",
1946 if (i915.enable_execlists) {
1948 for_each_ring(ring, dev_priv, i) {
1949 struct drm_i915_gem_object *ctx_obj =
1950 ctx->engine[i].state;
1951 struct intel_ringbuffer *ringbuf =
1952 ctx->engine[i].ringbuf;
1954 seq_printf(m, "%s: ", ring->name);
1956 describe_obj(m, ctx_obj);
1958 describe_ctx_ringbuf(m, ringbuf);
1962 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1968 mutex_unlock(&dev->struct_mutex);
1973 static void i915_dump_lrc_obj(struct seq_file *m,
1974 struct intel_engine_cs *ring,
1975 struct drm_i915_gem_object *ctx_obj)
1978 uint32_t *reg_state;
1980 unsigned long ggtt_offset = 0;
1982 if (ctx_obj == NULL) {
1983 seq_printf(m, "Context on %s with no gem object\n",
1988 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1989 intel_execlists_ctx_id(ctx_obj));
1991 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1992 seq_puts(m, "\tNot bound in GGTT\n");
1994 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1996 if (i915_gem_object_get_pages(ctx_obj)) {
1997 seq_puts(m, "\tFailed to get pages for context object\n");
2001 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2002 if (!WARN_ON(page == NULL)) {
2003 reg_state = kmap_atomic(page);
2005 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2006 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2007 ggtt_offset + 4096 + (j * 4),
2008 reg_state[j], reg_state[j + 1],
2009 reg_state[j + 2], reg_state[j + 3]);
2011 kunmap_atomic(reg_state);
2017 static int i915_dump_lrc(struct seq_file *m, void *unused)
2019 struct drm_info_node *node = (struct drm_info_node *) m->private;
2020 struct drm_device *dev = node->minor->dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 struct intel_engine_cs *ring;
2023 struct intel_context *ctx;
2026 if (!i915.enable_execlists) {
2027 seq_printf(m, "Logical Ring Contexts are disabled\n");
2031 ret = mutex_lock_interruptible(&dev->struct_mutex);
2035 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2036 for_each_ring(ring, dev_priv, i) {
2037 if (ring->default_context != ctx)
2038 i915_dump_lrc_obj(m, ring,
2039 ctx->engine[i].state);
2043 mutex_unlock(&dev->struct_mutex);
2048 static int i915_execlists(struct seq_file *m, void *data)
2050 struct drm_info_node *node = (struct drm_info_node *)m->private;
2051 struct drm_device *dev = node->minor->dev;
2052 struct drm_i915_private *dev_priv = dev->dev_private;
2053 struct intel_engine_cs *ring;
2059 struct list_head *cursor;
2063 if (!i915.enable_execlists) {
2064 seq_puts(m, "Logical Ring Contexts are disabled\n");
2068 ret = mutex_lock_interruptible(&dev->struct_mutex);
2072 intel_runtime_pm_get(dev_priv);
2074 for_each_ring(ring, dev_priv, ring_id) {
2075 struct drm_i915_gem_request *head_req = NULL;
2077 unsigned long flags;
2079 seq_printf(m, "%s\n", ring->name);
2081 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2082 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2083 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2086 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2087 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2089 read_pointer = ring->next_context_status_buffer;
2090 write_pointer = status_pointer & 0x07;
2091 if (read_pointer > write_pointer)
2093 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2094 read_pointer, write_pointer);
2096 for (i = 0; i < 6; i++) {
2097 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2098 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2100 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2104 spin_lock_irqsave(&ring->execlist_lock, flags);
2105 list_for_each(cursor, &ring->execlist_queue)
2107 head_req = list_first_entry_or_null(&ring->execlist_queue,
2108 struct drm_i915_gem_request, execlist_link);
2109 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2111 seq_printf(m, "\t%d requests in queue\n", count);
2113 struct drm_i915_gem_object *ctx_obj;
2115 ctx_obj = head_req->ctx->engine[ring_id].state;
2116 seq_printf(m, "\tHead request id: %u\n",
2117 intel_execlists_ctx_id(ctx_obj));
2118 seq_printf(m, "\tHead request tail: %u\n",
2125 intel_runtime_pm_put(dev_priv);
2126 mutex_unlock(&dev->struct_mutex);
2131 static const char *swizzle_string(unsigned swizzle)
2134 case I915_BIT_6_SWIZZLE_NONE:
2136 case I915_BIT_6_SWIZZLE_9:
2138 case I915_BIT_6_SWIZZLE_9_10:
2139 return "bit9/bit10";
2140 case I915_BIT_6_SWIZZLE_9_11:
2141 return "bit9/bit11";
2142 case I915_BIT_6_SWIZZLE_9_10_11:
2143 return "bit9/bit10/bit11";
2144 case I915_BIT_6_SWIZZLE_9_17:
2145 return "bit9/bit17";
2146 case I915_BIT_6_SWIZZLE_9_10_17:
2147 return "bit9/bit10/bit17";
2148 case I915_BIT_6_SWIZZLE_UNKNOWN:
2155 static int i915_swizzle_info(struct seq_file *m, void *data)
2157 struct drm_info_node *node = m->private;
2158 struct drm_device *dev = node->minor->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2162 ret = mutex_lock_interruptible(&dev->struct_mutex);
2165 intel_runtime_pm_get(dev_priv);
2167 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2168 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2169 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2170 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2172 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2173 seq_printf(m, "DDC = 0x%08x\n",
2175 seq_printf(m, "DDC2 = 0x%08x\n",
2177 seq_printf(m, "C0DRB3 = 0x%04x\n",
2178 I915_READ16(C0DRB3));
2179 seq_printf(m, "C1DRB3 = 0x%04x\n",
2180 I915_READ16(C1DRB3));
2181 } else if (INTEL_INFO(dev)->gen >= 6) {
2182 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2183 I915_READ(MAD_DIMM_C0));
2184 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2185 I915_READ(MAD_DIMM_C1));
2186 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2187 I915_READ(MAD_DIMM_C2));
2188 seq_printf(m, "TILECTL = 0x%08x\n",
2189 I915_READ(TILECTL));
2190 if (INTEL_INFO(dev)->gen >= 8)
2191 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2192 I915_READ(GAMTARBMODE));
2194 seq_printf(m, "ARB_MODE = 0x%08x\n",
2195 I915_READ(ARB_MODE));
2196 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2197 I915_READ(DISP_ARB_CTL));
2200 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2201 seq_puts(m, "L-shaped memory detected\n");
2203 intel_runtime_pm_put(dev_priv);
2204 mutex_unlock(&dev->struct_mutex);
2209 static int per_file_ctx(int id, void *ptr, void *data)
2211 struct intel_context *ctx = ptr;
2212 struct seq_file *m = data;
2213 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2216 seq_printf(m, " no ppgtt for context %d\n",
2221 if (i915_gem_context_is_default(ctx))
2222 seq_puts(m, " default context:\n");
2224 seq_printf(m, " context %d:\n", ctx->user_handle);
2225 ppgtt->debug_dump(ppgtt, m);
2230 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 struct intel_engine_cs *ring;
2234 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2240 for_each_ring(ring, dev_priv, unused) {
2241 seq_printf(m, "%s\n", ring->name);
2242 for (i = 0; i < 4; i++) {
2243 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2245 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2246 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2251 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 struct intel_engine_cs *ring;
2257 if (INTEL_INFO(dev)->gen == 6)
2258 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2260 for_each_ring(ring, dev_priv, i) {
2261 seq_printf(m, "%s\n", ring->name);
2262 if (INTEL_INFO(dev)->gen == 7)
2263 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2264 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2265 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2266 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2268 if (dev_priv->mm.aliasing_ppgtt) {
2269 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2271 seq_puts(m, "aliasing PPGTT:\n");
2272 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2274 ppgtt->debug_dump(ppgtt, m);
2277 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2280 static int i915_ppgtt_info(struct seq_file *m, void *data)
2282 struct drm_info_node *node = m->private;
2283 struct drm_device *dev = node->minor->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct drm_file *file;
2287 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2290 intel_runtime_pm_get(dev_priv);
2292 if (INTEL_INFO(dev)->gen >= 8)
2293 gen8_ppgtt_info(m, dev);
2294 else if (INTEL_INFO(dev)->gen >= 6)
2295 gen6_ppgtt_info(m, dev);
2297 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2298 struct drm_i915_file_private *file_priv = file->driver_priv;
2299 struct task_struct *task;
2301 task = get_pid_task(file->pid, PIDTYPE_PID);
2306 seq_printf(m, "\nproc: %s\n", task->comm);
2307 put_task_struct(task);
2308 idr_for_each(&file_priv->context_idr, per_file_ctx,
2309 (void *)(unsigned long)m);
2313 intel_runtime_pm_put(dev_priv);
2314 mutex_unlock(&dev->struct_mutex);
2319 static int count_irq_waiters(struct drm_i915_private *i915)
2321 struct intel_engine_cs *ring;
2325 for_each_ring(ring, i915, i)
2326 count += ring->irq_refcount;
2331 static int i915_rps_boost_info(struct seq_file *m, void *data)
2333 struct drm_info_node *node = m->private;
2334 struct drm_device *dev = node->minor->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_file *file;
2338 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2339 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2340 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2341 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2342 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2343 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2344 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2345 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2346 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2347 spin_lock(&dev_priv->rps.client_lock);
2348 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2349 struct drm_i915_file_private *file_priv = file->driver_priv;
2350 struct task_struct *task;
2353 task = pid_task(file->pid, PIDTYPE_PID);
2354 seq_printf(m, "%s [%d]: %d boosts%s\n",
2355 task ? task->comm : "<unknown>",
2356 task ? task->pid : -1,
2357 file_priv->rps.boosts,
2358 list_empty(&file_priv->rps.link) ? "" : ", active");
2361 seq_printf(m, "Semaphore boosts: %d%s\n",
2362 dev_priv->rps.semaphores.boosts,
2363 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2364 seq_printf(m, "MMIO flip boosts: %d%s\n",
2365 dev_priv->rps.mmioflips.boosts,
2366 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2367 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2368 spin_unlock(&dev_priv->rps.client_lock);
2373 static int i915_llc(struct seq_file *m, void *data)
2375 struct drm_info_node *node = m->private;
2376 struct drm_device *dev = node->minor->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2379 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2380 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2381 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2386 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2388 struct drm_info_node *node = m->private;
2389 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2390 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2393 if (!HAS_GUC_UCODE(dev_priv->dev))
2396 seq_printf(m, "GuC firmware status:\n");
2397 seq_printf(m, "\tpath: %s\n",
2398 guc_fw->guc_fw_path);
2399 seq_printf(m, "\tfetch: %s\n",
2400 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2401 seq_printf(m, "\tload: %s\n",
2402 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2403 seq_printf(m, "\tversion wanted: %d.%d\n",
2404 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2405 seq_printf(m, "\tversion found: %d.%d\n",
2406 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2407 seq_printf(m, "\theader: offset is %d; size = %d\n",
2408 guc_fw->header_offset, guc_fw->header_size);
2409 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2410 guc_fw->ucode_offset, guc_fw->ucode_size);
2411 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2412 guc_fw->rsa_offset, guc_fw->rsa_size);
2414 tmp = I915_READ(GUC_STATUS);
2416 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2417 seq_printf(m, "\tBootrom status = 0x%x\n",
2418 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2419 seq_printf(m, "\tuKernel status = 0x%x\n",
2420 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2421 seq_printf(m, "\tMIA Core status = 0x%x\n",
2422 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2423 seq_puts(m, "\nScratch registers:\n");
2424 for (i = 0; i < 16; i++)
2425 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2430 static void i915_guc_client_info(struct seq_file *m,
2431 struct drm_i915_private *dev_priv,
2432 struct i915_guc_client *client)
2434 struct intel_engine_cs *ring;
2438 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2439 client->priority, client->ctx_index, client->proc_desc_offset);
2440 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2441 client->doorbell_id, client->doorbell_offset, client->cookie);
2442 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2443 client->wq_size, client->wq_offset, client->wq_tail);
2445 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2446 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2447 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2449 for_each_ring(ring, dev_priv, i) {
2450 seq_printf(m, "\tSubmissions: %llu %s\n",
2451 client->submissions[i],
2453 tot += client->submissions[i];
2455 seq_printf(m, "\tTotal: %llu\n", tot);
2458 static int i915_guc_info(struct seq_file *m, void *data)
2460 struct drm_info_node *node = m->private;
2461 struct drm_device *dev = node->minor->dev;
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 struct intel_guc guc;
2464 struct i915_guc_client client = {};
2465 struct intel_engine_cs *ring;
2466 enum intel_ring_id i;
2469 if (!HAS_GUC_SCHED(dev_priv->dev))
2472 /* Take a local copy of the GuC data, so we can dump it at leisure */
2473 spin_lock(&dev_priv->guc.host2guc_lock);
2474 guc = dev_priv->guc;
2475 if (guc.execbuf_client) {
2476 spin_lock(&guc.execbuf_client->wq_lock);
2477 client = *guc.execbuf_client;
2478 spin_unlock(&guc.execbuf_client->wq_lock);
2480 spin_unlock(&dev_priv->guc.host2guc_lock);
2482 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2483 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2484 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2485 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2486 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2488 seq_printf(m, "\nGuC submissions:\n");
2489 for_each_ring(ring, dev_priv, i) {
2490 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2491 ring->name, guc.submissions[i],
2492 guc.last_seqno[i], guc.last_seqno[i]);
2493 total += guc.submissions[i];
2495 seq_printf(m, "\t%s: %llu\n", "Total", total);
2497 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2498 i915_guc_client_info(m, dev_priv, &client);
2500 /* Add more as required ... */
2505 static int i915_guc_log_dump(struct seq_file *m, void *data)
2507 struct drm_info_node *node = m->private;
2508 struct drm_device *dev = node->minor->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2517 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2518 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2520 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2521 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2522 *(log + i), *(log + i + 1),
2523 *(log + i + 2), *(log + i + 3));
2533 static int i915_edp_psr_status(struct seq_file *m, void *data)
2535 struct drm_info_node *node = m->private;
2536 struct drm_device *dev = node->minor->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2541 bool enabled = false;
2543 if (!HAS_PSR(dev)) {
2544 seq_puts(m, "PSR not supported\n");
2548 intel_runtime_pm_get(dev_priv);
2550 mutex_lock(&dev_priv->psr.lock);
2551 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2552 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2553 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2554 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2555 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2556 dev_priv->psr.busy_frontbuffer_bits);
2557 seq_printf(m, "Re-enable work scheduled: %s\n",
2558 yesno(work_busy(&dev_priv->psr.work.work)));
2561 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2563 for_each_pipe(dev_priv, pipe) {
2564 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2565 VLV_EDP_PSR_CURR_STATE_MASK;
2566 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2567 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2571 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2574 for_each_pipe(dev_priv, pipe) {
2575 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2576 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2577 seq_printf(m, " pipe %c", pipe_name(pipe));
2582 * VLV/CHV PSR has no kind of performance counter
2583 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2585 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2586 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2587 EDP_PSR_PERF_CNT_MASK;
2589 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2591 mutex_unlock(&dev_priv->psr.lock);
2593 intel_runtime_pm_put(dev_priv);
2597 static int i915_sink_crc(struct seq_file *m, void *data)
2599 struct drm_info_node *node = m->private;
2600 struct drm_device *dev = node->minor->dev;
2601 struct intel_encoder *encoder;
2602 struct intel_connector *connector;
2603 struct intel_dp *intel_dp = NULL;
2607 drm_modeset_lock_all(dev);
2608 for_each_intel_connector(dev, connector) {
2610 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2613 if (!connector->base.encoder)
2616 encoder = to_intel_encoder(connector->base.encoder);
2617 if (encoder->type != INTEL_OUTPUT_EDP)
2620 intel_dp = enc_to_intel_dp(&encoder->base);
2622 ret = intel_dp_sink_crc(intel_dp, crc);
2626 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2627 crc[0], crc[1], crc[2],
2628 crc[3], crc[4], crc[5]);
2633 drm_modeset_unlock_all(dev);
2637 static int i915_energy_uJ(struct seq_file *m, void *data)
2639 struct drm_info_node *node = m->private;
2640 struct drm_device *dev = node->minor->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2645 if (INTEL_INFO(dev)->gen < 6)
2648 intel_runtime_pm_get(dev_priv);
2650 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2651 power = (power & 0x1f00) >> 8;
2652 units = 1000000 / (1 << power); /* convert to uJ */
2653 power = I915_READ(MCH_SECP_NRG_STTS);
2656 intel_runtime_pm_put(dev_priv);
2658 seq_printf(m, "%llu", (long long unsigned)power);
2663 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2665 struct drm_info_node *node = m->private;
2666 struct drm_device *dev = node->minor->dev;
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2669 if (!HAS_RUNTIME_PM(dev)) {
2670 seq_puts(m, "not supported\n");
2674 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2675 seq_printf(m, "IRQs disabled: %s\n",
2676 yesno(!intel_irqs_enabled(dev_priv)));
2678 seq_printf(m, "Usage count: %d\n",
2679 atomic_read(&dev->dev->power.usage_count));
2681 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2687 static int i915_power_domain_info(struct seq_file *m, void *unused)
2689 struct drm_info_node *node = m->private;
2690 struct drm_device *dev = node->minor->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2695 mutex_lock(&power_domains->lock);
2697 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2698 for (i = 0; i < power_domains->power_well_count; i++) {
2699 struct i915_power_well *power_well;
2700 enum intel_display_power_domain power_domain;
2702 power_well = &power_domains->power_wells[i];
2703 seq_printf(m, "%-25s %d\n", power_well->name,
2706 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2708 if (!(BIT(power_domain) & power_well->domains))
2711 seq_printf(m, " %-23s %d\n",
2712 intel_display_power_domain_str(power_domain),
2713 power_domains->domain_use_count[power_domain]);
2717 mutex_unlock(&power_domains->lock);
2722 static int i915_dmc_info(struct seq_file *m, void *unused)
2724 struct drm_info_node *node = m->private;
2725 struct drm_device *dev = node->minor->dev;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 struct intel_csr *csr;
2729 if (!HAS_CSR(dev)) {
2730 seq_puts(m, "not supported\n");
2734 csr = &dev_priv->csr;
2736 intel_runtime_pm_get(dev_priv);
2738 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2739 seq_printf(m, "path: %s\n", csr->fw_path);
2741 if (!csr->dmc_payload)
2744 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2745 CSR_VERSION_MINOR(csr->version));
2747 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2748 seq_printf(m, "DC3 -> DC5 count: %d\n",
2749 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2750 seq_printf(m, "DC5 -> DC6 count: %d\n",
2751 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2752 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2753 seq_printf(m, "DC3 -> DC5 count: %d\n",
2754 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2758 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2759 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2760 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2762 intel_runtime_pm_put(dev_priv);
2767 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2768 struct drm_display_mode *mode)
2772 for (i = 0; i < tabs; i++)
2775 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2776 mode->base.id, mode->name,
2777 mode->vrefresh, mode->clock,
2778 mode->hdisplay, mode->hsync_start,
2779 mode->hsync_end, mode->htotal,
2780 mode->vdisplay, mode->vsync_start,
2781 mode->vsync_end, mode->vtotal,
2782 mode->type, mode->flags);
2785 static void intel_encoder_info(struct seq_file *m,
2786 struct intel_crtc *intel_crtc,
2787 struct intel_encoder *intel_encoder)
2789 struct drm_info_node *node = m->private;
2790 struct drm_device *dev = node->minor->dev;
2791 struct drm_crtc *crtc = &intel_crtc->base;
2792 struct intel_connector *intel_connector;
2793 struct drm_encoder *encoder;
2795 encoder = &intel_encoder->base;
2796 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2797 encoder->base.id, encoder->name);
2798 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2799 struct drm_connector *connector = &intel_connector->base;
2800 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2803 drm_get_connector_status_name(connector->status));
2804 if (connector->status == connector_status_connected) {
2805 struct drm_display_mode *mode = &crtc->mode;
2806 seq_printf(m, ", mode:\n");
2807 intel_seq_print_mode(m, 2, mode);
2814 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2816 struct drm_info_node *node = m->private;
2817 struct drm_device *dev = node->minor->dev;
2818 struct drm_crtc *crtc = &intel_crtc->base;
2819 struct intel_encoder *intel_encoder;
2820 struct drm_plane_state *plane_state = crtc->primary->state;
2821 struct drm_framebuffer *fb = plane_state->fb;
2824 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2825 fb->base.id, plane_state->src_x >> 16,
2826 plane_state->src_y >> 16, fb->width, fb->height);
2828 seq_puts(m, "\tprimary plane disabled\n");
2829 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2830 intel_encoder_info(m, intel_crtc, intel_encoder);
2833 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2835 struct drm_display_mode *mode = panel->fixed_mode;
2837 seq_printf(m, "\tfixed mode:\n");
2838 intel_seq_print_mode(m, 2, mode);
2841 static void intel_dp_info(struct seq_file *m,
2842 struct intel_connector *intel_connector)
2844 struct intel_encoder *intel_encoder = intel_connector->encoder;
2845 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2847 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2848 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2849 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2850 intel_panel_info(m, &intel_connector->panel);
2853 static void intel_hdmi_info(struct seq_file *m,
2854 struct intel_connector *intel_connector)
2856 struct intel_encoder *intel_encoder = intel_connector->encoder;
2857 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2859 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2862 static void intel_lvds_info(struct seq_file *m,
2863 struct intel_connector *intel_connector)
2865 intel_panel_info(m, &intel_connector->panel);
2868 static void intel_connector_info(struct seq_file *m,
2869 struct drm_connector *connector)
2871 struct intel_connector *intel_connector = to_intel_connector(connector);
2872 struct intel_encoder *intel_encoder = intel_connector->encoder;
2873 struct drm_display_mode *mode;
2875 seq_printf(m, "connector %d: type %s, status: %s\n",
2876 connector->base.id, connector->name,
2877 drm_get_connector_status_name(connector->status));
2878 if (connector->status == connector_status_connected) {
2879 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2880 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2881 connector->display_info.width_mm,
2882 connector->display_info.height_mm);
2883 seq_printf(m, "\tsubpixel order: %s\n",
2884 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2885 seq_printf(m, "\tCEA rev: %d\n",
2886 connector->display_info.cea_rev);
2888 if (intel_encoder) {
2889 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2890 intel_encoder->type == INTEL_OUTPUT_EDP)
2891 intel_dp_info(m, intel_connector);
2892 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2893 intel_hdmi_info(m, intel_connector);
2894 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2895 intel_lvds_info(m, intel_connector);
2898 seq_printf(m, "\tmodes:\n");
2899 list_for_each_entry(mode, &connector->modes, head)
2900 intel_seq_print_mode(m, 2, mode);
2903 static bool cursor_active(struct drm_device *dev, int pipe)
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2908 if (IS_845G(dev) || IS_I865G(dev))
2909 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2911 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2916 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2921 pos = I915_READ(CURPOS(pipe));
2923 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2924 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2927 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2928 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2931 return cursor_active(dev, pipe);
2934 static const char *plane_type(enum drm_plane_type type)
2937 case DRM_PLANE_TYPE_OVERLAY:
2939 case DRM_PLANE_TYPE_PRIMARY:
2941 case DRM_PLANE_TYPE_CURSOR:
2944 * Deliberately omitting default: to generate compiler warnings
2945 * when a new drm_plane_type gets added.
2952 static const char *plane_rotation(unsigned int rotation)
2954 static char buf[48];
2956 * According to doc only one DRM_ROTATE_ is allowed but this
2957 * will print them all to visualize if the values are misused
2959 snprintf(buf, sizeof(buf),
2960 "%s%s%s%s%s%s(0x%08x)",
2961 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2962 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2963 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
2964 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
2965 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
2966 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
2972 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2974 struct drm_info_node *node = m->private;
2975 struct drm_device *dev = node->minor->dev;
2976 struct intel_plane *intel_plane;
2978 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2979 struct drm_plane_state *state;
2980 struct drm_plane *plane = &intel_plane->base;
2982 if (!plane->state) {
2983 seq_puts(m, "plane->state is NULL!\n");
2987 state = plane->state;
2989 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2991 plane_type(intel_plane->base.type),
2992 state->crtc_x, state->crtc_y,
2993 state->crtc_w, state->crtc_h,
2994 (state->src_x >> 16),
2995 ((state->src_x & 0xffff) * 15625) >> 10,
2996 (state->src_y >> 16),
2997 ((state->src_y & 0xffff) * 15625) >> 10,
2998 (state->src_w >> 16),
2999 ((state->src_w & 0xffff) * 15625) >> 10,
3000 (state->src_h >> 16),
3001 ((state->src_h & 0xffff) * 15625) >> 10,
3002 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3003 plane_rotation(state->rotation));
3007 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3009 struct intel_crtc_state *pipe_config;
3010 int num_scalers = intel_crtc->num_scalers;
3013 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3015 /* Not all platformas have a scaler */
3017 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3019 pipe_config->scaler_state.scaler_users,
3020 pipe_config->scaler_state.scaler_id);
3022 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3023 struct intel_scaler *sc =
3024 &pipe_config->scaler_state.scalers[i];
3026 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3027 i, yesno(sc->in_use), sc->mode);
3031 seq_puts(m, "\tNo scalers available on this platform\n");
3035 static int i915_display_info(struct seq_file *m, void *unused)
3037 struct drm_info_node *node = m->private;
3038 struct drm_device *dev = node->minor->dev;
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 struct intel_crtc *crtc;
3041 struct drm_connector *connector;
3043 intel_runtime_pm_get(dev_priv);
3044 drm_modeset_lock_all(dev);
3045 seq_printf(m, "CRTC info\n");
3046 seq_printf(m, "---------\n");
3047 for_each_intel_crtc(dev, crtc) {
3049 struct intel_crtc_state *pipe_config;
3052 pipe_config = to_intel_crtc_state(crtc->base.state);
3054 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3055 crtc->base.base.id, pipe_name(crtc->pipe),
3056 yesno(pipe_config->base.active),
3057 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3058 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3060 if (pipe_config->base.active) {
3061 intel_crtc_info(m, crtc);
3063 active = cursor_position(dev, crtc->pipe, &x, &y);
3064 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3065 yesno(crtc->cursor_base),
3066 x, y, crtc->base.cursor->state->crtc_w,
3067 crtc->base.cursor->state->crtc_h,
3068 crtc->cursor_addr, yesno(active));
3069 intel_scaler_info(m, crtc);
3070 intel_plane_info(m, crtc);
3073 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3074 yesno(!crtc->cpu_fifo_underrun_disabled),
3075 yesno(!crtc->pch_fifo_underrun_disabled));
3078 seq_printf(m, "\n");
3079 seq_printf(m, "Connector info\n");
3080 seq_printf(m, "--------------\n");
3081 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3082 intel_connector_info(m, connector);
3084 drm_modeset_unlock_all(dev);
3085 intel_runtime_pm_put(dev_priv);
3090 static int i915_semaphore_status(struct seq_file *m, void *unused)
3092 struct drm_info_node *node = (struct drm_info_node *) m->private;
3093 struct drm_device *dev = node->minor->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095 struct intel_engine_cs *ring;
3096 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3099 if (!i915_semaphore_is_enabled(dev)) {
3100 seq_puts(m, "Semaphores are disabled\n");
3104 ret = mutex_lock_interruptible(&dev->struct_mutex);
3107 intel_runtime_pm_get(dev_priv);
3109 if (IS_BROADWELL(dev)) {
3113 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3115 seqno = (uint64_t *)kmap_atomic(page);
3116 for_each_ring(ring, dev_priv, i) {
3119 seq_printf(m, "%s\n", ring->name);
3121 seq_puts(m, " Last signal:");
3122 for (j = 0; j < num_rings; j++) {
3123 offset = i * I915_NUM_RINGS + j;
3124 seq_printf(m, "0x%08llx (0x%02llx) ",
3125 seqno[offset], offset * 8);
3129 seq_puts(m, " Last wait: ");
3130 for (j = 0; j < num_rings; j++) {
3131 offset = i + (j * I915_NUM_RINGS);
3132 seq_printf(m, "0x%08llx (0x%02llx) ",
3133 seqno[offset], offset * 8);
3138 kunmap_atomic(seqno);
3140 seq_puts(m, " Last signal:");
3141 for_each_ring(ring, dev_priv, i)
3142 for (j = 0; j < num_rings; j++)
3143 seq_printf(m, "0x%08x\n",
3144 I915_READ(ring->semaphore.mbox.signal[j]));
3148 seq_puts(m, "\nSync seqno:\n");
3149 for_each_ring(ring, dev_priv, i) {
3150 for (j = 0; j < num_rings; j++) {
3151 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3157 intel_runtime_pm_put(dev_priv);
3158 mutex_unlock(&dev->struct_mutex);
3162 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3164 struct drm_info_node *node = (struct drm_info_node *) m->private;
3165 struct drm_device *dev = node->minor->dev;
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3169 drm_modeset_lock_all(dev);
3170 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3171 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3173 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3174 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3175 pll->config.crtc_mask, pll->active, yesno(pll->on));
3176 seq_printf(m, " tracked hardware state:\n");
3177 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3178 seq_printf(m, " dpll_md: 0x%08x\n",
3179 pll->config.hw_state.dpll_md);
3180 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3181 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3182 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3184 drm_modeset_unlock_all(dev);
3189 static int i915_wa_registers(struct seq_file *m, void *unused)
3193 struct drm_info_node *node = (struct drm_info_node *) m->private;
3194 struct drm_device *dev = node->minor->dev;
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3197 ret = mutex_lock_interruptible(&dev->struct_mutex);
3201 intel_runtime_pm_get(dev_priv);
3203 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3204 for (i = 0; i < dev_priv->workarounds.count; ++i) {
3206 u32 mask, value, read;
3209 addr = dev_priv->workarounds.reg[i].addr;
3210 mask = dev_priv->workarounds.reg[i].mask;
3211 value = dev_priv->workarounds.reg[i].value;
3212 read = I915_READ(addr);
3213 ok = (value & mask) == (read & mask);
3214 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3215 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3218 intel_runtime_pm_put(dev_priv);
3219 mutex_unlock(&dev->struct_mutex);
3224 static int i915_ddb_info(struct seq_file *m, void *unused)
3226 struct drm_info_node *node = m->private;
3227 struct drm_device *dev = node->minor->dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 struct skl_ddb_allocation *ddb;
3230 struct skl_ddb_entry *entry;
3234 if (INTEL_INFO(dev)->gen < 9)
3237 drm_modeset_lock_all(dev);
3239 ddb = &dev_priv->wm.skl_hw.ddb;
3241 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3243 for_each_pipe(dev_priv, pipe) {
3244 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3246 for_each_plane(dev_priv, pipe, plane) {
3247 entry = &ddb->plane[pipe][plane];
3248 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3249 entry->start, entry->end,
3250 skl_ddb_entry_size(entry));
3253 entry = &ddb->plane[pipe][PLANE_CURSOR];
3254 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3255 entry->end, skl_ddb_entry_size(entry));
3258 drm_modeset_unlock_all(dev);
3263 static void drrs_status_per_crtc(struct seq_file *m,
3264 struct drm_device *dev, struct intel_crtc *intel_crtc)
3266 struct intel_encoder *intel_encoder;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct i915_drrs *drrs = &dev_priv->drrs;
3271 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3272 /* Encoder connected on this CRTC */
3273 switch (intel_encoder->type) {
3274 case INTEL_OUTPUT_EDP:
3275 seq_puts(m, "eDP:\n");
3277 case INTEL_OUTPUT_DSI:
3278 seq_puts(m, "DSI:\n");
3280 case INTEL_OUTPUT_HDMI:
3281 seq_puts(m, "HDMI:\n");
3283 case INTEL_OUTPUT_DISPLAYPORT:
3284 seq_puts(m, "DP:\n");
3287 seq_printf(m, "Other encoder (id=%d).\n",
3288 intel_encoder->type);
3293 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3294 seq_puts(m, "\tVBT: DRRS_type: Static");
3295 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3296 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3297 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3298 seq_puts(m, "\tVBT: DRRS_type: None");
3300 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3302 seq_puts(m, "\n\n");
3304 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3305 struct intel_panel *panel;
3307 mutex_lock(&drrs->mutex);
3308 /* DRRS Supported */
3309 seq_puts(m, "\tDRRS Supported: Yes\n");
3311 /* disable_drrs() will make drrs->dp NULL */
3313 seq_puts(m, "Idleness DRRS: Disabled");
3314 mutex_unlock(&drrs->mutex);
3318 panel = &drrs->dp->attached_connector->panel;
3319 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3320 drrs->busy_frontbuffer_bits);
3322 seq_puts(m, "\n\t\t");
3323 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3324 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3325 vrefresh = panel->fixed_mode->vrefresh;
3326 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3327 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3328 vrefresh = panel->downclock_mode->vrefresh;
3330 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3331 drrs->refresh_rate_type);
3332 mutex_unlock(&drrs->mutex);
3335 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3337 seq_puts(m, "\n\t\t");
3338 mutex_unlock(&drrs->mutex);
3340 /* DRRS not supported. Print the VBT parameter*/
3341 seq_puts(m, "\tDRRS Supported : No");
3346 static int i915_drrs_status(struct seq_file *m, void *unused)
3348 struct drm_info_node *node = m->private;
3349 struct drm_device *dev = node->minor->dev;
3350 struct intel_crtc *intel_crtc;
3351 int active_crtc_cnt = 0;
3353 for_each_intel_crtc(dev, intel_crtc) {
3354 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3356 if (intel_crtc->base.state->active) {
3358 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3360 drrs_status_per_crtc(m, dev, intel_crtc);
3363 drm_modeset_unlock(&intel_crtc->base.mutex);
3366 if (!active_crtc_cnt)
3367 seq_puts(m, "No active crtc found\n");
3372 struct pipe_crc_info {
3374 struct drm_device *dev;
3378 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3380 struct drm_info_node *node = (struct drm_info_node *) m->private;
3381 struct drm_device *dev = node->minor->dev;
3382 struct drm_encoder *encoder;
3383 struct intel_encoder *intel_encoder;
3384 struct intel_digital_port *intel_dig_port;
3385 drm_modeset_lock_all(dev);
3386 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3387 intel_encoder = to_intel_encoder(encoder);
3388 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3390 intel_dig_port = enc_to_dig_port(encoder);
3391 if (!intel_dig_port->dp.can_mst)
3394 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3396 drm_modeset_unlock_all(dev);
3400 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3402 struct pipe_crc_info *info = inode->i_private;
3403 struct drm_i915_private *dev_priv = info->dev->dev_private;
3404 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3406 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3409 spin_lock_irq(&pipe_crc->lock);
3411 if (pipe_crc->opened) {
3412 spin_unlock_irq(&pipe_crc->lock);
3413 return -EBUSY; /* already open */
3416 pipe_crc->opened = true;
3417 filep->private_data = inode->i_private;
3419 spin_unlock_irq(&pipe_crc->lock);
3424 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3426 struct pipe_crc_info *info = inode->i_private;
3427 struct drm_i915_private *dev_priv = info->dev->dev_private;
3428 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3430 spin_lock_irq(&pipe_crc->lock);
3431 pipe_crc->opened = false;
3432 spin_unlock_irq(&pipe_crc->lock);
3437 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3438 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3439 /* account for \'0' */
3440 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3442 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3444 assert_spin_locked(&pipe_crc->lock);
3445 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3446 INTEL_PIPE_CRC_ENTRIES_NR);
3450 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3453 struct pipe_crc_info *info = filep->private_data;
3454 struct drm_device *dev = info->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3457 char buf[PIPE_CRC_BUFFER_LEN];
3462 * Don't allow user space to provide buffers not big enough to hold
3465 if (count < PIPE_CRC_LINE_LEN)
3468 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3471 /* nothing to read */
3472 spin_lock_irq(&pipe_crc->lock);
3473 while (pipe_crc_data_count(pipe_crc) == 0) {
3476 if (filep->f_flags & O_NONBLOCK) {
3477 spin_unlock_irq(&pipe_crc->lock);
3481 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3482 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3484 spin_unlock_irq(&pipe_crc->lock);
3489 /* We now have one or more entries to read */
3490 n_entries = count / PIPE_CRC_LINE_LEN;
3493 while (n_entries > 0) {
3494 struct intel_pipe_crc_entry *entry =
3495 &pipe_crc->entries[pipe_crc->tail];
3498 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3499 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3502 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3503 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3505 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3506 "%8u %8x %8x %8x %8x %8x\n",
3507 entry->frame, entry->crc[0],
3508 entry->crc[1], entry->crc[2],
3509 entry->crc[3], entry->crc[4]);
3511 spin_unlock_irq(&pipe_crc->lock);
3513 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3514 if (ret == PIPE_CRC_LINE_LEN)
3517 user_buf += PIPE_CRC_LINE_LEN;
3520 spin_lock_irq(&pipe_crc->lock);
3523 spin_unlock_irq(&pipe_crc->lock);
3528 static const struct file_operations i915_pipe_crc_fops = {
3529 .owner = THIS_MODULE,
3530 .open = i915_pipe_crc_open,
3531 .read = i915_pipe_crc_read,
3532 .release = i915_pipe_crc_release,
3535 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3537 .name = "i915_pipe_A_crc",
3541 .name = "i915_pipe_B_crc",
3545 .name = "i915_pipe_C_crc",
3550 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3553 struct drm_device *dev = minor->dev;
3555 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3558 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3559 &i915_pipe_crc_fops);
3563 return drm_add_fake_info_node(minor, ent, info);
3566 static const char * const pipe_crc_sources[] = {
3579 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3581 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3582 return pipe_crc_sources[source];
3585 static int display_crc_ctl_show(struct seq_file *m, void *data)
3587 struct drm_device *dev = m->private;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3591 for (i = 0; i < I915_MAX_PIPES; i++)
3592 seq_printf(m, "%c %s\n", pipe_name(i),
3593 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3598 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3600 struct drm_device *dev = inode->i_private;
3602 return single_open(file, display_crc_ctl_show, dev);
3605 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3608 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3609 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3612 case INTEL_PIPE_CRC_SOURCE_PIPE:
3613 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3615 case INTEL_PIPE_CRC_SOURCE_NONE:
3625 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3626 enum intel_pipe_crc_source *source)
3628 struct intel_encoder *encoder;
3629 struct intel_crtc *crtc;
3630 struct intel_digital_port *dig_port;
3633 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3635 drm_modeset_lock_all(dev);
3636 for_each_intel_encoder(dev, encoder) {
3637 if (!encoder->base.crtc)
3640 crtc = to_intel_crtc(encoder->base.crtc);
3642 if (crtc->pipe != pipe)
3645 switch (encoder->type) {
3646 case INTEL_OUTPUT_TVOUT:
3647 *source = INTEL_PIPE_CRC_SOURCE_TV;
3649 case INTEL_OUTPUT_DISPLAYPORT:
3650 case INTEL_OUTPUT_EDP:
3651 dig_port = enc_to_dig_port(&encoder->base);
3652 switch (dig_port->port) {
3654 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3657 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3660 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3663 WARN(1, "nonexisting DP port %c\n",
3664 port_name(dig_port->port));
3672 drm_modeset_unlock_all(dev);
3677 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3679 enum intel_pipe_crc_source *source,
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 bool need_stable_symbols = false;
3685 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3686 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3692 case INTEL_PIPE_CRC_SOURCE_PIPE:
3693 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3695 case INTEL_PIPE_CRC_SOURCE_DP_B:
3696 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3697 need_stable_symbols = true;
3699 case INTEL_PIPE_CRC_SOURCE_DP_C:
3700 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3701 need_stable_symbols = true;
3703 case INTEL_PIPE_CRC_SOURCE_DP_D:
3704 if (!IS_CHERRYVIEW(dev))
3706 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3707 need_stable_symbols = true;
3709 case INTEL_PIPE_CRC_SOURCE_NONE:
3717 * When the pipe CRC tap point is after the transcoders we need
3718 * to tweak symbol-level features to produce a deterministic series of
3719 * symbols for a given frame. We need to reset those features only once
3720 * a frame (instead of every nth symbol):
3721 * - DC-balance: used to ensure a better clock recovery from the data
3723 * - DisplayPort scrambling: used for EMI reduction
3725 if (need_stable_symbols) {
3726 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3728 tmp |= DC_BALANCE_RESET_VLV;
3731 tmp |= PIPE_A_SCRAMBLE_RESET;
3734 tmp |= PIPE_B_SCRAMBLE_RESET;
3737 tmp |= PIPE_C_SCRAMBLE_RESET;
3742 I915_WRITE(PORT_DFT2_G4X, tmp);
3748 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3750 enum intel_pipe_crc_source *source,
3753 struct drm_i915_private *dev_priv = dev->dev_private;
3754 bool need_stable_symbols = false;
3756 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3757 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3763 case INTEL_PIPE_CRC_SOURCE_PIPE:
3764 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3766 case INTEL_PIPE_CRC_SOURCE_TV:
3767 if (!SUPPORTS_TV(dev))
3769 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3771 case INTEL_PIPE_CRC_SOURCE_DP_B:
3774 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3775 need_stable_symbols = true;
3777 case INTEL_PIPE_CRC_SOURCE_DP_C:
3780 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3781 need_stable_symbols = true;
3783 case INTEL_PIPE_CRC_SOURCE_DP_D:
3786 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3787 need_stable_symbols = true;
3789 case INTEL_PIPE_CRC_SOURCE_NONE:
3797 * When the pipe CRC tap point is after the transcoders we need
3798 * to tweak symbol-level features to produce a deterministic series of
3799 * symbols for a given frame. We need to reset those features only once
3800 * a frame (instead of every nth symbol):
3801 * - DC-balance: used to ensure a better clock recovery from the data
3803 * - DisplayPort scrambling: used for EMI reduction
3805 if (need_stable_symbols) {
3806 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3808 WARN_ON(!IS_G4X(dev));
3810 I915_WRITE(PORT_DFT_I9XX,
3811 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3814 tmp |= PIPE_A_SCRAMBLE_RESET;
3816 tmp |= PIPE_B_SCRAMBLE_RESET;
3818 I915_WRITE(PORT_DFT2_G4X, tmp);
3824 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3832 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3835 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3838 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3843 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3844 tmp &= ~DC_BALANCE_RESET_VLV;
3845 I915_WRITE(PORT_DFT2_G4X, tmp);
3849 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3856 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3858 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3859 I915_WRITE(PORT_DFT2_G4X, tmp);
3861 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3862 I915_WRITE(PORT_DFT_I9XX,
3863 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3867 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3870 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3871 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3874 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3875 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3877 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3878 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3880 case INTEL_PIPE_CRC_SOURCE_PIPE:
3881 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3883 case INTEL_PIPE_CRC_SOURCE_NONE:
3893 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 struct intel_crtc *crtc =
3897 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3898 struct intel_crtc_state *pipe_config;
3899 struct drm_atomic_state *state;
3902 drm_modeset_lock_all(dev);
3903 state = drm_atomic_state_alloc(dev);
3909 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3910 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3911 if (IS_ERR(pipe_config)) {
3912 ret = PTR_ERR(pipe_config);
3916 pipe_config->pch_pfit.force_thru = enable;
3917 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3918 pipe_config->pch_pfit.enabled != enable)
3919 pipe_config->base.connectors_changed = true;
3921 ret = drm_atomic_commit(state);
3923 drm_modeset_unlock_all(dev);
3924 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3926 drm_atomic_state_free(state);
3929 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3931 enum intel_pipe_crc_source *source,
3934 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3935 *source = INTEL_PIPE_CRC_SOURCE_PF;
3938 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3939 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3941 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3942 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3944 case INTEL_PIPE_CRC_SOURCE_PF:
3945 if (IS_HASWELL(dev) && pipe == PIPE_A)
3946 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3948 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3950 case INTEL_PIPE_CRC_SOURCE_NONE:
3960 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3961 enum intel_pipe_crc_source source)
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3965 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3967 u32 val = 0; /* shut up gcc */
3970 if (pipe_crc->source == source)
3973 /* forbid changing the source without going back to 'none' */
3974 if (pipe_crc->source && source)
3977 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3978 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3983 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3984 else if (INTEL_INFO(dev)->gen < 5)
3985 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3986 else if (IS_VALLEYVIEW(dev))
3987 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3988 else if (IS_GEN5(dev) || IS_GEN6(dev))
3989 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3991 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3996 /* none -> real source transition */
3998 struct intel_pipe_crc_entry *entries;
4000 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4001 pipe_name(pipe), pipe_crc_source_name(source));
4003 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4004 sizeof(pipe_crc->entries[0]),
4010 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4011 * enabled and disabled dynamically based on package C states,
4012 * user space can't make reliable use of the CRCs, so let's just
4013 * completely disable it.
4015 hsw_disable_ips(crtc);
4017 spin_lock_irq(&pipe_crc->lock);
4018 kfree(pipe_crc->entries);
4019 pipe_crc->entries = entries;
4022 spin_unlock_irq(&pipe_crc->lock);
4025 pipe_crc->source = source;
4027 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4028 POSTING_READ(PIPE_CRC_CTL(pipe));
4030 /* real source -> none transition */
4031 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4032 struct intel_pipe_crc_entry *entries;
4033 struct intel_crtc *crtc =
4034 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4036 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4039 drm_modeset_lock(&crtc->base.mutex, NULL);
4040 if (crtc->base.state->active)
4041 intel_wait_for_vblank(dev, pipe);
4042 drm_modeset_unlock(&crtc->base.mutex);
4044 spin_lock_irq(&pipe_crc->lock);
4045 entries = pipe_crc->entries;
4046 pipe_crc->entries = NULL;
4049 spin_unlock_irq(&pipe_crc->lock);
4054 g4x_undo_pipe_scramble_reset(dev, pipe);
4055 else if (IS_VALLEYVIEW(dev))
4056 vlv_undo_pipe_scramble_reset(dev, pipe);
4057 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4058 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4060 hsw_enable_ips(crtc);
4067 * Parse pipe CRC command strings:
4068 * command: wsp* object wsp+ name wsp+ source wsp*
4071 * source: (none | plane1 | plane2 | pf)
4072 * wsp: (#0x20 | #0x9 | #0xA)+
4075 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4076 * "pipe A none" -> Stop CRC
4078 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4085 /* skip leading white space */
4086 buf = skip_spaces(buf);
4088 break; /* end of buffer */
4090 /* find end of word */
4091 for (end = buf; *end && !isspace(*end); end++)
4094 if (n_words == max_words) {
4095 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4097 return -EINVAL; /* ran out of words[] before bytes */
4102 words[n_words++] = buf;
4109 enum intel_pipe_crc_object {
4110 PIPE_CRC_OBJECT_PIPE,
4113 static const char * const pipe_crc_objects[] = {
4118 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4122 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4123 if (!strcmp(buf, pipe_crc_objects[i])) {
4131 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4133 const char name = buf[0];
4135 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4144 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4148 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4149 if (!strcmp(buf, pipe_crc_sources[i])) {
4157 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4161 char *words[N_WORDS];
4163 enum intel_pipe_crc_object object;
4164 enum intel_pipe_crc_source source;
4166 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4167 if (n_words != N_WORDS) {
4168 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4173 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4174 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4178 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4179 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4183 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4184 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4188 return pipe_crc_set_source(dev, pipe, source);
4191 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4192 size_t len, loff_t *offp)
4194 struct seq_file *m = file->private_data;
4195 struct drm_device *dev = m->private;
4202 if (len > PAGE_SIZE - 1) {
4203 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4208 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4212 if (copy_from_user(tmpbuf, ubuf, len)) {
4218 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4229 static const struct file_operations i915_display_crc_ctl_fops = {
4230 .owner = THIS_MODULE,
4231 .open = display_crc_ctl_open,
4233 .llseek = seq_lseek,
4234 .release = single_release,
4235 .write = display_crc_ctl_write
4238 static ssize_t i915_displayport_test_active_write(struct file *file,
4239 const char __user *ubuf,
4240 size_t len, loff_t *offp)
4244 struct drm_device *dev;
4245 struct drm_connector *connector;
4246 struct list_head *connector_list;
4247 struct intel_dp *intel_dp;
4250 dev = ((struct seq_file *)file->private_data)->private;
4252 connector_list = &dev->mode_config.connector_list;
4257 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4261 if (copy_from_user(input_buffer, ubuf, len)) {
4266 input_buffer[len] = '\0';
4267 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4269 list_for_each_entry(connector, connector_list, head) {
4271 if (connector->connector_type !=
4272 DRM_MODE_CONNECTOR_DisplayPort)
4275 if (connector->status == connector_status_connected &&
4276 connector->encoder != NULL) {
4277 intel_dp = enc_to_intel_dp(connector->encoder);
4278 status = kstrtoint(input_buffer, 10, &val);
4281 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4282 /* To prevent erroneous activation of the compliance
4283 * testing code, only accept an actual value of 1 here
4286 intel_dp->compliance_test_active = 1;
4288 intel_dp->compliance_test_active = 0;
4292 kfree(input_buffer);
4300 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4302 struct drm_device *dev = m->private;
4303 struct drm_connector *connector;
4304 struct list_head *connector_list = &dev->mode_config.connector_list;
4305 struct intel_dp *intel_dp;
4307 list_for_each_entry(connector, connector_list, head) {
4309 if (connector->connector_type !=
4310 DRM_MODE_CONNECTOR_DisplayPort)
4313 if (connector->status == connector_status_connected &&
4314 connector->encoder != NULL) {
4315 intel_dp = enc_to_intel_dp(connector->encoder);
4316 if (intel_dp->compliance_test_active)
4327 static int i915_displayport_test_active_open(struct inode *inode,
4330 struct drm_device *dev = inode->i_private;
4332 return single_open(file, i915_displayport_test_active_show, dev);
4335 static const struct file_operations i915_displayport_test_active_fops = {
4336 .owner = THIS_MODULE,
4337 .open = i915_displayport_test_active_open,
4339 .llseek = seq_lseek,
4340 .release = single_release,
4341 .write = i915_displayport_test_active_write
4344 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4346 struct drm_device *dev = m->private;
4347 struct drm_connector *connector;
4348 struct list_head *connector_list = &dev->mode_config.connector_list;
4349 struct intel_dp *intel_dp;
4351 list_for_each_entry(connector, connector_list, head) {
4353 if (connector->connector_type !=
4354 DRM_MODE_CONNECTOR_DisplayPort)
4357 if (connector->status == connector_status_connected &&
4358 connector->encoder != NULL) {
4359 intel_dp = enc_to_intel_dp(connector->encoder);
4360 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4367 static int i915_displayport_test_data_open(struct inode *inode,
4370 struct drm_device *dev = inode->i_private;
4372 return single_open(file, i915_displayport_test_data_show, dev);
4375 static const struct file_operations i915_displayport_test_data_fops = {
4376 .owner = THIS_MODULE,
4377 .open = i915_displayport_test_data_open,
4379 .llseek = seq_lseek,
4380 .release = single_release
4383 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4385 struct drm_device *dev = m->private;
4386 struct drm_connector *connector;
4387 struct list_head *connector_list = &dev->mode_config.connector_list;
4388 struct intel_dp *intel_dp;
4390 list_for_each_entry(connector, connector_list, head) {
4392 if (connector->connector_type !=
4393 DRM_MODE_CONNECTOR_DisplayPort)
4396 if (connector->status == connector_status_connected &&
4397 connector->encoder != NULL) {
4398 intel_dp = enc_to_intel_dp(connector->encoder);
4399 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4407 static int i915_displayport_test_type_open(struct inode *inode,
4410 struct drm_device *dev = inode->i_private;
4412 return single_open(file, i915_displayport_test_type_show, dev);
4415 static const struct file_operations i915_displayport_test_type_fops = {
4416 .owner = THIS_MODULE,
4417 .open = i915_displayport_test_type_open,
4419 .llseek = seq_lseek,
4420 .release = single_release
4423 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4425 struct drm_device *dev = m->private;
4429 if (IS_CHERRYVIEW(dev))
4431 else if (IS_VALLEYVIEW(dev))
4434 num_levels = ilk_wm_max_level(dev) + 1;
4436 drm_modeset_lock_all(dev);
4438 for (level = 0; level < num_levels; level++) {
4439 unsigned int latency = wm[level];
4442 * - WM1+ latency values in 0.5us units
4443 * - latencies are in us on gen9/vlv/chv
4445 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4450 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4451 level, wm[level], latency / 10, latency % 10);
4454 drm_modeset_unlock_all(dev);
4457 static int pri_wm_latency_show(struct seq_file *m, void *data)
4459 struct drm_device *dev = m->private;
4460 struct drm_i915_private *dev_priv = dev->dev_private;
4461 const uint16_t *latencies;
4463 if (INTEL_INFO(dev)->gen >= 9)
4464 latencies = dev_priv->wm.skl_latency;
4466 latencies = to_i915(dev)->wm.pri_latency;
4468 wm_latency_show(m, latencies);
4473 static int spr_wm_latency_show(struct seq_file *m, void *data)
4475 struct drm_device *dev = m->private;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 const uint16_t *latencies;
4479 if (INTEL_INFO(dev)->gen >= 9)
4480 latencies = dev_priv->wm.skl_latency;
4482 latencies = to_i915(dev)->wm.spr_latency;
4484 wm_latency_show(m, latencies);
4489 static int cur_wm_latency_show(struct seq_file *m, void *data)
4491 struct drm_device *dev = m->private;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493 const uint16_t *latencies;
4495 if (INTEL_INFO(dev)->gen >= 9)
4496 latencies = dev_priv->wm.skl_latency;
4498 latencies = to_i915(dev)->wm.cur_latency;
4500 wm_latency_show(m, latencies);
4505 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4507 struct drm_device *dev = inode->i_private;
4509 if (INTEL_INFO(dev)->gen < 5)
4512 return single_open(file, pri_wm_latency_show, dev);
4515 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4517 struct drm_device *dev = inode->i_private;
4519 if (HAS_GMCH_DISPLAY(dev))
4522 return single_open(file, spr_wm_latency_show, dev);
4525 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4527 struct drm_device *dev = inode->i_private;
4529 if (HAS_GMCH_DISPLAY(dev))
4532 return single_open(file, cur_wm_latency_show, dev);
4535 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4536 size_t len, loff_t *offp, uint16_t wm[8])
4538 struct seq_file *m = file->private_data;
4539 struct drm_device *dev = m->private;
4540 uint16_t new[8] = { 0 };
4546 if (IS_CHERRYVIEW(dev))
4548 else if (IS_VALLEYVIEW(dev))
4551 num_levels = ilk_wm_max_level(dev) + 1;
4553 if (len >= sizeof(tmp))
4556 if (copy_from_user(tmp, ubuf, len))
4561 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4562 &new[0], &new[1], &new[2], &new[3],
4563 &new[4], &new[5], &new[6], &new[7]);
4564 if (ret != num_levels)
4567 drm_modeset_lock_all(dev);
4569 for (level = 0; level < num_levels; level++)
4570 wm[level] = new[level];
4572 drm_modeset_unlock_all(dev);
4578 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4579 size_t len, loff_t *offp)
4581 struct seq_file *m = file->private_data;
4582 struct drm_device *dev = m->private;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 uint16_t *latencies;
4586 if (INTEL_INFO(dev)->gen >= 9)
4587 latencies = dev_priv->wm.skl_latency;
4589 latencies = to_i915(dev)->wm.pri_latency;
4591 return wm_latency_write(file, ubuf, len, offp, latencies);
4594 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4595 size_t len, loff_t *offp)
4597 struct seq_file *m = file->private_data;
4598 struct drm_device *dev = m->private;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600 uint16_t *latencies;
4602 if (INTEL_INFO(dev)->gen >= 9)
4603 latencies = dev_priv->wm.skl_latency;
4605 latencies = to_i915(dev)->wm.spr_latency;
4607 return wm_latency_write(file, ubuf, len, offp, latencies);
4610 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4611 size_t len, loff_t *offp)
4613 struct seq_file *m = file->private_data;
4614 struct drm_device *dev = m->private;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 uint16_t *latencies;
4618 if (INTEL_INFO(dev)->gen >= 9)
4619 latencies = dev_priv->wm.skl_latency;
4621 latencies = to_i915(dev)->wm.cur_latency;
4623 return wm_latency_write(file, ubuf, len, offp, latencies);
4626 static const struct file_operations i915_pri_wm_latency_fops = {
4627 .owner = THIS_MODULE,
4628 .open = pri_wm_latency_open,
4630 .llseek = seq_lseek,
4631 .release = single_release,
4632 .write = pri_wm_latency_write
4635 static const struct file_operations i915_spr_wm_latency_fops = {
4636 .owner = THIS_MODULE,
4637 .open = spr_wm_latency_open,
4639 .llseek = seq_lseek,
4640 .release = single_release,
4641 .write = spr_wm_latency_write
4644 static const struct file_operations i915_cur_wm_latency_fops = {
4645 .owner = THIS_MODULE,
4646 .open = cur_wm_latency_open,
4648 .llseek = seq_lseek,
4649 .release = single_release,
4650 .write = cur_wm_latency_write
4654 i915_wedged_get(void *data, u64 *val)
4656 struct drm_device *dev = data;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4659 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4665 i915_wedged_set(void *data, u64 val)
4667 struct drm_device *dev = data;
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4671 * There is no safeguard against this debugfs entry colliding
4672 * with the hangcheck calling same i915_handle_error() in
4673 * parallel, causing an explosion. For now we assume that the
4674 * test harness is responsible enough not to inject gpu hangs
4675 * while it is writing to 'i915_wedged'
4678 if (i915_reset_in_progress(&dev_priv->gpu_error))
4681 intel_runtime_pm_get(dev_priv);
4683 i915_handle_error(dev, val,
4684 "Manually setting wedged to %llu", val);
4686 intel_runtime_pm_put(dev_priv);
4691 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4692 i915_wedged_get, i915_wedged_set,
4696 i915_ring_stop_get(void *data, u64 *val)
4698 struct drm_device *dev = data;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4701 *val = dev_priv->gpu_error.stop_rings;
4707 i915_ring_stop_set(void *data, u64 val)
4709 struct drm_device *dev = data;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4713 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4715 ret = mutex_lock_interruptible(&dev->struct_mutex);
4719 dev_priv->gpu_error.stop_rings = val;
4720 mutex_unlock(&dev->struct_mutex);
4725 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4726 i915_ring_stop_get, i915_ring_stop_set,
4730 i915_ring_missed_irq_get(void *data, u64 *val)
4732 struct drm_device *dev = data;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4735 *val = dev_priv->gpu_error.missed_irq_rings;
4740 i915_ring_missed_irq_set(void *data, u64 val)
4742 struct drm_device *dev = data;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4746 /* Lock against concurrent debugfs callers */
4747 ret = mutex_lock_interruptible(&dev->struct_mutex);
4750 dev_priv->gpu_error.missed_irq_rings = val;
4751 mutex_unlock(&dev->struct_mutex);
4756 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4757 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4761 i915_ring_test_irq_get(void *data, u64 *val)
4763 struct drm_device *dev = data;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4766 *val = dev_priv->gpu_error.test_irq_rings;
4772 i915_ring_test_irq_set(void *data, u64 val)
4774 struct drm_device *dev = data;
4775 struct drm_i915_private *dev_priv = dev->dev_private;
4778 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4780 /* Lock against concurrent debugfs callers */
4781 ret = mutex_lock_interruptible(&dev->struct_mutex);
4785 dev_priv->gpu_error.test_irq_rings = val;
4786 mutex_unlock(&dev->struct_mutex);
4791 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4792 i915_ring_test_irq_get, i915_ring_test_irq_set,
4795 #define DROP_UNBOUND 0x1
4796 #define DROP_BOUND 0x2
4797 #define DROP_RETIRE 0x4
4798 #define DROP_ACTIVE 0x8
4799 #define DROP_ALL (DROP_UNBOUND | \
4804 i915_drop_caches_get(void *data, u64 *val)
4812 i915_drop_caches_set(void *data, u64 val)
4814 struct drm_device *dev = data;
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4818 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4820 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4821 * on ioctls on -EAGAIN. */
4822 ret = mutex_lock_interruptible(&dev->struct_mutex);
4826 if (val & DROP_ACTIVE) {
4827 ret = i915_gpu_idle(dev);
4832 if (val & (DROP_RETIRE | DROP_ACTIVE))
4833 i915_gem_retire_requests(dev);
4835 if (val & DROP_BOUND)
4836 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4838 if (val & DROP_UNBOUND)
4839 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4842 mutex_unlock(&dev->struct_mutex);
4847 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4848 i915_drop_caches_get, i915_drop_caches_set,
4852 i915_max_freq_get(void *data, u64 *val)
4854 struct drm_device *dev = data;
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4858 if (INTEL_INFO(dev)->gen < 6)
4861 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4863 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4867 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4868 mutex_unlock(&dev_priv->rps.hw_lock);
4874 i915_max_freq_set(void *data, u64 val)
4876 struct drm_device *dev = data;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4881 if (INTEL_INFO(dev)->gen < 6)
4884 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4886 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4888 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4893 * Turbo will still be enabled, but won't go above the set value.
4895 val = intel_freq_opcode(dev_priv, val);
4897 hw_max = dev_priv->rps.max_freq;
4898 hw_min = dev_priv->rps.min_freq;
4900 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4901 mutex_unlock(&dev_priv->rps.hw_lock);
4905 dev_priv->rps.max_freq_softlimit = val;
4907 intel_set_rps(dev, val);
4909 mutex_unlock(&dev_priv->rps.hw_lock);
4914 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4915 i915_max_freq_get, i915_max_freq_set,
4919 i915_min_freq_get(void *data, u64 *val)
4921 struct drm_device *dev = data;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4925 if (INTEL_INFO(dev)->gen < 6)
4928 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4930 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4934 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4935 mutex_unlock(&dev_priv->rps.hw_lock);
4941 i915_min_freq_set(void *data, u64 val)
4943 struct drm_device *dev = data;
4944 struct drm_i915_private *dev_priv = dev->dev_private;
4948 if (INTEL_INFO(dev)->gen < 6)
4951 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4953 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4955 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4960 * Turbo will still be enabled, but won't go below the set value.
4962 val = intel_freq_opcode(dev_priv, val);
4964 hw_max = dev_priv->rps.max_freq;
4965 hw_min = dev_priv->rps.min_freq;
4967 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4968 mutex_unlock(&dev_priv->rps.hw_lock);
4972 dev_priv->rps.min_freq_softlimit = val;
4974 intel_set_rps(dev, val);
4976 mutex_unlock(&dev_priv->rps.hw_lock);
4981 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4982 i915_min_freq_get, i915_min_freq_set,
4986 i915_cache_sharing_get(void *data, u64 *val)
4988 struct drm_device *dev = data;
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4993 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4996 ret = mutex_lock_interruptible(&dev->struct_mutex);
4999 intel_runtime_pm_get(dev_priv);
5001 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5003 intel_runtime_pm_put(dev_priv);
5004 mutex_unlock(&dev_priv->dev->struct_mutex);
5006 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5012 i915_cache_sharing_set(void *data, u64 val)
5014 struct drm_device *dev = data;
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5018 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5024 intel_runtime_pm_get(dev_priv);
5025 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5027 /* Update the cache sharing policy here as well */
5028 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5029 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5030 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5031 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5033 intel_runtime_pm_put(dev_priv);
5037 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5038 i915_cache_sharing_get, i915_cache_sharing_set,
5041 struct sseu_dev_status {
5042 unsigned int slice_total;
5043 unsigned int subslice_total;
5044 unsigned int subslice_per_slice;
5045 unsigned int eu_total;
5046 unsigned int eu_per_subslice;
5049 static void cherryview_sseu_device_status(struct drm_device *dev,
5050 struct sseu_dev_status *stat)
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5055 u32 sig1[ss_max], sig2[ss_max];
5057 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5058 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5059 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5060 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5062 for (ss = 0; ss < ss_max; ss++) {
5063 unsigned int eu_cnt;
5065 if (sig1[ss] & CHV_SS_PG_ENABLE)
5066 /* skip disabled subslice */
5069 stat->slice_total = 1;
5070 stat->subslice_per_slice++;
5071 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5072 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5073 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5074 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5075 stat->eu_total += eu_cnt;
5076 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5078 stat->subslice_total = stat->subslice_per_slice;
5081 static void gen9_sseu_device_status(struct drm_device *dev,
5082 struct sseu_dev_status *stat)
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 int s_max = 3, ss_max = 4;
5087 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5089 /* BXT has a single slice and at most 3 subslices. */
5090 if (IS_BROXTON(dev)) {
5095 for (s = 0; s < s_max; s++) {
5096 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5097 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5098 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5101 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5102 GEN9_PGCTL_SSA_EU19_ACK |
5103 GEN9_PGCTL_SSA_EU210_ACK |
5104 GEN9_PGCTL_SSA_EU311_ACK;
5105 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5106 GEN9_PGCTL_SSB_EU19_ACK |
5107 GEN9_PGCTL_SSB_EU210_ACK |
5108 GEN9_PGCTL_SSB_EU311_ACK;
5110 for (s = 0; s < s_max; s++) {
5111 unsigned int ss_cnt = 0;
5113 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5114 /* skip disabled slice */
5117 stat->slice_total++;
5119 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5120 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5122 for (ss = 0; ss < ss_max; ss++) {
5123 unsigned int eu_cnt;
5125 if (IS_BROXTON(dev) &&
5126 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5127 /* skip disabled subslice */
5130 if (IS_BROXTON(dev))
5133 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5135 stat->eu_total += eu_cnt;
5136 stat->eu_per_subslice = max(stat->eu_per_subslice,
5140 stat->subslice_total += ss_cnt;
5141 stat->subslice_per_slice = max(stat->subslice_per_slice,
5146 static void broadwell_sseu_device_status(struct drm_device *dev,
5147 struct sseu_dev_status *stat)
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5151 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5153 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5155 if (stat->slice_total) {
5156 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5157 stat->subslice_total = stat->slice_total *
5158 stat->subslice_per_slice;
5159 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5160 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5162 /* subtract fused off EU(s) from enabled slice(s) */
5163 for (s = 0; s < stat->slice_total; s++) {
5164 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5166 stat->eu_total -= hweight8(subslice_7eu);
5171 static int i915_sseu_status(struct seq_file *m, void *unused)
5173 struct drm_info_node *node = (struct drm_info_node *) m->private;
5174 struct drm_device *dev = node->minor->dev;
5175 struct sseu_dev_status stat;
5177 if (INTEL_INFO(dev)->gen < 8)
5180 seq_puts(m, "SSEU Device Info\n");
5181 seq_printf(m, " Available Slice Total: %u\n",
5182 INTEL_INFO(dev)->slice_total);
5183 seq_printf(m, " Available Subslice Total: %u\n",
5184 INTEL_INFO(dev)->subslice_total);
5185 seq_printf(m, " Available Subslice Per Slice: %u\n",
5186 INTEL_INFO(dev)->subslice_per_slice);
5187 seq_printf(m, " Available EU Total: %u\n",
5188 INTEL_INFO(dev)->eu_total);
5189 seq_printf(m, " Available EU Per Subslice: %u\n",
5190 INTEL_INFO(dev)->eu_per_subslice);
5191 seq_printf(m, " Has Slice Power Gating: %s\n",
5192 yesno(INTEL_INFO(dev)->has_slice_pg));
5193 seq_printf(m, " Has Subslice Power Gating: %s\n",
5194 yesno(INTEL_INFO(dev)->has_subslice_pg));
5195 seq_printf(m, " Has EU Power Gating: %s\n",
5196 yesno(INTEL_INFO(dev)->has_eu_pg));
5198 seq_puts(m, "SSEU Device Status\n");
5199 memset(&stat, 0, sizeof(stat));
5200 if (IS_CHERRYVIEW(dev)) {
5201 cherryview_sseu_device_status(dev, &stat);
5202 } else if (IS_BROADWELL(dev)) {
5203 broadwell_sseu_device_status(dev, &stat);
5204 } else if (INTEL_INFO(dev)->gen >= 9) {
5205 gen9_sseu_device_status(dev, &stat);
5207 seq_printf(m, " Enabled Slice Total: %u\n",
5209 seq_printf(m, " Enabled Subslice Total: %u\n",
5210 stat.subslice_total);
5211 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5212 stat.subslice_per_slice);
5213 seq_printf(m, " Enabled EU Total: %u\n",
5215 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5216 stat.eu_per_subslice);
5221 static int i915_forcewake_open(struct inode *inode, struct file *file)
5223 struct drm_device *dev = inode->i_private;
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5226 if (INTEL_INFO(dev)->gen < 6)
5229 intel_runtime_pm_get(dev_priv);
5230 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5235 static int i915_forcewake_release(struct inode *inode, struct file *file)
5237 struct drm_device *dev = inode->i_private;
5238 struct drm_i915_private *dev_priv = dev->dev_private;
5240 if (INTEL_INFO(dev)->gen < 6)
5243 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5244 intel_runtime_pm_put(dev_priv);
5249 static const struct file_operations i915_forcewake_fops = {
5250 .owner = THIS_MODULE,
5251 .open = i915_forcewake_open,
5252 .release = i915_forcewake_release,
5255 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5257 struct drm_device *dev = minor->dev;
5260 ent = debugfs_create_file("i915_forcewake_user",
5263 &i915_forcewake_fops);
5267 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5270 static int i915_debugfs_create(struct dentry *root,
5271 struct drm_minor *minor,
5273 const struct file_operations *fops)
5275 struct drm_device *dev = minor->dev;
5278 ent = debugfs_create_file(name,
5285 return drm_add_fake_info_node(minor, ent, fops);
5288 static const struct drm_info_list i915_debugfs_list[] = {
5289 {"i915_capabilities", i915_capabilities, 0},
5290 {"i915_gem_objects", i915_gem_object_info, 0},
5291 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5292 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5293 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5294 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5295 {"i915_gem_stolen", i915_gem_stolen_list_info },
5296 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5297 {"i915_gem_request", i915_gem_request_info, 0},
5298 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5299 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5300 {"i915_gem_interrupt", i915_interrupt_info, 0},
5301 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5302 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5303 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5304 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5305 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5306 {"i915_guc_info", i915_guc_info, 0},
5307 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5308 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5309 {"i915_frequency_info", i915_frequency_info, 0},
5310 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5311 {"i915_drpc_info", i915_drpc_info, 0},
5312 {"i915_emon_status", i915_emon_status, 0},
5313 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5314 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5315 {"i915_fbc_status", i915_fbc_status, 0},
5316 {"i915_ips_status", i915_ips_status, 0},
5317 {"i915_sr_status", i915_sr_status, 0},
5318 {"i915_opregion", i915_opregion, 0},
5319 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5320 {"i915_context_status", i915_context_status, 0},
5321 {"i915_dump_lrc", i915_dump_lrc, 0},
5322 {"i915_execlists", i915_execlists, 0},
5323 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5324 {"i915_swizzle_info", i915_swizzle_info, 0},
5325 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5326 {"i915_llc", i915_llc, 0},
5327 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5328 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5329 {"i915_energy_uJ", i915_energy_uJ, 0},
5330 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5331 {"i915_power_domain_info", i915_power_domain_info, 0},
5332 {"i915_dmc_info", i915_dmc_info, 0},
5333 {"i915_display_info", i915_display_info, 0},
5334 {"i915_semaphore_status", i915_semaphore_status, 0},
5335 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5336 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5337 {"i915_wa_registers", i915_wa_registers, 0},
5338 {"i915_ddb_info", i915_ddb_info, 0},
5339 {"i915_sseu_status", i915_sseu_status, 0},
5340 {"i915_drrs_status", i915_drrs_status, 0},
5341 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5343 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5345 static const struct i915_debugfs_files {
5347 const struct file_operations *fops;
5348 } i915_debugfs_files[] = {
5349 {"i915_wedged", &i915_wedged_fops},
5350 {"i915_max_freq", &i915_max_freq_fops},
5351 {"i915_min_freq", &i915_min_freq_fops},
5352 {"i915_cache_sharing", &i915_cache_sharing_fops},
5353 {"i915_ring_stop", &i915_ring_stop_fops},
5354 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5355 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5356 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5357 {"i915_error_state", &i915_error_state_fops},
5358 {"i915_next_seqno", &i915_next_seqno_fops},
5359 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5360 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5361 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5362 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5363 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5364 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5365 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5366 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5369 void intel_display_crc_init(struct drm_device *dev)
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5374 for_each_pipe(dev_priv, pipe) {
5375 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5377 pipe_crc->opened = false;
5378 spin_lock_init(&pipe_crc->lock);
5379 init_waitqueue_head(&pipe_crc->wq);
5383 int i915_debugfs_init(struct drm_minor *minor)
5387 ret = i915_forcewake_create(minor->debugfs_root, minor);
5391 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5392 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5397 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5398 ret = i915_debugfs_create(minor->debugfs_root, minor,
5399 i915_debugfs_files[i].name,
5400 i915_debugfs_files[i].fops);
5405 return drm_debugfs_create_files(i915_debugfs_list,
5406 I915_DEBUGFS_ENTRIES,
5407 minor->debugfs_root, minor);
5410 void i915_debugfs_cleanup(struct drm_minor *minor)
5414 drm_debugfs_remove_files(i915_debugfs_list,
5415 I915_DEBUGFS_ENTRIES, minor);
5417 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5420 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5421 struct drm_info_list *info_list =
5422 (struct drm_info_list *)&i915_pipe_crc_data[i];
5424 drm_debugfs_remove_files(info_list, 1, minor);
5427 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5428 struct drm_info_list *info_list =
5429 (struct drm_info_list *) i915_debugfs_files[i].fops;
5431 drm_debugfs_remove_files(info_list, 1, minor);
5436 /* DPCD dump start address. */
5437 unsigned int offset;
5438 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5440 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5442 /* Only valid for eDP. */
5446 static const struct dpcd_block i915_dpcd_debug[] = {
5447 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5448 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5449 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5450 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5451 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5452 { .offset = DP_SET_POWER },
5453 { .offset = DP_EDP_DPCD_REV },
5454 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5455 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5456 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5459 static int i915_dpcd_show(struct seq_file *m, void *data)
5461 struct drm_connector *connector = m->private;
5462 struct intel_dp *intel_dp =
5463 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5468 if (connector->status != connector_status_connected)
5471 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5472 const struct dpcd_block *b = &i915_dpcd_debug[i];
5473 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5476 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5479 /* low tech for now */
5480 if (WARN_ON(size > sizeof(buf)))
5483 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5485 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5486 size, b->offset, err);
5490 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5496 static int i915_dpcd_open(struct inode *inode, struct file *file)
5498 return single_open(file, i915_dpcd_show, inode->i_private);
5501 static const struct file_operations i915_dpcd_fops = {
5502 .owner = THIS_MODULE,
5503 .open = i915_dpcd_open,
5505 .llseek = seq_lseek,
5506 .release = single_release,
5510 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5511 * @connector: pointer to a registered drm_connector
5513 * Cleanup will be done by drm_connector_unregister() through a call to
5514 * drm_debugfs_connector_remove().
5516 * Returns 0 on success, negative error codes on error.
5518 int i915_debugfs_connector_add(struct drm_connector *connector)
5520 struct dentry *root = connector->debugfs_entry;
5522 /* The connector must have been registered beforehands. */
5526 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5527 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5528 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,