drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include <linux/sched/mm.h>
  32 #include "intel_drv.h"
  33 #include "intel_guc_submission.h"
  34
  35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  36 {
  37         return to_i915(node->minor->dev);
  38 }
  39
  40 static int i915_capabilities(struct seq_file *m, void *data)
  41 {
  42         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  43         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  44         struct drm_printer p = drm_seq_file_printer(m);
  45
  46         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  47         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  48         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  49
  50         intel_device_info_dump_flags(info, &p);
  51         intel_device_info_dump_runtime(info, &p);
  52         intel_driver_caps_print(&dev_priv->caps, &p);
  53
  54         kernel_param_lock(THIS_MODULE);
  55         i915_params_dump(&i915_modparams, &p);
  56         kernel_param_unlock(THIS_MODULE);
  57
  58         return 0;
  59 }
  60
  61 static char get_active_flag(struct drm_i915_gem_object *obj)
  62 {
  63         return i915_gem_object_is_active(obj) ? '*' : ' ';
  64 }
  65
  66 static char get_pin_flag(struct drm_i915_gem_object *obj)
  67 {
  68         return obj->pin_global ? 'p' : ' ';
  69 }
  70
  71 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  72 {
  73         switch (i915_gem_object_get_tiling(obj)) {
  74         default:
  75         case I915_TILING_NONE: return ' ';
  76         case I915_TILING_X: return 'X';
  77         case I915_TILING_Y: return 'Y';
  78         }
  79 }
  80
  81 static char get_global_flag(struct drm_i915_gem_object *obj)
  82 {
  83         return obj->userfault_count ? 'g' : ' ';
  84 }
  85
  86 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
  87 {
  88         return obj->mm.mapping ? 'M' : ' ';
  89 }
  90
  91 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
  92 {
  93         u64 size = 0;
  94         struct i915_vma *vma;
  95
  96         for_each_ggtt_vma(vma, obj) {
  97                 if (drm_mm_node_allocated(&vma->node))
  98                         size += vma->node.size;
  99         }
 100
 101         return size;
 102 }
 103
 104 static const char *
 105 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
 106 {
 107         size_t x = 0;
 108
 109         switch (page_sizes) {
 110         case 0:
 111                 return "";
 112         case I915_GTT_PAGE_SIZE_4K:
 113                 return "4K";
 114         case I915_GTT_PAGE_SIZE_64K:
 115                 return "64K";
 116         case I915_GTT_PAGE_SIZE_2M:
 117                 return "2M";
 118         default:
 119                 if (!buf)
 120                         return "M";
 121
 122                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 123                         x += snprintf(buf + x, len - x, "2M, ");
 124                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 125                         x += snprintf(buf + x, len - x, "64K, ");
 126                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 127                         x += snprintf(buf + x, len - x, "4K, ");
 128                 buf[x-2] = '\0';
 129
 130                 return buf;
 131         }
 132 }
 133
 134 static void
 135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 138         struct intel_engine_cs *engine;
 139         struct i915_vma *vma;
 140         unsigned int frontbuffer_bits;
 141         int pin_count = 0;
 142
 143         lockdep_assert_held(&obj->base.dev->struct_mutex);
 144
 145         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 146                    &obj->base,
 147                    get_active_flag(obj),
 148                    get_pin_flag(obj),
 149                    get_tiling_flag(obj),
 150                    get_global_flag(obj),
 151                    get_pin_mapped_flag(obj),
 152                    obj->base.size / 1024,
 153                    obj->read_domains,
 154                    obj->write_domain,
 155                    i915_cache_level_str(dev_priv, obj->cache_level),
 156                    obj->mm.dirty ? " dirty" : "",
 157                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 158         if (obj->base.name)
 159                 seq_printf(m, " (name: %d)", obj->base.name);
 160         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 161                 if (i915_vma_is_pinned(vma))
 162                         pin_count++;
 163         }
 164         seq_printf(m, " (pinned x %d)", pin_count);
 165         if (obj->pin_global)
 166                 seq_printf(m, " (global)");
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (!drm_mm_node_allocated(&vma->node))
 169                         continue;
 170
 171                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 172                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 173                            vma->node.start, vma->node.size,
 174                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 175                 if (i915_vma_is_ggtt(vma)) {
 176                         switch (vma->ggtt_view.type) {
 177                         case I915_GGTT_VIEW_NORMAL:
 178                                 seq_puts(m, ", normal");
 179                                 break;
 180
 181                         case I915_GGTT_VIEW_PARTIAL:
 182                                 seq_printf(m, ", partial [%08llx+%x]",
 183                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 184                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 185                                 break;
 186
 187                         case I915_GGTT_VIEW_ROTATED:
 188                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 189                                            vma->ggtt_view.rotated.plane[0].width,
 190                                            vma->ggtt_view.rotated.plane[0].height,
 191                                            vma->ggtt_view.rotated.plane[0].stride,
 192                                            vma->ggtt_view.rotated.plane[0].offset,
 193                                            vma->ggtt_view.rotated.plane[1].width,
 194                                            vma->ggtt_view.rotated.plane[1].height,
 195                                            vma->ggtt_view.rotated.plane[1].stride,
 196                                            vma->ggtt_view.rotated.plane[1].offset);
 197                                 break;
 198
 199                         default:
 200                                 MISSING_CASE(vma->ggtt_view.type);
 201                                 break;
 202                         }
 203                 }
 204                 if (vma->fence)
 205                         seq_printf(m, " , fence: %d%s",
 206                                    vma->fence->id,
 207                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 208                 seq_puts(m, ")");
 209         }
 210         if (obj->stolen)
 211                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 212
 213         engine = i915_gem_object_last_write_engine(obj);
 214         if (engine)
 215                 seq_printf(m, " (%s)", engine->name);
 216
 217         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 218         if (frontbuffer_bits)
 219                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 220 }
 221
 222 static int obj_rank_by_stolen(const void *A, const void *B)
 223 {
 224         const struct drm_i915_gem_object *a =
 225                 *(const struct drm_i915_gem_object **)A;
 226         const struct drm_i915_gem_object *b =
 227                 *(const struct drm_i915_gem_object **)B;
 228
 229         if (a->stolen->start < b->stolen->start)
 230                 return -1;
 231         if (a->stolen->start > b->stolen->start)
 232                 return 1;
 233         return 0;
 234 }
 235
 236 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 237 {
 238         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 239         struct drm_device *dev = &dev_priv->drm;
 240         struct drm_i915_gem_object **objects;
 241         struct drm_i915_gem_object *obj;
 242         u64 total_obj_size, total_gtt_size;
 243         unsigned long total, count, n;
 244         int ret;
 245
 246         total = READ_ONCE(dev_priv->mm.object_count);
 247         objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
 248         if (!objects)
 249                 return -ENOMEM;
 250
 251         ret = mutex_lock_interruptible(&dev->struct_mutex);
 252         if (ret)
 253                 goto out;
 254
 255         total_obj_size = total_gtt_size = count = 0;
 256
 257         spin_lock(&dev_priv->mm.obj_lock);
 258         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 259                 if (count == total)
 260                         break;
 261
 262                 if (obj->stolen == NULL)
 263                         continue;
 264
 265                 objects[count++] = obj;
 266                 total_obj_size += obj->base.size;
 267                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 268
 269         }
 270         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 271                 if (count == total)
 272                         break;
 273
 274                 if (obj->stolen == NULL)
 275                         continue;
 276
 277                 objects[count++] = obj;
 278                 total_obj_size += obj->base.size;
 279         }
 280         spin_unlock(&dev_priv->mm.obj_lock);
 281
 282         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 283
 284         seq_puts(m, "Stolen:\n");
 285         for (n = 0; n < count; n++) {
 286                 seq_puts(m, "   ");
 287                 describe_obj(m, objects[n]);
 288                 seq_putc(m, '\n');
 289         }
 290         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 291                    count, total_obj_size, total_gtt_size);
 292
 293         mutex_unlock(&dev->struct_mutex);
 294 out:
 295         kvfree(objects);
 296         return ret;
 297 }
 298
 299 struct file_stats {
 300         struct drm_i915_file_private *file_priv;
 301         unsigned long count;
 302         u64 total, unbound;
 303         u64 global, shared;
 304         u64 active, inactive;
 305 };
 306
 307 static int per_file_stats(int id, void *ptr, void *data)
 308 {
 309         struct drm_i915_gem_object *obj = ptr;
 310         struct file_stats *stats = data;
 311         struct i915_vma *vma;
 312
 313         lockdep_assert_held(&obj->base.dev->struct_mutex);
 314
 315         stats->count++;
 316         stats->total += obj->base.size;
 317         if (!obj->bind_count)
 318                 stats->unbound += obj->base.size;
 319         if (obj->base.name || obj->base.dma_buf)
 320                 stats->shared += obj->base.size;
 321
 322         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 323                 if (!drm_mm_node_allocated(&vma->node))
 324                         continue;
 325
 326                 if (i915_vma_is_ggtt(vma)) {
 327                         stats->global += vma->node.size;
 328                 } else {
 329                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 330
 331                         if (ppgtt->base.file != stats->file_priv)
 332                                 continue;
 333                 }
 334
 335                 if (i915_vma_is_active(vma))
 336                         stats->active += vma->node.size;
 337                 else
 338                         stats->inactive += vma->node.size;
 339         }
 340
 341         return 0;
 342 }
 343
 344 #define print_file_stats(m, name, stats) do { \
 345         if (stats.count) \
 346                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 347                            name, \
 348                            stats.count, \
 349                            stats.total, \
 350                            stats.active, \
 351                            stats.inactive, \
 352                            stats.global, \
 353                            stats.shared, \
 354                            stats.unbound); \
 355 } while (0)
 356
 357 static void print_batch_pool_stats(struct seq_file *m,
 358                                    struct drm_i915_private *dev_priv)
 359 {
 360         struct drm_i915_gem_object *obj;
 361         struct file_stats stats;
 362         struct intel_engine_cs *engine;
 363         enum intel_engine_id id;
 364         int j;
 365
 366         memset(&stats, 0, sizeof(stats));
 367
 368         for_each_engine(engine, dev_priv, id) {
 369                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 370                         list_for_each_entry(obj,
 371                                             &engine->batch_pool.cache_list[j],
 372                                             batch_pool_link)
 373                                 per_file_stats(0, obj, &stats);
 374                 }
 375         }
 376
 377         print_file_stats(m, "[k]batch pool", stats);
 378 }
 379
 380 static int per_file_ctx_stats(int id, void *ptr, void *data)
 381 {
 382         struct i915_gem_context *ctx = ptr;
 383         int n;
 384
 385         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 386                 if (ctx->engine[n].state)
 387                         per_file_stats(0, ctx->engine[n].state->obj, data);
 388                 if (ctx->engine[n].ring)
 389                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 390         }
 391
 392         return 0;
 393 }
 394
 395 static void print_context_stats(struct seq_file *m,
 396                                 struct drm_i915_private *dev_priv)
 397 {
 398         struct drm_device *dev = &dev_priv->drm;
 399         struct file_stats stats;
 400         struct drm_file *file;
 401
 402         memset(&stats, 0, sizeof(stats));
 403
 404         mutex_lock(&dev->struct_mutex);
 405         if (dev_priv->kernel_context)
 406                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 407
 408         list_for_each_entry(file, &dev->filelist, lhead) {
 409                 struct drm_i915_file_private *fpriv = file->driver_priv;
 410                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 411         }
 412         mutex_unlock(&dev->struct_mutex);
 413
 414         print_file_stats(m, "[k]contexts", stats);
 415 }
 416
 417 static int i915_gem_object_info(struct seq_file *m, void *data)
 418 {
 419         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 420         struct drm_device *dev = &dev_priv->drm;
 421         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 422         u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
 423         u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
 424         struct drm_i915_gem_object *obj;
 425         unsigned int page_sizes = 0;
 426         struct drm_file *file;
 427         char buf[80];
 428         int ret;
 429
 430         ret = mutex_lock_interruptible(&dev->struct_mutex);
 431         if (ret)
 432                 return ret;
 433
 434         seq_printf(m, "%u objects, %llu bytes\n",
 435                    dev_priv->mm.object_count,
 436                    dev_priv->mm.object_memory);
 437
 438         size = count = 0;
 439         mapped_size = mapped_count = 0;
 440         purgeable_size = purgeable_count = 0;
 441         huge_size = huge_count = 0;
 442
 443         spin_lock(&dev_priv->mm.obj_lock);
 444         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 445                 size += obj->base.size;
 446                 ++count;
 447
 448                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 449                         purgeable_size += obj->base.size;
 450                         ++purgeable_count;
 451                 }
 452
 453                 if (obj->mm.mapping) {
 454                         mapped_count++;
 455                         mapped_size += obj->base.size;
 456                 }
 457
 458                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 459                         huge_count++;
 460                         huge_size += obj->base.size;
 461                         page_sizes |= obj->mm.page_sizes.sg;
 462                 }
 463         }
 464         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 465
 466         size = count = dpy_size = dpy_count = 0;
 467         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 468                 size += obj->base.size;
 469                 ++count;
 470
 471                 if (obj->pin_global) {
 472                         dpy_size += obj->base.size;
 473                         ++dpy_count;
 474                 }
 475
 476                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 477                         purgeable_size += obj->base.size;
 478                         ++purgeable_count;
 479                 }
 480
 481                 if (obj->mm.mapping) {
 482                         mapped_count++;
 483                         mapped_size += obj->base.size;
 484                 }
 485
 486                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 487                         huge_count++;
 488                         huge_size += obj->base.size;
 489                         page_sizes |= obj->mm.page_sizes.sg;
 490                 }
 491         }
 492         spin_unlock(&dev_priv->mm.obj_lock);
 493
 494         seq_printf(m, "%u bound objects, %llu bytes\n",
 495                    count, size);
 496         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 497                    purgeable_count, purgeable_size);
 498         seq_printf(m, "%u mapped objects, %llu bytes\n",
 499                    mapped_count, mapped_size);
 500         seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
 501                    huge_count,
 502                    stringify_page_sizes(page_sizes, buf, sizeof(buf)),
 503                    huge_size);
 504         seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
 505                    dpy_count, dpy_size);
 506
 507         seq_printf(m, "%llu [%pa] gtt total\n",
 508                    ggtt->base.total, &ggtt->mappable_end);
 509         seq_printf(m, "Supported page sizes: %s\n",
 510                    stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
 511                                         buf, sizeof(buf)));
 512
 513         seq_putc(m, '\n');
 514         print_batch_pool_stats(m, dev_priv);
 515         mutex_unlock(&dev->struct_mutex);
 516
 517         mutex_lock(&dev->filelist_mutex);
 518         print_context_stats(m, dev_priv);
 519         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 520                 struct file_stats stats;
 521                 struct drm_i915_file_private *file_priv = file->driver_priv;
 522                 struct i915_request *request;
 523                 struct task_struct *task;
 524
 525                 mutex_lock(&dev->struct_mutex);
 526
 527                 memset(&stats, 0, sizeof(stats));
 528                 stats.file_priv = file->driver_priv;
 529                 spin_lock(&file->table_lock);
 530                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 531                 spin_unlock(&file->table_lock);
 532                 /*
 533                  * Although we have a valid reference on file->pid, that does
 534                  * not guarantee that the task_struct who called get_pid() is
 535                  * still alive (e.g. get_pid(current) => fork() => exit()).
 536                  * Therefore, we need to protect this ->comm access using RCU.
 537                  */
 538                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 539                                                    struct i915_request,
 540                                                    client_link);
 541                 rcu_read_lock();
 542                 task = pid_task(request && request->ctx->pid ?
 543                                 request->ctx->pid : file->pid,
 544                                 PIDTYPE_PID);
 545                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 546                 rcu_read_unlock();
 547
 548                 mutex_unlock(&dev->struct_mutex);
 549         }
 550         mutex_unlock(&dev->filelist_mutex);
 551
 552         return 0;
 553 }
 554
 555 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 556 {
 557         struct drm_info_node *node = m->private;
 558         struct drm_i915_private *dev_priv = node_to_i915(node);
 559         struct drm_device *dev = &dev_priv->drm;
 560         struct drm_i915_gem_object **objects;
 561         struct drm_i915_gem_object *obj;
 562         u64 total_obj_size, total_gtt_size;
 563         unsigned long nobject, n;
 564         int count, ret;
 565
 566         nobject = READ_ONCE(dev_priv->mm.object_count);
 567         objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
 568         if (!objects)
 569                 return -ENOMEM;
 570
 571         ret = mutex_lock_interruptible(&dev->struct_mutex);
 572         if (ret)
 573                 return ret;
 574
 575         count = 0;
 576         spin_lock(&dev_priv->mm.obj_lock);
 577         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 578                 objects[count++] = obj;
 579                 if (count == nobject)
 580                         break;
 581         }
 582         spin_unlock(&dev_priv->mm.obj_lock);
 583
 584         total_obj_size = total_gtt_size = 0;
 585         for (n = 0;  n < count; n++) {
 586                 obj = objects[n];
 587
 588                 seq_puts(m, "   ");
 589                 describe_obj(m, obj);
 590                 seq_putc(m, '\n');
 591                 total_obj_size += obj->base.size;
 592                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 593         }
 594
 595         mutex_unlock(&dev->struct_mutex);
 596
 597         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 598                    count, total_obj_size, total_gtt_size);
 599         kvfree(objects);
 600
 601         return 0;
 602 }
 603
 604 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 605 {
 606         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 607         struct drm_device *dev = &dev_priv->drm;
 608         struct drm_i915_gem_object *obj;
 609         struct intel_engine_cs *engine;
 610         enum intel_engine_id id;
 611         int total = 0;
 612         int ret, j;
 613
 614         ret = mutex_lock_interruptible(&dev->struct_mutex);
 615         if (ret)
 616                 return ret;
 617
 618         for_each_engine(engine, dev_priv, id) {
 619                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 620                         int count;
 621
 622                         count = 0;
 623                         list_for_each_entry(obj,
 624                                             &engine->batch_pool.cache_list[j],
 625                                             batch_pool_link)
 626                                 count++;
 627                         seq_printf(m, "%s cache[%d]: %d objects\n",
 628                                    engine->name, j, count);
 629
 630                         list_for_each_entry(obj,
 631                                             &engine->batch_pool.cache_list[j],
 632                                             batch_pool_link) {
 633                                 seq_puts(m, "   ");
 634                                 describe_obj(m, obj);
 635                                 seq_putc(m, '\n');
 636                         }
 637
 638                         total += count;
 639                 }
 640         }
 641
 642         seq_printf(m, "total: %d\n", total);
 643
 644         mutex_unlock(&dev->struct_mutex);
 645
 646         return 0;
 647 }
 648
 649 static void gen8_display_interrupt_info(struct seq_file *m)
 650 {
 651         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 652         int pipe;
 653
 654         for_each_pipe(dev_priv, pipe) {
 655                 enum intel_display_power_domain power_domain;
 656
 657                 power_domain = POWER_DOMAIN_PIPE(pipe);
 658                 if (!intel_display_power_get_if_enabled(dev_priv,
 659                                                         power_domain)) {
 660                         seq_printf(m, "Pipe %c power disabled\n",
 661                                    pipe_name(pipe));
 662                         continue;
 663                 }
 664                 seq_printf(m, "Pipe %c IMR:\t%08x\n",
 665                            pipe_name(pipe),
 666                            I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 667                 seq_printf(m, "Pipe %c IIR:\t%08x\n",
 668                            pipe_name(pipe),
 669                            I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 670                 seq_printf(m, "Pipe %c IER:\t%08x\n",
 671                            pipe_name(pipe),
 672                            I915_READ(GEN8_DE_PIPE_IER(pipe)));
 673
 674                 intel_display_power_put(dev_priv, power_domain);
 675         }
 676
 677         seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 678                    I915_READ(GEN8_DE_PORT_IMR));
 679         seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 680                    I915_READ(GEN8_DE_PORT_IIR));
 681         seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 682                    I915_READ(GEN8_DE_PORT_IER));
 683
 684         seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 685                    I915_READ(GEN8_DE_MISC_IMR));
 686         seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 687                    I915_READ(GEN8_DE_MISC_IIR));
 688         seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 689                    I915_READ(GEN8_DE_MISC_IER));
 690
 691         seq_printf(m, "PCU interrupt mask:\t%08x\n",
 692                    I915_READ(GEN8_PCU_IMR));
 693         seq_printf(m, "PCU interrupt identity:\t%08x\n",
 694                    I915_READ(GEN8_PCU_IIR));
 695         seq_printf(m, "PCU interrupt enable:\t%08x\n",
 696                    I915_READ(GEN8_PCU_IER));
 697 }
 698
 699 static int i915_interrupt_info(struct seq_file *m, void *data)
 700 {
 701         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 702         struct intel_engine_cs *engine;
 703         enum intel_engine_id id;
 704         int i, pipe;
 705
 706         intel_runtime_pm_get(dev_priv);
 707
 708         if (IS_CHERRYVIEW(dev_priv)) {
 709                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 710                            I915_READ(GEN8_MASTER_IRQ));
 711
 712                 seq_printf(m, "Display IER:\t%08x\n",
 713                            I915_READ(VLV_IER));
 714                 seq_printf(m, "Display IIR:\t%08x\n",
 715                            I915_READ(VLV_IIR));
 716                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 717                            I915_READ(VLV_IIR_RW));
 718                 seq_printf(m, "Display IMR:\t%08x\n",
 719                            I915_READ(VLV_IMR));
 720                 for_each_pipe(dev_priv, pipe) {
 721                         enum intel_display_power_domain power_domain;
 722
 723                         power_domain = POWER_DOMAIN_PIPE(pipe);
 724                         if (!intel_display_power_get_if_enabled(dev_priv,
 725                                                                 power_domain)) {
 726                                 seq_printf(m, "Pipe %c power disabled\n",
 727                                            pipe_name(pipe));
 728                                 continue;
 729                         }
 730
 731                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 732                                    pipe_name(pipe),
 733                                    I915_READ(PIPESTAT(pipe)));
 734
 735                         intel_display_power_put(dev_priv, power_domain);
 736                 }
 737
 738                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 739                 seq_printf(m, "Port hotplug:\t%08x\n",
 740                            I915_READ(PORT_HOTPLUG_EN));
 741                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 742                            I915_READ(VLV_DPFLIPSTAT));
 743                 seq_printf(m, "DPINVGTT:\t%08x\n",
 744                            I915_READ(DPINVGTT));
 745                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 746
 747                 for (i = 0; i < 4; i++) {
 748                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 749                                    i, I915_READ(GEN8_GT_IMR(i)));
 750                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 751                                    i, I915_READ(GEN8_GT_IIR(i)));
 752                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 753                                    i, I915_READ(GEN8_GT_IER(i)));
 754                 }
 755
 756                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 757                            I915_READ(GEN8_PCU_IMR));
 758                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 759                            I915_READ(GEN8_PCU_IIR));
 760                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 761                            I915_READ(GEN8_PCU_IER));
 762         } else if (INTEL_GEN(dev_priv) >= 11) {
 763                 seq_printf(m, "Master Interrupt Control:  %08x\n",
 764                            I915_READ(GEN11_GFX_MSTR_IRQ));
 765
 766                 seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
 767                            I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
 768                 seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
 769                            I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
 770                 seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
 771                            I915_READ(GEN11_GUC_SG_INTR_ENABLE));
 772                 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
 773                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
 774                 seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
 775                            I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
 776                 seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
 777                            I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
 778
 779                 seq_printf(m, "Display Interrupt Control:\t%08x\n",
 780                            I915_READ(GEN11_DISPLAY_INT_CTL));
 781
 782                 gen8_display_interrupt_info(m);
 783         } else if (INTEL_GEN(dev_priv) >= 8) {
 784                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 785                            I915_READ(GEN8_MASTER_IRQ));
 786
 787                 for (i = 0; i < 4; i++) {
 788                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 789                                    i, I915_READ(GEN8_GT_IMR(i)));
 790                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 791                                    i, I915_READ(GEN8_GT_IIR(i)));
 792                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 793                                    i, I915_READ(GEN8_GT_IER(i)));
 794                 }
 795
 796                 gen8_display_interrupt_info(m);
 797         } else if (IS_VALLEYVIEW(dev_priv)) {
 798                 seq_printf(m, "Display IER:\t%08x\n",
 799                            I915_READ(VLV_IER));
 800                 seq_printf(m, "Display IIR:\t%08x\n",
 801                            I915_READ(VLV_IIR));
 802                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 803                            I915_READ(VLV_IIR_RW));
 804                 seq_printf(m, "Display IMR:\t%08x\n",
 805                            I915_READ(VLV_IMR));
 806                 for_each_pipe(dev_priv, pipe) {
 807                         enum intel_display_power_domain power_domain;
 808
 809                         power_domain = POWER_DOMAIN_PIPE(pipe);
 810                         if (!intel_display_power_get_if_enabled(dev_priv,
 811                                                                 power_domain)) {
 812                                 seq_printf(m, "Pipe %c power disabled\n",
 813                                            pipe_name(pipe));
 814                                 continue;
 815                         }
 816
 817                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 818                                    pipe_name(pipe),
 819                                    I915_READ(PIPESTAT(pipe)));
 820                         intel_display_power_put(dev_priv, power_domain);
 821                 }
 822
 823                 seq_printf(m, "Master IER:\t%08x\n",
 824                            I915_READ(VLV_MASTER_IER));
 825
 826                 seq_printf(m, "Render IER:\t%08x\n",
 827                            I915_READ(GTIER));
 828                 seq_printf(m, "Render IIR:\t%08x\n",
 829                            I915_READ(GTIIR));
 830                 seq_printf(m, "Render IMR:\t%08x\n",
 831                            I915_READ(GTIMR));
 832
 833                 seq_printf(m, "PM IER:\t\t%08x\n",
 834                            I915_READ(GEN6_PMIER));
 835                 seq_printf(m, "PM IIR:\t\t%08x\n",
 836                            I915_READ(GEN6_PMIIR));
 837                 seq_printf(m, "PM IMR:\t\t%08x\n",
 838                            I915_READ(GEN6_PMIMR));
 839
 840                 seq_printf(m, "Port hotplug:\t%08x\n",
 841                            I915_READ(PORT_HOTPLUG_EN));
 842                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 843                            I915_READ(VLV_DPFLIPSTAT));
 844                 seq_printf(m, "DPINVGTT:\t%08x\n",
 845                            I915_READ(DPINVGTT));
 846
 847         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 848                 seq_printf(m, "Interrupt enable:    %08x\n",
 849                            I915_READ(IER));
 850                 seq_printf(m, "Interrupt identity:  %08x\n",
 851                            I915_READ(IIR));
 852                 seq_printf(m, "Interrupt mask:      %08x\n",
 853                            I915_READ(IMR));
 854                 for_each_pipe(dev_priv, pipe)
 855                         seq_printf(m, "Pipe %c stat:         %08x\n",
 856                                    pipe_name(pipe),
 857                                    I915_READ(PIPESTAT(pipe)));
 858         } else {
 859                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 860                            I915_READ(DEIER));
 861                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 862                            I915_READ(DEIIR));
 863                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 864                            I915_READ(DEIMR));
 865                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 866                            I915_READ(SDEIER));
 867                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 868                            I915_READ(SDEIIR));
 869                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 870                            I915_READ(SDEIMR));
 871                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 872                            I915_READ(GTIER));
 873                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 874                            I915_READ(GTIIR));
 875                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 876                            I915_READ(GTIMR));
 877         }
 878
 879         if (INTEL_GEN(dev_priv) >= 11) {
 880                 seq_printf(m, "RCS Intr Mask:\t %08x\n",
 881                            I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
 882                 seq_printf(m, "BCS Intr Mask:\t %08x\n",
 883                            I915_READ(GEN11_BCS_RSVD_INTR_MASK));
 884                 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
 885                            I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
 886                 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
 887                            I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
 888                 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
 889                            I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
 890                 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
 891                            I915_READ(GEN11_GUC_SG_INTR_MASK));
 892                 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
 893                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
 894                 seq_printf(m, "Crypto Intr Mask:\t %08x\n",
 895                            I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
 896                 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
 897                            I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
 898
 899         } else if (INTEL_GEN(dev_priv) >= 6) {
 900                 for_each_engine(engine, dev_priv, id) {
 901                         seq_printf(m,
 902                                    "Graphics Interrupt mask (%s):       %08x\n",
 903                                    engine->name, I915_READ_IMR(engine));
 904                 }
 905         }
 906
 907         intel_runtime_pm_put(dev_priv);
 908
 909         return 0;
 910 }
 911
 912 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 913 {
 914         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 915         struct drm_device *dev = &dev_priv->drm;
 916         int i, ret;
 917
 918         ret = mutex_lock_interruptible(&dev->struct_mutex);
 919         if (ret)
 920                 return ret;
 921
 922         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 923         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 924                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 925
 926                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 927                            i, dev_priv->fence_regs[i].pin_count);
 928                 if (!vma)
 929                         seq_puts(m, "unused");
 930                 else
 931                         describe_obj(m, vma->obj);
 932                 seq_putc(m, '\n');
 933         }
 934
 935         mutex_unlock(&dev->struct_mutex);
 936         return 0;
 937 }
 938
 939 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 940 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 941                               size_t count, loff_t *pos)
 942 {
 943         struct i915_gpu_state *error = file->private_data;
 944         struct drm_i915_error_state_buf str;
 945         ssize_t ret;
 946         loff_t tmp;
 947
 948         if (!error)
 949                 return 0;
 950
 951         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 952         if (ret)
 953                 return ret;
 954
 955         ret = i915_error_state_to_str(&str, error);
 956         if (ret)
 957                 goto out;
 958
 959         tmp = 0;
 960         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 961         if (ret < 0)
 962                 goto out;
 963
 964         *pos = str.start + ret;
 965 out:
 966         i915_error_state_buf_release(&str);
 967         return ret;
 968 }
 969
 970 static int gpu_state_release(struct inode *inode, struct file *file)
 971 {
 972         i915_gpu_state_put(file->private_data);
 973         return 0;
 974 }
 975
 976 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 977 {
 978         struct drm_i915_private *i915 = inode->i_private;
 979         struct i915_gpu_state *gpu;
 980
 981         intel_runtime_pm_get(i915);
 982         gpu = i915_capture_gpu_state(i915);
 983         intel_runtime_pm_put(i915);
 984         if (!gpu)
 985                 return -ENOMEM;
 986
 987         file->private_data = gpu;
 988         return 0;
 989 }
 990
 991 static const struct file_operations i915_gpu_info_fops = {
 992         .owner = THIS_MODULE,
 993         .open = i915_gpu_info_open,
 994         .read = gpu_state_read,
 995         .llseek = default_llseek,
 996         .release = gpu_state_release,
 997 };
 998
 999 static ssize_t
1000 i915_error_state_write(struct file *filp,
1001                        const char __user *ubuf,
1002                        size_t cnt,
1003                        loff_t *ppos)
1004 {
1005         struct i915_gpu_state *error = filp->private_data;
1006
1007         if (!error)
1008                 return 0;
1009
1010         DRM_DEBUG_DRIVER("Resetting error state\n");
1011         i915_reset_error_state(error->i915);
1012
1013         return cnt;
1014 }
1015
1016 static int i915_error_state_open(struct inode *inode, struct file *file)
1017 {
1018         file->private_data = i915_first_error_state(inode->i_private);
1019         return 0;
1020 }
1021
1022 static const struct file_operations i915_error_state_fops = {
1023         .owner = THIS_MODULE,
1024         .open = i915_error_state_open,
1025         .read = gpu_state_read,
1026         .write = i915_error_state_write,
1027         .llseek = default_llseek,
1028         .release = gpu_state_release,
1029 };
1030 #endif
1031
1032 static int
1033 i915_next_seqno_set(void *data, u64 val)
1034 {
1035         struct drm_i915_private *dev_priv = data;
1036         struct drm_device *dev = &dev_priv->drm;
1037         int ret;
1038
1039         ret = mutex_lock_interruptible(&dev->struct_mutex);
1040         if (ret)
1041                 return ret;
1042
1043         intel_runtime_pm_get(dev_priv);
1044         ret = i915_gem_set_global_seqno(dev, val);
1045         intel_runtime_pm_put(dev_priv);
1046
1047         mutex_unlock(&dev->struct_mutex);
1048
1049         return ret;
1050 }
1051
1052 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1053                         NULL, i915_next_seqno_set,
1054                         "0x%llx\n");
1055
1056 static int i915_frequency_info(struct seq_file *m, void *unused)
1057 {
1058         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1059         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1060         int ret = 0;
1061
1062         intel_runtime_pm_get(dev_priv);
1063
1064         if (IS_GEN5(dev_priv)) {
1065                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1066                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1067
1068                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1069                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1070                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1071                            MEMSTAT_VID_SHIFT);
1072                 seq_printf(m, "Current P-state: %d\n",
1073                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1074         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1075                 u32 rpmodectl, freq_sts;
1076
1077                 mutex_lock(&dev_priv->pcu_lock);
1078
1079                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1080                 seq_printf(m, "Video Turbo Mode: %s\n",
1081                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1082                 seq_printf(m, "HW control enabled: %s\n",
1083                            yesno(rpmodectl & GEN6_RP_ENABLE));
1084                 seq_printf(m, "SW control enabled: %s\n",
1085                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1086                                   GEN6_RP_MEDIA_SW_MODE));
1087
1088                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1089                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1090                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1091
1092                 seq_printf(m, "actual GPU freq: %d MHz\n",
1093                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1094
1095                 seq_printf(m, "current GPU freq: %d MHz\n",
1096                            intel_gpu_freq(dev_priv, rps->cur_freq));
1097
1098                 seq_printf(m, "max GPU freq: %d MHz\n",
1099                            intel_gpu_freq(dev_priv, rps->max_freq));
1100
1101                 seq_printf(m, "min GPU freq: %d MHz\n",
1102                            intel_gpu_freq(dev_priv, rps->min_freq));
1103
1104                 seq_printf(m, "idle GPU freq: %d MHz\n",
1105                            intel_gpu_freq(dev_priv, rps->idle_freq));
1106
1107                 seq_printf(m,
1108                            "efficient (RPe) frequency: %d MHz\n",
1109                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1110                 mutex_unlock(&dev_priv->pcu_lock);
1111         } else if (INTEL_GEN(dev_priv) >= 6) {
1112                 u32 rp_state_limits;
1113                 u32 gt_perf_status;
1114                 u32 rp_state_cap;
1115                 u32 rpmodectl, rpinclimit, rpdeclimit;
1116                 u32 rpstat, cagf, reqf;
1117                 u32 rpupei, rpcurup, rpprevup;
1118                 u32 rpdownei, rpcurdown, rpprevdown;
1119                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1120                 int max_freq;
1121
1122                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1123                 if (IS_GEN9_LP(dev_priv)) {
1124                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1125                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1126                 } else {
1127                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1128                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1129                 }
1130
1131                 /* RPSTAT1 is in the GT power well */
1132                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1133
1134                 reqf = I915_READ(GEN6_RPNSWREQ);
1135                 if (INTEL_GEN(dev_priv) >= 9)
1136                         reqf >>= 23;
1137                 else {
1138                         reqf &= ~GEN6_TURBO_DISABLE;
1139                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1140                                 reqf >>= 24;
1141                         else
1142                                 reqf >>= 25;
1143                 }
1144                 reqf = intel_gpu_freq(dev_priv, reqf);
1145
1146                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1147                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1148                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1149
1150                 rpstat = I915_READ(GEN6_RPSTAT1);
1151                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1152                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1153                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1154                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1155                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1156                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1157                 cagf = intel_gpu_freq(dev_priv,
1158                                       intel_get_cagf(dev_priv, rpstat));
1159
1160                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1161
1162                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1163                         pm_ier = I915_READ(GEN6_PMIER);
1164                         pm_imr = I915_READ(GEN6_PMIMR);
1165                         pm_isr = I915_READ(GEN6_PMISR);
1166                         pm_iir = I915_READ(GEN6_PMIIR);
1167                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1168                 } else {
1169                         pm_ier = I915_READ(GEN8_GT_IER(2));
1170                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1171                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1172                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1173                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1174                 }
1175                 seq_printf(m, "Video Turbo Mode: %s\n",
1176                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1177                 seq_printf(m, "HW control enabled: %s\n",
1178                            yesno(rpmodectl & GEN6_RP_ENABLE));
1179                 seq_printf(m, "SW control enabled: %s\n",
1180                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1181                                   GEN6_RP_MEDIA_SW_MODE));
1182                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1183                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1184                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1185                            rps->pm_intrmsk_mbz);
1186                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1187                 seq_printf(m, "Render p-state ratio: %d\n",
1188                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1189                 seq_printf(m, "Render p-state VID: %d\n",
1190                            gt_perf_status & 0xff);
1191                 seq_printf(m, "Render p-state limit: %d\n",
1192                            rp_state_limits & 0xff);
1193                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1194                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1195                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1196                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1197                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1198                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1199                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1200                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1201                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1202                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1203                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1204                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1205                 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1206
1207                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1208                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1209                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1210                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1211                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1212                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1213                 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1214
1215                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1216                             rp_state_cap >> 16) & 0xff;
1217                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1218                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1219                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1220                            intel_gpu_freq(dev_priv, max_freq));
1221
1222                 max_freq = (rp_state_cap & 0xff00) >> 8;
1223                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1224                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1225                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1226                            intel_gpu_freq(dev_priv, max_freq));
1227
1228                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1229                             rp_state_cap >> 0) & 0xff;
1230                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1231                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1232                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1233                            intel_gpu_freq(dev_priv, max_freq));
1234                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1235                            intel_gpu_freq(dev_priv, rps->max_freq));
1236
1237                 seq_printf(m, "Current freq: %d MHz\n",
1238                            intel_gpu_freq(dev_priv, rps->cur_freq));
1239                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1240                 seq_printf(m, "Idle freq: %d MHz\n",
1241                            intel_gpu_freq(dev_priv, rps->idle_freq));
1242                 seq_printf(m, "Min freq: %d MHz\n",
1243                            intel_gpu_freq(dev_priv, rps->min_freq));
1244                 seq_printf(m, "Boost freq: %d MHz\n",
1245                            intel_gpu_freq(dev_priv, rps->boost_freq));
1246                 seq_printf(m, "Max freq: %d MHz\n",
1247                            intel_gpu_freq(dev_priv, rps->max_freq));
1248                 seq_printf(m,
1249                            "efficient (RPe) frequency: %d MHz\n",
1250                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1251         } else {
1252                 seq_puts(m, "no P-state info available\n");
1253         }
1254
1255         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1256         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1257         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1258
1259         intel_runtime_pm_put(dev_priv);
1260         return ret;
1261 }
1262
1263 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1264                                struct seq_file *m,
1265                                struct intel_instdone *instdone)
1266 {
1267         int slice;
1268         int subslice;
1269
1270         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1271                    instdone->instdone);
1272
1273         if (INTEL_GEN(dev_priv) <= 3)
1274                 return;
1275
1276         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1277                    instdone->slice_common);
1278
1279         if (INTEL_GEN(dev_priv) <= 6)
1280                 return;
1281
1282         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1283                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1284                            slice, subslice, instdone->sampler[slice][subslice]);
1285
1286         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1287                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1288                            slice, subslice, instdone->row[slice][subslice]);
1289 }
1290
1291 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1292 {
1293         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1294         struct intel_engine_cs *engine;
1295         u64 acthd[I915_NUM_ENGINES];
1296         u32 seqno[I915_NUM_ENGINES];
1297         struct intel_instdone instdone;
1298         enum intel_engine_id id;
1299
1300         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1301                 seq_puts(m, "Wedged\n");
1302         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1303                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1304         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1305                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1306         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1307                 seq_puts(m, "Waiter holding struct mutex\n");
1308         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1309                 seq_puts(m, "struct_mutex blocked for reset\n");
1310
1311         if (!i915_modparams.enable_hangcheck) {
1312                 seq_puts(m, "Hangcheck disabled\n");
1313                 return 0;
1314         }
1315
1316         intel_runtime_pm_get(dev_priv);
1317
1318         for_each_engine(engine, dev_priv, id) {
1319                 acthd[id] = intel_engine_get_active_head(engine);
1320                 seqno[id] = intel_engine_get_seqno(engine);
1321         }
1322
1323         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1324
1325         intel_runtime_pm_put(dev_priv);
1326
1327         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1328                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1329                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1330                                             jiffies));
1331         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1332                 seq_puts(m, "Hangcheck active, work pending\n");
1333         else
1334                 seq_puts(m, "Hangcheck inactive\n");
1335
1336         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1337
1338         for_each_engine(engine, dev_priv, id) {
1339                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1340                 struct rb_node *rb;
1341
1342                 seq_printf(m, "%s:\n", engine->name);
1343                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1344                            engine->hangcheck.seqno, seqno[id],
1345                            intel_engine_last_submit(engine),
1346                            engine->timeline->inflight_seqnos);
1347                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1348                            yesno(intel_engine_has_waiter(engine)),
1349                            yesno(test_bit(engine->id,
1350                                           &dev_priv->gpu_error.missed_irq_rings)),
1351                            yesno(engine->hangcheck.stalled));
1352
1353                 spin_lock_irq(&b->rb_lock);
1354                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1355                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1356
1357                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1358                                    w->tsk->comm, w->tsk->pid, w->seqno);
1359                 }
1360                 spin_unlock_irq(&b->rb_lock);
1361
1362                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1363                            (long long)engine->hangcheck.acthd,
1364                            (long long)acthd[id]);
1365                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1366                            hangcheck_action_to_str(engine->hangcheck.action),
1367                            engine->hangcheck.action,
1368                            jiffies_to_msecs(jiffies -
1369                                             engine->hangcheck.action_timestamp));
1370
1371                 if (engine->id == RCS) {
1372                         seq_puts(m, "\tinstdone read =\n");
1373
1374                         i915_instdone_info(dev_priv, m, &instdone);
1375
1376                         seq_puts(m, "\tinstdone accu =\n");
1377
1378                         i915_instdone_info(dev_priv, m,
1379                                            &engine->hangcheck.instdone);
1380                 }
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int i915_reset_info(struct seq_file *m, void *unused)
1387 {
1388         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1389         struct i915_gpu_error *error = &dev_priv->gpu_error;
1390         struct intel_engine_cs *engine;
1391         enum intel_engine_id id;
1392
1393         seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1394
1395         for_each_engine(engine, dev_priv, id) {
1396                 seq_printf(m, "%s = %u\n", engine->name,
1397                            i915_reset_engine_count(error, engine));
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int ironlake_drpc_info(struct seq_file *m)
1404 {
1405         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1406         u32 rgvmodectl, rstdbyctl;
1407         u16 crstandvid;
1408
1409         rgvmodectl = I915_READ(MEMMODECTL);
1410         rstdbyctl = I915_READ(RSTDBYCTL);
1411         crstandvid = I915_READ16(CRSTANDVID);
1412
1413         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1414         seq_printf(m, "Boost freq: %d\n",
1415                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1416                    MEMMODE_BOOST_FREQ_SHIFT);
1417         seq_printf(m, "HW control enabled: %s\n",
1418                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1419         seq_printf(m, "SW control enabled: %s\n",
1420                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1421         seq_printf(m, "Gated voltage change: %s\n",
1422                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1423         seq_printf(m, "Starting frequency: P%d\n",
1424                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1425         seq_printf(m, "Max P-state: P%d\n",
1426                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1427         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1428         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1429         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1430         seq_printf(m, "Render standby enabled: %s\n",
1431                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1432         seq_puts(m, "Current RS state: ");
1433         switch (rstdbyctl & RSX_STATUS_MASK) {
1434         case RSX_STATUS_ON:
1435                 seq_puts(m, "on\n");
1436                 break;
1437         case RSX_STATUS_RC1:
1438                 seq_puts(m, "RC1\n");
1439                 break;
1440         case RSX_STATUS_RC1E:
1441                 seq_puts(m, "RC1E\n");
1442                 break;
1443         case RSX_STATUS_RS1:
1444                 seq_puts(m, "RS1\n");
1445                 break;
1446         case RSX_STATUS_RS2:
1447                 seq_puts(m, "RS2 (RC6)\n");
1448                 break;
1449         case RSX_STATUS_RS3:
1450                 seq_puts(m, "RC3 (RC6+)\n");
1451                 break;
1452         default:
1453                 seq_puts(m, "unknown\n");
1454                 break;
1455         }
1456
1457         return 0;
1458 }
1459
1460 static int i915_forcewake_domains(struct seq_file *m, void *data)
1461 {
1462         struct drm_i915_private *i915 = node_to_i915(m->private);
1463         struct intel_uncore_forcewake_domain *fw_domain;
1464         unsigned int tmp;
1465
1466         seq_printf(m, "user.bypass_count = %u\n",
1467                    i915->uncore.user_forcewake.count);
1468
1469         for_each_fw_domain(fw_domain, i915, tmp)
1470                 seq_printf(m, "%s.wake_count = %u\n",
1471                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1472                            READ_ONCE(fw_domain->wake_count));
1473
1474         return 0;
1475 }
1476
1477 static void print_rc6_res(struct seq_file *m,
1478                           const char *title,
1479                           const i915_reg_t reg)
1480 {
1481         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1482
1483         seq_printf(m, "%s %u (%llu us)\n",
1484                    title, I915_READ(reg),
1485                    intel_rc6_residency_us(dev_priv, reg));
1486 }
1487
1488 static int vlv_drpc_info(struct seq_file *m)
1489 {
1490         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1491         u32 rcctl1, pw_status;
1492
1493         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1494         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1495
1496         seq_printf(m, "RC6 Enabled: %s\n",
1497                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1498                                         GEN6_RC_CTL_EI_MODE(1))));
1499         seq_printf(m, "Render Power Well: %s\n",
1500                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1501         seq_printf(m, "Media Power Well: %s\n",
1502                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1503
1504         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1505         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1506
1507         return i915_forcewake_domains(m, NULL);
1508 }
1509
1510 static int gen6_drpc_info(struct seq_file *m)
1511 {
1512         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1513         u32 gt_core_status, rcctl1, rc6vids = 0;
1514         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1515
1516         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1517         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1518
1519         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1520         if (INTEL_GEN(dev_priv) >= 9) {
1521                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1522                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1523         }
1524
1525         if (INTEL_GEN(dev_priv) <= 7) {
1526                 mutex_lock(&dev_priv->pcu_lock);
1527                 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
1528                                        &rc6vids);
1529                 mutex_unlock(&dev_priv->pcu_lock);
1530         }
1531
1532         seq_printf(m, "RC1e Enabled: %s\n",
1533                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1534         seq_printf(m, "RC6 Enabled: %s\n",
1535                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1536         if (INTEL_GEN(dev_priv) >= 9) {
1537                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1538                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1539                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1540                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1541         }
1542         seq_printf(m, "Deep RC6 Enabled: %s\n",
1543                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1544         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1545                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1546         seq_puts(m, "Current RC state: ");
1547         switch (gt_core_status & GEN6_RCn_MASK) {
1548         case GEN6_RC0:
1549                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1550                         seq_puts(m, "Core Power Down\n");
1551                 else
1552                         seq_puts(m, "on\n");
1553                 break;
1554         case GEN6_RC3:
1555                 seq_puts(m, "RC3\n");
1556                 break;
1557         case GEN6_RC6:
1558                 seq_puts(m, "RC6\n");
1559                 break;
1560         case GEN6_RC7:
1561                 seq_puts(m, "RC7\n");
1562                 break;
1563         default:
1564                 seq_puts(m, "Unknown\n");
1565                 break;
1566         }
1567
1568         seq_printf(m, "Core Power Down: %s\n",
1569                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1570         if (INTEL_GEN(dev_priv) >= 9) {
1571                 seq_printf(m, "Render Power Well: %s\n",
1572                         (gen9_powergate_status &
1573                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1574                 seq_printf(m, "Media Power Well: %s\n",
1575                         (gen9_powergate_status &
1576                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1577         }
1578
1579         /* Not exactly sure what this is */
1580         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1581                       GEN6_GT_GFX_RC6_LOCKED);
1582         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1583         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1584         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1585
1586         if (INTEL_GEN(dev_priv) <= 7) {
1587                 seq_printf(m, "RC6   voltage: %dmV\n",
1588                            GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589                 seq_printf(m, "RC6+  voltage: %dmV\n",
1590                            GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591                 seq_printf(m, "RC6++ voltage: %dmV\n",
1592                            GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1593         }
1594
1595         return i915_forcewake_domains(m, NULL);
1596 }
1597
1598 static int i915_drpc_info(struct seq_file *m, void *unused)
1599 {
1600         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1601         int err;
1602
1603         intel_runtime_pm_get(dev_priv);
1604
1605         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1606                 err = vlv_drpc_info(m);
1607         else if (INTEL_GEN(dev_priv) >= 6)
1608                 err = gen6_drpc_info(m);
1609         else
1610                 err = ironlake_drpc_info(m);
1611
1612         intel_runtime_pm_put(dev_priv);
1613
1614         return err;
1615 }
1616
1617 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1618 {
1619         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1620
1621         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1622                    dev_priv->fb_tracking.busy_bits);
1623
1624         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1625                    dev_priv->fb_tracking.flip_bits);
1626
1627         return 0;
1628 }
1629
1630 static int i915_fbc_status(struct seq_file *m, void *unused)
1631 {
1632         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1633         struct intel_fbc *fbc = &dev_priv->fbc;
1634
1635         if (!HAS_FBC(dev_priv))
1636                 return -ENODEV;
1637
1638         intel_runtime_pm_get(dev_priv);
1639         mutex_lock(&fbc->lock);
1640
1641         if (intel_fbc_is_active(dev_priv))
1642                 seq_puts(m, "FBC enabled\n");
1643         else
1644                 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1645
1646         if (fbc->work.scheduled)
1647                 seq_printf(m, "FBC worker scheduled on vblank %llu, now %llu\n",
1648                            fbc->work.scheduled_vblank,
1649                            drm_crtc_vblank_count(&fbc->crtc->base));
1650
1651         if (intel_fbc_is_active(dev_priv)) {
1652                 u32 mask;
1653
1654                 if (INTEL_GEN(dev_priv) >= 8)
1655                         mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1656                 else if (INTEL_GEN(dev_priv) >= 7)
1657                         mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1658                 else if (INTEL_GEN(dev_priv) >= 5)
1659                         mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1660                 else if (IS_G4X(dev_priv))
1661                         mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1662                 else
1663                         mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1664                                                         FBC_STAT_COMPRESSED);
1665
1666                 seq_printf(m, "Compressing: %s\n", yesno(mask));
1667         }
1668
1669         mutex_unlock(&fbc->lock);
1670         intel_runtime_pm_put(dev_priv);
1671
1672         return 0;
1673 }
1674
1675 static int i915_fbc_false_color_get(void *data, u64 *val)
1676 {
1677         struct drm_i915_private *dev_priv = data;
1678
1679         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1680                 return -ENODEV;
1681
1682         *val = dev_priv->fbc.false_color;
1683
1684         return 0;
1685 }
1686
1687 static int i915_fbc_false_color_set(void *data, u64 val)
1688 {
1689         struct drm_i915_private *dev_priv = data;
1690         u32 reg;
1691
1692         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1693                 return -ENODEV;
1694
1695         mutex_lock(&dev_priv->fbc.lock);
1696
1697         reg = I915_READ(ILK_DPFC_CONTROL);
1698         dev_priv->fbc.false_color = val;
1699
1700         I915_WRITE(ILK_DPFC_CONTROL, val ?
1701                    (reg | FBC_CTL_FALSE_COLOR) :
1702                    (reg & ~FBC_CTL_FALSE_COLOR));
1703
1704         mutex_unlock(&dev_priv->fbc.lock);
1705         return 0;
1706 }
1707
1708 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1709                         i915_fbc_false_color_get, i915_fbc_false_color_set,
1710                         "%llu\n");
1711
1712 static int i915_ips_status(struct seq_file *m, void *unused)
1713 {
1714         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1715
1716         if (!HAS_IPS(dev_priv))
1717                 return -ENODEV;
1718
1719         intel_runtime_pm_get(dev_priv);
1720
1721         seq_printf(m, "Enabled by kernel parameter: %s\n",
1722                    yesno(i915_modparams.enable_ips));
1723
1724         if (INTEL_GEN(dev_priv) >= 8) {
1725                 seq_puts(m, "Currently: unknown\n");
1726         } else {
1727                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1728                         seq_puts(m, "Currently: enabled\n");
1729                 else
1730                         seq_puts(m, "Currently: disabled\n");
1731         }
1732
1733         intel_runtime_pm_put(dev_priv);
1734
1735         return 0;
1736 }
1737
1738 static int i915_sr_status(struct seq_file *m, void *unused)
1739 {
1740         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1741         bool sr_enabled = false;
1742
1743         intel_runtime_pm_get(dev_priv);
1744         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1745
1746         if (INTEL_GEN(dev_priv) >= 9)
1747                 /* no global SR status; inspect per-plane WM */;
1748         else if (HAS_PCH_SPLIT(dev_priv))
1749                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1750         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1751                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1752                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1753         else if (IS_I915GM(dev_priv))
1754                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1755         else if (IS_PINEVIEW(dev_priv))
1756                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1757         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1758                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1759
1760         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1761         intel_runtime_pm_put(dev_priv);
1762
1763         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1764
1765         return 0;
1766 }
1767
1768 static int i915_emon_status(struct seq_file *m, void *unused)
1769 {
1770         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1771         struct drm_device *dev = &dev_priv->drm;
1772         unsigned long temp, chipset, gfx;
1773         int ret;
1774
1775         if (!IS_GEN5(dev_priv))
1776                 return -ENODEV;
1777
1778         ret = mutex_lock_interruptible(&dev->struct_mutex);
1779         if (ret)
1780                 return ret;
1781
1782         temp = i915_mch_val(dev_priv);
1783         chipset = i915_chipset_val(dev_priv);
1784         gfx = i915_gfx_val(dev_priv);
1785         mutex_unlock(&dev->struct_mutex);
1786
1787         seq_printf(m, "GMCH temp: %ld\n", temp);
1788         seq_printf(m, "Chipset power: %ld\n", chipset);
1789         seq_printf(m, "GFX power: %ld\n", gfx);
1790         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1791
1792         return 0;
1793 }
1794
1795 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1796 {
1797         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1798         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1799         unsigned int max_gpu_freq, min_gpu_freq;
1800         int gpu_freq, ia_freq;
1801         int ret;
1802
1803         if (!HAS_LLC(dev_priv))
1804                 return -ENODEV;
1805
1806         intel_runtime_pm_get(dev_priv);
1807
1808         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1809         if (ret)
1810                 goto out;
1811
1812         min_gpu_freq = rps->min_freq;
1813         max_gpu_freq = rps->max_freq;
1814         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1815                 /* Convert GT frequency to 50 HZ units */
1816                 min_gpu_freq /= GEN9_FREQ_SCALER;
1817                 max_gpu_freq /= GEN9_FREQ_SCALER;
1818         }
1819
1820         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1821
1822         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1823                 ia_freq = gpu_freq;
1824                 sandybridge_pcode_read(dev_priv,
1825                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1826                                        &ia_freq);
1827                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1828                            intel_gpu_freq(dev_priv, (gpu_freq *
1829                                                      (IS_GEN9_BC(dev_priv) ||
1830                                                       IS_CANNONLAKE(dev_priv) ?
1831                                                       GEN9_FREQ_SCALER : 1))),
1832                            ((ia_freq >> 0) & 0xff) * 100,
1833                            ((ia_freq >> 8) & 0xff) * 100);
1834         }
1835
1836         mutex_unlock(&dev_priv->pcu_lock);
1837
1838 out:
1839         intel_runtime_pm_put(dev_priv);
1840         return ret;
1841 }
1842
1843 static int i915_opregion(struct seq_file *m, void *unused)
1844 {
1845         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1846         struct drm_device *dev = &dev_priv->drm;
1847         struct intel_opregion *opregion = &dev_priv->opregion;
1848         int ret;
1849
1850         ret = mutex_lock_interruptible(&dev->struct_mutex);
1851         if (ret)
1852                 goto out;
1853
1854         if (opregion->header)
1855                 seq_write(m, opregion->header, OPREGION_SIZE);
1856
1857         mutex_unlock(&dev->struct_mutex);
1858
1859 out:
1860         return 0;
1861 }
1862
1863 static int i915_vbt(struct seq_file *m, void *unused)
1864 {
1865         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1866
1867         if (opregion->vbt)
1868                 seq_write(m, opregion->vbt, opregion->vbt_size);
1869
1870         return 0;
1871 }
1872
1873 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1874 {
1875         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1876         struct drm_device *dev = &dev_priv->drm;
1877         struct intel_framebuffer *fbdev_fb = NULL;
1878         struct drm_framebuffer *drm_fb;
1879         int ret;
1880
1881         ret = mutex_lock_interruptible(&dev->struct_mutex);
1882         if (ret)
1883                 return ret;
1884
1885 #ifdef CONFIG_DRM_FBDEV_EMULATION
1886         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1887                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1888
1889                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1890                            fbdev_fb->base.width,
1891                            fbdev_fb->base.height,
1892                            fbdev_fb->base.format->depth,
1893                            fbdev_fb->base.format->cpp[0] * 8,
1894                            fbdev_fb->base.modifier,
1895                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1896                 describe_obj(m, fbdev_fb->obj);
1897                 seq_putc(m, '\n');
1898         }
1899 #endif
1900
1901         mutex_lock(&dev->mode_config.fb_lock);
1902         drm_for_each_fb(drm_fb, dev) {
1903                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1904                 if (fb == fbdev_fb)
1905                         continue;
1906
1907                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1908                            fb->base.width,
1909                            fb->base.height,
1910                            fb->base.format->depth,
1911                            fb->base.format->cpp[0] * 8,
1912                            fb->base.modifier,
1913                            drm_framebuffer_read_refcount(&fb->base));
1914                 describe_obj(m, fb->obj);
1915                 seq_putc(m, '\n');
1916         }
1917         mutex_unlock(&dev->mode_config.fb_lock);
1918         mutex_unlock(&dev->struct_mutex);
1919
1920         return 0;
1921 }
1922
1923 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1924 {
1925         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
1926                    ring->space, ring->head, ring->tail, ring->emit);
1927 }
1928
1929 static int i915_context_status(struct seq_file *m, void *unused)
1930 {
1931         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1932         struct drm_device *dev = &dev_priv->drm;
1933         struct intel_engine_cs *engine;
1934         struct i915_gem_context *ctx;
1935         enum intel_engine_id id;
1936         int ret;
1937
1938         ret = mutex_lock_interruptible(&dev->struct_mutex);
1939         if (ret)
1940                 return ret;
1941
1942         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1943                 seq_printf(m, "HW context %u ", ctx->hw_id);
1944                 if (ctx->pid) {
1945                         struct task_struct *task;
1946
1947                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1948                         if (task) {
1949                                 seq_printf(m, "(%s [%d]) ",
1950                                            task->comm, task->pid);
1951                                 put_task_struct(task);
1952                         }
1953                 } else if (IS_ERR(ctx->file_priv)) {
1954                         seq_puts(m, "(deleted) ");
1955                 } else {
1956                         seq_puts(m, "(kernel) ");
1957                 }
1958
1959                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1960                 seq_putc(m, '\n');
1961
1962                 for_each_engine(engine, dev_priv, id) {
1963                         struct intel_context *ce = &ctx->engine[engine->id];
1964
1965                         seq_printf(m, "%s: ", engine->name);
1966                         if (ce->state)
1967                                 describe_obj(m, ce->state->obj);
1968                         if (ce->ring)
1969                                 describe_ctx_ring(m, ce->ring);
1970                         seq_putc(m, '\n');
1971                 }
1972
1973                 seq_putc(m, '\n');
1974         }
1975
1976         mutex_unlock(&dev->struct_mutex);
1977
1978         return 0;
1979 }
1980
1981 static const char *swizzle_string(unsigned swizzle)
1982 {
1983         switch (swizzle) {
1984         case I915_BIT_6_SWIZZLE_NONE:
1985                 return "none";
1986         case I915_BIT_6_SWIZZLE_9:
1987                 return "bit9";
1988         case I915_BIT_6_SWIZZLE_9_10:
1989                 return "bit9/bit10";
1990         case I915_BIT_6_SWIZZLE_9_11:
1991                 return "bit9/bit11";
1992         case I915_BIT_6_SWIZZLE_9_10_11:
1993                 return "bit9/bit10/bit11";
1994         case I915_BIT_6_SWIZZLE_9_17:
1995                 return "bit9/bit17";
1996         case I915_BIT_6_SWIZZLE_9_10_17:
1997                 return "bit9/bit10/bit17";
1998         case I915_BIT_6_SWIZZLE_UNKNOWN:
1999                 return "unknown";
2000         }
2001
2002         return "bug";
2003 }
2004
2005 static int i915_swizzle_info(struct seq_file *m, void *data)
2006 {
2007         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2008
2009         intel_runtime_pm_get(dev_priv);
2010
2011         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2012                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2013         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2014                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2015
2016         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2017                 seq_printf(m, "DDC = 0x%08x\n",
2018                            I915_READ(DCC));
2019                 seq_printf(m, "DDC2 = 0x%08x\n",
2020                            I915_READ(DCC2));
2021                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2022                            I915_READ16(C0DRB3));
2023                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2024                            I915_READ16(C1DRB3));
2025         } else if (INTEL_GEN(dev_priv) >= 6) {
2026                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2027                            I915_READ(MAD_DIMM_C0));
2028                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2029                            I915_READ(MAD_DIMM_C1));
2030                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2031                            I915_READ(MAD_DIMM_C2));
2032                 seq_printf(m, "TILECTL = 0x%08x\n",
2033                            I915_READ(TILECTL));
2034                 if (INTEL_GEN(dev_priv) >= 8)
2035                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2036                                    I915_READ(GAMTARBMODE));
2037                 else
2038                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2039                                    I915_READ(ARB_MODE));
2040                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2041                            I915_READ(DISP_ARB_CTL));
2042         }
2043
2044         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2045                 seq_puts(m, "L-shaped memory detected\n");
2046
2047         intel_runtime_pm_put(dev_priv);
2048
2049         return 0;
2050 }
2051
2052 static int per_file_ctx(int id, void *ptr, void *data)
2053 {
2054         struct i915_gem_context *ctx = ptr;
2055         struct seq_file *m = data;
2056         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2057
2058         if (!ppgtt) {
2059                 seq_printf(m, "  no ppgtt for context %d\n",
2060                            ctx->user_handle);
2061                 return 0;
2062         }
2063
2064         if (i915_gem_context_is_default(ctx))
2065                 seq_puts(m, "  default context:\n");
2066         else
2067                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2068         ppgtt->debug_dump(ppgtt, m);
2069
2070         return 0;
2071 }
2072
2073 static void gen8_ppgtt_info(struct seq_file *m,
2074                             struct drm_i915_private *dev_priv)
2075 {
2076         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2077         struct intel_engine_cs *engine;
2078         enum intel_engine_id id;
2079         int i;
2080
2081         if (!ppgtt)
2082                 return;
2083
2084         for_each_engine(engine, dev_priv, id) {
2085                 seq_printf(m, "%s\n", engine->name);
2086                 for (i = 0; i < 4; i++) {
2087                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2088                         pdp <<= 32;
2089                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2090                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2091                 }
2092         }
2093 }
2094
2095 static void gen6_ppgtt_info(struct seq_file *m,
2096                             struct drm_i915_private *dev_priv)
2097 {
2098         struct intel_engine_cs *engine;
2099         enum intel_engine_id id;
2100
2101         if (IS_GEN6(dev_priv))
2102                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2103
2104         for_each_engine(engine, dev_priv, id) {
2105                 seq_printf(m, "%s\n", engine->name);
2106                 if (IS_GEN7(dev_priv))
2107                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2108                                    I915_READ(RING_MODE_GEN7(engine)));
2109                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2110                            I915_READ(RING_PP_DIR_BASE(engine)));
2111                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2112                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2113                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2114                            I915_READ(RING_PP_DIR_DCLV(engine)));
2115         }
2116         if (dev_priv->mm.aliasing_ppgtt) {
2117                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2118
2119                 seq_puts(m, "aliasing PPGTT:\n");
2120                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2121
2122                 ppgtt->debug_dump(ppgtt, m);
2123         }
2124
2125         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2126 }
2127
2128 static int i915_ppgtt_info(struct seq_file *m, void *data)
2129 {
2130         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2131         struct drm_device *dev = &dev_priv->drm;
2132         struct drm_file *file;
2133         int ret;
2134
2135         mutex_lock(&dev->filelist_mutex);
2136         ret = mutex_lock_interruptible(&dev->struct_mutex);
2137         if (ret)
2138                 goto out_unlock;
2139
2140         intel_runtime_pm_get(dev_priv);
2141
2142         if (INTEL_GEN(dev_priv) >= 8)
2143                 gen8_ppgtt_info(m, dev_priv);
2144         else if (INTEL_GEN(dev_priv) >= 6)
2145                 gen6_ppgtt_info(m, dev_priv);
2146
2147         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2148                 struct drm_i915_file_private *file_priv = file->driver_priv;
2149                 struct task_struct *task;
2150
2151                 task = get_pid_task(file->pid, PIDTYPE_PID);
2152                 if (!task) {
2153                         ret = -ESRCH;
2154                         goto out_rpm;
2155                 }
2156                 seq_printf(m, "\nproc: %s\n", task->comm);
2157                 put_task_struct(task);
2158                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2159                              (void *)(unsigned long)m);
2160         }
2161
2162 out_rpm:
2163         intel_runtime_pm_put(dev_priv);
2164         mutex_unlock(&dev->struct_mutex);
2165 out_unlock:
2166         mutex_unlock(&dev->filelist_mutex);
2167         return ret;
2168 }
2169
2170 static int count_irq_waiters(struct drm_i915_private *i915)
2171 {
2172         struct intel_engine_cs *engine;
2173         enum intel_engine_id id;
2174         int count = 0;
2175
2176         for_each_engine(engine, i915, id)
2177                 count += intel_engine_has_waiter(engine);
2178
2179         return count;
2180 }
2181
2182 static const char *rps_power_to_str(unsigned int power)
2183 {
2184         static const char * const strings[] = {
2185                 [LOW_POWER] = "low power",
2186                 [BETWEEN] = "mixed",
2187                 [HIGH_POWER] = "high power",
2188         };
2189
2190         if (power >= ARRAY_SIZE(strings) || !strings[power])
2191                 return "unknown";
2192
2193         return strings[power];
2194 }
2195
2196 static int i915_rps_boost_info(struct seq_file *m, void *data)
2197 {
2198         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2199         struct drm_device *dev = &dev_priv->drm;
2200         struct intel_rps *rps = &dev_priv->gt_pm.rps;
2201         struct drm_file *file;
2202
2203         seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2204         seq_printf(m, "GPU busy? %s [%d requests]\n",
2205                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2206         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2207         seq_printf(m, "Boosts outstanding? %d\n",
2208                    atomic_read(&rps->num_waiters));
2209         seq_printf(m, "Frequency requested %d\n",
2210                    intel_gpu_freq(dev_priv, rps->cur_freq));
2211         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2212                    intel_gpu_freq(dev_priv, rps->min_freq),
2213                    intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2214                    intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2215                    intel_gpu_freq(dev_priv, rps->max_freq));
2216         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2217                    intel_gpu_freq(dev_priv, rps->idle_freq),
2218                    intel_gpu_freq(dev_priv, rps->efficient_freq),
2219                    intel_gpu_freq(dev_priv, rps->boost_freq));
2220
2221         mutex_lock(&dev->filelist_mutex);
2222         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2223                 struct drm_i915_file_private *file_priv = file->driver_priv;
2224                 struct task_struct *task;
2225
2226                 rcu_read_lock();
2227                 task = pid_task(file->pid, PIDTYPE_PID);
2228                 seq_printf(m, "%s [%d]: %d boosts\n",
2229                            task ? task->comm : "<unknown>",
2230                            task ? task->pid : -1,
2231                            atomic_read(&file_priv->rps_client.boosts));
2232                 rcu_read_unlock();
2233         }
2234         seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2235                    atomic_read(&rps->boosts));
2236         mutex_unlock(&dev->filelist_mutex);
2237
2238         if (INTEL_GEN(dev_priv) >= 6 &&
2239             rps->enabled &&
2240             dev_priv->gt.active_requests) {
2241                 u32 rpup, rpupei;
2242                 u32 rpdown, rpdownei;
2243
2244                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2245                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2246                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2247                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2248                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2249                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2250
2251                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2252                            rps_power_to_str(rps->power));
2253                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2254                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2255                            rps->up_threshold);
2256                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2257                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2258                            rps->down_threshold);
2259         } else {
2260                 seq_puts(m, "\nRPS Autotuning inactive\n");
2261         }
2262
2263         return 0;
2264 }
2265
2266 static int i915_llc(struct seq_file *m, void *data)
2267 {
2268         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2269         const bool edram = INTEL_GEN(dev_priv) > 8;
2270
2271         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2272         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2273                    intel_uncore_edram_size(dev_priv)/1024/1024);
2274
2275         return 0;
2276 }
2277
2278 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2279 {
2280         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2281         struct drm_printer p;
2282
2283         if (!HAS_HUC(dev_priv))
2284                 return -ENODEV;
2285
2286         p = drm_seq_file_printer(m);
2287         intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2288
2289         intel_runtime_pm_get(dev_priv);
2290         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2291         intel_runtime_pm_put(dev_priv);
2292
2293         return 0;
2294 }
2295
2296 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2297 {
2298         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2299         struct drm_printer p;
2300         u32 tmp, i;
2301
2302         if (!HAS_GUC(dev_priv))
2303                 return -ENODEV;
2304
2305         p = drm_seq_file_printer(m);
2306         intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2307
2308         intel_runtime_pm_get(dev_priv);
2309
2310         tmp = I915_READ(GUC_STATUS);
2311
2312         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2313         seq_printf(m, "\tBootrom status = 0x%x\n",
2314                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2315         seq_printf(m, "\tuKernel status = 0x%x\n",
2316                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2317         seq_printf(m, "\tMIA Core status = 0x%x\n",
2318                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2319         seq_puts(m, "\nScratch registers:\n");
2320         for (i = 0; i < 16; i++)
2321                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2322
2323         intel_runtime_pm_put(dev_priv);
2324
2325         return 0;
2326 }
2327
2328 static const char *
2329 stringify_guc_log_type(enum guc_log_buffer_type type)
2330 {
2331         switch (type) {
2332         case GUC_ISR_LOG_BUFFER:
2333                 return "ISR";
2334         case GUC_DPC_LOG_BUFFER:
2335                 return "DPC";
2336         case GUC_CRASH_DUMP_LOG_BUFFER:
2337                 return "CRASH";
2338         default:
2339                 MISSING_CASE(type);
2340         }
2341
2342         return "";
2343 }
2344
2345 static void i915_guc_log_info(struct seq_file *m,
2346                               struct drm_i915_private *dev_priv)
2347 {
2348         struct intel_guc_log *log = &dev_priv->guc.log;
2349         enum guc_log_buffer_type type;
2350
2351         if (!intel_guc_log_relay_enabled(log)) {
2352                 seq_puts(m, "GuC log relay disabled\n");
2353                 return;
2354         }
2355
2356         seq_puts(m, "GuC logging stats:\n");
2357
2358         seq_printf(m, "\tRelay full count: %u\n",
2359                    log->relay.full_count);
2360
2361         for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
2362                 seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
2363                            stringify_guc_log_type(type),
2364                            log->stats[type].flush,
2365                            log->stats[type].sampled_overflow);
2366         }
2367 }
2368
2369 static void i915_guc_client_info(struct seq_file *m,
2370                                  struct drm_i915_private *dev_priv,
2371                                  struct intel_guc_client *client)
2372 {
2373         struct intel_engine_cs *engine;
2374         enum intel_engine_id id;
2375         uint64_t tot = 0;
2376
2377         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2378                 client->priority, client->stage_id, client->proc_desc_offset);
2379         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2380                 client->doorbell_id, client->doorbell_offset);
2381
2382         for_each_engine(engine, dev_priv, id) {
2383                 u64 submissions = client->submissions[id];
2384                 tot += submissions;
2385                 seq_printf(m, "\tSubmissions: %llu %s\n",
2386                                 submissions, engine->name);
2387         }
2388         seq_printf(m, "\tTotal: %llu\n", tot);
2389 }
2390
2391 static int i915_guc_info(struct seq_file *m, void *data)
2392 {
2393         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2394         const struct intel_guc *guc = &dev_priv->guc;
2395
2396         if (!USES_GUC(dev_priv))
2397                 return -ENODEV;
2398
2399         i915_guc_log_info(m, dev_priv);
2400
2401         if (!USES_GUC_SUBMISSION(dev_priv))
2402                 return 0;
2403
2404         GEM_BUG_ON(!guc->execbuf_client);
2405
2406         seq_printf(m, "\nDoorbell map:\n");
2407         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2408         seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline);
2409
2410         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2411         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2412         if (guc->preempt_client) {
2413                 seq_printf(m, "\nGuC preempt client @ %p:\n",
2414                            guc->preempt_client);
2415                 i915_guc_client_info(m, dev_priv, guc->preempt_client);
2416         }
2417
2418         /* Add more as required ... */
2419
2420         return 0;
2421 }
2422
2423 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2424 {
2425         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2426         const struct intel_guc *guc = &dev_priv->guc;
2427         struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2428         struct intel_guc_client *client = guc->execbuf_client;
2429         unsigned int tmp;
2430         int index;
2431
2432         if (!USES_GUC_SUBMISSION(dev_priv))
2433                 return -ENODEV;
2434
2435         for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2436                 struct intel_engine_cs *engine;
2437
2438                 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2439                         continue;
2440
2441                 seq_printf(m, "GuC stage descriptor %u:\n", index);
2442                 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2443                 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2444                 seq_printf(m, "\tPriority: %d\n", desc->priority);
2445                 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2446                 seq_printf(m, "\tEngines used: 0x%x\n",
2447                            desc->engines_used);
2448                 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2449                            desc->db_trigger_phy,
2450                            desc->db_trigger_cpu,
2451                            desc->db_trigger_uk);
2452                 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2453                            desc->process_desc);
2454                 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2455                            desc->wq_addr, desc->wq_size);
2456                 seq_putc(m, '\n');
2457
2458                 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2459                         u32 guc_engine_id = engine->guc_id;
2460                         struct guc_execlist_context *lrc =
2461                                                 &desc->lrc[guc_engine_id];
2462
2463                         seq_printf(m, "\t%s LRC:\n", engine->name);
2464                         seq_printf(m, "\t\tContext desc: 0x%x\n",
2465                                    lrc->context_desc);
2466                         seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2467                         seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2468                         seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2469                         seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2470                         seq_putc(m, '\n');
2471                 }
2472         }
2473
2474         return 0;
2475 }
2476
2477 static int i915_guc_log_dump(struct seq_file *m, void *data)
2478 {
2479         struct drm_info_node *node = m->private;
2480         struct drm_i915_private *dev_priv = node_to_i915(node);
2481         bool dump_load_err = !!node->info_ent->data;
2482         struct drm_i915_gem_object *obj = NULL;
2483         u32 *log;
2484         int i = 0;
2485
2486         if (!HAS_GUC(dev_priv))
2487                 return -ENODEV;
2488
2489         if (dump_load_err)
2490                 obj = dev_priv->guc.load_err_log;
2491         else if (dev_priv->guc.log.vma)
2492                 obj = dev_priv->guc.log.vma->obj;
2493
2494         if (!obj)
2495                 return 0;
2496
2497         log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2498         if (IS_ERR(log)) {
2499                 DRM_DEBUG("Failed to pin object\n");
2500                 seq_puts(m, "(log data unaccessible)\n");
2501                 return PTR_ERR(log);
2502         }
2503
2504         for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2505                 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2506                            *(log + i), *(log + i + 1),
2507                            *(log + i + 2), *(log + i + 3));
2508
2509         seq_putc(m, '\n');
2510
2511         i915_gem_object_unpin_map(obj);
2512
2513         return 0;
2514 }
2515
2516 static int i915_guc_log_level_get(void *data, u64 *val)
2517 {
2518         struct drm_i915_private *dev_priv = data;
2519
2520         if (!USES_GUC(dev_priv))
2521                 return -ENODEV;
2522
2523         *val = intel_guc_log_level_get(&dev_priv->guc.log);
2524
2525         return 0;
2526 }
2527
2528 static int i915_guc_log_level_set(void *data, u64 val)
2529 {
2530         struct drm_i915_private *dev_priv = data;
2531
2532         if (!USES_GUC(dev_priv))
2533                 return -ENODEV;
2534
2535         return intel_guc_log_level_set(&dev_priv->guc.log, val);
2536 }
2537
2538 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
2539                         i915_guc_log_level_get, i915_guc_log_level_set,
2540                         "%lld\n");
2541
2542 static int i915_guc_log_relay_open(struct inode *inode, struct file *file)
2543 {
2544         struct drm_i915_private *dev_priv = inode->i_private;
2545
2546         if (!USES_GUC(dev_priv))
2547                 return -ENODEV;
2548
2549         file->private_data = &dev_priv->guc.log;
2550
2551         return intel_guc_log_relay_open(&dev_priv->guc.log);
2552 }
2553
2554 static ssize_t
2555 i915_guc_log_relay_write(struct file *filp,
2556                          const char __user *ubuf,
2557                          size_t cnt,
2558                          loff_t *ppos)
2559 {
2560         struct intel_guc_log *log = filp->private_data;
2561
2562         intel_guc_log_relay_flush(log);
2563
2564         return cnt;
2565 }
2566
2567 static int i915_guc_log_relay_release(struct inode *inode, struct file *file)
2568 {
2569         struct drm_i915_private *dev_priv = inode->i_private;
2570
2571         intel_guc_log_relay_close(&dev_priv->guc.log);
2572
2573         return 0;
2574 }
2575
2576 static const struct file_operations i915_guc_log_relay_fops = {
2577         .owner = THIS_MODULE,
2578         .open = i915_guc_log_relay_open,
2579         .write = i915_guc_log_relay_write,
2580         .release = i915_guc_log_relay_release,
2581 };
2582
2583 static const char *psr2_live_status(u32 val)
2584 {
2585         static const char * const live_status[] = {
2586                 "IDLE",
2587                 "CAPTURE",
2588                 "CAPTURE_FS",
2589                 "SLEEP",
2590                 "BUFON_FW",
2591                 "ML_UP",
2592                 "SU_STANDBY",
2593                 "FAST_SLEEP",
2594                 "DEEP_SLEEP",
2595                 "BUF_ON",
2596                 "TG_ON"
2597         };
2598
2599         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2600         if (val < ARRAY_SIZE(live_status))
2601                 return live_status[val];
2602
2603         return "unknown";
2604 }
2605
2606 static int i915_edp_psr_status(struct seq_file *m, void *data)
2607 {
2608         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2609         u32 psrperf = 0;
2610         u32 stat[3];
2611         enum pipe pipe;
2612         bool enabled = false;
2613         bool sink_support;
2614
2615         if (!HAS_PSR(dev_priv))
2616                 return -ENODEV;
2617
2618         sink_support = dev_priv->psr.sink_support;
2619         seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
2620         if (!sink_support)
2621                 return 0;
2622
2623         intel_runtime_pm_get(dev_priv);
2624
2625         mutex_lock(&dev_priv->psr.lock);
2626         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2627         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2628                    dev_priv->psr.busy_frontbuffer_bits);
2629         seq_printf(m, "Re-enable work scheduled: %s\n",
2630                    yesno(work_busy(&dev_priv->psr.work.work)));
2631
2632         if (HAS_DDI(dev_priv)) {
2633                 if (dev_priv->psr.psr2_support)
2634                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2635                 else
2636                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2637         } else {
2638                 for_each_pipe(dev_priv, pipe) {
2639                         enum transcoder cpu_transcoder =
2640                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2641                         enum intel_display_power_domain power_domain;
2642
2643                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2644                         if (!intel_display_power_get_if_enabled(dev_priv,
2645                                                                 power_domain))
2646                                 continue;
2647
2648                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2649                                 VLV_EDP_PSR_CURR_STATE_MASK;
2650                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2651                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2652                                 enabled = true;
2653
2654                         intel_display_power_put(dev_priv, power_domain);
2655                 }
2656         }
2657
2658         seq_printf(m, "Main link in standby mode: %s\n",
2659                    yesno(dev_priv->psr.link_standby));
2660
2661         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2662
2663         if (!HAS_DDI(dev_priv))
2664                 for_each_pipe(dev_priv, pipe) {
2665                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2666                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2667                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2668                 }
2669         seq_puts(m, "\n");
2670
2671         /*
2672          * VLV/CHV PSR has no kind of performance counter
2673          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2674          */
2675         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2676                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2677                         EDP_PSR_PERF_CNT_MASK;
2678
2679                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2680         }
2681         if (dev_priv->psr.psr2_support) {
2682                 u32 psr2 = I915_READ(EDP_PSR2_STATUS);
2683
2684                 seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
2685                            psr2, psr2_live_status(psr2));
2686         }
2687         mutex_unlock(&dev_priv->psr.lock);
2688
2689         intel_runtime_pm_put(dev_priv);
2690         return 0;
2691 }
2692
2693 static int i915_sink_crc(struct seq_file *m, void *data)
2694 {
2695         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2696         struct drm_device *dev = &dev_priv->drm;
2697         struct intel_connector *connector;
2698         struct drm_connector_list_iter conn_iter;
2699         struct intel_dp *intel_dp = NULL;
2700         struct drm_modeset_acquire_ctx ctx;
2701         int ret;
2702         u8 crc[6];
2703
2704         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2705
2706         drm_connector_list_iter_begin(dev, &conn_iter);
2707
2708         for_each_intel_connector_iter(connector, &conn_iter) {
2709                 struct drm_crtc *crtc;
2710                 struct drm_connector_state *state;
2711                 struct intel_crtc_state *crtc_state;
2712
2713                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2714                         continue;
2715
2716 retry:
2717                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2718                 if (ret)
2719                         goto err;
2720
2721                 state = connector->base.state;
2722                 if (!state->best_encoder)
2723                         continue;
2724
2725                 crtc = state->crtc;
2726                 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2727                 if (ret)
2728                         goto err;
2729
2730                 crtc_state = to_intel_crtc_state(crtc->state);
2731                 if (!crtc_state->base.active)
2732                         continue;
2733
2734                 /*
2735                  * We need to wait for all crtc updates to complete, to make
2736                  * sure any pending modesets and plane updates are completed.
2737                  */
2738                 if (crtc_state->base.commit) {
2739                         ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
2740
2741                         if (ret)
2742                                 goto err;
2743                 }
2744
2745                 intel_dp = enc_to_intel_dp(state->best_encoder);
2746
2747                 ret = intel_dp_sink_crc(intel_dp, crtc_state, crc);
2748                 if (ret)
2749                         goto err;
2750
2751                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2752                            crc[0], crc[1], crc[2],
2753                            crc[3], crc[4], crc[5]);
2754                 goto out;
2755
2756 err:
2757                 if (ret == -EDEADLK) {
2758                         ret = drm_modeset_backoff(&ctx);
2759                         if (!ret)
2760                                 goto retry;
2761                 }
2762                 goto out;
2763         }
2764         ret = -ENODEV;
2765 out:
2766         drm_connector_list_iter_end(&conn_iter);
2767         drm_modeset_drop_locks(&ctx);
2768         drm_modeset_acquire_fini(&ctx);
2769
2770         return ret;
2771 }
2772
2773 static int i915_energy_uJ(struct seq_file *m, void *data)
2774 {
2775         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2776         unsigned long long power;
2777         u32 units;
2778
2779         if (INTEL_GEN(dev_priv) < 6)
2780                 return -ENODEV;
2781
2782         intel_runtime_pm_get(dev_priv);
2783
2784         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2785                 intel_runtime_pm_put(dev_priv);
2786                 return -ENODEV;
2787         }
2788
2789         units = (power & 0x1f00) >> 8;
2790         power = I915_READ(MCH_SECP_NRG_STTS);
2791         power = (1000000 * power) >> units; /* convert to uJ */
2792
2793         intel_runtime_pm_put(dev_priv);
2794
2795         seq_printf(m, "%llu", power);
2796
2797         return 0;
2798 }
2799
2800 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2801 {
2802         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2803         struct pci_dev *pdev = dev_priv->drm.pdev;
2804
2805         if (!HAS_RUNTIME_PM(dev_priv))
2806                 seq_puts(m, "Runtime power management not supported\n");
2807
2808         seq_printf(m, "GPU idle: %s (epoch %u)\n",
2809                    yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
2810         seq_printf(m, "IRQs disabled: %s\n",
2811                    yesno(!intel_irqs_enabled(dev_priv)));
2812 #ifdef CONFIG_PM
2813         seq_printf(m, "Usage count: %d\n",
2814                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2815 #else
2816         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2817 #endif
2818         seq_printf(m, "PCI device power state: %s [%d]\n",
2819                    pci_power_name(pdev->current_state),
2820                    pdev->current_state);
2821
2822         return 0;
2823 }
2824
2825 static int i915_power_domain_info(struct seq_file *m, void *unused)
2826 {
2827         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2828         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2829         int i;
2830
2831         mutex_lock(&power_domains->lock);
2832
2833         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2834         for (i = 0; i < power_domains->power_well_count; i++) {
2835                 struct i915_power_well *power_well;
2836                 enum intel_display_power_domain power_domain;
2837
2838                 power_well = &power_domains->power_wells[i];
2839                 seq_printf(m, "%-25s %d\n", power_well->name,
2840                            power_well->count);
2841
2842                 for_each_power_domain(power_domain, power_well->domains)
2843                         seq_printf(m, "  %-23s %d\n",
2844                                  intel_display_power_domain_str(power_domain),
2845                                  power_domains->domain_use_count[power_domain]);
2846         }
2847
2848         mutex_unlock(&power_domains->lock);
2849
2850         return 0;
2851 }
2852
2853 static int i915_dmc_info(struct seq_file *m, void *unused)
2854 {
2855         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2856         struct intel_csr *csr;
2857
2858         if (!HAS_CSR(dev_priv))
2859                 return -ENODEV;
2860
2861         csr = &dev_priv->csr;
2862
2863         intel_runtime_pm_get(dev_priv);
2864
2865         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2866         seq_printf(m, "path: %s\n", csr->fw_path);
2867
2868         if (!csr->dmc_payload)
2869                 goto out;
2870
2871         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2872                    CSR_VERSION_MINOR(csr->version));
2873
2874         if (IS_KABYLAKE(dev_priv) ||
2875             (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2876                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2877                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2878                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2879                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2880         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2881                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2882                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2883         }
2884
2885 out:
2886         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2887         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2888         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2889
2890         intel_runtime_pm_put(dev_priv);
2891
2892         return 0;
2893 }
2894
2895 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2896                                  struct drm_display_mode *mode)
2897 {
2898         int i;
2899
2900         for (i = 0; i < tabs; i++)
2901                 seq_putc(m, '\t');
2902
2903         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2904                    mode->base.id, mode->name,
2905                    mode->vrefresh, mode->clock,
2906                    mode->hdisplay, mode->hsync_start,
2907                    mode->hsync_end, mode->htotal,
2908                    mode->vdisplay, mode->vsync_start,
2909                    mode->vsync_end, mode->vtotal,
2910                    mode->type, mode->flags);
2911 }
2912
2913 static void intel_encoder_info(struct seq_file *m,
2914                                struct intel_crtc *intel_crtc,
2915                                struct intel_encoder *intel_encoder)
2916 {
2917         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2918         struct drm_device *dev = &dev_priv->drm;
2919         struct drm_crtc *crtc = &intel_crtc->base;
2920         struct intel_connector *intel_connector;
2921         struct drm_encoder *encoder;
2922
2923         encoder = &intel_encoder->base;
2924         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2925                    encoder->base.id, encoder->name);
2926         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2927                 struct drm_connector *connector = &intel_connector->base;
2928                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2929                            connector->base.id,
2930                            connector->name,
2931                            drm_get_connector_status_name(connector->status));
2932                 if (connector->status == connector_status_connected) {
2933                         struct drm_display_mode *mode = &crtc->mode;
2934                         seq_printf(m, ", mode:\n");
2935                         intel_seq_print_mode(m, 2, mode);
2936                 } else {
2937                         seq_putc(m, '\n');
2938                 }
2939         }
2940 }
2941
2942 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2943 {
2944         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2945         struct drm_device *dev = &dev_priv->drm;
2946         struct drm_crtc *crtc = &intel_crtc->base;
2947         struct intel_encoder *intel_encoder;
2948         struct drm_plane_state *plane_state = crtc->primary->state;
2949         struct drm_framebuffer *fb = plane_state->fb;
2950
2951         if (fb)
2952                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2953                            fb->base.id, plane_state->src_x >> 16,
2954                            plane_state->src_y >> 16, fb->width, fb->height);
2955         else
2956                 seq_puts(m, "\tprimary plane disabled\n");
2957         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2958                 intel_encoder_info(m, intel_crtc, intel_encoder);
2959 }
2960
2961 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2962 {
2963         struct drm_display_mode *mode = panel->fixed_mode;
2964
2965         seq_printf(m, "\tfixed mode:\n");
2966         intel_seq_print_mode(m, 2, mode);
2967 }
2968
2969 static void intel_dp_info(struct seq_file *m,
2970                           struct intel_connector *intel_connector)
2971 {
2972         struct intel_encoder *intel_encoder = intel_connector->encoder;
2973         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2974
2975         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2976         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2977         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2978                 intel_panel_info(m, &intel_connector->panel);
2979
2980         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2981                                 &intel_dp->aux);
2982 }
2983
2984 static void intel_dp_mst_info(struct seq_file *m,
2985                           struct intel_connector *intel_connector)
2986 {
2987         struct intel_encoder *intel_encoder = intel_connector->encoder;
2988         struct intel_dp_mst_encoder *intel_mst =
2989                 enc_to_mst(&intel_encoder->base);
2990         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2991         struct intel_dp *intel_dp = &intel_dig_port->dp;
2992         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2993                                         intel_connector->port);
2994
2995         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2996 }
2997
2998 static void intel_hdmi_info(struct seq_file *m,
2999                             struct intel_connector *intel_connector)
3000 {
3001         struct intel_encoder *intel_encoder = intel_connector->encoder;
3002         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3003
3004         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3005 }
3006
3007 static void intel_lvds_info(struct seq_file *m,
3008                             struct intel_connector *intel_connector)
3009 {
3010         intel_panel_info(m, &intel_connector->panel);
3011 }
3012
3013 static void intel_connector_info(struct seq_file *m,
3014                                  struct drm_connector *connector)
3015 {
3016         struct intel_connector *intel_connector = to_intel_connector(connector);
3017         struct intel_encoder *intel_encoder = intel_connector->encoder;
3018         struct drm_display_mode *mode;
3019
3020         seq_printf(m, "connector %d: type %s, status: %s\n",
3021                    connector->base.id, connector->name,
3022                    drm_get_connector_status_name(connector->status));
3023         if (connector->status == connector_status_connected) {
3024                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3025                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3026                            connector->display_info.width_mm,
3027                            connector->display_info.height_mm);
3028                 seq_printf(m, "\tsubpixel order: %s\n",
3029                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3030                 seq_printf(m, "\tCEA rev: %d\n",
3031                            connector->display_info.cea_rev);
3032         }
3033
3034         if (!intel_encoder)
3035                 return;
3036
3037         switch (connector->connector_type) {
3038         case DRM_MODE_CONNECTOR_DisplayPort:
3039         case DRM_MODE_CONNECTOR_eDP:
3040                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3041                         intel_dp_mst_info(m, intel_connector);
3042                 else
3043                         intel_dp_info(m, intel_connector);
3044                 break;
3045         case DRM_MODE_CONNECTOR_LVDS:
3046                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3047                         intel_lvds_info(m, intel_connector);
3048                 break;
3049         case DRM_MODE_CONNECTOR_HDMIA:
3050                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3051                     intel_encoder->type == INTEL_OUTPUT_DDI)
3052                         intel_hdmi_info(m, intel_connector);
3053                 break;
3054         default:
3055                 break;
3056         }
3057
3058         seq_printf(m, "\tmodes:\n");
3059         list_for_each_entry(mode, &connector->modes, head)
3060                 intel_seq_print_mode(m, 2, mode);
3061 }
3062
3063 static const char *plane_type(enum drm_plane_type type)
3064 {
3065         switch (type) {
3066         case DRM_PLANE_TYPE_OVERLAY:
3067                 return "OVL";
3068         case DRM_PLANE_TYPE_PRIMARY:
3069                 return "PRI";
3070         case DRM_PLANE_TYPE_CURSOR:
3071                 return "CUR";
3072         /*
3073          * Deliberately omitting default: to generate compiler warnings
3074          * when a new drm_plane_type gets added.
3075          */
3076         }
3077
3078         return "unknown";
3079 }
3080
3081 static const char *plane_rotation(unsigned int rotation)
3082 {
3083         static char buf[48];
3084         /*
3085          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3086          * will print them all to visualize if the values are misused
3087          */
3088         snprintf(buf, sizeof(buf),
3089                  "%s%s%s%s%s%s(0x%08x)",
3090                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3091                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3092                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3093                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3094                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3095                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3096                  rotation);
3097
3098         return buf;
3099 }
3100
3101 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3102 {
3103         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3104         struct drm_device *dev = &dev_priv->drm;
3105         struct intel_plane *intel_plane;
3106
3107         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3108                 struct drm_plane_state *state;
3109                 struct drm_plane *plane = &intel_plane->base;
3110                 struct drm_format_name_buf format_name;
3111
3112                 if (!plane->state) {
3113                         seq_puts(m, "plane->state is NULL!\n");
3114                         continue;
3115                 }
3116
3117                 state = plane->state;
3118
3119                 if (state->fb) {
3120                         drm_get_format_name(state->fb->format->format,
3121                                             &format_name);
3122                 } else {
3123                         sprintf(format_name.str, "N/A");
3124                 }
3125
3126                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3127                            plane->base.id,
3128                            plane_type(intel_plane->base.type),
3129                            state->crtc_x, state->crtc_y,
3130                            state->crtc_w, state->crtc_h,
3131                            (state->src_x >> 16),
3132                            ((state->src_x & 0xffff) * 15625) >> 10,
3133                            (state->src_y >> 16),
3134                            ((state->src_y & 0xffff) * 15625) >> 10,
3135                            (state->src_w >> 16),
3136                            ((state->src_w & 0xffff) * 15625) >> 10,
3137                            (state->src_h >> 16),
3138                            ((state->src_h & 0xffff) * 15625) >> 10,
3139                            format_name.str,
3140                            plane_rotation(state->rotation));
3141         }
3142 }
3143
3144 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3145 {
3146         struct intel_crtc_state *pipe_config;
3147         int num_scalers = intel_crtc->num_scalers;
3148         int i;
3149
3150         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3151
3152         /* Not all platformas have a scaler */
3153         if (num_scalers) {
3154                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3155                            num_scalers,
3156                            pipe_config->scaler_state.scaler_users,
3157                            pipe_config->scaler_state.scaler_id);
3158
3159                 for (i = 0; i < num_scalers; i++) {
3160                         struct intel_scaler *sc =
3161                                         &pipe_config->scaler_state.scalers[i];
3162
3163                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3164                                    i, yesno(sc->in_use), sc->mode);
3165                 }
3166                 seq_puts(m, "\n");
3167         } else {
3168                 seq_puts(m, "\tNo scalers available on this platform\n");
3169         }
3170 }
3171
3172 static int i915_display_info(struct seq_file *m, void *unused)
3173 {
3174         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3175         struct drm_device *dev = &dev_priv->drm;
3176         struct intel_crtc *crtc;
3177         struct drm_connector *connector;
3178         struct drm_connector_list_iter conn_iter;
3179
3180         intel_runtime_pm_get(dev_priv);
3181         seq_printf(m, "CRTC info\n");
3182         seq_printf(m, "---------\n");
3183         for_each_intel_crtc(dev, crtc) {
3184                 struct intel_crtc_state *pipe_config;
3185
3186                 drm_modeset_lock(&crtc->base.mutex, NULL);
3187                 pipe_config = to_intel_crtc_state(crtc->base.state);
3188
3189                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3190                            crtc->base.base.id, pipe_name(crtc->pipe),
3191                            yesno(pipe_config->base.active),
3192                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3193                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3194
3195                 if (pipe_config->base.active) {
3196                         struct intel_plane *cursor =
3197                                 to_intel_plane(crtc->base.cursor);
3198
3199                         intel_crtc_info(m, crtc);
3200
3201                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3202                                    yesno(cursor->base.state->visible),
3203                                    cursor->base.state->crtc_x,
3204                                    cursor->base.state->crtc_y,
3205                                    cursor->base.state->crtc_w,
3206                                    cursor->base.state->crtc_h,
3207                                    cursor->cursor.base);
3208                         intel_scaler_info(m, crtc);
3209                         intel_plane_info(m, crtc);
3210                 }
3211
3212                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3213                            yesno(!crtc->cpu_fifo_underrun_disabled),
3214                            yesno(!crtc->pch_fifo_underrun_disabled));
3215                 drm_modeset_unlock(&crtc->base.mutex);
3216         }
3217
3218         seq_printf(m, "\n");
3219         seq_printf(m, "Connector info\n");
3220         seq_printf(m, "--------------\n");
3221         mutex_lock(&dev->mode_config.mutex);
3222         drm_connector_list_iter_begin(dev, &conn_iter);
3223         drm_for_each_connector_iter(connector, &conn_iter)
3224                 intel_connector_info(m, connector);
3225         drm_connector_list_iter_end(&conn_iter);
3226         mutex_unlock(&dev->mode_config.mutex);
3227
3228         intel_runtime_pm_put(dev_priv);
3229
3230         return 0;
3231 }
3232
3233 static int i915_engine_info(struct seq_file *m, void *unused)
3234 {
3235         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3236         struct intel_engine_cs *engine;
3237         enum intel_engine_id id;
3238         struct drm_printer p;
3239
3240         intel_runtime_pm_get(dev_priv);
3241
3242         seq_printf(m, "GT awake? %s (epoch %u)\n",
3243                    yesno(dev_priv->gt.awake), dev_priv->gt.epoch);
3244         seq_printf(m, "Global active requests: %d\n",
3245                    dev_priv->gt.active_requests);
3246         seq_printf(m, "CS timestamp frequency: %u kHz\n",
3247                    dev_priv->info.cs_timestamp_frequency_khz);
3248
3249         p = drm_seq_file_printer(m);
3250         for_each_engine(engine, dev_priv, id)
3251                 intel_engine_dump(engine, &p, "%s\n", engine->name);
3252
3253         intel_runtime_pm_put(dev_priv);
3254
3255         return 0;
3256 }
3257
3258 static int i915_rcs_topology(struct seq_file *m, void *unused)
3259 {
3260         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3261         struct drm_printer p = drm_seq_file_printer(m);
3262
3263         intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
3264
3265         return 0;
3266 }
3267
3268 static int i915_shrinker_info(struct seq_file *m, void *unused)
3269 {
3270         struct drm_i915_private *i915 = node_to_i915(m->private);
3271
3272         seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3273         seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3274
3275         return 0;
3276 }
3277
3278 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3279 {
3280         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3281         struct drm_device *dev = &dev_priv->drm;
3282         int i;
3283
3284         drm_modeset_lock_all(dev);
3285         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3286                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3287
3288                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3289                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3290                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3291                 seq_printf(m, " tracked hardware state:\n");
3292                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3293                 seq_printf(m, " dpll_md: 0x%08x\n",
3294                            pll->state.hw_state.dpll_md);
3295                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3296                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3297                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3298         }
3299         drm_modeset_unlock_all(dev);
3300
3301         return 0;
3302 }
3303
3304 static int i915_wa_registers(struct seq_file *m, void *unused)
3305 {
3306         int i;
3307         int ret;
3308         struct intel_engine_cs *engine;
3309         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3310         struct drm_device *dev = &dev_priv->drm;
3311         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3312         enum intel_engine_id id;
3313
3314         ret = mutex_lock_interruptible(&dev->struct_mutex);
3315         if (ret)
3316                 return ret;
3317
3318         intel_runtime_pm_get(dev_priv);
3319
3320         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3321         for_each_engine(engine, dev_priv, id)
3322                 seq_printf(m, "HW whitelist count for %s: %d\n",
3323                            engine->name, workarounds->hw_whitelist_count[id]);
3324         for (i = 0; i < workarounds->count; ++i) {
3325                 i915_reg_t addr;
3326                 u32 mask, value, read;
3327                 bool ok;
3328
3329                 addr = workarounds->reg[i].addr;
3330                 mask = workarounds->reg[i].mask;
3331                 value = workarounds->reg[i].value;
3332                 read = I915_READ(addr);
3333                 ok = (value & mask) == (read & mask);
3334                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3335                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3336         }
3337
3338         intel_runtime_pm_put(dev_priv);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         return 0;
3342 }
3343
3344 static int i915_ipc_status_show(struct seq_file *m, void *data)
3345 {
3346         struct drm_i915_private *dev_priv = m->private;
3347
3348         seq_printf(m, "Isochronous Priority Control: %s\n",
3349                         yesno(dev_priv->ipc_enabled));
3350         return 0;
3351 }
3352
3353 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3354 {
3355         struct drm_i915_private *dev_priv = inode->i_private;
3356
3357         if (!HAS_IPC(dev_priv))
3358                 return -ENODEV;
3359
3360         return single_open(file, i915_ipc_status_show, dev_priv);
3361 }
3362
3363 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3364                                      size_t len, loff_t *offp)
3365 {
3366         struct seq_file *m = file->private_data;
3367         struct drm_i915_private *dev_priv = m->private;
3368         int ret;
3369         bool enable;
3370
3371         ret = kstrtobool_from_user(ubuf, len, &enable);
3372         if (ret < 0)
3373                 return ret;
3374
3375         intel_runtime_pm_get(dev_priv);
3376         if (!dev_priv->ipc_enabled && enable)
3377                 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3378         dev_priv->wm.distrust_bios_wm = true;
3379         dev_priv->ipc_enabled = enable;
3380         intel_enable_ipc(dev_priv);
3381         intel_runtime_pm_put(dev_priv);
3382
3383         return len;
3384 }
3385
3386 static const struct file_operations i915_ipc_status_fops = {
3387         .owner = THIS_MODULE,
3388         .open = i915_ipc_status_open,
3389         .read = seq_read,
3390         .llseek = seq_lseek,
3391         .release = single_release,
3392         .write = i915_ipc_status_write
3393 };
3394
3395 static int i915_ddb_info(struct seq_file *m, void *unused)
3396 {
3397         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3398         struct drm_device *dev = &dev_priv->drm;
3399         struct skl_ddb_allocation *ddb;
3400         struct skl_ddb_entry *entry;
3401         enum pipe pipe;
3402         int plane;
3403
3404         if (INTEL_GEN(dev_priv) < 9)
3405                 return -ENODEV;
3406
3407         drm_modeset_lock_all(dev);
3408
3409         ddb = &dev_priv->wm.skl_hw.ddb;
3410
3411         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3412
3413         for_each_pipe(dev_priv, pipe) {
3414                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3415
3416                 for_each_universal_plane(dev_priv, pipe, plane) {
3417                         entry = &ddb->plane[pipe][plane];
3418                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3419                                    entry->start, entry->end,
3420                                    skl_ddb_entry_size(entry));
3421                 }
3422
3423                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3424                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3425                            entry->end, skl_ddb_entry_size(entry));
3426         }
3427
3428         drm_modeset_unlock_all(dev);
3429
3430         return 0;
3431 }
3432
3433 static void drrs_status_per_crtc(struct seq_file *m,
3434                                  struct drm_device *dev,
3435                                  struct intel_crtc *intel_crtc)
3436 {
3437         struct drm_i915_private *dev_priv = to_i915(dev);
3438         struct i915_drrs *drrs = &dev_priv->drrs;
3439         int vrefresh = 0;
3440         struct drm_connector *connector;
3441         struct drm_connector_list_iter conn_iter;
3442
3443         drm_connector_list_iter_begin(dev, &conn_iter);
3444         drm_for_each_connector_iter(connector, &conn_iter) {
3445                 if (connector->state->crtc != &intel_crtc->base)
3446                         continue;
3447
3448                 seq_printf(m, "%s:\n", connector->name);
3449         }
3450         drm_connector_list_iter_end(&conn_iter);
3451
3452         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3453                 seq_puts(m, "\tVBT: DRRS_type: Static");
3454         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3455                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3456         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3457                 seq_puts(m, "\tVBT: DRRS_type: None");
3458         else
3459                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3460
3461         seq_puts(m, "\n\n");
3462
3463         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3464                 struct intel_panel *panel;
3465
3466                 mutex_lock(&drrs->mutex);
3467                 /* DRRS Supported */
3468                 seq_puts(m, "\tDRRS Supported: Yes\n");
3469
3470                 /* disable_drrs() will make drrs->dp NULL */
3471                 if (!drrs->dp) {
3472                         seq_puts(m, "Idleness DRRS: Disabled\n");
3473                         if (dev_priv->psr.enabled)
3474                                 seq_puts(m,
3475                                 "\tAs PSR is enabled, DRRS is not enabled\n");
3476                         mutex_unlock(&drrs->mutex);
3477                         return;
3478                 }
3479
3480                 panel = &drrs->dp->attached_connector->panel;
3481                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3482                                         drrs->busy_frontbuffer_bits);
3483
3484                 seq_puts(m, "\n\t\t");
3485                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3486                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3487                         vrefresh = panel->fixed_mode->vrefresh;
3488                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3489                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3490                         vrefresh = panel->downclock_mode->vrefresh;
3491                 } else {
3492                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3493                                                 drrs->refresh_rate_type);
3494                         mutex_unlock(&drrs->mutex);
3495                         return;
3496                 }
3497                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3498
3499                 seq_puts(m, "\n\t\t");
3500                 mutex_unlock(&drrs->mutex);
3501         } else {
3502                 /* DRRS not supported. Print the VBT parameter*/
3503                 seq_puts(m, "\tDRRS Supported : No");
3504         }
3505         seq_puts(m, "\n");
3506 }
3507
3508 static int i915_drrs_status(struct seq_file *m, void *unused)
3509 {
3510         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3511         struct drm_device *dev = &dev_priv->drm;
3512         struct intel_crtc *intel_crtc;
3513         int active_crtc_cnt = 0;
3514
3515         drm_modeset_lock_all(dev);
3516         for_each_intel_crtc(dev, intel_crtc) {
3517                 if (intel_crtc->base.state->active) {
3518                         active_crtc_cnt++;
3519                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3520
3521                         drrs_status_per_crtc(m, dev, intel_crtc);
3522                 }
3523         }
3524         drm_modeset_unlock_all(dev);
3525
3526         if (!active_crtc_cnt)
3527                 seq_puts(m, "No active crtc found\n");
3528
3529         return 0;
3530 }
3531
3532 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3533 {
3534         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3535         struct drm_device *dev = &dev_priv->drm;
3536         struct intel_encoder *intel_encoder;
3537         struct intel_digital_port *intel_dig_port;
3538         struct drm_connector *connector;
3539         struct drm_connector_list_iter conn_iter;
3540
3541         drm_connector_list_iter_begin(dev, &conn_iter);
3542         drm_for_each_connector_iter(connector, &conn_iter) {
3543                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3544                         continue;
3545
3546                 intel_encoder = intel_attached_encoder(connector);
3547                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3548                         continue;
3549
3550                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3551                 if (!intel_dig_port->dp.can_mst)
3552                         continue;
3553
3554                 seq_printf(m, "MST Source Port %c\n",
3555                            port_name(intel_dig_port->base.port));
3556                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3557         }
3558         drm_connector_list_iter_end(&conn_iter);
3559
3560         return 0;
3561 }
3562
3563 static ssize_t i915_displayport_test_active_write(struct file *file,
3564                                                   const char __user *ubuf,
3565                                                   size_t len, loff_t *offp)
3566 {
3567         char *input_buffer;
3568         int status = 0;
3569         struct drm_device *dev;
3570         struct drm_connector *connector;
3571         struct drm_connector_list_iter conn_iter;
3572         struct intel_dp *intel_dp;
3573         int val = 0;
3574
3575         dev = ((struct seq_file *)file->private_data)->private;
3576
3577         if (len == 0)
3578                 return 0;
3579
3580         input_buffer = memdup_user_nul(ubuf, len);
3581         if (IS_ERR(input_buffer))
3582                 return PTR_ERR(input_buffer);
3583
3584         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3585
3586         drm_connector_list_iter_begin(dev, &conn_iter);
3587         drm_for_each_connector_iter(connector, &conn_iter) {
3588                 struct intel_encoder *encoder;
3589
3590                 if (connector->connector_type !=
3591                     DRM_MODE_CONNECTOR_DisplayPort)
3592                         continue;
3593
3594                 encoder = to_intel_encoder(connector->encoder);
3595                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3596                         continue;
3597
3598                 if (encoder && connector->status == connector_status_connected) {
3599                         intel_dp = enc_to_intel_dp(&encoder->base);
3600                         status = kstrtoint(input_buffer, 10, &val);
3601                         if (status < 0)
3602                                 break;
3603                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3604                         /* To prevent erroneous activation of the compliance
3605                          * testing code, only accept an actual value of 1 here
3606                          */
3607                         if (val == 1)
3608                                 intel_dp->compliance.test_active = 1;
3609                         else
3610                                 intel_dp->compliance.test_active = 0;
3611                 }
3612         }
3613         drm_connector_list_iter_end(&conn_iter);
3614         kfree(input_buffer);
3615         if (status < 0)
3616                 return status;
3617
3618         *offp += len;
3619         return len;
3620 }
3621
3622 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3623 {
3624         struct drm_i915_private *dev_priv = m->private;
3625         struct drm_device *dev = &dev_priv->drm;
3626         struct drm_connector *connector;
3627         struct drm_connector_list_iter conn_iter;
3628         struct intel_dp *intel_dp;
3629
3630         drm_connector_list_iter_begin(dev, &conn_iter);
3631         drm_for_each_connector_iter(connector, &conn_iter) {
3632                 struct intel_encoder *encoder;
3633
3634                 if (connector->connector_type !=
3635                     DRM_MODE_CONNECTOR_DisplayPort)
3636                         continue;
3637
3638                 encoder = to_intel_encoder(connector->encoder);
3639                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3640                         continue;
3641
3642                 if (encoder && connector->status == connector_status_connected) {
3643                         intel_dp = enc_to_intel_dp(&encoder->base);
3644                         if (intel_dp->compliance.test_active)
3645                                 seq_puts(m, "1");
3646                         else
3647                                 seq_puts(m, "0");
3648                 } else
3649                         seq_puts(m, "0");
3650         }
3651         drm_connector_list_iter_end(&conn_iter);
3652
3653         return 0;
3654 }
3655
3656 static int i915_displayport_test_active_open(struct inode *inode,
3657                                              struct file *file)
3658 {
3659         return single_open(file, i915_displayport_test_active_show,
3660                            inode->i_private);
3661 }
3662
3663 static const struct file_operations i915_displayport_test_active_fops = {
3664         .owner = THIS_MODULE,
3665         .open = i915_displayport_test_active_open,
3666         .read = seq_read,
3667         .llseek = seq_lseek,
3668         .release = single_release,
3669         .write = i915_displayport_test_active_write
3670 };
3671
3672 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3673 {
3674         struct drm_i915_private *dev_priv = m->private;
3675         struct drm_device *dev = &dev_priv->drm;
3676         struct drm_connector *connector;
3677         struct drm_connector_list_iter conn_iter;
3678         struct intel_dp *intel_dp;
3679
3680         drm_connector_list_iter_begin(dev, &conn_iter);
3681         drm_for_each_connector_iter(connector, &conn_iter) {
3682                 struct intel_encoder *encoder;
3683
3684                 if (connector->connector_type !=
3685                     DRM_MODE_CONNECTOR_DisplayPort)
3686                         continue;
3687
3688                 encoder = to_intel_encoder(connector->encoder);
3689                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3690                         continue;
3691
3692                 if (encoder && connector->status == connector_status_connected) {
3693                         intel_dp = enc_to_intel_dp(&encoder->base);
3694                         if (intel_dp->compliance.test_type ==
3695                             DP_TEST_LINK_EDID_READ)
3696                                 seq_printf(m, "%lx",
3697                                            intel_dp->compliance.test_data.edid);
3698                         else if (intel_dp->compliance.test_type ==
3699                                  DP_TEST_LINK_VIDEO_PATTERN) {
3700                                 seq_printf(m, "hdisplay: %d\n",
3701                                            intel_dp->compliance.test_data.hdisplay);
3702                                 seq_printf(m, "vdisplay: %d\n",
3703                                            intel_dp->compliance.test_data.vdisplay);
3704                                 seq_printf(m, "bpc: %u\n",
3705                                            intel_dp->compliance.test_data.bpc);
3706                         }
3707                 } else
3708                         seq_puts(m, "0");
3709         }
3710         drm_connector_list_iter_end(&conn_iter);
3711
3712         return 0;
3713 }
3714 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
3715
3716 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3717 {
3718         struct drm_i915_private *dev_priv = m->private;
3719         struct drm_device *dev = &dev_priv->drm;
3720         struct drm_connector *connector;
3721         struct drm_connector_list_iter conn_iter;
3722         struct intel_dp *intel_dp;
3723
3724         drm_connector_list_iter_begin(dev, &conn_iter);
3725         drm_for_each_connector_iter(connector, &conn_iter) {
3726                 struct intel_encoder *encoder;
3727
3728                 if (connector->connector_type !=
3729                     DRM_MODE_CONNECTOR_DisplayPort)
3730                         continue;
3731
3732                 encoder = to_intel_encoder(connector->encoder);
3733                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3734                         continue;
3735
3736                 if (encoder && connector->status == connector_status_connected) {
3737                         intel_dp = enc_to_intel_dp(&encoder->base);
3738                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3739                 } else
3740                         seq_puts(m, "0");
3741         }
3742         drm_connector_list_iter_end(&conn_iter);
3743
3744         return 0;
3745 }
3746 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
3747
3748 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3749 {
3750         struct drm_i915_private *dev_priv = m->private;
3751         struct drm_device *dev = &dev_priv->drm;
3752         int level;
3753         int num_levels;
3754
3755         if (IS_CHERRYVIEW(dev_priv))
3756                 num_levels = 3;
3757         else if (IS_VALLEYVIEW(dev_priv))
3758                 num_levels = 1;
3759         else if (IS_G4X(dev_priv))
3760                 num_levels = 3;
3761         else
3762                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3763
3764         drm_modeset_lock_all(dev);
3765
3766         for (level = 0; level < num_levels; level++) {
3767                 unsigned int latency = wm[level];
3768
3769                 /*
3770                  * - WM1+ latency values in 0.5us units
3771                  * - latencies are in us on gen9/vlv/chv
3772                  */
3773                 if (INTEL_GEN(dev_priv) >= 9 ||
3774                     IS_VALLEYVIEW(dev_priv) ||
3775                     IS_CHERRYVIEW(dev_priv) ||
3776                     IS_G4X(dev_priv))
3777                         latency *= 10;
3778                 else if (level > 0)
3779                         latency *= 5;
3780
3781                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3782                            level, wm[level], latency / 10, latency % 10);
3783         }
3784
3785         drm_modeset_unlock_all(dev);
3786 }
3787
3788 static int pri_wm_latency_show(struct seq_file *m, void *data)
3789 {
3790         struct drm_i915_private *dev_priv = m->private;
3791         const uint16_t *latencies;
3792
3793         if (INTEL_GEN(dev_priv) >= 9)
3794                 latencies = dev_priv->wm.skl_latency;
3795         else
3796                 latencies = dev_priv->wm.pri_latency;
3797
3798         wm_latency_show(m, latencies);
3799
3800         return 0;
3801 }
3802
3803 static int spr_wm_latency_show(struct seq_file *m, void *data)
3804 {
3805         struct drm_i915_private *dev_priv = m->private;
3806         const uint16_t *latencies;
3807
3808         if (INTEL_GEN(dev_priv) >= 9)
3809                 latencies = dev_priv->wm.skl_latency;
3810         else
3811                 latencies = dev_priv->wm.spr_latency;
3812
3813         wm_latency_show(m, latencies);
3814
3815         return 0;
3816 }
3817
3818 static int cur_wm_latency_show(struct seq_file *m, void *data)
3819 {
3820         struct drm_i915_private *dev_priv = m->private;
3821         const uint16_t *latencies;
3822
3823         if (INTEL_GEN(dev_priv) >= 9)
3824                 latencies = dev_priv->wm.skl_latency;
3825         else
3826                 latencies = dev_priv->wm.cur_latency;
3827
3828         wm_latency_show(m, latencies);
3829
3830         return 0;
3831 }
3832
3833 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3834 {
3835         struct drm_i915_private *dev_priv = inode->i_private;
3836
3837         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3838                 return -ENODEV;
3839
3840         return single_open(file, pri_wm_latency_show, dev_priv);
3841 }
3842
3843 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3844 {
3845         struct drm_i915_private *dev_priv = inode->i_private;
3846
3847         if (HAS_GMCH_DISPLAY(dev_priv))
3848                 return -ENODEV;
3849
3850         return single_open(file, spr_wm_latency_show, dev_priv);
3851 }
3852
3853 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3854 {
3855         struct drm_i915_private *dev_priv = inode->i_private;
3856
3857         if (HAS_GMCH_DISPLAY(dev_priv))
3858                 return -ENODEV;
3859
3860         return single_open(file, cur_wm_latency_show, dev_priv);
3861 }
3862
3863 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3864                                 size_t len, loff_t *offp, uint16_t wm[8])
3865 {
3866         struct seq_file *m = file->private_data;
3867         struct drm_i915_private *dev_priv = m->private;
3868         struct drm_device *dev = &dev_priv->drm;
3869         uint16_t new[8] = { 0 };
3870         int num_levels;
3871         int level;
3872         int ret;
3873         char tmp[32];
3874
3875         if (IS_CHERRYVIEW(dev_priv))
3876                 num_levels = 3;
3877         else if (IS_VALLEYVIEW(dev_priv))
3878                 num_levels = 1;
3879         else if (IS_G4X(dev_priv))
3880                 num_levels = 3;
3881         else
3882                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3883
3884         if (len >= sizeof(tmp))
3885                 return -EINVAL;
3886
3887         if (copy_from_user(tmp, ubuf, len))
3888                 return -EFAULT;
3889
3890         tmp[len] = '\0';
3891
3892         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3893                      &new[0], &new[1], &new[2], &new[3],
3894                      &new[4], &new[5], &new[6], &new[7]);
3895         if (ret != num_levels)
3896                 return -EINVAL;
3897
3898         drm_modeset_lock_all(dev);
3899
3900         for (level = 0; level < num_levels; level++)
3901                 wm[level] = new[level];
3902
3903         drm_modeset_unlock_all(dev);
3904
3905         return len;
3906 }
3907
3908
3909 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3910                                     size_t len, loff_t *offp)
3911 {
3912         struct seq_file *m = file->private_data;
3913         struct drm_i915_private *dev_priv = m->private;
3914         uint16_t *latencies;
3915
3916         if (INTEL_GEN(dev_priv) >= 9)
3917                 latencies = dev_priv->wm.skl_latency;
3918         else
3919                 latencies = dev_priv->wm.pri_latency;
3920
3921         return wm_latency_write(file, ubuf, len, offp, latencies);
3922 }
3923
3924 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3925                                     size_t len, loff_t *offp)
3926 {
3927         struct seq_file *m = file->private_data;
3928         struct drm_i915_private *dev_priv = m->private;
3929         uint16_t *latencies;
3930
3931         if (INTEL_GEN(dev_priv) >= 9)
3932                 latencies = dev_priv->wm.skl_latency;
3933         else
3934                 latencies = dev_priv->wm.spr_latency;
3935
3936         return wm_latency_write(file, ubuf, len, offp, latencies);
3937 }
3938
3939 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3940                                     size_t len, loff_t *offp)
3941 {
3942         struct seq_file *m = file->private_data;
3943         struct drm_i915_private *dev_priv = m->private;
3944         uint16_t *latencies;
3945
3946         if (INTEL_GEN(dev_priv) >= 9)
3947                 latencies = dev_priv->wm.skl_latency;
3948         else
3949                 latencies = dev_priv->wm.cur_latency;
3950
3951         return wm_latency_write(file, ubuf, len, offp, latencies);
3952 }
3953
3954 static const struct file_operations i915_pri_wm_latency_fops = {
3955         .owner = THIS_MODULE,
3956         .open = pri_wm_latency_open,
3957         .read = seq_read,
3958         .llseek = seq_lseek,
3959         .release = single_release,
3960         .write = pri_wm_latency_write
3961 };
3962
3963 static const struct file_operations i915_spr_wm_latency_fops = {
3964         .owner = THIS_MODULE,
3965         .open = spr_wm_latency_open,
3966         .read = seq_read,
3967         .llseek = seq_lseek,
3968         .release = single_release,
3969         .write = spr_wm_latency_write
3970 };
3971
3972 static const struct file_operations i915_cur_wm_latency_fops = {
3973         .owner = THIS_MODULE,
3974         .open = cur_wm_latency_open,
3975         .read = seq_read,
3976         .llseek = seq_lseek,
3977         .release = single_release,
3978         .write = cur_wm_latency_write
3979 };
3980
3981 static int
3982 i915_wedged_get(void *data, u64 *val)
3983 {
3984         struct drm_i915_private *dev_priv = data;
3985
3986         *val = i915_terminally_wedged(&dev_priv->gpu_error);
3987
3988         return 0;
3989 }
3990
3991 static int
3992 i915_wedged_set(void *data, u64 val)
3993 {
3994         struct drm_i915_private *i915 = data;
3995         struct intel_engine_cs *engine;
3996         unsigned int tmp;
3997
3998         /*
3999          * There is no safeguard against this debugfs entry colliding
4000          * with the hangcheck calling same i915_handle_error() in
4001          * parallel, causing an explosion. For now we assume that the
4002          * test harness is responsible enough not to inject gpu hangs
4003          * while it is writing to 'i915_wedged'
4004          */
4005
4006         if (i915_reset_backoff(&i915->gpu_error))
4007                 return -EAGAIN;
4008
4009         for_each_engine_masked(engine, i915, val, tmp) {
4010                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4011                 engine->hangcheck.stalled = true;
4012         }
4013
4014         i915_handle_error(i915, val, I915_ERROR_CAPTURE,
4015                           "Manually set wedged engine mask = %llx", val);
4016
4017         wait_on_bit(&i915->gpu_error.flags,
4018                     I915_RESET_HANDOFF,
4019                     TASK_UNINTERRUPTIBLE);
4020
4021         return 0;
4022 }
4023
4024 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4025                         i915_wedged_get, i915_wedged_set,
4026                         "%llu\n");
4027
4028 static int
4029 fault_irq_set(struct drm_i915_private *i915,
4030               unsigned long *irq,
4031               unsigned long val)
4032 {
4033         int err;
4034
4035         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4036         if (err)
4037                 return err;
4038
4039         err = i915_gem_wait_for_idle(i915,
4040                                      I915_WAIT_LOCKED |
4041                                      I915_WAIT_INTERRUPTIBLE);
4042         if (err)
4043                 goto err_unlock;
4044
4045         *irq = val;
4046         mutex_unlock(&i915->drm.struct_mutex);
4047
4048         /* Flush idle worker to disarm irq */
4049         drain_delayed_work(&i915->gt.idle_work);
4050
4051         return 0;
4052
4053 err_unlock:
4054         mutex_unlock(&i915->drm.struct_mutex);
4055         return err;
4056 }
4057
4058 static int
4059 i915_ring_missed_irq_get(void *data, u64 *val)
4060 {
4061         struct drm_i915_private *dev_priv = data;
4062
4063         *val = dev_priv->gpu_error.missed_irq_rings;
4064         return 0;
4065 }
4066
4067 static int
4068 i915_ring_missed_irq_set(void *data, u64 val)
4069 {
4070         struct drm_i915_private *i915 = data;
4071
4072         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4073 }
4074
4075 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4076                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4077                         "0x%08llx\n");
4078
4079 static int
4080 i915_ring_test_irq_get(void *data, u64 *val)
4081 {
4082         struct drm_i915_private *dev_priv = data;
4083
4084         *val = dev_priv->gpu_error.test_irq_rings;
4085
4086         return 0;
4087 }
4088
4089 static int
4090 i915_ring_test_irq_set(void *data, u64 val)
4091 {
4092         struct drm_i915_private *i915 = data;
4093
4094         val &= INTEL_INFO(i915)->ring_mask;
4095         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4096
4097         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4098 }
4099
4100 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4101                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4102                         "0x%08llx\n");
4103
4104 #define DROP_UNBOUND    BIT(0)
4105 #define DROP_BOUND      BIT(1)
4106 #define DROP_RETIRE     BIT(2)
4107 #define DROP_ACTIVE     BIT(3)
4108 #define DROP_FREED      BIT(4)
4109 #define DROP_SHRINK_ALL BIT(5)
4110 #define DROP_IDLE       BIT(6)
4111 #define DROP_ALL (DROP_UNBOUND  | \
4112                   DROP_BOUND    | \
4113                   DROP_RETIRE   | \
4114                   DROP_ACTIVE   | \
4115                   DROP_FREED    | \
4116                   DROP_SHRINK_ALL |\
4117                   DROP_IDLE)
4118 static int
4119 i915_drop_caches_get(void *data, u64 *val)
4120 {
4121         *val = DROP_ALL;
4122
4123         return 0;
4124 }
4125
4126 static int
4127 i915_drop_caches_set(void *data, u64 val)
4128 {
4129         struct drm_i915_private *dev_priv = data;
4130         struct drm_device *dev = &dev_priv->drm;
4131         int ret = 0;
4132
4133         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4134                   val, val & DROP_ALL);
4135
4136         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4137          * on ioctls on -EAGAIN. */
4138         if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4139                 ret = mutex_lock_interruptible(&dev->struct_mutex);
4140                 if (ret)
4141                         return ret;
4142
4143                 if (val & DROP_ACTIVE)
4144                         ret = i915_gem_wait_for_idle(dev_priv,
4145                                                      I915_WAIT_INTERRUPTIBLE |
4146                                                      I915_WAIT_LOCKED);
4147
4148                 if (val & DROP_RETIRE)
4149                         i915_retire_requests(dev_priv);
4150
4151                 mutex_unlock(&dev->struct_mutex);
4152         }
4153
4154         fs_reclaim_acquire(GFP_KERNEL);
4155         if (val & DROP_BOUND)
4156                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4157
4158         if (val & DROP_UNBOUND)
4159                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4160
4161         if (val & DROP_SHRINK_ALL)
4162                 i915_gem_shrink_all(dev_priv);
4163         fs_reclaim_release(GFP_KERNEL);
4164
4165         if (val & DROP_IDLE)
4166                 drain_delayed_work(&dev_priv->gt.idle_work);
4167
4168         if (val & DROP_FREED)
4169                 i915_gem_drain_freed_objects(dev_priv);
4170
4171         return ret;
4172 }
4173
4174 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4175                         i915_drop_caches_get, i915_drop_caches_set,
4176                         "0x%08llx\n");
4177
4178 static int
4179 i915_max_freq_get(void *data, u64 *val)
4180 {
4181         struct drm_i915_private *dev_priv = data;
4182
4183         if (INTEL_GEN(dev_priv) < 6)
4184                 return -ENODEV;
4185
4186         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4187         return 0;
4188 }
4189
4190 static int
4191 i915_max_freq_set(void *data, u64 val)
4192 {
4193         struct drm_i915_private *dev_priv = data;
4194         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4195         u32 hw_max, hw_min;
4196         int ret;
4197
4198         if (INTEL_GEN(dev_priv) < 6)
4199                 return -ENODEV;
4200
4201         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4202
4203         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4204         if (ret)
4205                 return ret;
4206
4207         /*
4208          * Turbo will still be enabled, but won't go above the set value.
4209          */
4210         val = intel_freq_opcode(dev_priv, val);
4211
4212         hw_max = rps->max_freq;
4213         hw_min = rps->min_freq;
4214
4215         if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4216                 mutex_unlock(&dev_priv->pcu_lock);
4217                 return -EINVAL;
4218         }
4219
4220         rps->max_freq_softlimit = val;
4221
4222         if (intel_set_rps(dev_priv, val))
4223                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4224
4225         mutex_unlock(&dev_priv->pcu_lock);
4226
4227         return 0;
4228 }
4229
4230 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4231                         i915_max_freq_get, i915_max_freq_set,
4232                         "%llu\n");
4233
4234 static int
4235 i915_min_freq_get(void *data, u64 *val)
4236 {
4237         struct drm_i915_private *dev_priv = data;
4238
4239         if (INTEL_GEN(dev_priv) < 6)
4240                 return -ENODEV;
4241
4242         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4243         return 0;
4244 }
4245
4246 static int
4247 i915_min_freq_set(void *data, u64 val)
4248 {
4249         struct drm_i915_private *dev_priv = data;
4250         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4251         u32 hw_max, hw_min;
4252         int ret;
4253
4254         if (INTEL_GEN(dev_priv) < 6)
4255                 return -ENODEV;
4256
4257         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4258
4259         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4260         if (ret)
4261                 return ret;
4262
4263         /*
4264          * Turbo will still be enabled, but won't go below the set value.
4265          */
4266         val = intel_freq_opcode(dev_priv, val);
4267
4268         hw_max = rps->max_freq;
4269         hw_min = rps->min_freq;
4270
4271         if (val < hw_min ||
4272             val > hw_max || val > rps->max_freq_softlimit) {
4273                 mutex_unlock(&dev_priv->pcu_lock);
4274                 return -EINVAL;
4275         }
4276
4277         rps->min_freq_softlimit = val;
4278
4279         if (intel_set_rps(dev_priv, val))
4280                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4281
4282         mutex_unlock(&dev_priv->pcu_lock);
4283
4284         return 0;
4285 }
4286
4287 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4288                         i915_min_freq_get, i915_min_freq_set,
4289                         "%llu\n");
4290
4291 static int
4292 i915_cache_sharing_get(void *data, u64 *val)
4293 {
4294         struct drm_i915_private *dev_priv = data;
4295         u32 snpcr;
4296
4297         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4298                 return -ENODEV;
4299
4300         intel_runtime_pm_get(dev_priv);
4301
4302         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4303
4304         intel_runtime_pm_put(dev_priv);
4305
4306         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4307
4308         return 0;
4309 }
4310
4311 static int
4312 i915_cache_sharing_set(void *data, u64 val)
4313 {
4314         struct drm_i915_private *dev_priv = data;
4315         u32 snpcr;
4316
4317         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4318                 return -ENODEV;
4319
4320         if (val > 3)
4321                 return -EINVAL;
4322
4323         intel_runtime_pm_get(dev_priv);
4324         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4325
4326         /* Update the cache sharing policy here as well */
4327         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4328         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4329         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4330         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4331
4332         intel_runtime_pm_put(dev_priv);
4333         return 0;
4334 }
4335
4336 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4337                         i915_cache_sharing_get, i915_cache_sharing_set,
4338                         "%llu\n");
4339
4340 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4341                                           struct sseu_dev_info *sseu)
4342 {
4343 #define SS_MAX 2
4344         const int ss_max = SS_MAX;
4345         u32 sig1[SS_MAX], sig2[SS_MAX];
4346         int ss;
4347
4348         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4349         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4350         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4351         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4352
4353         for (ss = 0; ss < ss_max; ss++) {
4354                 unsigned int eu_cnt;
4355
4356                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4357                         /* skip disabled subslice */
4358                         continue;
4359
4360                 sseu->slice_mask = BIT(0);
4361                 sseu->subslice_mask[0] |= BIT(ss);
4362                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4363                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4364                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4365                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4366                 sseu->eu_total += eu_cnt;
4367                 sseu->eu_per_subslice = max_t(unsigned int,
4368                                               sseu->eu_per_subslice, eu_cnt);
4369         }
4370 #undef SS_MAX
4371 }
4372
4373 static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
4374                                      struct sseu_dev_info *sseu)
4375 {
4376 #define SS_MAX 6
4377         const struct intel_device_info *info = INTEL_INFO(dev_priv);
4378         u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
4379         int s, ss;
4380
4381         for (s = 0; s < info->sseu.max_slices; s++) {
4382                 /*
4383                  * FIXME: Valid SS Mask respects the spec and read
4384                  * only valid bits for those registers, excluding reserverd
4385                  * although this seems wrong because it would leave many
4386                  * subslices without ACK.
4387                  */
4388                 s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
4389                         GEN10_PGCTL_VALID_SS_MASK(s);
4390                 eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
4391                 eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
4392         }
4393
4394         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4395                      GEN9_PGCTL_SSA_EU19_ACK |
4396                      GEN9_PGCTL_SSA_EU210_ACK |
4397                      GEN9_PGCTL_SSA_EU311_ACK;
4398         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4399                      GEN9_PGCTL_SSB_EU19_ACK |
4400                      GEN9_PGCTL_SSB_EU210_ACK |
4401                      GEN9_PGCTL_SSB_EU311_ACK;
4402
4403         for (s = 0; s < info->sseu.max_slices; s++) {
4404                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4405                         /* skip disabled slice */
4406                         continue;
4407
4408                 sseu->slice_mask |= BIT(s);
4409                 sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
4410
4411                 for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4412                         unsigned int eu_cnt;
4413
4414                         if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4415                                 /* skip disabled subslice */
4416                                 continue;
4417
4418                         eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
4419                                                eu_mask[ss % 2]);
4420                         sseu->eu_total += eu_cnt;
4421                         sseu->eu_per_subslice = max_t(unsigned int,
4422                                                       sseu->eu_per_subslice,
4423                                                       eu_cnt);
4424                 }
4425         }
4426 #undef SS_MAX
4427 }
4428
4429 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4430                                     struct sseu_dev_info *sseu)
4431 {
4432 #define SS_MAX 3
4433         const struct intel_device_info *info = INTEL_INFO(dev_priv);
4434         u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
4435         int s, ss;
4436
4437         for (s = 0; s < info->sseu.max_slices; s++) {
4438                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4439                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4440                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4441         }
4442
4443         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4444                      GEN9_PGCTL_SSA_EU19_ACK |
4445                      GEN9_PGCTL_SSA_EU210_ACK |
4446                      GEN9_PGCTL_SSA_EU311_ACK;
4447         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4448                      GEN9_PGCTL_SSB_EU19_ACK |
4449                      GEN9_PGCTL_SSB_EU210_ACK |
4450                      GEN9_PGCTL_SSB_EU311_ACK;
4451
4452         for (s = 0; s < info->sseu.max_slices; s++) {
4453                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4454                         /* skip disabled slice */
4455                         continue;
4456
4457                 sseu->slice_mask |= BIT(s);
4458
4459                 if (IS_GEN9_BC(dev_priv))
4460                         sseu->subslice_mask[s] =
4461                                 INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4462
4463                 for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4464                         unsigned int eu_cnt;
4465
4466                         if (IS_GEN9_LP(dev_priv)) {
4467                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4468                                         /* skip disabled subslice */
4469                                         continue;
4470
4471                                 sseu->subslice_mask[s] |= BIT(ss);
4472                         }
4473
4474                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4475                                                eu_mask[ss%2]);
4476                         sseu->eu_total += eu_cnt;
4477                         sseu->eu_per_subslice = max_t(unsigned int,
4478                                                       sseu->eu_per_subslice,
4479                                                       eu_cnt);
4480                 }
4481         }
4482 #undef SS_MAX
4483 }
4484
4485 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4486                                          struct sseu_dev_info *sseu)
4487 {
4488         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4489         int s;
4490
4491         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4492
4493         if (sseu->slice_mask) {
4494                 sseu->eu_per_subslice =
4495                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4496                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4497                         sseu->subslice_mask[s] =
4498                                 INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4499                 }
4500                 sseu->eu_total = sseu->eu_per_subslice *
4501                                  sseu_subslice_total(sseu);
4502
4503                 /* subtract fused off EU(s) from enabled slice(s) */
4504                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4505                         u8 subslice_7eu =
4506                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4507
4508                         sseu->eu_total -= hweight8(subslice_7eu);
4509                 }
4510         }
4511 }
4512
4513 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4514                                  const struct sseu_dev_info *sseu)
4515 {
4516         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4517         const char *type = is_available_info ? "Available" : "Enabled";
4518         int s;
4519
4520         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4521                    sseu->slice_mask);
4522         seq_printf(m, "  %s Slice Total: %u\n", type,
4523                    hweight8(sseu->slice_mask));
4524         seq_printf(m, "  %s Subslice Total: %u\n", type,
4525                    sseu_subslice_total(sseu));
4526         for (s = 0; s < fls(sseu->slice_mask); s++) {
4527                 seq_printf(m, "  %s Slice%i subslices: %u\n", type,
4528                            s, hweight8(sseu->subslice_mask[s]));
4529         }
4530         seq_printf(m, "  %s EU Total: %u\n", type,
4531                    sseu->eu_total);
4532         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4533                    sseu->eu_per_subslice);
4534
4535         if (!is_available_info)
4536                 return;
4537
4538         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4539         if (HAS_POOLED_EU(dev_priv))
4540                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4541
4542         seq_printf(m, "  Has Slice Power Gating: %s\n",
4543                    yesno(sseu->has_slice_pg));
4544         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4545                    yesno(sseu->has_subslice_pg));
4546         seq_printf(m, "  Has EU Power Gating: %s\n",
4547                    yesno(sseu->has_eu_pg));
4548 }
4549
4550 static int i915_sseu_status(struct seq_file *m, void *unused)
4551 {
4552         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4553         struct sseu_dev_info sseu;
4554
4555         if (INTEL_GEN(dev_priv) < 8)
4556                 return -ENODEV;
4557
4558         seq_puts(m, "SSEU Device Info\n");
4559         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4560
4561         seq_puts(m, "SSEU Device Status\n");
4562         memset(&sseu, 0, sizeof(sseu));
4563         sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
4564         sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
4565         sseu.max_eus_per_subslice =
4566                 INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
4567
4568         intel_runtime_pm_get(dev_priv);
4569
4570         if (IS_CHERRYVIEW(dev_priv)) {
4571                 cherryview_sseu_device_status(dev_priv, &sseu);
4572         } else if (IS_BROADWELL(dev_priv)) {
4573                 broadwell_sseu_device_status(dev_priv, &sseu);
4574         } else if (IS_GEN9(dev_priv)) {
4575                 gen9_sseu_device_status(dev_priv, &sseu);
4576         } else if (INTEL_GEN(dev_priv) >= 10) {
4577                 gen10_sseu_device_status(dev_priv, &sseu);
4578         }
4579
4580         intel_runtime_pm_put(dev_priv);
4581
4582         i915_print_sseu_info(m, false, &sseu);
4583
4584         return 0;
4585 }
4586
4587 static int i915_forcewake_open(struct inode *inode, struct file *file)
4588 {
4589         struct drm_i915_private *i915 = inode->i_private;
4590
4591         if (INTEL_GEN(i915) < 6)
4592                 return 0;
4593
4594         intel_runtime_pm_get(i915);
4595         intel_uncore_forcewake_user_get(i915);
4596
4597         return 0;
4598 }
4599
4600 static int i915_forcewake_release(struct inode *inode, struct file *file)
4601 {
4602         struct drm_i915_private *i915 = inode->i_private;
4603
4604         if (INTEL_GEN(i915) < 6)
4605                 return 0;
4606
4607         intel_uncore_forcewake_user_put(i915);
4608         intel_runtime_pm_put(i915);
4609
4610         return 0;
4611 }
4612
4613 static const struct file_operations i915_forcewake_fops = {
4614         .owner = THIS_MODULE,
4615         .open = i915_forcewake_open,
4616         .release = i915_forcewake_release,
4617 };
4618
4619 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4620 {
4621         struct drm_i915_private *dev_priv = m->private;
4622         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4623
4624         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4625         seq_printf(m, "Detected: %s\n",
4626                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4627
4628         return 0;
4629 }
4630
4631 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4632                                         const char __user *ubuf, size_t len,
4633                                         loff_t *offp)
4634 {
4635         struct seq_file *m = file->private_data;
4636         struct drm_i915_private *dev_priv = m->private;
4637         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4638         unsigned int new_threshold;
4639         int i;
4640         char *newline;
4641         char tmp[16];
4642
4643         if (len >= sizeof(tmp))
4644                 return -EINVAL;
4645
4646         if (copy_from_user(tmp, ubuf, len))
4647                 return -EFAULT;
4648
4649         tmp[len] = '\0';
4650
4651         /* Strip newline, if any */
4652         newline = strchr(tmp, '\n');
4653         if (newline)
4654                 *newline = '\0';
4655
4656         if (strcmp(tmp, "reset") == 0)
4657                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4658         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4659                 return -EINVAL;
4660
4661         if (new_threshold > 0)
4662                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4663                               new_threshold);
4664         else
4665                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4666
4667         spin_lock_irq(&dev_priv->irq_lock);
4668         hotplug->hpd_storm_threshold = new_threshold;
4669         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4670         for_each_hpd_pin(i)
4671                 hotplug->stats[i].count = 0;
4672         spin_unlock_irq(&dev_priv->irq_lock);
4673
4674         /* Re-enable hpd immediately if we were in an irq storm */
4675         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4676
4677         return len;
4678 }
4679
4680 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4681 {
4682         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4683 }
4684
4685 static const struct file_operations i915_hpd_storm_ctl_fops = {
4686         .owner = THIS_MODULE,
4687         .open = i915_hpd_storm_ctl_open,
4688         .read = seq_read,
4689         .llseek = seq_lseek,
4690         .release = single_release,
4691         .write = i915_hpd_storm_ctl_write
4692 };
4693
4694 static int i915_drrs_ctl_set(void *data, u64 val)
4695 {
4696         struct drm_i915_private *dev_priv = data;
4697         struct drm_device *dev = &dev_priv->drm;
4698         struct intel_crtc *intel_crtc;
4699         struct intel_encoder *encoder;
4700         struct intel_dp *intel_dp;
4701
4702         if (INTEL_GEN(dev_priv) < 7)
4703                 return -ENODEV;
4704
4705         drm_modeset_lock_all(dev);
4706         for_each_intel_crtc(dev, intel_crtc) {
4707                 if (!intel_crtc->base.state->active ||
4708                                         !intel_crtc->config->has_drrs)
4709                         continue;
4710
4711                 for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
4712                         if (encoder->type != INTEL_OUTPUT_EDP)
4713                                 continue;
4714
4715                         DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
4716                                                 val ? "en" : "dis", val);
4717
4718                         intel_dp = enc_to_intel_dp(&encoder->base);
4719                         if (val)
4720                                 intel_edp_drrs_enable(intel_dp,
4721                                                         intel_crtc->config);
4722                         else
4723                                 intel_edp_drrs_disable(intel_dp,
4724                                                         intel_crtc->config);
4725                 }
4726         }
4727         drm_modeset_unlock_all(dev);
4728
4729         return 0;
4730 }
4731
4732 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
4733
4734 static const struct drm_info_list i915_debugfs_list[] = {
4735         {"i915_capabilities", i915_capabilities, 0},
4736         {"i915_gem_objects", i915_gem_object_info, 0},
4737         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4738         {"i915_gem_stolen", i915_gem_stolen_list_info },
4739         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4740         {"i915_gem_interrupt", i915_interrupt_info, 0},
4741         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4742         {"i915_guc_info", i915_guc_info, 0},
4743         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4744         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4745         {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4746         {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4747         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4748         {"i915_frequency_info", i915_frequency_info, 0},
4749         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4750         {"i915_reset_info", i915_reset_info, 0},
4751         {"i915_drpc_info", i915_drpc_info, 0},
4752         {"i915_emon_status", i915_emon_status, 0},
4753         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4754         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4755         {"i915_fbc_status", i915_fbc_status, 0},
4756         {"i915_ips_status", i915_ips_status, 0},
4757         {"i915_sr_status", i915_sr_status, 0},
4758         {"i915_opregion", i915_opregion, 0},
4759         {"i915_vbt", i915_vbt, 0},
4760         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4761         {"i915_context_status", i915_context_status, 0},
4762         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4763         {"i915_swizzle_info", i915_swizzle_info, 0},
4764         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4765         {"i915_llc", i915_llc, 0},
4766         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4767         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4768         {"i915_energy_uJ", i915_energy_uJ, 0},
4769         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4770         {"i915_power_domain_info", i915_power_domain_info, 0},
4771         {"i915_dmc_info", i915_dmc_info, 0},
4772         {"i915_display_info", i915_display_info, 0},
4773         {"i915_engine_info", i915_engine_info, 0},
4774         {"i915_rcs_topology", i915_rcs_topology, 0},
4775         {"i915_shrinker_info", i915_shrinker_info, 0},
4776         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4777         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4778         {"i915_wa_registers", i915_wa_registers, 0},
4779         {"i915_ddb_info", i915_ddb_info, 0},
4780         {"i915_sseu_status", i915_sseu_status, 0},
4781         {"i915_drrs_status", i915_drrs_status, 0},
4782         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4783 };
4784 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4785
4786 static const struct i915_debugfs_files {
4787         const char *name;
4788         const struct file_operations *fops;
4789 } i915_debugfs_files[] = {
4790         {"i915_wedged", &i915_wedged_fops},
4791         {"i915_max_freq", &i915_max_freq_fops},
4792         {"i915_min_freq", &i915_min_freq_fops},
4793         {"i915_cache_sharing", &i915_cache_sharing_fops},
4794         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4795         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4796         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4797 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4798         {"i915_error_state", &i915_error_state_fops},
4799         {"i915_gpu_info", &i915_gpu_info_fops},
4800 #endif
4801         {"i915_next_seqno", &i915_next_seqno_fops},
4802         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4803         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4804         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4805         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4806         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4807         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4808         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4809         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4810         {"i915_guc_log_level", &i915_guc_log_level_fops},
4811         {"i915_guc_log_relay", &i915_guc_log_relay_fops},
4812         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4813         {"i915_ipc_status", &i915_ipc_status_fops},
4814         {"i915_drrs_ctl", &i915_drrs_ctl_fops}
4815 };
4816
4817 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4818 {
4819         struct drm_minor *minor = dev_priv->drm.primary;
4820         struct dentry *ent;
4821         int ret, i;
4822
4823         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4824                                   minor->debugfs_root, to_i915(minor->dev),
4825                                   &i915_forcewake_fops);
4826         if (!ent)
4827                 return -ENOMEM;
4828
4829         ret = intel_pipe_crc_create(minor);
4830         if (ret)
4831                 return ret;
4832
4833         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4834                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4835                                           S_IRUGO | S_IWUSR,
4836                                           minor->debugfs_root,
4837                                           to_i915(minor->dev),
4838                                           i915_debugfs_files[i].fops);
4839                 if (!ent)
4840                         return -ENOMEM;
4841         }
4842
4843         return drm_debugfs_create_files(i915_debugfs_list,
4844                                         I915_DEBUGFS_ENTRIES,
4845                                         minor->debugfs_root, minor);
4846 }
4847
4848 struct dpcd_block {
4849         /* DPCD dump start address. */
4850         unsigned int offset;
4851         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4852         unsigned int end;
4853         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4854         size_t size;
4855         /* Only valid for eDP. */
4856         bool edp;
4857 };
4858
4859 static const struct dpcd_block i915_dpcd_debug[] = {
4860         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4861         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4862         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4863         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4864         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4865         { .offset = DP_SET_POWER },
4866         { .offset = DP_EDP_DPCD_REV },
4867         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4868         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4869         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4870 };
4871
4872 static int i915_dpcd_show(struct seq_file *m, void *data)
4873 {
4874         struct drm_connector *connector = m->private;
4875         struct intel_dp *intel_dp =
4876                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4877         uint8_t buf[16];
4878         ssize_t err;
4879         int i;
4880
4881         if (connector->status != connector_status_connected)
4882                 return -ENODEV;
4883
4884         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4885                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4886                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4887
4888                 if (b->edp &&
4889                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4890                         continue;
4891
4892                 /* low tech for now */
4893                 if (WARN_ON(size > sizeof(buf)))
4894                         continue;
4895
4896                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4897                 if (err <= 0) {
4898                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4899                                   size, b->offset, err);
4900                         continue;
4901                 }
4902
4903                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4904         }
4905
4906         return 0;
4907 }
4908 DEFINE_SHOW_ATTRIBUTE(i915_dpcd);
4909
4910 static int i915_panel_show(struct seq_file *m, void *data)
4911 {
4912         struct drm_connector *connector = m->private;
4913         struct intel_dp *intel_dp =
4914                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4915
4916         if (connector->status != connector_status_connected)
4917                 return -ENODEV;
4918
4919         seq_printf(m, "Panel power up delay: %d\n",
4920                    intel_dp->panel_power_up_delay);
4921         seq_printf(m, "Panel power down delay: %d\n",
4922                    intel_dp->panel_power_down_delay);
4923         seq_printf(m, "Backlight on delay: %d\n",
4924                    intel_dp->backlight_on_delay);
4925         seq_printf(m, "Backlight off delay: %d\n",
4926                    intel_dp->backlight_off_delay);
4927
4928         return 0;
4929 }
4930 DEFINE_SHOW_ATTRIBUTE(i915_panel);
4931
4932 /**
4933  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4934  * @connector: pointer to a registered drm_connector
4935  *
4936  * Cleanup will be done by drm_connector_unregister() through a call to
4937  * drm_debugfs_connector_remove().
4938  *
4939  * Returns 0 on success, negative error codes on error.
4940  */
4941 int i915_debugfs_connector_add(struct drm_connector *connector)
4942 {
4943         struct dentry *root = connector->debugfs_entry;
4944
4945         /* The connector must have been registered beforehands. */
4946         if (!root)
4947                 return -ENODEV;
4948
4949         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4950             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4951                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4952                                     connector, &i915_dpcd_fops);
4953
4954         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4955                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4956                                     connector, &i915_panel_fops);
4957
4958         return 0;
4959 }