drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  44  * allocated we need to hook into the minor for release. */
  45 static int
  46 drm_add_fake_info_node(struct drm_minor *minor,
  47                        struct dentry *ent,
  48                        const void *key)
  49 {
  50         struct drm_info_node *node;
  51
  52         node = kmalloc(sizeof(*node), GFP_KERNEL);
  53         if (node == NULL) {
  54                 debugfs_remove(ent);
  55                 return -ENOMEM;
  56         }
  57
  58         node->minor = minor;
  59         node->dent = ent;
  60         node->info_ent = (void *) key;
  61
  62         mutex_lock(&minor->debugfs_lock);
  63         list_add(&node->list, &minor->debugfs_list);
  64         mutex_unlock(&minor->debugfs_lock);
  65
  66         return 0;
  67 }
  68
  69 static int i915_capabilities(struct seq_file *m, void *data)
  70 {
  71         struct drm_info_node *node = m->private;
  72         struct drm_device *dev = node->minor->dev;
  73         const struct intel_device_info *info = INTEL_INFO(dev);
  74
  75         seq_printf(m, "gen: %d\n", info->gen);
  76         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  77 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  78 #define SEP_SEMICOLON ;
  79         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  80 #undef PRINT_FLAG
  81 #undef SEP_SEMICOLON
  82
  83         return 0;
  84 }
  85
  86 static char get_active_flag(struct drm_i915_gem_object *obj)
  87 {
  88         return i915_gem_object_is_active(obj) ? '*' : ' ';
  89 }
  90
  91 static char get_pin_flag(struct drm_i915_gem_object *obj)
  92 {
  93         return obj->pin_display ? 'p' : ' ';
  94 }
  95
  96 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  97 {
  98         switch (i915_gem_object_get_tiling(obj)) {
  99         default:
 100         case I915_TILING_NONE: return ' ';
 101         case I915_TILING_X: return 'X';
 102         case I915_TILING_Y: return 'Y';
 103         }
 104 }
 105
 106 static char get_global_flag(struct drm_i915_gem_object *obj)
 107 {
 108         return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
 109 }
 110
 111 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 112 {
 113         return obj->mapping ? 'M' : ' ';
 114 }
 115
 116 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 117 {
 118         u64 size = 0;
 119         struct i915_vma *vma;
 120
 121         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 122                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 123                         size += vma->node.size;
 124         }
 125
 126         return size;
 127 }
 128
 129 static void
 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 133         struct intel_engine_cs *engine;
 134         struct i915_vma *vma;
 135         unsigned int frontbuffer_bits;
 136         int pin_count = 0;
 137         enum intel_engine_id id;
 138
 139         lockdep_assert_held(&obj->base.dev->struct_mutex);
 140
 141         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 142                    &obj->base,
 143                    get_active_flag(obj),
 144                    get_pin_flag(obj),
 145                    get_tiling_flag(obj),
 146                    get_global_flag(obj),
 147                    get_pin_mapped_flag(obj),
 148                    obj->base.size / 1024,
 149                    obj->base.read_domains,
 150                    obj->base.write_domain);
 151         for_each_engine_id(engine, dev_priv, id)
 152                 seq_printf(m, "%x ",
 153                            i915_gem_active_get_seqno(&obj->last_read[id],
 154                                                      &obj->base.dev->struct_mutex));
 155         seq_printf(m, "] %x %x%s%s%s",
 156                    i915_gem_active_get_seqno(&obj->last_write,
 157                                              &obj->base.dev->struct_mutex),
 158                    i915_gem_active_get_seqno(&obj->last_fence,
 159                                              &obj->base.dev->struct_mutex),
 160                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 161                    obj->dirty ? " dirty" : "",
 162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 163         if (obj->base.name)
 164                 seq_printf(m, " (name: %d)", obj->base.name);
 165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 166                 if (i915_vma_is_pinned(vma))
 167                         pin_count++;
 168         }
 169         seq_printf(m, " (pinned x %d)", pin_count);
 170         if (obj->pin_display)
 171                 seq_printf(m, " (display)");
 172         if (obj->fence_reg != I915_FENCE_REG_NONE)
 173                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 174         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 175                 if (!drm_mm_node_allocated(&vma->node))
 176                         continue;
 177
 178                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 179                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 180                            vma->node.start, vma->node.size);
 181                 if (i915_vma_is_ggtt(vma))
 182                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 183                 seq_puts(m, ")");
 184         }
 185         if (obj->stolen)
 186                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 187         if (obj->pin_display || obj->fault_mappable) {
 188                 char s[3], *t = s;
 189                 if (obj->pin_display)
 190                         *t++ = 'p';
 191                 if (obj->fault_mappable)
 192                         *t++ = 'f';
 193                 *t = '\0';
 194                 seq_printf(m, " (%s mappable)", s);
 195         }
 196
 197         engine = i915_gem_active_get_engine(&obj->last_write,
 198                                             &obj->base.dev->struct_mutex);
 199         if (engine)
 200                 seq_printf(m, " (%s)", engine->name);
 201
 202         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 203         if (frontbuffer_bits)
 204                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 205 }
 206
 207 static int obj_rank_by_stolen(void *priv,
 208                               struct list_head *A, struct list_head *B)
 209 {
 210         struct drm_i915_gem_object *a =
 211                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 212         struct drm_i915_gem_object *b =
 213                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 214
 215         if (a->stolen->start < b->stolen->start)
 216                 return -1;
 217         if (a->stolen->start > b->stolen->start)
 218                 return 1;
 219         return 0;
 220 }
 221
 222 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 223 {
 224         struct drm_info_node *node = m->private;
 225         struct drm_device *dev = node->minor->dev;
 226         struct drm_i915_private *dev_priv = to_i915(dev);
 227         struct drm_i915_gem_object *obj;
 228         u64 total_obj_size, total_gtt_size;
 229         LIST_HEAD(stolen);
 230         int count, ret;
 231
 232         ret = mutex_lock_interruptible(&dev->struct_mutex);
 233         if (ret)
 234                 return ret;
 235
 236         total_obj_size = total_gtt_size = count = 0;
 237         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 238                 if (obj->stolen == NULL)
 239                         continue;
 240
 241                 list_add(&obj->obj_exec_link, &stolen);
 242
 243                 total_obj_size += obj->base.size;
 244                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 245                 count++;
 246         }
 247         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 248                 if (obj->stolen == NULL)
 249                         continue;
 250
 251                 list_add(&obj->obj_exec_link, &stolen);
 252
 253                 total_obj_size += obj->base.size;
 254                 count++;
 255         }
 256         list_sort(NULL, &stolen, obj_rank_by_stolen);
 257         seq_puts(m, "Stolen:\n");
 258         while (!list_empty(&stolen)) {
 259                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 260                 seq_puts(m, "   ");
 261                 describe_obj(m, obj);
 262                 seq_putc(m, '\n');
 263                 list_del_init(&obj->obj_exec_link);
 264         }
 265         mutex_unlock(&dev->struct_mutex);
 266
 267         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 268                    count, total_obj_size, total_gtt_size);
 269         return 0;
 270 }
 271
 272 struct file_stats {
 273         struct drm_i915_file_private *file_priv;
 274         unsigned long count;
 275         u64 total, unbound;
 276         u64 global, shared;
 277         u64 active, inactive;
 278 };
 279
 280 static int per_file_stats(int id, void *ptr, void *data)
 281 {
 282         struct drm_i915_gem_object *obj = ptr;
 283         struct file_stats *stats = data;
 284         struct i915_vma *vma;
 285
 286         stats->count++;
 287         stats->total += obj->base.size;
 288         if (!obj->bind_count)
 289                 stats->unbound += obj->base.size;
 290         if (obj->base.name || obj->base.dma_buf)
 291                 stats->shared += obj->base.size;
 292
 293         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 294                 if (!drm_mm_node_allocated(&vma->node))
 295                         continue;
 296
 297                 if (i915_vma_is_ggtt(vma)) {
 298                         stats->global += vma->node.size;
 299                 } else {
 300                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 301
 302                         if (ppgtt->base.file != stats->file_priv)
 303                                 continue;
 304                 }
 305
 306                 if (i915_vma_is_active(vma))
 307                         stats->active += vma->node.size;
 308                 else
 309                         stats->inactive += vma->node.size;
 310         }
 311
 312         return 0;
 313 }
 314
 315 #define print_file_stats(m, name, stats) do { \
 316         if (stats.count) \
 317                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 318                            name, \
 319                            stats.count, \
 320                            stats.total, \
 321                            stats.active, \
 322                            stats.inactive, \
 323                            stats.global, \
 324                            stats.shared, \
 325                            stats.unbound); \
 326 } while (0)
 327
 328 static void print_batch_pool_stats(struct seq_file *m,
 329                                    struct drm_i915_private *dev_priv)
 330 {
 331         struct drm_i915_gem_object *obj;
 332         struct file_stats stats;
 333         struct intel_engine_cs *engine;
 334         int j;
 335
 336         memset(&stats, 0, sizeof(stats));
 337
 338         for_each_engine(engine, dev_priv) {
 339                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 340                         list_for_each_entry(obj,
 341                                             &engine->batch_pool.cache_list[j],
 342                                             batch_pool_link)
 343                                 per_file_stats(0, obj, &stats);
 344                 }
 345         }
 346
 347         print_file_stats(m, "[k]batch pool", stats);
 348 }
 349
 350 static int per_file_ctx_stats(int id, void *ptr, void *data)
 351 {
 352         struct i915_gem_context *ctx = ptr;
 353         int n;
 354
 355         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 356                 if (ctx->engine[n].state)
 357                         per_file_stats(0, ctx->engine[n].state->obj, data);
 358                 if (ctx->engine[n].ring)
 359                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 360         }
 361
 362         return 0;
 363 }
 364
 365 static void print_context_stats(struct seq_file *m,
 366                                 struct drm_i915_private *dev_priv)
 367 {
 368         struct file_stats stats;
 369         struct drm_file *file;
 370
 371         memset(&stats, 0, sizeof(stats));
 372
 373         mutex_lock(&dev_priv->drm.struct_mutex);
 374         if (dev_priv->kernel_context)
 375                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 376
 377         list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
 378                 struct drm_i915_file_private *fpriv = file->driver_priv;
 379                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 380         }
 381         mutex_unlock(&dev_priv->drm.struct_mutex);
 382
 383         print_file_stats(m, "[k]contexts", stats);
 384 }
 385
 386 static int i915_gem_object_info(struct seq_file *m, void* data)
 387 {
 388         struct drm_info_node *node = m->private;
 389         struct drm_device *dev = node->minor->dev;
 390         struct drm_i915_private *dev_priv = to_i915(dev);
 391         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 392         u32 count, mapped_count, purgeable_count, dpy_count;
 393         u64 size, mapped_size, purgeable_size, dpy_size;
 394         struct drm_i915_gem_object *obj;
 395         struct drm_file *file;
 396         int ret;
 397
 398         ret = mutex_lock_interruptible(&dev->struct_mutex);
 399         if (ret)
 400                 return ret;
 401
 402         seq_printf(m, "%u objects, %zu bytes\n",
 403                    dev_priv->mm.object_count,
 404                    dev_priv->mm.object_memory);
 405
 406         size = count = purgeable_size = purgeable_count = 0;
 407         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 408                 size += obj->base.size;
 409                 ++count;
 410
 411                 if (obj->madv == I915_MADV_DONTNEED) {
 412                         purgeable_size += obj->base.size;
 413                         ++purgeable_count;
 414                 }
 415
 416                 if (obj->mapping) {
 417                         mapped_count++;
 418                         mapped_size += obj->base.size;
 419                 }
 420         }
 421         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 422
 423         size = count = dpy_size = dpy_count = 0;
 424         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 425                 size += obj->base.size;
 426                 ++count;
 427
 428                 if (obj->pin_display) {
 429                         dpy_size += obj->base.size;
 430                         ++dpy_count;
 431                 }
 432
 433                 if (obj->madv == I915_MADV_DONTNEED) {
 434                         purgeable_size += obj->base.size;
 435                         ++purgeable_count;
 436                 }
 437
 438                 if (obj->mapping) {
 439                         mapped_count++;
 440                         mapped_size += obj->base.size;
 441                 }
 442         }
 443         seq_printf(m, "%u bound objects, %llu bytes\n",
 444                    count, size);
 445         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 446                    purgeable_count, purgeable_size);
 447         seq_printf(m, "%u mapped objects, %llu bytes\n",
 448                    mapped_count, mapped_size);
 449         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 450                    dpy_count, dpy_size);
 451
 452         seq_printf(m, "%llu [%llu] gtt total\n",
 453                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 454
 455         seq_putc(m, '\n');
 456         print_batch_pool_stats(m, dev_priv);
 457         mutex_unlock(&dev->struct_mutex);
 458
 459         mutex_lock(&dev->filelist_mutex);
 460         print_context_stats(m, dev_priv);
 461         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 462                 struct file_stats stats;
 463                 struct task_struct *task;
 464
 465                 memset(&stats, 0, sizeof(stats));
 466                 stats.file_priv = file->driver_priv;
 467                 spin_lock(&file->table_lock);
 468                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 469                 spin_unlock(&file->table_lock);
 470                 /*
 471                  * Although we have a valid reference on file->pid, that does
 472                  * not guarantee that the task_struct who called get_pid() is
 473                  * still alive (e.g. get_pid(current) => fork() => exit()).
 474                  * Therefore, we need to protect this ->comm access using RCU.
 475                  */
 476                 rcu_read_lock();
 477                 task = pid_task(file->pid, PIDTYPE_PID);
 478                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 479                 rcu_read_unlock();
 480         }
 481         mutex_unlock(&dev->filelist_mutex);
 482
 483         return 0;
 484 }
 485
 486 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 487 {
 488         struct drm_info_node *node = m->private;
 489         struct drm_device *dev = node->minor->dev;
 490         struct drm_i915_private *dev_priv = to_i915(dev);
 491         bool show_pin_display_only = !!data;
 492         struct drm_i915_gem_object *obj;
 493         u64 total_obj_size, total_gtt_size;
 494         int count, ret;
 495
 496         ret = mutex_lock_interruptible(&dev->struct_mutex);
 497         if (ret)
 498                 return ret;
 499
 500         total_obj_size = total_gtt_size = count = 0;
 501         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 502                 if (show_pin_display_only && !obj->pin_display)
 503                         continue;
 504
 505                 seq_puts(m, "   ");
 506                 describe_obj(m, obj);
 507                 seq_putc(m, '\n');
 508                 total_obj_size += obj->base.size;
 509                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 510                 count++;
 511         }
 512
 513         mutex_unlock(&dev->struct_mutex);
 514
 515         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 516                    count, total_obj_size, total_gtt_size);
 517
 518         return 0;
 519 }
 520
 521 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 522 {
 523         struct drm_info_node *node = m->private;
 524         struct drm_device *dev = node->minor->dev;
 525         struct drm_i915_private *dev_priv = to_i915(dev);
 526         struct intel_crtc *crtc;
 527         int ret;
 528
 529         ret = mutex_lock_interruptible(&dev->struct_mutex);
 530         if (ret)
 531                 return ret;
 532
 533         for_each_intel_crtc(dev, crtc) {
 534                 const char pipe = pipe_name(crtc->pipe);
 535                 const char plane = plane_name(crtc->plane);
 536                 struct intel_flip_work *work;
 537
 538                 spin_lock_irq(&dev->event_lock);
 539                 work = crtc->flip_work;
 540                 if (work == NULL) {
 541                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 542                                    pipe, plane);
 543                 } else {
 544                         u32 pending;
 545                         u32 addr;
 546
 547                         pending = atomic_read(&work->pending);
 548                         if (pending) {
 549                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 550                                            pipe, plane);
 551                         } else {
 552                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 553                                            pipe, plane);
 554                         }
 555                         if (work->flip_queued_req) {
 556                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 557
 558                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 559                                            engine->name,
 560                                            i915_gem_request_get_seqno(work->flip_queued_req),
 561                                            dev_priv->next_seqno,
 562                                            intel_engine_get_seqno(engine),
 563                                            i915_gem_request_completed(work->flip_queued_req));
 564                         } else
 565                                 seq_printf(m, "Flip not associated with any ring\n");
 566                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 567                                    work->flip_queued_vblank,
 568                                    work->flip_ready_vblank,
 569                                    intel_crtc_get_vblank_counter(crtc));
 570                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 571
 572                         if (INTEL_INFO(dev)->gen >= 4)
 573                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 574                         else
 575                                 addr = I915_READ(DSPADDR(crtc->plane));
 576                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 577
 578                         if (work->pending_flip_obj) {
 579                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 580                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 581                         }
 582                 }
 583                 spin_unlock_irq(&dev->event_lock);
 584         }
 585
 586         mutex_unlock(&dev->struct_mutex);
 587
 588         return 0;
 589 }
 590
 591 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 592 {
 593         struct drm_info_node *node = m->private;
 594         struct drm_device *dev = node->minor->dev;
 595         struct drm_i915_private *dev_priv = to_i915(dev);
 596         struct drm_i915_gem_object *obj;
 597         struct intel_engine_cs *engine;
 598         int total = 0;
 599         int ret, j;
 600
 601         ret = mutex_lock_interruptible(&dev->struct_mutex);
 602         if (ret)
 603                 return ret;
 604
 605         for_each_engine(engine, dev_priv) {
 606                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 607                         int count;
 608
 609                         count = 0;
 610                         list_for_each_entry(obj,
 611                                             &engine->batch_pool.cache_list[j],
 612                                             batch_pool_link)
 613                                 count++;
 614                         seq_printf(m, "%s cache[%d]: %d objects\n",
 615                                    engine->name, j, count);
 616
 617                         list_for_each_entry(obj,
 618                                             &engine->batch_pool.cache_list[j],
 619                                             batch_pool_link) {
 620                                 seq_puts(m, "   ");
 621                                 describe_obj(m, obj);
 622                                 seq_putc(m, '\n');
 623                         }
 624
 625                         total += count;
 626                 }
 627         }
 628
 629         seq_printf(m, "total: %d\n", total);
 630
 631         mutex_unlock(&dev->struct_mutex);
 632
 633         return 0;
 634 }
 635
 636 static int i915_gem_request_info(struct seq_file *m, void *data)
 637 {
 638         struct drm_info_node *node = m->private;
 639         struct drm_device *dev = node->minor->dev;
 640         struct drm_i915_private *dev_priv = to_i915(dev);
 641         struct intel_engine_cs *engine;
 642         struct drm_i915_gem_request *req;
 643         int ret, any;
 644
 645         ret = mutex_lock_interruptible(&dev->struct_mutex);
 646         if (ret)
 647                 return ret;
 648
 649         any = 0;
 650         for_each_engine(engine, dev_priv) {
 651                 int count;
 652
 653                 count = 0;
 654                 list_for_each_entry(req, &engine->request_list, link)
 655                         count++;
 656                 if (count == 0)
 657                         continue;
 658
 659                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 660                 list_for_each_entry(req, &engine->request_list, link) {
 661                         struct task_struct *task;
 662
 663                         rcu_read_lock();
 664                         task = NULL;
 665                         if (req->pid)
 666                                 task = pid_task(req->pid, PIDTYPE_PID);
 667                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 668                                    req->fence.seqno,
 669                                    (int) (jiffies - req->emitted_jiffies),
 670                                    task ? task->comm : "<unknown>",
 671                                    task ? task->pid : -1);
 672                         rcu_read_unlock();
 673                 }
 674
 675                 any++;
 676         }
 677         mutex_unlock(&dev->struct_mutex);
 678
 679         if (any == 0)
 680                 seq_puts(m, "No requests\n");
 681
 682         return 0;
 683 }
 684
 685 static void i915_ring_seqno_info(struct seq_file *m,
 686                                  struct intel_engine_cs *engine)
 687 {
 688         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 689         struct rb_node *rb;
 690
 691         seq_printf(m, "Current sequence (%s): %x\n",
 692                    engine->name, intel_engine_get_seqno(engine));
 693
 694         spin_lock(&b->lock);
 695         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 696                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 697
 698                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 699                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 700         }
 701         spin_unlock(&b->lock);
 702 }
 703
 704 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 705 {
 706         struct drm_info_node *node = m->private;
 707         struct drm_device *dev = node->minor->dev;
 708         struct drm_i915_private *dev_priv = to_i915(dev);
 709         struct intel_engine_cs *engine;
 710         int ret;
 711
 712         ret = mutex_lock_interruptible(&dev->struct_mutex);
 713         if (ret)
 714                 return ret;
 715         intel_runtime_pm_get(dev_priv);
 716
 717         for_each_engine(engine, dev_priv)
 718                 i915_ring_seqno_info(m, engine);
 719
 720         intel_runtime_pm_put(dev_priv);
 721         mutex_unlock(&dev->struct_mutex);
 722
 723         return 0;
 724 }
 725
 726
 727 static int i915_interrupt_info(struct seq_file *m, void *data)
 728 {
 729         struct drm_info_node *node = m->private;
 730         struct drm_device *dev = node->minor->dev;
 731         struct drm_i915_private *dev_priv = to_i915(dev);
 732         struct intel_engine_cs *engine;
 733         int ret, i, pipe;
 734
 735         ret = mutex_lock_interruptible(&dev->struct_mutex);
 736         if (ret)
 737                 return ret;
 738         intel_runtime_pm_get(dev_priv);
 739
 740         if (IS_CHERRYVIEW(dev)) {
 741                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 742                            I915_READ(GEN8_MASTER_IRQ));
 743
 744                 seq_printf(m, "Display IER:\t%08x\n",
 745                            I915_READ(VLV_IER));
 746                 seq_printf(m, "Display IIR:\t%08x\n",
 747                            I915_READ(VLV_IIR));
 748                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 749                            I915_READ(VLV_IIR_RW));
 750                 seq_printf(m, "Display IMR:\t%08x\n",
 751                            I915_READ(VLV_IMR));
 752                 for_each_pipe(dev_priv, pipe)
 753                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 754                                    pipe_name(pipe),
 755                                    I915_READ(PIPESTAT(pipe)));
 756
 757                 seq_printf(m, "Port hotplug:\t%08x\n",
 758                            I915_READ(PORT_HOTPLUG_EN));
 759                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 760                            I915_READ(VLV_DPFLIPSTAT));
 761                 seq_printf(m, "DPINVGTT:\t%08x\n",
 762                            I915_READ(DPINVGTT));
 763
 764                 for (i = 0; i < 4; i++) {
 765                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 766                                    i, I915_READ(GEN8_GT_IMR(i)));
 767                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IIR(i)));
 769                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 770                                    i, I915_READ(GEN8_GT_IER(i)));
 771                 }
 772
 773                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 774                            I915_READ(GEN8_PCU_IMR));
 775                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 776                            I915_READ(GEN8_PCU_IIR));
 777                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 778                            I915_READ(GEN8_PCU_IER));
 779         } else if (INTEL_INFO(dev)->gen >= 8) {
 780                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 781                            I915_READ(GEN8_MASTER_IRQ));
 782
 783                 for (i = 0; i < 4; i++) {
 784                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 785                                    i, I915_READ(GEN8_GT_IMR(i)));
 786                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 787                                    i, I915_READ(GEN8_GT_IIR(i)));
 788                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 789                                    i, I915_READ(GEN8_GT_IER(i)));
 790                 }
 791
 792                 for_each_pipe(dev_priv, pipe) {
 793                         enum intel_display_power_domain power_domain;
 794
 795                         power_domain = POWER_DOMAIN_PIPE(pipe);
 796                         if (!intel_display_power_get_if_enabled(dev_priv,
 797                                                                 power_domain)) {
 798                                 seq_printf(m, "Pipe %c power disabled\n",
 799                                            pipe_name(pipe));
 800                                 continue;
 801                         }
 802                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 803                                    pipe_name(pipe),
 804                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 805                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 806                                    pipe_name(pipe),
 807                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 808                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 809                                    pipe_name(pipe),
 810                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 811
 812                         intel_display_power_put(dev_priv, power_domain);
 813                 }
 814
 815                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 816                            I915_READ(GEN8_DE_PORT_IMR));
 817                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 818                            I915_READ(GEN8_DE_PORT_IIR));
 819                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 820                            I915_READ(GEN8_DE_PORT_IER));
 821
 822                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 823                            I915_READ(GEN8_DE_MISC_IMR));
 824                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 825                            I915_READ(GEN8_DE_MISC_IIR));
 826                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 827                            I915_READ(GEN8_DE_MISC_IER));
 828
 829                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 830                            I915_READ(GEN8_PCU_IMR));
 831                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 832                            I915_READ(GEN8_PCU_IIR));
 833                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 834                            I915_READ(GEN8_PCU_IER));
 835         } else if (IS_VALLEYVIEW(dev)) {
 836                 seq_printf(m, "Display IER:\t%08x\n",
 837                            I915_READ(VLV_IER));
 838                 seq_printf(m, "Display IIR:\t%08x\n",
 839                            I915_READ(VLV_IIR));
 840                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 841                            I915_READ(VLV_IIR_RW));
 842                 seq_printf(m, "Display IMR:\t%08x\n",
 843                            I915_READ(VLV_IMR));
 844                 for_each_pipe(dev_priv, pipe)
 845                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 846                                    pipe_name(pipe),
 847                                    I915_READ(PIPESTAT(pipe)));
 848
 849                 seq_printf(m, "Master IER:\t%08x\n",
 850                            I915_READ(VLV_MASTER_IER));
 851
 852                 seq_printf(m, "Render IER:\t%08x\n",
 853                            I915_READ(GTIER));
 854                 seq_printf(m, "Render IIR:\t%08x\n",
 855                            I915_READ(GTIIR));
 856                 seq_printf(m, "Render IMR:\t%08x\n",
 857                            I915_READ(GTIMR));
 858
 859                 seq_printf(m, "PM IER:\t\t%08x\n",
 860                            I915_READ(GEN6_PMIER));
 861                 seq_printf(m, "PM IIR:\t\t%08x\n",
 862                            I915_READ(GEN6_PMIIR));
 863                 seq_printf(m, "PM IMR:\t\t%08x\n",
 864                            I915_READ(GEN6_PMIMR));
 865
 866                 seq_printf(m, "Port hotplug:\t%08x\n",
 867                            I915_READ(PORT_HOTPLUG_EN));
 868                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 869                            I915_READ(VLV_DPFLIPSTAT));
 870                 seq_printf(m, "DPINVGTT:\t%08x\n",
 871                            I915_READ(DPINVGTT));
 872
 873         } else if (!HAS_PCH_SPLIT(dev)) {
 874                 seq_printf(m, "Interrupt enable:    %08x\n",
 875                            I915_READ(IER));
 876                 seq_printf(m, "Interrupt identity:  %08x\n",
 877                            I915_READ(IIR));
 878                 seq_printf(m, "Interrupt mask:      %08x\n",
 879                            I915_READ(IMR));
 880                 for_each_pipe(dev_priv, pipe)
 881                         seq_printf(m, "Pipe %c stat:         %08x\n",
 882                                    pipe_name(pipe),
 883                                    I915_READ(PIPESTAT(pipe)));
 884         } else {
 885                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 886                            I915_READ(DEIER));
 887                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 888                            I915_READ(DEIIR));
 889                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 890                            I915_READ(DEIMR));
 891                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 892                            I915_READ(SDEIER));
 893                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 894                            I915_READ(SDEIIR));
 895                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 896                            I915_READ(SDEIMR));
 897                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 898                            I915_READ(GTIER));
 899                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 900                            I915_READ(GTIIR));
 901                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 902                            I915_READ(GTIMR));
 903         }
 904         for_each_engine(engine, dev_priv) {
 905                 if (INTEL_INFO(dev)->gen >= 6) {
 906                         seq_printf(m,
 907                                    "Graphics Interrupt mask (%s):       %08x\n",
 908                                    engine->name, I915_READ_IMR(engine));
 909                 }
 910                 i915_ring_seqno_info(m, engine);
 911         }
 912         intel_runtime_pm_put(dev_priv);
 913         mutex_unlock(&dev->struct_mutex);
 914
 915         return 0;
 916 }
 917
 918 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 919 {
 920         struct drm_info_node *node = m->private;
 921         struct drm_device *dev = node->minor->dev;
 922         struct drm_i915_private *dev_priv = to_i915(dev);
 923         int i, ret;
 924
 925         ret = mutex_lock_interruptible(&dev->struct_mutex);
 926         if (ret)
 927                 return ret;
 928
 929         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 930         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 931                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 932
 933                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 934                            i, dev_priv->fence_regs[i].pin_count);
 935                 if (obj == NULL)
 936                         seq_puts(m, "unused");
 937                 else
 938                         describe_obj(m, obj);
 939                 seq_putc(m, '\n');
 940         }
 941
 942         mutex_unlock(&dev->struct_mutex);
 943         return 0;
 944 }
 945
 946 static int i915_hws_info(struct seq_file *m, void *data)
 947 {
 948         struct drm_info_node *node = m->private;
 949         struct drm_device *dev = node->minor->dev;
 950         struct drm_i915_private *dev_priv = to_i915(dev);
 951         struct intel_engine_cs *engine;
 952         const u32 *hws;
 953         int i;
 954
 955         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 956         hws = engine->status_page.page_addr;
 957         if (hws == NULL)
 958                 return 0;
 959
 960         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 961                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 962                            i * 4,
 963                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 964         }
 965         return 0;
 966 }
 967
 968 static ssize_t
 969 i915_error_state_write(struct file *filp,
 970                        const char __user *ubuf,
 971                        size_t cnt,
 972                        loff_t *ppos)
 973 {
 974         struct i915_error_state_file_priv *error_priv = filp->private_data;
 975         struct drm_device *dev = error_priv->dev;
 976         int ret;
 977
 978         DRM_DEBUG_DRIVER("Resetting error state\n");
 979
 980         ret = mutex_lock_interruptible(&dev->struct_mutex);
 981         if (ret)
 982                 return ret;
 983
 984         i915_destroy_error_state(dev);
 985         mutex_unlock(&dev->struct_mutex);
 986
 987         return cnt;
 988 }
 989
 990 static int i915_error_state_open(struct inode *inode, struct file *file)
 991 {
 992         struct drm_device *dev = inode->i_private;
 993         struct i915_error_state_file_priv *error_priv;
 994
 995         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 996         if (!error_priv)
 997                 return -ENOMEM;
 998
 999         error_priv->dev = dev;
1000
1001         i915_error_state_get(dev, error_priv);
1002
1003         file->private_data = error_priv;
1004
1005         return 0;
1006 }
1007
1008 static int i915_error_state_release(struct inode *inode, struct file *file)
1009 {
1010         struct i915_error_state_file_priv *error_priv = file->private_data;
1011
1012         i915_error_state_put(error_priv);
1013         kfree(error_priv);
1014
1015         return 0;
1016 }
1017
1018 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1019                                      size_t count, loff_t *pos)
1020 {
1021         struct i915_error_state_file_priv *error_priv = file->private_data;
1022         struct drm_i915_error_state_buf error_str;
1023         loff_t tmp_pos = 0;
1024         ssize_t ret_count = 0;
1025         int ret;
1026
1027         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1028         if (ret)
1029                 return ret;
1030
1031         ret = i915_error_state_to_str(&error_str, error_priv);
1032         if (ret)
1033                 goto out;
1034
1035         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1036                                             error_str.buf,
1037                                             error_str.bytes);
1038
1039         if (ret_count < 0)
1040                 ret = ret_count;
1041         else
1042                 *pos = error_str.start + ret_count;
1043 out:
1044         i915_error_state_buf_release(&error_str);
1045         return ret ?: ret_count;
1046 }
1047
1048 static const struct file_operations i915_error_state_fops = {
1049         .owner = THIS_MODULE,
1050         .open = i915_error_state_open,
1051         .read = i915_error_state_read,
1052         .write = i915_error_state_write,
1053         .llseek = default_llseek,
1054         .release = i915_error_state_release,
1055 };
1056
1057 static int
1058 i915_next_seqno_get(void *data, u64 *val)
1059 {
1060         struct drm_device *dev = data;
1061         struct drm_i915_private *dev_priv = to_i915(dev);
1062         int ret;
1063
1064         ret = mutex_lock_interruptible(&dev->struct_mutex);
1065         if (ret)
1066                 return ret;
1067
1068         *val = dev_priv->next_seqno;
1069         mutex_unlock(&dev->struct_mutex);
1070
1071         return 0;
1072 }
1073
1074 static int
1075 i915_next_seqno_set(void *data, u64 val)
1076 {
1077         struct drm_device *dev = data;
1078         int ret;
1079
1080         ret = mutex_lock_interruptible(&dev->struct_mutex);
1081         if (ret)
1082                 return ret;
1083
1084         ret = i915_gem_set_seqno(dev, val);
1085         mutex_unlock(&dev->struct_mutex);
1086
1087         return ret;
1088 }
1089
1090 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1091                         i915_next_seqno_get, i915_next_seqno_set,
1092                         "0x%llx\n");
1093
1094 static int i915_frequency_info(struct seq_file *m, void *unused)
1095 {
1096         struct drm_info_node *node = m->private;
1097         struct drm_device *dev = node->minor->dev;
1098         struct drm_i915_private *dev_priv = to_i915(dev);
1099         int ret = 0;
1100
1101         intel_runtime_pm_get(dev_priv);
1102
1103         if (IS_GEN5(dev)) {
1104                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1105                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1106
1107                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1108                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1109                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1110                            MEMSTAT_VID_SHIFT);
1111                 seq_printf(m, "Current P-state: %d\n",
1112                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1113         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1114                 u32 freq_sts;
1115
1116                 mutex_lock(&dev_priv->rps.hw_lock);
1117                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1118                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1119                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1120
1121                 seq_printf(m, "actual GPU freq: %d MHz\n",
1122                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1123
1124                 seq_printf(m, "current GPU freq: %d MHz\n",
1125                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1126
1127                 seq_printf(m, "max GPU freq: %d MHz\n",
1128                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1129
1130                 seq_printf(m, "min GPU freq: %d MHz\n",
1131                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1132
1133                 seq_printf(m, "idle GPU freq: %d MHz\n",
1134                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1135
1136                 seq_printf(m,
1137                            "efficient (RPe) frequency: %d MHz\n",
1138                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1139                 mutex_unlock(&dev_priv->rps.hw_lock);
1140         } else if (INTEL_INFO(dev)->gen >= 6) {
1141                 u32 rp_state_limits;
1142                 u32 gt_perf_status;
1143                 u32 rp_state_cap;
1144                 u32 rpmodectl, rpinclimit, rpdeclimit;
1145                 u32 rpstat, cagf, reqf;
1146                 u32 rpupei, rpcurup, rpprevup;
1147                 u32 rpdownei, rpcurdown, rpprevdown;
1148                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1149                 int max_freq;
1150
1151                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1152                 if (IS_BROXTON(dev)) {
1153                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1154                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1155                 } else {
1156                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1157                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1158                 }
1159
1160                 /* RPSTAT1 is in the GT power well */
1161                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1162                 if (ret)
1163                         goto out;
1164
1165                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1166
1167                 reqf = I915_READ(GEN6_RPNSWREQ);
1168                 if (IS_GEN9(dev))
1169                         reqf >>= 23;
1170                 else {
1171                         reqf &= ~GEN6_TURBO_DISABLE;
1172                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1173                                 reqf >>= 24;
1174                         else
1175                                 reqf >>= 25;
1176                 }
1177                 reqf = intel_gpu_freq(dev_priv, reqf);
1178
1179                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1180                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1181                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1182
1183                 rpstat = I915_READ(GEN6_RPSTAT1);
1184                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1185                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1186                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1187                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1188                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1189                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1190                 if (IS_GEN9(dev))
1191                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1192                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1193                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1194                 else
1195                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1196                 cagf = intel_gpu_freq(dev_priv, cagf);
1197
1198                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1199                 mutex_unlock(&dev->struct_mutex);
1200
1201                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1202                         pm_ier = I915_READ(GEN6_PMIER);
1203                         pm_imr = I915_READ(GEN6_PMIMR);
1204                         pm_isr = I915_READ(GEN6_PMISR);
1205                         pm_iir = I915_READ(GEN6_PMIIR);
1206                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1207                 } else {
1208                         pm_ier = I915_READ(GEN8_GT_IER(2));
1209                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1210                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1211                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1212                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1213                 }
1214                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1215                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1216                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1217                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1218                 seq_printf(m, "Render p-state ratio: %d\n",
1219                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1220                 seq_printf(m, "Render p-state VID: %d\n",
1221                            gt_perf_status & 0xff);
1222                 seq_printf(m, "Render p-state limit: %d\n",
1223                            rp_state_limits & 0xff);
1224                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1225                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1226                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1227                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1228                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1229                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1230                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1231                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1232                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1233                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1234                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1235                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1236                 seq_printf(m, "Up threshold: %d%%\n",
1237                            dev_priv->rps.up_threshold);
1238
1239                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1240                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1241                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1242                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1243                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1244                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1245                 seq_printf(m, "Down threshold: %d%%\n",
1246                            dev_priv->rps.down_threshold);
1247
1248                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1249                             rp_state_cap >> 16) & 0xff;
1250                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1251                              GEN9_FREQ_SCALER : 1);
1252                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1253                            intel_gpu_freq(dev_priv, max_freq));
1254
1255                 max_freq = (rp_state_cap & 0xff00) >> 8;
1256                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1257                              GEN9_FREQ_SCALER : 1);
1258                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, max_freq));
1260
1261                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1262                             rp_state_cap >> 0) & 0xff;
1263                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1264                              GEN9_FREQ_SCALER : 1);
1265                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1266                            intel_gpu_freq(dev_priv, max_freq));
1267                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1268                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1269
1270                 seq_printf(m, "Current freq: %d MHz\n",
1271                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1272                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1273                 seq_printf(m, "Idle freq: %d MHz\n",
1274                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1275                 seq_printf(m, "Min freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1277                 seq_printf(m, "Boost freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1279                 seq_printf(m, "Max freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1281                 seq_printf(m,
1282                            "efficient (RPe) frequency: %d MHz\n",
1283                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1284         } else {
1285                 seq_puts(m, "no P-state info available\n");
1286         }
1287
1288         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1289         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1290         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1291
1292 out:
1293         intel_runtime_pm_put(dev_priv);
1294         return ret;
1295 }
1296
1297 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1298 {
1299         struct drm_info_node *node = m->private;
1300         struct drm_device *dev = node->minor->dev;
1301         struct drm_i915_private *dev_priv = to_i915(dev);
1302         struct intel_engine_cs *engine;
1303         u64 acthd[I915_NUM_ENGINES];
1304         u32 seqno[I915_NUM_ENGINES];
1305         u32 instdone[I915_NUM_INSTDONE_REG];
1306         enum intel_engine_id id;
1307         int j;
1308
1309         if (!i915.enable_hangcheck) {
1310                 seq_printf(m, "Hangcheck disabled\n");
1311                 return 0;
1312         }
1313
1314         intel_runtime_pm_get(dev_priv);
1315
1316         for_each_engine_id(engine, dev_priv, id) {
1317                 acthd[id] = intel_engine_get_active_head(engine);
1318                 seqno[id] = intel_engine_get_seqno(engine);
1319         }
1320
1321         i915_get_extra_instdone(dev_priv, instdone);
1322
1323         intel_runtime_pm_put(dev_priv);
1324
1325         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1326                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1327                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1328                                             jiffies));
1329         } else
1330                 seq_printf(m, "Hangcheck inactive\n");
1331
1332         for_each_engine_id(engine, dev_priv, id) {
1333                 seq_printf(m, "%s:\n", engine->name);
1334                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1335                            engine->hangcheck.seqno,
1336                            seqno[id],
1337                            engine->last_submitted_seqno);
1338                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1339                            yesno(intel_engine_has_waiter(engine)),
1340                            yesno(test_bit(engine->id,
1341                                           &dev_priv->gpu_error.missed_irq_rings)));
1342                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1343                            (long long)engine->hangcheck.acthd,
1344                            (long long)acthd[id]);
1345                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1346                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1347
1348                 if (engine->id == RCS) {
1349                         seq_puts(m, "\tinstdone read =");
1350
1351                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1352                                 seq_printf(m, " 0x%08x", instdone[j]);
1353
1354                         seq_puts(m, "\n\tinstdone accu =");
1355
1356                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1357                                 seq_printf(m, " 0x%08x",
1358                                            engine->hangcheck.instdone[j]);
1359
1360                         seq_puts(m, "\n");
1361                 }
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int ironlake_drpc_info(struct seq_file *m)
1368 {
1369         struct drm_info_node *node = m->private;
1370         struct drm_device *dev = node->minor->dev;
1371         struct drm_i915_private *dev_priv = to_i915(dev);
1372         u32 rgvmodectl, rstdbyctl;
1373         u16 crstandvid;
1374         int ret;
1375
1376         ret = mutex_lock_interruptible(&dev->struct_mutex);
1377         if (ret)
1378                 return ret;
1379         intel_runtime_pm_get(dev_priv);
1380
1381         rgvmodectl = I915_READ(MEMMODECTL);
1382         rstdbyctl = I915_READ(RSTDBYCTL);
1383         crstandvid = I915_READ16(CRSTANDVID);
1384
1385         intel_runtime_pm_put(dev_priv);
1386         mutex_unlock(&dev->struct_mutex);
1387
1388         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1389         seq_printf(m, "Boost freq: %d\n",
1390                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1391                    MEMMODE_BOOST_FREQ_SHIFT);
1392         seq_printf(m, "HW control enabled: %s\n",
1393                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1394         seq_printf(m, "SW control enabled: %s\n",
1395                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1396         seq_printf(m, "Gated voltage change: %s\n",
1397                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1398         seq_printf(m, "Starting frequency: P%d\n",
1399                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1400         seq_printf(m, "Max P-state: P%d\n",
1401                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1402         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1403         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1404         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1405         seq_printf(m, "Render standby enabled: %s\n",
1406                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1407         seq_puts(m, "Current RS state: ");
1408         switch (rstdbyctl & RSX_STATUS_MASK) {
1409         case RSX_STATUS_ON:
1410                 seq_puts(m, "on\n");
1411                 break;
1412         case RSX_STATUS_RC1:
1413                 seq_puts(m, "RC1\n");
1414                 break;
1415         case RSX_STATUS_RC1E:
1416                 seq_puts(m, "RC1E\n");
1417                 break;
1418         case RSX_STATUS_RS1:
1419                 seq_puts(m, "RS1\n");
1420                 break;
1421         case RSX_STATUS_RS2:
1422                 seq_puts(m, "RS2 (RC6)\n");
1423                 break;
1424         case RSX_STATUS_RS3:
1425                 seq_puts(m, "RC3 (RC6+)\n");
1426                 break;
1427         default:
1428                 seq_puts(m, "unknown\n");
1429                 break;
1430         }
1431
1432         return 0;
1433 }
1434
1435 static int i915_forcewake_domains(struct seq_file *m, void *data)
1436 {
1437         struct drm_info_node *node = m->private;
1438         struct drm_device *dev = node->minor->dev;
1439         struct drm_i915_private *dev_priv = to_i915(dev);
1440         struct intel_uncore_forcewake_domain *fw_domain;
1441
1442         spin_lock_irq(&dev_priv->uncore.lock);
1443         for_each_fw_domain(fw_domain, dev_priv) {
1444                 seq_printf(m, "%s.wake_count = %u\n",
1445                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1446                            fw_domain->wake_count);
1447         }
1448         spin_unlock_irq(&dev_priv->uncore.lock);
1449
1450         return 0;
1451 }
1452
1453 static int vlv_drpc_info(struct seq_file *m)
1454 {
1455         struct drm_info_node *node = m->private;
1456         struct drm_device *dev = node->minor->dev;
1457         struct drm_i915_private *dev_priv = to_i915(dev);
1458         u32 rpmodectl1, rcctl1, pw_status;
1459
1460         intel_runtime_pm_get(dev_priv);
1461
1462         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1463         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1464         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1465
1466         intel_runtime_pm_put(dev_priv);
1467
1468         seq_printf(m, "Video Turbo Mode: %s\n",
1469                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1470         seq_printf(m, "Turbo enabled: %s\n",
1471                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1472         seq_printf(m, "HW control enabled: %s\n",
1473                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1474         seq_printf(m, "SW control enabled: %s\n",
1475                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1476                           GEN6_RP_MEDIA_SW_MODE));
1477         seq_printf(m, "RC6 Enabled: %s\n",
1478                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1479                                         GEN6_RC_CTL_EI_MODE(1))));
1480         seq_printf(m, "Render Power Well: %s\n",
1481                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1482         seq_printf(m, "Media Power Well: %s\n",
1483                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1484
1485         seq_printf(m, "Render RC6 residency since boot: %u\n",
1486                    I915_READ(VLV_GT_RENDER_RC6));
1487         seq_printf(m, "Media RC6 residency since boot: %u\n",
1488                    I915_READ(VLV_GT_MEDIA_RC6));
1489
1490         return i915_forcewake_domains(m, NULL);
1491 }
1492
1493 static int gen6_drpc_info(struct seq_file *m)
1494 {
1495         struct drm_info_node *node = m->private;
1496         struct drm_device *dev = node->minor->dev;
1497         struct drm_i915_private *dev_priv = to_i915(dev);
1498         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1499         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1500         unsigned forcewake_count;
1501         int count = 0, ret;
1502
1503         ret = mutex_lock_interruptible(&dev->struct_mutex);
1504         if (ret)
1505                 return ret;
1506         intel_runtime_pm_get(dev_priv);
1507
1508         spin_lock_irq(&dev_priv->uncore.lock);
1509         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1510         spin_unlock_irq(&dev_priv->uncore.lock);
1511
1512         if (forcewake_count) {
1513                 seq_puts(m, "RC information inaccurate because somebody "
1514                             "holds a forcewake reference \n");
1515         } else {
1516                 /* NB: we cannot use forcewake, else we read the wrong values */
1517                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1518                         udelay(10);
1519                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1520         }
1521
1522         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1523         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1524
1525         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1526         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1527         if (INTEL_INFO(dev)->gen >= 9) {
1528                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1529                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1530         }
1531         mutex_unlock(&dev->struct_mutex);
1532         mutex_lock(&dev_priv->rps.hw_lock);
1533         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1534         mutex_unlock(&dev_priv->rps.hw_lock);
1535
1536         intel_runtime_pm_put(dev_priv);
1537
1538         seq_printf(m, "Video Turbo Mode: %s\n",
1539                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1540         seq_printf(m, "HW control enabled: %s\n",
1541                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1542         seq_printf(m, "SW control enabled: %s\n",
1543                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1544                           GEN6_RP_MEDIA_SW_MODE));
1545         seq_printf(m, "RC1e Enabled: %s\n",
1546                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1547         seq_printf(m, "RC6 Enabled: %s\n",
1548                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1549         if (INTEL_INFO(dev)->gen >= 9) {
1550                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1551                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1552                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1553                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1554         }
1555         seq_printf(m, "Deep RC6 Enabled: %s\n",
1556                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1557         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1558                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1559         seq_puts(m, "Current RC state: ");
1560         switch (gt_core_status & GEN6_RCn_MASK) {
1561         case GEN6_RC0:
1562                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1563                         seq_puts(m, "Core Power Down\n");
1564                 else
1565                         seq_puts(m, "on\n");
1566                 break;
1567         case GEN6_RC3:
1568                 seq_puts(m, "RC3\n");
1569                 break;
1570         case GEN6_RC6:
1571                 seq_puts(m, "RC6\n");
1572                 break;
1573         case GEN6_RC7:
1574                 seq_puts(m, "RC7\n");
1575                 break;
1576         default:
1577                 seq_puts(m, "Unknown\n");
1578                 break;
1579         }
1580
1581         seq_printf(m, "Core Power Down: %s\n",
1582                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1583         if (INTEL_INFO(dev)->gen >= 9) {
1584                 seq_printf(m, "Render Power Well: %s\n",
1585                         (gen9_powergate_status &
1586                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1587                 seq_printf(m, "Media Power Well: %s\n",
1588                         (gen9_powergate_status &
1589                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1590         }
1591
1592         /* Not exactly sure what this is */
1593         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1594                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1595         seq_printf(m, "RC6 residency since boot: %u\n",
1596                    I915_READ(GEN6_GT_GFX_RC6));
1597         seq_printf(m, "RC6+ residency since boot: %u\n",
1598                    I915_READ(GEN6_GT_GFX_RC6p));
1599         seq_printf(m, "RC6++ residency since boot: %u\n",
1600                    I915_READ(GEN6_GT_GFX_RC6pp));
1601
1602         seq_printf(m, "RC6   voltage: %dmV\n",
1603                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1604         seq_printf(m, "RC6+  voltage: %dmV\n",
1605                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1606         seq_printf(m, "RC6++ voltage: %dmV\n",
1607                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1608         return i915_forcewake_domains(m, NULL);
1609 }
1610
1611 static int i915_drpc_info(struct seq_file *m, void *unused)
1612 {
1613         struct drm_info_node *node = m->private;
1614         struct drm_device *dev = node->minor->dev;
1615
1616         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1617                 return vlv_drpc_info(m);
1618         else if (INTEL_INFO(dev)->gen >= 6)
1619                 return gen6_drpc_info(m);
1620         else
1621                 return ironlake_drpc_info(m);
1622 }
1623
1624 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1625 {
1626         struct drm_info_node *node = m->private;
1627         struct drm_device *dev = node->minor->dev;
1628         struct drm_i915_private *dev_priv = to_i915(dev);
1629
1630         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1631                    dev_priv->fb_tracking.busy_bits);
1632
1633         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1634                    dev_priv->fb_tracking.flip_bits);
1635
1636         return 0;
1637 }
1638
1639 static int i915_fbc_status(struct seq_file *m, void *unused)
1640 {
1641         struct drm_info_node *node = m->private;
1642         struct drm_device *dev = node->minor->dev;
1643         struct drm_i915_private *dev_priv = to_i915(dev);
1644
1645         if (!HAS_FBC(dev)) {
1646                 seq_puts(m, "FBC unsupported on this chipset\n");
1647                 return 0;
1648         }
1649
1650         intel_runtime_pm_get(dev_priv);
1651         mutex_lock(&dev_priv->fbc.lock);
1652
1653         if (intel_fbc_is_active(dev_priv))
1654                 seq_puts(m, "FBC enabled\n");
1655         else
1656                 seq_printf(m, "FBC disabled: %s\n",
1657                            dev_priv->fbc.no_fbc_reason);
1658
1659         if (INTEL_INFO(dev_priv)->gen >= 7)
1660                 seq_printf(m, "Compressing: %s\n",
1661                            yesno(I915_READ(FBC_STATUS2) &
1662                                  FBC_COMPRESSION_MASK));
1663
1664         mutex_unlock(&dev_priv->fbc.lock);
1665         intel_runtime_pm_put(dev_priv);
1666
1667         return 0;
1668 }
1669
1670 static int i915_fbc_fc_get(void *data, u64 *val)
1671 {
1672         struct drm_device *dev = data;
1673         struct drm_i915_private *dev_priv = to_i915(dev);
1674
1675         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1676                 return -ENODEV;
1677
1678         *val = dev_priv->fbc.false_color;
1679
1680         return 0;
1681 }
1682
1683 static int i915_fbc_fc_set(void *data, u64 val)
1684 {
1685         struct drm_device *dev = data;
1686         struct drm_i915_private *dev_priv = to_i915(dev);
1687         u32 reg;
1688
1689         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1690                 return -ENODEV;
1691
1692         mutex_lock(&dev_priv->fbc.lock);
1693
1694         reg = I915_READ(ILK_DPFC_CONTROL);
1695         dev_priv->fbc.false_color = val;
1696
1697         I915_WRITE(ILK_DPFC_CONTROL, val ?
1698                    (reg | FBC_CTL_FALSE_COLOR) :
1699                    (reg & ~FBC_CTL_FALSE_COLOR));
1700
1701         mutex_unlock(&dev_priv->fbc.lock);
1702         return 0;
1703 }
1704
1705 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1706                         i915_fbc_fc_get, i915_fbc_fc_set,
1707                         "%llu\n");
1708
1709 static int i915_ips_status(struct seq_file *m, void *unused)
1710 {
1711         struct drm_info_node *node = m->private;
1712         struct drm_device *dev = node->minor->dev;
1713         struct drm_i915_private *dev_priv = to_i915(dev);
1714
1715         if (!HAS_IPS(dev)) {
1716                 seq_puts(m, "not supported\n");
1717                 return 0;
1718         }
1719
1720         intel_runtime_pm_get(dev_priv);
1721
1722         seq_printf(m, "Enabled by kernel parameter: %s\n",
1723                    yesno(i915.enable_ips));
1724
1725         if (INTEL_INFO(dev)->gen >= 8) {
1726                 seq_puts(m, "Currently: unknown\n");
1727         } else {
1728                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1729                         seq_puts(m, "Currently: enabled\n");
1730                 else
1731                         seq_puts(m, "Currently: disabled\n");
1732         }
1733
1734         intel_runtime_pm_put(dev_priv);
1735
1736         return 0;
1737 }
1738
1739 static int i915_sr_status(struct seq_file *m, void *unused)
1740 {
1741         struct drm_info_node *node = m->private;
1742         struct drm_device *dev = node->minor->dev;
1743         struct drm_i915_private *dev_priv = to_i915(dev);
1744         bool sr_enabled = false;
1745
1746         intel_runtime_pm_get(dev_priv);
1747
1748         if (HAS_PCH_SPLIT(dev))
1749                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1750         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1751                  IS_I945G(dev) || IS_I945GM(dev))
1752                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1753         else if (IS_I915GM(dev))
1754                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1755         else if (IS_PINEVIEW(dev))
1756                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1757         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1758                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1759
1760         intel_runtime_pm_put(dev_priv);
1761
1762         seq_printf(m, "self-refresh: %s\n",
1763                    sr_enabled ? "enabled" : "disabled");
1764
1765         return 0;
1766 }
1767
1768 static int i915_emon_status(struct seq_file *m, void *unused)
1769 {
1770         struct drm_info_node *node = m->private;
1771         struct drm_device *dev = node->minor->dev;
1772         struct drm_i915_private *dev_priv = to_i915(dev);
1773         unsigned long temp, chipset, gfx;
1774         int ret;
1775
1776         if (!IS_GEN5(dev))
1777                 return -ENODEV;
1778
1779         ret = mutex_lock_interruptible(&dev->struct_mutex);
1780         if (ret)
1781                 return ret;
1782
1783         temp = i915_mch_val(dev_priv);
1784         chipset = i915_chipset_val(dev_priv);
1785         gfx = i915_gfx_val(dev_priv);
1786         mutex_unlock(&dev->struct_mutex);
1787
1788         seq_printf(m, "GMCH temp: %ld\n", temp);
1789         seq_printf(m, "Chipset power: %ld\n", chipset);
1790         seq_printf(m, "GFX power: %ld\n", gfx);
1791         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1792
1793         return 0;
1794 }
1795
1796 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1797 {
1798         struct drm_info_node *node = m->private;
1799         struct drm_device *dev = node->minor->dev;
1800         struct drm_i915_private *dev_priv = to_i915(dev);
1801         int ret = 0;
1802         int gpu_freq, ia_freq;
1803         unsigned int max_gpu_freq, min_gpu_freq;
1804
1805         if (!HAS_CORE_RING_FREQ(dev)) {
1806                 seq_puts(m, "unsupported on this chipset\n");
1807                 return 0;
1808         }
1809
1810         intel_runtime_pm_get(dev_priv);
1811
1812         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1813         if (ret)
1814                 goto out;
1815
1816         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1817                 /* Convert GT frequency to 50 HZ units */
1818                 min_gpu_freq =
1819                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1820                 max_gpu_freq =
1821                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1822         } else {
1823                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1824                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1825         }
1826
1827         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1828
1829         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1830                 ia_freq = gpu_freq;
1831                 sandybridge_pcode_read(dev_priv,
1832                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1833                                        &ia_freq);
1834                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1835                            intel_gpu_freq(dev_priv, (gpu_freq *
1836                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1837                                  GEN9_FREQ_SCALER : 1))),
1838                            ((ia_freq >> 0) & 0xff) * 100,
1839                            ((ia_freq >> 8) & 0xff) * 100);
1840         }
1841
1842         mutex_unlock(&dev_priv->rps.hw_lock);
1843
1844 out:
1845         intel_runtime_pm_put(dev_priv);
1846         return ret;
1847 }
1848
1849 static int i915_opregion(struct seq_file *m, void *unused)
1850 {
1851         struct drm_info_node *node = m->private;
1852         struct drm_device *dev = node->minor->dev;
1853         struct drm_i915_private *dev_priv = to_i915(dev);
1854         struct intel_opregion *opregion = &dev_priv->opregion;
1855         int ret;
1856
1857         ret = mutex_lock_interruptible(&dev->struct_mutex);
1858         if (ret)
1859                 goto out;
1860
1861         if (opregion->header)
1862                 seq_write(m, opregion->header, OPREGION_SIZE);
1863
1864         mutex_unlock(&dev->struct_mutex);
1865
1866 out:
1867         return 0;
1868 }
1869
1870 static int i915_vbt(struct seq_file *m, void *unused)
1871 {
1872         struct drm_info_node *node = m->private;
1873         struct drm_device *dev = node->minor->dev;
1874         struct drm_i915_private *dev_priv = to_i915(dev);
1875         struct intel_opregion *opregion = &dev_priv->opregion;
1876
1877         if (opregion->vbt)
1878                 seq_write(m, opregion->vbt, opregion->vbt_size);
1879
1880         return 0;
1881 }
1882
1883 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1884 {
1885         struct drm_info_node *node = m->private;
1886         struct drm_device *dev = node->minor->dev;
1887         struct intel_framebuffer *fbdev_fb = NULL;
1888         struct drm_framebuffer *drm_fb;
1889         int ret;
1890
1891         ret = mutex_lock_interruptible(&dev->struct_mutex);
1892         if (ret)
1893                 return ret;
1894
1895 #ifdef CONFIG_DRM_FBDEV_EMULATION
1896         if (to_i915(dev)->fbdev) {
1897                 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1898
1899                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1900                            fbdev_fb->base.width,
1901                            fbdev_fb->base.height,
1902                            fbdev_fb->base.depth,
1903                            fbdev_fb->base.bits_per_pixel,
1904                            fbdev_fb->base.modifier[0],
1905                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1906                 describe_obj(m, fbdev_fb->obj);
1907                 seq_putc(m, '\n');
1908         }
1909 #endif
1910
1911         mutex_lock(&dev->mode_config.fb_lock);
1912         drm_for_each_fb(drm_fb, dev) {
1913                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1914                 if (fb == fbdev_fb)
1915                         continue;
1916
1917                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1918                            fb->base.width,
1919                            fb->base.height,
1920                            fb->base.depth,
1921                            fb->base.bits_per_pixel,
1922                            fb->base.modifier[0],
1923                            drm_framebuffer_read_refcount(&fb->base));
1924                 describe_obj(m, fb->obj);
1925                 seq_putc(m, '\n');
1926         }
1927         mutex_unlock(&dev->mode_config.fb_lock);
1928         mutex_unlock(&dev->struct_mutex);
1929
1930         return 0;
1931 }
1932
1933 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1934 {
1935         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1936                    ring->space, ring->head, ring->tail,
1937                    ring->last_retired_head);
1938 }
1939
1940 static int i915_context_status(struct seq_file *m, void *unused)
1941 {
1942         struct drm_info_node *node = m->private;
1943         struct drm_device *dev = node->minor->dev;
1944         struct drm_i915_private *dev_priv = to_i915(dev);
1945         struct intel_engine_cs *engine;
1946         struct i915_gem_context *ctx;
1947         int ret;
1948
1949         ret = mutex_lock_interruptible(&dev->struct_mutex);
1950         if (ret)
1951                 return ret;
1952
1953         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1954                 seq_printf(m, "HW context %u ", ctx->hw_id);
1955                 if (IS_ERR(ctx->file_priv)) {
1956                         seq_puts(m, "(deleted) ");
1957                 } else if (ctx->file_priv) {
1958                         struct pid *pid = ctx->file_priv->file->pid;
1959                         struct task_struct *task;
1960
1961                         task = get_pid_task(pid, PIDTYPE_PID);
1962                         if (task) {
1963                                 seq_printf(m, "(%s [%d]) ",
1964                                            task->comm, task->pid);
1965                                 put_task_struct(task);
1966                         }
1967                 } else {
1968                         seq_puts(m, "(kernel) ");
1969                 }
1970
1971                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1972                 seq_putc(m, '\n');
1973
1974                 for_each_engine(engine, dev_priv) {
1975                         struct intel_context *ce = &ctx->engine[engine->id];
1976
1977                         seq_printf(m, "%s: ", engine->name);
1978                         seq_putc(m, ce->initialised ? 'I' : 'i');
1979                         if (ce->state)
1980                                 describe_obj(m, ce->state->obj);
1981                         if (ce->ring)
1982                                 describe_ctx_ring(m, ce->ring);
1983                         seq_putc(m, '\n');
1984                 }
1985
1986                 seq_putc(m, '\n');
1987         }
1988
1989         mutex_unlock(&dev->struct_mutex);
1990
1991         return 0;
1992 }
1993
1994 static void i915_dump_lrc_obj(struct seq_file *m,
1995                               struct i915_gem_context *ctx,
1996                               struct intel_engine_cs *engine)
1997 {
1998         struct i915_vma *vma = ctx->engine[engine->id].state;
1999         struct page *page;
2000         int j;
2001
2002         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2003
2004         if (!vma) {
2005                 seq_puts(m, "\tFake context\n");
2006                 return;
2007         }
2008
2009         if (vma->flags & I915_VMA_GLOBAL_BIND)
2010                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2011                            lower_32_bits(vma->node.start));
2012
2013         if (i915_gem_object_get_pages(vma->obj)) {
2014                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2015                 return;
2016         }
2017
2018         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2019         if (page) {
2020                 u32 *reg_state = kmap_atomic(page);
2021
2022                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2023                         seq_printf(m,
2024                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2025                                    j * 4,
2026                                    reg_state[j], reg_state[j + 1],
2027                                    reg_state[j + 2], reg_state[j + 3]);
2028                 }
2029                 kunmap_atomic(reg_state);
2030         }
2031
2032         seq_putc(m, '\n');
2033 }
2034
2035 static int i915_dump_lrc(struct seq_file *m, void *unused)
2036 {
2037         struct drm_info_node *node = (struct drm_info_node *) m->private;
2038         struct drm_device *dev = node->minor->dev;
2039         struct drm_i915_private *dev_priv = to_i915(dev);
2040         struct intel_engine_cs *engine;
2041         struct i915_gem_context *ctx;
2042         int ret;
2043
2044         if (!i915.enable_execlists) {
2045                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2046                 return 0;
2047         }
2048
2049         ret = mutex_lock_interruptible(&dev->struct_mutex);
2050         if (ret)
2051                 return ret;
2052
2053         list_for_each_entry(ctx, &dev_priv->context_list, link)
2054                 for_each_engine(engine, dev_priv)
2055                         i915_dump_lrc_obj(m, ctx, engine);
2056
2057         mutex_unlock(&dev->struct_mutex);
2058
2059         return 0;
2060 }
2061
2062 static int i915_execlists(struct seq_file *m, void *data)
2063 {
2064         struct drm_info_node *node = (struct drm_info_node *)m->private;
2065         struct drm_device *dev = node->minor->dev;
2066         struct drm_i915_private *dev_priv = to_i915(dev);
2067         struct intel_engine_cs *engine;
2068         u32 status_pointer;
2069         u8 read_pointer;
2070         u8 write_pointer;
2071         u32 status;
2072         u32 ctx_id;
2073         struct list_head *cursor;
2074         int i, ret;
2075
2076         if (!i915.enable_execlists) {
2077                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2078                 return 0;
2079         }
2080
2081         ret = mutex_lock_interruptible(&dev->struct_mutex);
2082         if (ret)
2083                 return ret;
2084
2085         intel_runtime_pm_get(dev_priv);
2086
2087         for_each_engine(engine, dev_priv) {
2088                 struct drm_i915_gem_request *head_req = NULL;
2089                 int count = 0;
2090
2091                 seq_printf(m, "%s\n", engine->name);
2092
2093                 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2094                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2095                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2096                            status, ctx_id);
2097
2098                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2099                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2100
2101                 read_pointer = engine->next_context_status_buffer;
2102                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2103                 if (read_pointer > write_pointer)
2104                         write_pointer += GEN8_CSB_ENTRIES;
2105                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2106                            read_pointer, write_pointer);
2107
2108                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2109                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2110                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2111
2112                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2113                                    i, status, ctx_id);
2114                 }
2115
2116                 spin_lock_bh(&engine->execlist_lock);
2117                 list_for_each(cursor, &engine->execlist_queue)
2118                         count++;
2119                 head_req = list_first_entry_or_null(&engine->execlist_queue,
2120                                                     struct drm_i915_gem_request,
2121                                                     execlist_link);
2122                 spin_unlock_bh(&engine->execlist_lock);
2123
2124                 seq_printf(m, "\t%d requests in queue\n", count);
2125                 if (head_req) {
2126                         seq_printf(m, "\tHead request context: %u\n",
2127                                    head_req->ctx->hw_id);
2128                         seq_printf(m, "\tHead request tail: %u\n",
2129                                    head_req->tail);
2130                 }
2131
2132                 seq_putc(m, '\n');
2133         }
2134
2135         intel_runtime_pm_put(dev_priv);
2136         mutex_unlock(&dev->struct_mutex);
2137
2138         return 0;
2139 }
2140
2141 static const char *swizzle_string(unsigned swizzle)
2142 {
2143         switch (swizzle) {
2144         case I915_BIT_6_SWIZZLE_NONE:
2145                 return "none";
2146         case I915_BIT_6_SWIZZLE_9:
2147                 return "bit9";
2148         case I915_BIT_6_SWIZZLE_9_10:
2149                 return "bit9/bit10";
2150         case I915_BIT_6_SWIZZLE_9_11:
2151                 return "bit9/bit11";
2152         case I915_BIT_6_SWIZZLE_9_10_11:
2153                 return "bit9/bit10/bit11";
2154         case I915_BIT_6_SWIZZLE_9_17:
2155                 return "bit9/bit17";
2156         case I915_BIT_6_SWIZZLE_9_10_17:
2157                 return "bit9/bit10/bit17";
2158         case I915_BIT_6_SWIZZLE_UNKNOWN:
2159                 return "unknown";
2160         }
2161
2162         return "bug";
2163 }
2164
2165 static int i915_swizzle_info(struct seq_file *m, void *data)
2166 {
2167         struct drm_info_node *node = m->private;
2168         struct drm_device *dev = node->minor->dev;
2169         struct drm_i915_private *dev_priv = to_i915(dev);
2170         int ret;
2171
2172         ret = mutex_lock_interruptible(&dev->struct_mutex);
2173         if (ret)
2174                 return ret;
2175         intel_runtime_pm_get(dev_priv);
2176
2177         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2178                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2179         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2180                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2181
2182         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2183                 seq_printf(m, "DDC = 0x%08x\n",
2184                            I915_READ(DCC));
2185                 seq_printf(m, "DDC2 = 0x%08x\n",
2186                            I915_READ(DCC2));
2187                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2188                            I915_READ16(C0DRB3));
2189                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2190                            I915_READ16(C1DRB3));
2191         } else if (INTEL_INFO(dev)->gen >= 6) {
2192                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2193                            I915_READ(MAD_DIMM_C0));
2194                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2195                            I915_READ(MAD_DIMM_C1));
2196                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2197                            I915_READ(MAD_DIMM_C2));
2198                 seq_printf(m, "TILECTL = 0x%08x\n",
2199                            I915_READ(TILECTL));
2200                 if (INTEL_INFO(dev)->gen >= 8)
2201                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2202                                    I915_READ(GAMTARBMODE));
2203                 else
2204                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2205                                    I915_READ(ARB_MODE));
2206                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2207                            I915_READ(DISP_ARB_CTL));
2208         }
2209
2210         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2211                 seq_puts(m, "L-shaped memory detected\n");
2212
2213         intel_runtime_pm_put(dev_priv);
2214         mutex_unlock(&dev->struct_mutex);
2215
2216         return 0;
2217 }
2218
2219 static int per_file_ctx(int id, void *ptr, void *data)
2220 {
2221         struct i915_gem_context *ctx = ptr;
2222         struct seq_file *m = data;
2223         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2224
2225         if (!ppgtt) {
2226                 seq_printf(m, "  no ppgtt for context %d\n",
2227                            ctx->user_handle);
2228                 return 0;
2229         }
2230
2231         if (i915_gem_context_is_default(ctx))
2232                 seq_puts(m, "  default context:\n");
2233         else
2234                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2235         ppgtt->debug_dump(ppgtt, m);
2236
2237         return 0;
2238 }
2239
2240 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2241 {
2242         struct drm_i915_private *dev_priv = to_i915(dev);
2243         struct intel_engine_cs *engine;
2244         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2245         int i;
2246
2247         if (!ppgtt)
2248                 return;
2249
2250         for_each_engine(engine, dev_priv) {
2251                 seq_printf(m, "%s\n", engine->name);
2252                 for (i = 0; i < 4; i++) {
2253                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2254                         pdp <<= 32;
2255                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2256                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2257                 }
2258         }
2259 }
2260
2261 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(dev);
2264         struct intel_engine_cs *engine;
2265
2266         if (IS_GEN6(dev_priv))
2267                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2268
2269         for_each_engine(engine, dev_priv) {
2270                 seq_printf(m, "%s\n", engine->name);
2271                 if (IS_GEN7(dev_priv))
2272                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2273                                    I915_READ(RING_MODE_GEN7(engine)));
2274                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2275                            I915_READ(RING_PP_DIR_BASE(engine)));
2276                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2277                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2278                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2279                            I915_READ(RING_PP_DIR_DCLV(engine)));
2280         }
2281         if (dev_priv->mm.aliasing_ppgtt) {
2282                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2283
2284                 seq_puts(m, "aliasing PPGTT:\n");
2285                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2286
2287                 ppgtt->debug_dump(ppgtt, m);
2288         }
2289
2290         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2291 }
2292
2293 static int i915_ppgtt_info(struct seq_file *m, void *data)
2294 {
2295         struct drm_info_node *node = m->private;
2296         struct drm_device *dev = node->minor->dev;
2297         struct drm_i915_private *dev_priv = to_i915(dev);
2298         struct drm_file *file;
2299
2300         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2301         if (ret)
2302                 return ret;
2303         intel_runtime_pm_get(dev_priv);
2304
2305         if (INTEL_INFO(dev)->gen >= 8)
2306                 gen8_ppgtt_info(m, dev);
2307         else if (INTEL_INFO(dev)->gen >= 6)
2308                 gen6_ppgtt_info(m, dev);
2309
2310         mutex_lock(&dev->filelist_mutex);
2311         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2312                 struct drm_i915_file_private *file_priv = file->driver_priv;
2313                 struct task_struct *task;
2314
2315                 task = get_pid_task(file->pid, PIDTYPE_PID);
2316                 if (!task) {
2317                         ret = -ESRCH;
2318                         goto out_unlock;
2319                 }
2320                 seq_printf(m, "\nproc: %s\n", task->comm);
2321                 put_task_struct(task);
2322                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2323                              (void *)(unsigned long)m);
2324         }
2325 out_unlock:
2326         mutex_unlock(&dev->filelist_mutex);
2327
2328         intel_runtime_pm_put(dev_priv);
2329         mutex_unlock(&dev->struct_mutex);
2330
2331         return ret;
2332 }
2333
2334 static int count_irq_waiters(struct drm_i915_private *i915)
2335 {
2336         struct intel_engine_cs *engine;
2337         int count = 0;
2338
2339         for_each_engine(engine, i915)
2340                 count += intel_engine_has_waiter(engine);
2341
2342         return count;
2343 }
2344
2345 static const char *rps_power_to_str(unsigned int power)
2346 {
2347         static const char * const strings[] = {
2348                 [LOW_POWER] = "low power",
2349                 [BETWEEN] = "mixed",
2350                 [HIGH_POWER] = "high power",
2351         };
2352
2353         if (power >= ARRAY_SIZE(strings) || !strings[power])
2354                 return "unknown";
2355
2356         return strings[power];
2357 }
2358
2359 static int i915_rps_boost_info(struct seq_file *m, void *data)
2360 {
2361         struct drm_info_node *node = m->private;
2362         struct drm_device *dev = node->minor->dev;
2363         struct drm_i915_private *dev_priv = to_i915(dev);
2364         struct drm_file *file;
2365
2366         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2367         seq_printf(m, "GPU busy? %s [%x]\n",
2368                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2369         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2370         seq_printf(m, "Frequency requested %d\n",
2371                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2372         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2373                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2374                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2375                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2376                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2377         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2378                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2379                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2380                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2381
2382         mutex_lock(&dev->filelist_mutex);
2383         spin_lock(&dev_priv->rps.client_lock);
2384         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2385                 struct drm_i915_file_private *file_priv = file->driver_priv;
2386                 struct task_struct *task;
2387
2388                 rcu_read_lock();
2389                 task = pid_task(file->pid, PIDTYPE_PID);
2390                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2391                            task ? task->comm : "<unknown>",
2392                            task ? task->pid : -1,
2393                            file_priv->rps.boosts,
2394                            list_empty(&file_priv->rps.link) ? "" : ", active");
2395                 rcu_read_unlock();
2396         }
2397         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2398         spin_unlock(&dev_priv->rps.client_lock);
2399         mutex_unlock(&dev->filelist_mutex);
2400
2401         if (INTEL_GEN(dev_priv) >= 6 &&
2402             dev_priv->rps.enabled &&
2403             dev_priv->gt.active_engines) {
2404                 u32 rpup, rpupei;
2405                 u32 rpdown, rpdownei;
2406
2407                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2408                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2409                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2410                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2411                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2412                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2413
2414                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2415                            rps_power_to_str(dev_priv->rps.power));
2416                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2417                            100 * rpup / rpupei,
2418                            dev_priv->rps.up_threshold);
2419                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2420                            100 * rpdown / rpdownei,
2421                            dev_priv->rps.down_threshold);
2422         } else {
2423                 seq_puts(m, "\nRPS Autotuning inactive\n");
2424         }
2425
2426         return 0;
2427 }
2428
2429 static int i915_llc(struct seq_file *m, void *data)
2430 {
2431         struct drm_info_node *node = m->private;
2432         struct drm_device *dev = node->minor->dev;
2433         struct drm_i915_private *dev_priv = to_i915(dev);
2434         const bool edram = INTEL_GEN(dev_priv) > 8;
2435
2436         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2437         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2438                    intel_uncore_edram_size(dev_priv)/1024/1024);
2439
2440         return 0;
2441 }
2442
2443 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2444 {
2445         struct drm_info_node *node = m->private;
2446         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2447         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2448         u32 tmp, i;
2449
2450         if (!HAS_GUC_UCODE(dev_priv))
2451                 return 0;
2452
2453         seq_printf(m, "GuC firmware status:\n");
2454         seq_printf(m, "\tpath: %s\n",
2455                 guc_fw->guc_fw_path);
2456         seq_printf(m, "\tfetch: %s\n",
2457                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2458         seq_printf(m, "\tload: %s\n",
2459                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2460         seq_printf(m, "\tversion wanted: %d.%d\n",
2461                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2462         seq_printf(m, "\tversion found: %d.%d\n",
2463                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2464         seq_printf(m, "\theader: offset is %d; size = %d\n",
2465                 guc_fw->header_offset, guc_fw->header_size);
2466         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2467                 guc_fw->ucode_offset, guc_fw->ucode_size);
2468         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2469                 guc_fw->rsa_offset, guc_fw->rsa_size);
2470
2471         tmp = I915_READ(GUC_STATUS);
2472
2473         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2474         seq_printf(m, "\tBootrom status = 0x%x\n",
2475                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2476         seq_printf(m, "\tuKernel status = 0x%x\n",
2477                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2478         seq_printf(m, "\tMIA Core status = 0x%x\n",
2479                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2480         seq_puts(m, "\nScratch registers:\n");
2481         for (i = 0; i < 16; i++)
2482                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2483
2484         return 0;
2485 }
2486
2487 static void i915_guc_client_info(struct seq_file *m,
2488                                  struct drm_i915_private *dev_priv,
2489                                  struct i915_guc_client *client)
2490 {
2491         struct intel_engine_cs *engine;
2492         enum intel_engine_id id;
2493         uint64_t tot = 0;
2494
2495         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2496                 client->priority, client->ctx_index, client->proc_desc_offset);
2497         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2498                 client->doorbell_id, client->doorbell_offset, client->cookie);
2499         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2500                 client->wq_size, client->wq_offset, client->wq_tail);
2501
2502         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2503         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2504         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2505
2506         for_each_engine_id(engine, dev_priv, id) {
2507                 u64 submissions = client->submissions[id];
2508                 tot += submissions;
2509                 seq_printf(m, "\tSubmissions: %llu %s\n",
2510                                 submissions, engine->name);
2511         }
2512         seq_printf(m, "\tTotal: %llu\n", tot);
2513 }
2514
2515 static int i915_guc_info(struct seq_file *m, void *data)
2516 {
2517         struct drm_info_node *node = m->private;
2518         struct drm_device *dev = node->minor->dev;
2519         struct drm_i915_private *dev_priv = to_i915(dev);
2520         struct intel_guc guc;
2521         struct i915_guc_client client = {};
2522         struct intel_engine_cs *engine;
2523         enum intel_engine_id id;
2524         u64 total = 0;
2525
2526         if (!HAS_GUC_SCHED(dev_priv))
2527                 return 0;
2528
2529         if (mutex_lock_interruptible(&dev->struct_mutex))
2530                 return 0;
2531
2532         /* Take a local copy of the GuC data, so we can dump it at leisure */
2533         guc = dev_priv->guc;
2534         if (guc.execbuf_client)
2535                 client = *guc.execbuf_client;
2536
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         seq_printf(m, "Doorbell map:\n");
2540         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2541         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2542
2543         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2544         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2545         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2546         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2547         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2548
2549         seq_printf(m, "\nGuC submissions:\n");
2550         for_each_engine_id(engine, dev_priv, id) {
2551                 u64 submissions = guc.submissions[id];
2552                 total += submissions;
2553                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2554                         engine->name, submissions, guc.last_seqno[id]);
2555         }
2556         seq_printf(m, "\t%s: %llu\n", "Total", total);
2557
2558         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2559         i915_guc_client_info(m, dev_priv, &client);
2560
2561         /* Add more as required ... */
2562
2563         return 0;
2564 }
2565
2566 static int i915_guc_log_dump(struct seq_file *m, void *data)
2567 {
2568         struct drm_info_node *node = m->private;
2569         struct drm_device *dev = node->minor->dev;
2570         struct drm_i915_private *dev_priv = to_i915(dev);
2571         struct drm_i915_gem_object *obj;
2572         int i = 0, pg;
2573
2574         if (!dev_priv->guc.log_vma)
2575                 return 0;
2576
2577         obj = dev_priv->guc.log_vma->obj;
2578         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2579                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2580
2581                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2582                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2583                                    *(log + i), *(log + i + 1),
2584                                    *(log + i + 2), *(log + i + 3));
2585
2586                 kunmap_atomic(log);
2587         }
2588
2589         seq_putc(m, '\n');
2590
2591         return 0;
2592 }
2593
2594 static int i915_edp_psr_status(struct seq_file *m, void *data)
2595 {
2596         struct drm_info_node *node = m->private;
2597         struct drm_device *dev = node->minor->dev;
2598         struct drm_i915_private *dev_priv = to_i915(dev);
2599         u32 psrperf = 0;
2600         u32 stat[3];
2601         enum pipe pipe;
2602         bool enabled = false;
2603
2604         if (!HAS_PSR(dev)) {
2605                 seq_puts(m, "PSR not supported\n");
2606                 return 0;
2607         }
2608
2609         intel_runtime_pm_get(dev_priv);
2610
2611         mutex_lock(&dev_priv->psr.lock);
2612         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2613         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2614         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2615         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2616         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2617                    dev_priv->psr.busy_frontbuffer_bits);
2618         seq_printf(m, "Re-enable work scheduled: %s\n",
2619                    yesno(work_busy(&dev_priv->psr.work.work)));
2620
2621         if (HAS_DDI(dev))
2622                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2623         else {
2624                 for_each_pipe(dev_priv, pipe) {
2625                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2626                                 VLV_EDP_PSR_CURR_STATE_MASK;
2627                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2628                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2629                                 enabled = true;
2630                 }
2631         }
2632
2633         seq_printf(m, "Main link in standby mode: %s\n",
2634                    yesno(dev_priv->psr.link_standby));
2635
2636         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2637
2638         if (!HAS_DDI(dev))
2639                 for_each_pipe(dev_priv, pipe) {
2640                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2641                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2642                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2643                 }
2644         seq_puts(m, "\n");
2645
2646         /*
2647          * VLV/CHV PSR has no kind of performance counter
2648          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2649          */
2650         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2651                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2652                         EDP_PSR_PERF_CNT_MASK;
2653
2654                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2655         }
2656         mutex_unlock(&dev_priv->psr.lock);
2657
2658         intel_runtime_pm_put(dev_priv);
2659         return 0;
2660 }
2661
2662 static int i915_sink_crc(struct seq_file *m, void *data)
2663 {
2664         struct drm_info_node *node = m->private;
2665         struct drm_device *dev = node->minor->dev;
2666         struct intel_connector *connector;
2667         struct intel_dp *intel_dp = NULL;
2668         int ret;
2669         u8 crc[6];
2670
2671         drm_modeset_lock_all(dev);
2672         for_each_intel_connector(dev, connector) {
2673                 struct drm_crtc *crtc;
2674
2675                 if (!connector->base.state->best_encoder)
2676                         continue;
2677
2678                 crtc = connector->base.state->crtc;
2679                 if (!crtc->state->active)
2680                         continue;
2681
2682                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2683                         continue;
2684
2685                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2686
2687                 ret = intel_dp_sink_crc(intel_dp, crc);
2688                 if (ret)
2689                         goto out;
2690
2691                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2692                            crc[0], crc[1], crc[2],
2693                            crc[3], crc[4], crc[5]);
2694                 goto out;
2695         }
2696         ret = -ENODEV;
2697 out:
2698         drm_modeset_unlock_all(dev);
2699         return ret;
2700 }
2701
2702 static int i915_energy_uJ(struct seq_file *m, void *data)
2703 {
2704         struct drm_info_node *node = m->private;
2705         struct drm_device *dev = node->minor->dev;
2706         struct drm_i915_private *dev_priv = to_i915(dev);
2707         u64 power;
2708         u32 units;
2709
2710         if (INTEL_INFO(dev)->gen < 6)
2711                 return -ENODEV;
2712
2713         intel_runtime_pm_get(dev_priv);
2714
2715         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2716         power = (power & 0x1f00) >> 8;
2717         units = 1000000 / (1 << power); /* convert to uJ */
2718         power = I915_READ(MCH_SECP_NRG_STTS);
2719         power *= units;
2720
2721         intel_runtime_pm_put(dev_priv);
2722
2723         seq_printf(m, "%llu", (long long unsigned)power);
2724
2725         return 0;
2726 }
2727
2728 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2729 {
2730         struct drm_info_node *node = m->private;
2731         struct drm_device *dev = node->minor->dev;
2732         struct drm_i915_private *dev_priv = to_i915(dev);
2733
2734         if (!HAS_RUNTIME_PM(dev_priv))
2735                 seq_puts(m, "Runtime power management not supported\n");
2736
2737         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2738         seq_printf(m, "IRQs disabled: %s\n",
2739                    yesno(!intel_irqs_enabled(dev_priv)));
2740 #ifdef CONFIG_PM
2741         seq_printf(m, "Usage count: %d\n",
2742                    atomic_read(&dev->dev->power.usage_count));
2743 #else
2744         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2745 #endif
2746         seq_printf(m, "PCI device power state: %s [%d]\n",
2747                    pci_power_name(dev_priv->drm.pdev->current_state),
2748                    dev_priv->drm.pdev->current_state);
2749
2750         return 0;
2751 }
2752
2753 static int i915_power_domain_info(struct seq_file *m, void *unused)
2754 {
2755         struct drm_info_node *node = m->private;
2756         struct drm_device *dev = node->minor->dev;
2757         struct drm_i915_private *dev_priv = to_i915(dev);
2758         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2759         int i;
2760
2761         mutex_lock(&power_domains->lock);
2762
2763         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2764         for (i = 0; i < power_domains->power_well_count; i++) {
2765                 struct i915_power_well *power_well;
2766                 enum intel_display_power_domain power_domain;
2767
2768                 power_well = &power_domains->power_wells[i];
2769                 seq_printf(m, "%-25s %d\n", power_well->name,
2770                            power_well->count);
2771
2772                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2773                      power_domain++) {
2774                         if (!(BIT(power_domain) & power_well->domains))
2775                                 continue;
2776
2777                         seq_printf(m, "  %-23s %d\n",
2778                                  intel_display_power_domain_str(power_domain),
2779                                  power_domains->domain_use_count[power_domain]);
2780                 }
2781         }
2782
2783         mutex_unlock(&power_domains->lock);
2784
2785         return 0;
2786 }
2787
2788 static int i915_dmc_info(struct seq_file *m, void *unused)
2789 {
2790         struct drm_info_node *node = m->private;
2791         struct drm_device *dev = node->minor->dev;
2792         struct drm_i915_private *dev_priv = to_i915(dev);
2793         struct intel_csr *csr;
2794
2795         if (!HAS_CSR(dev)) {
2796                 seq_puts(m, "not supported\n");
2797                 return 0;
2798         }
2799
2800         csr = &dev_priv->csr;
2801
2802         intel_runtime_pm_get(dev_priv);
2803
2804         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2805         seq_printf(m, "path: %s\n", csr->fw_path);
2806
2807         if (!csr->dmc_payload)
2808                 goto out;
2809
2810         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2811                    CSR_VERSION_MINOR(csr->version));
2812
2813         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2814                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2815                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2816                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2817                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2818         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2819                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2820                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2821         }
2822
2823 out:
2824         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2825         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2826         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2827
2828         intel_runtime_pm_put(dev_priv);
2829
2830         return 0;
2831 }
2832
2833 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2834                                  struct drm_display_mode *mode)
2835 {
2836         int i;
2837
2838         for (i = 0; i < tabs; i++)
2839                 seq_putc(m, '\t');
2840
2841         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2842                    mode->base.id, mode->name,
2843                    mode->vrefresh, mode->clock,
2844                    mode->hdisplay, mode->hsync_start,
2845                    mode->hsync_end, mode->htotal,
2846                    mode->vdisplay, mode->vsync_start,
2847                    mode->vsync_end, mode->vtotal,
2848                    mode->type, mode->flags);
2849 }
2850
2851 static void intel_encoder_info(struct seq_file *m,
2852                                struct intel_crtc *intel_crtc,
2853                                struct intel_encoder *intel_encoder)
2854 {
2855         struct drm_info_node *node = m->private;
2856         struct drm_device *dev = node->minor->dev;
2857         struct drm_crtc *crtc = &intel_crtc->base;
2858         struct intel_connector *intel_connector;
2859         struct drm_encoder *encoder;
2860
2861         encoder = &intel_encoder->base;
2862         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2863                    encoder->base.id, encoder->name);
2864         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2865                 struct drm_connector *connector = &intel_connector->base;
2866                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2867                            connector->base.id,
2868                            connector->name,
2869                            drm_get_connector_status_name(connector->status));
2870                 if (connector->status == connector_status_connected) {
2871                         struct drm_display_mode *mode = &crtc->mode;
2872                         seq_printf(m, ", mode:\n");
2873                         intel_seq_print_mode(m, 2, mode);
2874                 } else {
2875                         seq_putc(m, '\n');
2876                 }
2877         }
2878 }
2879
2880 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2881 {
2882         struct drm_info_node *node = m->private;
2883         struct drm_device *dev = node->minor->dev;
2884         struct drm_crtc *crtc = &intel_crtc->base;
2885         struct intel_encoder *intel_encoder;
2886         struct drm_plane_state *plane_state = crtc->primary->state;
2887         struct drm_framebuffer *fb = plane_state->fb;
2888
2889         if (fb)
2890                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2891                            fb->base.id, plane_state->src_x >> 16,
2892                            plane_state->src_y >> 16, fb->width, fb->height);
2893         else
2894                 seq_puts(m, "\tprimary plane disabled\n");
2895         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2896                 intel_encoder_info(m, intel_crtc, intel_encoder);
2897 }
2898
2899 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2900 {
2901         struct drm_display_mode *mode = panel->fixed_mode;
2902
2903         seq_printf(m, "\tfixed mode:\n");
2904         intel_seq_print_mode(m, 2, mode);
2905 }
2906
2907 static void intel_dp_info(struct seq_file *m,
2908                           struct intel_connector *intel_connector)
2909 {
2910         struct intel_encoder *intel_encoder = intel_connector->encoder;
2911         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2912
2913         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2914         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2915         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2916                 intel_panel_info(m, &intel_connector->panel);
2917 }
2918
2919 static void intel_hdmi_info(struct seq_file *m,
2920                             struct intel_connector *intel_connector)
2921 {
2922         struct intel_encoder *intel_encoder = intel_connector->encoder;
2923         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2924
2925         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2926 }
2927
2928 static void intel_lvds_info(struct seq_file *m,
2929                             struct intel_connector *intel_connector)
2930 {
2931         intel_panel_info(m, &intel_connector->panel);
2932 }
2933
2934 static void intel_connector_info(struct seq_file *m,
2935                                  struct drm_connector *connector)
2936 {
2937         struct intel_connector *intel_connector = to_intel_connector(connector);
2938         struct intel_encoder *intel_encoder = intel_connector->encoder;
2939         struct drm_display_mode *mode;
2940
2941         seq_printf(m, "connector %d: type %s, status: %s\n",
2942                    connector->base.id, connector->name,
2943                    drm_get_connector_status_name(connector->status));
2944         if (connector->status == connector_status_connected) {
2945                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2946                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2947                            connector->display_info.width_mm,
2948                            connector->display_info.height_mm);
2949                 seq_printf(m, "\tsubpixel order: %s\n",
2950                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2951                 seq_printf(m, "\tCEA rev: %d\n",
2952                            connector->display_info.cea_rev);
2953         }
2954
2955         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2956                 return;
2957
2958         switch (connector->connector_type) {
2959         case DRM_MODE_CONNECTOR_DisplayPort:
2960         case DRM_MODE_CONNECTOR_eDP:
2961                 intel_dp_info(m, intel_connector);
2962                 break;
2963         case DRM_MODE_CONNECTOR_LVDS:
2964                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2965                         intel_lvds_info(m, intel_connector);
2966                 break;
2967         case DRM_MODE_CONNECTOR_HDMIA:
2968                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2969                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2970                         intel_hdmi_info(m, intel_connector);
2971                 break;
2972         default:
2973                 break;
2974         }
2975
2976         seq_printf(m, "\tmodes:\n");
2977         list_for_each_entry(mode, &connector->modes, head)
2978                 intel_seq_print_mode(m, 2, mode);
2979 }
2980
2981 static bool cursor_active(struct drm_device *dev, int pipe)
2982 {
2983         struct drm_i915_private *dev_priv = to_i915(dev);
2984         u32 state;
2985
2986         if (IS_845G(dev) || IS_I865G(dev))
2987                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2988         else
2989                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2990
2991         return state;
2992 }
2993
2994 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2995 {
2996         struct drm_i915_private *dev_priv = to_i915(dev);
2997         u32 pos;
2998
2999         pos = I915_READ(CURPOS(pipe));
3000
3001         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3002         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3003                 *x = -*x;
3004
3005         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3006         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3007                 *y = -*y;
3008
3009         return cursor_active(dev, pipe);
3010 }
3011
3012 static const char *plane_type(enum drm_plane_type type)
3013 {
3014         switch (type) {
3015         case DRM_PLANE_TYPE_OVERLAY:
3016                 return "OVL";
3017         case DRM_PLANE_TYPE_PRIMARY:
3018                 return "PRI";
3019         case DRM_PLANE_TYPE_CURSOR:
3020                 return "CUR";
3021         /*
3022          * Deliberately omitting default: to generate compiler warnings
3023          * when a new drm_plane_type gets added.
3024          */
3025         }
3026
3027         return "unknown";
3028 }
3029
3030 static const char *plane_rotation(unsigned int rotation)
3031 {
3032         static char buf[48];
3033         /*
3034          * According to doc only one DRM_ROTATE_ is allowed but this
3035          * will print them all to visualize if the values are misused
3036          */
3037         snprintf(buf, sizeof(buf),
3038                  "%s%s%s%s%s%s(0x%08x)",
3039                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3040                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3041                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3042                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3043                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3044                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3045                  rotation);
3046
3047         return buf;
3048 }
3049
3050 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3051 {
3052         struct drm_info_node *node = m->private;
3053         struct drm_device *dev = node->minor->dev;
3054         struct intel_plane *intel_plane;
3055
3056         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3057                 struct drm_plane_state *state;
3058                 struct drm_plane *plane = &intel_plane->base;
3059
3060                 if (!plane->state) {
3061                         seq_puts(m, "plane->state is NULL!\n");
3062                         continue;
3063                 }
3064
3065                 state = plane->state;
3066
3067                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3068                            plane->base.id,
3069                            plane_type(intel_plane->base.type),
3070                            state->crtc_x, state->crtc_y,
3071                            state->crtc_w, state->crtc_h,
3072                            (state->src_x >> 16),
3073                            ((state->src_x & 0xffff) * 15625) >> 10,
3074                            (state->src_y >> 16),
3075                            ((state->src_y & 0xffff) * 15625) >> 10,
3076                            (state->src_w >> 16),
3077                            ((state->src_w & 0xffff) * 15625) >> 10,
3078                            (state->src_h >> 16),
3079                            ((state->src_h & 0xffff) * 15625) >> 10,
3080                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3081                            plane_rotation(state->rotation));
3082         }
3083 }
3084
3085 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3086 {
3087         struct intel_crtc_state *pipe_config;
3088         int num_scalers = intel_crtc->num_scalers;
3089         int i;
3090
3091         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3092
3093         /* Not all platformas have a scaler */
3094         if (num_scalers) {
3095                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3096                            num_scalers,
3097                            pipe_config->scaler_state.scaler_users,
3098                            pipe_config->scaler_state.scaler_id);
3099
3100                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3101                         struct intel_scaler *sc =
3102                                         &pipe_config->scaler_state.scalers[i];
3103
3104                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3105                                    i, yesno(sc->in_use), sc->mode);
3106                 }
3107                 seq_puts(m, "\n");
3108         } else {
3109                 seq_puts(m, "\tNo scalers available on this platform\n");
3110         }
3111 }
3112
3113 static int i915_display_info(struct seq_file *m, void *unused)
3114 {
3115         struct drm_info_node *node = m->private;
3116         struct drm_device *dev = node->minor->dev;
3117         struct drm_i915_private *dev_priv = to_i915(dev);
3118         struct intel_crtc *crtc;
3119         struct drm_connector *connector;
3120
3121         intel_runtime_pm_get(dev_priv);
3122         drm_modeset_lock_all(dev);
3123         seq_printf(m, "CRTC info\n");
3124         seq_printf(m, "---------\n");
3125         for_each_intel_crtc(dev, crtc) {
3126                 bool active;
3127                 struct intel_crtc_state *pipe_config;
3128                 int x, y;
3129
3130                 pipe_config = to_intel_crtc_state(crtc->base.state);
3131
3132                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3133                            crtc->base.base.id, pipe_name(crtc->pipe),
3134                            yesno(pipe_config->base.active),
3135                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3136                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3137
3138                 if (pipe_config->base.active) {
3139                         intel_crtc_info(m, crtc);
3140
3141                         active = cursor_position(dev, crtc->pipe, &x, &y);
3142                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3143                                    yesno(crtc->cursor_base),
3144                                    x, y, crtc->base.cursor->state->crtc_w,
3145                                    crtc->base.cursor->state->crtc_h,
3146                                    crtc->cursor_addr, yesno(active));
3147                         intel_scaler_info(m, crtc);
3148                         intel_plane_info(m, crtc);
3149                 }
3150
3151                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3152                            yesno(!crtc->cpu_fifo_underrun_disabled),
3153                            yesno(!crtc->pch_fifo_underrun_disabled));
3154         }
3155
3156         seq_printf(m, "\n");
3157         seq_printf(m, "Connector info\n");
3158         seq_printf(m, "--------------\n");
3159         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3160                 intel_connector_info(m, connector);
3161         }
3162         drm_modeset_unlock_all(dev);
3163         intel_runtime_pm_put(dev_priv);
3164
3165         return 0;
3166 }
3167
3168 static int i915_semaphore_status(struct seq_file *m, void *unused)
3169 {
3170         struct drm_info_node *node = (struct drm_info_node *) m->private;
3171         struct drm_device *dev = node->minor->dev;
3172         struct drm_i915_private *dev_priv = to_i915(dev);
3173         struct intel_engine_cs *engine;
3174         int num_rings = INTEL_INFO(dev)->num_rings;
3175         enum intel_engine_id id;
3176         int j, ret;
3177
3178         if (!i915.semaphores) {
3179                 seq_puts(m, "Semaphores are disabled\n");
3180                 return 0;
3181         }
3182
3183         ret = mutex_lock_interruptible(&dev->struct_mutex);
3184         if (ret)
3185                 return ret;
3186         intel_runtime_pm_get(dev_priv);
3187
3188         if (IS_BROADWELL(dev)) {
3189                 struct page *page;
3190                 uint64_t *seqno;
3191
3192                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3193
3194                 seqno = (uint64_t *)kmap_atomic(page);
3195                 for_each_engine_id(engine, dev_priv, id) {
3196                         uint64_t offset;
3197
3198                         seq_printf(m, "%s\n", engine->name);
3199
3200                         seq_puts(m, "  Last signal:");
3201                         for (j = 0; j < num_rings; j++) {
3202                                 offset = id * I915_NUM_ENGINES + j;
3203                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3204                                            seqno[offset], offset * 8);
3205                         }
3206                         seq_putc(m, '\n');
3207
3208                         seq_puts(m, "  Last wait:  ");
3209                         for (j = 0; j < num_rings; j++) {
3210                                 offset = id + (j * I915_NUM_ENGINES);
3211                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3212                                            seqno[offset], offset * 8);
3213                         }
3214                         seq_putc(m, '\n');
3215
3216                 }
3217                 kunmap_atomic(seqno);
3218         } else {
3219                 seq_puts(m, "  Last signal:");
3220                 for_each_engine(engine, dev_priv)
3221                         for (j = 0; j < num_rings; j++)
3222                                 seq_printf(m, "0x%08x\n",
3223                                            I915_READ(engine->semaphore.mbox.signal[j]));
3224                 seq_putc(m, '\n');
3225         }
3226
3227         seq_puts(m, "\nSync seqno:\n");
3228         for_each_engine(engine, dev_priv) {
3229                 for (j = 0; j < num_rings; j++)
3230                         seq_printf(m, "  0x%08x ",
3231                                    engine->semaphore.sync_seqno[j]);
3232                 seq_putc(m, '\n');
3233         }
3234         seq_putc(m, '\n');
3235
3236         intel_runtime_pm_put(dev_priv);
3237         mutex_unlock(&dev->struct_mutex);
3238         return 0;
3239 }
3240
3241 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3242 {
3243         struct drm_info_node *node = (struct drm_info_node *) m->private;
3244         struct drm_device *dev = node->minor->dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246         int i;
3247
3248         drm_modeset_lock_all(dev);
3249         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3250                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3251
3252                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3253                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3254                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3255                 seq_printf(m, " tracked hardware state:\n");
3256                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3257                 seq_printf(m, " dpll_md: 0x%08x\n",
3258                            pll->config.hw_state.dpll_md);
3259                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3260                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3261                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3262         }
3263         drm_modeset_unlock_all(dev);
3264
3265         return 0;
3266 }
3267
3268 static int i915_wa_registers(struct seq_file *m, void *unused)
3269 {
3270         int i;
3271         int ret;
3272         struct intel_engine_cs *engine;
3273         struct drm_info_node *node = (struct drm_info_node *) m->private;
3274         struct drm_device *dev = node->minor->dev;
3275         struct drm_i915_private *dev_priv = to_i915(dev);
3276         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3277         enum intel_engine_id id;
3278
3279         ret = mutex_lock_interruptible(&dev->struct_mutex);
3280         if (ret)
3281                 return ret;
3282
3283         intel_runtime_pm_get(dev_priv);
3284
3285         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3286         for_each_engine_id(engine, dev_priv, id)
3287                 seq_printf(m, "HW whitelist count for %s: %d\n",
3288                            engine->name, workarounds->hw_whitelist_count[id]);
3289         for (i = 0; i < workarounds->count; ++i) {
3290                 i915_reg_t addr;
3291                 u32 mask, value, read;
3292                 bool ok;
3293
3294                 addr = workarounds->reg[i].addr;
3295                 mask = workarounds->reg[i].mask;
3296                 value = workarounds->reg[i].value;
3297                 read = I915_READ(addr);
3298                 ok = (value & mask) == (read & mask);
3299                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3300                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3301         }
3302
3303         intel_runtime_pm_put(dev_priv);
3304         mutex_unlock(&dev->struct_mutex);
3305
3306         return 0;
3307 }
3308
3309 static int i915_ddb_info(struct seq_file *m, void *unused)
3310 {
3311         struct drm_info_node *node = m->private;
3312         struct drm_device *dev = node->minor->dev;
3313         struct drm_i915_private *dev_priv = to_i915(dev);
3314         struct skl_ddb_allocation *ddb;
3315         struct skl_ddb_entry *entry;
3316         enum pipe pipe;
3317         int plane;
3318
3319         if (INTEL_INFO(dev)->gen < 9)
3320                 return 0;
3321
3322         drm_modeset_lock_all(dev);
3323
3324         ddb = &dev_priv->wm.skl_hw.ddb;
3325
3326         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3327
3328         for_each_pipe(dev_priv, pipe) {
3329                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3330
3331                 for_each_plane(dev_priv, pipe, plane) {
3332                         entry = &ddb->plane[pipe][plane];
3333                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3334                                    entry->start, entry->end,
3335                                    skl_ddb_entry_size(entry));
3336                 }
3337
3338                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3339                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3340                            entry->end, skl_ddb_entry_size(entry));
3341         }
3342
3343         drm_modeset_unlock_all(dev);
3344
3345         return 0;
3346 }
3347
3348 static void drrs_status_per_crtc(struct seq_file *m,
3349                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3350 {
3351         struct drm_i915_private *dev_priv = to_i915(dev);
3352         struct i915_drrs *drrs = &dev_priv->drrs;
3353         int vrefresh = 0;
3354         struct drm_connector *connector;
3355
3356         drm_for_each_connector(connector, dev) {
3357                 if (connector->state->crtc != &intel_crtc->base)
3358                         continue;
3359
3360                 seq_printf(m, "%s:\n", connector->name);
3361         }
3362
3363         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3364                 seq_puts(m, "\tVBT: DRRS_type: Static");
3365         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3366                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3367         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3368                 seq_puts(m, "\tVBT: DRRS_type: None");
3369         else
3370                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3371
3372         seq_puts(m, "\n\n");
3373
3374         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3375                 struct intel_panel *panel;
3376
3377                 mutex_lock(&drrs->mutex);
3378                 /* DRRS Supported */
3379                 seq_puts(m, "\tDRRS Supported: Yes\n");
3380
3381                 /* disable_drrs() will make drrs->dp NULL */
3382                 if (!drrs->dp) {
3383                         seq_puts(m, "Idleness DRRS: Disabled");
3384                         mutex_unlock(&drrs->mutex);
3385                         return;
3386                 }
3387
3388                 panel = &drrs->dp->attached_connector->panel;
3389                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3390                                         drrs->busy_frontbuffer_bits);
3391
3392                 seq_puts(m, "\n\t\t");
3393                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3394                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3395                         vrefresh = panel->fixed_mode->vrefresh;
3396                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3397                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3398                         vrefresh = panel->downclock_mode->vrefresh;
3399                 } else {
3400                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3401                                                 drrs->refresh_rate_type);
3402                         mutex_unlock(&drrs->mutex);
3403                         return;
3404                 }
3405                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3406
3407                 seq_puts(m, "\n\t\t");
3408                 mutex_unlock(&drrs->mutex);
3409         } else {
3410                 /* DRRS not supported. Print the VBT parameter*/
3411                 seq_puts(m, "\tDRRS Supported : No");
3412         }
3413         seq_puts(m, "\n");
3414 }
3415
3416 static int i915_drrs_status(struct seq_file *m, void *unused)
3417 {
3418         struct drm_info_node *node = m->private;
3419         struct drm_device *dev = node->minor->dev;
3420         struct intel_crtc *intel_crtc;
3421         int active_crtc_cnt = 0;
3422
3423         drm_modeset_lock_all(dev);
3424         for_each_intel_crtc(dev, intel_crtc) {
3425                 if (intel_crtc->base.state->active) {
3426                         active_crtc_cnt++;
3427                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3428
3429                         drrs_status_per_crtc(m, dev, intel_crtc);
3430                 }
3431         }
3432         drm_modeset_unlock_all(dev);
3433
3434         if (!active_crtc_cnt)
3435                 seq_puts(m, "No active crtc found\n");
3436
3437         return 0;
3438 }
3439
3440 struct pipe_crc_info {
3441         const char *name;
3442         struct drm_device *dev;
3443         enum pipe pipe;
3444 };
3445
3446 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3447 {
3448         struct drm_info_node *node = (struct drm_info_node *) m->private;
3449         struct drm_device *dev = node->minor->dev;
3450         struct intel_encoder *intel_encoder;
3451         struct intel_digital_port *intel_dig_port;
3452         struct drm_connector *connector;
3453
3454         drm_modeset_lock_all(dev);
3455         drm_for_each_connector(connector, dev) {
3456                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3457                         continue;
3458
3459                 intel_encoder = intel_attached_encoder(connector);
3460                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3461                         continue;
3462
3463                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3464                 if (!intel_dig_port->dp.can_mst)
3465                         continue;
3466
3467                 seq_printf(m, "MST Source Port %c\n",
3468                            port_name(intel_dig_port->port));
3469                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3470         }
3471         drm_modeset_unlock_all(dev);
3472         return 0;
3473 }
3474
3475 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3476 {
3477         struct pipe_crc_info *info = inode->i_private;
3478         struct drm_i915_private *dev_priv = to_i915(info->dev);
3479         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3480
3481         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3482                 return -ENODEV;
3483
3484         spin_lock_irq(&pipe_crc->lock);
3485
3486         if (pipe_crc->opened) {
3487                 spin_unlock_irq(&pipe_crc->lock);
3488                 return -EBUSY; /* already open */
3489         }
3490
3491         pipe_crc->opened = true;
3492         filep->private_data = inode->i_private;
3493
3494         spin_unlock_irq(&pipe_crc->lock);
3495
3496         return 0;
3497 }
3498
3499 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3500 {
3501         struct pipe_crc_info *info = inode->i_private;
3502         struct drm_i915_private *dev_priv = to_i915(info->dev);
3503         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3504
3505         spin_lock_irq(&pipe_crc->lock);
3506         pipe_crc->opened = false;
3507         spin_unlock_irq(&pipe_crc->lock);
3508
3509         return 0;
3510 }
3511
3512 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3513 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3514 /* account for \'0' */
3515 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3516
3517 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3518 {
3519         assert_spin_locked(&pipe_crc->lock);
3520         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3521                         INTEL_PIPE_CRC_ENTRIES_NR);
3522 }
3523
3524 static ssize_t
3525 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3526                    loff_t *pos)
3527 {
3528         struct pipe_crc_info *info = filep->private_data;
3529         struct drm_device *dev = info->dev;
3530         struct drm_i915_private *dev_priv = to_i915(dev);
3531         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3532         char buf[PIPE_CRC_BUFFER_LEN];
3533         int n_entries;
3534         ssize_t bytes_read;
3535
3536         /*
3537          * Don't allow user space to provide buffers not big enough to hold
3538          * a line of data.
3539          */
3540         if (count < PIPE_CRC_LINE_LEN)
3541                 return -EINVAL;
3542
3543         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3544                 return 0;
3545
3546         /* nothing to read */
3547         spin_lock_irq(&pipe_crc->lock);
3548         while (pipe_crc_data_count(pipe_crc) == 0) {
3549                 int ret;
3550
3551                 if (filep->f_flags & O_NONBLOCK) {
3552                         spin_unlock_irq(&pipe_crc->lock);
3553                         return -EAGAIN;
3554                 }
3555
3556                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3557                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3558                 if (ret) {
3559                         spin_unlock_irq(&pipe_crc->lock);
3560                         return ret;
3561                 }
3562         }
3563
3564         /* We now have one or more entries to read */
3565         n_entries = count / PIPE_CRC_LINE_LEN;
3566
3567         bytes_read = 0;
3568         while (n_entries > 0) {
3569                 struct intel_pipe_crc_entry *entry =
3570                         &pipe_crc->entries[pipe_crc->tail];
3571
3572                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3573                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3574                         break;
3575
3576                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3577                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3578
3579                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3580                                        "%8u %8x %8x %8x %8x %8x\n",
3581                                        entry->frame, entry->crc[0],
3582                                        entry->crc[1], entry->crc[2],
3583                                        entry->crc[3], entry->crc[4]);
3584
3585                 spin_unlock_irq(&pipe_crc->lock);
3586
3587                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3588                         return -EFAULT;
3589
3590                 user_buf += PIPE_CRC_LINE_LEN;
3591                 n_entries--;
3592
3593                 spin_lock_irq(&pipe_crc->lock);
3594         }
3595
3596         spin_unlock_irq(&pipe_crc->lock);
3597
3598         return bytes_read;
3599 }
3600
3601 static const struct file_operations i915_pipe_crc_fops = {
3602         .owner = THIS_MODULE,
3603         .open = i915_pipe_crc_open,
3604         .read = i915_pipe_crc_read,
3605         .release = i915_pipe_crc_release,
3606 };
3607
3608 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3609         {
3610                 .name = "i915_pipe_A_crc",
3611                 .pipe = PIPE_A,
3612         },
3613         {
3614                 .name = "i915_pipe_B_crc",
3615                 .pipe = PIPE_B,
3616         },
3617         {
3618                 .name = "i915_pipe_C_crc",
3619                 .pipe = PIPE_C,
3620         },
3621 };
3622
3623 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3624                                 enum pipe pipe)
3625 {
3626         struct drm_device *dev = minor->dev;
3627         struct dentry *ent;
3628         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3629
3630         info->dev = dev;
3631         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3632                                   &i915_pipe_crc_fops);
3633         if (!ent)
3634                 return -ENOMEM;
3635
3636         return drm_add_fake_info_node(minor, ent, info);
3637 }
3638
3639 static const char * const pipe_crc_sources[] = {
3640         "none",
3641         "plane1",
3642         "plane2",
3643         "pf",
3644         "pipe",
3645         "TV",
3646         "DP-B",
3647         "DP-C",
3648         "DP-D",
3649         "auto",
3650 };
3651
3652 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3653 {
3654         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3655         return pipe_crc_sources[source];
3656 }
3657
3658 static int display_crc_ctl_show(struct seq_file *m, void *data)
3659 {
3660         struct drm_device *dev = m->private;
3661         struct drm_i915_private *dev_priv = to_i915(dev);
3662         int i;
3663
3664         for (i = 0; i < I915_MAX_PIPES; i++)
3665                 seq_printf(m, "%c %s\n", pipe_name(i),
3666                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3667
3668         return 0;
3669 }
3670
3671 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3672 {
3673         struct drm_device *dev = inode->i_private;
3674
3675         return single_open(file, display_crc_ctl_show, dev);
3676 }
3677
3678 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3679                                  uint32_t *val)
3680 {
3681         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3682                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3683
3684         switch (*source) {
3685         case INTEL_PIPE_CRC_SOURCE_PIPE:
3686                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3687                 break;
3688         case INTEL_PIPE_CRC_SOURCE_NONE:
3689                 *val = 0;
3690                 break;
3691         default:
3692                 return -EINVAL;
3693         }
3694
3695         return 0;
3696 }
3697
3698 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3699                                      enum intel_pipe_crc_source *source)
3700 {
3701         struct intel_encoder *encoder;
3702         struct intel_crtc *crtc;
3703         struct intel_digital_port *dig_port;
3704         int ret = 0;
3705
3706         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3707
3708         drm_modeset_lock_all(dev);
3709         for_each_intel_encoder(dev, encoder) {
3710                 if (!encoder->base.crtc)
3711                         continue;
3712
3713                 crtc = to_intel_crtc(encoder->base.crtc);
3714
3715                 if (crtc->pipe != pipe)
3716                         continue;
3717
3718                 switch (encoder->type) {
3719                 case INTEL_OUTPUT_TVOUT:
3720                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3721                         break;
3722                 case INTEL_OUTPUT_DP:
3723                 case INTEL_OUTPUT_EDP:
3724                         dig_port = enc_to_dig_port(&encoder->base);
3725                         switch (dig_port->port) {
3726                         case PORT_B:
3727                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3728                                 break;
3729                         case PORT_C:
3730                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3731                                 break;
3732                         case PORT_D:
3733                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3734                                 break;
3735                         default:
3736                                 WARN(1, "nonexisting DP port %c\n",
3737                                      port_name(dig_port->port));
3738                                 break;
3739                         }
3740                         break;
3741                 default:
3742                         break;
3743                 }
3744         }
3745         drm_modeset_unlock_all(dev);
3746
3747         return ret;
3748 }
3749
3750 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3751                                 enum pipe pipe,
3752                                 enum intel_pipe_crc_source *source,
3753                                 uint32_t *val)
3754 {
3755         struct drm_i915_private *dev_priv = to_i915(dev);
3756         bool need_stable_symbols = false;
3757
3758         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3759                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3760                 if (ret)
3761                         return ret;
3762         }
3763
3764         switch (*source) {
3765         case INTEL_PIPE_CRC_SOURCE_PIPE:
3766                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3767                 break;
3768         case INTEL_PIPE_CRC_SOURCE_DP_B:
3769                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3770                 need_stable_symbols = true;
3771                 break;
3772         case INTEL_PIPE_CRC_SOURCE_DP_C:
3773                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3774                 need_stable_symbols = true;
3775                 break;
3776         case INTEL_PIPE_CRC_SOURCE_DP_D:
3777                 if (!IS_CHERRYVIEW(dev))
3778                         return -EINVAL;
3779                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3780                 need_stable_symbols = true;
3781                 break;
3782         case INTEL_PIPE_CRC_SOURCE_NONE:
3783                 *val = 0;
3784                 break;
3785         default:
3786                 return -EINVAL;
3787         }
3788
3789         /*
3790          * When the pipe CRC tap point is after the transcoders we need
3791          * to tweak symbol-level features to produce a deterministic series of
3792          * symbols for a given frame. We need to reset those features only once
3793          * a frame (instead of every nth symbol):
3794          *   - DC-balance: used to ensure a better clock recovery from the data
3795          *     link (SDVO)
3796          *   - DisplayPort scrambling: used for EMI reduction
3797          */
3798         if (need_stable_symbols) {
3799                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3800
3801                 tmp |= DC_BALANCE_RESET_VLV;
3802                 switch (pipe) {
3803                 case PIPE_A:
3804                         tmp |= PIPE_A_SCRAMBLE_RESET;
3805                         break;
3806                 case PIPE_B:
3807                         tmp |= PIPE_B_SCRAMBLE_RESET;
3808                         break;
3809                 case PIPE_C:
3810                         tmp |= PIPE_C_SCRAMBLE_RESET;
3811                         break;
3812                 default:
3813                         return -EINVAL;
3814                 }
3815                 I915_WRITE(PORT_DFT2_G4X, tmp);
3816         }
3817
3818         return 0;
3819 }
3820
3821 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3822                                  enum pipe pipe,
3823                                  enum intel_pipe_crc_source *source,
3824                                  uint32_t *val)
3825 {
3826         struct drm_i915_private *dev_priv = to_i915(dev);
3827         bool need_stable_symbols = false;
3828
3829         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3830                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3831                 if (ret)
3832                         return ret;
3833         }
3834
3835         switch (*source) {
3836         case INTEL_PIPE_CRC_SOURCE_PIPE:
3837                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3838                 break;
3839         case INTEL_PIPE_CRC_SOURCE_TV:
3840                 if (!SUPPORTS_TV(dev))
3841                         return -EINVAL;
3842                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3843                 break;
3844         case INTEL_PIPE_CRC_SOURCE_DP_B:
3845                 if (!IS_G4X(dev))
3846                         return -EINVAL;
3847                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3848                 need_stable_symbols = true;
3849                 break;
3850         case INTEL_PIPE_CRC_SOURCE_DP_C:
3851                 if (!IS_G4X(dev))
3852                         return -EINVAL;
3853                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3854                 need_stable_symbols = true;
3855                 break;
3856         case INTEL_PIPE_CRC_SOURCE_DP_D:
3857                 if (!IS_G4X(dev))
3858                         return -EINVAL;
3859                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3860                 need_stable_symbols = true;
3861                 break;
3862         case INTEL_PIPE_CRC_SOURCE_NONE:
3863                 *val = 0;
3864                 break;
3865         default:
3866                 return -EINVAL;
3867         }
3868
3869         /*
3870          * When the pipe CRC tap point is after the transcoders we need
3871          * to tweak symbol-level features to produce a deterministic series of
3872          * symbols for a given frame. We need to reset those features only once
3873          * a frame (instead of every nth symbol):
3874          *   - DC-balance: used to ensure a better clock recovery from the data
3875          *     link (SDVO)
3876          *   - DisplayPort scrambling: used for EMI reduction
3877          */
3878         if (need_stable_symbols) {
3879                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3880
3881                 WARN_ON(!IS_G4X(dev));
3882
3883                 I915_WRITE(PORT_DFT_I9XX,
3884                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3885
3886                 if (pipe == PIPE_A)
3887                         tmp |= PIPE_A_SCRAMBLE_RESET;
3888                 else
3889                         tmp |= PIPE_B_SCRAMBLE_RESET;
3890
3891                 I915_WRITE(PORT_DFT2_G4X, tmp);
3892         }
3893
3894         return 0;
3895 }
3896
3897 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3898                                          enum pipe pipe)
3899 {
3900         struct drm_i915_private *dev_priv = to_i915(dev);
3901         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3902
3903         switch (pipe) {
3904         case PIPE_A:
3905                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3906                 break;
3907         case PIPE_B:
3908                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3909                 break;
3910         case PIPE_C:
3911                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3912                 break;
3913         default:
3914                 return;
3915         }
3916         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3917                 tmp &= ~DC_BALANCE_RESET_VLV;
3918         I915_WRITE(PORT_DFT2_G4X, tmp);
3919
3920 }
3921
3922 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3923                                          enum pipe pipe)
3924 {
3925         struct drm_i915_private *dev_priv = to_i915(dev);
3926         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3927
3928         if (pipe == PIPE_A)
3929                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3930         else
3931                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3932         I915_WRITE(PORT_DFT2_G4X, tmp);
3933
3934         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3935                 I915_WRITE(PORT_DFT_I9XX,
3936                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3937         }
3938 }
3939
3940 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3941                                 uint32_t *val)
3942 {
3943         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3944                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3945
3946         switch (*source) {
3947         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3948                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3949                 break;
3950         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3951                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3952                 break;
3953         case INTEL_PIPE_CRC_SOURCE_PIPE:
3954                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3955                 break;
3956         case INTEL_PIPE_CRC_SOURCE_NONE:
3957                 *val = 0;
3958                 break;
3959         default:
3960                 return -EINVAL;
3961         }
3962
3963         return 0;
3964 }
3965
3966 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3967 {
3968         struct drm_i915_private *dev_priv = to_i915(dev);
3969         struct intel_crtc *crtc =
3970                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3971         struct intel_crtc_state *pipe_config;
3972         struct drm_atomic_state *state;
3973         int ret = 0;
3974
3975         drm_modeset_lock_all(dev);
3976         state = drm_atomic_state_alloc(dev);
3977         if (!state) {
3978                 ret = -ENOMEM;
3979                 goto out;
3980         }
3981
3982         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3983         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3984         if (IS_ERR(pipe_config)) {
3985                 ret = PTR_ERR(pipe_config);
3986                 goto out;
3987         }
3988
3989         pipe_config->pch_pfit.force_thru = enable;
3990         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3991             pipe_config->pch_pfit.enabled != enable)
3992                 pipe_config->base.connectors_changed = true;
3993
3994         ret = drm_atomic_commit(state);
3995 out:
3996         drm_modeset_unlock_all(dev);
3997         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3998         if (ret)
3999                 drm_atomic_state_free(state);
4000 }
4001
4002 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4003                                 enum pipe pipe,
4004                                 enum intel_pipe_crc_source *source,
4005                                 uint32_t *val)
4006 {
4007         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4008                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4009
4010         switch (*source) {
4011         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4012                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4013                 break;
4014         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4015                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4016                 break;
4017         case INTEL_PIPE_CRC_SOURCE_PF:
4018                 if (IS_HASWELL(dev) && pipe == PIPE_A)
4019                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
4020
4021                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4022                 break;
4023         case INTEL_PIPE_CRC_SOURCE_NONE:
4024                 *val = 0;
4025                 break;
4026         default:
4027                 return -EINVAL;
4028         }
4029
4030         return 0;
4031 }
4032
4033 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4034                                enum intel_pipe_crc_source source)
4035 {
4036         struct drm_i915_private *dev_priv = to_i915(dev);
4037         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4038         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4039                                                                         pipe));
4040         enum intel_display_power_domain power_domain;
4041         u32 val = 0; /* shut up gcc */
4042         int ret;
4043
4044         if (pipe_crc->source == source)
4045                 return 0;
4046
4047         /* forbid changing the source without going back to 'none' */
4048         if (pipe_crc->source && source)
4049                 return -EINVAL;
4050
4051         power_domain = POWER_DOMAIN_PIPE(pipe);
4052         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4053                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4054                 return -EIO;
4055         }
4056
4057         if (IS_GEN2(dev))
4058                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4059         else if (INTEL_INFO(dev)->gen < 5)
4060                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4061         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4062                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4063         else if (IS_GEN5(dev) || IS_GEN6(dev))
4064                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4065         else
4066                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4067
4068         if (ret != 0)
4069                 goto out;
4070
4071         /* none -> real source transition */
4072         if (source) {
4073                 struct intel_pipe_crc_entry *entries;
4074
4075                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4076                                  pipe_name(pipe), pipe_crc_source_name(source));
4077
4078                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4079                                   sizeof(pipe_crc->entries[0]),
4080                                   GFP_KERNEL);
4081                 if (!entries) {
4082                         ret = -ENOMEM;
4083                         goto out;
4084                 }
4085
4086                 /*
4087                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4088                  * enabled and disabled dynamically based on package C states,
4089                  * user space can't make reliable use of the CRCs, so let's just
4090                  * completely disable it.
4091                  */
4092                 hsw_disable_ips(crtc);
4093
4094                 spin_lock_irq(&pipe_crc->lock);
4095                 kfree(pipe_crc->entries);
4096                 pipe_crc->entries = entries;
4097                 pipe_crc->head = 0;
4098                 pipe_crc->tail = 0;
4099                 spin_unlock_irq(&pipe_crc->lock);
4100         }
4101
4102         pipe_crc->source = source;
4103
4104         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4105         POSTING_READ(PIPE_CRC_CTL(pipe));
4106
4107         /* real source -> none transition */
4108         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4109                 struct intel_pipe_crc_entry *entries;
4110                 struct intel_crtc *crtc =
4111                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4112
4113                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4114                                  pipe_name(pipe));
4115
4116                 drm_modeset_lock(&crtc->base.mutex, NULL);
4117                 if (crtc->base.state->active)
4118                         intel_wait_for_vblank(dev, pipe);
4119                 drm_modeset_unlock(&crtc->base.mutex);
4120
4121                 spin_lock_irq(&pipe_crc->lock);
4122                 entries = pipe_crc->entries;
4123                 pipe_crc->entries = NULL;
4124                 pipe_crc->head = 0;
4125                 pipe_crc->tail = 0;
4126                 spin_unlock_irq(&pipe_crc->lock);
4127
4128                 kfree(entries);
4129
4130                 if (IS_G4X(dev))
4131                         g4x_undo_pipe_scramble_reset(dev, pipe);
4132                 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4133                         vlv_undo_pipe_scramble_reset(dev, pipe);
4134                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4135                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4136
4137                 hsw_enable_ips(crtc);
4138         }
4139
4140         ret = 0;
4141
4142 out:
4143         intel_display_power_put(dev_priv, power_domain);
4144
4145         return ret;
4146 }
4147
4148 /*
4149  * Parse pipe CRC command strings:
4150  *   command: wsp* object wsp+ name wsp+ source wsp*
4151  *   object: 'pipe'
4152  *   name: (A | B | C)
4153  *   source: (none | plane1 | plane2 | pf)
4154  *   wsp: (#0x20 | #0x9 | #0xA)+
4155  *
4156  * eg.:
4157  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4158  *  "pipe A none"    ->  Stop CRC
4159  */
4160 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4161 {
4162         int n_words = 0;
4163
4164         while (*buf) {
4165                 char *end;
4166
4167                 /* skip leading white space */
4168                 buf = skip_spaces(buf);
4169                 if (!*buf)
4170                         break;  /* end of buffer */
4171
4172                 /* find end of word */
4173                 for (end = buf; *end && !isspace(*end); end++)
4174                         ;
4175
4176                 if (n_words == max_words) {
4177                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4178                                          max_words);
4179                         return -EINVAL; /* ran out of words[] before bytes */
4180                 }
4181
4182                 if (*end)
4183                         *end++ = '\0';
4184                 words[n_words++] = buf;
4185                 buf = end;
4186         }
4187
4188         return n_words;
4189 }
4190
4191 enum intel_pipe_crc_object {
4192         PIPE_CRC_OBJECT_PIPE,
4193 };
4194
4195 static const char * const pipe_crc_objects[] = {
4196         "pipe",
4197 };
4198
4199 static int
4200 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4201 {
4202         int i;
4203
4204         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4205                 if (!strcmp(buf, pipe_crc_objects[i])) {
4206                         *o = i;
4207                         return 0;
4208                     }
4209
4210         return -EINVAL;
4211 }
4212
4213 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4214 {
4215         const char name = buf[0];
4216
4217         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4218                 return -EINVAL;
4219
4220         *pipe = name - 'A';
4221
4222         return 0;
4223 }
4224
4225 static int
4226 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4227 {
4228         int i;
4229
4230         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4231                 if (!strcmp(buf, pipe_crc_sources[i])) {
4232                         *s = i;
4233                         return 0;
4234                     }
4235
4236         return -EINVAL;
4237 }
4238
4239 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4240 {
4241 #define N_WORDS 3
4242         int n_words;
4243         char *words[N_WORDS];
4244         enum pipe pipe;
4245         enum intel_pipe_crc_object object;
4246         enum intel_pipe_crc_source source;
4247
4248         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4249         if (n_words != N_WORDS) {
4250                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4251                                  N_WORDS);
4252                 return -EINVAL;
4253         }
4254
4255         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4256                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4257                 return -EINVAL;
4258         }
4259
4260         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4261                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4262                 return -EINVAL;
4263         }
4264
4265         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4266                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4267                 return -EINVAL;
4268         }
4269
4270         return pipe_crc_set_source(dev, pipe, source);
4271 }
4272
4273 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4274                                      size_t len, loff_t *offp)
4275 {
4276         struct seq_file *m = file->private_data;
4277         struct drm_device *dev = m->private;
4278         char *tmpbuf;
4279         int ret;
4280
4281         if (len == 0)
4282                 return 0;
4283
4284         if (len > PAGE_SIZE - 1) {
4285                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4286                                  PAGE_SIZE);
4287                 return -E2BIG;
4288         }
4289
4290         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4291         if (!tmpbuf)
4292                 return -ENOMEM;
4293
4294         if (copy_from_user(tmpbuf, ubuf, len)) {
4295                 ret = -EFAULT;
4296                 goto out;
4297         }
4298         tmpbuf[len] = '\0';
4299
4300         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4301
4302 out:
4303         kfree(tmpbuf);
4304         if (ret < 0)
4305                 return ret;
4306
4307         *offp += len;
4308         return len;
4309 }
4310
4311 static const struct file_operations i915_display_crc_ctl_fops = {
4312         .owner = THIS_MODULE,
4313         .open = display_crc_ctl_open,
4314         .read = seq_read,
4315         .llseek = seq_lseek,
4316         .release = single_release,
4317         .write = display_crc_ctl_write
4318 };
4319
4320 static ssize_t i915_displayport_test_active_write(struct file *file,
4321                                             const char __user *ubuf,
4322                                             size_t len, loff_t *offp)
4323 {
4324         char *input_buffer;
4325         int status = 0;
4326         struct drm_device *dev;
4327         struct drm_connector *connector;
4328         struct list_head *connector_list;
4329         struct intel_dp *intel_dp;
4330         int val = 0;
4331
4332         dev = ((struct seq_file *)file->private_data)->private;
4333
4334         connector_list = &dev->mode_config.connector_list;
4335
4336         if (len == 0)
4337                 return 0;
4338
4339         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4340         if (!input_buffer)
4341                 return -ENOMEM;
4342
4343         if (copy_from_user(input_buffer, ubuf, len)) {
4344                 status = -EFAULT;
4345                 goto out;
4346         }
4347
4348         input_buffer[len] = '\0';
4349         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4350
4351         list_for_each_entry(connector, connector_list, head) {
4352
4353                 if (connector->connector_type !=
4354                     DRM_MODE_CONNECTOR_DisplayPort)
4355                         continue;
4356
4357                 if (connector->status == connector_status_connected &&
4358                     connector->encoder != NULL) {
4359                         intel_dp = enc_to_intel_dp(connector->encoder);
4360                         status = kstrtoint(input_buffer, 10, &val);
4361                         if (status < 0)
4362                                 goto out;
4363                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4364                         /* To prevent erroneous activation of the compliance
4365                          * testing code, only accept an actual value of 1 here
4366                          */
4367                         if (val == 1)
4368                                 intel_dp->compliance_test_active = 1;
4369                         else
4370                                 intel_dp->compliance_test_active = 0;
4371                 }
4372         }
4373 out:
4374         kfree(input_buffer);
4375         if (status < 0)
4376                 return status;
4377
4378         *offp += len;
4379         return len;
4380 }
4381
4382 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4383 {
4384         struct drm_device *dev = m->private;
4385         struct drm_connector *connector;
4386         struct list_head *connector_list = &dev->mode_config.connector_list;
4387         struct intel_dp *intel_dp;
4388
4389         list_for_each_entry(connector, connector_list, head) {
4390
4391                 if (connector->connector_type !=
4392                     DRM_MODE_CONNECTOR_DisplayPort)
4393                         continue;
4394
4395                 if (connector->status == connector_status_connected &&
4396                     connector->encoder != NULL) {
4397                         intel_dp = enc_to_intel_dp(connector->encoder);
4398                         if (intel_dp->compliance_test_active)
4399                                 seq_puts(m, "1");
4400                         else
4401                                 seq_puts(m, "0");
4402                 } else
4403                         seq_puts(m, "0");
4404         }
4405
4406         return 0;
4407 }
4408
4409 static int i915_displayport_test_active_open(struct inode *inode,
4410                                        struct file *file)
4411 {
4412         struct drm_device *dev = inode->i_private;
4413
4414         return single_open(file, i915_displayport_test_active_show, dev);
4415 }
4416
4417 static const struct file_operations i915_displayport_test_active_fops = {
4418         .owner = THIS_MODULE,
4419         .open = i915_displayport_test_active_open,
4420         .read = seq_read,
4421         .llseek = seq_lseek,
4422         .release = single_release,
4423         .write = i915_displayport_test_active_write
4424 };
4425
4426 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4427 {
4428         struct drm_device *dev = m->private;
4429         struct drm_connector *connector;
4430         struct list_head *connector_list = &dev->mode_config.connector_list;
4431         struct intel_dp *intel_dp;
4432
4433         list_for_each_entry(connector, connector_list, head) {
4434
4435                 if (connector->connector_type !=
4436                     DRM_MODE_CONNECTOR_DisplayPort)
4437                         continue;
4438
4439                 if (connector->status == connector_status_connected &&
4440                     connector->encoder != NULL) {
4441                         intel_dp = enc_to_intel_dp(connector->encoder);
4442                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4443                 } else
4444                         seq_puts(m, "0");
4445         }
4446
4447         return 0;
4448 }
4449 static int i915_displayport_test_data_open(struct inode *inode,
4450                                        struct file *file)
4451 {
4452         struct drm_device *dev = inode->i_private;
4453
4454         return single_open(file, i915_displayport_test_data_show, dev);
4455 }
4456
4457 static const struct file_operations i915_displayport_test_data_fops = {
4458         .owner = THIS_MODULE,
4459         .open = i915_displayport_test_data_open,
4460         .read = seq_read,
4461         .llseek = seq_lseek,
4462         .release = single_release
4463 };
4464
4465 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4466 {
4467         struct drm_device *dev = m->private;
4468         struct drm_connector *connector;
4469         struct list_head *connector_list = &dev->mode_config.connector_list;
4470         struct intel_dp *intel_dp;
4471
4472         list_for_each_entry(connector, connector_list, head) {
4473
4474                 if (connector->connector_type !=
4475                     DRM_MODE_CONNECTOR_DisplayPort)
4476                         continue;
4477
4478                 if (connector->status == connector_status_connected &&
4479                     connector->encoder != NULL) {
4480                         intel_dp = enc_to_intel_dp(connector->encoder);
4481                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4482                 } else
4483                         seq_puts(m, "0");
4484         }
4485
4486         return 0;
4487 }
4488
4489 static int i915_displayport_test_type_open(struct inode *inode,
4490                                        struct file *file)
4491 {
4492         struct drm_device *dev = inode->i_private;
4493
4494         return single_open(file, i915_displayport_test_type_show, dev);
4495 }
4496
4497 static const struct file_operations i915_displayport_test_type_fops = {
4498         .owner = THIS_MODULE,
4499         .open = i915_displayport_test_type_open,
4500         .read = seq_read,
4501         .llseek = seq_lseek,
4502         .release = single_release
4503 };
4504
4505 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4506 {
4507         struct drm_device *dev = m->private;
4508         int level;
4509         int num_levels;
4510
4511         if (IS_CHERRYVIEW(dev))
4512                 num_levels = 3;
4513         else if (IS_VALLEYVIEW(dev))
4514                 num_levels = 1;
4515         else
4516                 num_levels = ilk_wm_max_level(dev) + 1;
4517
4518         drm_modeset_lock_all(dev);
4519
4520         for (level = 0; level < num_levels; level++) {
4521                 unsigned int latency = wm[level];
4522
4523                 /*
4524                  * - WM1+ latency values in 0.5us units
4525                  * - latencies are in us on gen9/vlv/chv
4526                  */
4527                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4528                     IS_CHERRYVIEW(dev))
4529                         latency *= 10;
4530                 else if (level > 0)
4531                         latency *= 5;
4532
4533                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4534                            level, wm[level], latency / 10, latency % 10);
4535         }
4536
4537         drm_modeset_unlock_all(dev);
4538 }
4539
4540 static int pri_wm_latency_show(struct seq_file *m, void *data)
4541 {
4542         struct drm_device *dev = m->private;
4543         struct drm_i915_private *dev_priv = to_i915(dev);
4544         const uint16_t *latencies;
4545
4546         if (INTEL_INFO(dev)->gen >= 9)
4547                 latencies = dev_priv->wm.skl_latency;
4548         else
4549                 latencies = to_i915(dev)->wm.pri_latency;
4550
4551         wm_latency_show(m, latencies);
4552
4553         return 0;
4554 }
4555
4556 static int spr_wm_latency_show(struct seq_file *m, void *data)
4557 {
4558         struct drm_device *dev = m->private;
4559         struct drm_i915_private *dev_priv = to_i915(dev);
4560         const uint16_t *latencies;
4561
4562         if (INTEL_INFO(dev)->gen >= 9)
4563                 latencies = dev_priv->wm.skl_latency;
4564         else
4565                 latencies = to_i915(dev)->wm.spr_latency;
4566
4567         wm_latency_show(m, latencies);
4568
4569         return 0;
4570 }
4571
4572 static int cur_wm_latency_show(struct seq_file *m, void *data)
4573 {
4574         struct drm_device *dev = m->private;
4575         struct drm_i915_private *dev_priv = to_i915(dev);
4576         const uint16_t *latencies;
4577
4578         if (INTEL_INFO(dev)->gen >= 9)
4579                 latencies = dev_priv->wm.skl_latency;
4580         else
4581                 latencies = to_i915(dev)->wm.cur_latency;
4582
4583         wm_latency_show(m, latencies);
4584
4585         return 0;
4586 }
4587
4588 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4589 {
4590         struct drm_device *dev = inode->i_private;
4591
4592         if (INTEL_INFO(dev)->gen < 5)
4593                 return -ENODEV;
4594
4595         return single_open(file, pri_wm_latency_show, dev);
4596 }
4597
4598 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4599 {
4600         struct drm_device *dev = inode->i_private;
4601
4602         if (HAS_GMCH_DISPLAY(dev))
4603                 return -ENODEV;
4604
4605         return single_open(file, spr_wm_latency_show, dev);
4606 }
4607
4608 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4609 {
4610         struct drm_device *dev = inode->i_private;
4611
4612         if (HAS_GMCH_DISPLAY(dev))
4613                 return -ENODEV;
4614
4615         return single_open(file, cur_wm_latency_show, dev);
4616 }
4617
4618 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4619                                 size_t len, loff_t *offp, uint16_t wm[8])
4620 {
4621         struct seq_file *m = file->private_data;
4622         struct drm_device *dev = m->private;
4623         uint16_t new[8] = { 0 };
4624         int num_levels;
4625         int level;
4626         int ret;
4627         char tmp[32];
4628
4629         if (IS_CHERRYVIEW(dev))
4630                 num_levels = 3;
4631         else if (IS_VALLEYVIEW(dev))
4632                 num_levels = 1;
4633         else
4634                 num_levels = ilk_wm_max_level(dev) + 1;
4635
4636         if (len >= sizeof(tmp))
4637                 return -EINVAL;
4638
4639         if (copy_from_user(tmp, ubuf, len))
4640                 return -EFAULT;
4641
4642         tmp[len] = '\0';
4643
4644         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4645                      &new[0], &new[1], &new[2], &new[3],
4646                      &new[4], &new[5], &new[6], &new[7]);
4647         if (ret != num_levels)
4648                 return -EINVAL;
4649
4650         drm_modeset_lock_all(dev);
4651
4652         for (level = 0; level < num_levels; level++)
4653                 wm[level] = new[level];
4654
4655         drm_modeset_unlock_all(dev);
4656
4657         return len;
4658 }
4659
4660
4661 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4662                                     size_t len, loff_t *offp)
4663 {
4664         struct seq_file *m = file->private_data;
4665         struct drm_device *dev = m->private;
4666         struct drm_i915_private *dev_priv = to_i915(dev);
4667         uint16_t *latencies;
4668
4669         if (INTEL_INFO(dev)->gen >= 9)
4670                 latencies = dev_priv->wm.skl_latency;
4671         else
4672                 latencies = to_i915(dev)->wm.pri_latency;
4673
4674         return wm_latency_write(file, ubuf, len, offp, latencies);
4675 }
4676
4677 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4678                                     size_t len, loff_t *offp)
4679 {
4680         struct seq_file *m = file->private_data;
4681         struct drm_device *dev = m->private;
4682         struct drm_i915_private *dev_priv = to_i915(dev);
4683         uint16_t *latencies;
4684
4685         if (INTEL_INFO(dev)->gen >= 9)
4686                 latencies = dev_priv->wm.skl_latency;
4687         else
4688                 latencies = to_i915(dev)->wm.spr_latency;
4689
4690         return wm_latency_write(file, ubuf, len, offp, latencies);
4691 }
4692
4693 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4694                                     size_t len, loff_t *offp)
4695 {
4696         struct seq_file *m = file->private_data;
4697         struct drm_device *dev = m->private;
4698         struct drm_i915_private *dev_priv = to_i915(dev);
4699         uint16_t *latencies;
4700
4701         if (INTEL_INFO(dev)->gen >= 9)
4702                 latencies = dev_priv->wm.skl_latency;
4703         else
4704                 latencies = to_i915(dev)->wm.cur_latency;
4705
4706         return wm_latency_write(file, ubuf, len, offp, latencies);
4707 }
4708
4709 static const struct file_operations i915_pri_wm_latency_fops = {
4710         .owner = THIS_MODULE,
4711         .open = pri_wm_latency_open,
4712         .read = seq_read,
4713         .llseek = seq_lseek,
4714         .release = single_release,
4715         .write = pri_wm_latency_write
4716 };
4717
4718 static const struct file_operations i915_spr_wm_latency_fops = {
4719         .owner = THIS_MODULE,
4720         .open = spr_wm_latency_open,
4721         .read = seq_read,
4722         .llseek = seq_lseek,
4723         .release = single_release,
4724         .write = spr_wm_latency_write
4725 };
4726
4727 static const struct file_operations i915_cur_wm_latency_fops = {
4728         .owner = THIS_MODULE,
4729         .open = cur_wm_latency_open,
4730         .read = seq_read,
4731         .llseek = seq_lseek,
4732         .release = single_release,
4733         .write = cur_wm_latency_write
4734 };
4735
4736 static int
4737 i915_wedged_get(void *data, u64 *val)
4738 {
4739         struct drm_device *dev = data;
4740         struct drm_i915_private *dev_priv = to_i915(dev);
4741
4742         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4743
4744         return 0;
4745 }
4746
4747 static int
4748 i915_wedged_set(void *data, u64 val)
4749 {
4750         struct drm_device *dev = data;
4751         struct drm_i915_private *dev_priv = to_i915(dev);
4752
4753         /*
4754          * There is no safeguard against this debugfs entry colliding
4755          * with the hangcheck calling same i915_handle_error() in
4756          * parallel, causing an explosion. For now we assume that the
4757          * test harness is responsible enough not to inject gpu hangs
4758          * while it is writing to 'i915_wedged'
4759          */
4760
4761         if (i915_reset_in_progress(&dev_priv->gpu_error))
4762                 return -EAGAIN;
4763
4764         intel_runtime_pm_get(dev_priv);
4765
4766         i915_handle_error(dev_priv, val,
4767                           "Manually setting wedged to %llu", val);
4768
4769         intel_runtime_pm_put(dev_priv);
4770
4771         return 0;
4772 }
4773
4774 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4775                         i915_wedged_get, i915_wedged_set,
4776                         "%llu\n");
4777
4778 static int
4779 i915_ring_missed_irq_get(void *data, u64 *val)
4780 {
4781         struct drm_device *dev = data;
4782         struct drm_i915_private *dev_priv = to_i915(dev);
4783
4784         *val = dev_priv->gpu_error.missed_irq_rings;
4785         return 0;
4786 }
4787
4788 static int
4789 i915_ring_missed_irq_set(void *data, u64 val)
4790 {
4791         struct drm_device *dev = data;
4792         struct drm_i915_private *dev_priv = to_i915(dev);
4793         int ret;
4794
4795         /* Lock against concurrent debugfs callers */
4796         ret = mutex_lock_interruptible(&dev->struct_mutex);
4797         if (ret)
4798                 return ret;
4799         dev_priv->gpu_error.missed_irq_rings = val;
4800         mutex_unlock(&dev->struct_mutex);
4801
4802         return 0;
4803 }
4804
4805 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4806                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4807                         "0x%08llx\n");
4808
4809 static int
4810 i915_ring_test_irq_get(void *data, u64 *val)
4811 {
4812         struct drm_device *dev = data;
4813         struct drm_i915_private *dev_priv = to_i915(dev);
4814
4815         *val = dev_priv->gpu_error.test_irq_rings;
4816
4817         return 0;
4818 }
4819
4820 static int
4821 i915_ring_test_irq_set(void *data, u64 val)
4822 {
4823         struct drm_device *dev = data;
4824         struct drm_i915_private *dev_priv = to_i915(dev);
4825
4826         val &= INTEL_INFO(dev_priv)->ring_mask;
4827         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4828         dev_priv->gpu_error.test_irq_rings = val;
4829
4830         return 0;
4831 }
4832
4833 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4834                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4835                         "0x%08llx\n");
4836
4837 #define DROP_UNBOUND 0x1
4838 #define DROP_BOUND 0x2
4839 #define DROP_RETIRE 0x4
4840 #define DROP_ACTIVE 0x8
4841 #define DROP_ALL (DROP_UNBOUND | \
4842                   DROP_BOUND | \
4843                   DROP_RETIRE | \
4844                   DROP_ACTIVE)
4845 static int
4846 i915_drop_caches_get(void *data, u64 *val)
4847 {
4848         *val = DROP_ALL;
4849
4850         return 0;
4851 }
4852
4853 static int
4854 i915_drop_caches_set(void *data, u64 val)
4855 {
4856         struct drm_device *dev = data;
4857         struct drm_i915_private *dev_priv = to_i915(dev);
4858         int ret;
4859
4860         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4861
4862         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4863          * on ioctls on -EAGAIN. */
4864         ret = mutex_lock_interruptible(&dev->struct_mutex);
4865         if (ret)
4866                 return ret;
4867
4868         if (val & DROP_ACTIVE) {
4869                 ret = i915_gem_wait_for_idle(dev_priv, true);
4870                 if (ret)
4871                         goto unlock;
4872         }
4873
4874         if (val & (DROP_RETIRE | DROP_ACTIVE))
4875                 i915_gem_retire_requests(dev_priv);
4876
4877         if (val & DROP_BOUND)
4878                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4879
4880         if (val & DROP_UNBOUND)
4881                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4882
4883 unlock:
4884         mutex_unlock(&dev->struct_mutex);
4885
4886         return ret;
4887 }
4888
4889 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4890                         i915_drop_caches_get, i915_drop_caches_set,
4891                         "0x%08llx\n");
4892
4893 static int
4894 i915_max_freq_get(void *data, u64 *val)
4895 {
4896         struct drm_device *dev = data;
4897         struct drm_i915_private *dev_priv = to_i915(dev);
4898
4899         if (INTEL_INFO(dev)->gen < 6)
4900                 return -ENODEV;
4901
4902         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4903         return 0;
4904 }
4905
4906 static int
4907 i915_max_freq_set(void *data, u64 val)
4908 {
4909         struct drm_device *dev = data;
4910         struct drm_i915_private *dev_priv = to_i915(dev);
4911         u32 hw_max, hw_min;
4912         int ret;
4913
4914         if (INTEL_INFO(dev)->gen < 6)
4915                 return -ENODEV;
4916
4917         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4918
4919         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4920         if (ret)
4921                 return ret;
4922
4923         /*
4924          * Turbo will still be enabled, but won't go above the set value.
4925          */
4926         val = intel_freq_opcode(dev_priv, val);
4927
4928         hw_max = dev_priv->rps.max_freq;
4929         hw_min = dev_priv->rps.min_freq;
4930
4931         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4932                 mutex_unlock(&dev_priv->rps.hw_lock);
4933                 return -EINVAL;
4934         }
4935
4936         dev_priv->rps.max_freq_softlimit = val;
4937
4938         intel_set_rps(dev_priv, val);
4939
4940         mutex_unlock(&dev_priv->rps.hw_lock);
4941
4942         return 0;
4943 }
4944
4945 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4946                         i915_max_freq_get, i915_max_freq_set,
4947                         "%llu\n");
4948
4949 static int
4950 i915_min_freq_get(void *data, u64 *val)
4951 {
4952         struct drm_device *dev = data;
4953         struct drm_i915_private *dev_priv = to_i915(dev);
4954
4955         if (INTEL_GEN(dev_priv) < 6)
4956                 return -ENODEV;
4957
4958         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4959         return 0;
4960 }
4961
4962 static int
4963 i915_min_freq_set(void *data, u64 val)
4964 {
4965         struct drm_device *dev = data;
4966         struct drm_i915_private *dev_priv = to_i915(dev);
4967         u32 hw_max, hw_min;
4968         int ret;
4969
4970         if (INTEL_GEN(dev_priv) < 6)
4971                 return -ENODEV;
4972
4973         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4974
4975         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4976         if (ret)
4977                 return ret;
4978
4979         /*
4980          * Turbo will still be enabled, but won't go below the set value.
4981          */
4982         val = intel_freq_opcode(dev_priv, val);
4983
4984         hw_max = dev_priv->rps.max_freq;
4985         hw_min = dev_priv->rps.min_freq;
4986
4987         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4988                 mutex_unlock(&dev_priv->rps.hw_lock);
4989                 return -EINVAL;
4990         }
4991
4992         dev_priv->rps.min_freq_softlimit = val;
4993
4994         intel_set_rps(dev_priv, val);
4995
4996         mutex_unlock(&dev_priv->rps.hw_lock);
4997
4998         return 0;
4999 }
5000
5001 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5002                         i915_min_freq_get, i915_min_freq_set,
5003                         "%llu\n");
5004
5005 static int
5006 i915_cache_sharing_get(void *data, u64 *val)
5007 {
5008         struct drm_device *dev = data;
5009         struct drm_i915_private *dev_priv = to_i915(dev);
5010         u32 snpcr;
5011         int ret;
5012
5013         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5014                 return -ENODEV;
5015
5016         ret = mutex_lock_interruptible(&dev->struct_mutex);
5017         if (ret)
5018                 return ret;
5019         intel_runtime_pm_get(dev_priv);
5020
5021         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5022
5023         intel_runtime_pm_put(dev_priv);
5024         mutex_unlock(&dev_priv->drm.struct_mutex);
5025
5026         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5027
5028         return 0;
5029 }
5030
5031 static int
5032 i915_cache_sharing_set(void *data, u64 val)
5033 {
5034         struct drm_device *dev = data;
5035         struct drm_i915_private *dev_priv = to_i915(dev);
5036         u32 snpcr;
5037
5038         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5039                 return -ENODEV;
5040
5041         if (val > 3)
5042                 return -EINVAL;
5043
5044         intel_runtime_pm_get(dev_priv);
5045         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5046
5047         /* Update the cache sharing policy here as well */
5048         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5049         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5050         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5051         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5052
5053         intel_runtime_pm_put(dev_priv);
5054         return 0;
5055 }
5056
5057 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5058                         i915_cache_sharing_get, i915_cache_sharing_set,
5059                         "%llu\n");
5060
5061 struct sseu_dev_status {
5062         unsigned int slice_total;
5063         unsigned int subslice_total;
5064         unsigned int subslice_per_slice;
5065         unsigned int eu_total;
5066         unsigned int eu_per_subslice;
5067 };
5068
5069 static void cherryview_sseu_device_status(struct drm_device *dev,
5070                                           struct sseu_dev_status *stat)
5071 {
5072         struct drm_i915_private *dev_priv = to_i915(dev);
5073         int ss_max = 2;
5074         int ss;
5075         u32 sig1[ss_max], sig2[ss_max];
5076
5077         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5078         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5079         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5080         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5081
5082         for (ss = 0; ss < ss_max; ss++) {
5083                 unsigned int eu_cnt;
5084
5085                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5086                         /* skip disabled subslice */
5087                         continue;
5088
5089                 stat->slice_total = 1;
5090                 stat->subslice_per_slice++;
5091                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5092                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5093                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5094                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5095                 stat->eu_total += eu_cnt;
5096                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5097         }
5098         stat->subslice_total = stat->subslice_per_slice;
5099 }
5100
5101 static void gen9_sseu_device_status(struct drm_device *dev,
5102                                     struct sseu_dev_status *stat)
5103 {
5104         struct drm_i915_private *dev_priv = to_i915(dev);
5105         int s_max = 3, ss_max = 4;
5106         int s, ss;
5107         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5108
5109         /* BXT has a single slice and at most 3 subslices. */
5110         if (IS_BROXTON(dev)) {
5111                 s_max = 1;
5112                 ss_max = 3;
5113         }
5114
5115         for (s = 0; s < s_max; s++) {
5116                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5117                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5118                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5119         }
5120
5121         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5122                      GEN9_PGCTL_SSA_EU19_ACK |
5123                      GEN9_PGCTL_SSA_EU210_ACK |
5124                      GEN9_PGCTL_SSA_EU311_ACK;
5125         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5126                      GEN9_PGCTL_SSB_EU19_ACK |
5127                      GEN9_PGCTL_SSB_EU210_ACK |
5128                      GEN9_PGCTL_SSB_EU311_ACK;
5129
5130         for (s = 0; s < s_max; s++) {
5131                 unsigned int ss_cnt = 0;
5132
5133                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5134                         /* skip disabled slice */
5135                         continue;
5136
5137                 stat->slice_total++;
5138
5139                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5140                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5141
5142                 for (ss = 0; ss < ss_max; ss++) {
5143                         unsigned int eu_cnt;
5144
5145                         if (IS_BROXTON(dev) &&
5146                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5147                                 /* skip disabled subslice */
5148                                 continue;
5149
5150                         if (IS_BROXTON(dev))
5151                                 ss_cnt++;
5152
5153                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5154                                                eu_mask[ss%2]);
5155                         stat->eu_total += eu_cnt;
5156                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5157                                                     eu_cnt);
5158                 }
5159
5160                 stat->subslice_total += ss_cnt;
5161                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5162                                                ss_cnt);
5163         }
5164 }
5165
5166 static void broadwell_sseu_device_status(struct drm_device *dev,
5167                                          struct sseu_dev_status *stat)
5168 {
5169         struct drm_i915_private *dev_priv = to_i915(dev);
5170         int s;
5171         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5172
5173         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5174
5175         if (stat->slice_total) {
5176                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5177                 stat->subslice_total = stat->slice_total *
5178                                        stat->subslice_per_slice;
5179                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5180                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5181
5182                 /* subtract fused off EU(s) from enabled slice(s) */
5183                 for (s = 0; s < stat->slice_total; s++) {
5184                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5185
5186                         stat->eu_total -= hweight8(subslice_7eu);
5187                 }
5188         }
5189 }
5190
5191 static int i915_sseu_status(struct seq_file *m, void *unused)
5192 {
5193         struct drm_info_node *node = (struct drm_info_node *) m->private;
5194         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5195         struct drm_device *dev = &dev_priv->drm;
5196         struct sseu_dev_status stat;
5197
5198         if (INTEL_INFO(dev)->gen < 8)
5199                 return -ENODEV;
5200
5201         seq_puts(m, "SSEU Device Info\n");
5202         seq_printf(m, "  Available Slice Total: %u\n",
5203                    INTEL_INFO(dev)->slice_total);
5204         seq_printf(m, "  Available Subslice Total: %u\n",
5205                    INTEL_INFO(dev)->subslice_total);
5206         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5207                    INTEL_INFO(dev)->subslice_per_slice);
5208         seq_printf(m, "  Available EU Total: %u\n",
5209                    INTEL_INFO(dev)->eu_total);
5210         seq_printf(m, "  Available EU Per Subslice: %u\n",
5211                    INTEL_INFO(dev)->eu_per_subslice);
5212         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5213         if (HAS_POOLED_EU(dev))
5214                 seq_printf(m, "  Min EU in pool: %u\n",
5215                            INTEL_INFO(dev)->min_eu_in_pool);
5216         seq_printf(m, "  Has Slice Power Gating: %s\n",
5217                    yesno(INTEL_INFO(dev)->has_slice_pg));
5218         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5219                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5220         seq_printf(m, "  Has EU Power Gating: %s\n",
5221                    yesno(INTEL_INFO(dev)->has_eu_pg));
5222
5223         seq_puts(m, "SSEU Device Status\n");
5224         memset(&stat, 0, sizeof(stat));
5225
5226         intel_runtime_pm_get(dev_priv);
5227
5228         if (IS_CHERRYVIEW(dev)) {
5229                 cherryview_sseu_device_status(dev, &stat);
5230         } else if (IS_BROADWELL(dev)) {
5231                 broadwell_sseu_device_status(dev, &stat);
5232         } else if (INTEL_INFO(dev)->gen >= 9) {
5233                 gen9_sseu_device_status(dev, &stat);
5234         }
5235
5236         intel_runtime_pm_put(dev_priv);
5237
5238         seq_printf(m, "  Enabled Slice Total: %u\n",
5239                    stat.slice_total);
5240         seq_printf(m, "  Enabled Subslice Total: %u\n",
5241                    stat.subslice_total);
5242         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5243                    stat.subslice_per_slice);
5244         seq_printf(m, "  Enabled EU Total: %u\n",
5245                    stat.eu_total);
5246         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5247                    stat.eu_per_subslice);
5248
5249         return 0;
5250 }
5251
5252 static int i915_forcewake_open(struct inode *inode, struct file *file)
5253 {
5254         struct drm_device *dev = inode->i_private;
5255         struct drm_i915_private *dev_priv = to_i915(dev);
5256
5257         if (INTEL_INFO(dev)->gen < 6)
5258                 return 0;
5259
5260         intel_runtime_pm_get(dev_priv);
5261         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5262
5263         return 0;
5264 }
5265
5266 static int i915_forcewake_release(struct inode *inode, struct file *file)
5267 {
5268         struct drm_device *dev = inode->i_private;
5269         struct drm_i915_private *dev_priv = to_i915(dev);
5270
5271         if (INTEL_INFO(dev)->gen < 6)
5272                 return 0;
5273
5274         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5275         intel_runtime_pm_put(dev_priv);
5276
5277         return 0;
5278 }
5279
5280 static const struct file_operations i915_forcewake_fops = {
5281         .owner = THIS_MODULE,
5282         .open = i915_forcewake_open,
5283         .release = i915_forcewake_release,
5284 };
5285
5286 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5287 {
5288         struct drm_device *dev = minor->dev;
5289         struct dentry *ent;
5290
5291         ent = debugfs_create_file("i915_forcewake_user",
5292                                   S_IRUSR,
5293                                   root, dev,
5294                                   &i915_forcewake_fops);
5295         if (!ent)
5296                 return -ENOMEM;
5297
5298         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5299 }
5300
5301 static int i915_debugfs_create(struct dentry *root,
5302                                struct drm_minor *minor,
5303                                const char *name,
5304                                const struct file_operations *fops)
5305 {
5306         struct drm_device *dev = minor->dev;
5307         struct dentry *ent;
5308
5309         ent = debugfs_create_file(name,
5310                                   S_IRUGO | S_IWUSR,
5311                                   root, dev,
5312                                   fops);
5313         if (!ent)
5314                 return -ENOMEM;
5315
5316         return drm_add_fake_info_node(minor, ent, fops);
5317 }
5318
5319 static const struct drm_info_list i915_debugfs_list[] = {
5320         {"i915_capabilities", i915_capabilities, 0},
5321         {"i915_gem_objects", i915_gem_object_info, 0},
5322         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5323         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5324         {"i915_gem_stolen", i915_gem_stolen_list_info },
5325         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5326         {"i915_gem_request", i915_gem_request_info, 0},
5327         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5328         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5329         {"i915_gem_interrupt", i915_interrupt_info, 0},
5330         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5331         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5332         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5333         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5334         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5335         {"i915_guc_info", i915_guc_info, 0},
5336         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5337         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5338         {"i915_frequency_info", i915_frequency_info, 0},
5339         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5340         {"i915_drpc_info", i915_drpc_info, 0},
5341         {"i915_emon_status", i915_emon_status, 0},
5342         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5343         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5344         {"i915_fbc_status", i915_fbc_status, 0},
5345         {"i915_ips_status", i915_ips_status, 0},
5346         {"i915_sr_status", i915_sr_status, 0},
5347         {"i915_opregion", i915_opregion, 0},
5348         {"i915_vbt", i915_vbt, 0},
5349         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5350         {"i915_context_status", i915_context_status, 0},
5351         {"i915_dump_lrc", i915_dump_lrc, 0},
5352         {"i915_execlists", i915_execlists, 0},
5353         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5354         {"i915_swizzle_info", i915_swizzle_info, 0},
5355         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5356         {"i915_llc", i915_llc, 0},
5357         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5358         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5359         {"i915_energy_uJ", i915_energy_uJ, 0},
5360         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5361         {"i915_power_domain_info", i915_power_domain_info, 0},
5362         {"i915_dmc_info", i915_dmc_info, 0},
5363         {"i915_display_info", i915_display_info, 0},
5364         {"i915_semaphore_status", i915_semaphore_status, 0},
5365         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5366         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5367         {"i915_wa_registers", i915_wa_registers, 0},
5368         {"i915_ddb_info", i915_ddb_info, 0},
5369         {"i915_sseu_status", i915_sseu_status, 0},
5370         {"i915_drrs_status", i915_drrs_status, 0},
5371         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5372 };
5373 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5374
5375 static const struct i915_debugfs_files {
5376         const char *name;
5377         const struct file_operations *fops;
5378 } i915_debugfs_files[] = {
5379         {"i915_wedged", &i915_wedged_fops},
5380         {"i915_max_freq", &i915_max_freq_fops},
5381         {"i915_min_freq", &i915_min_freq_fops},
5382         {"i915_cache_sharing", &i915_cache_sharing_fops},
5383         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5384         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5385         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5386         {"i915_error_state", &i915_error_state_fops},
5387         {"i915_next_seqno", &i915_next_seqno_fops},
5388         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5389         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5390         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5391         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5392         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5393         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5394         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5395         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5396 };
5397
5398 void intel_display_crc_init(struct drm_device *dev)
5399 {
5400         struct drm_i915_private *dev_priv = to_i915(dev);
5401         enum pipe pipe;
5402
5403         for_each_pipe(dev_priv, pipe) {
5404                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5405
5406                 pipe_crc->opened = false;
5407                 spin_lock_init(&pipe_crc->lock);
5408                 init_waitqueue_head(&pipe_crc->wq);
5409         }
5410 }
5411
5412 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5413 {
5414         struct drm_minor *minor = dev_priv->drm.primary;
5415         int ret, i;
5416
5417         ret = i915_forcewake_create(minor->debugfs_root, minor);
5418         if (ret)
5419                 return ret;
5420
5421         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5422                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5423                 if (ret)
5424                         return ret;
5425         }
5426
5427         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5428                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5429                                           i915_debugfs_files[i].name,
5430                                           i915_debugfs_files[i].fops);
5431                 if (ret)
5432                         return ret;
5433         }
5434
5435         return drm_debugfs_create_files(i915_debugfs_list,
5436                                         I915_DEBUGFS_ENTRIES,
5437                                         minor->debugfs_root, minor);
5438 }
5439
5440 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5441 {
5442         struct drm_minor *minor = dev_priv->drm.primary;
5443         int i;
5444
5445         drm_debugfs_remove_files(i915_debugfs_list,
5446                                  I915_DEBUGFS_ENTRIES, minor);
5447
5448         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5449                                  1, minor);
5450
5451         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5452                 struct drm_info_list *info_list =
5453                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5454
5455                 drm_debugfs_remove_files(info_list, 1, minor);
5456         }
5457
5458         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5459                 struct drm_info_list *info_list =
5460                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5461
5462                 drm_debugfs_remove_files(info_list, 1, minor);
5463         }
5464 }
5465
5466 struct dpcd_block {
5467         /* DPCD dump start address. */
5468         unsigned int offset;
5469         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5470         unsigned int end;
5471         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5472         size_t size;
5473         /* Only valid for eDP. */
5474         bool edp;
5475 };
5476
5477 static const struct dpcd_block i915_dpcd_debug[] = {
5478         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5479         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5480         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5481         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5482         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5483         { .offset = DP_SET_POWER },
5484         { .offset = DP_EDP_DPCD_REV },
5485         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5486         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5487         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5488 };
5489
5490 static int i915_dpcd_show(struct seq_file *m, void *data)
5491 {
5492         struct drm_connector *connector = m->private;
5493         struct intel_dp *intel_dp =
5494                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5495         uint8_t buf[16];
5496         ssize_t err;
5497         int i;
5498
5499         if (connector->status != connector_status_connected)
5500                 return -ENODEV;
5501
5502         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5503                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5504                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5505
5506                 if (b->edp &&
5507                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5508                         continue;
5509
5510                 /* low tech for now */
5511                 if (WARN_ON(size > sizeof(buf)))
5512                         continue;
5513
5514                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5515                 if (err <= 0) {
5516                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5517                                   size, b->offset, err);
5518                         continue;
5519                 }
5520
5521                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5522         }
5523
5524         return 0;
5525 }
5526
5527 static int i915_dpcd_open(struct inode *inode, struct file *file)
5528 {
5529         return single_open(file, i915_dpcd_show, inode->i_private);
5530 }
5531
5532 static const struct file_operations i915_dpcd_fops = {
5533         .owner = THIS_MODULE,
5534         .open = i915_dpcd_open,
5535         .read = seq_read,
5536         .llseek = seq_lseek,
5537         .release = single_release,
5538 };
5539
5540 /**
5541  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5542  * @connector: pointer to a registered drm_connector
5543  *
5544  * Cleanup will be done by drm_connector_unregister() through a call to
5545  * drm_debugfs_connector_remove().
5546  *
5547  * Returns 0 on success, negative error codes on error.
5548  */
5549 int i915_debugfs_connector_add(struct drm_connector *connector)
5550 {
5551         struct dentry *root = connector->debugfs_entry;
5552
5553         /* The connector must have been registered beforehands. */
5554         if (!root)
5555                 return -ENODEV;
5556
5557         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5558             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5559                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5560                                     &i915_dpcd_fops);
5561
5562         return 0;
5563 }