drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include <linux/sched/mm.h>
  32 #include "intel_drv.h"
  33 #include "intel_guc_submission.h"
  34
  35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  36 {
  37         return to_i915(node->minor->dev);
  38 }
  39
  40 static __always_inline void seq_print_param(struct seq_file *m,
  41                                             const char *name,
  42                                             const char *type,
  43                                             const void *x)
  44 {
  45         if (!__builtin_strcmp(type, "bool"))
  46                 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
  47         else if (!__builtin_strcmp(type, "int"))
  48                 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
  49         else if (!__builtin_strcmp(type, "unsigned int"))
  50                 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
  51         else if (!__builtin_strcmp(type, "char *"))
  52                 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
  53         else
  54                 BUILD_BUG();
  55 }
  56
  57 static int i915_capabilities(struct seq_file *m, void *data)
  58 {
  59         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  60         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  61
  62         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  63         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  64         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  65
  66 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  67         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  68 #undef PRINT_FLAG
  69
  70         kernel_param_lock(THIS_MODULE);
  71 #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
  72         I915_PARAMS_FOR_EACH(PRINT_PARAM);
  73 #undef PRINT_PARAM
  74         kernel_param_unlock(THIS_MODULE);
  75
  76         return 0;
  77 }
  78
  79 static char get_active_flag(struct drm_i915_gem_object *obj)
  80 {
  81         return i915_gem_object_is_active(obj) ? '*' : ' ';
  82 }
  83
  84 static char get_pin_flag(struct drm_i915_gem_object *obj)
  85 {
  86         return obj->pin_global ? 'p' : ' ';
  87 }
  88
  89 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  90 {
  91         switch (i915_gem_object_get_tiling(obj)) {
  92         default:
  93         case I915_TILING_NONE: return ' ';
  94         case I915_TILING_X: return 'X';
  95         case I915_TILING_Y: return 'Y';
  96         }
  97 }
  98
  99 static char get_global_flag(struct drm_i915_gem_object *obj)
 100 {
 101         return obj->userfault_count ? 'g' : ' ';
 102 }
 103
 104 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 105 {
 106         return obj->mm.mapping ? 'M' : ' ';
 107 }
 108
 109 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 110 {
 111         u64 size = 0;
 112         struct i915_vma *vma;
 113
 114         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 115                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 116                         size += vma->node.size;
 117         }
 118
 119         return size;
 120 }
 121
 122 static const char *
 123 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
 124 {
 125         size_t x = 0;
 126
 127         switch (page_sizes) {
 128         case 0:
 129                 return "";
 130         case I915_GTT_PAGE_SIZE_4K:
 131                 return "4K";
 132         case I915_GTT_PAGE_SIZE_64K:
 133                 return "64K";
 134         case I915_GTT_PAGE_SIZE_2M:
 135                 return "2M";
 136         default:
 137                 if (!buf)
 138                         return "M";
 139
 140                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 141                         x += snprintf(buf + x, len - x, "2M, ");
 142                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 143                         x += snprintf(buf + x, len - x, "64K, ");
 144                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 145                         x += snprintf(buf + x, len - x, "4K, ");
 146                 buf[x-2] = '\0';
 147
 148                 return buf;
 149         }
 150 }
 151
 152 static void
 153 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 154 {
 155         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 156         struct intel_engine_cs *engine;
 157         struct i915_vma *vma;
 158         unsigned int frontbuffer_bits;
 159         int pin_count = 0;
 160
 161         lockdep_assert_held(&obj->base.dev->struct_mutex);
 162
 163         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 164                    &obj->base,
 165                    get_active_flag(obj),
 166                    get_pin_flag(obj),
 167                    get_tiling_flag(obj),
 168                    get_global_flag(obj),
 169                    get_pin_mapped_flag(obj),
 170                    obj->base.size / 1024,
 171                    obj->base.read_domains,
 172                    obj->base.write_domain,
 173                    i915_cache_level_str(dev_priv, obj->cache_level),
 174                    obj->mm.dirty ? " dirty" : "",
 175                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 176         if (obj->base.name)
 177                 seq_printf(m, " (name: %d)", obj->base.name);
 178         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 179                 if (i915_vma_is_pinned(vma))
 180                         pin_count++;
 181         }
 182         seq_printf(m, " (pinned x %d)", pin_count);
 183         if (obj->pin_global)
 184                 seq_printf(m, " (global)");
 185         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 186                 if (!drm_mm_node_allocated(&vma->node))
 187                         continue;
 188
 189                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 190                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 191                            vma->node.start, vma->node.size,
 192                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 193                 if (i915_vma_is_ggtt(vma)) {
 194                         switch (vma->ggtt_view.type) {
 195                         case I915_GGTT_VIEW_NORMAL:
 196                                 seq_puts(m, ", normal");
 197                                 break;
 198
 199                         case I915_GGTT_VIEW_PARTIAL:
 200                                 seq_printf(m, ", partial [%08llx+%x]",
 201                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 202                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 203                                 break;
 204
 205                         case I915_GGTT_VIEW_ROTATED:
 206                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 207                                            vma->ggtt_view.rotated.plane[0].width,
 208                                            vma->ggtt_view.rotated.plane[0].height,
 209                                            vma->ggtt_view.rotated.plane[0].stride,
 210                                            vma->ggtt_view.rotated.plane[0].offset,
 211                                            vma->ggtt_view.rotated.plane[1].width,
 212                                            vma->ggtt_view.rotated.plane[1].height,
 213                                            vma->ggtt_view.rotated.plane[1].stride,
 214                                            vma->ggtt_view.rotated.plane[1].offset);
 215                                 break;
 216
 217                         default:
 218                                 MISSING_CASE(vma->ggtt_view.type);
 219                                 break;
 220                         }
 221                 }
 222                 if (vma->fence)
 223                         seq_printf(m, " , fence: %d%s",
 224                                    vma->fence->id,
 225                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 226                 seq_puts(m, ")");
 227         }
 228         if (obj->stolen)
 229                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 230
 231         engine = i915_gem_object_last_write_engine(obj);
 232         if (engine)
 233                 seq_printf(m, " (%s)", engine->name);
 234
 235         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 236         if (frontbuffer_bits)
 237                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 238 }
 239
 240 static int obj_rank_by_stolen(const void *A, const void *B)
 241 {
 242         const struct drm_i915_gem_object *a =
 243                 *(const struct drm_i915_gem_object **)A;
 244         const struct drm_i915_gem_object *b =
 245                 *(const struct drm_i915_gem_object **)B;
 246
 247         if (a->stolen->start < b->stolen->start)
 248                 return -1;
 249         if (a->stolen->start > b->stolen->start)
 250                 return 1;
 251         return 0;
 252 }
 253
 254 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 255 {
 256         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 257         struct drm_device *dev = &dev_priv->drm;
 258         struct drm_i915_gem_object **objects;
 259         struct drm_i915_gem_object *obj;
 260         u64 total_obj_size, total_gtt_size;
 261         unsigned long total, count, n;
 262         int ret;
 263
 264         total = READ_ONCE(dev_priv->mm.object_count);
 265         objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
 266         if (!objects)
 267                 return -ENOMEM;
 268
 269         ret = mutex_lock_interruptible(&dev->struct_mutex);
 270         if (ret)
 271                 goto out;
 272
 273         total_obj_size = total_gtt_size = count = 0;
 274
 275         spin_lock(&dev_priv->mm.obj_lock);
 276         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 277                 if (count == total)
 278                         break;
 279
 280                 if (obj->stolen == NULL)
 281                         continue;
 282
 283                 objects[count++] = obj;
 284                 total_obj_size += obj->base.size;
 285                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 286
 287         }
 288         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 289                 if (count == total)
 290                         break;
 291
 292                 if (obj->stolen == NULL)
 293                         continue;
 294
 295                 objects[count++] = obj;
 296                 total_obj_size += obj->base.size;
 297         }
 298         spin_unlock(&dev_priv->mm.obj_lock);
 299
 300         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 301
 302         seq_puts(m, "Stolen:\n");
 303         for (n = 0; n < count; n++) {
 304                 seq_puts(m, "   ");
 305                 describe_obj(m, objects[n]);
 306                 seq_putc(m, '\n');
 307         }
 308         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 309                    count, total_obj_size, total_gtt_size);
 310
 311         mutex_unlock(&dev->struct_mutex);
 312 out:
 313         kvfree(objects);
 314         return ret;
 315 }
 316
 317 struct file_stats {
 318         struct drm_i915_file_private *file_priv;
 319         unsigned long count;
 320         u64 total, unbound;
 321         u64 global, shared;
 322         u64 active, inactive;
 323 };
 324
 325 static int per_file_stats(int id, void *ptr, void *data)
 326 {
 327         struct drm_i915_gem_object *obj = ptr;
 328         struct file_stats *stats = data;
 329         struct i915_vma *vma;
 330
 331         lockdep_assert_held(&obj->base.dev->struct_mutex);
 332
 333         stats->count++;
 334         stats->total += obj->base.size;
 335         if (!obj->bind_count)
 336                 stats->unbound += obj->base.size;
 337         if (obj->base.name || obj->base.dma_buf)
 338                 stats->shared += obj->base.size;
 339
 340         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 341                 if (!drm_mm_node_allocated(&vma->node))
 342                         continue;
 343
 344                 if (i915_vma_is_ggtt(vma)) {
 345                         stats->global += vma->node.size;
 346                 } else {
 347                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 348
 349                         if (ppgtt->base.file != stats->file_priv)
 350                                 continue;
 351                 }
 352
 353                 if (i915_vma_is_active(vma))
 354                         stats->active += vma->node.size;
 355                 else
 356                         stats->inactive += vma->node.size;
 357         }
 358
 359         return 0;
 360 }
 361
 362 #define print_file_stats(m, name, stats) do { \
 363         if (stats.count) \
 364                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 365                            name, \
 366                            stats.count, \
 367                            stats.total, \
 368                            stats.active, \
 369                            stats.inactive, \
 370                            stats.global, \
 371                            stats.shared, \
 372                            stats.unbound); \
 373 } while (0)
 374
 375 static void print_batch_pool_stats(struct seq_file *m,
 376                                    struct drm_i915_private *dev_priv)
 377 {
 378         struct drm_i915_gem_object *obj;
 379         struct file_stats stats;
 380         struct intel_engine_cs *engine;
 381         enum intel_engine_id id;
 382         int j;
 383
 384         memset(&stats, 0, sizeof(stats));
 385
 386         for_each_engine(engine, dev_priv, id) {
 387                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 388                         list_for_each_entry(obj,
 389                                             &engine->batch_pool.cache_list[j],
 390                                             batch_pool_link)
 391                                 per_file_stats(0, obj, &stats);
 392                 }
 393         }
 394
 395         print_file_stats(m, "[k]batch pool", stats);
 396 }
 397
 398 static int per_file_ctx_stats(int id, void *ptr, void *data)
 399 {
 400         struct i915_gem_context *ctx = ptr;
 401         int n;
 402
 403         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 404                 if (ctx->engine[n].state)
 405                         per_file_stats(0, ctx->engine[n].state->obj, data);
 406                 if (ctx->engine[n].ring)
 407                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 408         }
 409
 410         return 0;
 411 }
 412
 413 static void print_context_stats(struct seq_file *m,
 414                                 struct drm_i915_private *dev_priv)
 415 {
 416         struct drm_device *dev = &dev_priv->drm;
 417         struct file_stats stats;
 418         struct drm_file *file;
 419
 420         memset(&stats, 0, sizeof(stats));
 421
 422         mutex_lock(&dev->struct_mutex);
 423         if (dev_priv->kernel_context)
 424                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 425
 426         list_for_each_entry(file, &dev->filelist, lhead) {
 427                 struct drm_i915_file_private *fpriv = file->driver_priv;
 428                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 429         }
 430         mutex_unlock(&dev->struct_mutex);
 431
 432         print_file_stats(m, "[k]contexts", stats);
 433 }
 434
 435 static int i915_gem_object_info(struct seq_file *m, void *data)
 436 {
 437         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 438         struct drm_device *dev = &dev_priv->drm;
 439         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 440         u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
 441         u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
 442         struct drm_i915_gem_object *obj;
 443         unsigned int page_sizes = 0;
 444         struct drm_file *file;
 445         char buf[80];
 446         int ret;
 447
 448         ret = mutex_lock_interruptible(&dev->struct_mutex);
 449         if (ret)
 450                 return ret;
 451
 452         seq_printf(m, "%u objects, %llu bytes\n",
 453                    dev_priv->mm.object_count,
 454                    dev_priv->mm.object_memory);
 455
 456         size = count = 0;
 457         mapped_size = mapped_count = 0;
 458         purgeable_size = purgeable_count = 0;
 459         huge_size = huge_count = 0;
 460
 461         spin_lock(&dev_priv->mm.obj_lock);
 462         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 463                 size += obj->base.size;
 464                 ++count;
 465
 466                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 467                         purgeable_size += obj->base.size;
 468                         ++purgeable_count;
 469                 }
 470
 471                 if (obj->mm.mapping) {
 472                         mapped_count++;
 473                         mapped_size += obj->base.size;
 474                 }
 475
 476                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 477                         huge_count++;
 478                         huge_size += obj->base.size;
 479                         page_sizes |= obj->mm.page_sizes.sg;
 480                 }
 481         }
 482         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 483
 484         size = count = dpy_size = dpy_count = 0;
 485         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 486                 size += obj->base.size;
 487                 ++count;
 488
 489                 if (obj->pin_global) {
 490                         dpy_size += obj->base.size;
 491                         ++dpy_count;
 492                 }
 493
 494                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 495                         purgeable_size += obj->base.size;
 496                         ++purgeable_count;
 497                 }
 498
 499                 if (obj->mm.mapping) {
 500                         mapped_count++;
 501                         mapped_size += obj->base.size;
 502                 }
 503
 504                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 505                         huge_count++;
 506                         huge_size += obj->base.size;
 507                         page_sizes |= obj->mm.page_sizes.sg;
 508                 }
 509         }
 510         spin_unlock(&dev_priv->mm.obj_lock);
 511
 512         seq_printf(m, "%u bound objects, %llu bytes\n",
 513                    count, size);
 514         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 515                    purgeable_count, purgeable_size);
 516         seq_printf(m, "%u mapped objects, %llu bytes\n",
 517                    mapped_count, mapped_size);
 518         seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
 519                    huge_count,
 520                    stringify_page_sizes(page_sizes, buf, sizeof(buf)),
 521                    huge_size);
 522         seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
 523                    dpy_count, dpy_size);
 524
 525         seq_printf(m, "%llu [%llu] gtt total\n",
 526                    ggtt->base.total, ggtt->mappable_end);
 527         seq_printf(m, "Supported page sizes: %s\n",
 528                    stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
 529                                         buf, sizeof(buf)));
 530
 531         seq_putc(m, '\n');
 532         print_batch_pool_stats(m, dev_priv);
 533         mutex_unlock(&dev->struct_mutex);
 534
 535         mutex_lock(&dev->filelist_mutex);
 536         print_context_stats(m, dev_priv);
 537         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 538                 struct file_stats stats;
 539                 struct drm_i915_file_private *file_priv = file->driver_priv;
 540                 struct drm_i915_gem_request *request;
 541                 struct task_struct *task;
 542
 543                 mutex_lock(&dev->struct_mutex);
 544
 545                 memset(&stats, 0, sizeof(stats));
 546                 stats.file_priv = file->driver_priv;
 547                 spin_lock(&file->table_lock);
 548                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 549                 spin_unlock(&file->table_lock);
 550                 /*
 551                  * Although we have a valid reference on file->pid, that does
 552                  * not guarantee that the task_struct who called get_pid() is
 553                  * still alive (e.g. get_pid(current) => fork() => exit()).
 554                  * Therefore, we need to protect this ->comm access using RCU.
 555                  */
 556                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 557                                                    struct drm_i915_gem_request,
 558                                                    client_link);
 559                 rcu_read_lock();
 560                 task = pid_task(request && request->ctx->pid ?
 561                                 request->ctx->pid : file->pid,
 562                                 PIDTYPE_PID);
 563                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 564                 rcu_read_unlock();
 565
 566                 mutex_unlock(&dev->struct_mutex);
 567         }
 568         mutex_unlock(&dev->filelist_mutex);
 569
 570         return 0;
 571 }
 572
 573 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 574 {
 575         struct drm_info_node *node = m->private;
 576         struct drm_i915_private *dev_priv = node_to_i915(node);
 577         struct drm_device *dev = &dev_priv->drm;
 578         struct drm_i915_gem_object **objects;
 579         struct drm_i915_gem_object *obj;
 580         u64 total_obj_size, total_gtt_size;
 581         unsigned long nobject, n;
 582         int count, ret;
 583
 584         nobject = READ_ONCE(dev_priv->mm.object_count);
 585         objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
 586         if (!objects)
 587                 return -ENOMEM;
 588
 589         ret = mutex_lock_interruptible(&dev->struct_mutex);
 590         if (ret)
 591                 return ret;
 592
 593         count = 0;
 594         spin_lock(&dev_priv->mm.obj_lock);
 595         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 596                 objects[count++] = obj;
 597                 if (count == nobject)
 598                         break;
 599         }
 600         spin_unlock(&dev_priv->mm.obj_lock);
 601
 602         total_obj_size = total_gtt_size = 0;
 603         for (n = 0;  n < count; n++) {
 604                 obj = objects[n];
 605
 606                 seq_puts(m, "   ");
 607                 describe_obj(m, obj);
 608                 seq_putc(m, '\n');
 609                 total_obj_size += obj->base.size;
 610                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 611         }
 612
 613         mutex_unlock(&dev->struct_mutex);
 614
 615         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 616                    count, total_obj_size, total_gtt_size);
 617         kvfree(objects);
 618
 619         return 0;
 620 }
 621
 622 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 623 {
 624         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 625         struct drm_device *dev = &dev_priv->drm;
 626         struct drm_i915_gem_object *obj;
 627         struct intel_engine_cs *engine;
 628         enum intel_engine_id id;
 629         int total = 0;
 630         int ret, j;
 631
 632         ret = mutex_lock_interruptible(&dev->struct_mutex);
 633         if (ret)
 634                 return ret;
 635
 636         for_each_engine(engine, dev_priv, id) {
 637                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 638                         int count;
 639
 640                         count = 0;
 641                         list_for_each_entry(obj,
 642                                             &engine->batch_pool.cache_list[j],
 643                                             batch_pool_link)
 644                                 count++;
 645                         seq_printf(m, "%s cache[%d]: %d objects\n",
 646                                    engine->name, j, count);
 647
 648                         list_for_each_entry(obj,
 649                                             &engine->batch_pool.cache_list[j],
 650                                             batch_pool_link) {
 651                                 seq_puts(m, "   ");
 652                                 describe_obj(m, obj);
 653                                 seq_putc(m, '\n');
 654                         }
 655
 656                         total += count;
 657                 }
 658         }
 659
 660         seq_printf(m, "total: %d\n", total);
 661
 662         mutex_unlock(&dev->struct_mutex);
 663
 664         return 0;
 665 }
 666
 667 static void i915_ring_seqno_info(struct seq_file *m,
 668                                  struct intel_engine_cs *engine)
 669 {
 670         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 671         struct rb_node *rb;
 672
 673         seq_printf(m, "Current sequence (%s): %x\n",
 674                    engine->name, intel_engine_get_seqno(engine));
 675
 676         spin_lock_irq(&b->rb_lock);
 677         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 678                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 679
 680                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 681                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 682         }
 683         spin_unlock_irq(&b->rb_lock);
 684 }
 685
 686 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 687 {
 688         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 689         struct intel_engine_cs *engine;
 690         enum intel_engine_id id;
 691
 692         for_each_engine(engine, dev_priv, id)
 693                 i915_ring_seqno_info(m, engine);
 694
 695         return 0;
 696 }
 697
 698
 699 static int i915_interrupt_info(struct seq_file *m, void *data)
 700 {
 701         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 702         struct intel_engine_cs *engine;
 703         enum intel_engine_id id;
 704         int i, pipe;
 705
 706         intel_runtime_pm_get(dev_priv);
 707
 708         if (IS_CHERRYVIEW(dev_priv)) {
 709                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 710                            I915_READ(GEN8_MASTER_IRQ));
 711
 712                 seq_printf(m, "Display IER:\t%08x\n",
 713                            I915_READ(VLV_IER));
 714                 seq_printf(m, "Display IIR:\t%08x\n",
 715                            I915_READ(VLV_IIR));
 716                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 717                            I915_READ(VLV_IIR_RW));
 718                 seq_printf(m, "Display IMR:\t%08x\n",
 719                            I915_READ(VLV_IMR));
 720                 for_each_pipe(dev_priv, pipe) {
 721                         enum intel_display_power_domain power_domain;
 722
 723                         power_domain = POWER_DOMAIN_PIPE(pipe);
 724                         if (!intel_display_power_get_if_enabled(dev_priv,
 725                                                                 power_domain)) {
 726                                 seq_printf(m, "Pipe %c power disabled\n",
 727                                            pipe_name(pipe));
 728                                 continue;
 729                         }
 730
 731                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 732                                    pipe_name(pipe),
 733                                    I915_READ(PIPESTAT(pipe)));
 734
 735                         intel_display_power_put(dev_priv, power_domain);
 736                 }
 737
 738                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 739                 seq_printf(m, "Port hotplug:\t%08x\n",
 740                            I915_READ(PORT_HOTPLUG_EN));
 741                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 742                            I915_READ(VLV_DPFLIPSTAT));
 743                 seq_printf(m, "DPINVGTT:\t%08x\n",
 744                            I915_READ(DPINVGTT));
 745                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 746
 747                 for (i = 0; i < 4; i++) {
 748                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 749                                    i, I915_READ(GEN8_GT_IMR(i)));
 750                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 751                                    i, I915_READ(GEN8_GT_IIR(i)));
 752                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 753                                    i, I915_READ(GEN8_GT_IER(i)));
 754                 }
 755
 756                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 757                            I915_READ(GEN8_PCU_IMR));
 758                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 759                            I915_READ(GEN8_PCU_IIR));
 760                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 761                            I915_READ(GEN8_PCU_IER));
 762         } else if (INTEL_GEN(dev_priv) >= 8) {
 763                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 764                            I915_READ(GEN8_MASTER_IRQ));
 765
 766                 for (i = 0; i < 4; i++) {
 767                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IMR(i)));
 769                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 770                                    i, I915_READ(GEN8_GT_IIR(i)));
 771                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 772                                    i, I915_READ(GEN8_GT_IER(i)));
 773                 }
 774
 775                 for_each_pipe(dev_priv, pipe) {
 776                         enum intel_display_power_domain power_domain;
 777
 778                         power_domain = POWER_DOMAIN_PIPE(pipe);
 779                         if (!intel_display_power_get_if_enabled(dev_priv,
 780                                                                 power_domain)) {
 781                                 seq_printf(m, "Pipe %c power disabled\n",
 782                                            pipe_name(pipe));
 783                                 continue;
 784                         }
 785                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 786                                    pipe_name(pipe),
 787                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 788                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 789                                    pipe_name(pipe),
 790                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 791                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 792                                    pipe_name(pipe),
 793                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 794
 795                         intel_display_power_put(dev_priv, power_domain);
 796                 }
 797
 798                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 799                            I915_READ(GEN8_DE_PORT_IMR));
 800                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 801                            I915_READ(GEN8_DE_PORT_IIR));
 802                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 803                            I915_READ(GEN8_DE_PORT_IER));
 804
 805                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 806                            I915_READ(GEN8_DE_MISC_IMR));
 807                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 808                            I915_READ(GEN8_DE_MISC_IIR));
 809                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 810                            I915_READ(GEN8_DE_MISC_IER));
 811
 812                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 813                            I915_READ(GEN8_PCU_IMR));
 814                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 815                            I915_READ(GEN8_PCU_IIR));
 816                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 817                            I915_READ(GEN8_PCU_IER));
 818         } else if (IS_VALLEYVIEW(dev_priv)) {
 819                 seq_printf(m, "Display IER:\t%08x\n",
 820                            I915_READ(VLV_IER));
 821                 seq_printf(m, "Display IIR:\t%08x\n",
 822                            I915_READ(VLV_IIR));
 823                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 824                            I915_READ(VLV_IIR_RW));
 825                 seq_printf(m, "Display IMR:\t%08x\n",
 826                            I915_READ(VLV_IMR));
 827                 for_each_pipe(dev_priv, pipe) {
 828                         enum intel_display_power_domain power_domain;
 829
 830                         power_domain = POWER_DOMAIN_PIPE(pipe);
 831                         if (!intel_display_power_get_if_enabled(dev_priv,
 832                                                                 power_domain)) {
 833                                 seq_printf(m, "Pipe %c power disabled\n",
 834                                            pipe_name(pipe));
 835                                 continue;
 836                         }
 837
 838                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 839                                    pipe_name(pipe),
 840                                    I915_READ(PIPESTAT(pipe)));
 841                         intel_display_power_put(dev_priv, power_domain);
 842                 }
 843
 844                 seq_printf(m, "Master IER:\t%08x\n",
 845                            I915_READ(VLV_MASTER_IER));
 846
 847                 seq_printf(m, "Render IER:\t%08x\n",
 848                            I915_READ(GTIER));
 849                 seq_printf(m, "Render IIR:\t%08x\n",
 850                            I915_READ(GTIIR));
 851                 seq_printf(m, "Render IMR:\t%08x\n",
 852                            I915_READ(GTIMR));
 853
 854                 seq_printf(m, "PM IER:\t\t%08x\n",
 855                            I915_READ(GEN6_PMIER));
 856                 seq_printf(m, "PM IIR:\t\t%08x\n",
 857                            I915_READ(GEN6_PMIIR));
 858                 seq_printf(m, "PM IMR:\t\t%08x\n",
 859                            I915_READ(GEN6_PMIMR));
 860
 861                 seq_printf(m, "Port hotplug:\t%08x\n",
 862                            I915_READ(PORT_HOTPLUG_EN));
 863                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 864                            I915_READ(VLV_DPFLIPSTAT));
 865                 seq_printf(m, "DPINVGTT:\t%08x\n",
 866                            I915_READ(DPINVGTT));
 867
 868         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 869                 seq_printf(m, "Interrupt enable:    %08x\n",
 870                            I915_READ(IER));
 871                 seq_printf(m, "Interrupt identity:  %08x\n",
 872                            I915_READ(IIR));
 873                 seq_printf(m, "Interrupt mask:      %08x\n",
 874                            I915_READ(IMR));
 875                 for_each_pipe(dev_priv, pipe)
 876                         seq_printf(m, "Pipe %c stat:         %08x\n",
 877                                    pipe_name(pipe),
 878                                    I915_READ(PIPESTAT(pipe)));
 879         } else {
 880                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 881                            I915_READ(DEIER));
 882                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 883                            I915_READ(DEIIR));
 884                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 885                            I915_READ(DEIMR));
 886                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 887                            I915_READ(SDEIER));
 888                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 889                            I915_READ(SDEIIR));
 890                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 891                            I915_READ(SDEIMR));
 892                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 893                            I915_READ(GTIER));
 894                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 895                            I915_READ(GTIIR));
 896                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 897                            I915_READ(GTIMR));
 898         }
 899         for_each_engine(engine, dev_priv, id) {
 900                 if (INTEL_GEN(dev_priv) >= 6) {
 901                         seq_printf(m,
 902                                    "Graphics Interrupt mask (%s):       %08x\n",
 903                                    engine->name, I915_READ_IMR(engine));
 904                 }
 905                 i915_ring_seqno_info(m, engine);
 906         }
 907         intel_runtime_pm_put(dev_priv);
 908
 909         return 0;
 910 }
 911
 912 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 913 {
 914         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 915         struct drm_device *dev = &dev_priv->drm;
 916         int i, ret;
 917
 918         ret = mutex_lock_interruptible(&dev->struct_mutex);
 919         if (ret)
 920                 return ret;
 921
 922         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 923         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 924                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 925
 926                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 927                            i, dev_priv->fence_regs[i].pin_count);
 928                 if (!vma)
 929                         seq_puts(m, "unused");
 930                 else
 931                         describe_obj(m, vma->obj);
 932                 seq_putc(m, '\n');
 933         }
 934
 935         mutex_unlock(&dev->struct_mutex);
 936         return 0;
 937 }
 938
 939 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 940 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 941                               size_t count, loff_t *pos)
 942 {
 943         struct i915_gpu_state *error = file->private_data;
 944         struct drm_i915_error_state_buf str;
 945         ssize_t ret;
 946         loff_t tmp;
 947
 948         if (!error)
 949                 return 0;
 950
 951         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 952         if (ret)
 953                 return ret;
 954
 955         ret = i915_error_state_to_str(&str, error);
 956         if (ret)
 957                 goto out;
 958
 959         tmp = 0;
 960         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 961         if (ret < 0)
 962                 goto out;
 963
 964         *pos = str.start + ret;
 965 out:
 966         i915_error_state_buf_release(&str);
 967         return ret;
 968 }
 969
 970 static int gpu_state_release(struct inode *inode, struct file *file)
 971 {
 972         i915_gpu_state_put(file->private_data);
 973         return 0;
 974 }
 975
 976 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 977 {
 978         struct drm_i915_private *i915 = inode->i_private;
 979         struct i915_gpu_state *gpu;
 980
 981         intel_runtime_pm_get(i915);
 982         gpu = i915_capture_gpu_state(i915);
 983         intel_runtime_pm_put(i915);
 984         if (!gpu)
 985                 return -ENOMEM;
 986
 987         file->private_data = gpu;
 988         return 0;
 989 }
 990
 991 static const struct file_operations i915_gpu_info_fops = {
 992         .owner = THIS_MODULE,
 993         .open = i915_gpu_info_open,
 994         .read = gpu_state_read,
 995         .llseek = default_llseek,
 996         .release = gpu_state_release,
 997 };
 998
 999 static ssize_t
1000 i915_error_state_write(struct file *filp,
1001                        const char __user *ubuf,
1002                        size_t cnt,
1003                        loff_t *ppos)
1004 {
1005         struct i915_gpu_state *error = filp->private_data;
1006
1007         if (!error)
1008                 return 0;
1009
1010         DRM_DEBUG_DRIVER("Resetting error state\n");
1011         i915_reset_error_state(error->i915);
1012
1013         return cnt;
1014 }
1015
1016 static int i915_error_state_open(struct inode *inode, struct file *file)
1017 {
1018         file->private_data = i915_first_error_state(inode->i_private);
1019         return 0;
1020 }
1021
1022 static const struct file_operations i915_error_state_fops = {
1023         .owner = THIS_MODULE,
1024         .open = i915_error_state_open,
1025         .read = gpu_state_read,
1026         .write = i915_error_state_write,
1027         .llseek = default_llseek,
1028         .release = gpu_state_release,
1029 };
1030 #endif
1031
1032 static int
1033 i915_next_seqno_set(void *data, u64 val)
1034 {
1035         struct drm_i915_private *dev_priv = data;
1036         struct drm_device *dev = &dev_priv->drm;
1037         int ret;
1038
1039         ret = mutex_lock_interruptible(&dev->struct_mutex);
1040         if (ret)
1041                 return ret;
1042
1043         ret = i915_gem_set_global_seqno(dev, val);
1044         mutex_unlock(&dev->struct_mutex);
1045
1046         return ret;
1047 }
1048
1049 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1050                         NULL, i915_next_seqno_set,
1051                         "0x%llx\n");
1052
1053 static int i915_frequency_info(struct seq_file *m, void *unused)
1054 {
1055         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1056         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1057         int ret = 0;
1058
1059         intel_runtime_pm_get(dev_priv);
1060
1061         if (IS_GEN5(dev_priv)) {
1062                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1063                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1064
1065                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1066                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1067                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1068                            MEMSTAT_VID_SHIFT);
1069                 seq_printf(m, "Current P-state: %d\n",
1070                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1071         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1072                 u32 rpmodectl, freq_sts;
1073
1074                 mutex_lock(&dev_priv->pcu_lock);
1075
1076                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1077                 seq_printf(m, "Video Turbo Mode: %s\n",
1078                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1079                 seq_printf(m, "HW control enabled: %s\n",
1080                            yesno(rpmodectl & GEN6_RP_ENABLE));
1081                 seq_printf(m, "SW control enabled: %s\n",
1082                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1083                                   GEN6_RP_MEDIA_SW_MODE));
1084
1085                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1086                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1087                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1088
1089                 seq_printf(m, "actual GPU freq: %d MHz\n",
1090                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1091
1092                 seq_printf(m, "current GPU freq: %d MHz\n",
1093                            intel_gpu_freq(dev_priv, rps->cur_freq));
1094
1095                 seq_printf(m, "max GPU freq: %d MHz\n",
1096                            intel_gpu_freq(dev_priv, rps->max_freq));
1097
1098                 seq_printf(m, "min GPU freq: %d MHz\n",
1099                            intel_gpu_freq(dev_priv, rps->min_freq));
1100
1101                 seq_printf(m, "idle GPU freq: %d MHz\n",
1102                            intel_gpu_freq(dev_priv, rps->idle_freq));
1103
1104                 seq_printf(m,
1105                            "efficient (RPe) frequency: %d MHz\n",
1106                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1107                 mutex_unlock(&dev_priv->pcu_lock);
1108         } else if (INTEL_GEN(dev_priv) >= 6) {
1109                 u32 rp_state_limits;
1110                 u32 gt_perf_status;
1111                 u32 rp_state_cap;
1112                 u32 rpmodectl, rpinclimit, rpdeclimit;
1113                 u32 rpstat, cagf, reqf;
1114                 u32 rpupei, rpcurup, rpprevup;
1115                 u32 rpdownei, rpcurdown, rpprevdown;
1116                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1117                 int max_freq;
1118
1119                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1120                 if (IS_GEN9_LP(dev_priv)) {
1121                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1122                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1123                 } else {
1124                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1125                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1126                 }
1127
1128                 /* RPSTAT1 is in the GT power well */
1129                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1130
1131                 reqf = I915_READ(GEN6_RPNSWREQ);
1132                 if (INTEL_GEN(dev_priv) >= 9)
1133                         reqf >>= 23;
1134                 else {
1135                         reqf &= ~GEN6_TURBO_DISABLE;
1136                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1137                                 reqf >>= 24;
1138                         else
1139                                 reqf >>= 25;
1140                 }
1141                 reqf = intel_gpu_freq(dev_priv, reqf);
1142
1143                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1144                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1145                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1146
1147                 rpstat = I915_READ(GEN6_RPSTAT1);
1148                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1149                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1150                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1151                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1152                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1153                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1154                 if (INTEL_GEN(dev_priv) >= 9)
1155                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1156                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1157                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1158                 else
1159                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1160                 cagf = intel_gpu_freq(dev_priv, cagf);
1161
1162                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1163
1164                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1165                         pm_ier = I915_READ(GEN6_PMIER);
1166                         pm_imr = I915_READ(GEN6_PMIMR);
1167                         pm_isr = I915_READ(GEN6_PMISR);
1168                         pm_iir = I915_READ(GEN6_PMIIR);
1169                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1170                 } else {
1171                         pm_ier = I915_READ(GEN8_GT_IER(2));
1172                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1173                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1174                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1175                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1176                 }
1177                 seq_printf(m, "Video Turbo Mode: %s\n",
1178                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1179                 seq_printf(m, "HW control enabled: %s\n",
1180                            yesno(rpmodectl & GEN6_RP_ENABLE));
1181                 seq_printf(m, "SW control enabled: %s\n",
1182                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1183                                   GEN6_RP_MEDIA_SW_MODE));
1184                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1185                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1186                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1187                            rps->pm_intrmsk_mbz);
1188                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1189                 seq_printf(m, "Render p-state ratio: %d\n",
1190                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1191                 seq_printf(m, "Render p-state VID: %d\n",
1192                            gt_perf_status & 0xff);
1193                 seq_printf(m, "Render p-state limit: %d\n",
1194                            rp_state_limits & 0xff);
1195                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1196                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1197                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1198                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1199                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1200                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1201                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1202                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1203                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1204                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1205                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1206                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1207                 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1208
1209                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1210                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1211                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1212                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1213                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1214                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1215                 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1216
1217                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1218                             rp_state_cap >> 16) & 0xff;
1219                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1220                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1221                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1222                            intel_gpu_freq(dev_priv, max_freq));
1223
1224                 max_freq = (rp_state_cap & 0xff00) >> 8;
1225                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1226                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1227                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1228                            intel_gpu_freq(dev_priv, max_freq));
1229
1230                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1231                             rp_state_cap >> 0) & 0xff;
1232                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1233                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1234                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1235                            intel_gpu_freq(dev_priv, max_freq));
1236                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1237                            intel_gpu_freq(dev_priv, rps->max_freq));
1238
1239                 seq_printf(m, "Current freq: %d MHz\n",
1240                            intel_gpu_freq(dev_priv, rps->cur_freq));
1241                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1242                 seq_printf(m, "Idle freq: %d MHz\n",
1243                            intel_gpu_freq(dev_priv, rps->idle_freq));
1244                 seq_printf(m, "Min freq: %d MHz\n",
1245                            intel_gpu_freq(dev_priv, rps->min_freq));
1246                 seq_printf(m, "Boost freq: %d MHz\n",
1247                            intel_gpu_freq(dev_priv, rps->boost_freq));
1248                 seq_printf(m, "Max freq: %d MHz\n",
1249                            intel_gpu_freq(dev_priv, rps->max_freq));
1250                 seq_printf(m,
1251                            "efficient (RPe) frequency: %d MHz\n",
1252                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1253         } else {
1254                 seq_puts(m, "no P-state info available\n");
1255         }
1256
1257         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1258         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1259         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1260
1261         intel_runtime_pm_put(dev_priv);
1262         return ret;
1263 }
1264
1265 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1266                                struct seq_file *m,
1267                                struct intel_instdone *instdone)
1268 {
1269         int slice;
1270         int subslice;
1271
1272         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1273                    instdone->instdone);
1274
1275         if (INTEL_GEN(dev_priv) <= 3)
1276                 return;
1277
1278         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1279                    instdone->slice_common);
1280
1281         if (INTEL_GEN(dev_priv) <= 6)
1282                 return;
1283
1284         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1285                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1286                            slice, subslice, instdone->sampler[slice][subslice]);
1287
1288         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1289                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1290                            slice, subslice, instdone->row[slice][subslice]);
1291 }
1292
1293 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1294 {
1295         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1296         struct intel_engine_cs *engine;
1297         u64 acthd[I915_NUM_ENGINES];
1298         u32 seqno[I915_NUM_ENGINES];
1299         struct intel_instdone instdone;
1300         enum intel_engine_id id;
1301
1302         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1303                 seq_puts(m, "Wedged\n");
1304         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1305                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1306         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1307                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1308         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1309                 seq_puts(m, "Waiter holding struct mutex\n");
1310         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1311                 seq_puts(m, "struct_mutex blocked for reset\n");
1312
1313         if (!i915_modparams.enable_hangcheck) {
1314                 seq_puts(m, "Hangcheck disabled\n");
1315                 return 0;
1316         }
1317
1318         intel_runtime_pm_get(dev_priv);
1319
1320         for_each_engine(engine, dev_priv, id) {
1321                 acthd[id] = intel_engine_get_active_head(engine);
1322                 seqno[id] = intel_engine_get_seqno(engine);
1323         }
1324
1325         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1326
1327         intel_runtime_pm_put(dev_priv);
1328
1329         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1330                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1331                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1332                                             jiffies));
1333         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1334                 seq_puts(m, "Hangcheck active, work pending\n");
1335         else
1336                 seq_puts(m, "Hangcheck inactive\n");
1337
1338         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1339
1340         for_each_engine(engine, dev_priv, id) {
1341                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1342                 struct rb_node *rb;
1343
1344                 seq_printf(m, "%s:\n", engine->name);
1345                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1346                            engine->hangcheck.seqno, seqno[id],
1347                            intel_engine_last_submit(engine),
1348                            engine->timeline->inflight_seqnos);
1349                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1350                            yesno(intel_engine_has_waiter(engine)),
1351                            yesno(test_bit(engine->id,
1352                                           &dev_priv->gpu_error.missed_irq_rings)),
1353                            yesno(engine->hangcheck.stalled));
1354
1355                 spin_lock_irq(&b->rb_lock);
1356                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1357                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1358
1359                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1360                                    w->tsk->comm, w->tsk->pid, w->seqno);
1361                 }
1362                 spin_unlock_irq(&b->rb_lock);
1363
1364                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1365                            (long long)engine->hangcheck.acthd,
1366                            (long long)acthd[id]);
1367                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1368                            hangcheck_action_to_str(engine->hangcheck.action),
1369                            engine->hangcheck.action,
1370                            jiffies_to_msecs(jiffies -
1371                                             engine->hangcheck.action_timestamp));
1372
1373                 if (engine->id == RCS) {
1374                         seq_puts(m, "\tinstdone read =\n");
1375
1376                         i915_instdone_info(dev_priv, m, &instdone);
1377
1378                         seq_puts(m, "\tinstdone accu =\n");
1379
1380                         i915_instdone_info(dev_priv, m,
1381                                            &engine->hangcheck.instdone);
1382                 }
1383         }
1384
1385         return 0;
1386 }
1387
1388 static int i915_reset_info(struct seq_file *m, void *unused)
1389 {
1390         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1391         struct i915_gpu_error *error = &dev_priv->gpu_error;
1392         struct intel_engine_cs *engine;
1393         enum intel_engine_id id;
1394
1395         seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1396
1397         for_each_engine(engine, dev_priv, id) {
1398                 seq_printf(m, "%s = %u\n", engine->name,
1399                            i915_reset_engine_count(error, engine));
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int ironlake_drpc_info(struct seq_file *m)
1406 {
1407         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1408         u32 rgvmodectl, rstdbyctl;
1409         u16 crstandvid;
1410
1411         rgvmodectl = I915_READ(MEMMODECTL);
1412         rstdbyctl = I915_READ(RSTDBYCTL);
1413         crstandvid = I915_READ16(CRSTANDVID);
1414
1415         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1416         seq_printf(m, "Boost freq: %d\n",
1417                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1418                    MEMMODE_BOOST_FREQ_SHIFT);
1419         seq_printf(m, "HW control enabled: %s\n",
1420                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1421         seq_printf(m, "SW control enabled: %s\n",
1422                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1423         seq_printf(m, "Gated voltage change: %s\n",
1424                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1425         seq_printf(m, "Starting frequency: P%d\n",
1426                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1427         seq_printf(m, "Max P-state: P%d\n",
1428                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1429         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1430         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1431         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1432         seq_printf(m, "Render standby enabled: %s\n",
1433                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1434         seq_puts(m, "Current RS state: ");
1435         switch (rstdbyctl & RSX_STATUS_MASK) {
1436         case RSX_STATUS_ON:
1437                 seq_puts(m, "on\n");
1438                 break;
1439         case RSX_STATUS_RC1:
1440                 seq_puts(m, "RC1\n");
1441                 break;
1442         case RSX_STATUS_RC1E:
1443                 seq_puts(m, "RC1E\n");
1444                 break;
1445         case RSX_STATUS_RS1:
1446                 seq_puts(m, "RS1\n");
1447                 break;
1448         case RSX_STATUS_RS2:
1449                 seq_puts(m, "RS2 (RC6)\n");
1450                 break;
1451         case RSX_STATUS_RS3:
1452                 seq_puts(m, "RC3 (RC6+)\n");
1453                 break;
1454         default:
1455                 seq_puts(m, "unknown\n");
1456                 break;
1457         }
1458
1459         return 0;
1460 }
1461
1462 static int i915_forcewake_domains(struct seq_file *m, void *data)
1463 {
1464         struct drm_i915_private *i915 = node_to_i915(m->private);
1465         struct intel_uncore_forcewake_domain *fw_domain;
1466         unsigned int tmp;
1467
1468         seq_printf(m, "user.bypass_count = %u\n",
1469                    i915->uncore.user_forcewake.count);
1470
1471         for_each_fw_domain(fw_domain, i915, tmp)
1472                 seq_printf(m, "%s.wake_count = %u\n",
1473                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1474                            READ_ONCE(fw_domain->wake_count));
1475
1476         return 0;
1477 }
1478
1479 static void print_rc6_res(struct seq_file *m,
1480                           const char *title,
1481                           const i915_reg_t reg)
1482 {
1483         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1484
1485         seq_printf(m, "%s %u (%llu us)\n",
1486                    title, I915_READ(reg),
1487                    intel_rc6_residency_us(dev_priv, reg));
1488 }
1489
1490 static int vlv_drpc_info(struct seq_file *m)
1491 {
1492         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1493         u32 rcctl1, pw_status;
1494
1495         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1496         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1497
1498         seq_printf(m, "RC6 Enabled: %s\n",
1499                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1500                                         GEN6_RC_CTL_EI_MODE(1))));
1501         seq_printf(m, "Render Power Well: %s\n",
1502                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1503         seq_printf(m, "Media Power Well: %s\n",
1504                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1505
1506         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1507         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1508
1509         return i915_forcewake_domains(m, NULL);
1510 }
1511
1512 static int gen6_drpc_info(struct seq_file *m)
1513 {
1514         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1515         u32 gt_core_status, rcctl1, rc6vids = 0;
1516         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1517         unsigned forcewake_count;
1518         int count = 0;
1519
1520         forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1521         if (forcewake_count) {
1522                 seq_puts(m, "RC information inaccurate because somebody "
1523                             "holds a forcewake reference \n");
1524         } else {
1525                 /* NB: we cannot use forcewake, else we read the wrong values */
1526                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1527                         udelay(10);
1528                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1529         }
1530
1531         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1532         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1533
1534         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535         if (INTEL_GEN(dev_priv) >= 9) {
1536                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1537                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1538         }
1539
1540         mutex_lock(&dev_priv->pcu_lock);
1541         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1542         mutex_unlock(&dev_priv->pcu_lock);
1543
1544         seq_printf(m, "RC1e Enabled: %s\n",
1545                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546         seq_printf(m, "RC6 Enabled: %s\n",
1547                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548         if (INTEL_GEN(dev_priv) >= 9) {
1549                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1550                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1551                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1552                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1553         }
1554         seq_printf(m, "Deep RC6 Enabled: %s\n",
1555                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1556         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1557                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1558         seq_puts(m, "Current RC state: ");
1559         switch (gt_core_status & GEN6_RCn_MASK) {
1560         case GEN6_RC0:
1561                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1562                         seq_puts(m, "Core Power Down\n");
1563                 else
1564                         seq_puts(m, "on\n");
1565                 break;
1566         case GEN6_RC3:
1567                 seq_puts(m, "RC3\n");
1568                 break;
1569         case GEN6_RC6:
1570                 seq_puts(m, "RC6\n");
1571                 break;
1572         case GEN6_RC7:
1573                 seq_puts(m, "RC7\n");
1574                 break;
1575         default:
1576                 seq_puts(m, "Unknown\n");
1577                 break;
1578         }
1579
1580         seq_printf(m, "Core Power Down: %s\n",
1581                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1582         if (INTEL_GEN(dev_priv) >= 9) {
1583                 seq_printf(m, "Render Power Well: %s\n",
1584                         (gen9_powergate_status &
1585                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1586                 seq_printf(m, "Media Power Well: %s\n",
1587                         (gen9_powergate_status &
1588                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1589         }
1590
1591         /* Not exactly sure what this is */
1592         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1593                       GEN6_GT_GFX_RC6_LOCKED);
1594         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1595         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1596         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1597
1598         seq_printf(m, "RC6   voltage: %dmV\n",
1599                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1600         seq_printf(m, "RC6+  voltage: %dmV\n",
1601                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1602         seq_printf(m, "RC6++ voltage: %dmV\n",
1603                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1604         return i915_forcewake_domains(m, NULL);
1605 }
1606
1607 static int i915_drpc_info(struct seq_file *m, void *unused)
1608 {
1609         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1610         int err;
1611
1612         intel_runtime_pm_get(dev_priv);
1613
1614         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1615                 err = vlv_drpc_info(m);
1616         else if (INTEL_GEN(dev_priv) >= 6)
1617                 err = gen6_drpc_info(m);
1618         else
1619                 err = ironlake_drpc_info(m);
1620
1621         intel_runtime_pm_put(dev_priv);
1622
1623         return err;
1624 }
1625
1626 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1627 {
1628         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1629
1630         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1631                    dev_priv->fb_tracking.busy_bits);
1632
1633         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1634                    dev_priv->fb_tracking.flip_bits);
1635
1636         return 0;
1637 }
1638
1639 static int i915_fbc_status(struct seq_file *m, void *unused)
1640 {
1641         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1642
1643         if (!HAS_FBC(dev_priv)) {
1644                 seq_puts(m, "FBC unsupported on this chipset\n");
1645                 return 0;
1646         }
1647
1648         intel_runtime_pm_get(dev_priv);
1649         mutex_lock(&dev_priv->fbc.lock);
1650
1651         if (intel_fbc_is_active(dev_priv))
1652                 seq_puts(m, "FBC enabled\n");
1653         else
1654                 seq_printf(m, "FBC disabled: %s\n",
1655                            dev_priv->fbc.no_fbc_reason);
1656
1657         if (intel_fbc_is_active(dev_priv)) {
1658                 u32 mask;
1659
1660                 if (INTEL_GEN(dev_priv) >= 8)
1661                         mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1662                 else if (INTEL_GEN(dev_priv) >= 7)
1663                         mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1664                 else if (INTEL_GEN(dev_priv) >= 5)
1665                         mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1666                 else if (IS_G4X(dev_priv))
1667                         mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1668                 else
1669                         mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1670                                                         FBC_STAT_COMPRESSED);
1671
1672                 seq_printf(m, "Compressing: %s\n", yesno(mask));
1673         }
1674
1675         mutex_unlock(&dev_priv->fbc.lock);
1676         intel_runtime_pm_put(dev_priv);
1677
1678         return 0;
1679 }
1680
1681 static int i915_fbc_false_color_get(void *data, u64 *val)
1682 {
1683         struct drm_i915_private *dev_priv = data;
1684
1685         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1686                 return -ENODEV;
1687
1688         *val = dev_priv->fbc.false_color;
1689
1690         return 0;
1691 }
1692
1693 static int i915_fbc_false_color_set(void *data, u64 val)
1694 {
1695         struct drm_i915_private *dev_priv = data;
1696         u32 reg;
1697
1698         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1699                 return -ENODEV;
1700
1701         mutex_lock(&dev_priv->fbc.lock);
1702
1703         reg = I915_READ(ILK_DPFC_CONTROL);
1704         dev_priv->fbc.false_color = val;
1705
1706         I915_WRITE(ILK_DPFC_CONTROL, val ?
1707                    (reg | FBC_CTL_FALSE_COLOR) :
1708                    (reg & ~FBC_CTL_FALSE_COLOR));
1709
1710         mutex_unlock(&dev_priv->fbc.lock);
1711         return 0;
1712 }
1713
1714 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1715                         i915_fbc_false_color_get, i915_fbc_false_color_set,
1716                         "%llu\n");
1717
1718 static int i915_ips_status(struct seq_file *m, void *unused)
1719 {
1720         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1721
1722         if (!HAS_IPS(dev_priv)) {
1723                 seq_puts(m, "not supported\n");
1724                 return 0;
1725         }
1726
1727         intel_runtime_pm_get(dev_priv);
1728
1729         seq_printf(m, "Enabled by kernel parameter: %s\n",
1730                    yesno(i915_modparams.enable_ips));
1731
1732         if (INTEL_GEN(dev_priv) >= 8) {
1733                 seq_puts(m, "Currently: unknown\n");
1734         } else {
1735                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736                         seq_puts(m, "Currently: enabled\n");
1737                 else
1738                         seq_puts(m, "Currently: disabled\n");
1739         }
1740
1741         intel_runtime_pm_put(dev_priv);
1742
1743         return 0;
1744 }
1745
1746 static int i915_sr_status(struct seq_file *m, void *unused)
1747 {
1748         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1749         bool sr_enabled = false;
1750
1751         intel_runtime_pm_get(dev_priv);
1752         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1753
1754         if (INTEL_GEN(dev_priv) >= 9)
1755                 /* no global SR status; inspect per-plane WM */;
1756         else if (HAS_PCH_SPLIT(dev_priv))
1757                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1758         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1759                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1760                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761         else if (IS_I915GM(dev_priv))
1762                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763         else if (IS_PINEVIEW(dev_priv))
1764                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1765         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1766                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1767
1768         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1769         intel_runtime_pm_put(dev_priv);
1770
1771         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1772
1773         return 0;
1774 }
1775
1776 static int i915_emon_status(struct seq_file *m, void *unused)
1777 {
1778         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1779         struct drm_device *dev = &dev_priv->drm;
1780         unsigned long temp, chipset, gfx;
1781         int ret;
1782
1783         if (!IS_GEN5(dev_priv))
1784                 return -ENODEV;
1785
1786         ret = mutex_lock_interruptible(&dev->struct_mutex);
1787         if (ret)
1788                 return ret;
1789
1790         temp = i915_mch_val(dev_priv);
1791         chipset = i915_chipset_val(dev_priv);
1792         gfx = i915_gfx_val(dev_priv);
1793         mutex_unlock(&dev->struct_mutex);
1794
1795         seq_printf(m, "GMCH temp: %ld\n", temp);
1796         seq_printf(m, "Chipset power: %ld\n", chipset);
1797         seq_printf(m, "GFX power: %ld\n", gfx);
1798         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1799
1800         return 0;
1801 }
1802
1803 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1804 {
1805         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1806         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1807         int ret = 0;
1808         int gpu_freq, ia_freq;
1809         unsigned int max_gpu_freq, min_gpu_freq;
1810
1811         if (!HAS_LLC(dev_priv)) {
1812                 seq_puts(m, "unsupported on this chipset\n");
1813                 return 0;
1814         }
1815
1816         intel_runtime_pm_get(dev_priv);
1817
1818         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1819         if (ret)
1820                 goto out;
1821
1822         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1823                 /* Convert GT frequency to 50 HZ units */
1824                 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1825                 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1826         } else {
1827                 min_gpu_freq = rps->min_freq_softlimit;
1828                 max_gpu_freq = rps->max_freq_softlimit;
1829         }
1830
1831         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1832
1833         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1834                 ia_freq = gpu_freq;
1835                 sandybridge_pcode_read(dev_priv,
1836                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1837                                        &ia_freq);
1838                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1839                            intel_gpu_freq(dev_priv, (gpu_freq *
1840                                                      (IS_GEN9_BC(dev_priv) ||
1841                                                       IS_CANNONLAKE(dev_priv) ?
1842                                                       GEN9_FREQ_SCALER : 1))),
1843                            ((ia_freq >> 0) & 0xff) * 100,
1844                            ((ia_freq >> 8) & 0xff) * 100);
1845         }
1846
1847         mutex_unlock(&dev_priv->pcu_lock);
1848
1849 out:
1850         intel_runtime_pm_put(dev_priv);
1851         return ret;
1852 }
1853
1854 static int i915_opregion(struct seq_file *m, void *unused)
1855 {
1856         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1857         struct drm_device *dev = &dev_priv->drm;
1858         struct intel_opregion *opregion = &dev_priv->opregion;
1859         int ret;
1860
1861         ret = mutex_lock_interruptible(&dev->struct_mutex);
1862         if (ret)
1863                 goto out;
1864
1865         if (opregion->header)
1866                 seq_write(m, opregion->header, OPREGION_SIZE);
1867
1868         mutex_unlock(&dev->struct_mutex);
1869
1870 out:
1871         return 0;
1872 }
1873
1874 static int i915_vbt(struct seq_file *m, void *unused)
1875 {
1876         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1877
1878         if (opregion->vbt)
1879                 seq_write(m, opregion->vbt, opregion->vbt_size);
1880
1881         return 0;
1882 }
1883
1884 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1885 {
1886         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1887         struct drm_device *dev = &dev_priv->drm;
1888         struct intel_framebuffer *fbdev_fb = NULL;
1889         struct drm_framebuffer *drm_fb;
1890         int ret;
1891
1892         ret = mutex_lock_interruptible(&dev->struct_mutex);
1893         if (ret)
1894                 return ret;
1895
1896 #ifdef CONFIG_DRM_FBDEV_EMULATION
1897         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1898                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1899
1900                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901                            fbdev_fb->base.width,
1902                            fbdev_fb->base.height,
1903                            fbdev_fb->base.format->depth,
1904                            fbdev_fb->base.format->cpp[0] * 8,
1905                            fbdev_fb->base.modifier,
1906                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1907                 describe_obj(m, fbdev_fb->obj);
1908                 seq_putc(m, '\n');
1909         }
1910 #endif
1911
1912         mutex_lock(&dev->mode_config.fb_lock);
1913         drm_for_each_fb(drm_fb, dev) {
1914                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1915                 if (fb == fbdev_fb)
1916                         continue;
1917
1918                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1919                            fb->base.width,
1920                            fb->base.height,
1921                            fb->base.format->depth,
1922                            fb->base.format->cpp[0] * 8,
1923                            fb->base.modifier,
1924                            drm_framebuffer_read_refcount(&fb->base));
1925                 describe_obj(m, fb->obj);
1926                 seq_putc(m, '\n');
1927         }
1928         mutex_unlock(&dev->mode_config.fb_lock);
1929         mutex_unlock(&dev->struct_mutex);
1930
1931         return 0;
1932 }
1933
1934 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1935 {
1936         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1937                    ring->space, ring->head, ring->tail);
1938 }
1939
1940 static int i915_context_status(struct seq_file *m, void *unused)
1941 {
1942         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1943         struct drm_device *dev = &dev_priv->drm;
1944         struct intel_engine_cs *engine;
1945         struct i915_gem_context *ctx;
1946         enum intel_engine_id id;
1947         int ret;
1948
1949         ret = mutex_lock_interruptible(&dev->struct_mutex);
1950         if (ret)
1951                 return ret;
1952
1953         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1954                 seq_printf(m, "HW context %u ", ctx->hw_id);
1955                 if (ctx->pid) {
1956                         struct task_struct *task;
1957
1958                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1959                         if (task) {
1960                                 seq_printf(m, "(%s [%d]) ",
1961                                            task->comm, task->pid);
1962                                 put_task_struct(task);
1963                         }
1964                 } else if (IS_ERR(ctx->file_priv)) {
1965                         seq_puts(m, "(deleted) ");
1966                 } else {
1967                         seq_puts(m, "(kernel) ");
1968                 }
1969
1970                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1971                 seq_putc(m, '\n');
1972
1973                 for_each_engine(engine, dev_priv, id) {
1974                         struct intel_context *ce = &ctx->engine[engine->id];
1975
1976                         seq_printf(m, "%s: ", engine->name);
1977                         if (ce->state)
1978                                 describe_obj(m, ce->state->obj);
1979                         if (ce->ring)
1980                                 describe_ctx_ring(m, ce->ring);
1981                         seq_putc(m, '\n');
1982                 }
1983
1984                 seq_putc(m, '\n');
1985         }
1986
1987         mutex_unlock(&dev->struct_mutex);
1988
1989         return 0;
1990 }
1991
1992 static const char *swizzle_string(unsigned swizzle)
1993 {
1994         switch (swizzle) {
1995         case I915_BIT_6_SWIZZLE_NONE:
1996                 return "none";
1997         case I915_BIT_6_SWIZZLE_9:
1998                 return "bit9";
1999         case I915_BIT_6_SWIZZLE_9_10:
2000                 return "bit9/bit10";
2001         case I915_BIT_6_SWIZZLE_9_11:
2002                 return "bit9/bit11";
2003         case I915_BIT_6_SWIZZLE_9_10_11:
2004                 return "bit9/bit10/bit11";
2005         case I915_BIT_6_SWIZZLE_9_17:
2006                 return "bit9/bit17";
2007         case I915_BIT_6_SWIZZLE_9_10_17:
2008                 return "bit9/bit10/bit17";
2009         case I915_BIT_6_SWIZZLE_UNKNOWN:
2010                 return "unknown";
2011         }
2012
2013         return "bug";
2014 }
2015
2016 static int i915_swizzle_info(struct seq_file *m, void *data)
2017 {
2018         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2019
2020         intel_runtime_pm_get(dev_priv);
2021
2022         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2023                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2024         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2025                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2026
2027         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2028                 seq_printf(m, "DDC = 0x%08x\n",
2029                            I915_READ(DCC));
2030                 seq_printf(m, "DDC2 = 0x%08x\n",
2031                            I915_READ(DCC2));
2032                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2033                            I915_READ16(C0DRB3));
2034                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2035                            I915_READ16(C1DRB3));
2036         } else if (INTEL_GEN(dev_priv) >= 6) {
2037                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2038                            I915_READ(MAD_DIMM_C0));
2039                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2040                            I915_READ(MAD_DIMM_C1));
2041                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2042                            I915_READ(MAD_DIMM_C2));
2043                 seq_printf(m, "TILECTL = 0x%08x\n",
2044                            I915_READ(TILECTL));
2045                 if (INTEL_GEN(dev_priv) >= 8)
2046                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2047                                    I915_READ(GAMTARBMODE));
2048                 else
2049                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2050                                    I915_READ(ARB_MODE));
2051                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2052                            I915_READ(DISP_ARB_CTL));
2053         }
2054
2055         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2056                 seq_puts(m, "L-shaped memory detected\n");
2057
2058         intel_runtime_pm_put(dev_priv);
2059
2060         return 0;
2061 }
2062
2063 static int per_file_ctx(int id, void *ptr, void *data)
2064 {
2065         struct i915_gem_context *ctx = ptr;
2066         struct seq_file *m = data;
2067         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2068
2069         if (!ppgtt) {
2070                 seq_printf(m, "  no ppgtt for context %d\n",
2071                            ctx->user_handle);
2072                 return 0;
2073         }
2074
2075         if (i915_gem_context_is_default(ctx))
2076                 seq_puts(m, "  default context:\n");
2077         else
2078                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2079         ppgtt->debug_dump(ppgtt, m);
2080
2081         return 0;
2082 }
2083
2084 static void gen8_ppgtt_info(struct seq_file *m,
2085                             struct drm_i915_private *dev_priv)
2086 {
2087         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2088         struct intel_engine_cs *engine;
2089         enum intel_engine_id id;
2090         int i;
2091
2092         if (!ppgtt)
2093                 return;
2094
2095         for_each_engine(engine, dev_priv, id) {
2096                 seq_printf(m, "%s\n", engine->name);
2097                 for (i = 0; i < 4; i++) {
2098                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2099                         pdp <<= 32;
2100                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2101                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2102                 }
2103         }
2104 }
2105
2106 static void gen6_ppgtt_info(struct seq_file *m,
2107                             struct drm_i915_private *dev_priv)
2108 {
2109         struct intel_engine_cs *engine;
2110         enum intel_engine_id id;
2111
2112         if (IS_GEN6(dev_priv))
2113                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2114
2115         for_each_engine(engine, dev_priv, id) {
2116                 seq_printf(m, "%s\n", engine->name);
2117                 if (IS_GEN7(dev_priv))
2118                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2119                                    I915_READ(RING_MODE_GEN7(engine)));
2120                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2121                            I915_READ(RING_PP_DIR_BASE(engine)));
2122                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2123                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2124                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2125                            I915_READ(RING_PP_DIR_DCLV(engine)));
2126         }
2127         if (dev_priv->mm.aliasing_ppgtt) {
2128                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2129
2130                 seq_puts(m, "aliasing PPGTT:\n");
2131                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2132
2133                 ppgtt->debug_dump(ppgtt, m);
2134         }
2135
2136         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2137 }
2138
2139 static int i915_ppgtt_info(struct seq_file *m, void *data)
2140 {
2141         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2142         struct drm_device *dev = &dev_priv->drm;
2143         struct drm_file *file;
2144         int ret;
2145
2146         mutex_lock(&dev->filelist_mutex);
2147         ret = mutex_lock_interruptible(&dev->struct_mutex);
2148         if (ret)
2149                 goto out_unlock;
2150
2151         intel_runtime_pm_get(dev_priv);
2152
2153         if (INTEL_GEN(dev_priv) >= 8)
2154                 gen8_ppgtt_info(m, dev_priv);
2155         else if (INTEL_GEN(dev_priv) >= 6)
2156                 gen6_ppgtt_info(m, dev_priv);
2157
2158         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2159                 struct drm_i915_file_private *file_priv = file->driver_priv;
2160                 struct task_struct *task;
2161
2162                 task = get_pid_task(file->pid, PIDTYPE_PID);
2163                 if (!task) {
2164                         ret = -ESRCH;
2165                         goto out_rpm;
2166                 }
2167                 seq_printf(m, "\nproc: %s\n", task->comm);
2168                 put_task_struct(task);
2169                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2170                              (void *)(unsigned long)m);
2171         }
2172
2173 out_rpm:
2174         intel_runtime_pm_put(dev_priv);
2175         mutex_unlock(&dev->struct_mutex);
2176 out_unlock:
2177         mutex_unlock(&dev->filelist_mutex);
2178         return ret;
2179 }
2180
2181 static int count_irq_waiters(struct drm_i915_private *i915)
2182 {
2183         struct intel_engine_cs *engine;
2184         enum intel_engine_id id;
2185         int count = 0;
2186
2187         for_each_engine(engine, i915, id)
2188                 count += intel_engine_has_waiter(engine);
2189
2190         return count;
2191 }
2192
2193 static const char *rps_power_to_str(unsigned int power)
2194 {
2195         static const char * const strings[] = {
2196                 [LOW_POWER] = "low power",
2197                 [BETWEEN] = "mixed",
2198                 [HIGH_POWER] = "high power",
2199         };
2200
2201         if (power >= ARRAY_SIZE(strings) || !strings[power])
2202                 return "unknown";
2203
2204         return strings[power];
2205 }
2206
2207 static int i915_rps_boost_info(struct seq_file *m, void *data)
2208 {
2209         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2210         struct drm_device *dev = &dev_priv->drm;
2211         struct intel_rps *rps = &dev_priv->gt_pm.rps;
2212         struct drm_file *file;
2213
2214         seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2215         seq_printf(m, "GPU busy? %s [%d requests]\n",
2216                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2217         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2218         seq_printf(m, "Boosts outstanding? %d\n",
2219                    atomic_read(&rps->num_waiters));
2220         seq_printf(m, "Frequency requested %d\n",
2221                    intel_gpu_freq(dev_priv, rps->cur_freq));
2222         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2223                    intel_gpu_freq(dev_priv, rps->min_freq),
2224                    intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2225                    intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2226                    intel_gpu_freq(dev_priv, rps->max_freq));
2227         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2228                    intel_gpu_freq(dev_priv, rps->idle_freq),
2229                    intel_gpu_freq(dev_priv, rps->efficient_freq),
2230                    intel_gpu_freq(dev_priv, rps->boost_freq));
2231
2232         mutex_lock(&dev->filelist_mutex);
2233         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2234                 struct drm_i915_file_private *file_priv = file->driver_priv;
2235                 struct task_struct *task;
2236
2237                 rcu_read_lock();
2238                 task = pid_task(file->pid, PIDTYPE_PID);
2239                 seq_printf(m, "%s [%d]: %d boosts\n",
2240                            task ? task->comm : "<unknown>",
2241                            task ? task->pid : -1,
2242                            atomic_read(&file_priv->rps_client.boosts));
2243                 rcu_read_unlock();
2244         }
2245         seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2246                    atomic_read(&rps->boosts));
2247         mutex_unlock(&dev->filelist_mutex);
2248
2249         if (INTEL_GEN(dev_priv) >= 6 &&
2250             rps->enabled &&
2251             dev_priv->gt.active_requests) {
2252                 u32 rpup, rpupei;
2253                 u32 rpdown, rpdownei;
2254
2255                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2256                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2257                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2258                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2259                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2260                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2261
2262                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2263                            rps_power_to_str(rps->power));
2264                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2265                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2266                            rps->up_threshold);
2267                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2268                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2269                            rps->down_threshold);
2270         } else {
2271                 seq_puts(m, "\nRPS Autotuning inactive\n");
2272         }
2273
2274         return 0;
2275 }
2276
2277 static int i915_llc(struct seq_file *m, void *data)
2278 {
2279         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2280         const bool edram = INTEL_GEN(dev_priv) > 8;
2281
2282         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2283         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2284                    intel_uncore_edram_size(dev_priv)/1024/1024);
2285
2286         return 0;
2287 }
2288
2289 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2290 {
2291         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2292         struct drm_printer p;
2293
2294         if (!HAS_HUC_UCODE(dev_priv))
2295                 return 0;
2296
2297         p = drm_seq_file_printer(m);
2298         intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2299
2300         intel_runtime_pm_get(dev_priv);
2301         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2302         intel_runtime_pm_put(dev_priv);
2303
2304         return 0;
2305 }
2306
2307 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2308 {
2309         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2310         struct drm_printer p;
2311         u32 tmp, i;
2312
2313         if (!HAS_GUC_UCODE(dev_priv))
2314                 return 0;
2315
2316         p = drm_seq_file_printer(m);
2317         intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2318
2319         intel_runtime_pm_get(dev_priv);
2320
2321         tmp = I915_READ(GUC_STATUS);
2322
2323         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2324         seq_printf(m, "\tBootrom status = 0x%x\n",
2325                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2326         seq_printf(m, "\tuKernel status = 0x%x\n",
2327                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2328         seq_printf(m, "\tMIA Core status = 0x%x\n",
2329                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2330         seq_puts(m, "\nScratch registers:\n");
2331         for (i = 0; i < 16; i++)
2332                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2333
2334         intel_runtime_pm_put(dev_priv);
2335
2336         return 0;
2337 }
2338
2339 static void i915_guc_log_info(struct seq_file *m,
2340                               struct drm_i915_private *dev_priv)
2341 {
2342         struct intel_guc *guc = &dev_priv->guc;
2343
2344         seq_puts(m, "\nGuC logging stats:\n");
2345
2346         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2347                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2348                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2349
2350         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2351                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2352                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2353
2354         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2355                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2356                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2357
2358         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2359                    guc->log.flush_interrupt_count);
2360
2361         seq_printf(m, "\tCapture miss count: %u\n",
2362                    guc->log.capture_miss_count);
2363 }
2364
2365 static void i915_guc_client_info(struct seq_file *m,
2366                                  struct drm_i915_private *dev_priv,
2367                                  struct intel_guc_client *client)
2368 {
2369         struct intel_engine_cs *engine;
2370         enum intel_engine_id id;
2371         uint64_t tot = 0;
2372
2373         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2374                 client->priority, client->stage_id, client->proc_desc_offset);
2375         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2376                 client->doorbell_id, client->doorbell_offset);
2377
2378         for_each_engine(engine, dev_priv, id) {
2379                 u64 submissions = client->submissions[id];
2380                 tot += submissions;
2381                 seq_printf(m, "\tSubmissions: %llu %s\n",
2382                                 submissions, engine->name);
2383         }
2384         seq_printf(m, "\tTotal: %llu\n", tot);
2385 }
2386
2387 static bool check_guc_submission(struct seq_file *m)
2388 {
2389         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2390         const struct intel_guc *guc = &dev_priv->guc;
2391
2392         if (!guc->execbuf_client) {
2393                 seq_printf(m, "GuC submission %s\n",
2394                            HAS_GUC_SCHED(dev_priv) ?
2395                            "disabled" :
2396                            "not supported");
2397                 return false;
2398         }
2399
2400         return true;
2401 }
2402
2403 static int i915_guc_info(struct seq_file *m, void *data)
2404 {
2405         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2406         const struct intel_guc *guc = &dev_priv->guc;
2407
2408         if (!check_guc_submission(m))
2409                 return 0;
2410
2411         seq_printf(m, "Doorbell map:\n");
2412         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2413         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2414
2415         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2416         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2417         seq_printf(m, "\nGuC preempt client @ %p:\n", guc->preempt_client);
2418         i915_guc_client_info(m, dev_priv, guc->preempt_client);
2419
2420         i915_guc_log_info(m, dev_priv);
2421
2422         /* Add more as required ... */
2423
2424         return 0;
2425 }
2426
2427 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2428 {
2429         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2430         const struct intel_guc *guc = &dev_priv->guc;
2431         struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2432         struct intel_guc_client *client = guc->execbuf_client;
2433         unsigned int tmp;
2434         int index;
2435
2436         if (!check_guc_submission(m))
2437                 return 0;
2438
2439         for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2440                 struct intel_engine_cs *engine;
2441
2442                 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2443                         continue;
2444
2445                 seq_printf(m, "GuC stage descriptor %u:\n", index);
2446                 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2447                 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2448                 seq_printf(m, "\tPriority: %d\n", desc->priority);
2449                 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2450                 seq_printf(m, "\tEngines used: 0x%x\n",
2451                            desc->engines_used);
2452                 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2453                            desc->db_trigger_phy,
2454                            desc->db_trigger_cpu,
2455                            desc->db_trigger_uk);
2456                 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2457                            desc->process_desc);
2458                 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2459                            desc->wq_addr, desc->wq_size);
2460                 seq_putc(m, '\n');
2461
2462                 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2463                         u32 guc_engine_id = engine->guc_id;
2464                         struct guc_execlist_context *lrc =
2465                                                 &desc->lrc[guc_engine_id];
2466
2467                         seq_printf(m, "\t%s LRC:\n", engine->name);
2468                         seq_printf(m, "\t\tContext desc: 0x%x\n",
2469                                    lrc->context_desc);
2470                         seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2471                         seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2472                         seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2473                         seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2474                         seq_putc(m, '\n');
2475                 }
2476         }
2477
2478         return 0;
2479 }
2480
2481 static int i915_guc_log_dump(struct seq_file *m, void *data)
2482 {
2483         struct drm_info_node *node = m->private;
2484         struct drm_i915_private *dev_priv = node_to_i915(node);
2485         bool dump_load_err = !!node->info_ent->data;
2486         struct drm_i915_gem_object *obj = NULL;
2487         u32 *log;
2488         int i = 0;
2489
2490         if (dump_load_err)
2491                 obj = dev_priv->guc.load_err_log;
2492         else if (dev_priv->guc.log.vma)
2493                 obj = dev_priv->guc.log.vma->obj;
2494
2495         if (!obj)
2496                 return 0;
2497
2498         log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2499         if (IS_ERR(log)) {
2500                 DRM_DEBUG("Failed to pin object\n");
2501                 seq_puts(m, "(log data unaccessible)\n");
2502                 return PTR_ERR(log);
2503         }
2504
2505         for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2506                 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2507                            *(log + i), *(log + i + 1),
2508                            *(log + i + 2), *(log + i + 3));
2509
2510         seq_putc(m, '\n');
2511
2512         i915_gem_object_unpin_map(obj);
2513
2514         return 0;
2515 }
2516
2517 static int i915_guc_log_control_get(void *data, u64 *val)
2518 {
2519         struct drm_i915_private *dev_priv = data;
2520
2521         if (!dev_priv->guc.log.vma)
2522                 return -EINVAL;
2523
2524         *val = i915_modparams.guc_log_level;
2525
2526         return 0;
2527 }
2528
2529 static int i915_guc_log_control_set(void *data, u64 val)
2530 {
2531         struct drm_i915_private *dev_priv = data;
2532         int ret;
2533
2534         if (!dev_priv->guc.log.vma)
2535                 return -EINVAL;
2536
2537         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
2538         if (ret)
2539                 return ret;
2540
2541         intel_runtime_pm_get(dev_priv);
2542         ret = i915_guc_log_control(dev_priv, val);
2543         intel_runtime_pm_put(dev_priv);
2544
2545         mutex_unlock(&dev_priv->drm.struct_mutex);
2546         return ret;
2547 }
2548
2549 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2550                         i915_guc_log_control_get, i915_guc_log_control_set,
2551                         "%lld\n");
2552
2553 static const char *psr2_live_status(u32 val)
2554 {
2555         static const char * const live_status[] = {
2556                 "IDLE",
2557                 "CAPTURE",
2558                 "CAPTURE_FS",
2559                 "SLEEP",
2560                 "BUFON_FW",
2561                 "ML_UP",
2562                 "SU_STANDBY",
2563                 "FAST_SLEEP",
2564                 "DEEP_SLEEP",
2565                 "BUF_ON",
2566                 "TG_ON"
2567         };
2568
2569         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2570         if (val < ARRAY_SIZE(live_status))
2571                 return live_status[val];
2572
2573         return "unknown";
2574 }
2575
2576 static int i915_edp_psr_status(struct seq_file *m, void *data)
2577 {
2578         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2579         u32 psrperf = 0;
2580         u32 stat[3];
2581         enum pipe pipe;
2582         bool enabled = false;
2583
2584         if (!HAS_PSR(dev_priv)) {
2585                 seq_puts(m, "PSR not supported\n");
2586                 return 0;
2587         }
2588
2589         intel_runtime_pm_get(dev_priv);
2590
2591         mutex_lock(&dev_priv->psr.lock);
2592         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2593         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2594         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2595         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2596         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2597                    dev_priv->psr.busy_frontbuffer_bits);
2598         seq_printf(m, "Re-enable work scheduled: %s\n",
2599                    yesno(work_busy(&dev_priv->psr.work.work)));
2600
2601         if (HAS_DDI(dev_priv)) {
2602                 if (dev_priv->psr.psr2_support)
2603                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2604                 else
2605                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2606         } else {
2607                 for_each_pipe(dev_priv, pipe) {
2608                         enum transcoder cpu_transcoder =
2609                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2610                         enum intel_display_power_domain power_domain;
2611
2612                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2613                         if (!intel_display_power_get_if_enabled(dev_priv,
2614                                                                 power_domain))
2615                                 continue;
2616
2617                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2618                                 VLV_EDP_PSR_CURR_STATE_MASK;
2619                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2620                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2621                                 enabled = true;
2622
2623                         intel_display_power_put(dev_priv, power_domain);
2624                 }
2625         }
2626
2627         seq_printf(m, "Main link in standby mode: %s\n",
2628                    yesno(dev_priv->psr.link_standby));
2629
2630         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2631
2632         if (!HAS_DDI(dev_priv))
2633                 for_each_pipe(dev_priv, pipe) {
2634                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2635                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2636                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2637                 }
2638         seq_puts(m, "\n");
2639
2640         /*
2641          * VLV/CHV PSR has no kind of performance counter
2642          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2643          */
2644         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2645                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2646                         EDP_PSR_PERF_CNT_MASK;
2647
2648                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2649         }
2650         if (dev_priv->psr.psr2_support) {
2651                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2652
2653                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2654                            psr2, psr2_live_status(psr2));
2655         }
2656         mutex_unlock(&dev_priv->psr.lock);
2657
2658         intel_runtime_pm_put(dev_priv);
2659         return 0;
2660 }
2661
2662 static int i915_sink_crc(struct seq_file *m, void *data)
2663 {
2664         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2665         struct drm_device *dev = &dev_priv->drm;
2666         struct intel_connector *connector;
2667         struct drm_connector_list_iter conn_iter;
2668         struct intel_dp *intel_dp = NULL;
2669         struct drm_modeset_acquire_ctx ctx;
2670         int ret;
2671         u8 crc[6];
2672
2673         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2674
2675         drm_connector_list_iter_begin(dev, &conn_iter);
2676
2677         for_each_intel_connector_iter(connector, &conn_iter) {
2678                 struct drm_crtc *crtc;
2679                 struct drm_connector_state *state;
2680                 struct intel_crtc_state *crtc_state;
2681
2682                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2683                         continue;
2684
2685 retry:
2686                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2687                 if (ret)
2688                         goto err;
2689
2690                 state = connector->base.state;
2691                 if (!state->best_encoder)
2692                         continue;
2693
2694                 crtc = state->crtc;
2695                 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2696                 if (ret)
2697                         goto err;
2698
2699                 crtc_state = to_intel_crtc_state(crtc->state);
2700                 if (!crtc_state->base.active)
2701                         continue;
2702
2703                 /*
2704                  * We need to wait for all crtc updates to complete, to make
2705                  * sure any pending modesets and plane updates are completed.
2706                  */
2707                 if (crtc_state->base.commit) {
2708                         ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
2709
2710                         if (ret)
2711                                 goto err;
2712                 }
2713
2714                 intel_dp = enc_to_intel_dp(state->best_encoder);
2715
2716                 ret = intel_dp_sink_crc(intel_dp, crtc_state, crc);
2717                 if (ret)
2718                         goto err;
2719
2720                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2721                            crc[0], crc[1], crc[2],
2722                            crc[3], crc[4], crc[5]);
2723                 goto out;
2724
2725 err:
2726                 if (ret == -EDEADLK) {
2727                         ret = drm_modeset_backoff(&ctx);
2728                         if (!ret)
2729                                 goto retry;
2730                 }
2731                 goto out;
2732         }
2733         ret = -ENODEV;
2734 out:
2735         drm_connector_list_iter_end(&conn_iter);
2736         drm_modeset_drop_locks(&ctx);
2737         drm_modeset_acquire_fini(&ctx);
2738
2739         return ret;
2740 }
2741
2742 static int i915_energy_uJ(struct seq_file *m, void *data)
2743 {
2744         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2745         unsigned long long power;
2746         u32 units;
2747
2748         if (INTEL_GEN(dev_priv) < 6)
2749                 return -ENODEV;
2750
2751         intel_runtime_pm_get(dev_priv);
2752
2753         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2754                 intel_runtime_pm_put(dev_priv);
2755                 return -ENODEV;
2756         }
2757
2758         units = (power & 0x1f00) >> 8;
2759         power = I915_READ(MCH_SECP_NRG_STTS);
2760         power = (1000000 * power) >> units; /* convert to uJ */
2761
2762         intel_runtime_pm_put(dev_priv);
2763
2764         seq_printf(m, "%llu", power);
2765
2766         return 0;
2767 }
2768
2769 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2770 {
2771         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2772         struct pci_dev *pdev = dev_priv->drm.pdev;
2773
2774         if (!HAS_RUNTIME_PM(dev_priv))
2775                 seq_puts(m, "Runtime power management not supported\n");
2776
2777         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2778         seq_printf(m, "IRQs disabled: %s\n",
2779                    yesno(!intel_irqs_enabled(dev_priv)));
2780 #ifdef CONFIG_PM
2781         seq_printf(m, "Usage count: %d\n",
2782                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2783 #else
2784         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2785 #endif
2786         seq_printf(m, "PCI device power state: %s [%d]\n",
2787                    pci_power_name(pdev->current_state),
2788                    pdev->current_state);
2789
2790         return 0;
2791 }
2792
2793 static int i915_power_domain_info(struct seq_file *m, void *unused)
2794 {
2795         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2796         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2797         int i;
2798
2799         mutex_lock(&power_domains->lock);
2800
2801         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2802         for (i = 0; i < power_domains->power_well_count; i++) {
2803                 struct i915_power_well *power_well;
2804                 enum intel_display_power_domain power_domain;
2805
2806                 power_well = &power_domains->power_wells[i];
2807                 seq_printf(m, "%-25s %d\n", power_well->name,
2808                            power_well->count);
2809
2810                 for_each_power_domain(power_domain, power_well->domains)
2811                         seq_printf(m, "  %-23s %d\n",
2812                                  intel_display_power_domain_str(power_domain),
2813                                  power_domains->domain_use_count[power_domain]);
2814         }
2815
2816         mutex_unlock(&power_domains->lock);
2817
2818         return 0;
2819 }
2820
2821 static int i915_dmc_info(struct seq_file *m, void *unused)
2822 {
2823         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2824         struct intel_csr *csr;
2825
2826         if (!HAS_CSR(dev_priv)) {
2827                 seq_puts(m, "not supported\n");
2828                 return 0;
2829         }
2830
2831         csr = &dev_priv->csr;
2832
2833         intel_runtime_pm_get(dev_priv);
2834
2835         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2836         seq_printf(m, "path: %s\n", csr->fw_path);
2837
2838         if (!csr->dmc_payload)
2839                 goto out;
2840
2841         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2842                    CSR_VERSION_MINOR(csr->version));
2843
2844         if (IS_KABYLAKE(dev_priv) ||
2845             (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2846                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2847                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2848                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2849                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2850         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2851                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2852                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2853         }
2854
2855 out:
2856         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2857         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2858         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2859
2860         intel_runtime_pm_put(dev_priv);
2861
2862         return 0;
2863 }
2864
2865 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2866                                  struct drm_display_mode *mode)
2867 {
2868         int i;
2869
2870         for (i = 0; i < tabs; i++)
2871                 seq_putc(m, '\t');
2872
2873         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2874                    mode->base.id, mode->name,
2875                    mode->vrefresh, mode->clock,
2876                    mode->hdisplay, mode->hsync_start,
2877                    mode->hsync_end, mode->htotal,
2878                    mode->vdisplay, mode->vsync_start,
2879                    mode->vsync_end, mode->vtotal,
2880                    mode->type, mode->flags);
2881 }
2882
2883 static void intel_encoder_info(struct seq_file *m,
2884                                struct intel_crtc *intel_crtc,
2885                                struct intel_encoder *intel_encoder)
2886 {
2887         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2888         struct drm_device *dev = &dev_priv->drm;
2889         struct drm_crtc *crtc = &intel_crtc->base;
2890         struct intel_connector *intel_connector;
2891         struct drm_encoder *encoder;
2892
2893         encoder = &intel_encoder->base;
2894         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2895                    encoder->base.id, encoder->name);
2896         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2897                 struct drm_connector *connector = &intel_connector->base;
2898                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2899                            connector->base.id,
2900                            connector->name,
2901                            drm_get_connector_status_name(connector->status));
2902                 if (connector->status == connector_status_connected) {
2903                         struct drm_display_mode *mode = &crtc->mode;
2904                         seq_printf(m, ", mode:\n");
2905                         intel_seq_print_mode(m, 2, mode);
2906                 } else {
2907                         seq_putc(m, '\n');
2908                 }
2909         }
2910 }
2911
2912 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2913 {
2914         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2915         struct drm_device *dev = &dev_priv->drm;
2916         struct drm_crtc *crtc = &intel_crtc->base;
2917         struct intel_encoder *intel_encoder;
2918         struct drm_plane_state *plane_state = crtc->primary->state;
2919         struct drm_framebuffer *fb = plane_state->fb;
2920
2921         if (fb)
2922                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2923                            fb->base.id, plane_state->src_x >> 16,
2924                            plane_state->src_y >> 16, fb->width, fb->height);
2925         else
2926                 seq_puts(m, "\tprimary plane disabled\n");
2927         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2928                 intel_encoder_info(m, intel_crtc, intel_encoder);
2929 }
2930
2931 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2932 {
2933         struct drm_display_mode *mode = panel->fixed_mode;
2934
2935         seq_printf(m, "\tfixed mode:\n");
2936         intel_seq_print_mode(m, 2, mode);
2937 }
2938
2939 static void intel_dp_info(struct seq_file *m,
2940                           struct intel_connector *intel_connector)
2941 {
2942         struct intel_encoder *intel_encoder = intel_connector->encoder;
2943         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2944
2945         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2946         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2947         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2948                 intel_panel_info(m, &intel_connector->panel);
2949
2950         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2951                                 &intel_dp->aux);
2952 }
2953
2954 static void intel_dp_mst_info(struct seq_file *m,
2955                           struct intel_connector *intel_connector)
2956 {
2957         struct intel_encoder *intel_encoder = intel_connector->encoder;
2958         struct intel_dp_mst_encoder *intel_mst =
2959                 enc_to_mst(&intel_encoder->base);
2960         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2961         struct intel_dp *intel_dp = &intel_dig_port->dp;
2962         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2963                                         intel_connector->port);
2964
2965         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2966 }
2967
2968 static void intel_hdmi_info(struct seq_file *m,
2969                             struct intel_connector *intel_connector)
2970 {
2971         struct intel_encoder *intel_encoder = intel_connector->encoder;
2972         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2973
2974         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2975 }
2976
2977 static void intel_lvds_info(struct seq_file *m,
2978                             struct intel_connector *intel_connector)
2979 {
2980         intel_panel_info(m, &intel_connector->panel);
2981 }
2982
2983 static void intel_connector_info(struct seq_file *m,
2984                                  struct drm_connector *connector)
2985 {
2986         struct intel_connector *intel_connector = to_intel_connector(connector);
2987         struct intel_encoder *intel_encoder = intel_connector->encoder;
2988         struct drm_display_mode *mode;
2989
2990         seq_printf(m, "connector %d: type %s, status: %s\n",
2991                    connector->base.id, connector->name,
2992                    drm_get_connector_status_name(connector->status));
2993         if (connector->status == connector_status_connected) {
2994                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2995                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2996                            connector->display_info.width_mm,
2997                            connector->display_info.height_mm);
2998                 seq_printf(m, "\tsubpixel order: %s\n",
2999                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3000                 seq_printf(m, "\tCEA rev: %d\n",
3001                            connector->display_info.cea_rev);
3002         }
3003
3004         if (!intel_encoder)
3005                 return;
3006
3007         switch (connector->connector_type) {
3008         case DRM_MODE_CONNECTOR_DisplayPort:
3009         case DRM_MODE_CONNECTOR_eDP:
3010                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3011                         intel_dp_mst_info(m, intel_connector);
3012                 else
3013                         intel_dp_info(m, intel_connector);
3014                 break;
3015         case DRM_MODE_CONNECTOR_LVDS:
3016                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3017                         intel_lvds_info(m, intel_connector);
3018                 break;
3019         case DRM_MODE_CONNECTOR_HDMIA:
3020                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3021                     intel_encoder->type == INTEL_OUTPUT_DDI)
3022                         intel_hdmi_info(m, intel_connector);
3023                 break;
3024         default:
3025                 break;
3026         }
3027
3028         seq_printf(m, "\tmodes:\n");
3029         list_for_each_entry(mode, &connector->modes, head)
3030                 intel_seq_print_mode(m, 2, mode);
3031 }
3032
3033 static const char *plane_type(enum drm_plane_type type)
3034 {
3035         switch (type) {
3036         case DRM_PLANE_TYPE_OVERLAY:
3037                 return "OVL";
3038         case DRM_PLANE_TYPE_PRIMARY:
3039                 return "PRI";
3040         case DRM_PLANE_TYPE_CURSOR:
3041                 return "CUR";
3042         /*
3043          * Deliberately omitting default: to generate compiler warnings
3044          * when a new drm_plane_type gets added.
3045          */
3046         }
3047
3048         return "unknown";
3049 }
3050
3051 static const char *plane_rotation(unsigned int rotation)
3052 {
3053         static char buf[48];
3054         /*
3055          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3056          * will print them all to visualize if the values are misused
3057          */
3058         snprintf(buf, sizeof(buf),
3059                  "%s%s%s%s%s%s(0x%08x)",
3060                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3061                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3062                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3063                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3064                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3065                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3066                  rotation);
3067
3068         return buf;
3069 }
3070
3071 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3072 {
3073         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3074         struct drm_device *dev = &dev_priv->drm;
3075         struct intel_plane *intel_plane;
3076
3077         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3078                 struct drm_plane_state *state;
3079                 struct drm_plane *plane = &intel_plane->base;
3080                 struct drm_format_name_buf format_name;
3081
3082                 if (!plane->state) {
3083                         seq_puts(m, "plane->state is NULL!\n");
3084                         continue;
3085                 }
3086
3087                 state = plane->state;
3088
3089                 if (state->fb) {
3090                         drm_get_format_name(state->fb->format->format,
3091                                             &format_name);
3092                 } else {
3093                         sprintf(format_name.str, "N/A");
3094                 }
3095
3096                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3097                            plane->base.id,
3098                            plane_type(intel_plane->base.type),
3099                            state->crtc_x, state->crtc_y,
3100                            state->crtc_w, state->crtc_h,
3101                            (state->src_x >> 16),
3102                            ((state->src_x & 0xffff) * 15625) >> 10,
3103                            (state->src_y >> 16),
3104                            ((state->src_y & 0xffff) * 15625) >> 10,
3105                            (state->src_w >> 16),
3106                            ((state->src_w & 0xffff) * 15625) >> 10,
3107                            (state->src_h >> 16),
3108                            ((state->src_h & 0xffff) * 15625) >> 10,
3109                            format_name.str,
3110                            plane_rotation(state->rotation));
3111         }
3112 }
3113
3114 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3115 {
3116         struct intel_crtc_state *pipe_config;
3117         int num_scalers = intel_crtc->num_scalers;
3118         int i;
3119
3120         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3121
3122         /* Not all platformas have a scaler */
3123         if (num_scalers) {
3124                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3125                            num_scalers,
3126                            pipe_config->scaler_state.scaler_users,
3127                            pipe_config->scaler_state.scaler_id);
3128
3129                 for (i = 0; i < num_scalers; i++) {
3130                         struct intel_scaler *sc =
3131                                         &pipe_config->scaler_state.scalers[i];
3132
3133                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3134                                    i, yesno(sc->in_use), sc->mode);
3135                 }
3136                 seq_puts(m, "\n");
3137         } else {
3138                 seq_puts(m, "\tNo scalers available on this platform\n");
3139         }
3140 }
3141
3142 static int i915_display_info(struct seq_file *m, void *unused)
3143 {
3144         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3145         struct drm_device *dev = &dev_priv->drm;
3146         struct intel_crtc *crtc;
3147         struct drm_connector *connector;
3148         struct drm_connector_list_iter conn_iter;
3149
3150         intel_runtime_pm_get(dev_priv);
3151         seq_printf(m, "CRTC info\n");
3152         seq_printf(m, "---------\n");
3153         for_each_intel_crtc(dev, crtc) {
3154                 struct intel_crtc_state *pipe_config;
3155
3156                 drm_modeset_lock(&crtc->base.mutex, NULL);
3157                 pipe_config = to_intel_crtc_state(crtc->base.state);
3158
3159                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3160                            crtc->base.base.id, pipe_name(crtc->pipe),
3161                            yesno(pipe_config->base.active),
3162                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3163                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3164
3165                 if (pipe_config->base.active) {
3166                         struct intel_plane *cursor =
3167                                 to_intel_plane(crtc->base.cursor);
3168
3169                         intel_crtc_info(m, crtc);
3170
3171                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3172                                    yesno(cursor->base.state->visible),
3173                                    cursor->base.state->crtc_x,
3174                                    cursor->base.state->crtc_y,
3175                                    cursor->base.state->crtc_w,
3176                                    cursor->base.state->crtc_h,
3177                                    cursor->cursor.base);
3178                         intel_scaler_info(m, crtc);
3179                         intel_plane_info(m, crtc);
3180                 }
3181
3182                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3183                            yesno(!crtc->cpu_fifo_underrun_disabled),
3184                            yesno(!crtc->pch_fifo_underrun_disabled));
3185                 drm_modeset_unlock(&crtc->base.mutex);
3186         }
3187
3188         seq_printf(m, "\n");
3189         seq_printf(m, "Connector info\n");
3190         seq_printf(m, "--------------\n");
3191         mutex_lock(&dev->mode_config.mutex);
3192         drm_connector_list_iter_begin(dev, &conn_iter);
3193         drm_for_each_connector_iter(connector, &conn_iter)
3194                 intel_connector_info(m, connector);
3195         drm_connector_list_iter_end(&conn_iter);
3196         mutex_unlock(&dev->mode_config.mutex);
3197
3198         intel_runtime_pm_put(dev_priv);
3199
3200         return 0;
3201 }
3202
3203 static int i915_engine_info(struct seq_file *m, void *unused)
3204 {
3205         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3206         struct intel_engine_cs *engine;
3207         enum intel_engine_id id;
3208         struct drm_printer p;
3209
3210         intel_runtime_pm_get(dev_priv);
3211
3212         seq_printf(m, "GT awake? %s\n",
3213                    yesno(dev_priv->gt.awake));
3214         seq_printf(m, "Global active requests: %d\n",
3215                    dev_priv->gt.active_requests);
3216         seq_printf(m, "CS timestamp frequency: %u kHz\n",
3217                    dev_priv->info.cs_timestamp_frequency_khz);
3218
3219         p = drm_seq_file_printer(m);
3220         for_each_engine(engine, dev_priv, id)
3221                 intel_engine_dump(engine, &p);
3222
3223         intel_runtime_pm_put(dev_priv);
3224
3225         return 0;
3226 }
3227
3228 static int i915_shrinker_info(struct seq_file *m, void *unused)
3229 {
3230         struct drm_i915_private *i915 = node_to_i915(m->private);
3231
3232         seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3233         seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3234
3235         return 0;
3236 }
3237
3238 static int i915_semaphore_status(struct seq_file *m, void *unused)
3239 {
3240         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3241         struct drm_device *dev = &dev_priv->drm;
3242         struct intel_engine_cs *engine;
3243         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3244         enum intel_engine_id id;
3245         int j, ret;
3246
3247         if (!i915_modparams.semaphores) {
3248                 seq_puts(m, "Semaphores are disabled\n");
3249                 return 0;
3250         }
3251
3252         ret = mutex_lock_interruptible(&dev->struct_mutex);
3253         if (ret)
3254                 return ret;
3255         intel_runtime_pm_get(dev_priv);
3256
3257         if (IS_BROADWELL(dev_priv)) {
3258                 struct page *page;
3259                 uint64_t *seqno;
3260
3261                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3262
3263                 seqno = (uint64_t *)kmap_atomic(page);
3264                 for_each_engine(engine, dev_priv, id) {
3265                         uint64_t offset;
3266
3267                         seq_printf(m, "%s\n", engine->name);
3268
3269                         seq_puts(m, "  Last signal:");
3270                         for (j = 0; j < num_rings; j++) {
3271                                 offset = id * I915_NUM_ENGINES + j;
3272                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3273                                            seqno[offset], offset * 8);
3274                         }
3275                         seq_putc(m, '\n');
3276
3277                         seq_puts(m, "  Last wait:  ");
3278                         for (j = 0; j < num_rings; j++) {
3279                                 offset = id + (j * I915_NUM_ENGINES);
3280                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3281                                            seqno[offset], offset * 8);
3282                         }
3283                         seq_putc(m, '\n');
3284
3285                 }
3286                 kunmap_atomic(seqno);
3287         } else {
3288                 seq_puts(m, "  Last signal:");
3289                 for_each_engine(engine, dev_priv, id)
3290                         for (j = 0; j < num_rings; j++)
3291                                 seq_printf(m, "0x%08x\n",
3292                                            I915_READ(engine->semaphore.mbox.signal[j]));
3293                 seq_putc(m, '\n');
3294         }
3295
3296         intel_runtime_pm_put(dev_priv);
3297         mutex_unlock(&dev->struct_mutex);
3298         return 0;
3299 }
3300
3301 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3302 {
3303         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3304         struct drm_device *dev = &dev_priv->drm;
3305         int i;
3306
3307         drm_modeset_lock_all(dev);
3308         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3309                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3310
3311                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3312                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3313                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3314                 seq_printf(m, " tracked hardware state:\n");
3315                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3316                 seq_printf(m, " dpll_md: 0x%08x\n",
3317                            pll->state.hw_state.dpll_md);
3318                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3319                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3320                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3321         }
3322         drm_modeset_unlock_all(dev);
3323
3324         return 0;
3325 }
3326
3327 static int i915_wa_registers(struct seq_file *m, void *unused)
3328 {
3329         int i;
3330         int ret;
3331         struct intel_engine_cs *engine;
3332         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3333         struct drm_device *dev = &dev_priv->drm;
3334         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3335         enum intel_engine_id id;
3336
3337         ret = mutex_lock_interruptible(&dev->struct_mutex);
3338         if (ret)
3339                 return ret;
3340
3341         intel_runtime_pm_get(dev_priv);
3342
3343         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3344         for_each_engine(engine, dev_priv, id)
3345                 seq_printf(m, "HW whitelist count for %s: %d\n",
3346                            engine->name, workarounds->hw_whitelist_count[id]);
3347         for (i = 0; i < workarounds->count; ++i) {
3348                 i915_reg_t addr;
3349                 u32 mask, value, read;
3350                 bool ok;
3351
3352                 addr = workarounds->reg[i].addr;
3353                 mask = workarounds->reg[i].mask;
3354                 value = workarounds->reg[i].value;
3355                 read = I915_READ(addr);
3356                 ok = (value & mask) == (read & mask);
3357                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3358                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3359         }
3360
3361         intel_runtime_pm_put(dev_priv);
3362         mutex_unlock(&dev->struct_mutex);
3363
3364         return 0;
3365 }
3366
3367 static int i915_ipc_status_show(struct seq_file *m, void *data)
3368 {
3369         struct drm_i915_private *dev_priv = m->private;
3370
3371         seq_printf(m, "Isochronous Priority Control: %s\n",
3372                         yesno(dev_priv->ipc_enabled));
3373         return 0;
3374 }
3375
3376 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3377 {
3378         struct drm_i915_private *dev_priv = inode->i_private;
3379
3380         if (!HAS_IPC(dev_priv))
3381                 return -ENODEV;
3382
3383         return single_open(file, i915_ipc_status_show, dev_priv);
3384 }
3385
3386 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3387                                      size_t len, loff_t *offp)
3388 {
3389         struct seq_file *m = file->private_data;
3390         struct drm_i915_private *dev_priv = m->private;
3391         int ret;
3392         bool enable;
3393
3394         ret = kstrtobool_from_user(ubuf, len, &enable);
3395         if (ret < 0)
3396                 return ret;
3397
3398         intel_runtime_pm_get(dev_priv);
3399         if (!dev_priv->ipc_enabled && enable)
3400                 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3401         dev_priv->wm.distrust_bios_wm = true;
3402         dev_priv->ipc_enabled = enable;
3403         intel_enable_ipc(dev_priv);
3404         intel_runtime_pm_put(dev_priv);
3405
3406         return len;
3407 }
3408
3409 static const struct file_operations i915_ipc_status_fops = {
3410         .owner = THIS_MODULE,
3411         .open = i915_ipc_status_open,
3412         .read = seq_read,
3413         .llseek = seq_lseek,
3414         .release = single_release,
3415         .write = i915_ipc_status_write
3416 };
3417
3418 static int i915_ddb_info(struct seq_file *m, void *unused)
3419 {
3420         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3421         struct drm_device *dev = &dev_priv->drm;
3422         struct skl_ddb_allocation *ddb;
3423         struct skl_ddb_entry *entry;
3424         enum pipe pipe;
3425         int plane;
3426
3427         if (INTEL_GEN(dev_priv) < 9)
3428                 return 0;
3429
3430         drm_modeset_lock_all(dev);
3431
3432         ddb = &dev_priv->wm.skl_hw.ddb;
3433
3434         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3435
3436         for_each_pipe(dev_priv, pipe) {
3437                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3438
3439                 for_each_universal_plane(dev_priv, pipe, plane) {
3440                         entry = &ddb->plane[pipe][plane];
3441                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3442                                    entry->start, entry->end,
3443                                    skl_ddb_entry_size(entry));
3444                 }
3445
3446                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3447                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3448                            entry->end, skl_ddb_entry_size(entry));
3449         }
3450
3451         drm_modeset_unlock_all(dev);
3452
3453         return 0;
3454 }
3455
3456 static void drrs_status_per_crtc(struct seq_file *m,
3457                                  struct drm_device *dev,
3458                                  struct intel_crtc *intel_crtc)
3459 {
3460         struct drm_i915_private *dev_priv = to_i915(dev);
3461         struct i915_drrs *drrs = &dev_priv->drrs;
3462         int vrefresh = 0;
3463         struct drm_connector *connector;
3464         struct drm_connector_list_iter conn_iter;
3465
3466         drm_connector_list_iter_begin(dev, &conn_iter);
3467         drm_for_each_connector_iter(connector, &conn_iter) {
3468                 if (connector->state->crtc != &intel_crtc->base)
3469                         continue;
3470
3471                 seq_printf(m, "%s:\n", connector->name);
3472         }
3473         drm_connector_list_iter_end(&conn_iter);
3474
3475         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3476                 seq_puts(m, "\tVBT: DRRS_type: Static");
3477         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3478                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3479         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3480                 seq_puts(m, "\tVBT: DRRS_type: None");
3481         else
3482                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3483
3484         seq_puts(m, "\n\n");
3485
3486         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3487                 struct intel_panel *panel;
3488
3489                 mutex_lock(&drrs->mutex);
3490                 /* DRRS Supported */
3491                 seq_puts(m, "\tDRRS Supported: Yes\n");
3492
3493                 /* disable_drrs() will make drrs->dp NULL */
3494                 if (!drrs->dp) {
3495                         seq_puts(m, "Idleness DRRS: Disabled");
3496                         mutex_unlock(&drrs->mutex);
3497                         return;
3498                 }
3499
3500                 panel = &drrs->dp->attached_connector->panel;
3501                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3502                                         drrs->busy_frontbuffer_bits);
3503
3504                 seq_puts(m, "\n\t\t");
3505                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3506                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3507                         vrefresh = panel->fixed_mode->vrefresh;
3508                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3509                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3510                         vrefresh = panel->downclock_mode->vrefresh;
3511                 } else {
3512                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3513                                                 drrs->refresh_rate_type);
3514                         mutex_unlock(&drrs->mutex);
3515                         return;
3516                 }
3517                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3518
3519                 seq_puts(m, "\n\t\t");
3520                 mutex_unlock(&drrs->mutex);
3521         } else {
3522                 /* DRRS not supported. Print the VBT parameter*/
3523                 seq_puts(m, "\tDRRS Supported : No");
3524         }
3525         seq_puts(m, "\n");
3526 }
3527
3528 static int i915_drrs_status(struct seq_file *m, void *unused)
3529 {
3530         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3531         struct drm_device *dev = &dev_priv->drm;
3532         struct intel_crtc *intel_crtc;
3533         int active_crtc_cnt = 0;
3534
3535         drm_modeset_lock_all(dev);
3536         for_each_intel_crtc(dev, intel_crtc) {
3537                 if (intel_crtc->base.state->active) {
3538                         active_crtc_cnt++;
3539                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3540
3541                         drrs_status_per_crtc(m, dev, intel_crtc);
3542                 }
3543         }
3544         drm_modeset_unlock_all(dev);
3545
3546         if (!active_crtc_cnt)
3547                 seq_puts(m, "No active crtc found\n");
3548
3549         return 0;
3550 }
3551
3552 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3553 {
3554         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3555         struct drm_device *dev = &dev_priv->drm;
3556         struct intel_encoder *intel_encoder;
3557         struct intel_digital_port *intel_dig_port;
3558         struct drm_connector *connector;
3559         struct drm_connector_list_iter conn_iter;
3560
3561         drm_connector_list_iter_begin(dev, &conn_iter);
3562         drm_for_each_connector_iter(connector, &conn_iter) {
3563                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3564                         continue;
3565
3566                 intel_encoder = intel_attached_encoder(connector);
3567                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3568                         continue;
3569
3570                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3571                 if (!intel_dig_port->dp.can_mst)
3572                         continue;
3573
3574                 seq_printf(m, "MST Source Port %c\n",
3575                            port_name(intel_dig_port->base.port));
3576                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3577         }
3578         drm_connector_list_iter_end(&conn_iter);
3579
3580         return 0;
3581 }
3582
3583 static ssize_t i915_displayport_test_active_write(struct file *file,
3584                                                   const char __user *ubuf,
3585                                                   size_t len, loff_t *offp)
3586 {
3587         char *input_buffer;
3588         int status = 0;
3589         struct drm_device *dev;
3590         struct drm_connector *connector;
3591         struct drm_connector_list_iter conn_iter;
3592         struct intel_dp *intel_dp;
3593         int val = 0;
3594
3595         dev = ((struct seq_file *)file->private_data)->private;
3596
3597         if (len == 0)
3598                 return 0;
3599
3600         input_buffer = memdup_user_nul(ubuf, len);
3601         if (IS_ERR(input_buffer))
3602                 return PTR_ERR(input_buffer);
3603
3604         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3605
3606         drm_connector_list_iter_begin(dev, &conn_iter);
3607         drm_for_each_connector_iter(connector, &conn_iter) {
3608                 struct intel_encoder *encoder;
3609
3610                 if (connector->connector_type !=
3611                     DRM_MODE_CONNECTOR_DisplayPort)
3612                         continue;
3613
3614                 encoder = to_intel_encoder(connector->encoder);
3615                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3616                         continue;
3617
3618                 if (encoder && connector->status == connector_status_connected) {
3619                         intel_dp = enc_to_intel_dp(&encoder->base);
3620                         status = kstrtoint(input_buffer, 10, &val);
3621                         if (status < 0)
3622                                 break;
3623                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3624                         /* To prevent erroneous activation of the compliance
3625                          * testing code, only accept an actual value of 1 here
3626                          */
3627                         if (val == 1)
3628                                 intel_dp->compliance.test_active = 1;
3629                         else
3630                                 intel_dp->compliance.test_active = 0;
3631                 }
3632         }
3633         drm_connector_list_iter_end(&conn_iter);
3634         kfree(input_buffer);
3635         if (status < 0)
3636                 return status;
3637
3638         *offp += len;
3639         return len;
3640 }
3641
3642 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3643 {
3644         struct drm_device *dev = m->private;
3645         struct drm_connector *connector;
3646         struct drm_connector_list_iter conn_iter;
3647         struct intel_dp *intel_dp;
3648
3649         drm_connector_list_iter_begin(dev, &conn_iter);
3650         drm_for_each_connector_iter(connector, &conn_iter) {
3651                 struct intel_encoder *encoder;
3652
3653                 if (connector->connector_type !=
3654                     DRM_MODE_CONNECTOR_DisplayPort)
3655                         continue;
3656
3657                 encoder = to_intel_encoder(connector->encoder);
3658                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3659                         continue;
3660
3661                 if (encoder && connector->status == connector_status_connected) {
3662                         intel_dp = enc_to_intel_dp(&encoder->base);
3663                         if (intel_dp->compliance.test_active)
3664                                 seq_puts(m, "1");
3665                         else
3666                                 seq_puts(m, "0");
3667                 } else
3668                         seq_puts(m, "0");
3669         }
3670         drm_connector_list_iter_end(&conn_iter);
3671
3672         return 0;
3673 }
3674
3675 static int i915_displayport_test_active_open(struct inode *inode,
3676                                              struct file *file)
3677 {
3678         struct drm_i915_private *dev_priv = inode->i_private;
3679
3680         return single_open(file, i915_displayport_test_active_show,
3681                            &dev_priv->drm);
3682 }
3683
3684 static const struct file_operations i915_displayport_test_active_fops = {
3685         .owner = THIS_MODULE,
3686         .open = i915_displayport_test_active_open,
3687         .read = seq_read,
3688         .llseek = seq_lseek,
3689         .release = single_release,
3690         .write = i915_displayport_test_active_write
3691 };
3692
3693 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3694 {
3695         struct drm_device *dev = m->private;
3696         struct drm_connector *connector;
3697         struct drm_connector_list_iter conn_iter;
3698         struct intel_dp *intel_dp;
3699
3700         drm_connector_list_iter_begin(dev, &conn_iter);
3701         drm_for_each_connector_iter(connector, &conn_iter) {
3702                 struct intel_encoder *encoder;
3703
3704                 if (connector->connector_type !=
3705                     DRM_MODE_CONNECTOR_DisplayPort)
3706                         continue;
3707
3708                 encoder = to_intel_encoder(connector->encoder);
3709                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3710                         continue;
3711
3712                 if (encoder && connector->status == connector_status_connected) {
3713                         intel_dp = enc_to_intel_dp(&encoder->base);
3714                         if (intel_dp->compliance.test_type ==
3715                             DP_TEST_LINK_EDID_READ)
3716                                 seq_printf(m, "%lx",
3717                                            intel_dp->compliance.test_data.edid);
3718                         else if (intel_dp->compliance.test_type ==
3719                                  DP_TEST_LINK_VIDEO_PATTERN) {
3720                                 seq_printf(m, "hdisplay: %d\n",
3721                                            intel_dp->compliance.test_data.hdisplay);
3722                                 seq_printf(m, "vdisplay: %d\n",
3723                                            intel_dp->compliance.test_data.vdisplay);
3724                                 seq_printf(m, "bpc: %u\n",
3725                                            intel_dp->compliance.test_data.bpc);
3726                         }
3727                 } else
3728                         seq_puts(m, "0");
3729         }
3730         drm_connector_list_iter_end(&conn_iter);
3731
3732         return 0;
3733 }
3734 static int i915_displayport_test_data_open(struct inode *inode,
3735                                            struct file *file)
3736 {
3737         struct drm_i915_private *dev_priv = inode->i_private;
3738
3739         return single_open(file, i915_displayport_test_data_show,
3740                            &dev_priv->drm);
3741 }
3742
3743 static const struct file_operations i915_displayport_test_data_fops = {
3744         .owner = THIS_MODULE,
3745         .open = i915_displayport_test_data_open,
3746         .read = seq_read,
3747         .llseek = seq_lseek,
3748         .release = single_release
3749 };
3750
3751 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3752 {
3753         struct drm_device *dev = m->private;
3754         struct drm_connector *connector;
3755         struct drm_connector_list_iter conn_iter;
3756         struct intel_dp *intel_dp;
3757
3758         drm_connector_list_iter_begin(dev, &conn_iter);
3759         drm_for_each_connector_iter(connector, &conn_iter) {
3760                 struct intel_encoder *encoder;
3761
3762                 if (connector->connector_type !=
3763                     DRM_MODE_CONNECTOR_DisplayPort)
3764                         continue;
3765
3766                 encoder = to_intel_encoder(connector->encoder);
3767                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3768                         continue;
3769
3770                 if (encoder && connector->status == connector_status_connected) {
3771                         intel_dp = enc_to_intel_dp(&encoder->base);
3772                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3773                 } else
3774                         seq_puts(m, "0");
3775         }
3776         drm_connector_list_iter_end(&conn_iter);
3777
3778         return 0;
3779 }
3780
3781 static int i915_displayport_test_type_open(struct inode *inode,
3782                                        struct file *file)
3783 {
3784         struct drm_i915_private *dev_priv = inode->i_private;
3785
3786         return single_open(file, i915_displayport_test_type_show,
3787                            &dev_priv->drm);
3788 }
3789
3790 static const struct file_operations i915_displayport_test_type_fops = {
3791         .owner = THIS_MODULE,
3792         .open = i915_displayport_test_type_open,
3793         .read = seq_read,
3794         .llseek = seq_lseek,
3795         .release = single_release
3796 };
3797
3798 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3799 {
3800         struct drm_i915_private *dev_priv = m->private;
3801         struct drm_device *dev = &dev_priv->drm;
3802         int level;
3803         int num_levels;
3804
3805         if (IS_CHERRYVIEW(dev_priv))
3806                 num_levels = 3;
3807         else if (IS_VALLEYVIEW(dev_priv))
3808                 num_levels = 1;
3809         else if (IS_G4X(dev_priv))
3810                 num_levels = 3;
3811         else
3812                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3813
3814         drm_modeset_lock_all(dev);
3815
3816         for (level = 0; level < num_levels; level++) {
3817                 unsigned int latency = wm[level];
3818
3819                 /*
3820                  * - WM1+ latency values in 0.5us units
3821                  * - latencies are in us on gen9/vlv/chv
3822                  */
3823                 if (INTEL_GEN(dev_priv) >= 9 ||
3824                     IS_VALLEYVIEW(dev_priv) ||
3825                     IS_CHERRYVIEW(dev_priv) ||
3826                     IS_G4X(dev_priv))
3827                         latency *= 10;
3828                 else if (level > 0)
3829                         latency *= 5;
3830
3831                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3832                            level, wm[level], latency / 10, latency % 10);
3833         }
3834
3835         drm_modeset_unlock_all(dev);
3836 }
3837
3838 static int pri_wm_latency_show(struct seq_file *m, void *data)
3839 {
3840         struct drm_i915_private *dev_priv = m->private;
3841         const uint16_t *latencies;
3842
3843         if (INTEL_GEN(dev_priv) >= 9)
3844                 latencies = dev_priv->wm.skl_latency;
3845         else
3846                 latencies = dev_priv->wm.pri_latency;
3847
3848         wm_latency_show(m, latencies);
3849
3850         return 0;
3851 }
3852
3853 static int spr_wm_latency_show(struct seq_file *m, void *data)
3854 {
3855         struct drm_i915_private *dev_priv = m->private;
3856         const uint16_t *latencies;
3857
3858         if (INTEL_GEN(dev_priv) >= 9)
3859                 latencies = dev_priv->wm.skl_latency;
3860         else
3861                 latencies = dev_priv->wm.spr_latency;
3862
3863         wm_latency_show(m, latencies);
3864
3865         return 0;
3866 }
3867
3868 static int cur_wm_latency_show(struct seq_file *m, void *data)
3869 {
3870         struct drm_i915_private *dev_priv = m->private;
3871         const uint16_t *latencies;
3872
3873         if (INTEL_GEN(dev_priv) >= 9)
3874                 latencies = dev_priv->wm.skl_latency;
3875         else
3876                 latencies = dev_priv->wm.cur_latency;
3877
3878         wm_latency_show(m, latencies);
3879
3880         return 0;
3881 }
3882
3883 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3884 {
3885         struct drm_i915_private *dev_priv = inode->i_private;
3886
3887         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3888                 return -ENODEV;
3889
3890         return single_open(file, pri_wm_latency_show, dev_priv);
3891 }
3892
3893 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3894 {
3895         struct drm_i915_private *dev_priv = inode->i_private;
3896
3897         if (HAS_GMCH_DISPLAY(dev_priv))
3898                 return -ENODEV;
3899
3900         return single_open(file, spr_wm_latency_show, dev_priv);
3901 }
3902
3903 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3904 {
3905         struct drm_i915_private *dev_priv = inode->i_private;
3906
3907         if (HAS_GMCH_DISPLAY(dev_priv))
3908                 return -ENODEV;
3909
3910         return single_open(file, cur_wm_latency_show, dev_priv);
3911 }
3912
3913 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3914                                 size_t len, loff_t *offp, uint16_t wm[8])
3915 {
3916         struct seq_file *m = file->private_data;
3917         struct drm_i915_private *dev_priv = m->private;
3918         struct drm_device *dev = &dev_priv->drm;
3919         uint16_t new[8] = { 0 };
3920         int num_levels;
3921         int level;
3922         int ret;
3923         char tmp[32];
3924
3925         if (IS_CHERRYVIEW(dev_priv))
3926                 num_levels = 3;
3927         else if (IS_VALLEYVIEW(dev_priv))
3928                 num_levels = 1;
3929         else if (IS_G4X(dev_priv))
3930                 num_levels = 3;
3931         else
3932                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3933
3934         if (len >= sizeof(tmp))
3935                 return -EINVAL;
3936
3937         if (copy_from_user(tmp, ubuf, len))
3938                 return -EFAULT;
3939
3940         tmp[len] = '\0';
3941
3942         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3943                      &new[0], &new[1], &new[2], &new[3],
3944                      &new[4], &new[5], &new[6], &new[7]);
3945         if (ret != num_levels)
3946                 return -EINVAL;
3947
3948         drm_modeset_lock_all(dev);
3949
3950         for (level = 0; level < num_levels; level++)
3951                 wm[level] = new[level];
3952
3953         drm_modeset_unlock_all(dev);
3954
3955         return len;
3956 }
3957
3958
3959 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3960                                     size_t len, loff_t *offp)
3961 {
3962         struct seq_file *m = file->private_data;
3963         struct drm_i915_private *dev_priv = m->private;
3964         uint16_t *latencies;
3965
3966         if (INTEL_GEN(dev_priv) >= 9)
3967                 latencies = dev_priv->wm.skl_latency;
3968         else
3969                 latencies = dev_priv->wm.pri_latency;
3970
3971         return wm_latency_write(file, ubuf, len, offp, latencies);
3972 }
3973
3974 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3975                                     size_t len, loff_t *offp)
3976 {
3977         struct seq_file *m = file->private_data;
3978         struct drm_i915_private *dev_priv = m->private;
3979         uint16_t *latencies;
3980
3981         if (INTEL_GEN(dev_priv) >= 9)
3982                 latencies = dev_priv->wm.skl_latency;
3983         else
3984                 latencies = dev_priv->wm.spr_latency;
3985
3986         return wm_latency_write(file, ubuf, len, offp, latencies);
3987 }
3988
3989 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3990                                     size_t len, loff_t *offp)
3991 {
3992         struct seq_file *m = file->private_data;
3993         struct drm_i915_private *dev_priv = m->private;
3994         uint16_t *latencies;
3995
3996         if (INTEL_GEN(dev_priv) >= 9)
3997                 latencies = dev_priv->wm.skl_latency;
3998         else
3999                 latencies = dev_priv->wm.cur_latency;
4000
4001         return wm_latency_write(file, ubuf, len, offp, latencies);
4002 }
4003
4004 static const struct file_operations i915_pri_wm_latency_fops = {
4005         .owner = THIS_MODULE,
4006         .open = pri_wm_latency_open,
4007         .read = seq_read,
4008         .llseek = seq_lseek,
4009         .release = single_release,
4010         .write = pri_wm_latency_write
4011 };
4012
4013 static const struct file_operations i915_spr_wm_latency_fops = {
4014         .owner = THIS_MODULE,
4015         .open = spr_wm_latency_open,
4016         .read = seq_read,
4017         .llseek = seq_lseek,
4018         .release = single_release,
4019         .write = spr_wm_latency_write
4020 };
4021
4022 static const struct file_operations i915_cur_wm_latency_fops = {
4023         .owner = THIS_MODULE,
4024         .open = cur_wm_latency_open,
4025         .read = seq_read,
4026         .llseek = seq_lseek,
4027         .release = single_release,
4028         .write = cur_wm_latency_write
4029 };
4030
4031 static int
4032 i915_wedged_get(void *data, u64 *val)
4033 {
4034         struct drm_i915_private *dev_priv = data;
4035
4036         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4037
4038         return 0;
4039 }
4040
4041 static int
4042 i915_wedged_set(void *data, u64 val)
4043 {
4044         struct drm_i915_private *i915 = data;
4045         struct intel_engine_cs *engine;
4046         unsigned int tmp;
4047
4048         /*
4049          * There is no safeguard against this debugfs entry colliding
4050          * with the hangcheck calling same i915_handle_error() in
4051          * parallel, causing an explosion. For now we assume that the
4052          * test harness is responsible enough not to inject gpu hangs
4053          * while it is writing to 'i915_wedged'
4054          */
4055
4056         if (i915_reset_backoff(&i915->gpu_error))
4057                 return -EAGAIN;
4058
4059         for_each_engine_masked(engine, i915, val, tmp) {
4060                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4061                 engine->hangcheck.stalled = true;
4062         }
4063
4064         i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4065
4066         wait_on_bit(&i915->gpu_error.flags,
4067                     I915_RESET_HANDOFF,
4068                     TASK_UNINTERRUPTIBLE);
4069
4070         return 0;
4071 }
4072
4073 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4074                         i915_wedged_get, i915_wedged_set,
4075                         "%llu\n");
4076
4077 static int
4078 fault_irq_set(struct drm_i915_private *i915,
4079               unsigned long *irq,
4080               unsigned long val)
4081 {
4082         int err;
4083
4084         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4085         if (err)
4086                 return err;
4087
4088         err = i915_gem_wait_for_idle(i915,
4089                                      I915_WAIT_LOCKED |
4090                                      I915_WAIT_INTERRUPTIBLE);
4091         if (err)
4092                 goto err_unlock;
4093
4094         *irq = val;
4095         mutex_unlock(&i915->drm.struct_mutex);
4096
4097         /* Flush idle worker to disarm irq */
4098         drain_delayed_work(&i915->gt.idle_work);
4099
4100         return 0;
4101
4102 err_unlock:
4103         mutex_unlock(&i915->drm.struct_mutex);
4104         return err;
4105 }
4106
4107 static int
4108 i915_ring_missed_irq_get(void *data, u64 *val)
4109 {
4110         struct drm_i915_private *dev_priv = data;
4111
4112         *val = dev_priv->gpu_error.missed_irq_rings;
4113         return 0;
4114 }
4115
4116 static int
4117 i915_ring_missed_irq_set(void *data, u64 val)
4118 {
4119         struct drm_i915_private *i915 = data;
4120
4121         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4122 }
4123
4124 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4125                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4126                         "0x%08llx\n");
4127
4128 static int
4129 i915_ring_test_irq_get(void *data, u64 *val)
4130 {
4131         struct drm_i915_private *dev_priv = data;
4132
4133         *val = dev_priv->gpu_error.test_irq_rings;
4134
4135         return 0;
4136 }
4137
4138 static int
4139 i915_ring_test_irq_set(void *data, u64 val)
4140 {
4141         struct drm_i915_private *i915 = data;
4142
4143         val &= INTEL_INFO(i915)->ring_mask;
4144         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4145
4146         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4147 }
4148
4149 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4150                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4151                         "0x%08llx\n");
4152
4153 #define DROP_UNBOUND    BIT(0)
4154 #define DROP_BOUND      BIT(1)
4155 #define DROP_RETIRE     BIT(2)
4156 #define DROP_ACTIVE     BIT(3)
4157 #define DROP_FREED      BIT(4)
4158 #define DROP_SHRINK_ALL BIT(5)
4159 #define DROP_IDLE       BIT(6)
4160 #define DROP_ALL (DROP_UNBOUND  | \
4161                   DROP_BOUND    | \
4162                   DROP_RETIRE   | \
4163                   DROP_ACTIVE   | \
4164                   DROP_FREED    | \
4165                   DROP_SHRINK_ALL |\
4166                   DROP_IDLE)
4167 static int
4168 i915_drop_caches_get(void *data, u64 *val)
4169 {
4170         *val = DROP_ALL;
4171
4172         return 0;
4173 }
4174
4175 static int
4176 i915_drop_caches_set(void *data, u64 val)
4177 {
4178         struct drm_i915_private *dev_priv = data;
4179         struct drm_device *dev = &dev_priv->drm;
4180         int ret = 0;
4181
4182         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4183                   val, val & DROP_ALL);
4184
4185         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4186          * on ioctls on -EAGAIN. */
4187         if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4188                 ret = mutex_lock_interruptible(&dev->struct_mutex);
4189                 if (ret)
4190                         return ret;
4191
4192                 if (val & DROP_ACTIVE)
4193                         ret = i915_gem_wait_for_idle(dev_priv,
4194                                                      I915_WAIT_INTERRUPTIBLE |
4195                                                      I915_WAIT_LOCKED);
4196
4197                 if (val & DROP_RETIRE)
4198                         i915_gem_retire_requests(dev_priv);
4199
4200                 mutex_unlock(&dev->struct_mutex);
4201         }
4202
4203         fs_reclaim_acquire(GFP_KERNEL);
4204         if (val & DROP_BOUND)
4205                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4206
4207         if (val & DROP_UNBOUND)
4208                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4209
4210         if (val & DROP_SHRINK_ALL)
4211                 i915_gem_shrink_all(dev_priv);
4212         fs_reclaim_release(GFP_KERNEL);
4213
4214         if (val & DROP_IDLE)
4215                 drain_delayed_work(&dev_priv->gt.idle_work);
4216
4217         if (val & DROP_FREED) {
4218                 synchronize_rcu();
4219                 i915_gem_drain_freed_objects(dev_priv);
4220         }
4221
4222         return ret;
4223 }
4224
4225 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4226                         i915_drop_caches_get, i915_drop_caches_set,
4227                         "0x%08llx\n");
4228
4229 static int
4230 i915_max_freq_get(void *data, u64 *val)
4231 {
4232         struct drm_i915_private *dev_priv = data;
4233
4234         if (INTEL_GEN(dev_priv) < 6)
4235                 return -ENODEV;
4236
4237         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4238         return 0;
4239 }
4240
4241 static int
4242 i915_max_freq_set(void *data, u64 val)
4243 {
4244         struct drm_i915_private *dev_priv = data;
4245         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4246         u32 hw_max, hw_min;
4247         int ret;
4248
4249         if (INTEL_GEN(dev_priv) < 6)
4250                 return -ENODEV;
4251
4252         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4253
4254         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4255         if (ret)
4256                 return ret;
4257
4258         /*
4259          * Turbo will still be enabled, but won't go above the set value.
4260          */
4261         val = intel_freq_opcode(dev_priv, val);
4262
4263         hw_max = rps->max_freq;
4264         hw_min = rps->min_freq;
4265
4266         if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4267                 mutex_unlock(&dev_priv->pcu_lock);
4268                 return -EINVAL;
4269         }
4270
4271         rps->max_freq_softlimit = val;
4272
4273         if (intel_set_rps(dev_priv, val))
4274                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4275
4276         mutex_unlock(&dev_priv->pcu_lock);
4277
4278         return 0;
4279 }
4280
4281 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4282                         i915_max_freq_get, i915_max_freq_set,
4283                         "%llu\n");
4284
4285 static int
4286 i915_min_freq_get(void *data, u64 *val)
4287 {
4288         struct drm_i915_private *dev_priv = data;
4289
4290         if (INTEL_GEN(dev_priv) < 6)
4291                 return -ENODEV;
4292
4293         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4294         return 0;
4295 }
4296
4297 static int
4298 i915_min_freq_set(void *data, u64 val)
4299 {
4300         struct drm_i915_private *dev_priv = data;
4301         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4302         u32 hw_max, hw_min;
4303         int ret;
4304
4305         if (INTEL_GEN(dev_priv) < 6)
4306                 return -ENODEV;
4307
4308         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4309
4310         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4311         if (ret)
4312                 return ret;
4313
4314         /*
4315          * Turbo will still be enabled, but won't go below the set value.
4316          */
4317         val = intel_freq_opcode(dev_priv, val);
4318
4319         hw_max = rps->max_freq;
4320         hw_min = rps->min_freq;
4321
4322         if (val < hw_min ||
4323             val > hw_max || val > rps->max_freq_softlimit) {
4324                 mutex_unlock(&dev_priv->pcu_lock);
4325                 return -EINVAL;
4326         }
4327
4328         rps->min_freq_softlimit = val;
4329
4330         if (intel_set_rps(dev_priv, val))
4331                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4332
4333         mutex_unlock(&dev_priv->pcu_lock);
4334
4335         return 0;
4336 }
4337
4338 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4339                         i915_min_freq_get, i915_min_freq_set,
4340                         "%llu\n");
4341
4342 static int
4343 i915_cache_sharing_get(void *data, u64 *val)
4344 {
4345         struct drm_i915_private *dev_priv = data;
4346         u32 snpcr;
4347
4348         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4349                 return -ENODEV;
4350
4351         intel_runtime_pm_get(dev_priv);
4352
4353         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4354
4355         intel_runtime_pm_put(dev_priv);
4356
4357         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4358
4359         return 0;
4360 }
4361
4362 static int
4363 i915_cache_sharing_set(void *data, u64 val)
4364 {
4365         struct drm_i915_private *dev_priv = data;
4366         u32 snpcr;
4367
4368         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4369                 return -ENODEV;
4370
4371         if (val > 3)
4372                 return -EINVAL;
4373
4374         intel_runtime_pm_get(dev_priv);
4375         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4376
4377         /* Update the cache sharing policy here as well */
4378         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4379         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4380         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4381         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4382
4383         intel_runtime_pm_put(dev_priv);
4384         return 0;
4385 }
4386
4387 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4388                         i915_cache_sharing_get, i915_cache_sharing_set,
4389                         "%llu\n");
4390
4391 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4392                                           struct sseu_dev_info *sseu)
4393 {
4394         int ss_max = 2;
4395         int ss;
4396         u32 sig1[ss_max], sig2[ss_max];
4397
4398         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4399         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4400         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4401         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4402
4403         for (ss = 0; ss < ss_max; ss++) {
4404                 unsigned int eu_cnt;
4405
4406                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4407                         /* skip disabled subslice */
4408                         continue;
4409
4410                 sseu->slice_mask = BIT(0);
4411                 sseu->subslice_mask |= BIT(ss);
4412                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4413                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4414                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4415                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4416                 sseu->eu_total += eu_cnt;
4417                 sseu->eu_per_subslice = max_t(unsigned int,
4418                                               sseu->eu_per_subslice, eu_cnt);
4419         }
4420 }
4421
4422 static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
4423                                      struct sseu_dev_info *sseu)
4424 {
4425         const struct intel_device_info *info = INTEL_INFO(dev_priv);
4426         int s_max = 6, ss_max = 4;
4427         int s, ss;
4428         u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
4429
4430         for (s = 0; s < s_max; s++) {
4431                 /*
4432                  * FIXME: Valid SS Mask respects the spec and read
4433                  * only valid bits for those registers, excluding reserverd
4434                  * although this seems wrong because it would leave many
4435                  * subslices without ACK.
4436                  */
4437                 s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
4438                         GEN10_PGCTL_VALID_SS_MASK(s);
4439                 eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
4440                 eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
4441         }
4442
4443         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4444                      GEN9_PGCTL_SSA_EU19_ACK |
4445                      GEN9_PGCTL_SSA_EU210_ACK |
4446                      GEN9_PGCTL_SSA_EU311_ACK;
4447         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4448                      GEN9_PGCTL_SSB_EU19_ACK |
4449                      GEN9_PGCTL_SSB_EU210_ACK |
4450                      GEN9_PGCTL_SSB_EU311_ACK;
4451
4452         for (s = 0; s < s_max; s++) {
4453                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4454                         /* skip disabled slice */
4455                         continue;
4456
4457                 sseu->slice_mask |= BIT(s);
4458                 sseu->subslice_mask = info->sseu.subslice_mask;
4459
4460                 for (ss = 0; ss < ss_max; ss++) {
4461                         unsigned int eu_cnt;
4462
4463                         if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4464                                 /* skip disabled subslice */
4465                                 continue;
4466
4467                         eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
4468                                                eu_mask[ss % 2]);
4469                         sseu->eu_total += eu_cnt;
4470                         sseu->eu_per_subslice = max_t(unsigned int,
4471                                                       sseu->eu_per_subslice,
4472                                                       eu_cnt);
4473                 }
4474         }
4475 }
4476
4477 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4478                                     struct sseu_dev_info *sseu)
4479 {
4480         int s_max = 3, ss_max = 4;
4481         int s, ss;
4482         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4483
4484         /* BXT has a single slice and at most 3 subslices. */
4485         if (IS_GEN9_LP(dev_priv)) {
4486                 s_max = 1;
4487                 ss_max = 3;
4488         }
4489
4490         for (s = 0; s < s_max; s++) {
4491                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4492                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4493                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4494         }
4495
4496         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4497                      GEN9_PGCTL_SSA_EU19_ACK |
4498                      GEN9_PGCTL_SSA_EU210_ACK |
4499                      GEN9_PGCTL_SSA_EU311_ACK;
4500         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4501                      GEN9_PGCTL_SSB_EU19_ACK |
4502                      GEN9_PGCTL_SSB_EU210_ACK |
4503                      GEN9_PGCTL_SSB_EU311_ACK;
4504
4505         for (s = 0; s < s_max; s++) {
4506                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4507                         /* skip disabled slice */
4508                         continue;
4509
4510                 sseu->slice_mask |= BIT(s);
4511
4512                 if (IS_GEN9_BC(dev_priv))
4513                         sseu->subslice_mask =
4514                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4515
4516                 for (ss = 0; ss < ss_max; ss++) {
4517                         unsigned int eu_cnt;
4518
4519                         if (IS_GEN9_LP(dev_priv)) {
4520                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4521                                         /* skip disabled subslice */
4522                                         continue;
4523
4524                                 sseu->subslice_mask |= BIT(ss);
4525                         }
4526
4527                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4528                                                eu_mask[ss%2]);
4529                         sseu->eu_total += eu_cnt;
4530                         sseu->eu_per_subslice = max_t(unsigned int,
4531                                                       sseu->eu_per_subslice,
4532                                                       eu_cnt);
4533                 }
4534         }
4535 }
4536
4537 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4538                                          struct sseu_dev_info *sseu)
4539 {
4540         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4541         int s;
4542
4543         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4544
4545         if (sseu->slice_mask) {
4546                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4547                 sseu->eu_per_subslice =
4548                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4549                 sseu->eu_total = sseu->eu_per_subslice *
4550                                  sseu_subslice_total(sseu);
4551
4552                 /* subtract fused off EU(s) from enabled slice(s) */
4553                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4554                         u8 subslice_7eu =
4555                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4556
4557                         sseu->eu_total -= hweight8(subslice_7eu);
4558                 }
4559         }
4560 }
4561
4562 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4563                                  const struct sseu_dev_info *sseu)
4564 {
4565         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4566         const char *type = is_available_info ? "Available" : "Enabled";
4567
4568         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4569                    sseu->slice_mask);
4570         seq_printf(m, "  %s Slice Total: %u\n", type,
4571                    hweight8(sseu->slice_mask));
4572         seq_printf(m, "  %s Subslice Total: %u\n", type,
4573                    sseu_subslice_total(sseu));
4574         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4575                    sseu->subslice_mask);
4576         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4577                    hweight8(sseu->subslice_mask));
4578         seq_printf(m, "  %s EU Total: %u\n", type,
4579                    sseu->eu_total);
4580         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4581                    sseu->eu_per_subslice);
4582
4583         if (!is_available_info)
4584                 return;
4585
4586         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4587         if (HAS_POOLED_EU(dev_priv))
4588                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4589
4590         seq_printf(m, "  Has Slice Power Gating: %s\n",
4591                    yesno(sseu->has_slice_pg));
4592         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4593                    yesno(sseu->has_subslice_pg));
4594         seq_printf(m, "  Has EU Power Gating: %s\n",
4595                    yesno(sseu->has_eu_pg));
4596 }
4597
4598 static int i915_sseu_status(struct seq_file *m, void *unused)
4599 {
4600         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4601         struct sseu_dev_info sseu;
4602
4603         if (INTEL_GEN(dev_priv) < 8)
4604                 return -ENODEV;
4605
4606         seq_puts(m, "SSEU Device Info\n");
4607         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4608
4609         seq_puts(m, "SSEU Device Status\n");
4610         memset(&sseu, 0, sizeof(sseu));
4611
4612         intel_runtime_pm_get(dev_priv);
4613
4614         if (IS_CHERRYVIEW(dev_priv)) {
4615                 cherryview_sseu_device_status(dev_priv, &sseu);
4616         } else if (IS_BROADWELL(dev_priv)) {
4617                 broadwell_sseu_device_status(dev_priv, &sseu);
4618         } else if (IS_GEN9(dev_priv)) {
4619                 gen9_sseu_device_status(dev_priv, &sseu);
4620         } else if (INTEL_GEN(dev_priv) >= 10) {
4621                 gen10_sseu_device_status(dev_priv, &sseu);
4622         }
4623
4624         intel_runtime_pm_put(dev_priv);
4625
4626         i915_print_sseu_info(m, false, &sseu);
4627
4628         return 0;
4629 }
4630
4631 static int i915_forcewake_open(struct inode *inode, struct file *file)
4632 {
4633         struct drm_i915_private *i915 = inode->i_private;
4634
4635         if (INTEL_GEN(i915) < 6)
4636                 return 0;
4637
4638         intel_runtime_pm_get(i915);
4639         intel_uncore_forcewake_user_get(i915);
4640
4641         return 0;
4642 }
4643
4644 static int i915_forcewake_release(struct inode *inode, struct file *file)
4645 {
4646         struct drm_i915_private *i915 = inode->i_private;
4647
4648         if (INTEL_GEN(i915) < 6)
4649                 return 0;
4650
4651         intel_uncore_forcewake_user_put(i915);
4652         intel_runtime_pm_put(i915);
4653
4654         return 0;
4655 }
4656
4657 static const struct file_operations i915_forcewake_fops = {
4658         .owner = THIS_MODULE,
4659         .open = i915_forcewake_open,
4660         .release = i915_forcewake_release,
4661 };
4662
4663 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4664 {
4665         struct drm_i915_private *dev_priv = m->private;
4666         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4667
4668         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4669         seq_printf(m, "Detected: %s\n",
4670                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4671
4672         return 0;
4673 }
4674
4675 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4676                                         const char __user *ubuf, size_t len,
4677                                         loff_t *offp)
4678 {
4679         struct seq_file *m = file->private_data;
4680         struct drm_i915_private *dev_priv = m->private;
4681         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4682         unsigned int new_threshold;
4683         int i;
4684         char *newline;
4685         char tmp[16];
4686
4687         if (len >= sizeof(tmp))
4688                 return -EINVAL;
4689
4690         if (copy_from_user(tmp, ubuf, len))
4691                 return -EFAULT;
4692
4693         tmp[len] = '\0';
4694
4695         /* Strip newline, if any */
4696         newline = strchr(tmp, '\n');
4697         if (newline)
4698                 *newline = '\0';
4699
4700         if (strcmp(tmp, "reset") == 0)
4701                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4702         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4703                 return -EINVAL;
4704
4705         if (new_threshold > 0)
4706                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4707                               new_threshold);
4708         else
4709                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4710
4711         spin_lock_irq(&dev_priv->irq_lock);
4712         hotplug->hpd_storm_threshold = new_threshold;
4713         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4714         for_each_hpd_pin(i)
4715                 hotplug->stats[i].count = 0;
4716         spin_unlock_irq(&dev_priv->irq_lock);
4717
4718         /* Re-enable hpd immediately if we were in an irq storm */
4719         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4720
4721         return len;
4722 }
4723
4724 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4725 {
4726         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4727 }
4728
4729 static const struct file_operations i915_hpd_storm_ctl_fops = {
4730         .owner = THIS_MODULE,
4731         .open = i915_hpd_storm_ctl_open,
4732         .read = seq_read,
4733         .llseek = seq_lseek,
4734         .release = single_release,
4735         .write = i915_hpd_storm_ctl_write
4736 };
4737
4738 static const struct drm_info_list i915_debugfs_list[] = {
4739         {"i915_capabilities", i915_capabilities, 0},
4740         {"i915_gem_objects", i915_gem_object_info, 0},
4741         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4742         {"i915_gem_stolen", i915_gem_stolen_list_info },
4743         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4744         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4745         {"i915_gem_interrupt", i915_interrupt_info, 0},
4746         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4747         {"i915_guc_info", i915_guc_info, 0},
4748         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4749         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4750         {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4751         {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4752         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4753         {"i915_frequency_info", i915_frequency_info, 0},
4754         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4755         {"i915_reset_info", i915_reset_info, 0},
4756         {"i915_drpc_info", i915_drpc_info, 0},
4757         {"i915_emon_status", i915_emon_status, 0},
4758         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4759         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4760         {"i915_fbc_status", i915_fbc_status, 0},
4761         {"i915_ips_status", i915_ips_status, 0},
4762         {"i915_sr_status", i915_sr_status, 0},
4763         {"i915_opregion", i915_opregion, 0},
4764         {"i915_vbt", i915_vbt, 0},
4765         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4766         {"i915_context_status", i915_context_status, 0},
4767         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4768         {"i915_swizzle_info", i915_swizzle_info, 0},
4769         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4770         {"i915_llc", i915_llc, 0},
4771         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4772         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4773         {"i915_energy_uJ", i915_energy_uJ, 0},
4774         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4775         {"i915_power_domain_info", i915_power_domain_info, 0},
4776         {"i915_dmc_info", i915_dmc_info, 0},
4777         {"i915_display_info", i915_display_info, 0},
4778         {"i915_engine_info", i915_engine_info, 0},
4779         {"i915_shrinker_info", i915_shrinker_info, 0},
4780         {"i915_semaphore_status", i915_semaphore_status, 0},
4781         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4782         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4783         {"i915_wa_registers", i915_wa_registers, 0},
4784         {"i915_ddb_info", i915_ddb_info, 0},
4785         {"i915_sseu_status", i915_sseu_status, 0},
4786         {"i915_drrs_status", i915_drrs_status, 0},
4787         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4788 };
4789 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4790
4791 static const struct i915_debugfs_files {
4792         const char *name;
4793         const struct file_operations *fops;
4794 } i915_debugfs_files[] = {
4795         {"i915_wedged", &i915_wedged_fops},
4796         {"i915_max_freq", &i915_max_freq_fops},
4797         {"i915_min_freq", &i915_min_freq_fops},
4798         {"i915_cache_sharing", &i915_cache_sharing_fops},
4799         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4800         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4801         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4802 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4803         {"i915_error_state", &i915_error_state_fops},
4804         {"i915_gpu_info", &i915_gpu_info_fops},
4805 #endif
4806         {"i915_next_seqno", &i915_next_seqno_fops},
4807         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4808         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4809         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4810         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4811         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4812         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4813         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4814         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4815         {"i915_guc_log_control", &i915_guc_log_control_fops},
4816         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4817         {"i915_ipc_status", &i915_ipc_status_fops}
4818 };
4819
4820 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4821 {
4822         struct drm_minor *minor = dev_priv->drm.primary;
4823         struct dentry *ent;
4824         int ret, i;
4825
4826         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4827                                   minor->debugfs_root, to_i915(minor->dev),
4828                                   &i915_forcewake_fops);
4829         if (!ent)
4830                 return -ENOMEM;
4831
4832         ret = intel_pipe_crc_create(minor);
4833         if (ret)
4834                 return ret;
4835
4836         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4837                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4838                                           S_IRUGO | S_IWUSR,
4839                                           minor->debugfs_root,
4840                                           to_i915(minor->dev),
4841                                           i915_debugfs_files[i].fops);
4842                 if (!ent)
4843                         return -ENOMEM;
4844         }
4845
4846         return drm_debugfs_create_files(i915_debugfs_list,
4847                                         I915_DEBUGFS_ENTRIES,
4848                                         minor->debugfs_root, minor);
4849 }
4850
4851 struct dpcd_block {
4852         /* DPCD dump start address. */
4853         unsigned int offset;
4854         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4855         unsigned int end;
4856         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4857         size_t size;
4858         /* Only valid for eDP. */
4859         bool edp;
4860 };
4861
4862 static const struct dpcd_block i915_dpcd_debug[] = {
4863         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4864         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4865         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4866         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4867         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4868         { .offset = DP_SET_POWER },
4869         { .offset = DP_EDP_DPCD_REV },
4870         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4871         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4872         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4873 };
4874
4875 static int i915_dpcd_show(struct seq_file *m, void *data)
4876 {
4877         struct drm_connector *connector = m->private;
4878         struct intel_dp *intel_dp =
4879                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4880         uint8_t buf[16];
4881         ssize_t err;
4882         int i;
4883
4884         if (connector->status != connector_status_connected)
4885                 return -ENODEV;
4886
4887         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4888                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4889                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4890
4891                 if (b->edp &&
4892                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4893                         continue;
4894
4895                 /* low tech for now */
4896                 if (WARN_ON(size > sizeof(buf)))
4897                         continue;
4898
4899                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4900                 if (err <= 0) {
4901                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4902                                   size, b->offset, err);
4903                         continue;
4904                 }
4905
4906                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4907         }
4908
4909         return 0;
4910 }
4911
4912 static int i915_dpcd_open(struct inode *inode, struct file *file)
4913 {
4914         return single_open(file, i915_dpcd_show, inode->i_private);
4915 }
4916
4917 static const struct file_operations i915_dpcd_fops = {
4918         .owner = THIS_MODULE,
4919         .open = i915_dpcd_open,
4920         .read = seq_read,
4921         .llseek = seq_lseek,
4922         .release = single_release,
4923 };
4924
4925 static int i915_panel_show(struct seq_file *m, void *data)
4926 {
4927         struct drm_connector *connector = m->private;
4928         struct intel_dp *intel_dp =
4929                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4930
4931         if (connector->status != connector_status_connected)
4932                 return -ENODEV;
4933
4934         seq_printf(m, "Panel power up delay: %d\n",
4935                    intel_dp->panel_power_up_delay);
4936         seq_printf(m, "Panel power down delay: %d\n",
4937                    intel_dp->panel_power_down_delay);
4938         seq_printf(m, "Backlight on delay: %d\n",
4939                    intel_dp->backlight_on_delay);
4940         seq_printf(m, "Backlight off delay: %d\n",
4941                    intel_dp->backlight_off_delay);
4942
4943         return 0;
4944 }
4945
4946 static int i915_panel_open(struct inode *inode, struct file *file)
4947 {
4948         return single_open(file, i915_panel_show, inode->i_private);
4949 }
4950
4951 static const struct file_operations i915_panel_fops = {
4952         .owner = THIS_MODULE,
4953         .open = i915_panel_open,
4954         .read = seq_read,
4955         .llseek = seq_lseek,
4956         .release = single_release,
4957 };
4958
4959 /**
4960  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4961  * @connector: pointer to a registered drm_connector
4962  *
4963  * Cleanup will be done by drm_connector_unregister() through a call to
4964  * drm_debugfs_connector_remove().
4965  *
4966  * Returns 0 on success, negative error codes on error.
4967  */
4968 int i915_debugfs_connector_add(struct drm_connector *connector)
4969 {
4970         struct dentry *root = connector->debugfs_entry;
4971
4972         /* The connector must have been registered beforehands. */
4973         if (!root)
4974                 return -ENODEV;
4975
4976         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4977             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4978                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4979                                     connector, &i915_dpcd_fops);
4980
4981         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4982                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4983                                     connector, &i915_panel_fops);
4984
4985         return 0;
4986 }