drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 121                 if (i915_is_ggtt(vma->vm) &&
 122                     drm_mm_node_allocated(&vma->node))
 123                         size += vma->node.size;
 124         }
 125
 126         return size;
 127 }
 128
 129 static void
 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 133         struct intel_engine_cs *ring;
 134         struct i915_vma *vma;
 135         int pin_count = 0;
 136         int i;
 137
 138         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 139                    &obj->base,
 140                    obj->active ? "*" : " ",
 141                    get_pin_flag(obj),
 142                    get_tiling_flag(obj),
 143                    get_global_flag(obj),
 144                    obj->base.size / 1024,
 145                    obj->base.read_domains,
 146                    obj->base.write_domain);
 147         for_each_ring(ring, dev_priv, i)
 148                 seq_printf(m, "%x ",
 149                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 150         seq_printf(m, "] %x %x%s%s%s",
 151                    i915_gem_request_get_seqno(obj->last_write_req),
 152                    i915_gem_request_get_seqno(obj->last_fenced_req),
 153                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 154                    obj->dirty ? " dirty" : "",
 155                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 156         if (obj->base.name)
 157                 seq_printf(m, " (name: %d)", obj->base.name);
 158         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 159                 if (vma->pin_count > 0)
 160                         pin_count++;
 161         }
 162         seq_printf(m, " (pinned x %d)", pin_count);
 163         if (obj->pin_display)
 164                 seq_printf(m, " (display)");
 165         if (obj->fence_reg != I915_FENCE_REG_NONE)
 166                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 167         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_is_ggtt(vma->vm))
 172                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 173                 else
 174                         seq_puts(m, ")");
 175         }
 176         if (obj->stolen)
 177                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 178         if (obj->pin_display || obj->fault_mappable) {
 179                 char s[3], *t = s;
 180                 if (obj->pin_display)
 181                         *t++ = 'p';
 182                 if (obj->fault_mappable)
 183                         *t++ = 'f';
 184                 *t = '\0';
 185                 seq_printf(m, " (%s mappable)", s);
 186         }
 187         if (obj->last_write_req != NULL)
 188                 seq_printf(m, " (%s)",
 189                            i915_gem_request_get_ring(obj->last_write_req)->name);
 190         if (obj->frontbuffer_bits)
 191                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 192 }
 193
 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 195 {
 196         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 197         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 198         seq_putc(m, ' ');
 199 }
 200
 201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 202 {
 203         struct drm_info_node *node = m->private;
 204         uintptr_t list = (uintptr_t) node->info_ent->data;
 205         struct list_head *head;
 206         struct drm_device *dev = node->minor->dev;
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         struct i915_address_space *vm = &dev_priv->gtt.base;
 209         struct i915_vma *vma;
 210         u64 total_obj_size, total_gtt_size;
 211         int count, ret;
 212
 213         ret = mutex_lock_interruptible(&dev->struct_mutex);
 214         if (ret)
 215                 return ret;
 216
 217         /* FIXME: the user of this interface might want more than just GGTT */
 218         switch (list) {
 219         case ACTIVE_LIST:
 220                 seq_puts(m, "Active:\n");
 221                 head = &vm->active_list;
 222                 break;
 223         case INACTIVE_LIST:
 224                 seq_puts(m, "Inactive:\n");
 225                 head = &vm->inactive_list;
 226                 break;
 227         default:
 228                 mutex_unlock(&dev->struct_mutex);
 229                 return -EINVAL;
 230         }
 231
 232         total_obj_size = total_gtt_size = count = 0;
 233         list_for_each_entry(vma, head, mm_list) {
 234                 seq_printf(m, "   ");
 235                 describe_obj(m, vma->obj);
 236                 seq_printf(m, "\n");
 237                 total_obj_size += vma->obj->base.size;
 238                 total_gtt_size += vma->node.size;
 239                 count++;
 240         }
 241         mutex_unlock(&dev->struct_mutex);
 242
 243         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 244                    count, total_obj_size, total_gtt_size);
 245         return 0;
 246 }
 247
 248 static int obj_rank_by_stolen(void *priv,
 249                               struct list_head *A, struct list_head *B)
 250 {
 251         struct drm_i915_gem_object *a =
 252                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 253         struct drm_i915_gem_object *b =
 254                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 255
 256         return a->stolen->start - b->stolen->start;
 257 }
 258
 259 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 260 {
 261         struct drm_info_node *node = m->private;
 262         struct drm_device *dev = node->minor->dev;
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         struct drm_i915_gem_object *obj;
 265         u64 total_obj_size, total_gtt_size;
 266         LIST_HEAD(stolen);
 267         int count, ret;
 268
 269         ret = mutex_lock_interruptible(&dev->struct_mutex);
 270         if (ret)
 271                 return ret;
 272
 273         total_obj_size = total_gtt_size = count = 0;
 274         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 275                 if (obj->stolen == NULL)
 276                         continue;
 277
 278                 list_add(&obj->obj_exec_link, &stolen);
 279
 280                 total_obj_size += obj->base.size;
 281                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 282                 count++;
 283         }
 284         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 285                 if (obj->stolen == NULL)
 286                         continue;
 287
 288                 list_add(&obj->obj_exec_link, &stolen);
 289
 290                 total_obj_size += obj->base.size;
 291                 count++;
 292         }
 293         list_sort(NULL, &stolen, obj_rank_by_stolen);
 294         seq_puts(m, "Stolen:\n");
 295         while (!list_empty(&stolen)) {
 296                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 297                 seq_puts(m, "   ");
 298                 describe_obj(m, obj);
 299                 seq_putc(m, '\n');
 300                 list_del_init(&obj->obj_exec_link);
 301         }
 302         mutex_unlock(&dev->struct_mutex);
 303
 304         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 305                    count, total_obj_size, total_gtt_size);
 306         return 0;
 307 }
 308
 309 #define count_objects(list, member) do { \
 310         list_for_each_entry(obj, list, member) { \
 311                 size += i915_gem_obj_total_ggtt_size(obj); \
 312                 ++count; \
 313                 if (obj->map_and_fenceable) { \
 314                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 315                         ++mappable_count; \
 316                 } \
 317         } \
 318 } while (0)
 319
 320 struct file_stats {
 321         struct drm_i915_file_private *file_priv;
 322         unsigned long count;
 323         u64 total, unbound;
 324         u64 global, shared;
 325         u64 active, inactive;
 326 };
 327
 328 static int per_file_stats(int id, void *ptr, void *data)
 329 {
 330         struct drm_i915_gem_object *obj = ptr;
 331         struct file_stats *stats = data;
 332         struct i915_vma *vma;
 333
 334         stats->count++;
 335         stats->total += obj->base.size;
 336
 337         if (obj->base.name || obj->base.dma_buf)
 338                 stats->shared += obj->base.size;
 339
 340         if (USES_FULL_PPGTT(obj->base.dev)) {
 341                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 342                         struct i915_hw_ppgtt *ppgtt;
 343
 344                         if (!drm_mm_node_allocated(&vma->node))
 345                                 continue;
 346
 347                         if (i915_is_ggtt(vma->vm)) {
 348                                 stats->global += obj->base.size;
 349                                 continue;
 350                         }
 351
 352                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 353                         if (ppgtt->file_priv != stats->file_priv)
 354                                 continue;
 355
 356                         if (obj->active) /* XXX per-vma statistic */
 357                                 stats->active += obj->base.size;
 358                         else
 359                                 stats->inactive += obj->base.size;
 360
 361                         return 0;
 362                 }
 363         } else {
 364                 if (i915_gem_obj_ggtt_bound(obj)) {
 365                         stats->global += obj->base.size;
 366                         if (obj->active)
 367                                 stats->active += obj->base.size;
 368                         else
 369                                 stats->inactive += obj->base.size;
 370                         return 0;
 371                 }
 372         }
 373
 374         if (!list_empty(&obj->global_list))
 375                 stats->unbound += obj->base.size;
 376
 377         return 0;
 378 }
 379
 380 #define print_file_stats(m, name, stats) do { \
 381         if (stats.count) \
 382                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 383                            name, \
 384                            stats.count, \
 385                            stats.total, \
 386                            stats.active, \
 387                            stats.inactive, \
 388                            stats.global, \
 389                            stats.shared, \
 390                            stats.unbound); \
 391 } while (0)
 392
 393 static void print_batch_pool_stats(struct seq_file *m,
 394                                    struct drm_i915_private *dev_priv)
 395 {
 396         struct drm_i915_gem_object *obj;
 397         struct file_stats stats;
 398         struct intel_engine_cs *ring;
 399         int i, j;
 400
 401         memset(&stats, 0, sizeof(stats));
 402
 403         for_each_ring(ring, dev_priv, i) {
 404                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 405                         list_for_each_entry(obj,
 406                                             &ring->batch_pool.cache_list[j],
 407                                             batch_pool_link)
 408                                 per_file_stats(0, obj, &stats);
 409                 }
 410         }
 411
 412         print_file_stats(m, "[k]batch pool", stats);
 413 }
 414
 415 #define count_vmas(list, member) do { \
 416         list_for_each_entry(vma, list, member) { \
 417                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 418                 ++count; \
 419                 if (vma->obj->map_and_fenceable) { \
 420                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 421                         ++mappable_count; \
 422                 } \
 423         } \
 424 } while (0)
 425
 426 static int i915_gem_object_info(struct seq_file *m, void* data)
 427 {
 428         struct drm_info_node *node = m->private;
 429         struct drm_device *dev = node->minor->dev;
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431         u32 count, mappable_count, purgeable_count;
 432         u64 size, mappable_size, purgeable_size;
 433         struct drm_i915_gem_object *obj;
 434         struct i915_address_space *vm = &dev_priv->gtt.base;
 435         struct drm_file *file;
 436         struct i915_vma *vma;
 437         int ret;
 438
 439         ret = mutex_lock_interruptible(&dev->struct_mutex);
 440         if (ret)
 441                 return ret;
 442
 443         seq_printf(m, "%u objects, %zu bytes\n",
 444                    dev_priv->mm.object_count,
 445                    dev_priv->mm.object_memory);
 446
 447         size = count = mappable_size = mappable_count = 0;
 448         count_objects(&dev_priv->mm.bound_list, global_list);
 449         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 450                    count, mappable_count, size, mappable_size);
 451
 452         size = count = mappable_size = mappable_count = 0;
 453         count_vmas(&vm->active_list, mm_list);
 454         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 455                    count, mappable_count, size, mappable_size);
 456
 457         size = count = mappable_size = mappable_count = 0;
 458         count_vmas(&vm->inactive_list, mm_list);
 459         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 460                    count, mappable_count, size, mappable_size);
 461
 462         size = count = purgeable_size = purgeable_count = 0;
 463         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 464                 size += obj->base.size, ++count;
 465                 if (obj->madv == I915_MADV_DONTNEED)
 466                         purgeable_size += obj->base.size, ++purgeable_count;
 467         }
 468         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 469
 470         size = count = mappable_size = mappable_count = 0;
 471         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 472                 if (obj->fault_mappable) {
 473                         size += i915_gem_obj_ggtt_size(obj);
 474                         ++count;
 475                 }
 476                 if (obj->pin_display) {
 477                         mappable_size += i915_gem_obj_ggtt_size(obj);
 478                         ++mappable_count;
 479                 }
 480                 if (obj->madv == I915_MADV_DONTNEED) {
 481                         purgeable_size += obj->base.size;
 482                         ++purgeable_count;
 483                 }
 484         }
 485         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 486                    purgeable_count, purgeable_size);
 487         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 488                    mappable_count, mappable_size);
 489         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 490                    count, size);
 491
 492         seq_printf(m, "%llu [%llu] gtt total\n",
 493                    dev_priv->gtt.base.total,
 494                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 495
 496         seq_putc(m, '\n');
 497         print_batch_pool_stats(m, dev_priv);
 498         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 499                 struct file_stats stats;
 500                 struct task_struct *task;
 501
 502                 memset(&stats, 0, sizeof(stats));
 503                 stats.file_priv = file->driver_priv;
 504                 spin_lock(&file->table_lock);
 505                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 506                 spin_unlock(&file->table_lock);
 507                 /*
 508                  * Although we have a valid reference on file->pid, that does
 509                  * not guarantee that the task_struct who called get_pid() is
 510                  * still alive (e.g. get_pid(current) => fork() => exit()).
 511                  * Therefore, we need to protect this ->comm access using RCU.
 512                  */
 513                 rcu_read_lock();
 514                 task = pid_task(file->pid, PIDTYPE_PID);
 515                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 516                 rcu_read_unlock();
 517         }
 518
 519         mutex_unlock(&dev->struct_mutex);
 520
 521         return 0;
 522 }
 523
 524 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 525 {
 526         struct drm_info_node *node = m->private;
 527         struct drm_device *dev = node->minor->dev;
 528         uintptr_t list = (uintptr_t) node->info_ent->data;
 529         struct drm_i915_private *dev_priv = dev->dev_private;
 530         struct drm_i915_gem_object *obj;
 531         u64 total_obj_size, total_gtt_size;
 532         int count, ret;
 533
 534         ret = mutex_lock_interruptible(&dev->struct_mutex);
 535         if (ret)
 536                 return ret;
 537
 538         total_obj_size = total_gtt_size = count = 0;
 539         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 540                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 541                         continue;
 542
 543                 seq_puts(m, "   ");
 544                 describe_obj(m, obj);
 545                 seq_putc(m, '\n');
 546                 total_obj_size += obj->base.size;
 547                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 548                 count++;
 549         }
 550
 551         mutex_unlock(&dev->struct_mutex);
 552
 553         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 554                    count, total_obj_size, total_gtt_size);
 555
 556         return 0;
 557 }
 558
 559 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 560 {
 561         struct drm_info_node *node = m->private;
 562         struct drm_device *dev = node->minor->dev;
 563         struct drm_i915_private *dev_priv = dev->dev_private;
 564         struct intel_crtc *crtc;
 565         int ret;
 566
 567         ret = mutex_lock_interruptible(&dev->struct_mutex);
 568         if (ret)
 569                 return ret;
 570
 571         for_each_intel_crtc(dev, crtc) {
 572                 const char pipe = pipe_name(crtc->pipe);
 573                 const char plane = plane_name(crtc->plane);
 574                 struct intel_unpin_work *work;
 575
 576                 spin_lock_irq(&dev->event_lock);
 577                 work = crtc->unpin_work;
 578                 if (work == NULL) {
 579                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 580                                    pipe, plane);
 581                 } else {
 582                         u32 addr;
 583
 584                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 585                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 586                                            pipe, plane);
 587                         } else {
 588                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 589                                            pipe, plane);
 590                         }
 591                         if (work->flip_queued_req) {
 592                                 struct intel_engine_cs *ring =
 593                                         i915_gem_request_get_ring(work->flip_queued_req);
 594
 595                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 596                                            ring->name,
 597                                            i915_gem_request_get_seqno(work->flip_queued_req),
 598                                            dev_priv->next_seqno,
 599                                            ring->get_seqno(ring, true),
 600                                            i915_gem_request_completed(work->flip_queued_req, true));
 601                         } else
 602                                 seq_printf(m, "Flip not associated with any ring\n");
 603                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 604                                    work->flip_queued_vblank,
 605                                    work->flip_ready_vblank,
 606                                    drm_crtc_vblank_count(&crtc->base));
 607                         if (work->enable_stall_check)
 608                                 seq_puts(m, "Stall check enabled, ");
 609                         else
 610                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 611                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 612
 613                         if (INTEL_INFO(dev)->gen >= 4)
 614                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 615                         else
 616                                 addr = I915_READ(DSPADDR(crtc->plane));
 617                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 618
 619                         if (work->pending_flip_obj) {
 620                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 621                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 622                         }
 623                 }
 624                 spin_unlock_irq(&dev->event_lock);
 625         }
 626
 627         mutex_unlock(&dev->struct_mutex);
 628
 629         return 0;
 630 }
 631
 632 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 633 {
 634         struct drm_info_node *node = m->private;
 635         struct drm_device *dev = node->minor->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         struct drm_i915_gem_object *obj;
 638         struct intel_engine_cs *ring;
 639         int total = 0;
 640         int ret, i, j;
 641
 642         ret = mutex_lock_interruptible(&dev->struct_mutex);
 643         if (ret)
 644                 return ret;
 645
 646         for_each_ring(ring, dev_priv, i) {
 647                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 648                         int count;
 649
 650                         count = 0;
 651                         list_for_each_entry(obj,
 652                                             &ring->batch_pool.cache_list[j],
 653                                             batch_pool_link)
 654                                 count++;
 655                         seq_printf(m, "%s cache[%d]: %d objects\n",
 656                                    ring->name, j, count);
 657
 658                         list_for_each_entry(obj,
 659                                             &ring->batch_pool.cache_list[j],
 660                                             batch_pool_link) {
 661                                 seq_puts(m, "   ");
 662                                 describe_obj(m, obj);
 663                                 seq_putc(m, '\n');
 664                         }
 665
 666                         total += count;
 667                 }
 668         }
 669
 670         seq_printf(m, "total: %d\n", total);
 671
 672         mutex_unlock(&dev->struct_mutex);
 673
 674         return 0;
 675 }
 676
 677 static int i915_gem_request_info(struct seq_file *m, void *data)
 678 {
 679         struct drm_info_node *node = m->private;
 680         struct drm_device *dev = node->minor->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         struct intel_engine_cs *ring;
 683         struct drm_i915_gem_request *req;
 684         int ret, any, i;
 685
 686         ret = mutex_lock_interruptible(&dev->struct_mutex);
 687         if (ret)
 688                 return ret;
 689
 690         any = 0;
 691         for_each_ring(ring, dev_priv, i) {
 692                 int count;
 693
 694                 count = 0;
 695                 list_for_each_entry(req, &ring->request_list, list)
 696                         count++;
 697                 if (count == 0)
 698                         continue;
 699
 700                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 701                 list_for_each_entry(req, &ring->request_list, list) {
 702                         struct task_struct *task;
 703
 704                         rcu_read_lock();
 705                         task = NULL;
 706                         if (req->pid)
 707                                 task = pid_task(req->pid, PIDTYPE_PID);
 708                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 709                                    req->seqno,
 710                                    (int) (jiffies - req->emitted_jiffies),
 711                                    task ? task->comm : "<unknown>",
 712                                    task ? task->pid : -1);
 713                         rcu_read_unlock();
 714                 }
 715
 716                 any++;
 717         }
 718         mutex_unlock(&dev->struct_mutex);
 719
 720         if (any == 0)
 721                 seq_puts(m, "No requests\n");
 722
 723         return 0;
 724 }
 725
 726 static void i915_ring_seqno_info(struct seq_file *m,
 727                                  struct intel_engine_cs *ring)
 728 {
 729         if (ring->get_seqno) {
 730                 seq_printf(m, "Current sequence (%s): %x\n",
 731                            ring->name, ring->get_seqno(ring, false));
 732         }
 733 }
 734
 735 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 736 {
 737         struct drm_info_node *node = m->private;
 738         struct drm_device *dev = node->minor->dev;
 739         struct drm_i915_private *dev_priv = dev->dev_private;
 740         struct intel_engine_cs *ring;
 741         int ret, i;
 742
 743         ret = mutex_lock_interruptible(&dev->struct_mutex);
 744         if (ret)
 745                 return ret;
 746         intel_runtime_pm_get(dev_priv);
 747
 748         for_each_ring(ring, dev_priv, i)
 749                 i915_ring_seqno_info(m, ring);
 750
 751         intel_runtime_pm_put(dev_priv);
 752         mutex_unlock(&dev->struct_mutex);
 753
 754         return 0;
 755 }
 756
 757
 758 static int i915_interrupt_info(struct seq_file *m, void *data)
 759 {
 760         struct drm_info_node *node = m->private;
 761         struct drm_device *dev = node->minor->dev;
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         struct intel_engine_cs *ring;
 764         int ret, i, pipe;
 765
 766         ret = mutex_lock_interruptible(&dev->struct_mutex);
 767         if (ret)
 768                 return ret;
 769         intel_runtime_pm_get(dev_priv);
 770
 771         if (IS_CHERRYVIEW(dev)) {
 772                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 773                            I915_READ(GEN8_MASTER_IRQ));
 774
 775                 seq_printf(m, "Display IER:\t%08x\n",
 776                            I915_READ(VLV_IER));
 777                 seq_printf(m, "Display IIR:\t%08x\n",
 778                            I915_READ(VLV_IIR));
 779                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 780                            I915_READ(VLV_IIR_RW));
 781                 seq_printf(m, "Display IMR:\t%08x\n",
 782                            I915_READ(VLV_IMR));
 783                 for_each_pipe(dev_priv, pipe)
 784                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 785                                    pipe_name(pipe),
 786                                    I915_READ(PIPESTAT(pipe)));
 787
 788                 seq_printf(m, "Port hotplug:\t%08x\n",
 789                            I915_READ(PORT_HOTPLUG_EN));
 790                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 791                            I915_READ(VLV_DPFLIPSTAT));
 792                 seq_printf(m, "DPINVGTT:\t%08x\n",
 793                            I915_READ(DPINVGTT));
 794
 795                 for (i = 0; i < 4; i++) {
 796                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 797                                    i, I915_READ(GEN8_GT_IMR(i)));
 798                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IIR(i)));
 800                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IER(i)));
 802                 }
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (INTEL_INFO(dev)->gen >= 8) {
 811                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 812                            I915_READ(GEN8_MASTER_IRQ));
 813
 814                 for (i = 0; i < 4; i++) {
 815                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 816                                    i, I915_READ(GEN8_GT_IMR(i)));
 817                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 818                                    i, I915_READ(GEN8_GT_IIR(i)));
 819                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IER(i)));
 821                 }
 822
 823                 for_each_pipe(dev_priv, pipe) {
 824                         if (!intel_display_power_is_enabled(dev_priv,
 825                                                 POWER_DOMAIN_PIPE(pipe))) {
 826                                 seq_printf(m, "Pipe %c power disabled\n",
 827                                            pipe_name(pipe));
 828                                 continue;
 829                         }
 830                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 831                                    pipe_name(pipe),
 832                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 833                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 834                                    pipe_name(pipe),
 835                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 836                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 837                                    pipe_name(pipe),
 838                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 839                 }
 840
 841                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 842                            I915_READ(GEN8_DE_PORT_IMR));
 843                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 844                            I915_READ(GEN8_DE_PORT_IIR));
 845                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 846                            I915_READ(GEN8_DE_PORT_IER));
 847
 848                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 849                            I915_READ(GEN8_DE_MISC_IMR));
 850                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 851                            I915_READ(GEN8_DE_MISC_IIR));
 852                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 853                            I915_READ(GEN8_DE_MISC_IER));
 854
 855                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 856                            I915_READ(GEN8_PCU_IMR));
 857                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 858                            I915_READ(GEN8_PCU_IIR));
 859                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 860                            I915_READ(GEN8_PCU_IER));
 861         } else if (IS_VALLEYVIEW(dev)) {
 862                 seq_printf(m, "Display IER:\t%08x\n",
 863                            I915_READ(VLV_IER));
 864                 seq_printf(m, "Display IIR:\t%08x\n",
 865                            I915_READ(VLV_IIR));
 866                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 867                            I915_READ(VLV_IIR_RW));
 868                 seq_printf(m, "Display IMR:\t%08x\n",
 869                            I915_READ(VLV_IMR));
 870                 for_each_pipe(dev_priv, pipe)
 871                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 872                                    pipe_name(pipe),
 873                                    I915_READ(PIPESTAT(pipe)));
 874
 875                 seq_printf(m, "Master IER:\t%08x\n",
 876                            I915_READ(VLV_MASTER_IER));
 877
 878                 seq_printf(m, "Render IER:\t%08x\n",
 879                            I915_READ(GTIER));
 880                 seq_printf(m, "Render IIR:\t%08x\n",
 881                            I915_READ(GTIIR));
 882                 seq_printf(m, "Render IMR:\t%08x\n",
 883                            I915_READ(GTIMR));
 884
 885                 seq_printf(m, "PM IER:\t\t%08x\n",
 886                            I915_READ(GEN6_PMIER));
 887                 seq_printf(m, "PM IIR:\t\t%08x\n",
 888                            I915_READ(GEN6_PMIIR));
 889                 seq_printf(m, "PM IMR:\t\t%08x\n",
 890                            I915_READ(GEN6_PMIMR));
 891
 892                 seq_printf(m, "Port hotplug:\t%08x\n",
 893                            I915_READ(PORT_HOTPLUG_EN));
 894                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 895                            I915_READ(VLV_DPFLIPSTAT));
 896                 seq_printf(m, "DPINVGTT:\t%08x\n",
 897                            I915_READ(DPINVGTT));
 898
 899         } else if (!HAS_PCH_SPLIT(dev)) {
 900                 seq_printf(m, "Interrupt enable:    %08x\n",
 901                            I915_READ(IER));
 902                 seq_printf(m, "Interrupt identity:  %08x\n",
 903                            I915_READ(IIR));
 904                 seq_printf(m, "Interrupt mask:      %08x\n",
 905                            I915_READ(IMR));
 906                 for_each_pipe(dev_priv, pipe)
 907                         seq_printf(m, "Pipe %c stat:         %08x\n",
 908                                    pipe_name(pipe),
 909                                    I915_READ(PIPESTAT(pipe)));
 910         } else {
 911                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 912                            I915_READ(DEIER));
 913                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 914                            I915_READ(DEIIR));
 915                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 916                            I915_READ(DEIMR));
 917                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 918                            I915_READ(SDEIER));
 919                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 920                            I915_READ(SDEIIR));
 921                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 922                            I915_READ(SDEIMR));
 923                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 924                            I915_READ(GTIER));
 925                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 926                            I915_READ(GTIIR));
 927                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 928                            I915_READ(GTIMR));
 929         }
 930         for_each_ring(ring, dev_priv, i) {
 931                 if (INTEL_INFO(dev)->gen >= 6) {
 932                         seq_printf(m,
 933                                    "Graphics Interrupt mask (%s):       %08x\n",
 934                                    ring->name, I915_READ_IMR(ring));
 935                 }
 936                 i915_ring_seqno_info(m, ring);
 937         }
 938         intel_runtime_pm_put(dev_priv);
 939         mutex_unlock(&dev->struct_mutex);
 940
 941         return 0;
 942 }
 943
 944 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 945 {
 946         struct drm_info_node *node = m->private;
 947         struct drm_device *dev = node->minor->dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         int i, ret;
 950
 951         ret = mutex_lock_interruptible(&dev->struct_mutex);
 952         if (ret)
 953                 return ret;
 954
 955         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 956         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 957         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 958                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 959
 960                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 961                            i, dev_priv->fence_regs[i].pin_count);
 962                 if (obj == NULL)
 963                         seq_puts(m, "unused");
 964                 else
 965                         describe_obj(m, obj);
 966                 seq_putc(m, '\n');
 967         }
 968
 969         mutex_unlock(&dev->struct_mutex);
 970         return 0;
 971 }
 972
 973 static int i915_hws_info(struct seq_file *m, void *data)
 974 {
 975         struct drm_info_node *node = m->private;
 976         struct drm_device *dev = node->minor->dev;
 977         struct drm_i915_private *dev_priv = dev->dev_private;
 978         struct intel_engine_cs *ring;
 979         const u32 *hws;
 980         int i;
 981
 982         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 983         hws = ring->status_page.page_addr;
 984         if (hws == NULL)
 985                 return 0;
 986
 987         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 988                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 989                            i * 4,
 990                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 991         }
 992         return 0;
 993 }
 994
 995 static ssize_t
 996 i915_error_state_write(struct file *filp,
 997                        const char __user *ubuf,
 998                        size_t cnt,
 999                        loff_t *ppos)
1000 {
1001         struct i915_error_state_file_priv *error_priv = filp->private_data;
1002         struct drm_device *dev = error_priv->dev;
1003         int ret;
1004
1005         DRM_DEBUG_DRIVER("Resetting error state\n");
1006
1007         ret = mutex_lock_interruptible(&dev->struct_mutex);
1008         if (ret)
1009                 return ret;
1010
1011         i915_destroy_error_state(dev);
1012         mutex_unlock(&dev->struct_mutex);
1013
1014         return cnt;
1015 }
1016
1017 static int i915_error_state_open(struct inode *inode, struct file *file)
1018 {
1019         struct drm_device *dev = inode->i_private;
1020         struct i915_error_state_file_priv *error_priv;
1021
1022         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1023         if (!error_priv)
1024                 return -ENOMEM;
1025
1026         error_priv->dev = dev;
1027
1028         i915_error_state_get(dev, error_priv);
1029
1030         file->private_data = error_priv;
1031
1032         return 0;
1033 }
1034
1035 static int i915_error_state_release(struct inode *inode, struct file *file)
1036 {
1037         struct i915_error_state_file_priv *error_priv = file->private_data;
1038
1039         i915_error_state_put(error_priv);
1040         kfree(error_priv);
1041
1042         return 0;
1043 }
1044
1045 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1046                                      size_t count, loff_t *pos)
1047 {
1048         struct i915_error_state_file_priv *error_priv = file->private_data;
1049         struct drm_i915_error_state_buf error_str;
1050         loff_t tmp_pos = 0;
1051         ssize_t ret_count = 0;
1052         int ret;
1053
1054         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1055         if (ret)
1056                 return ret;
1057
1058         ret = i915_error_state_to_str(&error_str, error_priv);
1059         if (ret)
1060                 goto out;
1061
1062         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1063                                             error_str.buf,
1064                                             error_str.bytes);
1065
1066         if (ret_count < 0)
1067                 ret = ret_count;
1068         else
1069                 *pos = error_str.start + ret_count;
1070 out:
1071         i915_error_state_buf_release(&error_str);
1072         return ret ?: ret_count;
1073 }
1074
1075 static const struct file_operations i915_error_state_fops = {
1076         .owner = THIS_MODULE,
1077         .open = i915_error_state_open,
1078         .read = i915_error_state_read,
1079         .write = i915_error_state_write,
1080         .llseek = default_llseek,
1081         .release = i915_error_state_release,
1082 };
1083
1084 static int
1085 i915_next_seqno_get(void *data, u64 *val)
1086 {
1087         struct drm_device *dev = data;
1088         struct drm_i915_private *dev_priv = dev->dev_private;
1089         int ret;
1090
1091         ret = mutex_lock_interruptible(&dev->struct_mutex);
1092         if (ret)
1093                 return ret;
1094
1095         *val = dev_priv->next_seqno;
1096         mutex_unlock(&dev->struct_mutex);
1097
1098         return 0;
1099 }
1100
1101 static int
1102 i915_next_seqno_set(void *data, u64 val)
1103 {
1104         struct drm_device *dev = data;
1105         int ret;
1106
1107         ret = mutex_lock_interruptible(&dev->struct_mutex);
1108         if (ret)
1109                 return ret;
1110
1111         ret = i915_gem_set_seqno(dev, val);
1112         mutex_unlock(&dev->struct_mutex);
1113
1114         return ret;
1115 }
1116
1117 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1118                         i915_next_seqno_get, i915_next_seqno_set,
1119                         "0x%llx\n");
1120
1121 static int i915_frequency_info(struct seq_file *m, void *unused)
1122 {
1123         struct drm_info_node *node = m->private;
1124         struct drm_device *dev = node->minor->dev;
1125         struct drm_i915_private *dev_priv = dev->dev_private;
1126         int ret = 0;
1127
1128         intel_runtime_pm_get(dev_priv);
1129
1130         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1131
1132         if (IS_GEN5(dev)) {
1133                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1134                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1135
1136                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1137                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1138                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1139                            MEMSTAT_VID_SHIFT);
1140                 seq_printf(m, "Current P-state: %d\n",
1141                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1142         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1143                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1144                 u32 rp_state_limits;
1145                 u32 gt_perf_status;
1146                 u32 rp_state_cap;
1147                 u32 rpmodectl, rpinclimit, rpdeclimit;
1148                 u32 rpstat, cagf, reqf;
1149                 u32 rpupei, rpcurup, rpprevup;
1150                 u32 rpdownei, rpcurdown, rpprevdown;
1151                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1152                 int max_freq;
1153
1154                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1155                 if (IS_BROXTON(dev)) {
1156                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1157                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1158                 } else {
1159                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1160                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1161                 }
1162
1163                 /* RPSTAT1 is in the GT power well */
1164                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1165                 if (ret)
1166                         goto out;
1167
1168                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1169
1170                 reqf = I915_READ(GEN6_RPNSWREQ);
1171                 if (IS_GEN9(dev))
1172                         reqf >>= 23;
1173                 else {
1174                         reqf &= ~GEN6_TURBO_DISABLE;
1175                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1176                                 reqf >>= 24;
1177                         else
1178                                 reqf >>= 25;
1179                 }
1180                 reqf = intel_gpu_freq(dev_priv, reqf);
1181
1182                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1183                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1184                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1185
1186                 rpstat = I915_READ(GEN6_RPSTAT1);
1187                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1188                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1189                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1190                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1191                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1192                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1193                 if (IS_GEN9(dev))
1194                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1195                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1196                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1197                 else
1198                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1199                 cagf = intel_gpu_freq(dev_priv, cagf);
1200
1201                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1202                 mutex_unlock(&dev->struct_mutex);
1203
1204                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1205                         pm_ier = I915_READ(GEN6_PMIER);
1206                         pm_imr = I915_READ(GEN6_PMIMR);
1207                         pm_isr = I915_READ(GEN6_PMISR);
1208                         pm_iir = I915_READ(GEN6_PMIIR);
1209                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1210                 } else {
1211                         pm_ier = I915_READ(GEN8_GT_IER(2));
1212                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1213                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1214                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1215                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1216                 }
1217                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1218                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1219                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1220                 seq_printf(m, "Render p-state ratio: %d\n",
1221                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1222                 seq_printf(m, "Render p-state VID: %d\n",
1223                            gt_perf_status & 0xff);
1224                 seq_printf(m, "Render p-state limit: %d\n",
1225                            rp_state_limits & 0xff);
1226                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1227                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1228                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1229                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1230                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1231                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1232                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1233                            GEN6_CURICONT_MASK);
1234                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1235                            GEN6_CURBSYTAVG_MASK);
1236                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1237                            GEN6_CURBSYTAVG_MASK);
1238                 seq_printf(m, "Up threshold: %d%%\n",
1239                            dev_priv->rps.up_threshold);
1240
1241                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1242                            GEN6_CURIAVG_MASK);
1243                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1244                            GEN6_CURBSYTAVG_MASK);
1245                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1246                            GEN6_CURBSYTAVG_MASK);
1247                 seq_printf(m, "Down threshold: %d%%\n",
1248                            dev_priv->rps.down_threshold);
1249
1250                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1251                             rp_state_cap >> 16) & 0xff;
1252                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1253                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1254                            intel_gpu_freq(dev_priv, max_freq));
1255
1256                 max_freq = (rp_state_cap & 0xff00) >> 8;
1257                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1258                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, max_freq));
1260
1261                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1262                             rp_state_cap >> 0) & 0xff;
1263                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1264                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1265                            intel_gpu_freq(dev_priv, max_freq));
1266                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1267                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1268
1269                 seq_printf(m, "Current freq: %d MHz\n",
1270                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1271                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1272                 seq_printf(m, "Idle freq: %d MHz\n",
1273                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1274                 seq_printf(m, "Min freq: %d MHz\n",
1275                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1276                 seq_printf(m, "Max freq: %d MHz\n",
1277                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1278                 seq_printf(m,
1279                            "efficient (RPe) frequency: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1281         } else if (IS_VALLEYVIEW(dev)) {
1282                 u32 freq_sts;
1283
1284                 mutex_lock(&dev_priv->rps.hw_lock);
1285                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1286                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1287                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1288
1289                 seq_printf(m, "actual GPU freq: %d MHz\n",
1290                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1291
1292                 seq_printf(m, "current GPU freq: %d MHz\n",
1293                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1294
1295                 seq_printf(m, "max GPU freq: %d MHz\n",
1296                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1297
1298                 seq_printf(m, "min GPU freq: %d MHz\n",
1299                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1300
1301                 seq_printf(m, "idle GPU freq: %d MHz\n",
1302                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1303
1304                 seq_printf(m,
1305                            "efficient (RPe) frequency: %d MHz\n",
1306                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1307                 mutex_unlock(&dev_priv->rps.hw_lock);
1308         } else {
1309                 seq_puts(m, "no P-state info available\n");
1310         }
1311
1312 out:
1313         intel_runtime_pm_put(dev_priv);
1314         return ret;
1315 }
1316
1317 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1318 {
1319         struct drm_info_node *node = m->private;
1320         struct drm_device *dev = node->minor->dev;
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322         struct intel_engine_cs *ring;
1323         u64 acthd[I915_NUM_RINGS];
1324         u32 seqno[I915_NUM_RINGS];
1325         int i;
1326
1327         if (!i915.enable_hangcheck) {
1328                 seq_printf(m, "Hangcheck disabled\n");
1329                 return 0;
1330         }
1331
1332         intel_runtime_pm_get(dev_priv);
1333
1334         for_each_ring(ring, dev_priv, i) {
1335                 seqno[i] = ring->get_seqno(ring, false);
1336                 acthd[i] = intel_ring_get_active_head(ring);
1337         }
1338
1339         intel_runtime_pm_put(dev_priv);
1340
1341         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1342                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1343                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1344                                             jiffies));
1345         } else
1346                 seq_printf(m, "Hangcheck inactive\n");
1347
1348         for_each_ring(ring, dev_priv, i) {
1349                 seq_printf(m, "%s:\n", ring->name);
1350                 seq_printf(m, "\tseqno = %x [current %x]\n",
1351                            ring->hangcheck.seqno, seqno[i]);
1352                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1353                            (long long)ring->hangcheck.acthd,
1354                            (long long)acthd[i]);
1355                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1356                            (long long)ring->hangcheck.max_acthd);
1357                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1358                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int ironlake_drpc_info(struct seq_file *m)
1365 {
1366         struct drm_info_node *node = m->private;
1367         struct drm_device *dev = node->minor->dev;
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         u32 rgvmodectl, rstdbyctl;
1370         u16 crstandvid;
1371         int ret;
1372
1373         ret = mutex_lock_interruptible(&dev->struct_mutex);
1374         if (ret)
1375                 return ret;
1376         intel_runtime_pm_get(dev_priv);
1377
1378         rgvmodectl = I915_READ(MEMMODECTL);
1379         rstdbyctl = I915_READ(RSTDBYCTL);
1380         crstandvid = I915_READ16(CRSTANDVID);
1381
1382         intel_runtime_pm_put(dev_priv);
1383         mutex_unlock(&dev->struct_mutex);
1384
1385         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1386                    "yes" : "no");
1387         seq_printf(m, "Boost freq: %d\n",
1388                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1389                    MEMMODE_BOOST_FREQ_SHIFT);
1390         seq_printf(m, "HW control enabled: %s\n",
1391                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1392         seq_printf(m, "SW control enabled: %s\n",
1393                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1394         seq_printf(m, "Gated voltage change: %s\n",
1395                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1396         seq_printf(m, "Starting frequency: P%d\n",
1397                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1398         seq_printf(m, "Max P-state: P%d\n",
1399                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1400         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1401         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1402         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1403         seq_printf(m, "Render standby enabled: %s\n",
1404                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1405         seq_puts(m, "Current RS state: ");
1406         switch (rstdbyctl & RSX_STATUS_MASK) {
1407         case RSX_STATUS_ON:
1408                 seq_puts(m, "on\n");
1409                 break;
1410         case RSX_STATUS_RC1:
1411                 seq_puts(m, "RC1\n");
1412                 break;
1413         case RSX_STATUS_RC1E:
1414                 seq_puts(m, "RC1E\n");
1415                 break;
1416         case RSX_STATUS_RS1:
1417                 seq_puts(m, "RS1\n");
1418                 break;
1419         case RSX_STATUS_RS2:
1420                 seq_puts(m, "RS2 (RC6)\n");
1421                 break;
1422         case RSX_STATUS_RS3:
1423                 seq_puts(m, "RC3 (RC6+)\n");
1424                 break;
1425         default:
1426                 seq_puts(m, "unknown\n");
1427                 break;
1428         }
1429
1430         return 0;
1431 }
1432
1433 static int i915_forcewake_domains(struct seq_file *m, void *data)
1434 {
1435         struct drm_info_node *node = m->private;
1436         struct drm_device *dev = node->minor->dev;
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         struct intel_uncore_forcewake_domain *fw_domain;
1439         int i;
1440
1441         spin_lock_irq(&dev_priv->uncore.lock);
1442         for_each_fw_domain(fw_domain, dev_priv, i) {
1443                 seq_printf(m, "%s.wake_count = %u\n",
1444                            intel_uncore_forcewake_domain_to_str(i),
1445                            fw_domain->wake_count);
1446         }
1447         spin_unlock_irq(&dev_priv->uncore.lock);
1448
1449         return 0;
1450 }
1451
1452 static int vlv_drpc_info(struct seq_file *m)
1453 {
1454         struct drm_info_node *node = m->private;
1455         struct drm_device *dev = node->minor->dev;
1456         struct drm_i915_private *dev_priv = dev->dev_private;
1457         u32 rpmodectl1, rcctl1, pw_status;
1458
1459         intel_runtime_pm_get(dev_priv);
1460
1461         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1462         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1463         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1464
1465         intel_runtime_pm_put(dev_priv);
1466
1467         seq_printf(m, "Video Turbo Mode: %s\n",
1468                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1469         seq_printf(m, "Turbo enabled: %s\n",
1470                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1471         seq_printf(m, "HW control enabled: %s\n",
1472                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1473         seq_printf(m, "SW control enabled: %s\n",
1474                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1475                           GEN6_RP_MEDIA_SW_MODE));
1476         seq_printf(m, "RC6 Enabled: %s\n",
1477                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1478                                         GEN6_RC_CTL_EI_MODE(1))));
1479         seq_printf(m, "Render Power Well: %s\n",
1480                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1481         seq_printf(m, "Media Power Well: %s\n",
1482                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1483
1484         seq_printf(m, "Render RC6 residency since boot: %u\n",
1485                    I915_READ(VLV_GT_RENDER_RC6));
1486         seq_printf(m, "Media RC6 residency since boot: %u\n",
1487                    I915_READ(VLV_GT_MEDIA_RC6));
1488
1489         return i915_forcewake_domains(m, NULL);
1490 }
1491
1492 static int gen6_drpc_info(struct seq_file *m)
1493 {
1494         struct drm_info_node *node = m->private;
1495         struct drm_device *dev = node->minor->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1498         unsigned forcewake_count;
1499         int count = 0, ret;
1500
1501         ret = mutex_lock_interruptible(&dev->struct_mutex);
1502         if (ret)
1503                 return ret;
1504         intel_runtime_pm_get(dev_priv);
1505
1506         spin_lock_irq(&dev_priv->uncore.lock);
1507         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1508         spin_unlock_irq(&dev_priv->uncore.lock);
1509
1510         if (forcewake_count) {
1511                 seq_puts(m, "RC information inaccurate because somebody "
1512                             "holds a forcewake reference \n");
1513         } else {
1514                 /* NB: we cannot use forcewake, else we read the wrong values */
1515                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1516                         udelay(10);
1517                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1518         }
1519
1520         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1521         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1522
1523         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1524         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1525         mutex_unlock(&dev->struct_mutex);
1526         mutex_lock(&dev_priv->rps.hw_lock);
1527         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1528         mutex_unlock(&dev_priv->rps.hw_lock);
1529
1530         intel_runtime_pm_put(dev_priv);
1531
1532         seq_printf(m, "Video Turbo Mode: %s\n",
1533                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1534         seq_printf(m, "HW control enabled: %s\n",
1535                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1536         seq_printf(m, "SW control enabled: %s\n",
1537                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1538                           GEN6_RP_MEDIA_SW_MODE));
1539         seq_printf(m, "RC1e Enabled: %s\n",
1540                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1541         seq_printf(m, "RC6 Enabled: %s\n",
1542                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1543         seq_printf(m, "Deep RC6 Enabled: %s\n",
1544                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1545         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1546                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1547         seq_puts(m, "Current RC state: ");
1548         switch (gt_core_status & GEN6_RCn_MASK) {
1549         case GEN6_RC0:
1550                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1551                         seq_puts(m, "Core Power Down\n");
1552                 else
1553                         seq_puts(m, "on\n");
1554                 break;
1555         case GEN6_RC3:
1556                 seq_puts(m, "RC3\n");
1557                 break;
1558         case GEN6_RC6:
1559                 seq_puts(m, "RC6\n");
1560                 break;
1561         case GEN6_RC7:
1562                 seq_puts(m, "RC7\n");
1563                 break;
1564         default:
1565                 seq_puts(m, "Unknown\n");
1566                 break;
1567         }
1568
1569         seq_printf(m, "Core Power Down: %s\n",
1570                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1571
1572         /* Not exactly sure what this is */
1573         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1574                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1575         seq_printf(m, "RC6 residency since boot: %u\n",
1576                    I915_READ(GEN6_GT_GFX_RC6));
1577         seq_printf(m, "RC6+ residency since boot: %u\n",
1578                    I915_READ(GEN6_GT_GFX_RC6p));
1579         seq_printf(m, "RC6++ residency since boot: %u\n",
1580                    I915_READ(GEN6_GT_GFX_RC6pp));
1581
1582         seq_printf(m, "RC6   voltage: %dmV\n",
1583                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1584         seq_printf(m, "RC6+  voltage: %dmV\n",
1585                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1586         seq_printf(m, "RC6++ voltage: %dmV\n",
1587                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1588         return 0;
1589 }
1590
1591 static int i915_drpc_info(struct seq_file *m, void *unused)
1592 {
1593         struct drm_info_node *node = m->private;
1594         struct drm_device *dev = node->minor->dev;
1595
1596         if (IS_VALLEYVIEW(dev))
1597                 return vlv_drpc_info(m);
1598         else if (INTEL_INFO(dev)->gen >= 6)
1599                 return gen6_drpc_info(m);
1600         else
1601                 return ironlake_drpc_info(m);
1602 }
1603
1604 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1605 {
1606         struct drm_info_node *node = m->private;
1607         struct drm_device *dev = node->minor->dev;
1608         struct drm_i915_private *dev_priv = dev->dev_private;
1609
1610         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1611                    dev_priv->fb_tracking.busy_bits);
1612
1613         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1614                    dev_priv->fb_tracking.flip_bits);
1615
1616         return 0;
1617 }
1618
1619 static int i915_fbc_status(struct seq_file *m, void *unused)
1620 {
1621         struct drm_info_node *node = m->private;
1622         struct drm_device *dev = node->minor->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625         if (!HAS_FBC(dev)) {
1626                 seq_puts(m, "FBC unsupported on this chipset\n");
1627                 return 0;
1628         }
1629
1630         intel_runtime_pm_get(dev_priv);
1631         mutex_lock(&dev_priv->fbc.lock);
1632
1633         if (intel_fbc_enabled(dev_priv))
1634                 seq_puts(m, "FBC enabled\n");
1635         else
1636                 seq_printf(m, "FBC disabled: %s\n",
1637                           intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1638
1639         if (INTEL_INFO(dev_priv)->gen >= 7)
1640                 seq_printf(m, "Compressing: %s\n",
1641                            yesno(I915_READ(FBC_STATUS2) &
1642                                  FBC_COMPRESSION_MASK));
1643
1644         mutex_unlock(&dev_priv->fbc.lock);
1645         intel_runtime_pm_put(dev_priv);
1646
1647         return 0;
1648 }
1649
1650 static int i915_fbc_fc_get(void *data, u64 *val)
1651 {
1652         struct drm_device *dev = data;
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654
1655         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1656                 return -ENODEV;
1657
1658         *val = dev_priv->fbc.false_color;
1659
1660         return 0;
1661 }
1662
1663 static int i915_fbc_fc_set(void *data, u64 val)
1664 {
1665         struct drm_device *dev = data;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         u32 reg;
1668
1669         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1670                 return -ENODEV;
1671
1672         mutex_lock(&dev_priv->fbc.lock);
1673
1674         reg = I915_READ(ILK_DPFC_CONTROL);
1675         dev_priv->fbc.false_color = val;
1676
1677         I915_WRITE(ILK_DPFC_CONTROL, val ?
1678                    (reg | FBC_CTL_FALSE_COLOR) :
1679                    (reg & ~FBC_CTL_FALSE_COLOR));
1680
1681         mutex_unlock(&dev_priv->fbc.lock);
1682         return 0;
1683 }
1684
1685 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1686                         i915_fbc_fc_get, i915_fbc_fc_set,
1687                         "%llu\n");
1688
1689 static int i915_ips_status(struct seq_file *m, void *unused)
1690 {
1691         struct drm_info_node *node = m->private;
1692         struct drm_device *dev = node->minor->dev;
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694
1695         if (!HAS_IPS(dev)) {
1696                 seq_puts(m, "not supported\n");
1697                 return 0;
1698         }
1699
1700         intel_runtime_pm_get(dev_priv);
1701
1702         seq_printf(m, "Enabled by kernel parameter: %s\n",
1703                    yesno(i915.enable_ips));
1704
1705         if (INTEL_INFO(dev)->gen >= 8) {
1706                 seq_puts(m, "Currently: unknown\n");
1707         } else {
1708                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1709                         seq_puts(m, "Currently: enabled\n");
1710                 else
1711                         seq_puts(m, "Currently: disabled\n");
1712         }
1713
1714         intel_runtime_pm_put(dev_priv);
1715
1716         return 0;
1717 }
1718
1719 static int i915_sr_status(struct seq_file *m, void *unused)
1720 {
1721         struct drm_info_node *node = m->private;
1722         struct drm_device *dev = node->minor->dev;
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         bool sr_enabled = false;
1725
1726         intel_runtime_pm_get(dev_priv);
1727
1728         if (HAS_PCH_SPLIT(dev))
1729                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1730         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1731                  IS_I945G(dev) || IS_I945GM(dev))
1732                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1733         else if (IS_I915GM(dev))
1734                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1735         else if (IS_PINEVIEW(dev))
1736                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1737         else if (IS_VALLEYVIEW(dev))
1738                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1739
1740         intel_runtime_pm_put(dev_priv);
1741
1742         seq_printf(m, "self-refresh: %s\n",
1743                    sr_enabled ? "enabled" : "disabled");
1744
1745         return 0;
1746 }
1747
1748 static int i915_emon_status(struct seq_file *m, void *unused)
1749 {
1750         struct drm_info_node *node = m->private;
1751         struct drm_device *dev = node->minor->dev;
1752         struct drm_i915_private *dev_priv = dev->dev_private;
1753         unsigned long temp, chipset, gfx;
1754         int ret;
1755
1756         if (!IS_GEN5(dev))
1757                 return -ENODEV;
1758
1759         ret = mutex_lock_interruptible(&dev->struct_mutex);
1760         if (ret)
1761                 return ret;
1762
1763         temp = i915_mch_val(dev_priv);
1764         chipset = i915_chipset_val(dev_priv);
1765         gfx = i915_gfx_val(dev_priv);
1766         mutex_unlock(&dev->struct_mutex);
1767
1768         seq_printf(m, "GMCH temp: %ld\n", temp);
1769         seq_printf(m, "Chipset power: %ld\n", chipset);
1770         seq_printf(m, "GFX power: %ld\n", gfx);
1771         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1772
1773         return 0;
1774 }
1775
1776 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1777 {
1778         struct drm_info_node *node = m->private;
1779         struct drm_device *dev = node->minor->dev;
1780         struct drm_i915_private *dev_priv = dev->dev_private;
1781         int ret = 0;
1782         int gpu_freq, ia_freq;
1783         unsigned int max_gpu_freq, min_gpu_freq;
1784
1785         if (!HAS_CORE_RING_FREQ(dev)) {
1786                 seq_puts(m, "unsupported on this chipset\n");
1787                 return 0;
1788         }
1789
1790         intel_runtime_pm_get(dev_priv);
1791
1792         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1793
1794         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1795         if (ret)
1796                 goto out;
1797
1798         if (IS_SKYLAKE(dev)) {
1799                 /* Convert GT frequency to 50 HZ units */
1800                 min_gpu_freq =
1801                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1802                 max_gpu_freq =
1803                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1804         } else {
1805                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1806                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1807         }
1808
1809         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1810
1811         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1812                 ia_freq = gpu_freq;
1813                 sandybridge_pcode_read(dev_priv,
1814                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1815                                        &ia_freq);
1816                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1817                            intel_gpu_freq(dev_priv, (gpu_freq *
1818                                 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1819                            ((ia_freq >> 0) & 0xff) * 100,
1820                            ((ia_freq >> 8) & 0xff) * 100);
1821         }
1822
1823         mutex_unlock(&dev_priv->rps.hw_lock);
1824
1825 out:
1826         intel_runtime_pm_put(dev_priv);
1827         return ret;
1828 }
1829
1830 static int i915_opregion(struct seq_file *m, void *unused)
1831 {
1832         struct drm_info_node *node = m->private;
1833         struct drm_device *dev = node->minor->dev;
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         struct intel_opregion *opregion = &dev_priv->opregion;
1836         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1837         int ret;
1838
1839         if (data == NULL)
1840                 return -ENOMEM;
1841
1842         ret = mutex_lock_interruptible(&dev->struct_mutex);
1843         if (ret)
1844                 goto out;
1845
1846         if (opregion->header) {
1847                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1848                 seq_write(m, data, OPREGION_SIZE);
1849         }
1850
1851         mutex_unlock(&dev->struct_mutex);
1852
1853 out:
1854         kfree(data);
1855         return 0;
1856 }
1857
1858 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1859 {
1860         struct drm_info_node *node = m->private;
1861         struct drm_device *dev = node->minor->dev;
1862         struct intel_fbdev *ifbdev = NULL;
1863         struct intel_framebuffer *fb;
1864         struct drm_framebuffer *drm_fb;
1865
1866 #ifdef CONFIG_DRM_FBDEV_EMULATION
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868
1869         ifbdev = dev_priv->fbdev;
1870         fb = to_intel_framebuffer(ifbdev->helper.fb);
1871
1872         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1873                    fb->base.width,
1874                    fb->base.height,
1875                    fb->base.depth,
1876                    fb->base.bits_per_pixel,
1877                    fb->base.modifier[0],
1878                    atomic_read(&fb->base.refcount.refcount));
1879         describe_obj(m, fb->obj);
1880         seq_putc(m, '\n');
1881 #endif
1882
1883         mutex_lock(&dev->mode_config.fb_lock);
1884         drm_for_each_fb(drm_fb, dev) {
1885                 fb = to_intel_framebuffer(drm_fb);
1886                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1887                         continue;
1888
1889                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1890                            fb->base.width,
1891                            fb->base.height,
1892                            fb->base.depth,
1893                            fb->base.bits_per_pixel,
1894                            fb->base.modifier[0],
1895                            atomic_read(&fb->base.refcount.refcount));
1896                 describe_obj(m, fb->obj);
1897                 seq_putc(m, '\n');
1898         }
1899         mutex_unlock(&dev->mode_config.fb_lock);
1900
1901         return 0;
1902 }
1903
1904 static void describe_ctx_ringbuf(struct seq_file *m,
1905                                  struct intel_ringbuffer *ringbuf)
1906 {
1907         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1908                    ringbuf->space, ringbuf->head, ringbuf->tail,
1909                    ringbuf->last_retired_head);
1910 }
1911
1912 static int i915_context_status(struct seq_file *m, void *unused)
1913 {
1914         struct drm_info_node *node = m->private;
1915         struct drm_device *dev = node->minor->dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_engine_cs *ring;
1918         struct intel_context *ctx;
1919         int ret, i;
1920
1921         ret = mutex_lock_interruptible(&dev->struct_mutex);
1922         if (ret)
1923                 return ret;
1924
1925         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1926                 if (!i915.enable_execlists &&
1927                     ctx->legacy_hw_ctx.rcs_state == NULL)
1928                         continue;
1929
1930                 seq_puts(m, "HW context ");
1931                 describe_ctx(m, ctx);
1932                 for_each_ring(ring, dev_priv, i) {
1933                         if (ring->default_context == ctx)
1934                                 seq_printf(m, "(default context %s) ",
1935                                            ring->name);
1936                 }
1937
1938                 if (i915.enable_execlists) {
1939                         seq_putc(m, '\n');
1940                         for_each_ring(ring, dev_priv, i) {
1941                                 struct drm_i915_gem_object *ctx_obj =
1942                                         ctx->engine[i].state;
1943                                 struct intel_ringbuffer *ringbuf =
1944                                         ctx->engine[i].ringbuf;
1945
1946                                 seq_printf(m, "%s: ", ring->name);
1947                                 if (ctx_obj)
1948                                         describe_obj(m, ctx_obj);
1949                                 if (ringbuf)
1950                                         describe_ctx_ringbuf(m, ringbuf);
1951                                 seq_putc(m, '\n');
1952                         }
1953                 } else {
1954                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1955                 }
1956
1957                 seq_putc(m, '\n');
1958         }
1959
1960         mutex_unlock(&dev->struct_mutex);
1961
1962         return 0;
1963 }
1964
1965 static void i915_dump_lrc_obj(struct seq_file *m,
1966                               struct intel_engine_cs *ring,
1967                               struct drm_i915_gem_object *ctx_obj)
1968 {
1969         struct page *page;
1970         uint32_t *reg_state;
1971         int j;
1972         unsigned long ggtt_offset = 0;
1973
1974         if (ctx_obj == NULL) {
1975                 seq_printf(m, "Context on %s with no gem object\n",
1976                            ring->name);
1977                 return;
1978         }
1979
1980         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1981                    intel_execlists_ctx_id(ctx_obj));
1982
1983         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1984                 seq_puts(m, "\tNot bound in GGTT\n");
1985         else
1986                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1987
1988         if (i915_gem_object_get_pages(ctx_obj)) {
1989                 seq_puts(m, "\tFailed to get pages for context object\n");
1990                 return;
1991         }
1992
1993         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
1994         if (!WARN_ON(page == NULL)) {
1995                 reg_state = kmap_atomic(page);
1996
1997                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1998                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1999                                    ggtt_offset + 4096 + (j * 4),
2000                                    reg_state[j], reg_state[j + 1],
2001                                    reg_state[j + 2], reg_state[j + 3]);
2002                 }
2003                 kunmap_atomic(reg_state);
2004         }
2005
2006         seq_putc(m, '\n');
2007 }
2008
2009 static int i915_dump_lrc(struct seq_file *m, void *unused)
2010 {
2011         struct drm_info_node *node = (struct drm_info_node *) m->private;
2012         struct drm_device *dev = node->minor->dev;
2013         struct drm_i915_private *dev_priv = dev->dev_private;
2014         struct intel_engine_cs *ring;
2015         struct intel_context *ctx;
2016         int ret, i;
2017
2018         if (!i915.enable_execlists) {
2019                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2020                 return 0;
2021         }
2022
2023         ret = mutex_lock_interruptible(&dev->struct_mutex);
2024         if (ret)
2025                 return ret;
2026
2027         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2028                 for_each_ring(ring, dev_priv, i) {
2029                         if (ring->default_context != ctx)
2030                                 i915_dump_lrc_obj(m, ring,
2031                                                   ctx->engine[i].state);
2032                 }
2033         }
2034
2035         mutex_unlock(&dev->struct_mutex);
2036
2037         return 0;
2038 }
2039
2040 static int i915_execlists(struct seq_file *m, void *data)
2041 {
2042         struct drm_info_node *node = (struct drm_info_node *)m->private;
2043         struct drm_device *dev = node->minor->dev;
2044         struct drm_i915_private *dev_priv = dev->dev_private;
2045         struct intel_engine_cs *ring;
2046         u32 status_pointer;
2047         u8 read_pointer;
2048         u8 write_pointer;
2049         u32 status;
2050         u32 ctx_id;
2051         struct list_head *cursor;
2052         int ring_id, i;
2053         int ret;
2054
2055         if (!i915.enable_execlists) {
2056                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2057                 return 0;
2058         }
2059
2060         ret = mutex_lock_interruptible(&dev->struct_mutex);
2061         if (ret)
2062                 return ret;
2063
2064         intel_runtime_pm_get(dev_priv);
2065
2066         for_each_ring(ring, dev_priv, ring_id) {
2067                 struct drm_i915_gem_request *head_req = NULL;
2068                 int count = 0;
2069                 unsigned long flags;
2070
2071                 seq_printf(m, "%s\n", ring->name);
2072
2073                 status = I915_READ(RING_EXECLIST_STATUS(ring));
2074                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2075                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2076                            status, ctx_id);
2077
2078                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2079                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2080
2081                 read_pointer = ring->next_context_status_buffer;
2082                 write_pointer = status_pointer & 0x07;
2083                 if (read_pointer > write_pointer)
2084                         write_pointer += 6;
2085                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2086                            read_pointer, write_pointer);
2087
2088                 for (i = 0; i < 6; i++) {
2089                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2090                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2091
2092                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2093                                    i, status, ctx_id);
2094                 }
2095
2096                 spin_lock_irqsave(&ring->execlist_lock, flags);
2097                 list_for_each(cursor, &ring->execlist_queue)
2098                         count++;
2099                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2100                                 struct drm_i915_gem_request, execlist_link);
2101                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2102
2103                 seq_printf(m, "\t%d requests in queue\n", count);
2104                 if (head_req) {
2105                         struct drm_i915_gem_object *ctx_obj;
2106
2107                         ctx_obj = head_req->ctx->engine[ring_id].state;
2108                         seq_printf(m, "\tHead request id: %u\n",
2109                                    intel_execlists_ctx_id(ctx_obj));
2110                         seq_printf(m, "\tHead request tail: %u\n",
2111                                    head_req->tail);
2112                 }
2113
2114                 seq_putc(m, '\n');
2115         }
2116
2117         intel_runtime_pm_put(dev_priv);
2118         mutex_unlock(&dev->struct_mutex);
2119
2120         return 0;
2121 }
2122
2123 static const char *swizzle_string(unsigned swizzle)
2124 {
2125         switch (swizzle) {
2126         case I915_BIT_6_SWIZZLE_NONE:
2127                 return "none";
2128         case I915_BIT_6_SWIZZLE_9:
2129                 return "bit9";
2130         case I915_BIT_6_SWIZZLE_9_10:
2131                 return "bit9/bit10";
2132         case I915_BIT_6_SWIZZLE_9_11:
2133                 return "bit9/bit11";
2134         case I915_BIT_6_SWIZZLE_9_10_11:
2135                 return "bit9/bit10/bit11";
2136         case I915_BIT_6_SWIZZLE_9_17:
2137                 return "bit9/bit17";
2138         case I915_BIT_6_SWIZZLE_9_10_17:
2139                 return "bit9/bit10/bit17";
2140         case I915_BIT_6_SWIZZLE_UNKNOWN:
2141                 return "unknown";
2142         }
2143
2144         return "bug";
2145 }
2146
2147 static int i915_swizzle_info(struct seq_file *m, void *data)
2148 {
2149         struct drm_info_node *node = m->private;
2150         struct drm_device *dev = node->minor->dev;
2151         struct drm_i915_private *dev_priv = dev->dev_private;
2152         int ret;
2153
2154         ret = mutex_lock_interruptible(&dev->struct_mutex);
2155         if (ret)
2156                 return ret;
2157         intel_runtime_pm_get(dev_priv);
2158
2159         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2160                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2161         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2162                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2163
2164         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2165                 seq_printf(m, "DDC = 0x%08x\n",
2166                            I915_READ(DCC));
2167                 seq_printf(m, "DDC2 = 0x%08x\n",
2168                            I915_READ(DCC2));
2169                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2170                            I915_READ16(C0DRB3));
2171                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2172                            I915_READ16(C1DRB3));
2173         } else if (INTEL_INFO(dev)->gen >= 6) {
2174                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2175                            I915_READ(MAD_DIMM_C0));
2176                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2177                            I915_READ(MAD_DIMM_C1));
2178                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2179                            I915_READ(MAD_DIMM_C2));
2180                 seq_printf(m, "TILECTL = 0x%08x\n",
2181                            I915_READ(TILECTL));
2182                 if (INTEL_INFO(dev)->gen >= 8)
2183                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2184                                    I915_READ(GAMTARBMODE));
2185                 else
2186                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2187                                    I915_READ(ARB_MODE));
2188                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2189                            I915_READ(DISP_ARB_CTL));
2190         }
2191
2192         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2193                 seq_puts(m, "L-shaped memory detected\n");
2194
2195         intel_runtime_pm_put(dev_priv);
2196         mutex_unlock(&dev->struct_mutex);
2197
2198         return 0;
2199 }
2200
2201 static int per_file_ctx(int id, void *ptr, void *data)
2202 {
2203         struct intel_context *ctx = ptr;
2204         struct seq_file *m = data;
2205         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2206
2207         if (!ppgtt) {
2208                 seq_printf(m, "  no ppgtt for context %d\n",
2209                            ctx->user_handle);
2210                 return 0;
2211         }
2212
2213         if (i915_gem_context_is_default(ctx))
2214                 seq_puts(m, "  default context:\n");
2215         else
2216                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2217         ppgtt->debug_dump(ppgtt, m);
2218
2219         return 0;
2220 }
2221
2222 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2223 {
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225         struct intel_engine_cs *ring;
2226         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2227         int unused, i;
2228
2229         if (!ppgtt)
2230                 return;
2231
2232         for_each_ring(ring, dev_priv, unused) {
2233                 seq_printf(m, "%s\n", ring->name);
2234                 for (i = 0; i < 4; i++) {
2235                         u32 offset = 0x270 + i * 8;
2236                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2237                         pdp <<= 32;
2238                         pdp |= I915_READ(ring->mmio_base + offset);
2239                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2240                 }
2241         }
2242 }
2243
2244 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2245 {
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247         struct intel_engine_cs *ring;
2248         int i;
2249
2250         if (INTEL_INFO(dev)->gen == 6)
2251                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2252
2253         for_each_ring(ring, dev_priv, i) {
2254                 seq_printf(m, "%s\n", ring->name);
2255                 if (INTEL_INFO(dev)->gen == 7)
2256                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2257                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2258                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2259                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2260         }
2261         if (dev_priv->mm.aliasing_ppgtt) {
2262                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2263
2264                 seq_puts(m, "aliasing PPGTT:\n");
2265                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2266
2267                 ppgtt->debug_dump(ppgtt, m);
2268         }
2269
2270         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2271 }
2272
2273 static int i915_ppgtt_info(struct seq_file *m, void *data)
2274 {
2275         struct drm_info_node *node = m->private;
2276         struct drm_device *dev = node->minor->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct drm_file *file;
2279
2280         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2281         if (ret)
2282                 return ret;
2283         intel_runtime_pm_get(dev_priv);
2284
2285         if (INTEL_INFO(dev)->gen >= 8)
2286                 gen8_ppgtt_info(m, dev);
2287         else if (INTEL_INFO(dev)->gen >= 6)
2288                 gen6_ppgtt_info(m, dev);
2289
2290         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2291                 struct drm_i915_file_private *file_priv = file->driver_priv;
2292
2293                 seq_printf(m, "\nproc: %s\n",
2294                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2295                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2296                              (void *)(unsigned long)m);
2297         }
2298
2299         intel_runtime_pm_put(dev_priv);
2300         mutex_unlock(&dev->struct_mutex);
2301
2302         return 0;
2303 }
2304
2305 static int count_irq_waiters(struct drm_i915_private *i915)
2306 {
2307         struct intel_engine_cs *ring;
2308         int count = 0;
2309         int i;
2310
2311         for_each_ring(ring, i915, i)
2312                 count += ring->irq_refcount;
2313
2314         return count;
2315 }
2316
2317 static int i915_rps_boost_info(struct seq_file *m, void *data)
2318 {
2319         struct drm_info_node *node = m->private;
2320         struct drm_device *dev = node->minor->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct drm_file *file;
2323
2324         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2325         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2326         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2327         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2328                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2329                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2330                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2331                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2332                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2333         spin_lock(&dev_priv->rps.client_lock);
2334         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2335                 struct drm_i915_file_private *file_priv = file->driver_priv;
2336                 struct task_struct *task;
2337
2338                 rcu_read_lock();
2339                 task = pid_task(file->pid, PIDTYPE_PID);
2340                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2341                            task ? task->comm : "<unknown>",
2342                            task ? task->pid : -1,
2343                            file_priv->rps.boosts,
2344                            list_empty(&file_priv->rps.link) ? "" : ", active");
2345                 rcu_read_unlock();
2346         }
2347         seq_printf(m, "Semaphore boosts: %d%s\n",
2348                    dev_priv->rps.semaphores.boosts,
2349                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2350         seq_printf(m, "MMIO flip boosts: %d%s\n",
2351                    dev_priv->rps.mmioflips.boosts,
2352                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2353         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2354         spin_unlock(&dev_priv->rps.client_lock);
2355
2356         return 0;
2357 }
2358
2359 static int i915_llc(struct seq_file *m, void *data)
2360 {
2361         struct drm_info_node *node = m->private;
2362         struct drm_device *dev = node->minor->dev;
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364
2365         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2366         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2367         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2368
2369         return 0;
2370 }
2371
2372 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2373 {
2374         struct drm_info_node *node = m->private;
2375         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2376         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2377         u32 tmp, i;
2378
2379         if (!HAS_GUC_UCODE(dev_priv->dev))
2380                 return 0;
2381
2382         seq_printf(m, "GuC firmware status:\n");
2383         seq_printf(m, "\tpath: %s\n",
2384                 guc_fw->guc_fw_path);
2385         seq_printf(m, "\tfetch: %s\n",
2386                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2387         seq_printf(m, "\tload: %s\n",
2388                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2389         seq_printf(m, "\tversion wanted: %d.%d\n",
2390                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2391         seq_printf(m, "\tversion found: %d.%d\n",
2392                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2393
2394         tmp = I915_READ(GUC_STATUS);
2395
2396         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2397         seq_printf(m, "\tBootrom status = 0x%x\n",
2398                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2399         seq_printf(m, "\tuKernel status = 0x%x\n",
2400                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2401         seq_printf(m, "\tMIA Core status = 0x%x\n",
2402                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2403         seq_puts(m, "\nScratch registers:\n");
2404         for (i = 0; i < 16; i++)
2405                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2406
2407         return 0;
2408 }
2409
2410 static void i915_guc_client_info(struct seq_file *m,
2411                                  struct drm_i915_private *dev_priv,
2412                                  struct i915_guc_client *client)
2413 {
2414         struct intel_engine_cs *ring;
2415         uint64_t tot = 0;
2416         uint32_t i;
2417
2418         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2419                 client->priority, client->ctx_index, client->proc_desc_offset);
2420         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2421                 client->doorbell_id, client->doorbell_offset, client->cookie);
2422         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2423                 client->wq_size, client->wq_offset, client->wq_tail);
2424
2425         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2426         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2427         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2428
2429         for_each_ring(ring, dev_priv, i) {
2430                 seq_printf(m, "\tSubmissions: %llu %s\n",
2431                                 client->submissions[i],
2432                                 ring->name);
2433                 tot += client->submissions[i];
2434         }
2435         seq_printf(m, "\tTotal: %llu\n", tot);
2436 }
2437
2438 static int i915_guc_info(struct seq_file *m, void *data)
2439 {
2440         struct drm_info_node *node = m->private;
2441         struct drm_device *dev = node->minor->dev;
2442         struct drm_i915_private *dev_priv = dev->dev_private;
2443         struct intel_guc guc;
2444         struct i915_guc_client client = {};
2445         struct intel_engine_cs *ring;
2446         enum intel_ring_id i;
2447         u64 total = 0;
2448
2449         if (!HAS_GUC_SCHED(dev_priv->dev))
2450                 return 0;
2451
2452         /* Take a local copy of the GuC data, so we can dump it at leisure */
2453         spin_lock(&dev_priv->guc.host2guc_lock);
2454         guc = dev_priv->guc;
2455         if (guc.execbuf_client) {
2456                 spin_lock(&guc.execbuf_client->wq_lock);
2457                 client = *guc.execbuf_client;
2458                 spin_unlock(&guc.execbuf_client->wq_lock);
2459         }
2460         spin_unlock(&dev_priv->guc.host2guc_lock);
2461
2462         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2463         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2464         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2465         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2466         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2467
2468         seq_printf(m, "\nGuC submissions:\n");
2469         for_each_ring(ring, dev_priv, i) {
2470                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2471                         ring->name, guc.submissions[i],
2472                         guc.last_seqno[i], guc.last_seqno[i]);
2473                 total += guc.submissions[i];
2474         }
2475         seq_printf(m, "\t%s: %llu\n", "Total", total);
2476
2477         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2478         i915_guc_client_info(m, dev_priv, &client);
2479
2480         /* Add more as required ... */
2481
2482         return 0;
2483 }
2484
2485 static int i915_guc_log_dump(struct seq_file *m, void *data)
2486 {
2487         struct drm_info_node *node = m->private;
2488         struct drm_device *dev = node->minor->dev;
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2491         u32 *log;
2492         int i = 0, pg;
2493
2494         if (!log_obj)
2495                 return 0;
2496
2497         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2498                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2499
2500                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2501                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2502                                    *(log + i), *(log + i + 1),
2503                                    *(log + i + 2), *(log + i + 3));
2504
2505                 kunmap_atomic(log);
2506         }
2507
2508         seq_putc(m, '\n');
2509
2510         return 0;
2511 }
2512
2513 static int i915_edp_psr_status(struct seq_file *m, void *data)
2514 {
2515         struct drm_info_node *node = m->private;
2516         struct drm_device *dev = node->minor->dev;
2517         struct drm_i915_private *dev_priv = dev->dev_private;
2518         u32 psrperf = 0;
2519         u32 stat[3];
2520         enum pipe pipe;
2521         bool enabled = false;
2522
2523         if (!HAS_PSR(dev)) {
2524                 seq_puts(m, "PSR not supported\n");
2525                 return 0;
2526         }
2527
2528         intel_runtime_pm_get(dev_priv);
2529
2530         mutex_lock(&dev_priv->psr.lock);
2531         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2532         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2533         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2534         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2535         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2536                    dev_priv->psr.busy_frontbuffer_bits);
2537         seq_printf(m, "Re-enable work scheduled: %s\n",
2538                    yesno(work_busy(&dev_priv->psr.work.work)));
2539
2540         if (HAS_DDI(dev))
2541                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2542         else {
2543                 for_each_pipe(dev_priv, pipe) {
2544                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2545                                 VLV_EDP_PSR_CURR_STATE_MASK;
2546                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2547                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2548                                 enabled = true;
2549                 }
2550         }
2551         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2552
2553         if (!HAS_DDI(dev))
2554                 for_each_pipe(dev_priv, pipe) {
2555                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2556                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2557                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2558                 }
2559         seq_puts(m, "\n");
2560
2561         /* CHV PSR has no kind of performance counter */
2562         if (HAS_DDI(dev)) {
2563                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2564                         EDP_PSR_PERF_CNT_MASK;
2565
2566                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2567         }
2568         mutex_unlock(&dev_priv->psr.lock);
2569
2570         intel_runtime_pm_put(dev_priv);
2571         return 0;
2572 }
2573
2574 static int i915_sink_crc(struct seq_file *m, void *data)
2575 {
2576         struct drm_info_node *node = m->private;
2577         struct drm_device *dev = node->minor->dev;
2578         struct intel_encoder *encoder;
2579         struct intel_connector *connector;
2580         struct intel_dp *intel_dp = NULL;
2581         int ret;
2582         u8 crc[6];
2583
2584         drm_modeset_lock_all(dev);
2585         for_each_intel_connector(dev, connector) {
2586
2587                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2588                         continue;
2589
2590                 if (!connector->base.encoder)
2591                         continue;
2592
2593                 encoder = to_intel_encoder(connector->base.encoder);
2594                 if (encoder->type != INTEL_OUTPUT_EDP)
2595                         continue;
2596
2597                 intel_dp = enc_to_intel_dp(&encoder->base);
2598
2599                 ret = intel_dp_sink_crc(intel_dp, crc);
2600                 if (ret)
2601                         goto out;
2602
2603                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2604                            crc[0], crc[1], crc[2],
2605                            crc[3], crc[4], crc[5]);
2606                 goto out;
2607         }
2608         ret = -ENODEV;
2609 out:
2610         drm_modeset_unlock_all(dev);
2611         return ret;
2612 }
2613
2614 static int i915_energy_uJ(struct seq_file *m, void *data)
2615 {
2616         struct drm_info_node *node = m->private;
2617         struct drm_device *dev = node->minor->dev;
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         u64 power;
2620         u32 units;
2621
2622         if (INTEL_INFO(dev)->gen < 6)
2623                 return -ENODEV;
2624
2625         intel_runtime_pm_get(dev_priv);
2626
2627         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2628         power = (power & 0x1f00) >> 8;
2629         units = 1000000 / (1 << power); /* convert to uJ */
2630         power = I915_READ(MCH_SECP_NRG_STTS);
2631         power *= units;
2632
2633         intel_runtime_pm_put(dev_priv);
2634
2635         seq_printf(m, "%llu", (long long unsigned)power);
2636
2637         return 0;
2638 }
2639
2640 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2641 {
2642         struct drm_info_node *node = m->private;
2643         struct drm_device *dev = node->minor->dev;
2644         struct drm_i915_private *dev_priv = dev->dev_private;
2645
2646         if (!HAS_RUNTIME_PM(dev)) {
2647                 seq_puts(m, "not supported\n");
2648                 return 0;
2649         }
2650
2651         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2652         seq_printf(m, "IRQs disabled: %s\n",
2653                    yesno(!intel_irqs_enabled(dev_priv)));
2654 #ifdef CONFIG_PM
2655         seq_printf(m, "Usage count: %d\n",
2656                    atomic_read(&dev->dev->power.usage_count));
2657 #else
2658         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2659 #endif
2660
2661         return 0;
2662 }
2663
2664 static const char *power_domain_str(enum intel_display_power_domain domain)
2665 {
2666         switch (domain) {
2667         case POWER_DOMAIN_PIPE_A:
2668                 return "PIPE_A";
2669         case POWER_DOMAIN_PIPE_B:
2670                 return "PIPE_B";
2671         case POWER_DOMAIN_PIPE_C:
2672                 return "PIPE_C";
2673         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2674                 return "PIPE_A_PANEL_FITTER";
2675         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2676                 return "PIPE_B_PANEL_FITTER";
2677         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2678                 return "PIPE_C_PANEL_FITTER";
2679         case POWER_DOMAIN_TRANSCODER_A:
2680                 return "TRANSCODER_A";
2681         case POWER_DOMAIN_TRANSCODER_B:
2682                 return "TRANSCODER_B";
2683         case POWER_DOMAIN_TRANSCODER_C:
2684                 return "TRANSCODER_C";
2685         case POWER_DOMAIN_TRANSCODER_EDP:
2686                 return "TRANSCODER_EDP";
2687         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2688                 return "PORT_DDI_A_2_LANES";
2689         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2690                 return "PORT_DDI_A_4_LANES";
2691         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2692                 return "PORT_DDI_B_2_LANES";
2693         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2694                 return "PORT_DDI_B_4_LANES";
2695         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2696                 return "PORT_DDI_C_2_LANES";
2697         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2698                 return "PORT_DDI_C_4_LANES";
2699         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2700                 return "PORT_DDI_D_2_LANES";
2701         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2702                 return "PORT_DDI_D_4_LANES";
2703         case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2704                 return "PORT_DDI_E_2_LANES";
2705         case POWER_DOMAIN_PORT_DSI:
2706                 return "PORT_DSI";
2707         case POWER_DOMAIN_PORT_CRT:
2708                 return "PORT_CRT";
2709         case POWER_DOMAIN_PORT_OTHER:
2710                 return "PORT_OTHER";
2711         case POWER_DOMAIN_VGA:
2712                 return "VGA";
2713         case POWER_DOMAIN_AUDIO:
2714                 return "AUDIO";
2715         case POWER_DOMAIN_PLLS:
2716                 return "PLLS";
2717         case POWER_DOMAIN_AUX_A:
2718                 return "AUX_A";
2719         case POWER_DOMAIN_AUX_B:
2720                 return "AUX_B";
2721         case POWER_DOMAIN_AUX_C:
2722                 return "AUX_C";
2723         case POWER_DOMAIN_AUX_D:
2724                 return "AUX_D";
2725         case POWER_DOMAIN_INIT:
2726                 return "INIT";
2727         default:
2728                 MISSING_CASE(domain);
2729                 return "?";
2730         }
2731 }
2732
2733 static int i915_power_domain_info(struct seq_file *m, void *unused)
2734 {
2735         struct drm_info_node *node = m->private;
2736         struct drm_device *dev = node->minor->dev;
2737         struct drm_i915_private *dev_priv = dev->dev_private;
2738         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2739         int i;
2740
2741         mutex_lock(&power_domains->lock);
2742
2743         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2744         for (i = 0; i < power_domains->power_well_count; i++) {
2745                 struct i915_power_well *power_well;
2746                 enum intel_display_power_domain power_domain;
2747
2748                 power_well = &power_domains->power_wells[i];
2749                 seq_printf(m, "%-25s %d\n", power_well->name,
2750                            power_well->count);
2751
2752                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2753                      power_domain++) {
2754                         if (!(BIT(power_domain) & power_well->domains))
2755                                 continue;
2756
2757                         seq_printf(m, "  %-23s %d\n",
2758                                  power_domain_str(power_domain),
2759                                  power_domains->domain_use_count[power_domain]);
2760                 }
2761         }
2762
2763         mutex_unlock(&power_domains->lock);
2764
2765         return 0;
2766 }
2767
2768 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2769                                  struct drm_display_mode *mode)
2770 {
2771         int i;
2772
2773         for (i = 0; i < tabs; i++)
2774                 seq_putc(m, '\t');
2775
2776         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2777                    mode->base.id, mode->name,
2778                    mode->vrefresh, mode->clock,
2779                    mode->hdisplay, mode->hsync_start,
2780                    mode->hsync_end, mode->htotal,
2781                    mode->vdisplay, mode->vsync_start,
2782                    mode->vsync_end, mode->vtotal,
2783                    mode->type, mode->flags);
2784 }
2785
2786 static void intel_encoder_info(struct seq_file *m,
2787                                struct intel_crtc *intel_crtc,
2788                                struct intel_encoder *intel_encoder)
2789 {
2790         struct drm_info_node *node = m->private;
2791         struct drm_device *dev = node->minor->dev;
2792         struct drm_crtc *crtc = &intel_crtc->base;
2793         struct intel_connector *intel_connector;
2794         struct drm_encoder *encoder;
2795
2796         encoder = &intel_encoder->base;
2797         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2798                    encoder->base.id, encoder->name);
2799         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2800                 struct drm_connector *connector = &intel_connector->base;
2801                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2802                            connector->base.id,
2803                            connector->name,
2804                            drm_get_connector_status_name(connector->status));
2805                 if (connector->status == connector_status_connected) {
2806                         struct drm_display_mode *mode = &crtc->mode;
2807                         seq_printf(m, ", mode:\n");
2808                         intel_seq_print_mode(m, 2, mode);
2809                 } else {
2810                         seq_putc(m, '\n');
2811                 }
2812         }
2813 }
2814
2815 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2816 {
2817         struct drm_info_node *node = m->private;
2818         struct drm_device *dev = node->minor->dev;
2819         struct drm_crtc *crtc = &intel_crtc->base;
2820         struct intel_encoder *intel_encoder;
2821
2822         if (crtc->primary->fb)
2823                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2824                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2825                            crtc->primary->fb->width, crtc->primary->fb->height);
2826         else
2827                 seq_puts(m, "\tprimary plane disabled\n");
2828         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2829                 intel_encoder_info(m, intel_crtc, intel_encoder);
2830 }
2831
2832 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2833 {
2834         struct drm_display_mode *mode = panel->fixed_mode;
2835
2836         seq_printf(m, "\tfixed mode:\n");
2837         intel_seq_print_mode(m, 2, mode);
2838 }
2839
2840 static void intel_dp_info(struct seq_file *m,
2841                           struct intel_connector *intel_connector)
2842 {
2843         struct intel_encoder *intel_encoder = intel_connector->encoder;
2844         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2845
2846         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2847         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2848                    "no");
2849         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2850                 intel_panel_info(m, &intel_connector->panel);
2851 }
2852
2853 static void intel_hdmi_info(struct seq_file *m,
2854                             struct intel_connector *intel_connector)
2855 {
2856         struct intel_encoder *intel_encoder = intel_connector->encoder;
2857         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2858
2859         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2860                    "no");
2861 }
2862
2863 static void intel_lvds_info(struct seq_file *m,
2864                             struct intel_connector *intel_connector)
2865 {
2866         intel_panel_info(m, &intel_connector->panel);
2867 }
2868
2869 static void intel_connector_info(struct seq_file *m,
2870                                  struct drm_connector *connector)
2871 {
2872         struct intel_connector *intel_connector = to_intel_connector(connector);
2873         struct intel_encoder *intel_encoder = intel_connector->encoder;
2874         struct drm_display_mode *mode;
2875
2876         seq_printf(m, "connector %d: type %s, status: %s\n",
2877                    connector->base.id, connector->name,
2878                    drm_get_connector_status_name(connector->status));
2879         if (connector->status == connector_status_connected) {
2880                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2881                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2882                            connector->display_info.width_mm,
2883                            connector->display_info.height_mm);
2884                 seq_printf(m, "\tsubpixel order: %s\n",
2885                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2886                 seq_printf(m, "\tCEA rev: %d\n",
2887                            connector->display_info.cea_rev);
2888         }
2889         if (intel_encoder) {
2890                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2891                     intel_encoder->type == INTEL_OUTPUT_EDP)
2892                         intel_dp_info(m, intel_connector);
2893                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2894                         intel_hdmi_info(m, intel_connector);
2895                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2896                         intel_lvds_info(m, intel_connector);
2897         }
2898
2899         seq_printf(m, "\tmodes:\n");
2900         list_for_each_entry(mode, &connector->modes, head)
2901                 intel_seq_print_mode(m, 2, mode);
2902 }
2903
2904 static bool cursor_active(struct drm_device *dev, int pipe)
2905 {
2906         struct drm_i915_private *dev_priv = dev->dev_private;
2907         u32 state;
2908
2909         if (IS_845G(dev) || IS_I865G(dev))
2910                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2911         else
2912                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2913
2914         return state;
2915 }
2916
2917 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2918 {
2919         struct drm_i915_private *dev_priv = dev->dev_private;
2920         u32 pos;
2921
2922         pos = I915_READ(CURPOS(pipe));
2923
2924         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2925         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2926                 *x = -*x;
2927
2928         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2929         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2930                 *y = -*y;
2931
2932         return cursor_active(dev, pipe);
2933 }
2934
2935 static int i915_display_info(struct seq_file *m, void *unused)
2936 {
2937         struct drm_info_node *node = m->private;
2938         struct drm_device *dev = node->minor->dev;
2939         struct drm_i915_private *dev_priv = dev->dev_private;
2940         struct intel_crtc *crtc;
2941         struct drm_connector *connector;
2942
2943         intel_runtime_pm_get(dev_priv);
2944         drm_modeset_lock_all(dev);
2945         seq_printf(m, "CRTC info\n");
2946         seq_printf(m, "---------\n");
2947         for_each_intel_crtc(dev, crtc) {
2948                 bool active;
2949                 struct intel_crtc_state *pipe_config;
2950                 int x, y;
2951
2952                 pipe_config = to_intel_crtc_state(crtc->base.state);
2953
2954                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2955                            crtc->base.base.id, pipe_name(crtc->pipe),
2956                            yesno(pipe_config->base.active),
2957                            pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2958                 if (pipe_config->base.active) {
2959                         intel_crtc_info(m, crtc);
2960
2961                         active = cursor_position(dev, crtc->pipe, &x, &y);
2962                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2963                                    yesno(crtc->cursor_base),
2964                                    x, y, crtc->base.cursor->state->crtc_w,
2965                                    crtc->base.cursor->state->crtc_h,
2966                                    crtc->cursor_addr, yesno(active));
2967                 }
2968
2969                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2970                            yesno(!crtc->cpu_fifo_underrun_disabled),
2971                            yesno(!crtc->pch_fifo_underrun_disabled));
2972         }
2973
2974         seq_printf(m, "\n");
2975         seq_printf(m, "Connector info\n");
2976         seq_printf(m, "--------------\n");
2977         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2978                 intel_connector_info(m, connector);
2979         }
2980         drm_modeset_unlock_all(dev);
2981         intel_runtime_pm_put(dev_priv);
2982
2983         return 0;
2984 }
2985
2986 static int i915_semaphore_status(struct seq_file *m, void *unused)
2987 {
2988         struct drm_info_node *node = (struct drm_info_node *) m->private;
2989         struct drm_device *dev = node->minor->dev;
2990         struct drm_i915_private *dev_priv = dev->dev_private;
2991         struct intel_engine_cs *ring;
2992         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2993         int i, j, ret;
2994
2995         if (!i915_semaphore_is_enabled(dev)) {
2996                 seq_puts(m, "Semaphores are disabled\n");
2997                 return 0;
2998         }
2999
3000         ret = mutex_lock_interruptible(&dev->struct_mutex);
3001         if (ret)
3002                 return ret;
3003         intel_runtime_pm_get(dev_priv);
3004
3005         if (IS_BROADWELL(dev)) {
3006                 struct page *page;
3007                 uint64_t *seqno;
3008
3009                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3010
3011                 seqno = (uint64_t *)kmap_atomic(page);
3012                 for_each_ring(ring, dev_priv, i) {
3013                         uint64_t offset;
3014
3015                         seq_printf(m, "%s\n", ring->name);
3016
3017                         seq_puts(m, "  Last signal:");
3018                         for (j = 0; j < num_rings; j++) {
3019                                 offset = i * I915_NUM_RINGS + j;
3020                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3021                                            seqno[offset], offset * 8);
3022                         }
3023                         seq_putc(m, '\n');
3024
3025                         seq_puts(m, "  Last wait:  ");
3026                         for (j = 0; j < num_rings; j++) {
3027                                 offset = i + (j * I915_NUM_RINGS);
3028                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3029                                            seqno[offset], offset * 8);
3030                         }
3031                         seq_putc(m, '\n');
3032
3033                 }
3034                 kunmap_atomic(seqno);
3035         } else {
3036                 seq_puts(m, "  Last signal:");
3037                 for_each_ring(ring, dev_priv, i)
3038                         for (j = 0; j < num_rings; j++)
3039                                 seq_printf(m, "0x%08x\n",
3040                                            I915_READ(ring->semaphore.mbox.signal[j]));
3041                 seq_putc(m, '\n');
3042         }
3043
3044         seq_puts(m, "\nSync seqno:\n");
3045         for_each_ring(ring, dev_priv, i) {
3046                 for (j = 0; j < num_rings; j++) {
3047                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
3048                 }
3049                 seq_putc(m, '\n');
3050         }
3051         seq_putc(m, '\n');
3052
3053         intel_runtime_pm_put(dev_priv);
3054         mutex_unlock(&dev->struct_mutex);
3055         return 0;
3056 }
3057
3058 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3059 {
3060         struct drm_info_node *node = (struct drm_info_node *) m->private;
3061         struct drm_device *dev = node->minor->dev;
3062         struct drm_i915_private *dev_priv = dev->dev_private;
3063         int i;
3064
3065         drm_modeset_lock_all(dev);
3066         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3067                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3068
3069                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3070                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3071                            pll->config.crtc_mask, pll->active, yesno(pll->on));
3072                 seq_printf(m, " tracked hardware state:\n");
3073                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3074                 seq_printf(m, " dpll_md: 0x%08x\n",
3075                            pll->config.hw_state.dpll_md);
3076                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3077                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3078                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3079         }
3080         drm_modeset_unlock_all(dev);
3081
3082         return 0;
3083 }
3084
3085 static int i915_wa_registers(struct seq_file *m, void *unused)
3086 {
3087         int i;
3088         int ret;
3089         struct drm_info_node *node = (struct drm_info_node *) m->private;
3090         struct drm_device *dev = node->minor->dev;
3091         struct drm_i915_private *dev_priv = dev->dev_private;
3092
3093         ret = mutex_lock_interruptible(&dev->struct_mutex);
3094         if (ret)
3095                 return ret;
3096
3097         intel_runtime_pm_get(dev_priv);
3098
3099         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3100         for (i = 0; i < dev_priv->workarounds.count; ++i) {
3101                 u32 addr, mask, value, read;
3102                 bool ok;
3103
3104                 addr = dev_priv->workarounds.reg[i].addr;
3105                 mask = dev_priv->workarounds.reg[i].mask;
3106                 value = dev_priv->workarounds.reg[i].value;
3107                 read = I915_READ(addr);
3108                 ok = (value & mask) == (read & mask);
3109                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3110                            addr, value, mask, read, ok ? "OK" : "FAIL");
3111         }
3112
3113         intel_runtime_pm_put(dev_priv);
3114         mutex_unlock(&dev->struct_mutex);
3115
3116         return 0;
3117 }
3118
3119 static int i915_ddb_info(struct seq_file *m, void *unused)
3120 {
3121         struct drm_info_node *node = m->private;
3122         struct drm_device *dev = node->minor->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct skl_ddb_allocation *ddb;
3125         struct skl_ddb_entry *entry;
3126         enum pipe pipe;
3127         int plane;
3128
3129         if (INTEL_INFO(dev)->gen < 9)
3130                 return 0;
3131
3132         drm_modeset_lock_all(dev);
3133
3134         ddb = &dev_priv->wm.skl_hw.ddb;
3135
3136         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3137
3138         for_each_pipe(dev_priv, pipe) {
3139                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3140
3141                 for_each_plane(dev_priv, pipe, plane) {
3142                         entry = &ddb->plane[pipe][plane];
3143                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3144                                    entry->start, entry->end,
3145                                    skl_ddb_entry_size(entry));
3146                 }
3147
3148                 entry = &ddb->cursor[pipe];
3149                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3150                            entry->end, skl_ddb_entry_size(entry));
3151         }
3152
3153         drm_modeset_unlock_all(dev);
3154
3155         return 0;
3156 }
3157
3158 static void drrs_status_per_crtc(struct seq_file *m,
3159                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3160 {
3161         struct intel_encoder *intel_encoder;
3162         struct drm_i915_private *dev_priv = dev->dev_private;
3163         struct i915_drrs *drrs = &dev_priv->drrs;
3164         int vrefresh = 0;
3165
3166         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3167                 /* Encoder connected on this CRTC */
3168                 switch (intel_encoder->type) {
3169                 case INTEL_OUTPUT_EDP:
3170                         seq_puts(m, "eDP:\n");
3171                         break;
3172                 case INTEL_OUTPUT_DSI:
3173                         seq_puts(m, "DSI:\n");
3174                         break;
3175                 case INTEL_OUTPUT_HDMI:
3176                         seq_puts(m, "HDMI:\n");
3177                         break;
3178                 case INTEL_OUTPUT_DISPLAYPORT:
3179                         seq_puts(m, "DP:\n");
3180                         break;
3181                 default:
3182                         seq_printf(m, "Other encoder (id=%d).\n",
3183                                                 intel_encoder->type);
3184                         return;
3185                 }
3186         }
3187
3188         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3189                 seq_puts(m, "\tVBT: DRRS_type: Static");
3190         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3191                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3192         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3193                 seq_puts(m, "\tVBT: DRRS_type: None");
3194         else
3195                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3196
3197         seq_puts(m, "\n\n");
3198
3199         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3200                 struct intel_panel *panel;
3201
3202                 mutex_lock(&drrs->mutex);
3203                 /* DRRS Supported */
3204                 seq_puts(m, "\tDRRS Supported: Yes\n");
3205
3206                 /* disable_drrs() will make drrs->dp NULL */
3207                 if (!drrs->dp) {
3208                         seq_puts(m, "Idleness DRRS: Disabled");
3209                         mutex_unlock(&drrs->mutex);
3210                         return;
3211                 }
3212
3213                 panel = &drrs->dp->attached_connector->panel;
3214                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3215                                         drrs->busy_frontbuffer_bits);
3216
3217                 seq_puts(m, "\n\t\t");
3218                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3219                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3220                         vrefresh = panel->fixed_mode->vrefresh;
3221                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3222                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3223                         vrefresh = panel->downclock_mode->vrefresh;
3224                 } else {
3225                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3226                                                 drrs->refresh_rate_type);
3227                         mutex_unlock(&drrs->mutex);
3228                         return;
3229                 }
3230                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3231
3232                 seq_puts(m, "\n\t\t");
3233                 mutex_unlock(&drrs->mutex);
3234         } else {
3235                 /* DRRS not supported. Print the VBT parameter*/
3236                 seq_puts(m, "\tDRRS Supported : No");
3237         }
3238         seq_puts(m, "\n");
3239 }
3240
3241 static int i915_drrs_status(struct seq_file *m, void *unused)
3242 {
3243         struct drm_info_node *node = m->private;
3244         struct drm_device *dev = node->minor->dev;
3245         struct intel_crtc *intel_crtc;
3246         int active_crtc_cnt = 0;
3247
3248         for_each_intel_crtc(dev, intel_crtc) {
3249                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3250
3251                 if (intel_crtc->base.state->active) {
3252                         active_crtc_cnt++;
3253                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3254
3255                         drrs_status_per_crtc(m, dev, intel_crtc);
3256                 }
3257
3258                 drm_modeset_unlock(&intel_crtc->base.mutex);
3259         }
3260
3261         if (!active_crtc_cnt)
3262                 seq_puts(m, "No active crtc found\n");
3263
3264         return 0;
3265 }
3266
3267 struct pipe_crc_info {
3268         const char *name;
3269         struct drm_device *dev;
3270         enum pipe pipe;
3271 };
3272
3273 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3274 {
3275         struct drm_info_node *node = (struct drm_info_node *) m->private;
3276         struct drm_device *dev = node->minor->dev;
3277         struct drm_encoder *encoder;
3278         struct intel_encoder *intel_encoder;
3279         struct intel_digital_port *intel_dig_port;
3280         drm_modeset_lock_all(dev);
3281         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3282                 intel_encoder = to_intel_encoder(encoder);
3283                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3284                         continue;
3285                 intel_dig_port = enc_to_dig_port(encoder);
3286                 if (!intel_dig_port->dp.can_mst)
3287                         continue;
3288
3289                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3290         }
3291         drm_modeset_unlock_all(dev);
3292         return 0;
3293 }
3294
3295 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3296 {
3297         struct pipe_crc_info *info = inode->i_private;
3298         struct drm_i915_private *dev_priv = info->dev->dev_private;
3299         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3300
3301         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3302                 return -ENODEV;
3303
3304         spin_lock_irq(&pipe_crc->lock);
3305
3306         if (pipe_crc->opened) {
3307                 spin_unlock_irq(&pipe_crc->lock);
3308                 return -EBUSY; /* already open */
3309         }
3310
3311         pipe_crc->opened = true;
3312         filep->private_data = inode->i_private;
3313
3314         spin_unlock_irq(&pipe_crc->lock);
3315
3316         return 0;
3317 }
3318
3319 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3320 {
3321         struct pipe_crc_info *info = inode->i_private;
3322         struct drm_i915_private *dev_priv = info->dev->dev_private;
3323         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3324
3325         spin_lock_irq(&pipe_crc->lock);
3326         pipe_crc->opened = false;
3327         spin_unlock_irq(&pipe_crc->lock);
3328
3329         return 0;
3330 }
3331
3332 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3333 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3334 /* account for \'0' */
3335 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3336
3337 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3338 {
3339         assert_spin_locked(&pipe_crc->lock);
3340         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3341                         INTEL_PIPE_CRC_ENTRIES_NR);
3342 }
3343
3344 static ssize_t
3345 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3346                    loff_t *pos)
3347 {
3348         struct pipe_crc_info *info = filep->private_data;
3349         struct drm_device *dev = info->dev;
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3352         char buf[PIPE_CRC_BUFFER_LEN];
3353         int n_entries;
3354         ssize_t bytes_read;
3355
3356         /*
3357          * Don't allow user space to provide buffers not big enough to hold
3358          * a line of data.
3359          */
3360         if (count < PIPE_CRC_LINE_LEN)
3361                 return -EINVAL;
3362
3363         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3364                 return 0;
3365
3366         /* nothing to read */
3367         spin_lock_irq(&pipe_crc->lock);
3368         while (pipe_crc_data_count(pipe_crc) == 0) {
3369                 int ret;
3370
3371                 if (filep->f_flags & O_NONBLOCK) {
3372                         spin_unlock_irq(&pipe_crc->lock);
3373                         return -EAGAIN;
3374                 }
3375
3376                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3377                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3378                 if (ret) {
3379                         spin_unlock_irq(&pipe_crc->lock);
3380                         return ret;
3381                 }
3382         }
3383
3384         /* We now have one or more entries to read */
3385         n_entries = count / PIPE_CRC_LINE_LEN;
3386
3387         bytes_read = 0;
3388         while (n_entries > 0) {
3389                 struct intel_pipe_crc_entry *entry =
3390                         &pipe_crc->entries[pipe_crc->tail];
3391                 int ret;
3392
3393                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3394                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3395                         break;
3396
3397                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3398                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3399
3400                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3401                                        "%8u %8x %8x %8x %8x %8x\n",
3402                                        entry->frame, entry->crc[0],
3403                                        entry->crc[1], entry->crc[2],
3404                                        entry->crc[3], entry->crc[4]);
3405
3406                 spin_unlock_irq(&pipe_crc->lock);
3407
3408                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3409                 if (ret == PIPE_CRC_LINE_LEN)
3410                         return -EFAULT;
3411
3412                 user_buf += PIPE_CRC_LINE_LEN;
3413                 n_entries--;
3414
3415                 spin_lock_irq(&pipe_crc->lock);
3416         }
3417
3418         spin_unlock_irq(&pipe_crc->lock);
3419
3420         return bytes_read;
3421 }
3422
3423 static const struct file_operations i915_pipe_crc_fops = {
3424         .owner = THIS_MODULE,
3425         .open = i915_pipe_crc_open,
3426         .read = i915_pipe_crc_read,
3427         .release = i915_pipe_crc_release,
3428 };
3429
3430 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3431         {
3432                 .name = "i915_pipe_A_crc",
3433                 .pipe = PIPE_A,
3434         },
3435         {
3436                 .name = "i915_pipe_B_crc",
3437                 .pipe = PIPE_B,
3438         },
3439         {
3440                 .name = "i915_pipe_C_crc",
3441                 .pipe = PIPE_C,
3442         },
3443 };
3444
3445 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3446                                 enum pipe pipe)
3447 {
3448         struct drm_device *dev = minor->dev;
3449         struct dentry *ent;
3450         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3451
3452         info->dev = dev;
3453         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3454                                   &i915_pipe_crc_fops);
3455         if (!ent)
3456                 return -ENOMEM;
3457
3458         return drm_add_fake_info_node(minor, ent, info);
3459 }
3460
3461 static const char * const pipe_crc_sources[] = {
3462         "none",
3463         "plane1",
3464         "plane2",
3465         "pf",
3466         "pipe",
3467         "TV",
3468         "DP-B",
3469         "DP-C",
3470         "DP-D",
3471         "auto",
3472 };
3473
3474 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3475 {
3476         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3477         return pipe_crc_sources[source];
3478 }
3479
3480 static int display_crc_ctl_show(struct seq_file *m, void *data)
3481 {
3482         struct drm_device *dev = m->private;
3483         struct drm_i915_private *dev_priv = dev->dev_private;
3484         int i;
3485
3486         for (i = 0; i < I915_MAX_PIPES; i++)
3487                 seq_printf(m, "%c %s\n", pipe_name(i),
3488                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3489
3490         return 0;
3491 }
3492
3493 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3494 {
3495         struct drm_device *dev = inode->i_private;
3496
3497         return single_open(file, display_crc_ctl_show, dev);
3498 }
3499
3500 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3501                                  uint32_t *val)
3502 {
3503         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3504                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3505
3506         switch (*source) {
3507         case INTEL_PIPE_CRC_SOURCE_PIPE:
3508                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3509                 break;
3510         case INTEL_PIPE_CRC_SOURCE_NONE:
3511                 *val = 0;
3512                 break;
3513         default:
3514                 return -EINVAL;
3515         }
3516
3517         return 0;
3518 }
3519
3520 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3521                                      enum intel_pipe_crc_source *source)
3522 {
3523         struct intel_encoder *encoder;
3524         struct intel_crtc *crtc;
3525         struct intel_digital_port *dig_port;
3526         int ret = 0;
3527
3528         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3529
3530         drm_modeset_lock_all(dev);
3531         for_each_intel_encoder(dev, encoder) {
3532                 if (!encoder->base.crtc)
3533                         continue;
3534
3535                 crtc = to_intel_crtc(encoder->base.crtc);
3536
3537                 if (crtc->pipe != pipe)
3538                         continue;
3539
3540                 switch (encoder->type) {
3541                 case INTEL_OUTPUT_TVOUT:
3542                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3543                         break;
3544                 case INTEL_OUTPUT_DISPLAYPORT:
3545                 case INTEL_OUTPUT_EDP:
3546                         dig_port = enc_to_dig_port(&encoder->base);
3547                         switch (dig_port->port) {
3548                         case PORT_B:
3549                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3550                                 break;
3551                         case PORT_C:
3552                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3553                                 break;
3554                         case PORT_D:
3555                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3556                                 break;
3557                         default:
3558                                 WARN(1, "nonexisting DP port %c\n",
3559                                      port_name(dig_port->port));
3560                                 break;
3561                         }
3562                         break;
3563                 default:
3564                         break;
3565                 }
3566         }
3567         drm_modeset_unlock_all(dev);
3568
3569         return ret;
3570 }
3571
3572 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3573                                 enum pipe pipe,
3574                                 enum intel_pipe_crc_source *source,
3575                                 uint32_t *val)
3576 {
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         bool need_stable_symbols = false;
3579
3580         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3581                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3582                 if (ret)
3583                         return ret;
3584         }
3585
3586         switch (*source) {
3587         case INTEL_PIPE_CRC_SOURCE_PIPE:
3588                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3589                 break;
3590         case INTEL_PIPE_CRC_SOURCE_DP_B:
3591                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3592                 need_stable_symbols = true;
3593                 break;
3594         case INTEL_PIPE_CRC_SOURCE_DP_C:
3595                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3596                 need_stable_symbols = true;
3597                 break;
3598         case INTEL_PIPE_CRC_SOURCE_DP_D:
3599                 if (!IS_CHERRYVIEW(dev))
3600                         return -EINVAL;
3601                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3602                 need_stable_symbols = true;
3603                 break;
3604         case INTEL_PIPE_CRC_SOURCE_NONE:
3605                 *val = 0;
3606                 break;
3607         default:
3608                 return -EINVAL;
3609         }
3610
3611         /*
3612          * When the pipe CRC tap point is after the transcoders we need
3613          * to tweak symbol-level features to produce a deterministic series of
3614          * symbols for a given frame. We need to reset those features only once
3615          * a frame (instead of every nth symbol):
3616          *   - DC-balance: used to ensure a better clock recovery from the data
3617          *     link (SDVO)
3618          *   - DisplayPort scrambling: used for EMI reduction
3619          */
3620         if (need_stable_symbols) {
3621                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3622
3623                 tmp |= DC_BALANCE_RESET_VLV;
3624                 switch (pipe) {
3625                 case PIPE_A:
3626                         tmp |= PIPE_A_SCRAMBLE_RESET;
3627                         break;
3628                 case PIPE_B:
3629                         tmp |= PIPE_B_SCRAMBLE_RESET;
3630                         break;
3631                 case PIPE_C:
3632                         tmp |= PIPE_C_SCRAMBLE_RESET;
3633                         break;
3634                 default:
3635                         return -EINVAL;
3636                 }
3637                 I915_WRITE(PORT_DFT2_G4X, tmp);
3638         }
3639
3640         return 0;
3641 }
3642
3643 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3644                                  enum pipe pipe,
3645                                  enum intel_pipe_crc_source *source,
3646                                  uint32_t *val)
3647 {
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         bool need_stable_symbols = false;
3650
3651         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3652                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3653                 if (ret)
3654                         return ret;
3655         }
3656
3657         switch (*source) {
3658         case INTEL_PIPE_CRC_SOURCE_PIPE:
3659                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3660                 break;
3661         case INTEL_PIPE_CRC_SOURCE_TV:
3662                 if (!SUPPORTS_TV(dev))
3663                         return -EINVAL;
3664                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3665                 break;
3666         case INTEL_PIPE_CRC_SOURCE_DP_B:
3667                 if (!IS_G4X(dev))
3668                         return -EINVAL;
3669                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3670                 need_stable_symbols = true;
3671                 break;
3672         case INTEL_PIPE_CRC_SOURCE_DP_C:
3673                 if (!IS_G4X(dev))
3674                         return -EINVAL;
3675                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3676                 need_stable_symbols = true;
3677                 break;
3678         case INTEL_PIPE_CRC_SOURCE_DP_D:
3679                 if (!IS_G4X(dev))
3680                         return -EINVAL;
3681                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3682                 need_stable_symbols = true;
3683                 break;
3684         case INTEL_PIPE_CRC_SOURCE_NONE:
3685                 *val = 0;
3686                 break;
3687         default:
3688                 return -EINVAL;
3689         }
3690
3691         /*
3692          * When the pipe CRC tap point is after the transcoders we need
3693          * to tweak symbol-level features to produce a deterministic series of
3694          * symbols for a given frame. We need to reset those features only once
3695          * a frame (instead of every nth symbol):
3696          *   - DC-balance: used to ensure a better clock recovery from the data
3697          *     link (SDVO)
3698          *   - DisplayPort scrambling: used for EMI reduction
3699          */
3700         if (need_stable_symbols) {
3701                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3702
3703                 WARN_ON(!IS_G4X(dev));
3704
3705                 I915_WRITE(PORT_DFT_I9XX,
3706                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3707
3708                 if (pipe == PIPE_A)
3709                         tmp |= PIPE_A_SCRAMBLE_RESET;
3710                 else
3711                         tmp |= PIPE_B_SCRAMBLE_RESET;
3712
3713                 I915_WRITE(PORT_DFT2_G4X, tmp);
3714         }
3715
3716         return 0;
3717 }
3718
3719 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3720                                          enum pipe pipe)
3721 {
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3724
3725         switch (pipe) {
3726         case PIPE_A:
3727                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3728                 break;
3729         case PIPE_B:
3730                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3731                 break;
3732         case PIPE_C:
3733                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3734                 break;
3735         default:
3736                 return;
3737         }
3738         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3739                 tmp &= ~DC_BALANCE_RESET_VLV;
3740         I915_WRITE(PORT_DFT2_G4X, tmp);
3741
3742 }
3743
3744 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3745                                          enum pipe pipe)
3746 {
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3749
3750         if (pipe == PIPE_A)
3751                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3752         else
3753                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3754         I915_WRITE(PORT_DFT2_G4X, tmp);
3755
3756         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3757                 I915_WRITE(PORT_DFT_I9XX,
3758                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3759         }
3760 }
3761
3762 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3763                                 uint32_t *val)
3764 {
3765         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3766                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3767
3768         switch (*source) {
3769         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3770                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3771                 break;
3772         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3773                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3774                 break;
3775         case INTEL_PIPE_CRC_SOURCE_PIPE:
3776                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3777                 break;
3778         case INTEL_PIPE_CRC_SOURCE_NONE:
3779                 *val = 0;
3780                 break;
3781         default:
3782                 return -EINVAL;
3783         }
3784
3785         return 0;
3786 }
3787
3788 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3789 {
3790         struct drm_i915_private *dev_priv = dev->dev_private;
3791         struct intel_crtc *crtc =
3792                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3793         struct intel_crtc_state *pipe_config;
3794         struct drm_atomic_state *state;
3795         int ret = 0;
3796
3797         drm_modeset_lock_all(dev);
3798         state = drm_atomic_state_alloc(dev);
3799         if (!state) {
3800                 ret = -ENOMEM;
3801                 goto out;
3802         }
3803
3804         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3805         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3806         if (IS_ERR(pipe_config)) {
3807                 ret = PTR_ERR(pipe_config);
3808                 goto out;
3809         }
3810
3811         pipe_config->pch_pfit.force_thru = enable;
3812         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3813             pipe_config->pch_pfit.enabled != enable)
3814                 pipe_config->base.connectors_changed = true;
3815
3816         ret = drm_atomic_commit(state);
3817 out:
3818         drm_modeset_unlock_all(dev);
3819         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3820         if (ret)
3821                 drm_atomic_state_free(state);
3822 }
3823
3824 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3825                                 enum pipe pipe,
3826                                 enum intel_pipe_crc_source *source,
3827                                 uint32_t *val)
3828 {
3829         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3830                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3831
3832         switch (*source) {
3833         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3834                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3835                 break;
3836         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3837                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3838                 break;
3839         case INTEL_PIPE_CRC_SOURCE_PF:
3840                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3841                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
3842
3843                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3844                 break;
3845         case INTEL_PIPE_CRC_SOURCE_NONE:
3846                 *val = 0;
3847                 break;
3848         default:
3849                 return -EINVAL;
3850         }
3851
3852         return 0;
3853 }
3854
3855 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3856                                enum intel_pipe_crc_source source)
3857 {
3858         struct drm_i915_private *dev_priv = dev->dev_private;
3859         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3860         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3861                                                                         pipe));
3862         u32 val = 0; /* shut up gcc */
3863         int ret;
3864
3865         if (pipe_crc->source == source)
3866                 return 0;
3867
3868         /* forbid changing the source without going back to 'none' */
3869         if (pipe_crc->source && source)
3870                 return -EINVAL;
3871
3872         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3873                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3874                 return -EIO;
3875         }
3876
3877         if (IS_GEN2(dev))
3878                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3879         else if (INTEL_INFO(dev)->gen < 5)
3880                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3881         else if (IS_VALLEYVIEW(dev))
3882                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3883         else if (IS_GEN5(dev) || IS_GEN6(dev))
3884                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3885         else
3886                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3887
3888         if (ret != 0)
3889                 return ret;
3890
3891         /* none -> real source transition */
3892         if (source) {
3893                 struct intel_pipe_crc_entry *entries;
3894
3895                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3896                                  pipe_name(pipe), pipe_crc_source_name(source));
3897
3898                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3899                                   sizeof(pipe_crc->entries[0]),
3900                                   GFP_KERNEL);
3901                 if (!entries)
3902                         return -ENOMEM;
3903
3904                 /*
3905                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3906                  * enabled and disabled dynamically based on package C states,
3907                  * user space can't make reliable use of the CRCs, so let's just
3908                  * completely disable it.
3909                  */
3910                 hsw_disable_ips(crtc);
3911
3912                 spin_lock_irq(&pipe_crc->lock);
3913                 kfree(pipe_crc->entries);
3914                 pipe_crc->entries = entries;
3915                 pipe_crc->head = 0;
3916                 pipe_crc->tail = 0;
3917                 spin_unlock_irq(&pipe_crc->lock);
3918         }
3919
3920         pipe_crc->source = source;
3921
3922         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3923         POSTING_READ(PIPE_CRC_CTL(pipe));
3924
3925         /* real source -> none transition */
3926         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3927                 struct intel_pipe_crc_entry *entries;
3928                 struct intel_crtc *crtc =
3929                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3930
3931                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3932                                  pipe_name(pipe));
3933
3934                 drm_modeset_lock(&crtc->base.mutex, NULL);
3935                 if (crtc->base.state->active)
3936                         intel_wait_for_vblank(dev, pipe);
3937                 drm_modeset_unlock(&crtc->base.mutex);
3938
3939                 spin_lock_irq(&pipe_crc->lock);
3940                 entries = pipe_crc->entries;
3941                 pipe_crc->entries = NULL;
3942                 pipe_crc->head = 0;
3943                 pipe_crc->tail = 0;
3944                 spin_unlock_irq(&pipe_crc->lock);
3945
3946                 kfree(entries);
3947
3948                 if (IS_G4X(dev))
3949                         g4x_undo_pipe_scramble_reset(dev, pipe);
3950                 else if (IS_VALLEYVIEW(dev))
3951                         vlv_undo_pipe_scramble_reset(dev, pipe);
3952                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3953                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
3954
3955                 hsw_enable_ips(crtc);
3956         }
3957
3958         return 0;
3959 }
3960
3961 /*
3962  * Parse pipe CRC command strings:
3963  *   command: wsp* object wsp+ name wsp+ source wsp*
3964  *   object: 'pipe'
3965  *   name: (A | B | C)
3966  *   source: (none | plane1 | plane2 | pf)
3967  *   wsp: (#0x20 | #0x9 | #0xA)+
3968  *
3969  * eg.:
3970  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3971  *  "pipe A none"    ->  Stop CRC
3972  */
3973 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3974 {
3975         int n_words = 0;
3976
3977         while (*buf) {
3978                 char *end;
3979
3980                 /* skip leading white space */
3981                 buf = skip_spaces(buf);
3982                 if (!*buf)
3983                         break;  /* end of buffer */
3984
3985                 /* find end of word */
3986                 for (end = buf; *end && !isspace(*end); end++)
3987                         ;
3988
3989                 if (n_words == max_words) {
3990                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3991                                          max_words);
3992                         return -EINVAL; /* ran out of words[] before bytes */
3993                 }
3994
3995                 if (*end)
3996                         *end++ = '\0';
3997                 words[n_words++] = buf;
3998                 buf = end;
3999         }
4000
4001         return n_words;
4002 }
4003
4004 enum intel_pipe_crc_object {
4005         PIPE_CRC_OBJECT_PIPE,
4006 };
4007
4008 static const char * const pipe_crc_objects[] = {
4009         "pipe",
4010 };
4011
4012 static int
4013 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4014 {
4015         int i;
4016
4017         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4018                 if (!strcmp(buf, pipe_crc_objects[i])) {
4019                         *o = i;
4020                         return 0;
4021                     }
4022
4023         return -EINVAL;
4024 }
4025
4026 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4027 {
4028         const char name = buf[0];
4029
4030         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4031                 return -EINVAL;
4032
4033         *pipe = name - 'A';
4034
4035         return 0;
4036 }
4037
4038 static int
4039 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4040 {
4041         int i;
4042
4043         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4044                 if (!strcmp(buf, pipe_crc_sources[i])) {
4045                         *s = i;
4046                         return 0;
4047                     }
4048
4049         return -EINVAL;
4050 }
4051
4052 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4053 {
4054 #define N_WORDS 3
4055         int n_words;
4056         char *words[N_WORDS];
4057         enum pipe pipe;
4058         enum intel_pipe_crc_object object;
4059         enum intel_pipe_crc_source source;
4060
4061         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4062         if (n_words != N_WORDS) {
4063                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4064                                  N_WORDS);
4065                 return -EINVAL;
4066         }
4067
4068         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4069                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4070                 return -EINVAL;
4071         }
4072
4073         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4074                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4075                 return -EINVAL;
4076         }
4077
4078         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4079                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4080                 return -EINVAL;
4081         }
4082
4083         return pipe_crc_set_source(dev, pipe, source);
4084 }
4085
4086 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4087                                      size_t len, loff_t *offp)
4088 {
4089         struct seq_file *m = file->private_data;
4090         struct drm_device *dev = m->private;
4091         char *tmpbuf;
4092         int ret;
4093
4094         if (len == 0)
4095                 return 0;
4096
4097         if (len > PAGE_SIZE - 1) {
4098                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4099                                  PAGE_SIZE);
4100                 return -E2BIG;
4101         }
4102
4103         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4104         if (!tmpbuf)
4105                 return -ENOMEM;
4106
4107         if (copy_from_user(tmpbuf, ubuf, len)) {
4108                 ret = -EFAULT;
4109                 goto out;
4110         }
4111         tmpbuf[len] = '\0';
4112
4113         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4114
4115 out:
4116         kfree(tmpbuf);
4117         if (ret < 0)
4118                 return ret;
4119
4120         *offp += len;
4121         return len;
4122 }
4123
4124 static const struct file_operations i915_display_crc_ctl_fops = {
4125         .owner = THIS_MODULE,
4126         .open = display_crc_ctl_open,
4127         .read = seq_read,
4128         .llseek = seq_lseek,
4129         .release = single_release,
4130         .write = display_crc_ctl_write
4131 };
4132
4133 static ssize_t i915_displayport_test_active_write(struct file *file,
4134                                             const char __user *ubuf,
4135                                             size_t len, loff_t *offp)
4136 {
4137         char *input_buffer;
4138         int status = 0;
4139         struct drm_device *dev;
4140         struct drm_connector *connector;
4141         struct list_head *connector_list;
4142         struct intel_dp *intel_dp;
4143         int val = 0;
4144
4145         dev = ((struct seq_file *)file->private_data)->private;
4146
4147         connector_list = &dev->mode_config.connector_list;
4148
4149         if (len == 0)
4150                 return 0;
4151
4152         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4153         if (!input_buffer)
4154                 return -ENOMEM;
4155
4156         if (copy_from_user(input_buffer, ubuf, len)) {
4157                 status = -EFAULT;
4158                 goto out;
4159         }
4160
4161         input_buffer[len] = '\0';
4162         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4163
4164         list_for_each_entry(connector, connector_list, head) {
4165
4166                 if (connector->connector_type !=
4167                     DRM_MODE_CONNECTOR_DisplayPort)
4168                         continue;
4169
4170                 if (connector->status == connector_status_connected &&
4171                     connector->encoder != NULL) {
4172                         intel_dp = enc_to_intel_dp(connector->encoder);
4173                         status = kstrtoint(input_buffer, 10, &val);
4174                         if (status < 0)
4175                                 goto out;
4176                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4177                         /* To prevent erroneous activation of the compliance
4178                          * testing code, only accept an actual value of 1 here
4179                          */
4180                         if (val == 1)
4181                                 intel_dp->compliance_test_active = 1;
4182                         else
4183                                 intel_dp->compliance_test_active = 0;
4184                 }
4185         }
4186 out:
4187         kfree(input_buffer);
4188         if (status < 0)
4189                 return status;
4190
4191         *offp += len;
4192         return len;
4193 }
4194
4195 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4196 {
4197         struct drm_device *dev = m->private;
4198         struct drm_connector *connector;
4199         struct list_head *connector_list = &dev->mode_config.connector_list;
4200         struct intel_dp *intel_dp;
4201
4202         list_for_each_entry(connector, connector_list, head) {
4203
4204                 if (connector->connector_type !=
4205                     DRM_MODE_CONNECTOR_DisplayPort)
4206                         continue;
4207
4208                 if (connector->status == connector_status_connected &&
4209                     connector->encoder != NULL) {
4210                         intel_dp = enc_to_intel_dp(connector->encoder);
4211                         if (intel_dp->compliance_test_active)
4212                                 seq_puts(m, "1");
4213                         else
4214                                 seq_puts(m, "0");
4215                 } else
4216                         seq_puts(m, "0");
4217         }
4218
4219         return 0;
4220 }
4221
4222 static int i915_displayport_test_active_open(struct inode *inode,
4223                                        struct file *file)
4224 {
4225         struct drm_device *dev = inode->i_private;
4226
4227         return single_open(file, i915_displayport_test_active_show, dev);
4228 }
4229
4230 static const struct file_operations i915_displayport_test_active_fops = {
4231         .owner = THIS_MODULE,
4232         .open = i915_displayport_test_active_open,
4233         .read = seq_read,
4234         .llseek = seq_lseek,
4235         .release = single_release,
4236         .write = i915_displayport_test_active_write
4237 };
4238
4239 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4240 {
4241         struct drm_device *dev = m->private;
4242         struct drm_connector *connector;
4243         struct list_head *connector_list = &dev->mode_config.connector_list;
4244         struct intel_dp *intel_dp;
4245
4246         list_for_each_entry(connector, connector_list, head) {
4247
4248                 if (connector->connector_type !=
4249                     DRM_MODE_CONNECTOR_DisplayPort)
4250                         continue;
4251
4252                 if (connector->status == connector_status_connected &&
4253                     connector->encoder != NULL) {
4254                         intel_dp = enc_to_intel_dp(connector->encoder);
4255                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4256                 } else
4257                         seq_puts(m, "0");
4258         }
4259
4260         return 0;
4261 }
4262 static int i915_displayport_test_data_open(struct inode *inode,
4263                                        struct file *file)
4264 {
4265         struct drm_device *dev = inode->i_private;
4266
4267         return single_open(file, i915_displayport_test_data_show, dev);
4268 }
4269
4270 static const struct file_operations i915_displayport_test_data_fops = {
4271         .owner = THIS_MODULE,
4272         .open = i915_displayport_test_data_open,
4273         .read = seq_read,
4274         .llseek = seq_lseek,
4275         .release = single_release
4276 };
4277
4278 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4279 {
4280         struct drm_device *dev = m->private;
4281         struct drm_connector *connector;
4282         struct list_head *connector_list = &dev->mode_config.connector_list;
4283         struct intel_dp *intel_dp;
4284
4285         list_for_each_entry(connector, connector_list, head) {
4286
4287                 if (connector->connector_type !=
4288                     DRM_MODE_CONNECTOR_DisplayPort)
4289                         continue;
4290
4291                 if (connector->status == connector_status_connected &&
4292                     connector->encoder != NULL) {
4293                         intel_dp = enc_to_intel_dp(connector->encoder);
4294                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4295                 } else
4296                         seq_puts(m, "0");
4297         }
4298
4299         return 0;
4300 }
4301
4302 static int i915_displayport_test_type_open(struct inode *inode,
4303                                        struct file *file)
4304 {
4305         struct drm_device *dev = inode->i_private;
4306
4307         return single_open(file, i915_displayport_test_type_show, dev);
4308 }
4309
4310 static const struct file_operations i915_displayport_test_type_fops = {
4311         .owner = THIS_MODULE,
4312         .open = i915_displayport_test_type_open,
4313         .read = seq_read,
4314         .llseek = seq_lseek,
4315         .release = single_release
4316 };
4317
4318 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4319 {
4320         struct drm_device *dev = m->private;
4321         int level;
4322         int num_levels;
4323
4324         if (IS_CHERRYVIEW(dev))
4325                 num_levels = 3;
4326         else if (IS_VALLEYVIEW(dev))
4327                 num_levels = 1;
4328         else
4329                 num_levels = ilk_wm_max_level(dev) + 1;
4330
4331         drm_modeset_lock_all(dev);
4332
4333         for (level = 0; level < num_levels; level++) {
4334                 unsigned int latency = wm[level];
4335
4336                 /*
4337                  * - WM1+ latency values in 0.5us units
4338                  * - latencies are in us on gen9/vlv/chv
4339                  */
4340                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4341                         latency *= 10;
4342                 else if (level > 0)
4343                         latency *= 5;
4344
4345                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4346                            level, wm[level], latency / 10, latency % 10);
4347         }
4348
4349         drm_modeset_unlock_all(dev);
4350 }
4351
4352 static int pri_wm_latency_show(struct seq_file *m, void *data)
4353 {
4354         struct drm_device *dev = m->private;
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         const uint16_t *latencies;
4357
4358         if (INTEL_INFO(dev)->gen >= 9)
4359                 latencies = dev_priv->wm.skl_latency;
4360         else
4361                 latencies = to_i915(dev)->wm.pri_latency;
4362
4363         wm_latency_show(m, latencies);
4364
4365         return 0;
4366 }
4367
4368 static int spr_wm_latency_show(struct seq_file *m, void *data)
4369 {
4370         struct drm_device *dev = m->private;
4371         struct drm_i915_private *dev_priv = dev->dev_private;
4372         const uint16_t *latencies;
4373
4374         if (INTEL_INFO(dev)->gen >= 9)
4375                 latencies = dev_priv->wm.skl_latency;
4376         else
4377                 latencies = to_i915(dev)->wm.spr_latency;
4378
4379         wm_latency_show(m, latencies);
4380
4381         return 0;
4382 }
4383
4384 static int cur_wm_latency_show(struct seq_file *m, void *data)
4385 {
4386         struct drm_device *dev = m->private;
4387         struct drm_i915_private *dev_priv = dev->dev_private;
4388         const uint16_t *latencies;
4389
4390         if (INTEL_INFO(dev)->gen >= 9)
4391                 latencies = dev_priv->wm.skl_latency;
4392         else
4393                 latencies = to_i915(dev)->wm.cur_latency;
4394
4395         wm_latency_show(m, latencies);
4396
4397         return 0;
4398 }
4399
4400 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4401 {
4402         struct drm_device *dev = inode->i_private;
4403
4404         if (INTEL_INFO(dev)->gen < 5)
4405                 return -ENODEV;
4406
4407         return single_open(file, pri_wm_latency_show, dev);
4408 }
4409
4410 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4411 {
4412         struct drm_device *dev = inode->i_private;
4413
4414         if (HAS_GMCH_DISPLAY(dev))
4415                 return -ENODEV;
4416
4417         return single_open(file, spr_wm_latency_show, dev);
4418 }
4419
4420 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4421 {
4422         struct drm_device *dev = inode->i_private;
4423
4424         if (HAS_GMCH_DISPLAY(dev))
4425                 return -ENODEV;
4426
4427         return single_open(file, cur_wm_latency_show, dev);
4428 }
4429
4430 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4431                                 size_t len, loff_t *offp, uint16_t wm[8])
4432 {
4433         struct seq_file *m = file->private_data;
4434         struct drm_device *dev = m->private;
4435         uint16_t new[8] = { 0 };
4436         int num_levels;
4437         int level;
4438         int ret;
4439         char tmp[32];
4440
4441         if (IS_CHERRYVIEW(dev))
4442                 num_levels = 3;
4443         else if (IS_VALLEYVIEW(dev))
4444                 num_levels = 1;
4445         else
4446                 num_levels = ilk_wm_max_level(dev) + 1;
4447
4448         if (len >= sizeof(tmp))
4449                 return -EINVAL;
4450
4451         if (copy_from_user(tmp, ubuf, len))
4452                 return -EFAULT;
4453
4454         tmp[len] = '\0';
4455
4456         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4457                      &new[0], &new[1], &new[2], &new[3],
4458                      &new[4], &new[5], &new[6], &new[7]);
4459         if (ret != num_levels)
4460                 return -EINVAL;
4461
4462         drm_modeset_lock_all(dev);
4463
4464         for (level = 0; level < num_levels; level++)
4465                 wm[level] = new[level];
4466
4467         drm_modeset_unlock_all(dev);
4468
4469         return len;
4470 }
4471
4472
4473 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4474                                     size_t len, loff_t *offp)
4475 {
4476         struct seq_file *m = file->private_data;
4477         struct drm_device *dev = m->private;
4478         struct drm_i915_private *dev_priv = dev->dev_private;
4479         uint16_t *latencies;
4480
4481         if (INTEL_INFO(dev)->gen >= 9)
4482                 latencies = dev_priv->wm.skl_latency;
4483         else
4484                 latencies = to_i915(dev)->wm.pri_latency;
4485
4486         return wm_latency_write(file, ubuf, len, offp, latencies);
4487 }
4488
4489 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4490                                     size_t len, loff_t *offp)
4491 {
4492         struct seq_file *m = file->private_data;
4493         struct drm_device *dev = m->private;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         uint16_t *latencies;
4496
4497         if (INTEL_INFO(dev)->gen >= 9)
4498                 latencies = dev_priv->wm.skl_latency;
4499         else
4500                 latencies = to_i915(dev)->wm.spr_latency;
4501
4502         return wm_latency_write(file, ubuf, len, offp, latencies);
4503 }
4504
4505 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4506                                     size_t len, loff_t *offp)
4507 {
4508         struct seq_file *m = file->private_data;
4509         struct drm_device *dev = m->private;
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511         uint16_t *latencies;
4512
4513         if (INTEL_INFO(dev)->gen >= 9)
4514                 latencies = dev_priv->wm.skl_latency;
4515         else
4516                 latencies = to_i915(dev)->wm.cur_latency;
4517
4518         return wm_latency_write(file, ubuf, len, offp, latencies);
4519 }
4520
4521 static const struct file_operations i915_pri_wm_latency_fops = {
4522         .owner = THIS_MODULE,
4523         .open = pri_wm_latency_open,
4524         .read = seq_read,
4525         .llseek = seq_lseek,
4526         .release = single_release,
4527         .write = pri_wm_latency_write
4528 };
4529
4530 static const struct file_operations i915_spr_wm_latency_fops = {
4531         .owner = THIS_MODULE,
4532         .open = spr_wm_latency_open,
4533         .read = seq_read,
4534         .llseek = seq_lseek,
4535         .release = single_release,
4536         .write = spr_wm_latency_write
4537 };
4538
4539 static const struct file_operations i915_cur_wm_latency_fops = {
4540         .owner = THIS_MODULE,
4541         .open = cur_wm_latency_open,
4542         .read = seq_read,
4543         .llseek = seq_lseek,
4544         .release = single_release,
4545         .write = cur_wm_latency_write
4546 };
4547
4548 static int
4549 i915_wedged_get(void *data, u64 *val)
4550 {
4551         struct drm_device *dev = data;
4552         struct drm_i915_private *dev_priv = dev->dev_private;
4553
4554         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4555
4556         return 0;
4557 }
4558
4559 static int
4560 i915_wedged_set(void *data, u64 val)
4561 {
4562         struct drm_device *dev = data;
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565         /*
4566          * There is no safeguard against this debugfs entry colliding
4567          * with the hangcheck calling same i915_handle_error() in
4568          * parallel, causing an explosion. For now we assume that the
4569          * test harness is responsible enough not to inject gpu hangs
4570          * while it is writing to 'i915_wedged'
4571          */
4572
4573         if (i915_reset_in_progress(&dev_priv->gpu_error))
4574                 return -EAGAIN;
4575
4576         intel_runtime_pm_get(dev_priv);
4577
4578         i915_handle_error(dev, val,
4579                           "Manually setting wedged to %llu", val);
4580
4581         intel_runtime_pm_put(dev_priv);
4582
4583         return 0;
4584 }
4585
4586 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4587                         i915_wedged_get, i915_wedged_set,
4588                         "%llu\n");
4589
4590 static int
4591 i915_ring_stop_get(void *data, u64 *val)
4592 {
4593         struct drm_device *dev = data;
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595
4596         *val = dev_priv->gpu_error.stop_rings;
4597
4598         return 0;
4599 }
4600
4601 static int
4602 i915_ring_stop_set(void *data, u64 val)
4603 {
4604         struct drm_device *dev = data;
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         int ret;
4607
4608         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4609
4610         ret = mutex_lock_interruptible(&dev->struct_mutex);
4611         if (ret)
4612                 return ret;
4613
4614         dev_priv->gpu_error.stop_rings = val;
4615         mutex_unlock(&dev->struct_mutex);
4616
4617         return 0;
4618 }
4619
4620 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4621                         i915_ring_stop_get, i915_ring_stop_set,
4622                         "0x%08llx\n");
4623
4624 static int
4625 i915_ring_missed_irq_get(void *data, u64 *val)
4626 {
4627         struct drm_device *dev = data;
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629
4630         *val = dev_priv->gpu_error.missed_irq_rings;
4631         return 0;
4632 }
4633
4634 static int
4635 i915_ring_missed_irq_set(void *data, u64 val)
4636 {
4637         struct drm_device *dev = data;
4638         struct drm_i915_private *dev_priv = dev->dev_private;
4639         int ret;
4640
4641         /* Lock against concurrent debugfs callers */
4642         ret = mutex_lock_interruptible(&dev->struct_mutex);
4643         if (ret)
4644                 return ret;
4645         dev_priv->gpu_error.missed_irq_rings = val;
4646         mutex_unlock(&dev->struct_mutex);
4647
4648         return 0;
4649 }
4650
4651 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4652                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4653                         "0x%08llx\n");
4654
4655 static int
4656 i915_ring_test_irq_get(void *data, u64 *val)
4657 {
4658         struct drm_device *dev = data;
4659         struct drm_i915_private *dev_priv = dev->dev_private;
4660
4661         *val = dev_priv->gpu_error.test_irq_rings;
4662
4663         return 0;
4664 }
4665
4666 static int
4667 i915_ring_test_irq_set(void *data, u64 val)
4668 {
4669         struct drm_device *dev = data;
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         int ret;
4672
4673         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4674
4675         /* Lock against concurrent debugfs callers */
4676         ret = mutex_lock_interruptible(&dev->struct_mutex);
4677         if (ret)
4678                 return ret;
4679
4680         dev_priv->gpu_error.test_irq_rings = val;
4681         mutex_unlock(&dev->struct_mutex);
4682
4683         return 0;
4684 }
4685
4686 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4687                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4688                         "0x%08llx\n");
4689
4690 #define DROP_UNBOUND 0x1
4691 #define DROP_BOUND 0x2
4692 #define DROP_RETIRE 0x4
4693 #define DROP_ACTIVE 0x8
4694 #define DROP_ALL (DROP_UNBOUND | \
4695                   DROP_BOUND | \
4696                   DROP_RETIRE | \
4697                   DROP_ACTIVE)
4698 static int
4699 i915_drop_caches_get(void *data, u64 *val)
4700 {
4701         *val = DROP_ALL;
4702
4703         return 0;
4704 }
4705
4706 static int
4707 i915_drop_caches_set(void *data, u64 val)
4708 {
4709         struct drm_device *dev = data;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         int ret;
4712
4713         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4714
4715         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4716          * on ioctls on -EAGAIN. */
4717         ret = mutex_lock_interruptible(&dev->struct_mutex);
4718         if (ret)
4719                 return ret;
4720
4721         if (val & DROP_ACTIVE) {
4722                 ret = i915_gpu_idle(dev);
4723                 if (ret)
4724                         goto unlock;
4725         }
4726
4727         if (val & (DROP_RETIRE | DROP_ACTIVE))
4728                 i915_gem_retire_requests(dev);
4729
4730         if (val & DROP_BOUND)
4731                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4732
4733         if (val & DROP_UNBOUND)
4734                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4735
4736 unlock:
4737         mutex_unlock(&dev->struct_mutex);
4738
4739         return ret;
4740 }
4741
4742 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4743                         i915_drop_caches_get, i915_drop_caches_set,
4744                         "0x%08llx\n");
4745
4746 static int
4747 i915_max_freq_get(void *data, u64 *val)
4748 {
4749         struct drm_device *dev = data;
4750         struct drm_i915_private *dev_priv = dev->dev_private;
4751         int ret;
4752
4753         if (INTEL_INFO(dev)->gen < 6)
4754                 return -ENODEV;
4755
4756         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4757
4758         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4759         if (ret)
4760                 return ret;
4761
4762         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4763         mutex_unlock(&dev_priv->rps.hw_lock);
4764
4765         return 0;
4766 }
4767
4768 static int
4769 i915_max_freq_set(void *data, u64 val)
4770 {
4771         struct drm_device *dev = data;
4772         struct drm_i915_private *dev_priv = dev->dev_private;
4773         u32 hw_max, hw_min;
4774         int ret;
4775
4776         if (INTEL_INFO(dev)->gen < 6)
4777                 return -ENODEV;
4778
4779         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4780
4781         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4782
4783         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4784         if (ret)
4785                 return ret;
4786
4787         /*
4788          * Turbo will still be enabled, but won't go above the set value.
4789          */
4790         val = intel_freq_opcode(dev_priv, val);
4791
4792         hw_max = dev_priv->rps.max_freq;
4793         hw_min = dev_priv->rps.min_freq;
4794
4795         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4796                 mutex_unlock(&dev_priv->rps.hw_lock);
4797                 return -EINVAL;
4798         }
4799
4800         dev_priv->rps.max_freq_softlimit = val;
4801
4802         intel_set_rps(dev, val);
4803
4804         mutex_unlock(&dev_priv->rps.hw_lock);
4805
4806         return 0;
4807 }
4808
4809 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4810                         i915_max_freq_get, i915_max_freq_set,
4811                         "%llu\n");
4812
4813 static int
4814 i915_min_freq_get(void *data, u64 *val)
4815 {
4816         struct drm_device *dev = data;
4817         struct drm_i915_private *dev_priv = dev->dev_private;
4818         int ret;
4819
4820         if (INTEL_INFO(dev)->gen < 6)
4821                 return -ENODEV;
4822
4823         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4824
4825         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4826         if (ret)
4827                 return ret;
4828
4829         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4830         mutex_unlock(&dev_priv->rps.hw_lock);
4831
4832         return 0;
4833 }
4834
4835 static int
4836 i915_min_freq_set(void *data, u64 val)
4837 {
4838         struct drm_device *dev = data;
4839         struct drm_i915_private *dev_priv = dev->dev_private;
4840         u32 hw_max, hw_min;
4841         int ret;
4842
4843         if (INTEL_INFO(dev)->gen < 6)
4844                 return -ENODEV;
4845
4846         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4847
4848         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4849
4850         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4851         if (ret)
4852                 return ret;
4853
4854         /*
4855          * Turbo will still be enabled, but won't go below the set value.
4856          */
4857         val = intel_freq_opcode(dev_priv, val);
4858
4859         hw_max = dev_priv->rps.max_freq;
4860         hw_min = dev_priv->rps.min_freq;
4861
4862         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4863                 mutex_unlock(&dev_priv->rps.hw_lock);
4864                 return -EINVAL;
4865         }
4866
4867         dev_priv->rps.min_freq_softlimit = val;
4868
4869         intel_set_rps(dev, val);
4870
4871         mutex_unlock(&dev_priv->rps.hw_lock);
4872
4873         return 0;
4874 }
4875
4876 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4877                         i915_min_freq_get, i915_min_freq_set,
4878                         "%llu\n");
4879
4880 static int
4881 i915_cache_sharing_get(void *data, u64 *val)
4882 {
4883         struct drm_device *dev = data;
4884         struct drm_i915_private *dev_priv = dev->dev_private;
4885         u32 snpcr;
4886         int ret;
4887
4888         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4889                 return -ENODEV;
4890
4891         ret = mutex_lock_interruptible(&dev->struct_mutex);
4892         if (ret)
4893                 return ret;
4894         intel_runtime_pm_get(dev_priv);
4895
4896         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4897
4898         intel_runtime_pm_put(dev_priv);
4899         mutex_unlock(&dev_priv->dev->struct_mutex);
4900
4901         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4902
4903         return 0;
4904 }
4905
4906 static int
4907 i915_cache_sharing_set(void *data, u64 val)
4908 {
4909         struct drm_device *dev = data;
4910         struct drm_i915_private *dev_priv = dev->dev_private;
4911         u32 snpcr;
4912
4913         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4914                 return -ENODEV;
4915
4916         if (val > 3)
4917                 return -EINVAL;
4918
4919         intel_runtime_pm_get(dev_priv);
4920         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4921
4922         /* Update the cache sharing policy here as well */
4923         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4924         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4925         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4926         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4927
4928         intel_runtime_pm_put(dev_priv);
4929         return 0;
4930 }
4931
4932 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4933                         i915_cache_sharing_get, i915_cache_sharing_set,
4934                         "%llu\n");
4935
4936 struct sseu_dev_status {
4937         unsigned int slice_total;
4938         unsigned int subslice_total;
4939         unsigned int subslice_per_slice;
4940         unsigned int eu_total;
4941         unsigned int eu_per_subslice;
4942 };
4943
4944 static void cherryview_sseu_device_status(struct drm_device *dev,
4945                                           struct sseu_dev_status *stat)
4946 {
4947         struct drm_i915_private *dev_priv = dev->dev_private;
4948         int ss_max = 2;
4949         int ss;
4950         u32 sig1[ss_max], sig2[ss_max];
4951
4952         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4953         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4954         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4955         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4956
4957         for (ss = 0; ss < ss_max; ss++) {
4958                 unsigned int eu_cnt;
4959
4960                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4961                         /* skip disabled subslice */
4962                         continue;
4963
4964                 stat->slice_total = 1;
4965                 stat->subslice_per_slice++;
4966                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4967                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4968                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4969                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4970                 stat->eu_total += eu_cnt;
4971                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4972         }
4973         stat->subslice_total = stat->subslice_per_slice;
4974 }
4975
4976 static void gen9_sseu_device_status(struct drm_device *dev,
4977                                     struct sseu_dev_status *stat)
4978 {
4979         struct drm_i915_private *dev_priv = dev->dev_private;
4980         int s_max = 3, ss_max = 4;
4981         int s, ss;
4982         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4983
4984         /* BXT has a single slice and at most 3 subslices. */
4985         if (IS_BROXTON(dev)) {
4986                 s_max = 1;
4987                 ss_max = 3;
4988         }
4989
4990         for (s = 0; s < s_max; s++) {
4991                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4992                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4993                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4994         }
4995
4996         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4997                      GEN9_PGCTL_SSA_EU19_ACK |
4998                      GEN9_PGCTL_SSA_EU210_ACK |
4999                      GEN9_PGCTL_SSA_EU311_ACK;
5000         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5001                      GEN9_PGCTL_SSB_EU19_ACK |
5002                      GEN9_PGCTL_SSB_EU210_ACK |
5003                      GEN9_PGCTL_SSB_EU311_ACK;
5004
5005         for (s = 0; s < s_max; s++) {
5006                 unsigned int ss_cnt = 0;
5007
5008                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5009                         /* skip disabled slice */
5010                         continue;
5011
5012                 stat->slice_total++;
5013
5014                 if (IS_SKYLAKE(dev))
5015                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5016
5017                 for (ss = 0; ss < ss_max; ss++) {
5018                         unsigned int eu_cnt;
5019
5020                         if (IS_BROXTON(dev) &&
5021                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5022                                 /* skip disabled subslice */
5023                                 continue;
5024
5025                         if (IS_BROXTON(dev))
5026                                 ss_cnt++;
5027
5028                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5029                                                eu_mask[ss%2]);
5030                         stat->eu_total += eu_cnt;
5031                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5032                                                     eu_cnt);
5033                 }
5034
5035                 stat->subslice_total += ss_cnt;
5036                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5037                                                ss_cnt);
5038         }
5039 }
5040
5041 static int i915_sseu_status(struct seq_file *m, void *unused)
5042 {
5043         struct drm_info_node *node = (struct drm_info_node *) m->private;
5044         struct drm_device *dev = node->minor->dev;
5045         struct sseu_dev_status stat;
5046
5047         if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
5048                 return -ENODEV;
5049
5050         seq_puts(m, "SSEU Device Info\n");
5051         seq_printf(m, "  Available Slice Total: %u\n",
5052                    INTEL_INFO(dev)->slice_total);
5053         seq_printf(m, "  Available Subslice Total: %u\n",
5054                    INTEL_INFO(dev)->subslice_total);
5055         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5056                    INTEL_INFO(dev)->subslice_per_slice);
5057         seq_printf(m, "  Available EU Total: %u\n",
5058                    INTEL_INFO(dev)->eu_total);
5059         seq_printf(m, "  Available EU Per Subslice: %u\n",
5060                    INTEL_INFO(dev)->eu_per_subslice);
5061         seq_printf(m, "  Has Slice Power Gating: %s\n",
5062                    yesno(INTEL_INFO(dev)->has_slice_pg));
5063         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5064                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5065         seq_printf(m, "  Has EU Power Gating: %s\n",
5066                    yesno(INTEL_INFO(dev)->has_eu_pg));
5067
5068         seq_puts(m, "SSEU Device Status\n");
5069         memset(&stat, 0, sizeof(stat));
5070         if (IS_CHERRYVIEW(dev)) {
5071                 cherryview_sseu_device_status(dev, &stat);
5072         } else if (INTEL_INFO(dev)->gen >= 9) {
5073                 gen9_sseu_device_status(dev, &stat);
5074         }
5075         seq_printf(m, "  Enabled Slice Total: %u\n",
5076                    stat.slice_total);
5077         seq_printf(m, "  Enabled Subslice Total: %u\n",
5078                    stat.subslice_total);
5079         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5080                    stat.subslice_per_slice);
5081         seq_printf(m, "  Enabled EU Total: %u\n",
5082                    stat.eu_total);
5083         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5084                    stat.eu_per_subslice);
5085
5086         return 0;
5087 }
5088
5089 static int i915_forcewake_open(struct inode *inode, struct file *file)
5090 {
5091         struct drm_device *dev = inode->i_private;
5092         struct drm_i915_private *dev_priv = dev->dev_private;
5093
5094         if (INTEL_INFO(dev)->gen < 6)
5095                 return 0;
5096
5097         intel_runtime_pm_get(dev_priv);
5098         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5099
5100         return 0;
5101 }
5102
5103 static int i915_forcewake_release(struct inode *inode, struct file *file)
5104 {
5105         struct drm_device *dev = inode->i_private;
5106         struct drm_i915_private *dev_priv = dev->dev_private;
5107
5108         if (INTEL_INFO(dev)->gen < 6)
5109                 return 0;
5110
5111         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5112         intel_runtime_pm_put(dev_priv);
5113
5114         return 0;
5115 }
5116
5117 static const struct file_operations i915_forcewake_fops = {
5118         .owner = THIS_MODULE,
5119         .open = i915_forcewake_open,
5120         .release = i915_forcewake_release,
5121 };
5122
5123 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5124 {
5125         struct drm_device *dev = minor->dev;
5126         struct dentry *ent;
5127
5128         ent = debugfs_create_file("i915_forcewake_user",
5129                                   S_IRUSR,
5130                                   root, dev,
5131                                   &i915_forcewake_fops);
5132         if (!ent)
5133                 return -ENOMEM;
5134
5135         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5136 }
5137
5138 static int i915_debugfs_create(struct dentry *root,
5139                                struct drm_minor *minor,
5140                                const char *name,
5141                                const struct file_operations *fops)
5142 {
5143         struct drm_device *dev = minor->dev;
5144         struct dentry *ent;
5145
5146         ent = debugfs_create_file(name,
5147                                   S_IRUGO | S_IWUSR,
5148                                   root, dev,
5149                                   fops);
5150         if (!ent)
5151                 return -ENOMEM;
5152
5153         return drm_add_fake_info_node(minor, ent, fops);
5154 }
5155
5156 static const struct drm_info_list i915_debugfs_list[] = {
5157         {"i915_capabilities", i915_capabilities, 0},
5158         {"i915_gem_objects", i915_gem_object_info, 0},
5159         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5160         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5161         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5162         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5163         {"i915_gem_stolen", i915_gem_stolen_list_info },
5164         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5165         {"i915_gem_request", i915_gem_request_info, 0},
5166         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5167         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5168         {"i915_gem_interrupt", i915_interrupt_info, 0},
5169         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5170         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5171         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5172         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5173         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5174         {"i915_guc_info", i915_guc_info, 0},
5175         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5176         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5177         {"i915_frequency_info", i915_frequency_info, 0},
5178         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5179         {"i915_drpc_info", i915_drpc_info, 0},
5180         {"i915_emon_status", i915_emon_status, 0},
5181         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5182         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5183         {"i915_fbc_status", i915_fbc_status, 0},
5184         {"i915_ips_status", i915_ips_status, 0},
5185         {"i915_sr_status", i915_sr_status, 0},
5186         {"i915_opregion", i915_opregion, 0},
5187         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5188         {"i915_context_status", i915_context_status, 0},
5189         {"i915_dump_lrc", i915_dump_lrc, 0},
5190         {"i915_execlists", i915_execlists, 0},
5191         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5192         {"i915_swizzle_info", i915_swizzle_info, 0},
5193         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5194         {"i915_llc", i915_llc, 0},
5195         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5196         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5197         {"i915_energy_uJ", i915_energy_uJ, 0},
5198         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5199         {"i915_power_domain_info", i915_power_domain_info, 0},
5200         {"i915_display_info", i915_display_info, 0},
5201         {"i915_semaphore_status", i915_semaphore_status, 0},
5202         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5203         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5204         {"i915_wa_registers", i915_wa_registers, 0},
5205         {"i915_ddb_info", i915_ddb_info, 0},
5206         {"i915_sseu_status", i915_sseu_status, 0},
5207         {"i915_drrs_status", i915_drrs_status, 0},
5208         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5209 };
5210 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5211
5212 static const struct i915_debugfs_files {
5213         const char *name;
5214         const struct file_operations *fops;
5215 } i915_debugfs_files[] = {
5216         {"i915_wedged", &i915_wedged_fops},
5217         {"i915_max_freq", &i915_max_freq_fops},
5218         {"i915_min_freq", &i915_min_freq_fops},
5219         {"i915_cache_sharing", &i915_cache_sharing_fops},
5220         {"i915_ring_stop", &i915_ring_stop_fops},
5221         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5222         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5223         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5224         {"i915_error_state", &i915_error_state_fops},
5225         {"i915_next_seqno", &i915_next_seqno_fops},
5226         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5227         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5228         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5229         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5230         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5231         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5232         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5233         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5234 };
5235
5236 void intel_display_crc_init(struct drm_device *dev)
5237 {
5238         struct drm_i915_private *dev_priv = dev->dev_private;
5239         enum pipe pipe;
5240
5241         for_each_pipe(dev_priv, pipe) {
5242                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5243
5244                 pipe_crc->opened = false;
5245                 spin_lock_init(&pipe_crc->lock);
5246                 init_waitqueue_head(&pipe_crc->wq);
5247         }
5248 }
5249
5250 int i915_debugfs_init(struct drm_minor *minor)
5251 {
5252         int ret, i;
5253
5254         ret = i915_forcewake_create(minor->debugfs_root, minor);
5255         if (ret)
5256                 return ret;
5257
5258         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5259                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5260                 if (ret)
5261                         return ret;
5262         }
5263
5264         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5265                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5266                                           i915_debugfs_files[i].name,
5267                                           i915_debugfs_files[i].fops);
5268                 if (ret)
5269                         return ret;
5270         }
5271
5272         return drm_debugfs_create_files(i915_debugfs_list,
5273                                         I915_DEBUGFS_ENTRIES,
5274                                         minor->debugfs_root, minor);
5275 }
5276
5277 void i915_debugfs_cleanup(struct drm_minor *minor)
5278 {
5279         int i;
5280
5281         drm_debugfs_remove_files(i915_debugfs_list,
5282                                  I915_DEBUGFS_ENTRIES, minor);
5283
5284         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5285                                  1, minor);
5286
5287         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5288                 struct drm_info_list *info_list =
5289                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5290
5291                 drm_debugfs_remove_files(info_list, 1, minor);
5292         }
5293
5294         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5295                 struct drm_info_list *info_list =
5296                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5297
5298                 drm_debugfs_remove_files(info_list, 1, minor);
5299         }
5300 }
5301
5302 struct dpcd_block {
5303         /* DPCD dump start address. */
5304         unsigned int offset;
5305         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5306         unsigned int end;
5307         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5308         size_t size;
5309         /* Only valid for eDP. */
5310         bool edp;
5311 };
5312
5313 static const struct dpcd_block i915_dpcd_debug[] = {
5314         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5315         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5316         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5317         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5318         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5319         { .offset = DP_SET_POWER },
5320         { .offset = DP_EDP_DPCD_REV },
5321         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5322         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5323         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5324 };
5325
5326 static int i915_dpcd_show(struct seq_file *m, void *data)
5327 {
5328         struct drm_connector *connector = m->private;
5329         struct intel_dp *intel_dp =
5330                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5331         uint8_t buf[16];
5332         ssize_t err;
5333         int i;
5334
5335         if (connector->status != connector_status_connected)
5336                 return -ENODEV;
5337
5338         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5339                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5340                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5341
5342                 if (b->edp &&
5343                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5344                         continue;
5345
5346                 /* low tech for now */
5347                 if (WARN_ON(size > sizeof(buf)))
5348                         continue;
5349
5350                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5351                 if (err <= 0) {
5352                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5353                                   size, b->offset, err);
5354                         continue;
5355                 }
5356
5357                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5358         }
5359
5360         return 0;
5361 }
5362
5363 static int i915_dpcd_open(struct inode *inode, struct file *file)
5364 {
5365         return single_open(file, i915_dpcd_show, inode->i_private);
5366 }
5367
5368 static const struct file_operations i915_dpcd_fops = {
5369         .owner = THIS_MODULE,
5370         .open = i915_dpcd_open,
5371         .read = seq_read,
5372         .llseek = seq_lseek,
5373         .release = single_release,
5374 };
5375
5376 /**
5377  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5378  * @connector: pointer to a registered drm_connector
5379  *
5380  * Cleanup will be done by drm_connector_unregister() through a call to
5381  * drm_debugfs_connector_remove().
5382  *
5383  * Returns 0 on success, negative error codes on error.
5384  */
5385 int i915_debugfs_connector_add(struct drm_connector *connector)
5386 {
5387         struct dentry *root = connector->debugfs_entry;
5388
5389         /* The connector must have been registered beforehands. */
5390         if (!root)
5391                 return -ENODEV;
5392
5393         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5394             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5395                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5396                                     &i915_dpcd_fops);
5397
5398         return 0;
5399 }