2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
36 #include "i915_pvinfo.h"
38 void populate_pvinfo_page(struct intel_vgpu *vgpu)
40 /* setup the ballooning information */
41 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
42 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
43 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
44 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
45 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
47 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
51 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
52 vgpu_aperture_gmadr_base(vgpu);
53 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
54 vgpu_aperture_sz(vgpu);
55 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
56 vgpu_hidden_gmadr_base(vgpu);
57 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
60 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
62 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
63 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
65 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
66 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
67 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
68 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
69 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
70 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
72 WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
75 #define VGPU_MAX_WEIGHT 16
76 #define VGPU_WEIGHT(vgpu_num) \
77 (VGPU_MAX_WEIGHT / (vgpu_num))
84 /* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
85 * with a weight of 4 on a contended host, different vGPU type has
86 * different weight set. Legal weights range from 1 to 16.
89 enum intel_vgpu_edid edid;
92 /* Fixed vGPU type table */
93 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
94 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
95 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
96 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
100 * intel_gvt_init_vgpu_types - initialize vGPU type list
103 * Initialize vGPU type list based on available resource.
106 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
108 unsigned int num_types;
109 unsigned int i, low_avail, high_avail;
110 unsigned int min_low;
112 /* vGPU type name is defined as GVTg_Vx_y which contains
113 * physical GPU generation type (e.g V4 as BDW server, V5 as
116 * Depend on physical SKU resource, might see vGPU types like
117 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
118 * different types of vGPU on same physical GPU depending on
119 * available resource. Each vGPU type will have "avail_instance"
120 * to indicate how many vGPU instance can be created for this
124 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
125 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
126 num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
128 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
133 min_low = MB_TO_BYTES(32);
134 for (i = 0; i < num_types; ++i) {
135 if (low_avail / vgpu_types[i].low_mm == 0)
138 gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
139 gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
140 gvt->types[i].fence = vgpu_types[i].fence;
142 if (vgpu_types[i].weight < 1 ||
143 vgpu_types[i].weight > VGPU_MAX_WEIGHT)
146 gvt->types[i].weight = vgpu_types[i].weight;
147 gvt->types[i].resolution = vgpu_types[i].edid;
148 gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
149 high_avail / vgpu_types[i].high_mm);
151 if (IS_GEN(gvt->dev_priv, 8))
152 sprintf(gvt->types[i].name, "GVTg_V4_%s",
154 else if (IS_GEN(gvt->dev_priv, 9))
155 sprintf(gvt->types[i].name, "GVTg_V5_%s",
158 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
159 i, gvt->types[i].name,
160 gvt->types[i].avail_instance,
161 gvt->types[i].low_gm_size,
162 gvt->types[i].high_gm_size, gvt->types[i].fence,
163 gvt->types[i].weight,
164 vgpu_edid_str(gvt->types[i].resolution));
171 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
176 static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
179 unsigned int low_gm_avail, high_gm_avail, fence_avail;
180 unsigned int low_gm_min, high_gm_min, fence_min;
182 /* Need to depend on maxium hw resource size but keep on
183 * static config for now.
185 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
186 gvt->gm.vgpu_allocated_low_gm_size;
187 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
188 gvt->gm.vgpu_allocated_high_gm_size;
189 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
190 gvt->fence.vgpu_allocated_fence_num;
192 for (i = 0; i < gvt->num_types; i++) {
193 low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
194 high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
195 fence_min = fence_avail / gvt->types[i].fence;
196 gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
199 gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
200 i, gvt->types[i].name,
201 gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
202 gvt->types[i].high_gm_size, gvt->types[i].fence);
207 * intel_gvt_active_vgpu - activate a virtual GPU
210 * This function is called when user wants to activate a virtual GPU.
213 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
215 mutex_lock(&vgpu->vgpu_lock);
217 mutex_unlock(&vgpu->vgpu_lock);
221 * intel_gvt_deactive_vgpu - deactivate a virtual GPU
224 * This function is called when user wants to deactivate a virtual GPU.
225 * The virtual GPU will be stopped.
228 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
230 mutex_lock(&vgpu->vgpu_lock);
232 vgpu->active = false;
234 if (atomic_read(&vgpu->submission.running_workload_num)) {
235 mutex_unlock(&vgpu->vgpu_lock);
236 intel_gvt_wait_vgpu_idle(vgpu);
237 mutex_lock(&vgpu->vgpu_lock);
240 intel_vgpu_stop_schedule(vgpu);
242 mutex_unlock(&vgpu->vgpu_lock);
246 * intel_gvt_release_vgpu - release a virtual GPU
249 * This function is called when user wants to release a virtual GPU.
250 * The virtual GPU will be stopped and all runtime information will be
254 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
256 intel_gvt_deactivate_vgpu(vgpu);
258 mutex_lock(&vgpu->vgpu_lock);
259 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
260 intel_vgpu_dmabuf_cleanup(vgpu);
261 mutex_unlock(&vgpu->vgpu_lock);
265 * intel_gvt_destroy_vgpu - destroy a virtual GPU
268 * This function is called when user wants to destroy a virtual GPU.
271 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
273 struct intel_gvt *gvt = vgpu->gvt;
275 WARN(vgpu->active, "vGPU is still active!\n");
278 * remove idr first so later clean can judge if need to stop
279 * service if no active vgpu.
281 mutex_lock(&gvt->lock);
282 idr_remove(&gvt->vgpu_idr, vgpu->id);
283 mutex_unlock(&gvt->lock);
285 mutex_lock(&vgpu->vgpu_lock);
286 intel_gvt_debugfs_remove_vgpu(vgpu);
287 intel_vgpu_clean_sched_policy(vgpu);
288 intel_vgpu_clean_submission(vgpu);
289 intel_vgpu_clean_display(vgpu);
290 intel_vgpu_clean_opregion(vgpu);
291 intel_vgpu_reset_ggtt(vgpu, true);
292 intel_vgpu_clean_gtt(vgpu);
293 intel_gvt_hypervisor_detach_vgpu(vgpu);
294 intel_vgpu_free_resource(vgpu);
295 intel_vgpu_clean_mmio(vgpu);
296 intel_vgpu_dmabuf_cleanup(vgpu);
297 mutex_unlock(&vgpu->vgpu_lock);
299 mutex_lock(&gvt->lock);
300 if (idr_is_empty(&gvt->vgpu_idr))
301 intel_gvt_clean_irq(gvt);
302 intel_gvt_update_vgpu_types(gvt);
303 mutex_unlock(&gvt->lock);
308 #define IDLE_VGPU_IDR 0
311 * intel_gvt_create_idle_vgpu - create an idle virtual GPU
314 * This function is called when user wants to create an idle virtual GPU.
317 * pointer to intel_vgpu, error pointer if failed.
319 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
321 struct intel_vgpu *vgpu;
322 enum intel_engine_id i;
325 vgpu = vzalloc(sizeof(*vgpu));
327 return ERR_PTR(-ENOMEM);
329 vgpu->id = IDLE_VGPU_IDR;
331 mutex_init(&vgpu->vgpu_lock);
333 for (i = 0; i < I915_NUM_ENGINES; i++)
334 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
336 ret = intel_vgpu_init_sched_policy(vgpu);
340 vgpu->active = false;
350 * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
353 * This function is called when user wants to destroy an idle virtual GPU.
356 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
358 mutex_lock(&vgpu->vgpu_lock);
359 intel_vgpu_clean_sched_policy(vgpu);
360 mutex_unlock(&vgpu->vgpu_lock);
365 static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
366 struct intel_vgpu_creation_params *param)
368 struct intel_vgpu *vgpu;
371 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
372 param->handle, param->low_gm_sz, param->high_gm_sz,
375 vgpu = vzalloc(sizeof(*vgpu));
377 return ERR_PTR(-ENOMEM);
379 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
385 vgpu->handle = param->handle;
387 vgpu->sched_ctl.weight = param->weight;
388 mutex_init(&vgpu->vgpu_lock);
389 mutex_init(&vgpu->dmabuf_lock);
390 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
391 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
392 idr_init(&vgpu->object_idr);
393 intel_vgpu_init_cfg_space(vgpu, param->primary);
395 ret = intel_vgpu_init_mmio(vgpu);
399 ret = intel_vgpu_alloc_resource(vgpu, param);
401 goto out_clean_vgpu_mmio;
403 populate_pvinfo_page(vgpu);
405 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
407 goto out_clean_vgpu_resource;
409 ret = intel_vgpu_init_gtt(vgpu);
411 goto out_detach_hypervisor_vgpu;
413 ret = intel_vgpu_init_opregion(vgpu);
417 ret = intel_vgpu_init_display(vgpu, param->resolution);
419 goto out_clean_opregion;
421 ret = intel_vgpu_setup_submission(vgpu);
423 goto out_clean_display;
425 ret = intel_vgpu_init_sched_policy(vgpu);
427 goto out_clean_submission;
429 intel_gvt_debugfs_add_vgpu(vgpu);
431 ret = intel_gvt_hypervisor_set_opregion(vgpu);
433 goto out_clean_sched_policy;
435 /*TODO: add more platforms support */
436 if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv))
437 ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
439 goto out_clean_sched_policy;
443 out_clean_sched_policy:
444 intel_vgpu_clean_sched_policy(vgpu);
445 out_clean_submission:
446 intel_vgpu_clean_submission(vgpu);
448 intel_vgpu_clean_display(vgpu);
450 intel_vgpu_clean_opregion(vgpu);
452 intel_vgpu_clean_gtt(vgpu);
453 out_detach_hypervisor_vgpu:
454 intel_gvt_hypervisor_detach_vgpu(vgpu);
455 out_clean_vgpu_resource:
456 intel_vgpu_free_resource(vgpu);
458 intel_vgpu_clean_mmio(vgpu);
460 idr_remove(&gvt->vgpu_idr, vgpu->id);
467 * intel_gvt_create_vgpu - create a virtual GPU
469 * @type: type of the vGPU to create
471 * This function is called when user wants to create a virtual GPU.
474 * pointer to intel_vgpu, error pointer if failed.
476 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
477 struct intel_vgpu_type *type)
479 struct intel_vgpu_creation_params param;
480 struct intel_vgpu *vgpu;
484 param.low_gm_sz = type->low_gm_size;
485 param.high_gm_sz = type->high_gm_size;
486 param.fence_sz = type->fence;
487 param.weight = type->weight;
488 param.resolution = type->resolution;
490 /* XXX current param based on MB */
491 param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
492 param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
494 mutex_lock(&gvt->lock);
495 vgpu = __intel_gvt_create_vgpu(gvt, ¶m);
497 /* calculate left instance change for types */
498 intel_gvt_update_vgpu_types(gvt);
499 mutex_unlock(&gvt->lock);
505 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
507 * @dmlr: vGPU Device Model Level Reset or GT Reset
508 * @engine_mask: engines to reset for GT reset
510 * This function is called when user wants to reset a virtual GPU through
511 * device model reset or GT reset. The caller should hold the vgpu lock.
513 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
514 * the whole vGPU to default state as when it is created. This vGPU function
515 * is required both for functionary and security concerns.The ultimate goal
516 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
517 * assign a vGPU to a virtual machine we must isse such reset first.
519 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
520 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
521 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
522 * the reset request. Guest driver can issue a GT reset by programming the
523 * virtual GDRST register to reset specific virtual GPU engine or all
526 * The parameter dev_level is to identify if we will do DMLR or GT reset.
527 * The parameter engine_mask is to specific the engines that need to be
528 * resetted. If value ALL_ENGINES is given for engine_mask, it means
529 * the caller requests a full GT reset that we will reset all virtual
530 * GPU engines. For FLR, engine_mask is ignored.
532 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
533 intel_engine_mask_t engine_mask)
535 struct intel_gvt *gvt = vgpu->gvt;
536 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
537 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
539 gvt_dbg_core("------------------------------------------\n");
540 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
541 vgpu->id, dmlr, engine_mask);
543 vgpu->resetting_eng = resetting_eng;
545 intel_vgpu_stop_schedule(vgpu);
547 * The current_vgpu will set to NULL after stopping the
548 * scheduler when the reset is triggered by current vgpu.
550 if (scheduler->current_vgpu == NULL) {
551 mutex_unlock(&vgpu->vgpu_lock);
552 intel_gvt_wait_vgpu_idle(vgpu);
553 mutex_lock(&vgpu->vgpu_lock);
556 intel_vgpu_reset_submission(vgpu, resetting_eng);
557 /* full GPU reset or device model level reset */
558 if (engine_mask == ALL_ENGINES || dmlr) {
559 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
560 intel_vgpu_invalidate_ppgtt(vgpu);
561 /*fence will not be reset during virtual reset */
563 intel_vgpu_reset_gtt(vgpu);
564 intel_vgpu_reset_resource(vgpu);
567 intel_vgpu_reset_mmio(vgpu, dmlr);
568 populate_pvinfo_page(vgpu);
571 intel_vgpu_reset_display(vgpu);
572 intel_vgpu_reset_cfg_space(vgpu);
573 /* only reset the failsafe mode when dmlr reset */
574 vgpu->failsafe = false;
575 vgpu->pv_notified = false;
579 vgpu->resetting_eng = 0;
580 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
581 gvt_dbg_core("------------------------------------------\n");
585 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
588 * This function is called when user wants to reset a virtual GPU.
591 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
593 mutex_lock(&vgpu->vgpu_lock);
594 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
595 mutex_unlock(&vgpu->vgpu_lock);