drivers/gpu/drm/i915/gvt/interrupt.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Kevin Tian <kevin.tian@intel.com>
  25  *    Zhi Wang <zhi.a.wang@intel.com>
  26  *
  27  * Contributors:
  28  *    Min he <min.he@intel.com>
  29  *
  30  */
  31
  32 #include "i915_drv.h"
  33
  34 /* common offset among interrupt control registers */
  35 #define regbase_to_isr(base)    (base)
  36 #define regbase_to_imr(base)    (base + 0x4)
  37 #define regbase_to_iir(base)    (base + 0x8)
  38 #define regbase_to_ier(base)    (base + 0xC)
  39
  40 #define iir_to_regbase(iir)    (iir - 0x8)
  41 #define ier_to_regbase(ier)    (ier - 0xC)
  42
  43 #define get_event_virt_handler(irq, e)  (irq->events[e].v_handler)
  44 #define get_irq_info(irq, e)            (irq->events[e].info)
  45
  46 #define irq_to_gvt(irq) \
  47         container_of(irq, struct intel_gvt, irq)
  48
  49 static void update_upstream_irq(struct intel_vgpu *vgpu,
  50                 struct intel_gvt_irq_info *info);
  51
  52 const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
  53         [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
  54         [RCS_DEBUG] = "Render EU debug from SVG",
  55         [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
  56         [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt",
  57         [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify",
  58         [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded",
  59         [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults",
  60         [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt",
  61
  62         [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT",
  63         [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status",
  64         [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt",
  65         [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify",
  66         [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded",
  67         [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults",
  68         [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt",
  69         [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT",
  70         [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify",
  71         [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt",
  72
  73         [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT",
  74         [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status",
  75         [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt",
  76         [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify",
  77         [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults",
  78         [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt",
  79
  80         [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify",
  81         [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt",
  82
  83         [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun",
  84         [PIPE_A_CRC_ERR] = "Pipe A CRC error",
  85         [PIPE_A_CRC_DONE] = "Pipe A CRC done",
  86         [PIPE_A_VSYNC] = "Pipe A vsync",
  87         [PIPE_A_LINE_COMPARE] = "Pipe A line compare",
  88         [PIPE_A_ODD_FIELD] = "Pipe A odd field",
  89         [PIPE_A_EVEN_FIELD] = "Pipe A even field",
  90         [PIPE_A_VBLANK] = "Pipe A vblank",
  91         [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun",
  92         [PIPE_B_CRC_ERR] = "Pipe B CRC error",
  93         [PIPE_B_CRC_DONE] = "Pipe B CRC done",
  94         [PIPE_B_VSYNC] = "Pipe B vsync",
  95         [PIPE_B_LINE_COMPARE] = "Pipe B line compare",
  96         [PIPE_B_ODD_FIELD] = "Pipe B odd field",
  97         [PIPE_B_EVEN_FIELD] = "Pipe B even field",
  98         [PIPE_B_VBLANK] = "Pipe B vblank",
  99         [PIPE_C_VBLANK] = "Pipe C vblank",
 100         [DPST_PHASE_IN] = "DPST phase in event",
 101         [DPST_HISTOGRAM] = "DPST histogram event",
 102         [GSE] = "GSE",
 103         [DP_A_HOTPLUG] = "DP A Hotplug",
 104         [AUX_CHANNEL_A] = "AUX Channel A",
 105         [PERF_COUNTER] = "Performance counter",
 106         [POISON] = "Poison",
 107         [GTT_FAULT] = "GTT fault",
 108         [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done",
 109         [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done",
 110         [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done",
 111         [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done",
 112         [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done",
 113         [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done",
 114
 115         [PCU_THERMAL] = "PCU Thermal Event",
 116         [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event",
 117
 118         [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A",
 119         [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A",
 120         [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A",
 121         [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B",
 122         [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B",
 123         [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B",
 124         [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
 125         [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
 126         [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
 127         [ERR_AND_DBG] = "South Error and Debug Interupts Combined",
 128         [GMBUS] = "Gmbus",
 129         [SDVO_B_HOTPLUG] = "SDVO B hotplug",
 130         [CRT_HOTPLUG] = "CRT Hotplug",
 131         [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug",
 132         [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug",
 133         [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug",
 134         [AUX_CHANNEL_B] = "AUX Channel B",
 135         [AUX_CHANNEL_C] = "AUX Channel C",
 136         [AUX_CHANNEL_D] = "AUX Channel D",
 137         [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B",
 138         [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C",
 139         [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D",
 140
 141         [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!",
 142 };
 143
 144 static inline struct intel_gvt_irq_info *regbase_to_irq_info(
 145                 struct intel_gvt *gvt,
 146                 unsigned int reg)
 147 {
 148         struct intel_gvt_irq *irq = &gvt->irq;
 149         int i;
 150
 151         for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
 152                 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
 153                         return irq->info[i];
 154         }
 155
 156         return NULL;
 157 }
 158
 159 /**
 160  * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
 161  * @vgpu: a vGPU
 162  * @reg: register offset written by guest
 163  * @p_data: register data written by guest
 164  * @bytes: register data length
 165  *
 166  * This function is used to emulate the generic IMR register bit change
 167  * behavior.
 168  *
 169  * Returns:
 170  * Zero on success, negative error code if failed.
 171  *
 172  */
 173 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
 174         unsigned int reg, void *p_data, unsigned int bytes)
 175 {
 176         struct intel_gvt *gvt = vgpu->gvt;
 177         struct intel_gvt_irq_ops *ops = gvt->irq.ops;
 178         u32 changed, masked, unmasked;
 179         u32 imr = *(u32 *)p_data;
 180
 181         gvt_dbg_irq("write IMR %x with val %x\n",
 182                 reg, imr);
 183
 184         gvt_dbg_irq("old vIMR %x\n", vgpu_vreg(vgpu, reg));
 185
 186         /* figure out newly masked/unmasked bits */
 187         changed = vgpu_vreg(vgpu, reg) ^ imr;
 188         masked = (vgpu_vreg(vgpu, reg) & changed) ^ changed;
 189         unmasked = masked ^ changed;
 190
 191         gvt_dbg_irq("changed %x, masked %x, unmasked %x\n",
 192                 changed, masked, unmasked);
 193
 194         vgpu_vreg(vgpu, reg) = imr;
 195
 196         ops->check_pending_irq(vgpu);
 197         gvt_dbg_irq("IRQ: new vIMR %x\n", vgpu_vreg(vgpu, reg));
 198         return 0;
 199 }
 200
 201 /**
 202  * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
 203  * @vgpu: a vGPU
 204  * @reg: register offset written by guest
 205  * @p_data: register data written by guest
 206  * @bytes: register data length
 207  *
 208  * This function is used to emulate the master IRQ register on gen8+.
 209  *
 210  * Returns:
 211  * Zero on success, negative error code if failed.
 212  *
 213  */
 214 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
 215         unsigned int reg, void *p_data, unsigned int bytes)
 216 {
 217         struct intel_gvt *gvt = vgpu->gvt;
 218         struct intel_gvt_irq_ops *ops = gvt->irq.ops;
 219         u32 changed, enabled, disabled;
 220         u32 ier = *(u32 *)p_data;
 221         u32 virtual_ier = vgpu_vreg(vgpu, reg);
 222
 223         gvt_dbg_irq("write master irq reg %x with val %x\n",
 224                 reg, ier);
 225
 226         gvt_dbg_irq("old vreg %x\n", vgpu_vreg(vgpu, reg));
 227
 228         /*
 229          * GEN8_MASTER_IRQ is a special irq register,
 230          * only bit 31 is allowed to be modified
 231          * and treated as an IER bit.
 232          */
 233         ier &= GEN8_MASTER_IRQ_CONTROL;
 234         virtual_ier &= GEN8_MASTER_IRQ_CONTROL;
 235         vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
 236         vgpu_vreg(vgpu, reg) |= ier;
 237
 238         /* figure out newly enabled/disable bits */
 239         changed = virtual_ier ^ ier;
 240         enabled = (virtual_ier & changed) ^ changed;
 241         disabled = enabled ^ changed;
 242
 243         gvt_dbg_irq("changed %x, enabled %x, disabled %x\n",
 244                         changed, enabled, disabled);
 245
 246         ops->check_pending_irq(vgpu);
 247         gvt_dbg_irq("new vreg %x\n", vgpu_vreg(vgpu, reg));
 248         return 0;
 249 }
 250
 251 /**
 252  * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
 253  * @vgpu: a vGPU
 254  * @reg: register offset written by guest
 255  * @p_data: register data written by guest
 256  * @bytes: register data length
 257  *
 258  * This function is used to emulate the generic IER register behavior.
 259  *
 260  * Returns:
 261  * Zero on success, negative error code if failed.
 262  *
 263  */
 264 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
 265         unsigned int reg, void *p_data, unsigned int bytes)
 266 {
 267         struct intel_gvt *gvt = vgpu->gvt;
 268         struct intel_gvt_irq_ops *ops = gvt->irq.ops;
 269         struct intel_gvt_irq_info *info;
 270         u32 changed, enabled, disabled;
 271         u32 ier = *(u32 *)p_data;
 272
 273         gvt_dbg_irq("write IER %x with val %x\n",
 274                 reg, ier);
 275
 276         gvt_dbg_irq("old vIER %x\n", vgpu_vreg(vgpu, reg));
 277
 278         /* figure out newly enabled/disable bits */
 279         changed = vgpu_vreg(vgpu, reg) ^ ier;
 280         enabled = (vgpu_vreg(vgpu, reg) & changed) ^ changed;
 281         disabled = enabled ^ changed;
 282
 283         gvt_dbg_irq("changed %x, enabled %x, disabled %x\n",
 284                         changed, enabled, disabled);
 285         vgpu_vreg(vgpu, reg) = ier;
 286
 287         info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
 288         if (WARN_ON(!info))
 289                 return -EINVAL;
 290
 291         if (info->has_upstream_irq)
 292                 update_upstream_irq(vgpu, info);
 293
 294         ops->check_pending_irq(vgpu);
 295         gvt_dbg_irq("new vIER %x\n", vgpu_vreg(vgpu, reg));
 296         return 0;
 297 }
 298
 299 /**
 300  * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
 301  * @vgpu: a vGPU
 302  * @reg: register offset written by guest
 303  * @p_data: register data written by guest
 304  * @bytes: register data length
 305  *
 306  * This function is used to emulate the generic IIR register behavior.
 307  *
 308  * Returns:
 309  * Zero on success, negative error code if failed.
 310  *
 311  */
 312 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
 313         void *p_data, unsigned int bytes)
 314 {
 315         struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
 316                 iir_to_regbase(reg));
 317         u32 iir = *(u32 *)p_data;
 318
 319         gvt_dbg_irq("write IIR %x with val %x\n", reg, iir);
 320
 321         if (WARN_ON(!info))
 322                 return -EINVAL;
 323
 324         vgpu_vreg(vgpu, reg) &= ~iir;
 325
 326         if (info->has_upstream_irq)
 327                 update_upstream_irq(vgpu, info);
 328         return 0;
 329 }
 330
 331 static struct intel_gvt_irq_map gen8_irq_map[] = {
 332         { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
 333         { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
 334         { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff },
 335         { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 },
 336         { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff },
 337         { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff },
 338         { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
 339         { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
 340         { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 },
 341         { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 },
 342         { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 },
 343         { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 },
 344         { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 },
 345         { -1, -1, ~0 },
 346 };
 347
 348 static void update_upstream_irq(struct intel_vgpu *vgpu,
 349                 struct intel_gvt_irq_info *info)
 350 {
 351         struct intel_gvt_irq *irq = &vgpu->gvt->irq;
 352         struct intel_gvt_irq_map *map = irq->irq_map;
 353         struct intel_gvt_irq_info *up_irq_info = NULL;
 354         u32 set_bits = 0;
 355         u32 clear_bits = 0;
 356         int bit;
 357         u32 val = vgpu_vreg(vgpu,
 358                         regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
 359                 & vgpu_vreg(vgpu,
 360                         regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
 361
 362         if (!info->has_upstream_irq)
 363                 return;
 364
 365         for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
 366                 if (info->group != map->down_irq_group)
 367                         continue;
 368
 369                 if (!up_irq_info)
 370                         up_irq_info = irq->info[map->up_irq_group];
 371                 else
 372                         WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
 373
 374                 bit = map->up_irq_bit;
 375
 376                 if (val & map->down_irq_bitmask)
 377                         set_bits |= (1 << bit);
 378                 else
 379                         clear_bits |= (1 << bit);
 380         }
 381
 382         WARN_ON(!up_irq_info);
 383
 384         if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
 385                 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
 386
 387                 vgpu_vreg(vgpu, isr) &= ~clear_bits;
 388                 vgpu_vreg(vgpu, isr) |= set_bits;
 389         } else {
 390                 u32 iir = regbase_to_iir(
 391                         i915_mmio_reg_offset(up_irq_info->reg_base));
 392                 u32 imr = regbase_to_imr(
 393                         i915_mmio_reg_offset(up_irq_info->reg_base));
 394
 395                 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
 396         }
 397
 398         if (up_irq_info->has_upstream_irq)
 399                 update_upstream_irq(vgpu, up_irq_info);
 400 }
 401
 402 static void init_irq_map(struct intel_gvt_irq *irq)
 403 {
 404         struct intel_gvt_irq_map *map;
 405         struct intel_gvt_irq_info *up_info, *down_info;
 406         int up_bit;
 407
 408         for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
 409                 up_info = irq->info[map->up_irq_group];
 410                 up_bit = map->up_irq_bit;
 411                 down_info = irq->info[map->down_irq_group];
 412
 413                 set_bit(up_bit, up_info->downstream_irq_bitmap);
 414                 down_info->has_upstream_irq = true;
 415
 416                 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",
 417                         up_info->group, up_bit,
 418                         down_info->group, map->down_irq_bitmask);
 419         }
 420 }
 421
 422 /* =======================vEvent injection===================== */
 423 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
 424 {
 425         return intel_gvt_hypervisor_inject_msi(vgpu);
 426 }
 427
 428 static void propagate_event(struct intel_gvt_irq *irq,
 429         enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
 430 {
 431         struct intel_gvt_irq_info *info;
 432         unsigned int reg_base;
 433         int bit;
 434
 435         info = get_irq_info(irq, event);
 436         if (WARN_ON(!info))
 437                 return;
 438
 439         reg_base = i915_mmio_reg_offset(info->reg_base);
 440         bit = irq->events[event].bit;
 441
 442         if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
 443                                         regbase_to_imr(reg_base)))) {
 444                 gvt_dbg_irq("set bit (%d) for (%s) for vgpu (%d)\n",
 445                                 bit, irq_name[event], vgpu->id);
 446                 set_bit(bit, (void *)&vgpu_vreg(vgpu,
 447                                         regbase_to_iir(reg_base)));
 448         }
 449 }
 450
 451 /* =======================vEvent Handlers===================== */
 452 static void handle_default_event_virt(struct intel_gvt_irq *irq,
 453         enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
 454 {
 455         if (!vgpu->irq.irq_warn_once[event]) {
 456                 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
 457                         vgpu->id, event, irq_name[event]);
 458                 vgpu->irq.irq_warn_once[event] = true;
 459         }
 460         propagate_event(irq, event, vgpu);
 461 }
 462
 463 /* =====================GEN specific logic======================= */
 464 /* GEN8 interrupt routines. */
 465
 466 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \
 467 static struct intel_gvt_irq_info gen8_##regname##_info = { \
 468         .name = #regname"-IRQ", \
 469         .reg_base = (regbase), \
 470         .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
 471                 INTEL_GVT_EVENT_RESERVED}, \
 472 }
 473
 474 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0));
 475 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
 476 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2));
 477 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3));
 478 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
 479 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
 480 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
 481 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR);
 482 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR);
 483 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR);
 484 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
 485
 486 static struct intel_gvt_irq_info gvt_base_pch_info = {
 487         .name = "PCH-IRQ",
 488         .reg_base = SDEISR,
 489         .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
 490                 INTEL_GVT_EVENT_RESERVED},
 491 };
 492
 493 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
 494 {
 495         struct intel_gvt_irq *irq = &vgpu->gvt->irq;
 496         int i;
 497
 498         if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
 499                                 GEN8_MASTER_IRQ_CONTROL))
 500                 return;
 501
 502         for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
 503                 struct intel_gvt_irq_info *info = irq->info[i];
 504                 u32 reg_base;
 505
 506                 if (!info->has_upstream_irq)
 507                         continue;
 508
 509                 reg_base = i915_mmio_reg_offset(info->reg_base);
 510                 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
 511                                 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
 512                         update_upstream_irq(vgpu, info);
 513         }
 514
 515         if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
 516                         & ~GEN8_MASTER_IRQ_CONTROL)
 517                 inject_virtual_interrupt(vgpu);
 518 }
 519
 520 static void gen8_init_irq(
 521                 struct intel_gvt_irq *irq)
 522 {
 523         struct intel_gvt *gvt = irq_to_gvt(irq);
 524
 525 #define SET_BIT_INFO(s, b, e, i)                \
 526         do {                                    \
 527                 s->events[e].bit = b;           \
 528                 s->events[e].info = s->info[i]; \
 529                 s->info[i]->bit_to_event[b] = e;\
 530         } while (0)
 531
 532 #define SET_IRQ_GROUP(s, g, i) \
 533         do { \
 534                 s->info[g] = i; \
 535                 (i)->group = g; \
 536                 set_bit(g, s->irq_info_bitmap); \
 537         } while (0)
 538
 539         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
 540         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
 541         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
 542         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
 543         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
 544         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
 545         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
 546         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
 547         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
 548         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
 549         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
 550         SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
 551
 552         /* GEN8 level 2 interrupts. */
 553
 554         /* GEN8 interrupt GT0 events */
 555         SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
 556         SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
 557         SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
 558
 559         SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
 560         SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
 561         SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
 562
 563         /* GEN8 interrupt GT1 events */
 564         SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
 565         SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
 566         SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
 567
 568         if (HAS_BSD2(gvt->dev_priv)) {
 569                 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
 570                         INTEL_GVT_IRQ_INFO_GT1);
 571                 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
 572                         INTEL_GVT_IRQ_INFO_GT1);
 573                 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
 574                         INTEL_GVT_IRQ_INFO_GT1);
 575         }
 576
 577         /* GEN8 interrupt GT3 events */
 578         SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
 579         SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
 580         SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
 581
 582         SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
 583         SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
 584         SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
 585
 586         /* GEN8 interrupt DE PORT events */
 587         SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
 588         SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
 589
 590         /* GEN8 interrupt DE MISC events */
 591         SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
 592
 593         /* PCH events */
 594         SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
 595         SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
 596         SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
 597         SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
 598         SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
 599
 600         if (IS_BROADWELL(gvt->dev_priv)) {
 601                 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
 602                 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
 603                 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
 604
 605                 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
 606                 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
 607
 608                 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
 609                 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
 610
 611                 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
 612                 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
 613         } else if (IS_SKYLAKE(gvt->dev_priv)) {
 614                 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
 615                 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
 616                 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
 617
 618                 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
 619                 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
 620                 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
 621         }
 622
 623         /* GEN8 interrupt PCU events */
 624         SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
 625         SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
 626 }
 627
 628 static struct intel_gvt_irq_ops gen8_irq_ops = {
 629         .init_irq = gen8_init_irq,
 630         .check_pending_irq = gen8_check_pending_irq,
 631 };
 632
 633 /**
 634  * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
 635  * @vgpu: a vGPU
 636  * @event: interrupt event
 637  *
 638  * This function is used to trigger a virtual interrupt event for vGPU.
 639  * The caller provides the event to be triggered, the framework itself
 640  * will emulate the IRQ register bit change.
 641  *
 642  */
 643 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
 644         enum intel_gvt_event_type event)
 645 {
 646         struct intel_gvt *gvt = vgpu->gvt;
 647         struct intel_gvt_irq *irq = &gvt->irq;
 648         gvt_event_virt_handler_t handler;
 649         struct intel_gvt_irq_ops *ops = gvt->irq.ops;
 650
 651         handler = get_event_virt_handler(irq, event);
 652         WARN_ON(!handler);
 653
 654         handler(irq, event, vgpu);
 655
 656         ops->check_pending_irq(vgpu);
 657 }
 658
 659 static void init_events(
 660         struct intel_gvt_irq *irq)
 661 {
 662         int i;
 663
 664         for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) {
 665                 irq->events[i].info = NULL;
 666                 irq->events[i].v_handler = handle_default_event_virt;
 667         }
 668 }
 669
 670 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
 671 {
 672         struct intel_gvt_vblank_timer *vblank_timer;
 673         struct intel_gvt_irq *irq;
 674         struct intel_gvt *gvt;
 675
 676         vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer);
 677         irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
 678         gvt = container_of(irq, struct intel_gvt, irq);
 679
 680         intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK);
 681         hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
 682         return HRTIMER_RESTART;
 683 }
 684
 685 /**
 686  * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem
 687  * @gvt: a GVT device
 688  *
 689  * This function is called at driver unloading stage, to clean up GVT-g IRQ
 690  * emulation subsystem.
 691  *
 692  */
 693 void intel_gvt_clean_irq(struct intel_gvt *gvt)
 694 {
 695         struct intel_gvt_irq *irq = &gvt->irq;
 696
 697         hrtimer_cancel(&irq->vblank_timer.timer);
 698 }
 699
 700 #define VBLNAK_TIMER_PERIOD 16000000
 701
 702 /**
 703  * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
 704  * @gvt: a GVT device
 705  *
 706  * This function is called at driver loading stage, to initialize the GVT-g IRQ
 707  * emulation subsystem.
 708  *
 709  * Returns:
 710  * Zero on success, negative error code if failed.
 711  */
 712 int intel_gvt_init_irq(struct intel_gvt *gvt)
 713 {
 714         struct intel_gvt_irq *irq = &gvt->irq;
 715         struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
 716
 717         gvt_dbg_core("init irq framework\n");
 718
 719         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
 720                 irq->ops = &gen8_irq_ops;
 721                 irq->irq_map = gen8_irq_map;
 722         } else {
 723                 WARN_ON(1);
 724                 return -ENODEV;
 725         }
 726
 727         /* common event initialization */
 728         init_events(irq);
 729
 730         /* gen specific initialization */
 731         irq->ops->init_irq(irq);
 732
 733         init_irq_map(irq);
 734
 735         hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
 736         vblank_timer->timer.function = vblank_timer_fn;
 737         vblank_timer->period = VBLNAK_TIMER_PERIOD;
 738
 739         return 0;
 740 }