drivers/gpu/drm/i915/gvt/gtt.c

   1 /*
   2  * GTT virtualization
   3  *
   4  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Zhi Wang <zhi.a.wang@intel.com>
  27  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  28  *    Xiao Zheng <xiao.zheng@intel.com>
  29  *
  30  * Contributors:
  31  *    Min He <min.he@intel.com>
  32  *    Bing Niu <bing.niu@intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37 #include "gvt.h"
  38 #include "i915_pvinfo.h"
  39 #include "trace.h"
  40
  41 #if defined(VERBOSE_DEBUG)
  42 #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
  43 #else
  44 #define gvt_vdbg_mm(fmt, args...)
  45 #endif
  46
  47 static bool enable_out_of_sync = false;
  48 static int preallocated_oos_pages = 8192;
  49
  50 /*
  51  * validate a gm address and related range size,
  52  * translate it to host gm address
  53  */
  54 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
  55 {
  56         if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
  57                         && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
  58                 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
  59                                 addr, size);
  60                 return false;
  61         }
  62         return true;
  63 }
  64
  65 /* translate a guest gmadr to host gmadr */
  66 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
  67 {
  68         if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
  69                  "invalid guest gmadr %llx\n", g_addr))
  70                 return -EACCES;
  71
  72         if (vgpu_gmadr_is_aperture(vgpu, g_addr))
  73                 *h_addr = vgpu_aperture_gmadr_base(vgpu)
  74                           + (g_addr - vgpu_aperture_offset(vgpu));
  75         else
  76                 *h_addr = vgpu_hidden_gmadr_base(vgpu)
  77                           + (g_addr - vgpu_hidden_offset(vgpu));
  78         return 0;
  79 }
  80
  81 /* translate a host gmadr to guest gmadr */
  82 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
  83 {
  84         if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
  85                  "invalid host gmadr %llx\n", h_addr))
  86                 return -EACCES;
  87
  88         if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
  89                 *g_addr = vgpu_aperture_gmadr_base(vgpu)
  90                         + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
  91         else
  92                 *g_addr = vgpu_hidden_gmadr_base(vgpu)
  93                         + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
  94         return 0;
  95 }
  96
  97 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
  98                              unsigned long *h_index)
  99 {
 100         u64 h_addr;
 101         int ret;
 102
 103         ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
 104                                        &h_addr);
 105         if (ret)
 106                 return ret;
 107
 108         *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
 109         return 0;
 110 }
 111
 112 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
 113                              unsigned long *g_index)
 114 {
 115         u64 g_addr;
 116         int ret;
 117
 118         ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
 119                                        &g_addr);
 120         if (ret)
 121                 return ret;
 122
 123         *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
 124         return 0;
 125 }
 126
 127 #define gtt_type_is_entry(type) \
 128         (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
 129          && type != GTT_TYPE_PPGTT_PTE_ENTRY \
 130          && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
 131
 132 #define gtt_type_is_pt(type) \
 133         (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
 134
 135 #define gtt_type_is_pte_pt(type) \
 136         (type == GTT_TYPE_PPGTT_PTE_PT)
 137
 138 #define gtt_type_is_root_pointer(type) \
 139         (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
 140
 141 #define gtt_init_entry(e, t, p, v) do { \
 142         (e)->type = t; \
 143         (e)->pdev = p; \
 144         memcpy(&(e)->val64, &v, sizeof(v)); \
 145 } while (0)
 146
 147 /*
 148  * Mappings between GTT_TYPE* enumerations.
 149  * Following information can be found according to the given type:
 150  * - type of next level page table
 151  * - type of entry inside this level page table
 152  * - type of entry with PSE set
 153  *
 154  * If the given type doesn't have such a kind of information,
 155  * e.g. give a l4 root entry type, then request to get its PSE type,
 156  * give a PTE page table type, then request to get its next level page
 157  * table type, as we know l4 root entry doesn't have a PSE bit,
 158  * and a PTE page table doesn't have a next level page table type,
 159  * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 160  * page table.
 161  */
 162
 163 struct gtt_type_table_entry {
 164         int entry_type;
 165         int pt_type;
 166         int next_pt_type;
 167         int pse_entry_type;
 168 };
 169
 170 #define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
 171         [type] = { \
 172                 .entry_type = e_type, \
 173                 .pt_type = cpt_type, \
 174                 .next_pt_type = npt_type, \
 175                 .pse_entry_type = pse_type, \
 176         }
 177
 178 static struct gtt_type_table_entry gtt_type_table[] = {
 179         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
 180                         GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
 181                         GTT_TYPE_INVALID,
 182                         GTT_TYPE_PPGTT_PML4_PT,
 183                         GTT_TYPE_INVALID),
 184         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
 185                         GTT_TYPE_PPGTT_PML4_ENTRY,
 186                         GTT_TYPE_PPGTT_PML4_PT,
 187                         GTT_TYPE_PPGTT_PDP_PT,
 188                         GTT_TYPE_INVALID),
 189         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
 190                         GTT_TYPE_PPGTT_PML4_ENTRY,
 191                         GTT_TYPE_PPGTT_PML4_PT,
 192                         GTT_TYPE_PPGTT_PDP_PT,
 193                         GTT_TYPE_INVALID),
 194         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
 195                         GTT_TYPE_PPGTT_PDP_ENTRY,
 196                         GTT_TYPE_PPGTT_PDP_PT,
 197                         GTT_TYPE_PPGTT_PDE_PT,
 198                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 199         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
 200                         GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
 201                         GTT_TYPE_INVALID,
 202                         GTT_TYPE_PPGTT_PDE_PT,
 203                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 204         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
 205                         GTT_TYPE_PPGTT_PDP_ENTRY,
 206                         GTT_TYPE_PPGTT_PDP_PT,
 207                         GTT_TYPE_PPGTT_PDE_PT,
 208                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 209         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
 210                         GTT_TYPE_PPGTT_PDE_ENTRY,
 211                         GTT_TYPE_PPGTT_PDE_PT,
 212                         GTT_TYPE_PPGTT_PTE_PT,
 213                         GTT_TYPE_PPGTT_PTE_2M_ENTRY),
 214         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
 215                         GTT_TYPE_PPGTT_PDE_ENTRY,
 216                         GTT_TYPE_PPGTT_PDE_PT,
 217                         GTT_TYPE_PPGTT_PTE_PT,
 218                         GTT_TYPE_PPGTT_PTE_2M_ENTRY),
 219         /* We take IPS bit as 'PSE' for PTE level. */
 220         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
 221                         GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 222                         GTT_TYPE_PPGTT_PTE_PT,
 223                         GTT_TYPE_INVALID,
 224                         GTT_TYPE_PPGTT_PTE_64K_ENTRY),
 225         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 226                         GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 227                         GTT_TYPE_PPGTT_PTE_PT,
 228                         GTT_TYPE_INVALID,
 229                         GTT_TYPE_PPGTT_PTE_64K_ENTRY),
 230         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
 231                         GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 232                         GTT_TYPE_PPGTT_PTE_PT,
 233                         GTT_TYPE_INVALID,
 234                         GTT_TYPE_PPGTT_PTE_64K_ENTRY),
 235         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
 236                         GTT_TYPE_PPGTT_PDE_ENTRY,
 237                         GTT_TYPE_PPGTT_PDE_PT,
 238                         GTT_TYPE_INVALID,
 239                         GTT_TYPE_PPGTT_PTE_2M_ENTRY),
 240         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
 241                         GTT_TYPE_PPGTT_PDP_ENTRY,
 242                         GTT_TYPE_PPGTT_PDP_PT,
 243                         GTT_TYPE_INVALID,
 244                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 245         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
 246                         GTT_TYPE_GGTT_PTE,
 247                         GTT_TYPE_INVALID,
 248                         GTT_TYPE_INVALID,
 249                         GTT_TYPE_INVALID),
 250 };
 251
 252 static inline int get_next_pt_type(int type)
 253 {
 254         return gtt_type_table[type].next_pt_type;
 255 }
 256
 257 static inline int get_pt_type(int type)
 258 {
 259         return gtt_type_table[type].pt_type;
 260 }
 261
 262 static inline int get_entry_type(int type)
 263 {
 264         return gtt_type_table[type].entry_type;
 265 }
 266
 267 static inline int get_pse_type(int type)
 268 {
 269         return gtt_type_table[type].pse_entry_type;
 270 }
 271
 272 static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
 273 {
 274         void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
 275
 276         return readq(addr);
 277 }
 278
 279 static void ggtt_invalidate(struct drm_i915_private *dev_priv)
 280 {
 281         mmio_hw_access_pre(dev_priv);
 282         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 283         mmio_hw_access_post(dev_priv);
 284 }
 285
 286 static void write_pte64(struct drm_i915_private *dev_priv,
 287                 unsigned long index, u64 pte)
 288 {
 289         void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
 290
 291         writeq(pte, addr);
 292 }
 293
 294 static inline int gtt_get_entry64(void *pt,
 295                 struct intel_gvt_gtt_entry *e,
 296                 unsigned long index, bool hypervisor_access, unsigned long gpa,
 297                 struct intel_vgpu *vgpu)
 298 {
 299         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
 300         int ret;
 301
 302         if (WARN_ON(info->gtt_entry_size != 8))
 303                 return -EINVAL;
 304
 305         if (hypervisor_access) {
 306                 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
 307                                 (index << info->gtt_entry_size_shift),
 308                                 &e->val64, 8);
 309                 if (WARN_ON(ret))
 310                         return ret;
 311         } else if (!pt) {
 312                 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
 313         } else {
 314                 e->val64 = *((u64 *)pt + index);
 315         }
 316         return 0;
 317 }
 318
 319 static inline int gtt_set_entry64(void *pt,
 320                 struct intel_gvt_gtt_entry *e,
 321                 unsigned long index, bool hypervisor_access, unsigned long gpa,
 322                 struct intel_vgpu *vgpu)
 323 {
 324         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
 325         int ret;
 326
 327         if (WARN_ON(info->gtt_entry_size != 8))
 328                 return -EINVAL;
 329
 330         if (hypervisor_access) {
 331                 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
 332                                 (index << info->gtt_entry_size_shift),
 333                                 &e->val64, 8);
 334                 if (WARN_ON(ret))
 335                         return ret;
 336         } else if (!pt) {
 337                 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
 338         } else {
 339                 *((u64 *)pt + index) = e->val64;
 340         }
 341         return 0;
 342 }
 343
 344 #define GTT_HAW 46
 345
 346 #define ADDR_1G_MASK    GENMASK_ULL(GTT_HAW - 1, 30)
 347 #define ADDR_2M_MASK    GENMASK_ULL(GTT_HAW - 1, 21)
 348 #define ADDR_64K_MASK   GENMASK_ULL(GTT_HAW - 1, 16)
 349 #define ADDR_4K_MASK    GENMASK_ULL(GTT_HAW - 1, 12)
 350
 351 #define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
 352 #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
 353
 354 #define GTT_64K_PTE_STRIDE 16
 355
 356 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
 357 {
 358         unsigned long pfn;
 359
 360         if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
 361                 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
 362         else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
 363                 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
 364         else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
 365                 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
 366         else
 367                 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
 368         return pfn;
 369 }
 370
 371 static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
 372 {
 373         if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
 374                 e->val64 &= ~ADDR_1G_MASK;
 375                 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
 376         } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
 377                 e->val64 &= ~ADDR_2M_MASK;
 378                 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
 379         } else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
 380                 e->val64 &= ~ADDR_64K_MASK;
 381                 pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
 382         } else {
 383                 e->val64 &= ~ADDR_4K_MASK;
 384                 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
 385         }
 386
 387         e->val64 |= (pfn << PAGE_SHIFT);
 388 }
 389
 390 static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
 391 {
 392         return !!(e->val64 & _PAGE_PSE);
 393 }
 394
 395 static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
 396 {
 397         if (gen8_gtt_test_pse(e)) {
 398                 switch (e->type) {
 399                 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
 400                         e->val64 &= ~_PAGE_PSE;
 401                         e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
 402                         break;
 403                 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
 404                         e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
 405                         e->val64 &= ~_PAGE_PSE;
 406                         break;
 407                 default:
 408                         WARN_ON(1);
 409                 }
 410         }
 411 }
 412
 413 static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
 414 {
 415         if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
 416                 return false;
 417
 418         return !!(e->val64 & GEN8_PDE_IPS_64K);
 419 }
 420
 421 static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
 422 {
 423         if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
 424                 return;
 425
 426         e->val64 &= ~GEN8_PDE_IPS_64K;
 427 }
 428
 429 static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
 430 {
 431         /*
 432          * i915 writes PDP root pointer registers without present bit,
 433          * it also works, so we need to treat root pointer entry
 434          * specifically.
 435          */
 436         if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
 437                         || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
 438                 return (e->val64 != 0);
 439         else
 440                 return (e->val64 & _PAGE_PRESENT);
 441 }
 442
 443 static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
 444 {
 445         e->val64 &= ~_PAGE_PRESENT;
 446 }
 447
 448 static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
 449 {
 450         e->val64 |= _PAGE_PRESENT;
 451 }
 452
 453 static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
 454 {
 455         return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
 456 }
 457
 458 static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
 459 {
 460         e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
 461 }
 462
 463 static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
 464 {
 465         e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
 466 }
 467
 468 /*
 469  * Per-platform GMA routines.
 470  */
 471 static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
 472 {
 473         unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
 474
 475         trace_gma_index(__func__, gma, x);
 476         return x;
 477 }
 478
 479 #define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
 480 static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
 481 { \
 482         unsigned long x = (exp); \
 483         trace_gma_index(__func__, gma, x); \
 484         return x; \
 485 }
 486
 487 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
 488 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
 489 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
 490 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
 491 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
 492
 493 static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
 494         .get_entry = gtt_get_entry64,
 495         .set_entry = gtt_set_entry64,
 496         .clear_present = gtt_entry_clear_present,
 497         .set_present = gtt_entry_set_present,
 498         .test_present = gen8_gtt_test_present,
 499         .test_pse = gen8_gtt_test_pse,
 500         .clear_pse = gen8_gtt_clear_pse,
 501         .clear_ips = gen8_gtt_clear_ips,
 502         .test_ips = gen8_gtt_test_ips,
 503         .clear_64k_splited = gen8_gtt_clear_64k_splited,
 504         .set_64k_splited = gen8_gtt_set_64k_splited,
 505         .test_64k_splited = gen8_gtt_test_64k_splited,
 506         .get_pfn = gen8_gtt_get_pfn,
 507         .set_pfn = gen8_gtt_set_pfn,
 508 };
 509
 510 static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
 511         .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
 512         .gma_to_pte_index = gen8_gma_to_pte_index,
 513         .gma_to_pde_index = gen8_gma_to_pde_index,
 514         .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
 515         .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
 516         .gma_to_pml4_index = gen8_gma_to_pml4_index,
 517 };
 518
 519 /* Update entry type per pse and ips bit. */
 520 static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
 521         struct intel_gvt_gtt_entry *entry, bool ips)
 522 {
 523         switch (entry->type) {
 524         case GTT_TYPE_PPGTT_PDE_ENTRY:
 525         case GTT_TYPE_PPGTT_PDP_ENTRY:
 526                 if (pte_ops->test_pse(entry))
 527                         entry->type = get_pse_type(entry->type);
 528                 break;
 529         case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
 530                 if (ips)
 531                         entry->type = get_pse_type(entry->type);
 532                 break;
 533         default:
 534                 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
 535         }
 536
 537         GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
 538 }
 539
 540 /*
 541  * MM helpers.
 542  */
 543 static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
 544                 struct intel_gvt_gtt_entry *entry, unsigned long index,
 545                 bool guest)
 546 {
 547         struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 548
 549         GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
 550
 551         entry->type = mm->ppgtt_mm.root_entry_type;
 552         pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
 553                            mm->ppgtt_mm.shadow_pdps,
 554                            entry, index, false, 0, mm->vgpu);
 555         update_entry_type_for_real(pte_ops, entry, false);
 556 }
 557
 558 static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
 559                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 560 {
 561         _ppgtt_get_root_entry(mm, entry, index, true);
 562 }
 563
 564 static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
 565                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 566 {
 567         _ppgtt_get_root_entry(mm, entry, index, false);
 568 }
 569
 570 static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
 571                 struct intel_gvt_gtt_entry *entry, unsigned long index,
 572                 bool guest)
 573 {
 574         struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 575
 576         pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
 577                            mm->ppgtt_mm.shadow_pdps,
 578                            entry, index, false, 0, mm->vgpu);
 579 }
 580
 581 static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
 582                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 583 {
 584         _ppgtt_set_root_entry(mm, entry, index, true);
 585 }
 586
 587 static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
 588                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 589 {
 590         _ppgtt_set_root_entry(mm, entry, index, false);
 591 }
 592
 593 static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
 594                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 595 {
 596         struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 597
 598         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 599
 600         entry->type = GTT_TYPE_GGTT_PTE;
 601         pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
 602                            false, 0, mm->vgpu);
 603 }
 604
 605 static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
 606                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 607 {
 608         struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 609
 610         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 611
 612         pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
 613                            false, 0, mm->vgpu);
 614 }
 615
 616 static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
 617                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 618 {
 619         struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 620
 621         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 622
 623         pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
 624 }
 625
 626 static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
 627                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 628 {
 629         struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 630
 631         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 632
 633         pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
 634 }
 635
 636 /*
 637  * PPGTT shadow page table helpers.
 638  */
 639 static inline int ppgtt_spt_get_entry(
 640                 struct intel_vgpu_ppgtt_spt *spt,
 641                 void *page_table, int type,
 642                 struct intel_gvt_gtt_entry *e, unsigned long index,
 643                 bool guest)
 644 {
 645         struct intel_gvt *gvt = spt->vgpu->gvt;
 646         struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
 647         int ret;
 648
 649         e->type = get_entry_type(type);
 650
 651         if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
 652                 return -EINVAL;
 653
 654         ret = ops->get_entry(page_table, e, index, guest,
 655                         spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
 656                         spt->vgpu);
 657         if (ret)
 658                 return ret;
 659
 660         update_entry_type_for_real(ops, e, guest ?
 661                                    spt->guest_page.pde_ips : false);
 662
 663         gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
 664                     type, e->type, index, e->val64);
 665         return 0;
 666 }
 667
 668 static inline int ppgtt_spt_set_entry(
 669                 struct intel_vgpu_ppgtt_spt *spt,
 670                 void *page_table, int type,
 671                 struct intel_gvt_gtt_entry *e, unsigned long index,
 672                 bool guest)
 673 {
 674         struct intel_gvt *gvt = spt->vgpu->gvt;
 675         struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
 676
 677         if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
 678                 return -EINVAL;
 679
 680         gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
 681                     type, e->type, index, e->val64);
 682
 683         return ops->set_entry(page_table, e, index, guest,
 684                         spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
 685                         spt->vgpu);
 686 }
 687
 688 #define ppgtt_get_guest_entry(spt, e, index) \
 689         ppgtt_spt_get_entry(spt, NULL, \
 690                 spt->guest_page.type, e, index, true)
 691
 692 #define ppgtt_set_guest_entry(spt, e, index) \
 693         ppgtt_spt_set_entry(spt, NULL, \
 694                 spt->guest_page.type, e, index, true)
 695
 696 #define ppgtt_get_shadow_entry(spt, e, index) \
 697         ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
 698                 spt->shadow_page.type, e, index, false)
 699
 700 #define ppgtt_set_shadow_entry(spt, e, index) \
 701         ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
 702                 spt->shadow_page.type, e, index, false)
 703
 704 static void *alloc_spt(gfp_t gfp_mask)
 705 {
 706         struct intel_vgpu_ppgtt_spt *spt;
 707
 708         spt = kzalloc(sizeof(*spt), gfp_mask);
 709         if (!spt)
 710                 return NULL;
 711
 712         spt->shadow_page.page = alloc_page(gfp_mask);
 713         if (!spt->shadow_page.page) {
 714                 kfree(spt);
 715                 return NULL;
 716         }
 717         return spt;
 718 }
 719
 720 static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
 721 {
 722         __free_page(spt->shadow_page.page);
 723         kfree(spt);
 724 }
 725
 726 static int detach_oos_page(struct intel_vgpu *vgpu,
 727                 struct intel_vgpu_oos_page *oos_page);
 728
 729 static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
 730 {
 731         struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
 732
 733         trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
 734
 735         dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
 736                        PCI_DMA_BIDIRECTIONAL);
 737
 738         radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
 739
 740         if (spt->guest_page.gfn) {
 741                 if (spt->guest_page.oos_page)
 742                         detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
 743
 744                 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
 745         }
 746
 747         list_del_init(&spt->post_shadow_list);
 748         free_spt(spt);
 749 }
 750
 751 static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
 752 {
 753         struct intel_vgpu_ppgtt_spt *spt, *spn;
 754         struct radix_tree_iter iter;
 755         LIST_HEAD(all_spt);
 756         void __rcu **slot;
 757
 758         rcu_read_lock();
 759         radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
 760                 spt = radix_tree_deref_slot(slot);
 761                 list_move(&spt->post_shadow_list, &all_spt);
 762         }
 763         rcu_read_unlock();
 764
 765         list_for_each_entry_safe(spt, spn, &all_spt, post_shadow_list)
 766                 ppgtt_free_spt(spt);
 767 }
 768
 769 static int ppgtt_handle_guest_write_page_table_bytes(
 770                 struct intel_vgpu_ppgtt_spt *spt,
 771                 u64 pa, void *p_data, int bytes);
 772
 773 static int ppgtt_write_protection_handler(
 774                 struct intel_vgpu_page_track *page_track,
 775                 u64 gpa, void *data, int bytes)
 776 {
 777         struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
 778
 779         int ret;
 780
 781         if (bytes != 4 && bytes != 8)
 782                 return -EINVAL;
 783
 784         ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
 785         if (ret)
 786                 return ret;
 787         return ret;
 788 }
 789
 790 /* Find a spt by guest gfn. */
 791 static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
 792                 struct intel_vgpu *vgpu, unsigned long gfn)
 793 {
 794         struct intel_vgpu_page_track *track;
 795
 796         track = intel_vgpu_find_page_track(vgpu, gfn);
 797         if (track && track->handler == ppgtt_write_protection_handler)
 798                 return track->priv_data;
 799
 800         return NULL;
 801 }
 802
 803 /* Find the spt by shadow page mfn. */
 804 static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
 805                 struct intel_vgpu *vgpu, unsigned long mfn)
 806 {
 807         return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
 808 }
 809
 810 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
 811
 812 /* Allocate shadow page table without guest page. */
 813 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
 814                 struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type)
 815 {
 816         struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
 817         struct intel_vgpu_ppgtt_spt *spt = NULL;
 818         dma_addr_t daddr;
 819         int ret;
 820
 821 retry:
 822         spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
 823         if (!spt) {
 824                 if (reclaim_one_ppgtt_mm(vgpu->gvt))
 825                         goto retry;
 826
 827                 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
 828                 return ERR_PTR(-ENOMEM);
 829         }
 830
 831         spt->vgpu = vgpu;
 832         atomic_set(&spt->refcount, 1);
 833         INIT_LIST_HEAD(&spt->post_shadow_list);
 834
 835         /*
 836          * Init shadow_page.
 837          */
 838         spt->shadow_page.type = type;
 839         daddr = dma_map_page(kdev, spt->shadow_page.page,
 840                              0, 4096, PCI_DMA_BIDIRECTIONAL);
 841         if (dma_mapping_error(kdev, daddr)) {
 842                 gvt_vgpu_err("fail to map dma addr\n");
 843                 ret = -EINVAL;
 844                 goto err_free_spt;
 845         }
 846         spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
 847         spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
 848
 849         ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
 850         if (ret)
 851                 goto err_unmap_dma;
 852
 853         return spt;
 854
 855 err_unmap_dma:
 856         dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 857 err_free_spt:
 858         free_spt(spt);
 859         return ERR_PTR(ret);
 860 }
 861
 862 /* Allocate shadow page table associated with specific gfn. */
 863 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
 864                 struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type,
 865                 unsigned long gfn, bool guest_pde_ips)
 866 {
 867         struct intel_vgpu_ppgtt_spt *spt;
 868         int ret;
 869
 870         spt = ppgtt_alloc_spt(vgpu, type);
 871         if (IS_ERR(spt))
 872                 return spt;
 873
 874         /*
 875          * Init guest_page.
 876          */
 877         ret = intel_vgpu_register_page_track(vgpu, gfn,
 878                         ppgtt_write_protection_handler, spt);
 879         if (ret) {
 880                 ppgtt_free_spt(spt);
 881                 return ERR_PTR(ret);
 882         }
 883
 884         spt->guest_page.type = type;
 885         spt->guest_page.gfn = gfn;
 886         spt->guest_page.pde_ips = guest_pde_ips;
 887
 888         trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
 889
 890         return spt;
 891 }
 892
 893 #define pt_entry_size_shift(spt) \
 894         ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
 895
 896 #define pt_entries(spt) \
 897         (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
 898
 899 #define for_each_present_guest_entry(spt, e, i) \
 900         for (i = 0; i < pt_entries(spt); \
 901              i += spt->guest_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
 902                 if (!ppgtt_get_guest_entry(spt, e, i) && \
 903                     spt->vgpu->gvt->gtt.pte_ops->test_present(e))
 904
 905 #define for_each_present_shadow_entry(spt, e, i) \
 906         for (i = 0; i < pt_entries(spt); \
 907              i += spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
 908                 if (!ppgtt_get_shadow_entry(spt, e, i) && \
 909                     spt->vgpu->gvt->gtt.pte_ops->test_present(e))
 910
 911 #define for_each_shadow_entry(spt, e, i) \
 912         for (i = 0; i < pt_entries(spt); \
 913              i += (spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1)) \
 914                 if (!ppgtt_get_shadow_entry(spt, e, i))
 915
 916 static inline void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
 917 {
 918         int v = atomic_read(&spt->refcount);
 919
 920         trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
 921         atomic_inc(&spt->refcount);
 922 }
 923
 924 static inline int ppgtt_put_spt(struct intel_vgpu_ppgtt_spt *spt)
 925 {
 926         int v = atomic_read(&spt->refcount);
 927
 928         trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
 929         return atomic_dec_return(&spt->refcount);
 930 }
 931
 932 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
 933
 934 static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
 935                 struct intel_gvt_gtt_entry *e)
 936 {
 937         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 938         struct intel_vgpu_ppgtt_spt *s;
 939         intel_gvt_gtt_type_t cur_pt_type;
 940
 941         GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
 942
 943         if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
 944                 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 945                 cur_pt_type = get_next_pt_type(e->type) + 1;
 946                 if (ops->get_pfn(e) ==
 947                         vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
 948                         return 0;
 949         }
 950         s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
 951         if (!s) {
 952                 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
 953                                 ops->get_pfn(e));
 954                 return -ENXIO;
 955         }
 956         return ppgtt_invalidate_spt(s);
 957 }
 958
 959 static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
 960                 struct intel_gvt_gtt_entry *entry)
 961 {
 962         struct intel_vgpu *vgpu = spt->vgpu;
 963         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 964         unsigned long pfn;
 965         int type;
 966
 967         pfn = ops->get_pfn(entry);
 968         type = spt->shadow_page.type;
 969
 970         /* Uninitialized spte or unshadowed spte. */
 971         if (!pfn || pfn == vgpu->gtt.scratch_pt[type].page_mfn)
 972                 return;
 973
 974         intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
 975 }
 976
 977 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
 978 {
 979         struct intel_vgpu *vgpu = spt->vgpu;
 980         struct intel_gvt_gtt_entry e;
 981         unsigned long index;
 982         int ret;
 983
 984         trace_spt_change(spt->vgpu->id, "die", spt,
 985                         spt->guest_page.gfn, spt->shadow_page.type);
 986
 987         if (ppgtt_put_spt(spt) > 0)
 988                 return 0;
 989
 990         for_each_present_shadow_entry(spt, &e, index) {
 991                 switch (e.type) {
 992                 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
 993                         gvt_vdbg_mm("invalidate 4K entry\n");
 994                         ppgtt_invalidate_pte(spt, &e);
 995                         break;
 996                 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
 997                         /* We don't setup 64K shadow entry so far. */
 998                         WARN(1, "suspicious 64K gtt entry\n");
 999                         continue;
1000                 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1001                         gvt_vdbg_mm("invalidate 2M entry\n");
1002                         continue;
1003                 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1004                         WARN(1, "GVT doesn't support 1GB page\n");
1005                         continue;
1006                 case GTT_TYPE_PPGTT_PML4_ENTRY:
1007                 case GTT_TYPE_PPGTT_PDP_ENTRY:
1008                 case GTT_TYPE_PPGTT_PDE_ENTRY:
1009                         gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
1010                         ret = ppgtt_invalidate_spt_by_shadow_entry(
1011                                         spt->vgpu, &e);
1012                         if (ret)
1013                                 goto fail;
1014                         break;
1015                 default:
1016                         GEM_BUG_ON(1);
1017                 }
1018         }
1019
1020         trace_spt_change(spt->vgpu->id, "release", spt,
1021                          spt->guest_page.gfn, spt->shadow_page.type);
1022         ppgtt_free_spt(spt);
1023         return 0;
1024 fail:
1025         gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
1026                         spt, e.val64, e.type);
1027         return ret;
1028 }
1029
1030 static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
1031 {
1032         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1033
1034         if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
1035                 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
1036                         GAMW_ECO_ENABLE_64K_IPS_FIELD;
1037
1038                 return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
1039         } else if (INTEL_GEN(dev_priv) >= 11) {
1040                 /* 64K paging only controlled by IPS bit in PTE now. */
1041                 return true;
1042         } else
1043                 return false;
1044 }
1045
1046 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
1047
1048 static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
1049                 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
1050 {
1051         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1052         struct intel_vgpu_ppgtt_spt *spt = NULL;
1053         bool ips = false;
1054         int ret;
1055
1056         GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
1057
1058         if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1059                 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1060
1061         spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
1062         if (spt) {
1063                 ppgtt_get_spt(spt);
1064
1065                 if (ips != spt->guest_page.pde_ips) {
1066                         spt->guest_page.pde_ips = ips;
1067
1068                         gvt_dbg_mm("reshadow PDE since ips changed\n");
1069                         clear_page(spt->shadow_page.vaddr);
1070                         ret = ppgtt_populate_spt(spt);
1071                         if (ret) {
1072                                 ppgtt_put_spt(spt);
1073                                 goto err;
1074                         }
1075                 }
1076         } else {
1077                 int type = get_next_pt_type(we->type);
1078
1079                 spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
1080                 if (IS_ERR(spt)) {
1081                         ret = PTR_ERR(spt);
1082                         goto err;
1083                 }
1084
1085                 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
1086                 if (ret)
1087                         goto err_free_spt;
1088
1089                 ret = ppgtt_populate_spt(spt);
1090                 if (ret)
1091                         goto err_free_spt;
1092
1093                 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
1094                                  spt->shadow_page.type);
1095         }
1096         return spt;
1097
1098 err_free_spt:
1099         ppgtt_free_spt(spt);
1100 err:
1101         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1102                      spt, we->val64, we->type);
1103         return ERR_PTR(ret);
1104 }
1105
1106 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
1107                 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
1108 {
1109         struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1110
1111         se->type = ge->type;
1112         se->val64 = ge->val64;
1113
1114         /* Because we always split 64KB pages, so clear IPS in shadow PDE. */
1115         if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1116                 ops->clear_ips(se);
1117
1118         ops->set_pfn(se, s->shadow_page.mfn);
1119 }
1120
1121 /**
1122  * Check if can do 2M page
1123  * @vgpu: target vgpu
1124  * @entry: target pfn's gtt entry
1125  *
1126  * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
1127  * negtive if found err.
1128  */
1129 static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
1130         struct intel_gvt_gtt_entry *entry)
1131 {
1132         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1133         unsigned long pfn;
1134
1135         if (!HAS_PAGE_SIZES(vgpu->gvt->dev_priv, I915_GTT_PAGE_SIZE_2M))
1136                 return 0;
1137
1138         pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, ops->get_pfn(entry));
1139         if (pfn == INTEL_GVT_INVALID_ADDR)
1140                 return -EINVAL;
1141
1142         return PageTransHuge(pfn_to_page(pfn));
1143 }
1144
1145 static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
1146         struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1147         struct intel_gvt_gtt_entry *se)
1148 {
1149         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1150         struct intel_vgpu_ppgtt_spt *sub_spt;
1151         struct intel_gvt_gtt_entry sub_se;
1152         unsigned long start_gfn;
1153         dma_addr_t dma_addr;
1154         unsigned long sub_index;
1155         int ret;
1156
1157         gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1158
1159         start_gfn = ops->get_pfn(se);
1160
1161         sub_spt = ppgtt_alloc_spt(vgpu, GTT_TYPE_PPGTT_PTE_PT);
1162         if (IS_ERR(sub_spt))
1163                 return PTR_ERR(sub_spt);
1164
1165         for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
1166                 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
1167                                 start_gfn + sub_index, PAGE_SIZE, &dma_addr);
1168                 if (ret) {
1169                         ppgtt_invalidate_spt(spt);
1170                         return ret;
1171                 }
1172                 sub_se.val64 = se->val64;
1173
1174                 /* Copy the PAT field from PDE. */
1175                 sub_se.val64 &= ~_PAGE_PAT;
1176                 sub_se.val64 |= (se->val64 & _PAGE_PAT_LARGE) >> 5;
1177
1178                 ops->set_pfn(&sub_se, dma_addr >> PAGE_SHIFT);
1179                 ppgtt_set_shadow_entry(sub_spt, &sub_se, sub_index);
1180         }
1181
1182         /* Clear dirty field. */
1183         se->val64 &= ~_PAGE_DIRTY;
1184
1185         ops->clear_pse(se);
1186         ops->clear_ips(se);
1187         ops->set_pfn(se, sub_spt->shadow_page.mfn);
1188         ppgtt_set_shadow_entry(spt, se, index);
1189         return 0;
1190 }
1191
1192 static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
1193         struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1194         struct intel_gvt_gtt_entry *se)
1195 {
1196         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1197         struct intel_gvt_gtt_entry entry = *se;
1198         unsigned long start_gfn;
1199         dma_addr_t dma_addr;
1200         int i, ret;
1201
1202         gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1203
1204         GEM_BUG_ON(index % GTT_64K_PTE_STRIDE);
1205
1206         start_gfn = ops->get_pfn(se);
1207
1208         entry.type = GTT_TYPE_PPGTT_PTE_4K_ENTRY;
1209         ops->set_64k_splited(&entry);
1210
1211         for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1212                 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
1213                                         start_gfn + i, PAGE_SIZE, &dma_addr);
1214                 if (ret)
1215                         return ret;
1216
1217                 ops->set_pfn(&entry, dma_addr >> PAGE_SHIFT);
1218                 ppgtt_set_shadow_entry(spt, &entry, index + i);
1219         }
1220         return 0;
1221 }
1222
1223 static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
1224         struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1225         struct intel_gvt_gtt_entry *ge)
1226 {
1227         struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1228         struct intel_gvt_gtt_entry se = *ge;
1229         unsigned long gfn, page_size = PAGE_SIZE;
1230         dma_addr_t dma_addr;
1231         int ret;
1232
1233         if (!pte_ops->test_present(ge))
1234                 return 0;
1235
1236         gfn = pte_ops->get_pfn(ge);
1237
1238         switch (ge->type) {
1239         case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1240                 gvt_vdbg_mm("shadow 4K gtt entry\n");
1241                 break;
1242         case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1243                 gvt_vdbg_mm("shadow 64K gtt entry\n");
1244                 /*
1245                  * The layout of 64K page is special, the page size is
1246                  * controlled by uper PDE. To be simple, we always split
1247                  * 64K page to smaller 4K pages in shadow PT.
1248                  */
1249                 return split_64KB_gtt_entry(vgpu, spt, index, &se);
1250         case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1251                 gvt_vdbg_mm("shadow 2M gtt entry\n");
1252                 ret = is_2MB_gtt_possible(vgpu, ge);
1253                 if (ret == 0)
1254                         return split_2MB_gtt_entry(vgpu, spt, index, &se);
1255                 else if (ret < 0)
1256                         return ret;
1257                 page_size = I915_GTT_PAGE_SIZE_2M;
1258                 break;
1259         case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1260                 gvt_vgpu_err("GVT doesn't support 1GB entry\n");
1261                 return -EINVAL;
1262         default:
1263                 GEM_BUG_ON(1);
1264         };
1265
1266         /* direct shadow */
1267         ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, page_size,
1268                                                       &dma_addr);
1269         if (ret)
1270                 return -ENXIO;
1271
1272         pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
1273         ppgtt_set_shadow_entry(spt, &se, index);
1274         return 0;
1275 }
1276
1277 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
1278 {
1279         struct intel_vgpu *vgpu = spt->vgpu;
1280         struct intel_gvt *gvt = vgpu->gvt;
1281         struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1282         struct intel_vgpu_ppgtt_spt *s;
1283         struct intel_gvt_gtt_entry se, ge;
1284         unsigned long gfn, i;
1285         int ret;
1286
1287         trace_spt_change(spt->vgpu->id, "born", spt,
1288                          spt->guest_page.gfn, spt->shadow_page.type);
1289
1290         for_each_present_guest_entry(spt, &ge, i) {
1291                 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1292                         s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1293                         if (IS_ERR(s)) {
1294                                 ret = PTR_ERR(s);
1295                                 goto fail;
1296                         }
1297                         ppgtt_get_shadow_entry(spt, &se, i);
1298                         ppgtt_generate_shadow_entry(&se, s, &ge);
1299                         ppgtt_set_shadow_entry(spt, &se, i);
1300                 } else {
1301                         gfn = ops->get_pfn(&ge);
1302                         if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1303                                 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1304                                 ppgtt_set_shadow_entry(spt, &se, i);
1305                                 continue;
1306                         }
1307
1308                         ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1309                         if (ret)
1310                                 goto fail;
1311                 }
1312         }
1313         return 0;
1314 fail:
1315         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1316                         spt, ge.val64, ge.type);
1317         return ret;
1318 }
1319
1320 static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1321                 struct intel_gvt_gtt_entry *se, unsigned long index)
1322 {
1323         struct intel_vgpu *vgpu = spt->vgpu;
1324         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1325         int ret;
1326
1327         trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1328                                spt->shadow_page.type, se->val64, index);
1329
1330         gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1331                     se->type, index, se->val64);
1332
1333         if (!ops->test_present(se))
1334                 return 0;
1335
1336         if (ops->get_pfn(se) ==
1337             vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1338                 return 0;
1339
1340         if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1341                 struct intel_vgpu_ppgtt_spt *s =
1342                         intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
1343                 if (!s) {
1344                         gvt_vgpu_err("fail to find guest page\n");
1345                         ret = -ENXIO;
1346                         goto fail;
1347                 }
1348                 ret = ppgtt_invalidate_spt(s);
1349                 if (ret)
1350                         goto fail;
1351         } else {
1352                 /* We don't setup 64K shadow entry so far. */
1353                 WARN(se->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY,
1354                      "suspicious 64K entry\n");
1355                 ppgtt_invalidate_pte(spt, se);
1356         }
1357
1358         return 0;
1359 fail:
1360         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1361                         spt, se->val64, se->type);
1362         return ret;
1363 }
1364
1365 static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
1366                 struct intel_gvt_gtt_entry *we, unsigned long index)
1367 {
1368         struct intel_vgpu *vgpu = spt->vgpu;
1369         struct intel_gvt_gtt_entry m;
1370         struct intel_vgpu_ppgtt_spt *s;
1371         int ret;
1372
1373         trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1374                                we->val64, index);
1375
1376         gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1377                     we->type, index, we->val64);
1378
1379         if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1380                 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1381                 if (IS_ERR(s)) {
1382                         ret = PTR_ERR(s);
1383                         goto fail;
1384                 }
1385                 ppgtt_get_shadow_entry(spt, &m, index);
1386                 ppgtt_generate_shadow_entry(&m, s, we);
1387                 ppgtt_set_shadow_entry(spt, &m, index);
1388         } else {
1389                 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1390                 if (ret)
1391                         goto fail;
1392         }
1393         return 0;
1394 fail:
1395         gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1396                 spt, we->val64, we->type);
1397         return ret;
1398 }
1399
1400 static int sync_oos_page(struct intel_vgpu *vgpu,
1401                 struct intel_vgpu_oos_page *oos_page)
1402 {
1403         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1404         struct intel_gvt *gvt = vgpu->gvt;
1405         struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1406         struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1407         struct intel_gvt_gtt_entry old, new;
1408         int index;
1409         int ret;
1410
1411         trace_oos_change(vgpu->id, "sync", oos_page->id,
1412                          spt, spt->guest_page.type);
1413
1414         old.type = new.type = get_entry_type(spt->guest_page.type);
1415         old.val64 = new.val64 = 0;
1416
1417         for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1418                                 info->gtt_entry_size_shift); index++) {
1419                 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1420                 ops->get_entry(NULL, &new, index, true,
1421                                spt->guest_page.gfn << PAGE_SHIFT, vgpu);
1422
1423                 if (old.val64 == new.val64
1424                         && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1425                         continue;
1426
1427                 trace_oos_sync(vgpu->id, oos_page->id,
1428                                 spt, spt->guest_page.type,
1429                                 new.val64, index);
1430
1431                 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
1432                 if (ret)
1433                         return ret;
1434
1435                 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
1436         }
1437
1438         spt->guest_page.write_cnt = 0;
1439         list_del_init(&spt->post_shadow_list);
1440         return 0;
1441 }
1442
1443 static int detach_oos_page(struct intel_vgpu *vgpu,
1444                 struct intel_vgpu_oos_page *oos_page)
1445 {
1446         struct intel_gvt *gvt = vgpu->gvt;
1447         struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1448
1449         trace_oos_change(vgpu->id, "detach", oos_page->id,
1450                          spt, spt->guest_page.type);
1451
1452         spt->guest_page.write_cnt = 0;
1453         spt->guest_page.oos_page = NULL;
1454         oos_page->spt = NULL;
1455
1456         list_del_init(&oos_page->vm_list);
1457         list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1458
1459         return 0;
1460 }
1461
1462 static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1463                 struct intel_vgpu_ppgtt_spt *spt)
1464 {
1465         struct intel_gvt *gvt = spt->vgpu->gvt;
1466         int ret;
1467
1468         ret = intel_gvt_hypervisor_read_gpa(spt->vgpu,
1469                         spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
1470                         oos_page->mem, I915_GTT_PAGE_SIZE);
1471         if (ret)
1472                 return ret;
1473
1474         oos_page->spt = spt;
1475         spt->guest_page.oos_page = oos_page;
1476
1477         list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1478
1479         trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1480                          spt, spt->guest_page.type);
1481         return 0;
1482 }
1483
1484 static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
1485 {
1486         struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1487         int ret;
1488
1489         ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
1490         if (ret)
1491                 return ret;
1492
1493         trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1494                          spt, spt->guest_page.type);
1495
1496         list_del_init(&oos_page->vm_list);
1497         return sync_oos_page(spt->vgpu, oos_page);
1498 }
1499
1500 static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
1501 {
1502         struct intel_gvt *gvt = spt->vgpu->gvt;
1503         struct intel_gvt_gtt *gtt = &gvt->gtt;
1504         struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1505         int ret;
1506
1507         WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1508
1509         if (list_empty(&gtt->oos_page_free_list_head)) {
1510                 oos_page = container_of(gtt->oos_page_use_list_head.next,
1511                         struct intel_vgpu_oos_page, list);
1512                 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1513                 if (ret)
1514                         return ret;
1515                 ret = detach_oos_page(spt->vgpu, oos_page);
1516                 if (ret)
1517                         return ret;
1518         } else
1519                 oos_page = container_of(gtt->oos_page_free_list_head.next,
1520                         struct intel_vgpu_oos_page, list);
1521         return attach_oos_page(oos_page, spt);
1522 }
1523
1524 static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
1525 {
1526         struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1527
1528         if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1529                 return -EINVAL;
1530
1531         trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1532                          spt, spt->guest_page.type);
1533
1534         list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
1535         return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
1536 }
1537
1538 /**
1539  * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1540  * @vgpu: a vGPU
1541  *
1542  * This function is called before submitting a guest workload to host,
1543  * to sync all the out-of-synced shadow for vGPU
1544  *
1545  * Returns:
1546  * Zero on success, negative error code if failed.
1547  */
1548 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1549 {
1550         struct list_head *pos, *n;
1551         struct intel_vgpu_oos_page *oos_page;
1552         int ret;
1553
1554         if (!enable_out_of_sync)
1555                 return 0;
1556
1557         list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1558                 oos_page = container_of(pos,
1559                                 struct intel_vgpu_oos_page, vm_list);
1560                 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1561                 if (ret)
1562                         return ret;
1563         }
1564         return 0;
1565 }
1566
1567 /*
1568  * The heart of PPGTT shadow page table.
1569  */
1570 static int ppgtt_handle_guest_write_page_table(
1571                 struct intel_vgpu_ppgtt_spt *spt,
1572                 struct intel_gvt_gtt_entry *we, unsigned long index)
1573 {
1574         struct intel_vgpu *vgpu = spt->vgpu;
1575         int type = spt->shadow_page.type;
1576         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1577         struct intel_gvt_gtt_entry old_se;
1578         int new_present;
1579         int i, ret;
1580
1581         new_present = ops->test_present(we);
1582
1583         /*
1584          * Adding the new entry first and then removing the old one, that can
1585          * guarantee the ppgtt table is validated during the window between
1586          * adding and removal.
1587          */
1588         ppgtt_get_shadow_entry(spt, &old_se, index);
1589
1590         if (new_present) {
1591                 ret = ppgtt_handle_guest_entry_add(spt, we, index);
1592                 if (ret)
1593                         goto fail;
1594         }
1595
1596         ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
1597         if (ret)
1598                 goto fail;
1599
1600         if (!new_present) {
1601                 /* For 64KB splited entries, we need clear them all. */
1602                 if (ops->test_64k_splited(&old_se) &&
1603                     !(index % GTT_64K_PTE_STRIDE)) {
1604                         gvt_vdbg_mm("remove splited 64K shadow entries\n");
1605                         for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1606                                 ops->clear_64k_splited(&old_se);
1607                                 ops->set_pfn(&old_se,
1608                                         vgpu->gtt.scratch_pt[type].page_mfn);
1609                                 ppgtt_set_shadow_entry(spt, &old_se, index + i);
1610                         }
1611                 } else if (old_se.type == GTT_TYPE_PPGTT_PTE_2M_ENTRY ||
1612                            old_se.type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
1613                         ops->clear_pse(&old_se);
1614                         ops->set_pfn(&old_se,
1615                                      vgpu->gtt.scratch_pt[type].page_mfn);
1616                         ppgtt_set_shadow_entry(spt, &old_se, index);
1617                 } else {
1618                         ops->set_pfn(&old_se,
1619                                      vgpu->gtt.scratch_pt[type].page_mfn);
1620                         ppgtt_set_shadow_entry(spt, &old_se, index);
1621                 }
1622         }
1623
1624         return 0;
1625 fail:
1626         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1627                         spt, we->val64, we->type);
1628         return ret;
1629 }
1630
1631
1632
1633 static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
1634 {
1635         return enable_out_of_sync
1636                 && gtt_type_is_pte_pt(spt->guest_page.type)
1637                 && spt->guest_page.write_cnt >= 2;
1638 }
1639
1640 static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1641                 unsigned long index)
1642 {
1643         set_bit(index, spt->post_shadow_bitmap);
1644         if (!list_empty(&spt->post_shadow_list))
1645                 return;
1646
1647         list_add_tail(&spt->post_shadow_list,
1648                         &spt->vgpu->gtt.post_shadow_list_head);
1649 }
1650
1651 /**
1652  * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1653  * @vgpu: a vGPU
1654  *
1655  * This function is called before submitting a guest workload to host,
1656  * to flush all the post shadows for a vGPU.
1657  *
1658  * Returns:
1659  * Zero on success, negative error code if failed.
1660  */
1661 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1662 {
1663         struct list_head *pos, *n;
1664         struct intel_vgpu_ppgtt_spt *spt;
1665         struct intel_gvt_gtt_entry ge;
1666         unsigned long index;
1667         int ret;
1668
1669         list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1670                 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1671                                 post_shadow_list);
1672
1673                 for_each_set_bit(index, spt->post_shadow_bitmap,
1674                                 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1675                         ppgtt_get_guest_entry(spt, &ge, index);
1676
1677                         ret = ppgtt_handle_guest_write_page_table(spt,
1678                                                         &ge, index);
1679                         if (ret)
1680                                 return ret;
1681                         clear_bit(index, spt->post_shadow_bitmap);
1682                 }
1683                 list_del_init(&spt->post_shadow_list);
1684         }
1685         return 0;
1686 }
1687
1688 static int ppgtt_handle_guest_write_page_table_bytes(
1689                 struct intel_vgpu_ppgtt_spt *spt,
1690                 u64 pa, void *p_data, int bytes)
1691 {
1692         struct intel_vgpu *vgpu = spt->vgpu;
1693         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1694         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1695         struct intel_gvt_gtt_entry we, se;
1696         unsigned long index;
1697         int ret;
1698
1699         index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1700
1701         ppgtt_get_guest_entry(spt, &we, index);
1702
1703         /*
1704          * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1705          * PTE#32, ... PTE#496 are used. Unused PTEs update should be
1706          * ignored.
1707          */
1708         if (we.type == GTT_TYPE_PPGTT_PTE_64K_ENTRY &&
1709             (index % GTT_64K_PTE_STRIDE)) {
1710                 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1711                             index);
1712                 return 0;
1713         }
1714
1715         if (bytes == info->gtt_entry_size) {
1716                 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
1717                 if (ret)
1718                         return ret;
1719         } else {
1720                 if (!test_bit(index, spt->post_shadow_bitmap)) {
1721                         int type = spt->shadow_page.type;
1722
1723                         ppgtt_get_shadow_entry(spt, &se, index);
1724                         ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
1725                         if (ret)
1726                                 return ret;
1727                         ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1728                         ppgtt_set_shadow_entry(spt, &se, index);
1729                 }
1730                 ppgtt_set_post_shadow(spt, index);
1731         }
1732
1733         if (!enable_out_of_sync)
1734                 return 0;
1735
1736         spt->guest_page.write_cnt++;
1737
1738         if (spt->guest_page.oos_page)
1739                 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
1740                                 false, 0, vgpu);
1741
1742         if (can_do_out_of_sync(spt)) {
1743                 if (!spt->guest_page.oos_page)
1744                         ppgtt_allocate_oos_page(spt);
1745
1746                 ret = ppgtt_set_guest_page_oos(spt);
1747                 if (ret < 0)
1748                         return ret;
1749         }
1750         return 0;
1751 }
1752
1753 static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
1754 {
1755         struct intel_vgpu *vgpu = mm->vgpu;
1756         struct intel_gvt *gvt = vgpu->gvt;
1757         struct intel_gvt_gtt *gtt = &gvt->gtt;
1758         struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1759         struct intel_gvt_gtt_entry se;
1760         int index;
1761
1762         if (!mm->ppgtt_mm.shadowed)
1763                 return;
1764
1765         for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1766                 ppgtt_get_shadow_root_entry(mm, &se, index);
1767
1768                 if (!ops->test_present(&se))
1769                         continue;
1770
1771                 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
1772                 se.val64 = 0;
1773                 ppgtt_set_shadow_root_entry(mm, &se, index);
1774
1775                 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1776                                        NULL, se.type, se.val64, index);
1777         }
1778
1779         mm->ppgtt_mm.shadowed = false;
1780 }
1781
1782
1783 static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
1784 {
1785         struct intel_vgpu *vgpu = mm->vgpu;
1786         struct intel_gvt *gvt = vgpu->gvt;
1787         struct intel_gvt_gtt *gtt = &gvt->gtt;
1788         struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1789         struct intel_vgpu_ppgtt_spt *spt;
1790         struct intel_gvt_gtt_entry ge, se;
1791         int index, ret;
1792
1793         if (mm->ppgtt_mm.shadowed)
1794                 return 0;
1795
1796         mm->ppgtt_mm.shadowed = true;
1797
1798         for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1799                 ppgtt_get_guest_root_entry(mm, &ge, index);
1800
1801                 if (!ops->test_present(&ge))
1802                         continue;
1803
1804                 trace_spt_guest_change(vgpu->id, __func__, NULL,
1805                                        ge.type, ge.val64, index);
1806
1807                 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1808                 if (IS_ERR(spt)) {
1809                         gvt_vgpu_err("fail to populate guest root pointer\n");
1810                         ret = PTR_ERR(spt);
1811                         goto fail;
1812                 }
1813                 ppgtt_generate_shadow_entry(&se, spt, &ge);
1814                 ppgtt_set_shadow_root_entry(mm, &se, index);
1815
1816                 trace_spt_guest_change(vgpu->id, "populate root pointer",
1817                                        NULL, se.type, se.val64, index);
1818         }
1819
1820         return 0;
1821 fail:
1822         invalidate_ppgtt_mm(mm);
1823         return ret;
1824 }
1825
1826 static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1827 {
1828         struct intel_vgpu_mm *mm;
1829
1830         mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1831         if (!mm)
1832                 return NULL;
1833
1834         mm->vgpu = vgpu;
1835         kref_init(&mm->ref);
1836         atomic_set(&mm->pincount, 0);
1837
1838         return mm;
1839 }
1840
1841 static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1842 {
1843         kfree(mm);
1844 }
1845
1846 /**
1847  * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
1848  * @vgpu: a vGPU
1849  * @root_entry_type: ppgtt root entry type
1850  * @pdps: guest pdps.
1851  *
1852  * This function is used to create a ppgtt mm object for a vGPU.
1853  *
1854  * Returns:
1855  * Zero on success, negative error code in pointer if failed.
1856  */
1857 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1858                 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
1859 {
1860         struct intel_gvt *gvt = vgpu->gvt;
1861         struct intel_vgpu_mm *mm;
1862         int ret;
1863
1864         mm = vgpu_alloc_mm(vgpu);
1865         if (!mm)
1866                 return ERR_PTR(-ENOMEM);
1867
1868         mm->type = INTEL_GVT_MM_PPGTT;
1869
1870         GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1871                    root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1872         mm->ppgtt_mm.root_entry_type = root_entry_type;
1873
1874         INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1875         INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
1876
1877         if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1878                 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1879         else
1880                 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1881                        sizeof(mm->ppgtt_mm.guest_pdps));
1882
1883         ret = shadow_ppgtt_mm(mm);
1884         if (ret) {
1885                 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1886                 vgpu_free_mm(mm);
1887                 return ERR_PTR(ret);
1888         }
1889
1890         list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1891
1892         mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1893         list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1894         mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1895
1896         return mm;
1897 }
1898
1899 static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1900 {
1901         struct intel_vgpu_mm *mm;
1902         unsigned long nr_entries;
1903
1904         mm = vgpu_alloc_mm(vgpu);
1905         if (!mm)
1906                 return ERR_PTR(-ENOMEM);
1907
1908         mm->type = INTEL_GVT_MM_GGTT;
1909
1910         nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1911         mm->ggtt_mm.virtual_ggtt =
1912                 vzalloc(array_size(nr_entries,
1913                                    vgpu->gvt->device_info.gtt_entry_size));
1914         if (!mm->ggtt_mm.virtual_ggtt) {
1915                 vgpu_free_mm(mm);
1916                 return ERR_PTR(-ENOMEM);
1917         }
1918
1919         return mm;
1920 }
1921
1922 /**
1923  * _intel_vgpu_mm_release - destroy a mm object
1924  * @mm_ref: a kref object
1925  *
1926  * This function is used to destroy a mm object for vGPU
1927  *
1928  */
1929 void _intel_vgpu_mm_release(struct kref *mm_ref)
1930 {
1931         struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1932
1933         if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1934                 gvt_err("vgpu mm pin count bug detected\n");
1935
1936         if (mm->type == INTEL_GVT_MM_PPGTT) {
1937                 list_del(&mm->ppgtt_mm.list);
1938                 list_del(&mm->ppgtt_mm.lru_list);
1939                 invalidate_ppgtt_mm(mm);
1940         } else {
1941                 vfree(mm->ggtt_mm.virtual_ggtt);
1942         }
1943
1944         vgpu_free_mm(mm);
1945 }
1946
1947 /**
1948  * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1949  * @mm: a vGPU mm object
1950  *
1951  * This function is called when user doesn't want to use a vGPU mm object
1952  */
1953 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1954 {
1955         atomic_dec_if_positive(&mm->pincount);
1956 }
1957
1958 /**
1959  * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1960  * @mm: target vgpu mm
1961  *
1962  * This function is called when user wants to use a vGPU mm object. If this
1963  * mm object hasn't been shadowed yet, the shadow will be populated at this
1964  * time.
1965  *
1966  * Returns:
1967  * Zero on success, negative error code if failed.
1968  */
1969 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1970 {
1971         int ret;
1972
1973         atomic_inc(&mm->pincount);
1974
1975         if (mm->type == INTEL_GVT_MM_PPGTT) {
1976                 ret = shadow_ppgtt_mm(mm);
1977                 if (ret)
1978                         return ret;
1979
1980                 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1981                 list_move_tail(&mm->ppgtt_mm.lru_list,
1982                                &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1983                 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1984         }
1985
1986         return 0;
1987 }
1988
1989 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
1990 {
1991         struct intel_vgpu_mm *mm;
1992         struct list_head *pos, *n;
1993
1994         mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1995
1996         list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
1997                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
1998
1999                 if (atomic_read(&mm->pincount))
2000                         continue;
2001
2002                 list_del_init(&mm->ppgtt_mm.lru_list);
2003                 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2004                 invalidate_ppgtt_mm(mm);
2005                 return 1;
2006         }
2007         mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2008         return 0;
2009 }
2010
2011 /*
2012  * GMA translation APIs.
2013  */
2014 static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
2015                 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
2016 {
2017         struct intel_vgpu *vgpu = mm->vgpu;
2018         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2019         struct intel_vgpu_ppgtt_spt *s;
2020
2021         s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2022         if (!s)
2023                 return -ENXIO;
2024
2025         if (!guest)
2026                 ppgtt_get_shadow_entry(s, e, index);
2027         else
2028                 ppgtt_get_guest_entry(s, e, index);
2029         return 0;
2030 }
2031
2032 /**
2033  * intel_vgpu_gma_to_gpa - translate a gma to GPA
2034  * @mm: mm object. could be a PPGTT or GGTT mm object
2035  * @gma: graphics memory address in this mm object
2036  *
2037  * This function is used to translate a graphics memory address in specific
2038  * graphics memory space to guest physical address.
2039  *
2040  * Returns:
2041  * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
2042  */
2043 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
2044 {
2045         struct intel_vgpu *vgpu = mm->vgpu;
2046         struct intel_gvt *gvt = vgpu->gvt;
2047         struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2048         struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2049         unsigned long gpa = INTEL_GVT_INVALID_ADDR;
2050         unsigned long gma_index[4];
2051         struct intel_gvt_gtt_entry e;
2052         int i, levels = 0;
2053         int ret;
2054
2055         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
2056                    mm->type != INTEL_GVT_MM_PPGTT);
2057
2058         if (mm->type == INTEL_GVT_MM_GGTT) {
2059                 if (!vgpu_gmadr_is_valid(vgpu, gma))
2060                         goto err;
2061
2062                 ggtt_get_guest_entry(mm, &e,
2063                         gma_ops->gma_to_ggtt_pte_index(gma));
2064
2065                 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
2066                         + (gma & ~I915_GTT_PAGE_MASK);
2067
2068                 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
2069         } else {
2070                 switch (mm->ppgtt_mm.root_entry_type) {
2071                 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2072                         ppgtt_get_shadow_root_entry(mm, &e, 0);
2073
2074                         gma_index[0] = gma_ops->gma_to_pml4_index(gma);
2075                         gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
2076                         gma_index[2] = gma_ops->gma_to_pde_index(gma);
2077                         gma_index[3] = gma_ops->gma_to_pte_index(gma);
2078                         levels = 4;
2079                         break;
2080                 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2081                         ppgtt_get_shadow_root_entry(mm, &e,
2082                                         gma_ops->gma_to_l3_pdp_index(gma));
2083
2084                         gma_index[0] = gma_ops->gma_to_pde_index(gma);
2085                         gma_index[1] = gma_ops->gma_to_pte_index(gma);
2086                         levels = 2;
2087                         break;
2088                 default:
2089                         GEM_BUG_ON(1);
2090                 }
2091
2092                 /* walk the shadow page table and get gpa from guest entry */
2093                 for (i = 0; i < levels; i++) {
2094                         ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
2095                                 (i == levels - 1));
2096                         if (ret)
2097                                 goto err;
2098
2099                         if (!pte_ops->test_present(&e)) {
2100                                 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
2101                                 goto err;
2102                         }
2103                 }
2104
2105                 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
2106                                         (gma & ~I915_GTT_PAGE_MASK);
2107                 trace_gma_translate(vgpu->id, "ppgtt", 0,
2108                                     mm->ppgtt_mm.root_entry_type, gma, gpa);
2109         }
2110
2111         return gpa;
2112 err:
2113         gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2114         return INTEL_GVT_INVALID_ADDR;
2115 }
2116
2117 static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2118         unsigned int off, void *p_data, unsigned int bytes)
2119 {
2120         struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2121         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2122         unsigned long index = off >> info->gtt_entry_size_shift;
2123         struct intel_gvt_gtt_entry e;
2124
2125         if (bytes != 4 && bytes != 8)
2126                 return -EINVAL;
2127
2128         ggtt_get_guest_entry(ggtt_mm, &e, index);
2129         memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
2130                         bytes);
2131         return 0;
2132 }
2133
2134 /**
2135  * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
2136  * @vgpu: a vGPU
2137  * @off: register offset
2138  * @p_data: data will be returned to guest
2139  * @bytes: data length
2140  *
2141  * This function is used to emulate the GTT MMIO register read
2142  *
2143  * Returns:
2144  * Zero on success, error code if failed.
2145  */
2146 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
2147         void *p_data, unsigned int bytes)
2148 {
2149         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2150         int ret;
2151
2152         if (bytes != 4 && bytes != 8)
2153                 return -EINVAL;
2154
2155         off -= info->gtt_start_offset;
2156         ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
2157         return ret;
2158 }
2159
2160 static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
2161                 struct intel_gvt_gtt_entry *entry)
2162 {
2163         struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2164         unsigned long pfn;
2165
2166         pfn = pte_ops->get_pfn(entry);
2167         if (pfn != vgpu->gvt->gtt.scratch_mfn)
2168                 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu,
2169                                                 pfn << PAGE_SHIFT);
2170 }
2171
2172 static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2173         void *p_data, unsigned int bytes)
2174 {
2175         struct intel_gvt *gvt = vgpu->gvt;
2176         const struct intel_gvt_device_info *info = &gvt->device_info;
2177         struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2178         struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2179         unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
2180         unsigned long gma, gfn;
2181         struct intel_gvt_gtt_entry e, m;
2182         dma_addr_t dma_addr;
2183         int ret;
2184         struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2185         bool partial_update = false;
2186
2187         if (bytes != 4 && bytes != 8)
2188                 return -EINVAL;
2189
2190         gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
2191
2192         /* the VM may configure the whole GM space when ballooning is used */
2193         if (!vgpu_gmadr_is_valid(vgpu, gma))
2194                 return 0;
2195
2196         e.type = GTT_TYPE_GGTT_PTE;
2197         memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2198                         bytes);
2199
2200         /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2201          * write, save the first 4 bytes in a list and update virtual
2202          * PTE. Only update shadow PTE when the second 4 bytes comes.
2203          */
2204         if (bytes < info->gtt_entry_size) {
2205                 bool found = false;
2206
2207                 list_for_each_entry_safe(pos, n,
2208                                 &ggtt_mm->ggtt_mm.partial_pte_list, list) {
2209                         if (g_gtt_index == pos->offset >>
2210                                         info->gtt_entry_size_shift) {
2211                                 if (off != pos->offset) {
2212                                         /* the second partial part*/
2213                                         int last_off = pos->offset &
2214                                                 (info->gtt_entry_size - 1);
2215
2216                                         memcpy((void *)&e.val64 + last_off,
2217                                                 (void *)&pos->data + last_off,
2218                                                 bytes);
2219
2220                                         list_del(&pos->list);
2221                                         kfree(pos);
2222                                         found = true;
2223                                         break;
2224                                 }
2225
2226                                 /* update of the first partial part */
2227                                 pos->data = e.val64;
2228                                 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2229                                 return 0;
2230                         }
2231                 }
2232
2233                 if (!found) {
2234                         /* the first partial part */
2235                         partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2236                         if (!partial_pte)
2237                                 return -ENOMEM;
2238                         partial_pte->offset = off;
2239                         partial_pte->data = e.val64;
2240                         list_add_tail(&partial_pte->list,
2241                                 &ggtt_mm->ggtt_mm.partial_pte_list);
2242                         partial_update = true;
2243                 }
2244         }
2245
2246         if (!partial_update && (ops->test_present(&e))) {
2247                 gfn = ops->get_pfn(&e);
2248                 m = e;
2249
2250                 /* one PTE update may be issued in multiple writes and the
2251                  * first write may not construct a valid gfn
2252                  */
2253                 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
2254                         ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2255                         goto out;
2256                 }
2257
2258                 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn,
2259                                                         PAGE_SIZE, &dma_addr);
2260                 if (ret) {
2261                         gvt_vgpu_err("fail to populate guest ggtt entry\n");
2262                         /* guest driver may read/write the entry when partial
2263                          * update the entry in this situation p2m will fail
2264                          * settting the shadow entry to point to a scratch page
2265                          */
2266                         ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2267                 } else
2268                         ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
2269         } else {
2270                 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2271                 ops->clear_present(&m);
2272         }
2273
2274 out:
2275         ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2276
2277         ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2278         ggtt_invalidate_pte(vgpu, &e);
2279
2280         ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2281         ggtt_invalidate(gvt->dev_priv);
2282         return 0;
2283 }
2284
2285 /*
2286  * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
2287  * @vgpu: a vGPU
2288  * @off: register offset
2289  * @p_data: data from guest write
2290  * @bytes: data length
2291  *
2292  * This function is used to emulate the GTT MMIO register write
2293  *
2294  * Returns:
2295  * Zero on success, error code if failed.
2296  */
2297 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2298                 unsigned int off, void *p_data, unsigned int bytes)
2299 {
2300         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2301         int ret;
2302
2303         if (bytes != 4 && bytes != 8)
2304                 return -EINVAL;
2305
2306         off -= info->gtt_start_offset;
2307         ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2308         return ret;
2309 }
2310
2311 static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2312                 intel_gvt_gtt_type_t type)
2313 {
2314         struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2315         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2316         int page_entry_num = I915_GTT_PAGE_SIZE >>
2317                                 vgpu->gvt->device_info.gtt_entry_size_shift;
2318         void *scratch_pt;
2319         int i;
2320         struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2321         dma_addr_t daddr;
2322
2323         if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2324                 return -EINVAL;
2325
2326         scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
2327         if (!scratch_pt) {
2328                 gvt_vgpu_err("fail to allocate scratch page\n");
2329                 return -ENOMEM;
2330         }
2331
2332         daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
2333                         4096, PCI_DMA_BIDIRECTIONAL);
2334         if (dma_mapping_error(dev, daddr)) {
2335                 gvt_vgpu_err("fail to dmamap scratch_pt\n");
2336                 __free_page(virt_to_page(scratch_pt));
2337                 return -ENOMEM;
2338         }
2339         gtt->scratch_pt[type].page_mfn =
2340                 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2341         gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
2342         gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
2343                         vgpu->id, type, gtt->scratch_pt[type].page_mfn);
2344
2345         /* Build the tree by full filled the scratch pt with the entries which
2346          * point to the next level scratch pt or scratch page. The
2347          * scratch_pt[type] indicate the scratch pt/scratch page used by the
2348          * 'type' pt.
2349          * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
2350          * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
2351          * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
2352          */
2353         if (type > GTT_TYPE_PPGTT_PTE_PT) {
2354                 struct intel_gvt_gtt_entry se;
2355
2356                 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
2357                 se.type = get_entry_type(type - 1);
2358                 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2359
2360                 /* The entry parameters like present/writeable/cache type
2361                  * set to the same as i915's scratch page tree.
2362                  */
2363                 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
2364                 if (type == GTT_TYPE_PPGTT_PDE_PT)
2365                         se.val64 |= PPAT_CACHED;
2366
2367                 for (i = 0; i < page_entry_num; i++)
2368                         ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
2369         }
2370
2371         return 0;
2372 }
2373
2374 static int release_scratch_page_tree(struct intel_vgpu *vgpu)
2375 {
2376         int i;
2377         struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2378         dma_addr_t daddr;
2379
2380         for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2381                 if (vgpu->gtt.scratch_pt[i].page != NULL) {
2382                         daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
2383                                         I915_GTT_PAGE_SHIFT);
2384                         dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2385                         __free_page(vgpu->gtt.scratch_pt[i].page);
2386                         vgpu->gtt.scratch_pt[i].page = NULL;
2387                         vgpu->gtt.scratch_pt[i].page_mfn = 0;
2388                 }
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2395 {
2396         int i, ret;
2397
2398         for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2399                 ret = alloc_scratch_pages(vgpu, i);
2400                 if (ret)
2401                         goto err;
2402         }
2403
2404         return 0;
2405
2406 err:
2407         release_scratch_page_tree(vgpu);
2408         return ret;
2409 }
2410
2411 /**
2412  * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2413  * @vgpu: a vGPU
2414  *
2415  * This function is used to initialize per-vGPU graphics memory virtualization
2416  * components.
2417  *
2418  * Returns:
2419  * Zero on success, error code if failed.
2420  */
2421 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2422 {
2423         struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2424
2425         INIT_RADIX_TREE(&gtt->spt_tree, GFP_KERNEL);
2426
2427         INIT_LIST_HEAD(&gtt->ppgtt_mm_list_head);
2428         INIT_LIST_HEAD(&gtt->oos_page_list_head);
2429         INIT_LIST_HEAD(&gtt->post_shadow_list_head);
2430
2431         gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2432         if (IS_ERR(gtt->ggtt_mm)) {
2433                 gvt_vgpu_err("fail to create mm for ggtt.\n");
2434                 return PTR_ERR(gtt->ggtt_mm);
2435         }
2436
2437         intel_vgpu_reset_ggtt(vgpu, false);
2438
2439         INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2440
2441         return create_scratch_page_tree(vgpu);
2442 }
2443
2444 static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2445 {
2446         struct list_head *pos, *n;
2447         struct intel_vgpu_mm *mm;
2448
2449         list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2450                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2451                 intel_vgpu_destroy_mm(mm);
2452         }
2453
2454         if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
2455                 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
2456
2457         if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
2458                 gvt_err("Why we still has spt not freed?\n");
2459                 ppgtt_free_all_spt(vgpu);
2460         }
2461 }
2462
2463 static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2464 {
2465         struct intel_gvt_partial_pte *pos, *next;
2466
2467         list_for_each_entry_safe(pos, next,
2468                                  &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
2469                                  list) {
2470                 gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2471                         pos->offset, pos->data);
2472                 kfree(pos);
2473         }
2474         intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2475         vgpu->gtt.ggtt_mm = NULL;
2476 }
2477
2478 /**
2479  * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2480  * @vgpu: a vGPU
2481  *
2482  * This function is used to clean up per-vGPU graphics memory virtualization
2483  * components.
2484  *
2485  * Returns:
2486  * Zero on success, error code if failed.
2487  */
2488 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2489 {
2490         intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2491         intel_vgpu_destroy_ggtt_mm(vgpu);
2492         release_scratch_page_tree(vgpu);
2493 }
2494
2495 static void clean_spt_oos(struct intel_gvt *gvt)
2496 {
2497         struct intel_gvt_gtt *gtt = &gvt->gtt;
2498         struct list_head *pos, *n;
2499         struct intel_vgpu_oos_page *oos_page;
2500
2501         WARN(!list_empty(&gtt->oos_page_use_list_head),
2502                 "someone is still using oos page\n");
2503
2504         list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2505                 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2506                 list_del(&oos_page->list);
2507                 free_page((unsigned long)oos_page->mem);
2508                 kfree(oos_page);
2509         }
2510 }
2511
2512 static int setup_spt_oos(struct intel_gvt *gvt)
2513 {
2514         struct intel_gvt_gtt *gtt = &gvt->gtt;
2515         struct intel_vgpu_oos_page *oos_page;
2516         int i;
2517         int ret;
2518
2519         INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2520         INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2521
2522         for (i = 0; i < preallocated_oos_pages; i++) {
2523                 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2524                 if (!oos_page) {
2525                         ret = -ENOMEM;
2526                         goto fail;
2527                 }
2528                 oos_page->mem = (void *)__get_free_pages(GFP_KERNEL, 0);
2529                 if (!oos_page->mem) {
2530                         ret = -ENOMEM;
2531                         kfree(oos_page);
2532                         goto fail;
2533                 }
2534
2535                 INIT_LIST_HEAD(&oos_page->list);
2536                 INIT_LIST_HEAD(&oos_page->vm_list);
2537                 oos_page->id = i;
2538                 list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2539         }
2540
2541         gvt_dbg_mm("%d oos pages preallocated\n", i);
2542
2543         return 0;
2544 fail:
2545         clean_spt_oos(gvt);
2546         return ret;
2547 }
2548
2549 /**
2550  * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2551  * @vgpu: a vGPU
2552  * @pdps: pdp root array
2553  *
2554  * This function is used to find a PPGTT mm object from mm object pool
2555  *
2556  * Returns:
2557  * pointer to mm object on success, NULL if failed.
2558  */
2559 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
2560                 u64 pdps[])
2561 {
2562         struct intel_vgpu_mm *mm;
2563         struct list_head *pos;
2564
2565         list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2566                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2567
2568                 switch (mm->ppgtt_mm.root_entry_type) {
2569                 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2570                         if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2571                                 return mm;
2572                         break;
2573                 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2574                         if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2575                                     sizeof(mm->ppgtt_mm.guest_pdps)))
2576                                 return mm;
2577                         break;
2578                 default:
2579                         GEM_BUG_ON(1);
2580                 }
2581         }
2582         return NULL;
2583 }
2584
2585 /**
2586  * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2587  * @vgpu: a vGPU
2588  * @root_entry_type: ppgtt root entry type
2589  * @pdps: guest pdps
2590  *
2591  * This function is used to find or create a PPGTT mm object from a guest.
2592  *
2593  * Returns:
2594  * Zero on success, negative error code if failed.
2595  */
2596 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
2597                 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2598 {
2599         struct intel_vgpu_mm *mm;
2600
2601         mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2602         if (mm) {
2603                 intel_vgpu_mm_get(mm);
2604         } else {
2605                 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
2606                 if (IS_ERR(mm))
2607                         gvt_vgpu_err("fail to create mm\n");
2608         }
2609         return mm;
2610 }
2611
2612 /**
2613  * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2614  * @vgpu: a vGPU
2615  * @pdps: guest pdps
2616  *
2617  * This function is used to find a PPGTT mm object from a guest and destroy it.
2618  *
2619  * Returns:
2620  * Zero on success, negative error code if failed.
2621  */
2622 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2623 {
2624         struct intel_vgpu_mm *mm;
2625
2626         mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2627         if (!mm) {
2628                 gvt_vgpu_err("fail to find ppgtt instance.\n");
2629                 return -EINVAL;
2630         }
2631         intel_vgpu_mm_put(mm);
2632         return 0;
2633 }
2634
2635 /**
2636  * intel_gvt_init_gtt - initialize mm components of a GVT device
2637  * @gvt: GVT device
2638  *
2639  * This function is called at the initialization stage, to initialize
2640  * the mm components of a GVT device.
2641  *
2642  * Returns:
2643  * zero on success, negative error code if failed.
2644  */
2645 int intel_gvt_init_gtt(struct intel_gvt *gvt)
2646 {
2647         int ret;
2648         void *page;
2649         struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2650         dma_addr_t daddr;
2651
2652         gvt_dbg_core("init gtt\n");
2653
2654         gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2655         gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2656
2657         page = (void *)get_zeroed_page(GFP_KERNEL);
2658         if (!page) {
2659                 gvt_err("fail to allocate scratch ggtt page\n");
2660                 return -ENOMEM;
2661         }
2662
2663         daddr = dma_map_page(dev, virt_to_page(page), 0,
2664                         4096, PCI_DMA_BIDIRECTIONAL);
2665         if (dma_mapping_error(dev, daddr)) {
2666                 gvt_err("fail to dmamap scratch ggtt page\n");
2667                 __free_page(virt_to_page(page));
2668                 return -ENOMEM;
2669         }
2670
2671         gvt->gtt.scratch_page = virt_to_page(page);
2672         gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2673
2674         if (enable_out_of_sync) {
2675                 ret = setup_spt_oos(gvt);
2676                 if (ret) {
2677                         gvt_err("fail to initialize SPT oos\n");
2678                         dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2679                         __free_page(gvt->gtt.scratch_page);
2680                         return ret;
2681                 }
2682         }
2683         INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2684         mutex_init(&gvt->gtt.ppgtt_mm_lock);
2685         return 0;
2686 }
2687
2688 /**
2689  * intel_gvt_clean_gtt - clean up mm components of a GVT device
2690  * @gvt: GVT device
2691  *
2692  * This function is called at the driver unloading stage, to clean up the
2693  * the mm components of a GVT device.
2694  *
2695  */
2696 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2697 {
2698         struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2699         dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2700                                         I915_GTT_PAGE_SHIFT);
2701
2702         dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2703
2704         __free_page(gvt->gtt.scratch_page);
2705
2706         if (enable_out_of_sync)
2707                 clean_spt_oos(gvt);
2708 }
2709
2710 /**
2711  * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2712  * @vgpu: a vGPU
2713  *
2714  * This function is called when invalidate all PPGTT instances of a vGPU.
2715  *
2716  */
2717 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2718 {
2719         struct list_head *pos, *n;
2720         struct intel_vgpu_mm *mm;
2721
2722         list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2723                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2724                 if (mm->type == INTEL_GVT_MM_PPGTT) {
2725                         mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2726                         list_del_init(&mm->ppgtt_mm.lru_list);
2727                         mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2728                         if (mm->ppgtt_mm.shadowed)
2729                                 invalidate_ppgtt_mm(mm);
2730                 }
2731         }
2732 }
2733
2734 /**
2735  * intel_vgpu_reset_ggtt - reset the GGTT entry
2736  * @vgpu: a vGPU
2737  * @invalidate_old: invalidate old entries
2738  *
2739  * This function is called at the vGPU create stage
2740  * to reset all the GGTT entries.
2741  *
2742  */
2743 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
2744 {
2745         struct intel_gvt *gvt = vgpu->gvt;
2746         struct drm_i915_private *dev_priv = gvt->dev_priv;
2747         struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2748         struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
2749         struct intel_gvt_gtt_entry old_entry;
2750         u32 index;
2751         u32 num_entries;
2752
2753         pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2754         pte_ops->set_present(&entry);
2755
2756         index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2757         num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2758         while (num_entries--) {
2759                 if (invalidate_old) {
2760                         ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2761                         ggtt_invalidate_pte(vgpu, &old_entry);
2762                 }
2763                 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2764         }
2765
2766         index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2767         num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2768         while (num_entries--) {
2769                 if (invalidate_old) {
2770                         ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2771                         ggtt_invalidate_pte(vgpu, &old_entry);
2772                 }
2773                 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2774         }
2775
2776         ggtt_invalidate(dev_priv);
2777 }
2778
2779 /**
2780  * intel_vgpu_reset_gtt - reset the all GTT related status
2781  * @vgpu: a vGPU
2782  *
2783  * This function is called from vfio core to reset reset all
2784  * GTT related status, including GGTT, PPGTT, scratch page.
2785  *
2786  */
2787 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
2788 {
2789         /* Shadow pages are only created when there is no page
2790          * table tracking data, so remove page tracking data after
2791          * removing the shadow pages.
2792          */
2793         intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2794         intel_vgpu_reset_ggtt(vgpu, true);
2795 }