4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Zhi Wang <zhi.a.wang@intel.com>
27 * Zhenyu Wang <zhenyuw@linux.intel.com>
28 * Xiao Zheng <xiao.zheng@intel.com>
31 * Min He <min.he@intel.com>
32 * Bing Niu <bing.niu@intel.com>
38 #include "i915_pvinfo.h"
41 #if defined(VERBOSE_DEBUG)
42 #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
44 #define gvt_vdbg_mm(fmt, args...)
47 static bool enable_out_of_sync = false;
48 static int preallocated_oos_pages = 8192;
51 * validate a gm address and related range size,
52 * translate it to host gm address
54 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
56 if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
57 && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
58 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
65 /* translate a guest gmadr to host gmadr */
66 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
68 if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
69 "invalid guest gmadr %llx\n", g_addr))
72 if (vgpu_gmadr_is_aperture(vgpu, g_addr))
73 *h_addr = vgpu_aperture_gmadr_base(vgpu)
74 + (g_addr - vgpu_aperture_offset(vgpu));
76 *h_addr = vgpu_hidden_gmadr_base(vgpu)
77 + (g_addr - vgpu_hidden_offset(vgpu));
81 /* translate a host gmadr to guest gmadr */
82 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
84 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
85 "invalid host gmadr %llx\n", h_addr))
88 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
89 *g_addr = vgpu_aperture_gmadr_base(vgpu)
90 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
92 *g_addr = vgpu_hidden_gmadr_base(vgpu)
93 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
97 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
98 unsigned long *h_index)
103 ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
108 *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
112 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
113 unsigned long *g_index)
118 ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
123 *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
127 #define gtt_type_is_entry(type) \
128 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
129 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
130 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
132 #define gtt_type_is_pt(type) \
133 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
135 #define gtt_type_is_pte_pt(type) \
136 (type == GTT_TYPE_PPGTT_PTE_PT)
138 #define gtt_type_is_root_pointer(type) \
139 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
141 #define gtt_init_entry(e, t, p, v) do { \
144 memcpy(&(e)->val64, &v, sizeof(v)); \
148 * Mappings between GTT_TYPE* enumerations.
149 * Following information can be found according to the given type:
150 * - type of next level page table
151 * - type of entry inside this level page table
152 * - type of entry with PSE set
154 * If the given type doesn't have such a kind of information,
155 * e.g. give a l4 root entry type, then request to get its PSE type,
156 * give a PTE page table type, then request to get its next level page
157 * table type, as we know l4 root entry doesn't have a PSE bit,
158 * and a PTE page table doesn't have a next level page table type,
159 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
163 struct gtt_type_table_entry {
170 #define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
172 .entry_type = e_type, \
173 .pt_type = cpt_type, \
174 .next_pt_type = npt_type, \
175 .pse_entry_type = pse_type, \
178 static struct gtt_type_table_entry gtt_type_table[] = {
179 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
180 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
182 GTT_TYPE_PPGTT_PML4_PT,
184 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
185 GTT_TYPE_PPGTT_PML4_ENTRY,
186 GTT_TYPE_PPGTT_PML4_PT,
187 GTT_TYPE_PPGTT_PDP_PT,
189 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
190 GTT_TYPE_PPGTT_PML4_ENTRY,
191 GTT_TYPE_PPGTT_PML4_PT,
192 GTT_TYPE_PPGTT_PDP_PT,
194 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
195 GTT_TYPE_PPGTT_PDP_ENTRY,
196 GTT_TYPE_PPGTT_PDP_PT,
197 GTT_TYPE_PPGTT_PDE_PT,
198 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
199 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
200 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
202 GTT_TYPE_PPGTT_PDE_PT,
203 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
204 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
205 GTT_TYPE_PPGTT_PDP_ENTRY,
206 GTT_TYPE_PPGTT_PDP_PT,
207 GTT_TYPE_PPGTT_PDE_PT,
208 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
209 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
210 GTT_TYPE_PPGTT_PDE_ENTRY,
211 GTT_TYPE_PPGTT_PDE_PT,
212 GTT_TYPE_PPGTT_PTE_PT,
213 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
214 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
215 GTT_TYPE_PPGTT_PDE_ENTRY,
216 GTT_TYPE_PPGTT_PDE_PT,
217 GTT_TYPE_PPGTT_PTE_PT,
218 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
219 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
220 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
221 GTT_TYPE_PPGTT_PTE_PT,
224 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
225 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
226 GTT_TYPE_PPGTT_PTE_PT,
229 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
230 GTT_TYPE_PPGTT_PDE_ENTRY,
231 GTT_TYPE_PPGTT_PDE_PT,
233 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
234 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
235 GTT_TYPE_PPGTT_PDP_ENTRY,
236 GTT_TYPE_PPGTT_PDP_PT,
238 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
239 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
246 static inline int get_next_pt_type(int type)
248 return gtt_type_table[type].next_pt_type;
251 static inline int get_pt_type(int type)
253 return gtt_type_table[type].pt_type;
256 static inline int get_entry_type(int type)
258 return gtt_type_table[type].entry_type;
261 static inline int get_pse_type(int type)
263 return gtt_type_table[type].pse_entry_type;
266 static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
268 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
273 static void ggtt_invalidate(struct drm_i915_private *dev_priv)
275 mmio_hw_access_pre(dev_priv);
276 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
277 mmio_hw_access_post(dev_priv);
280 static void write_pte64(struct drm_i915_private *dev_priv,
281 unsigned long index, u64 pte)
283 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
288 static inline int gtt_get_entry64(void *pt,
289 struct intel_gvt_gtt_entry *e,
290 unsigned long index, bool hypervisor_access, unsigned long gpa,
291 struct intel_vgpu *vgpu)
293 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
296 if (WARN_ON(info->gtt_entry_size != 8))
299 if (hypervisor_access) {
300 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
301 (index << info->gtt_entry_size_shift),
306 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
308 e->val64 = *((u64 *)pt + index);
313 static inline int gtt_set_entry64(void *pt,
314 struct intel_gvt_gtt_entry *e,
315 unsigned long index, bool hypervisor_access, unsigned long gpa,
316 struct intel_vgpu *vgpu)
318 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
321 if (WARN_ON(info->gtt_entry_size != 8))
324 if (hypervisor_access) {
325 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
326 (index << info->gtt_entry_size_shift),
331 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
333 *((u64 *)pt + index) = e->val64;
340 #define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
341 #define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
342 #define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
344 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
348 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
349 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
350 else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
351 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
353 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
357 static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
359 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
360 e->val64 &= ~ADDR_1G_MASK;
361 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
362 } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
363 e->val64 &= ~ADDR_2M_MASK;
364 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
366 e->val64 &= ~ADDR_4K_MASK;
367 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
370 e->val64 |= (pfn << PAGE_SHIFT);
373 static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
375 /* Entry doesn't have PSE bit. */
376 if (get_pse_type(e->type) == GTT_TYPE_INVALID)
379 e->type = get_entry_type(e->type);
380 if (!(e->val64 & _PAGE_PSE))
383 e->type = get_pse_type(e->type);
387 static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
390 * i915 writes PDP root pointer registers without present bit,
391 * it also works, so we need to treat root pointer entry
394 if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
395 || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
396 return (e->val64 != 0);
398 return (e->val64 & _PAGE_PRESENT);
401 static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
403 e->val64 &= ~_PAGE_PRESENT;
406 static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
408 e->val64 |= _PAGE_PRESENT;
412 * Per-platform GMA routines.
414 static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
416 unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
418 trace_gma_index(__func__, gma, x);
422 #define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
423 static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
425 unsigned long x = (exp); \
426 trace_gma_index(__func__, gma, x); \
430 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
431 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
432 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
433 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
434 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
436 static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
437 .get_entry = gtt_get_entry64,
438 .set_entry = gtt_set_entry64,
439 .clear_present = gtt_entry_clear_present,
440 .set_present = gtt_entry_set_present,
441 .test_present = gen8_gtt_test_present,
442 .test_pse = gen8_gtt_test_pse,
443 .get_pfn = gen8_gtt_get_pfn,
444 .set_pfn = gen8_gtt_set_pfn,
447 static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
448 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
449 .gma_to_pte_index = gen8_gma_to_pte_index,
450 .gma_to_pde_index = gen8_gma_to_pde_index,
451 .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
452 .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
453 .gma_to_pml4_index = gen8_gma_to_pml4_index,
459 static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
460 struct intel_gvt_gtt_entry *entry, unsigned long index,
463 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
465 GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
467 entry->type = mm->ppgtt_mm.root_entry_type;
468 pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
469 mm->ppgtt_mm.shadow_pdps,
470 entry, index, false, 0, mm->vgpu);
472 pte_ops->test_pse(entry);
475 static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
476 struct intel_gvt_gtt_entry *entry, unsigned long index)
478 _ppgtt_get_root_entry(mm, entry, index, true);
481 static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
482 struct intel_gvt_gtt_entry *entry, unsigned long index)
484 _ppgtt_get_root_entry(mm, entry, index, false);
487 static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
488 struct intel_gvt_gtt_entry *entry, unsigned long index,
491 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
493 pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
494 mm->ppgtt_mm.shadow_pdps,
495 entry, index, false, 0, mm->vgpu);
498 static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
499 struct intel_gvt_gtt_entry *entry, unsigned long index)
501 _ppgtt_set_root_entry(mm, entry, index, true);
504 static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
505 struct intel_gvt_gtt_entry *entry, unsigned long index)
507 _ppgtt_set_root_entry(mm, entry, index, false);
510 static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
511 struct intel_gvt_gtt_entry *entry, unsigned long index)
513 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
515 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
517 entry->type = GTT_TYPE_GGTT_PTE;
518 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
522 static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
523 struct intel_gvt_gtt_entry *entry, unsigned long index)
525 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
527 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
529 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
533 static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
534 struct intel_gvt_gtt_entry *entry, unsigned long index)
536 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
538 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
540 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
543 static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
544 struct intel_gvt_gtt_entry *entry, unsigned long index)
546 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
548 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
550 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
554 * PPGTT shadow page table helpers.
556 static inline int ppgtt_spt_get_entry(
557 struct intel_vgpu_ppgtt_spt *spt,
558 void *page_table, int type,
559 struct intel_gvt_gtt_entry *e, unsigned long index,
562 struct intel_gvt *gvt = spt->vgpu->gvt;
563 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
566 e->type = get_entry_type(type);
568 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
571 ret = ops->get_entry(page_table, e, index, guest,
572 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
579 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
580 type, e->type, index, e->val64);
584 static inline int ppgtt_spt_set_entry(
585 struct intel_vgpu_ppgtt_spt *spt,
586 void *page_table, int type,
587 struct intel_gvt_gtt_entry *e, unsigned long index,
590 struct intel_gvt *gvt = spt->vgpu->gvt;
591 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
593 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
596 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
597 type, e->type, index, e->val64);
599 return ops->set_entry(page_table, e, index, guest,
600 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
604 #define ppgtt_get_guest_entry(spt, e, index) \
605 ppgtt_spt_get_entry(spt, NULL, \
606 spt->guest_page.type, e, index, true)
608 #define ppgtt_set_guest_entry(spt, e, index) \
609 ppgtt_spt_set_entry(spt, NULL, \
610 spt->guest_page.type, e, index, true)
612 #define ppgtt_get_shadow_entry(spt, e, index) \
613 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
614 spt->shadow_page.type, e, index, false)
616 #define ppgtt_set_shadow_entry(spt, e, index) \
617 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
618 spt->shadow_page.type, e, index, false)
620 static void *alloc_spt(gfp_t gfp_mask)
622 struct intel_vgpu_ppgtt_spt *spt;
624 spt = kzalloc(sizeof(*spt), gfp_mask);
628 spt->shadow_page.page = alloc_page(gfp_mask);
629 if (!spt->shadow_page.page) {
636 static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
638 __free_page(spt->shadow_page.page);
642 static int detach_oos_page(struct intel_vgpu *vgpu,
643 struct intel_vgpu_oos_page *oos_page);
645 static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
647 struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
649 trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
651 dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
652 PCI_DMA_BIDIRECTIONAL);
654 radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
656 if (spt->guest_page.oos_page)
657 detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
659 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
661 list_del_init(&spt->post_shadow_list);
665 static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
667 struct intel_vgpu_ppgtt_spt *spt;
668 struct radix_tree_iter iter;
671 radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
672 spt = radix_tree_deref_slot(slot);
677 static int ppgtt_handle_guest_write_page_table_bytes(
678 struct intel_vgpu_ppgtt_spt *spt,
679 u64 pa, void *p_data, int bytes);
681 static int ppgtt_write_protection_handler(
682 struct intel_vgpu_page_track *page_track,
683 u64 gpa, void *data, int bytes)
685 struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
689 if (bytes != 4 && bytes != 8)
692 ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
698 /* Find a spt by guest gfn. */
699 static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
700 struct intel_vgpu *vgpu, unsigned long gfn)
702 struct intel_vgpu_page_track *track;
704 track = intel_vgpu_find_page_track(vgpu, gfn);
705 if (track && track->handler == ppgtt_write_protection_handler)
706 return track->priv_data;
711 /* Find the spt by shadow page mfn. */
712 static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
713 struct intel_vgpu *vgpu, unsigned long mfn)
715 return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
718 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
720 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
721 struct intel_vgpu *vgpu, int type, unsigned long gfn)
723 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
724 struct intel_vgpu_ppgtt_spt *spt = NULL;
729 spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
731 if (reclaim_one_ppgtt_mm(vgpu->gvt))
734 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
735 return ERR_PTR(-ENOMEM);
739 atomic_set(&spt->refcount, 1);
740 INIT_LIST_HEAD(&spt->post_shadow_list);
745 spt->shadow_page.type = type;
746 daddr = dma_map_page(kdev, spt->shadow_page.page,
747 0, 4096, PCI_DMA_BIDIRECTIONAL);
748 if (dma_mapping_error(kdev, daddr)) {
749 gvt_vgpu_err("fail to map dma addr\n");
753 spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
754 spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
759 spt->guest_page.type = type;
760 spt->guest_page.gfn = gfn;
762 ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
763 ppgtt_write_protection_handler, spt);
767 ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
769 goto err_unreg_page_track;
771 trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
774 err_unreg_page_track:
775 intel_vgpu_unregister_page_track(vgpu, spt->guest_page.gfn);
777 dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
783 #define pt_entry_size_shift(spt) \
784 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
786 #define pt_entries(spt) \
787 (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
789 #define for_each_present_guest_entry(spt, e, i) \
790 for (i = 0; i < pt_entries(spt); i++) \
791 if (!ppgtt_get_guest_entry(spt, e, i) && \
792 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
794 #define for_each_present_shadow_entry(spt, e, i) \
795 for (i = 0; i < pt_entries(spt); i++) \
796 if (!ppgtt_get_shadow_entry(spt, e, i) && \
797 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
799 static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
801 int v = atomic_read(&spt->refcount);
803 trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
805 atomic_inc(&spt->refcount);
808 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
810 static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
811 struct intel_gvt_gtt_entry *e)
813 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
814 struct intel_vgpu_ppgtt_spt *s;
815 intel_gvt_gtt_type_t cur_pt_type;
817 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
819 if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
820 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
821 cur_pt_type = get_next_pt_type(e->type) + 1;
822 if (ops->get_pfn(e) ==
823 vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
826 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
828 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
832 return ppgtt_invalidate_spt(s);
835 static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
836 struct intel_gvt_gtt_entry *entry)
838 struct intel_vgpu *vgpu = spt->vgpu;
839 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
843 pfn = ops->get_pfn(entry);
844 type = spt->shadow_page.type;
846 if (pfn == vgpu->gtt.scratch_pt[type].page_mfn)
849 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
852 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
854 struct intel_vgpu *vgpu = spt->vgpu;
855 struct intel_gvt_gtt_entry e;
858 int v = atomic_read(&spt->refcount);
860 trace_spt_change(spt->vgpu->id, "die", spt,
861 spt->guest_page.gfn, spt->shadow_page.type);
863 trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
865 if (atomic_dec_return(&spt->refcount) > 0)
868 for_each_present_shadow_entry(spt, &e, index) {
870 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
871 gvt_vdbg_mm("invalidate 4K entry\n");
872 ppgtt_invalidate_pte(spt, &e);
874 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
875 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
876 WARN(1, "GVT doesn't support 2M/1GB page\n");
878 case GTT_TYPE_PPGTT_PML4_ENTRY:
879 case GTT_TYPE_PPGTT_PDP_ENTRY:
880 case GTT_TYPE_PPGTT_PDE_ENTRY:
881 gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
882 ret = ppgtt_invalidate_spt_by_shadow_entry(
892 trace_spt_change(spt->vgpu->id, "release", spt,
893 spt->guest_page.gfn, spt->shadow_page.type);
897 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
898 spt, e.val64, e.type);
902 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
904 static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
905 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
907 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
908 struct intel_vgpu_ppgtt_spt *spt = NULL;
911 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
913 spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
917 int type = get_next_pt_type(we->type);
919 spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we));
925 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
929 ret = ppgtt_populate_spt(spt);
933 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
934 spt->shadow_page.type);
938 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
939 spt, we->val64, we->type);
943 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
944 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
946 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
949 se->val64 = ge->val64;
951 ops->set_pfn(se, s->shadow_page.mfn);
954 static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
955 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
956 struct intel_gvt_gtt_entry *ge)
958 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
959 struct intel_gvt_gtt_entry se = *ge;
964 if (!pte_ops->test_present(ge))
967 gfn = pte_ops->get_pfn(ge);
970 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
971 gvt_vdbg_mm("shadow 4K gtt entry\n");
973 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
974 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
975 gvt_vgpu_err("GVT doesn't support 2M/1GB entry\n");
982 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, &dma_addr);
986 pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
987 ppgtt_set_shadow_entry(spt, &se, index);
991 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
993 struct intel_vgpu *vgpu = spt->vgpu;
994 struct intel_gvt *gvt = vgpu->gvt;
995 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
996 struct intel_vgpu_ppgtt_spt *s;
997 struct intel_gvt_gtt_entry se, ge;
998 unsigned long gfn, i;
1001 trace_spt_change(spt->vgpu->id, "born", spt,
1002 spt->guest_page.gfn, spt->shadow_page.type);
1004 for_each_present_guest_entry(spt, &ge, i) {
1005 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1006 s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1011 ppgtt_get_shadow_entry(spt, &se, i);
1012 ppgtt_generate_shadow_entry(&se, s, &ge);
1013 ppgtt_set_shadow_entry(spt, &se, i);
1015 gfn = ops->get_pfn(&ge);
1016 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1017 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1018 ppgtt_set_shadow_entry(spt, &se, i);
1022 ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1029 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1030 spt, ge.val64, ge.type);
1034 static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1035 struct intel_gvt_gtt_entry *se, unsigned long index)
1037 struct intel_vgpu *vgpu = spt->vgpu;
1038 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1041 trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1042 spt->shadow_page.type, se->val64, index);
1044 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1045 se->type, index, se->val64);
1047 if (!ops->test_present(se))
1050 if (ops->get_pfn(se) ==
1051 vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1054 if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1055 struct intel_vgpu_ppgtt_spt *s =
1056 intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
1058 gvt_vgpu_err("fail to find guest page\n");
1062 ret = ppgtt_invalidate_spt(s);
1066 ppgtt_invalidate_pte(spt, se);
1070 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1071 spt, se->val64, se->type);
1075 static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
1076 struct intel_gvt_gtt_entry *we, unsigned long index)
1078 struct intel_vgpu *vgpu = spt->vgpu;
1079 struct intel_gvt_gtt_entry m;
1080 struct intel_vgpu_ppgtt_spt *s;
1083 trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1086 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1087 we->type, index, we->val64);
1089 if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1090 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1095 ppgtt_get_shadow_entry(spt, &m, index);
1096 ppgtt_generate_shadow_entry(&m, s, we);
1097 ppgtt_set_shadow_entry(spt, &m, index);
1099 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1105 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1106 spt, we->val64, we->type);
1110 static int sync_oos_page(struct intel_vgpu *vgpu,
1111 struct intel_vgpu_oos_page *oos_page)
1113 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1114 struct intel_gvt *gvt = vgpu->gvt;
1115 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1116 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1117 struct intel_gvt_gtt_entry old, new;
1121 trace_oos_change(vgpu->id, "sync", oos_page->id,
1122 spt, spt->guest_page.type);
1124 old.type = new.type = get_entry_type(spt->guest_page.type);
1125 old.val64 = new.val64 = 0;
1127 for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1128 info->gtt_entry_size_shift); index++) {
1129 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1130 ops->get_entry(NULL, &new, index, true,
1131 spt->guest_page.gfn << PAGE_SHIFT, vgpu);
1133 if (old.val64 == new.val64
1134 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1137 trace_oos_sync(vgpu->id, oos_page->id,
1138 spt, spt->guest_page.type,
1141 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
1145 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
1148 spt->guest_page.write_cnt = 0;
1149 list_del_init(&spt->post_shadow_list);
1153 static int detach_oos_page(struct intel_vgpu *vgpu,
1154 struct intel_vgpu_oos_page *oos_page)
1156 struct intel_gvt *gvt = vgpu->gvt;
1157 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1159 trace_oos_change(vgpu->id, "detach", oos_page->id,
1160 spt, spt->guest_page.type);
1162 spt->guest_page.write_cnt = 0;
1163 spt->guest_page.oos_page = NULL;
1164 oos_page->spt = NULL;
1166 list_del_init(&oos_page->vm_list);
1167 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1172 static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1173 struct intel_vgpu_ppgtt_spt *spt)
1175 struct intel_gvt *gvt = spt->vgpu->gvt;
1178 ret = intel_gvt_hypervisor_read_gpa(spt->vgpu,
1179 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
1180 oos_page->mem, I915_GTT_PAGE_SIZE);
1184 oos_page->spt = spt;
1185 spt->guest_page.oos_page = oos_page;
1187 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1189 trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1190 spt, spt->guest_page.type);
1194 static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
1196 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1199 ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
1203 trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1204 spt, spt->guest_page.type);
1206 list_del_init(&oos_page->vm_list);
1207 return sync_oos_page(spt->vgpu, oos_page);
1210 static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
1212 struct intel_gvt *gvt = spt->vgpu->gvt;
1213 struct intel_gvt_gtt *gtt = &gvt->gtt;
1214 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1217 WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1219 if (list_empty(>t->oos_page_free_list_head)) {
1220 oos_page = container_of(gtt->oos_page_use_list_head.next,
1221 struct intel_vgpu_oos_page, list);
1222 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1225 ret = detach_oos_page(spt->vgpu, oos_page);
1229 oos_page = container_of(gtt->oos_page_free_list_head.next,
1230 struct intel_vgpu_oos_page, list);
1231 return attach_oos_page(oos_page, spt);
1234 static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
1236 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1238 if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1241 trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1242 spt, spt->guest_page.type);
1244 list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
1245 return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
1249 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1252 * This function is called before submitting a guest workload to host,
1253 * to sync all the out-of-synced shadow for vGPU
1256 * Zero on success, negative error code if failed.
1258 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1260 struct list_head *pos, *n;
1261 struct intel_vgpu_oos_page *oos_page;
1264 if (!enable_out_of_sync)
1267 list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1268 oos_page = container_of(pos,
1269 struct intel_vgpu_oos_page, vm_list);
1270 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1278 * The heart of PPGTT shadow page table.
1280 static int ppgtt_handle_guest_write_page_table(
1281 struct intel_vgpu_ppgtt_spt *spt,
1282 struct intel_gvt_gtt_entry *we, unsigned long index)
1284 struct intel_vgpu *vgpu = spt->vgpu;
1285 int type = spt->shadow_page.type;
1286 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1287 struct intel_gvt_gtt_entry old_se;
1291 new_present = ops->test_present(we);
1294 * Adding the new entry first and then removing the old one, that can
1295 * guarantee the ppgtt table is validated during the window between
1296 * adding and removal.
1298 ppgtt_get_shadow_entry(spt, &old_se, index);
1301 ret = ppgtt_handle_guest_entry_add(spt, we, index);
1306 ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
1311 ops->set_pfn(&old_se, vgpu->gtt.scratch_pt[type].page_mfn);
1312 ppgtt_set_shadow_entry(spt, &old_se, index);
1317 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1318 spt, we->val64, we->type);
1324 static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
1326 return enable_out_of_sync
1327 && gtt_type_is_pte_pt(spt->guest_page.type)
1328 && spt->guest_page.write_cnt >= 2;
1331 static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1332 unsigned long index)
1334 set_bit(index, spt->post_shadow_bitmap);
1335 if (!list_empty(&spt->post_shadow_list))
1338 list_add_tail(&spt->post_shadow_list,
1339 &spt->vgpu->gtt.post_shadow_list_head);
1343 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1346 * This function is called before submitting a guest workload to host,
1347 * to flush all the post shadows for a vGPU.
1350 * Zero on success, negative error code if failed.
1352 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1354 struct list_head *pos, *n;
1355 struct intel_vgpu_ppgtt_spt *spt;
1356 struct intel_gvt_gtt_entry ge;
1357 unsigned long index;
1360 list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1361 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1364 for_each_set_bit(index, spt->post_shadow_bitmap,
1365 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1366 ppgtt_get_guest_entry(spt, &ge, index);
1368 ret = ppgtt_handle_guest_write_page_table(spt,
1372 clear_bit(index, spt->post_shadow_bitmap);
1374 list_del_init(&spt->post_shadow_list);
1379 static int ppgtt_handle_guest_write_page_table_bytes(
1380 struct intel_vgpu_ppgtt_spt *spt,
1381 u64 pa, void *p_data, int bytes)
1383 struct intel_vgpu *vgpu = spt->vgpu;
1384 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1385 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1386 struct intel_gvt_gtt_entry we, se;
1387 unsigned long index;
1390 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1392 ppgtt_get_guest_entry(spt, &we, index);
1396 if (bytes == info->gtt_entry_size) {
1397 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
1401 if (!test_bit(index, spt->post_shadow_bitmap)) {
1402 int type = spt->shadow_page.type;
1404 ppgtt_get_shadow_entry(spt, &se, index);
1405 ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
1408 ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1409 ppgtt_set_shadow_entry(spt, &se, index);
1411 ppgtt_set_post_shadow(spt, index);
1414 if (!enable_out_of_sync)
1417 spt->guest_page.write_cnt++;
1419 if (spt->guest_page.oos_page)
1420 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
1423 if (can_do_out_of_sync(spt)) {
1424 if (!spt->guest_page.oos_page)
1425 ppgtt_allocate_oos_page(spt);
1427 ret = ppgtt_set_guest_page_oos(spt);
1434 static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
1436 struct intel_vgpu *vgpu = mm->vgpu;
1437 struct intel_gvt *gvt = vgpu->gvt;
1438 struct intel_gvt_gtt *gtt = &gvt->gtt;
1439 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1440 struct intel_gvt_gtt_entry se;
1443 if (!mm->ppgtt_mm.shadowed)
1446 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1447 ppgtt_get_shadow_root_entry(mm, &se, index);
1449 if (!ops->test_present(&se))
1452 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
1454 ppgtt_set_shadow_root_entry(mm, &se, index);
1456 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1457 NULL, se.type, se.val64, index);
1460 mm->ppgtt_mm.shadowed = false;
1464 static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
1466 struct intel_vgpu *vgpu = mm->vgpu;
1467 struct intel_gvt *gvt = vgpu->gvt;
1468 struct intel_gvt_gtt *gtt = &gvt->gtt;
1469 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1470 struct intel_vgpu_ppgtt_spt *spt;
1471 struct intel_gvt_gtt_entry ge, se;
1474 if (mm->ppgtt_mm.shadowed)
1477 mm->ppgtt_mm.shadowed = true;
1479 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1480 ppgtt_get_guest_root_entry(mm, &ge, index);
1482 if (!ops->test_present(&ge))
1485 trace_spt_guest_change(vgpu->id, __func__, NULL,
1486 ge.type, ge.val64, index);
1488 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1490 gvt_vgpu_err("fail to populate guest root pointer\n");
1494 ppgtt_generate_shadow_entry(&se, spt, &ge);
1495 ppgtt_set_shadow_root_entry(mm, &se, index);
1497 trace_spt_guest_change(vgpu->id, "populate root pointer",
1498 NULL, se.type, se.val64, index);
1503 invalidate_ppgtt_mm(mm);
1507 static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1509 struct intel_vgpu_mm *mm;
1511 mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1516 kref_init(&mm->ref);
1517 atomic_set(&mm->pincount, 0);
1522 static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1528 * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
1530 * @root_entry_type: ppgtt root entry type
1531 * @pdps: guest pdps.
1533 * This function is used to create a ppgtt mm object for a vGPU.
1536 * Zero on success, negative error code in pointer if failed.
1538 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1539 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
1541 struct intel_gvt *gvt = vgpu->gvt;
1542 struct intel_vgpu_mm *mm;
1545 mm = vgpu_alloc_mm(vgpu);
1547 return ERR_PTR(-ENOMEM);
1549 mm->type = INTEL_GVT_MM_PPGTT;
1551 GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1552 root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1553 mm->ppgtt_mm.root_entry_type = root_entry_type;
1555 INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1556 INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
1558 if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1559 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1561 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1562 sizeof(mm->ppgtt_mm.guest_pdps));
1564 ret = shadow_ppgtt_mm(mm);
1566 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1568 return ERR_PTR(ret);
1571 list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1572 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1576 static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1578 struct intel_vgpu_mm *mm;
1579 unsigned long nr_entries;
1581 mm = vgpu_alloc_mm(vgpu);
1583 return ERR_PTR(-ENOMEM);
1585 mm->type = INTEL_GVT_MM_GGTT;
1587 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1588 mm->ggtt_mm.virtual_ggtt = vzalloc(nr_entries *
1589 vgpu->gvt->device_info.gtt_entry_size);
1590 if (!mm->ggtt_mm.virtual_ggtt) {
1592 return ERR_PTR(-ENOMEM);
1599 * _intel_vgpu_mm_release - destroy a mm object
1600 * @mm_ref: a kref object
1602 * This function is used to destroy a mm object for vGPU
1605 void _intel_vgpu_mm_release(struct kref *mm_ref)
1607 struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1609 if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1610 gvt_err("vgpu mm pin count bug detected\n");
1612 if (mm->type == INTEL_GVT_MM_PPGTT) {
1613 list_del(&mm->ppgtt_mm.list);
1614 list_del(&mm->ppgtt_mm.lru_list);
1615 invalidate_ppgtt_mm(mm);
1617 vfree(mm->ggtt_mm.virtual_ggtt);
1624 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1625 * @mm: a vGPU mm object
1627 * This function is called when user doesn't want to use a vGPU mm object
1629 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1631 atomic_dec(&mm->pincount);
1635 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1638 * This function is called when user wants to use a vGPU mm object. If this
1639 * mm object hasn't been shadowed yet, the shadow will be populated at this
1643 * Zero on success, negative error code if failed.
1645 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1649 atomic_inc(&mm->pincount);
1651 if (mm->type == INTEL_GVT_MM_PPGTT) {
1652 ret = shadow_ppgtt_mm(mm);
1656 list_move_tail(&mm->ppgtt_mm.lru_list,
1657 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1664 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
1666 struct intel_vgpu_mm *mm;
1667 struct list_head *pos, *n;
1669 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
1670 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
1672 if (atomic_read(&mm->pincount))
1675 list_del_init(&mm->ppgtt_mm.lru_list);
1676 invalidate_ppgtt_mm(mm);
1683 * GMA translation APIs.
1685 static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
1686 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
1688 struct intel_vgpu *vgpu = mm->vgpu;
1689 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1690 struct intel_vgpu_ppgtt_spt *s;
1692 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
1697 ppgtt_get_shadow_entry(s, e, index);
1699 ppgtt_get_guest_entry(s, e, index);
1704 * intel_vgpu_gma_to_gpa - translate a gma to GPA
1705 * @mm: mm object. could be a PPGTT or GGTT mm object
1706 * @gma: graphics memory address in this mm object
1708 * This function is used to translate a graphics memory address in specific
1709 * graphics memory space to guest physical address.
1712 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
1714 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
1716 struct intel_vgpu *vgpu = mm->vgpu;
1717 struct intel_gvt *gvt = vgpu->gvt;
1718 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
1719 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
1720 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
1721 unsigned long gma_index[4];
1722 struct intel_gvt_gtt_entry e;
1726 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
1727 mm->type != INTEL_GVT_MM_PPGTT);
1729 if (mm->type == INTEL_GVT_MM_GGTT) {
1730 if (!vgpu_gmadr_is_valid(vgpu, gma))
1733 ggtt_get_guest_entry(mm, &e,
1734 gma_ops->gma_to_ggtt_pte_index(gma));
1736 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
1737 + (gma & ~I915_GTT_PAGE_MASK);
1739 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
1741 switch (mm->ppgtt_mm.root_entry_type) {
1742 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
1743 ppgtt_get_shadow_root_entry(mm, &e, 0);
1745 gma_index[0] = gma_ops->gma_to_pml4_index(gma);
1746 gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
1747 gma_index[2] = gma_ops->gma_to_pde_index(gma);
1748 gma_index[3] = gma_ops->gma_to_pte_index(gma);
1751 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
1752 ppgtt_get_shadow_root_entry(mm, &e,
1753 gma_ops->gma_to_l3_pdp_index(gma));
1755 gma_index[0] = gma_ops->gma_to_pde_index(gma);
1756 gma_index[1] = gma_ops->gma_to_pte_index(gma);
1763 /* walk the shadow page table and get gpa from guest entry */
1764 for (i = 0; i < levels; i++) {
1765 ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
1770 if (!pte_ops->test_present(&e)) {
1771 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
1776 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
1777 (gma & ~I915_GTT_PAGE_MASK);
1778 trace_gma_translate(vgpu->id, "ppgtt", 0,
1779 mm->ppgtt_mm.root_entry_type, gma, gpa);
1784 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
1785 return INTEL_GVT_INVALID_ADDR;
1788 static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
1789 unsigned int off, void *p_data, unsigned int bytes)
1791 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1792 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1793 unsigned long index = off >> info->gtt_entry_size_shift;
1794 struct intel_gvt_gtt_entry e;
1796 if (bytes != 4 && bytes != 8)
1799 ggtt_get_guest_entry(ggtt_mm, &e, index);
1800 memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
1806 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
1808 * @off: register offset
1809 * @p_data: data will be returned to guest
1810 * @bytes: data length
1812 * This function is used to emulate the GTT MMIO register read
1815 * Zero on success, error code if failed.
1817 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
1818 void *p_data, unsigned int bytes)
1820 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1823 if (bytes != 4 && bytes != 8)
1826 off -= info->gtt_start_offset;
1827 ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
1831 static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
1832 struct intel_gvt_gtt_entry *entry)
1834 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1837 pfn = pte_ops->get_pfn(entry);
1838 if (pfn != vgpu->gvt->gtt.scratch_mfn)
1839 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu,
1843 static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
1844 void *p_data, unsigned int bytes)
1846 struct intel_gvt *gvt = vgpu->gvt;
1847 const struct intel_gvt_device_info *info = &gvt->device_info;
1848 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1849 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1850 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
1851 unsigned long gma, gfn;
1852 struct intel_gvt_gtt_entry e, m;
1853 dma_addr_t dma_addr;
1856 if (bytes != 4 && bytes != 8)
1859 gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
1861 /* the VM may configure the whole GM space when ballooning is used */
1862 if (!vgpu_gmadr_is_valid(vgpu, gma))
1865 ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
1867 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
1870 if (ops->test_present(&e)) {
1871 gfn = ops->get_pfn(&e);
1874 /* one PTE update may be issued in multiple writes and the
1875 * first write may not construct a valid gfn
1877 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1878 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
1882 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn,
1885 gvt_vgpu_err("fail to populate guest ggtt entry\n");
1886 /* guest driver may read/write the entry when partial
1887 * update the entry in this situation p2m will fail
1888 * settting the shadow entry to point to a scratch page
1890 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
1892 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
1894 ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
1895 ggtt_invalidate_pte(vgpu, &m);
1896 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
1897 ops->clear_present(&m);
1901 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
1902 ggtt_invalidate(gvt->dev_priv);
1903 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
1908 * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
1910 * @off: register offset
1911 * @p_data: data from guest write
1912 * @bytes: data length
1914 * This function is used to emulate the GTT MMIO register write
1917 * Zero on success, error code if failed.
1919 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
1920 unsigned int off, void *p_data, unsigned int bytes)
1922 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1925 if (bytes != 4 && bytes != 8)
1928 off -= info->gtt_start_offset;
1929 ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
1933 static int alloc_scratch_pages(struct intel_vgpu *vgpu,
1934 intel_gvt_gtt_type_t type)
1936 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
1937 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1938 int page_entry_num = I915_GTT_PAGE_SIZE >>
1939 vgpu->gvt->device_info.gtt_entry_size_shift;
1942 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
1945 if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
1948 scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
1950 gvt_vgpu_err("fail to allocate scratch page\n");
1954 daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
1955 4096, PCI_DMA_BIDIRECTIONAL);
1956 if (dma_mapping_error(dev, daddr)) {
1957 gvt_vgpu_err("fail to dmamap scratch_pt\n");
1958 __free_page(virt_to_page(scratch_pt));
1961 gtt->scratch_pt[type].page_mfn =
1962 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
1963 gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
1964 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
1965 vgpu->id, type, gtt->scratch_pt[type].page_mfn);
1967 /* Build the tree by full filled the scratch pt with the entries which
1968 * point to the next level scratch pt or scratch page. The
1969 * scratch_pt[type] indicate the scratch pt/scratch page used by the
1971 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
1972 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
1973 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
1975 if (type > GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX) {
1976 struct intel_gvt_gtt_entry se;
1978 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
1979 se.type = get_entry_type(type - 1);
1980 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
1982 /* The entry parameters like present/writeable/cache type
1983 * set to the same as i915's scratch page tree.
1985 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
1986 if (type == GTT_TYPE_PPGTT_PDE_PT)
1987 se.val64 |= PPAT_CACHED;
1989 for (i = 0; i < page_entry_num; i++)
1990 ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
1996 static int release_scratch_page_tree(struct intel_vgpu *vgpu)
1999 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2002 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2003 if (vgpu->gtt.scratch_pt[i].page != NULL) {
2004 daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
2005 I915_GTT_PAGE_SHIFT);
2006 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2007 __free_page(vgpu->gtt.scratch_pt[i].page);
2008 vgpu->gtt.scratch_pt[i].page = NULL;
2009 vgpu->gtt.scratch_pt[i].page_mfn = 0;
2016 static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2020 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2021 ret = alloc_scratch_pages(vgpu, i);
2029 release_scratch_page_tree(vgpu);
2034 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2037 * This function is used to initialize per-vGPU graphics memory virtualization
2041 * Zero on success, error code if failed.
2043 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2045 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2047 INIT_RADIX_TREE(>t->spt_tree, GFP_KERNEL);
2049 INIT_LIST_HEAD(>t->ppgtt_mm_list_head);
2050 INIT_LIST_HEAD(>t->oos_page_list_head);
2051 INIT_LIST_HEAD(>t->post_shadow_list_head);
2053 gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2054 if (IS_ERR(gtt->ggtt_mm)) {
2055 gvt_vgpu_err("fail to create mm for ggtt.\n");
2056 return PTR_ERR(gtt->ggtt_mm);
2059 intel_vgpu_reset_ggtt(vgpu, false);
2061 return create_scratch_page_tree(vgpu);
2064 static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2066 struct list_head *pos, *n;
2067 struct intel_vgpu_mm *mm;
2069 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2070 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2071 intel_vgpu_destroy_mm(mm);
2074 if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
2075 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
2077 if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
2078 gvt_err("Why we still has spt not freed?\n");
2079 ppgtt_free_all_spt(vgpu);
2083 static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2085 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2086 vgpu->gtt.ggtt_mm = NULL;
2090 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2093 * This function is used to clean up per-vGPU graphics memory virtualization
2097 * Zero on success, error code if failed.
2099 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2101 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2102 intel_vgpu_destroy_ggtt_mm(vgpu);
2103 release_scratch_page_tree(vgpu);
2106 static void clean_spt_oos(struct intel_gvt *gvt)
2108 struct intel_gvt_gtt *gtt = &gvt->gtt;
2109 struct list_head *pos, *n;
2110 struct intel_vgpu_oos_page *oos_page;
2112 WARN(!list_empty(>t->oos_page_use_list_head),
2113 "someone is still using oos page\n");
2115 list_for_each_safe(pos, n, >t->oos_page_free_list_head) {
2116 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2117 list_del(&oos_page->list);
2122 static int setup_spt_oos(struct intel_gvt *gvt)
2124 struct intel_gvt_gtt *gtt = &gvt->gtt;
2125 struct intel_vgpu_oos_page *oos_page;
2129 INIT_LIST_HEAD(>t->oos_page_free_list_head);
2130 INIT_LIST_HEAD(>t->oos_page_use_list_head);
2132 for (i = 0; i < preallocated_oos_pages; i++) {
2133 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2139 INIT_LIST_HEAD(&oos_page->list);
2140 INIT_LIST_HEAD(&oos_page->vm_list);
2142 list_add_tail(&oos_page->list, >t->oos_page_free_list_head);
2145 gvt_dbg_mm("%d oos pages preallocated\n", i);
2154 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2156 * @page_table_level: PPGTT page table level
2157 * @root_entry: PPGTT page table root pointers
2159 * This function is used to find a PPGTT mm object from mm object pool
2162 * pointer to mm object on success, NULL if failed.
2164 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
2167 struct intel_vgpu_mm *mm;
2168 struct list_head *pos;
2170 list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2171 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2173 switch (mm->ppgtt_mm.root_entry_type) {
2174 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2175 if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2178 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2179 if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2180 sizeof(mm->ppgtt_mm.guest_pdps)))
2191 * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2193 * @root_entry_type: ppgtt root entry type
2196 * This function is used to find or create a PPGTT mm object from a guest.
2199 * Zero on success, negative error code if failed.
2201 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
2202 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2204 struct intel_vgpu_mm *mm;
2206 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2208 intel_vgpu_mm_get(mm);
2210 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
2212 gvt_vgpu_err("fail to create mm\n");
2218 * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2222 * This function is used to find a PPGTT mm object from a guest and destroy it.
2225 * Zero on success, negative error code if failed.
2227 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2229 struct intel_vgpu_mm *mm;
2231 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2233 gvt_vgpu_err("fail to find ppgtt instance.\n");
2236 intel_vgpu_mm_put(mm);
2241 * intel_gvt_init_gtt - initialize mm components of a GVT device
2244 * This function is called at the initialization stage, to initialize
2245 * the mm components of a GVT device.
2248 * zero on success, negative error code if failed.
2250 int intel_gvt_init_gtt(struct intel_gvt *gvt)
2254 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2257 gvt_dbg_core("init gtt\n");
2259 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
2260 || IS_KABYLAKE(gvt->dev_priv)) {
2261 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2262 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2267 page = (void *)get_zeroed_page(GFP_KERNEL);
2269 gvt_err("fail to allocate scratch ggtt page\n");
2273 daddr = dma_map_page(dev, virt_to_page(page), 0,
2274 4096, PCI_DMA_BIDIRECTIONAL);
2275 if (dma_mapping_error(dev, daddr)) {
2276 gvt_err("fail to dmamap scratch ggtt page\n");
2277 __free_page(virt_to_page(page));
2281 gvt->gtt.scratch_page = virt_to_page(page);
2282 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2284 if (enable_out_of_sync) {
2285 ret = setup_spt_oos(gvt);
2287 gvt_err("fail to initialize SPT oos\n");
2288 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2289 __free_page(gvt->gtt.scratch_page);
2293 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2298 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2301 * This function is called at the driver unloading stage, to clean up the
2302 * the mm components of a GVT device.
2305 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2307 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2308 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2309 I915_GTT_PAGE_SHIFT);
2311 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2313 __free_page(gvt->gtt.scratch_page);
2315 if (enable_out_of_sync)
2320 * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2323 * This function is called when invalidate all PPGTT instances of a vGPU.
2326 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2328 struct list_head *pos, *n;
2329 struct intel_vgpu_mm *mm;
2331 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2332 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2333 if (mm->type == INTEL_GVT_MM_PPGTT) {
2334 list_del_init(&mm->ppgtt_mm.lru_list);
2335 if (mm->ppgtt_mm.shadowed)
2336 invalidate_ppgtt_mm(mm);
2342 * intel_vgpu_reset_ggtt - reset the GGTT entry
2344 * @invalidate_old: invalidate old entries
2346 * This function is called at the vGPU create stage
2347 * to reset all the GGTT entries.
2350 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
2352 struct intel_gvt *gvt = vgpu->gvt;
2353 struct drm_i915_private *dev_priv = gvt->dev_priv;
2354 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2355 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
2356 struct intel_gvt_gtt_entry old_entry;
2360 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2361 pte_ops->set_present(&entry);
2363 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2364 num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2365 while (num_entries--) {
2366 if (invalidate_old) {
2367 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2368 ggtt_invalidate_pte(vgpu, &old_entry);
2370 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2373 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2374 num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2375 while (num_entries--) {
2376 if (invalidate_old) {
2377 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2378 ggtt_invalidate_pte(vgpu, &old_entry);
2380 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2383 ggtt_invalidate(dev_priv);
2387 * intel_vgpu_reset_gtt - reset the all GTT related status
2390 * This function is called from vfio core to reset reset all
2391 * GTT related status, including GGTT, PPGTT, scratch page.
2394 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
2396 /* Shadow pages are only created when there is no page
2397 * table tracking data, so remove page tracking data after
2398 * removing the shadow pages.
2400 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2401 intel_vgpu_reset_ggtt(vgpu, true);