drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38
  39 #include "i915_drv.h"
  40 #include "gt/intel_ring.h"
  41 #include "gvt.h"
  42 #include "i915_pvinfo.h"
  43 #include "trace.h"
  44
  45 #define INVALID_OP    (~0U)
  46
  47 #define OP_LEN_MI           9
  48 #define OP_LEN_2D           10
  49 #define OP_LEN_3D_MEDIA     16
  50 #define OP_LEN_MFX_VC       16
  51 #define OP_LEN_VEBOX        16
  52
  53 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  54
  55 struct sub_op_bits {
  56         int hi;
  57         int low;
  58 };
  59 struct decode_info {
  60         const char *name;
  61         int op_len;
  62         int nr_sub_op;
  63         const struct sub_op_bits *sub_op;
  64 };
  65
  66 #define   MAX_CMD_BUDGET                        0x7fffffff
  67 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  68 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  69 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  70
  71 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  72 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  73 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  74
  75 /* Render Command Map */
  76
  77 /* MI_* command Opcode (28:23) */
  78 #define OP_MI_NOOP                          0x0
  79 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  80 #define OP_MI_USER_INTERRUPT                0x2
  81 #define OP_MI_WAIT_FOR_EVENT                0x3
  82 #define OP_MI_FLUSH                         0x4
  83 #define OP_MI_ARB_CHECK                     0x5
  84 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  85 #define OP_MI_REPORT_HEAD                   0x7
  86 #define OP_MI_ARB_ON_OFF                    0x8
  87 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  88 #define OP_MI_BATCH_BUFFER_END              0xA
  89 #define OP_MI_SUSPEND_FLUSH                 0xB
  90 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  91 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  92 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  93 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  94 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  95 #define OP_MI_DISPLAY_FLIP                  0x14
  96 #define OP_MI_SEMAPHORE_MBOX                0x16
  97 #define OP_MI_SET_CONTEXT                   0x18
  98 #define OP_MI_MATH                          0x1A
  99 #define OP_MI_URB_CLEAR                     0x19
 100 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
 101 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 102
 103 #define OP_MI_STORE_DATA_IMM                0x20
 104 #define OP_MI_STORE_DATA_INDEX              0x21
 105 #define OP_MI_LOAD_REGISTER_IMM             0x22
 106 #define OP_MI_UPDATE_GTT                    0x23
 107 #define OP_MI_STORE_REGISTER_MEM            0x24
 108 #define OP_MI_FLUSH_DW                      0x26
 109 #define OP_MI_CLFLUSH                       0x27
 110 #define OP_MI_REPORT_PERF_COUNT             0x28
 111 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 112 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 113 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 114 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 115 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 116 #define OP_MI_2E                            0x2E  /* BDW+ */
 117 #define OP_MI_2F                            0x2F  /* BDW+ */
 118 #define OP_MI_BATCH_BUFFER_START            0x31
 119
 120 /* Bit definition for dword 0 */
 121 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 122
 123 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 124
 125 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 126 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 127 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 128 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 129
 130 /* 2D command: Opcode (28:22) */
 131 #define OP_2D(x)    ((2<<7) | x)
 132
 133 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 134 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 135 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 136 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 137 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 138 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 139 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 140 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 141 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 142 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 143 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 144 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 145 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 146 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 147 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 148 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 149 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 150 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 151 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 152 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 153 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 154 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 155 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 156 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 157
 158 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 159 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 160         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 161
 162 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 163
 164 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 165 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 166 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 167
 168 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 169
 170 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 171
 172 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 173 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 174 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 175 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 176 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 177 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 178
 179 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 180 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 181 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 182 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 183
 184 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 185 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 186 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 187 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 188 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 189 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 190 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 191 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 192 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 193 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 194 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 195 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 196 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 197 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 198 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 199 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 200 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 201 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 202 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 203 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 204 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 205 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 206 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 207 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 208 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 209 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 210 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 211 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 212 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 213 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 214 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 215 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 219 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 220 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 224 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 225 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 226 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 227 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 228 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 229 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 232 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 233 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 234 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 238 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 239 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 240 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 241 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 242 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 243 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 244 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 247 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 248 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 249 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 250
 251 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 252 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 253 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 254 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 255 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 256 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 257 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 258 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 259 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 260 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 261 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 262
 263 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 264 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 265 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 266 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 267 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 268 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 269 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 270 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 271 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 272 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 273 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 274 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 275 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 276 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 277 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 281 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 282 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 283 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 284 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 285 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 286 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 287 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 288 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 289 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 290 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 291
 292 /* VCCP Command Parser */
 293
 294 /*
 295  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 296  * git://anongit.freedesktop.org/vaapi/intel-driver
 297  * src/i965_defines.h
 298  *
 299  */
 300
 301 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 302         (3 << 13 | \
 303          (pipeline) << 11 | \
 304          (op) << 8 | \
 305          (sub_opa) << 5 | \
 306          (sub_opb))
 307
 308 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 309 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 310 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 311 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 312 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 313 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 314 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 315 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 316 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 317 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 318 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 319
 320 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 321
 322 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 323 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 324 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 325 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 326 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 327 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 328 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 329 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 330 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 331 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 332 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 333 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 334
 335 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 336 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 337 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 338 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 339 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 340
 341 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 342 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 343 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 344 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 345 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 346
 347 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 348 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 349 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 350
 351 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 352 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 353 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 354
 355 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 356         (3 << 13 | \
 357          (pipeline) << 11 | \
 358          (op) << 8 | \
 359          (sub_opa) << 5 | \
 360          (sub_opb))
 361
 362 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 363 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 364 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 365
 366 struct parser_exec_state;
 367
 368 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 369
 370 #define GVT_CMD_HASH_BITS   7
 371
 372 /* which DWords need address fix */
 373 #define ADDR_FIX_1(x1)                  (1 << (x1))
 374 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 375 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 376 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 377 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 378
 379 #define DWORD_FIELD(dword, end, start) \
 380         FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
 381
 382 #define OP_LENGTH_BIAS 2
 383 #define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
 384
 385 static int gvt_check_valid_cmd_length(int len, int valid_len)
 386 {
 387         if (valid_len != len) {
 388                 gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 389                         len, valid_len);
 390                 return -EFAULT;
 391         }
 392         return 0;
 393 }
 394
 395 struct cmd_info {
 396         const char *name;
 397         u32 opcode;
 398
 399 #define F_LEN_MASK      3U
 400 #define F_LEN_CONST  1U
 401 #define F_LEN_VAR    0U
 402 /* value is const although LEN maybe variable */
 403 #define F_LEN_VAR_FIXED    (1<<1)
 404
 405 /*
 406  * command has its own ip advance logic
 407  * e.g. MI_BATCH_START, MI_BATCH_END
 408  */
 409 #define F_IP_ADVANCE_CUSTOM (1<<2)
 410         u32 flag;
 411
 412 #define R_RCS   BIT(RCS0)
 413 #define R_VCS1  BIT(VCS0)
 414 #define R_VCS2  BIT(VCS1)
 415 #define R_VCS   (R_VCS1 | R_VCS2)
 416 #define R_BCS   BIT(BCS0)
 417 #define R_VECS  BIT(VECS0)
 418 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 419         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 420         u16 rings;
 421
 422         /* devices that support this cmd: SNB/IVB/HSW/... */
 423         u16 devices;
 424
 425         /* which DWords are address that need fix up.
 426          * bit 0 means a 32-bit non address operand in command
 427          * bit 1 means address operand, which could be 32-bit
 428          * or 64-bit depending on different architectures.(
 429          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 430          * No matter the address length, each address only takes
 431          * one bit in the bitmap.
 432          */
 433         u16 addr_bitmap;
 434
 435         /* flag == F_LEN_CONST : command length
 436          * flag == F_LEN_VAR : length bias bits
 437          * Note: length is in DWord
 438          */
 439         u32 len;
 440
 441         parser_cmd_handler handler;
 442
 443         /* valid length in DWord */
 444         u32 valid_len;
 445 };
 446
 447 struct cmd_entry {
 448         struct hlist_node hlist;
 449         const struct cmd_info *info;
 450 };
 451
 452 enum {
 453         RING_BUFFER_INSTRUCTION,
 454         BATCH_BUFFER_INSTRUCTION,
 455         BATCH_BUFFER_2ND_LEVEL,
 456 };
 457
 458 enum {
 459         GTT_BUFFER,
 460         PPGTT_BUFFER
 461 };
 462
 463 struct parser_exec_state {
 464         struct intel_vgpu *vgpu;
 465         const struct intel_engine_cs *engine;
 466
 467         int buf_type;
 468
 469         /* batch buffer address type */
 470         int buf_addr_type;
 471
 472         /* graphics memory address of ring buffer start */
 473         unsigned long ring_start;
 474         unsigned long ring_size;
 475         unsigned long ring_head;
 476         unsigned long ring_tail;
 477
 478         /* instruction graphics memory address */
 479         unsigned long ip_gma;
 480
 481         /* mapped va of the instr_gma */
 482         void *ip_va;
 483         void *rb_va;
 484
 485         void *ret_bb_va;
 486         /* next instruction when return from  batch buffer to ring buffer */
 487         unsigned long ret_ip_gma_ring;
 488
 489         /* next instruction when return from 2nd batch buffer to batch buffer */
 490         unsigned long ret_ip_gma_bb;
 491
 492         /* batch buffer address type (GTT or PPGTT)
 493          * used when ret from 2nd level batch buffer
 494          */
 495         int saved_buf_addr_type;
 496         bool is_ctx_wa;
 497
 498         const struct cmd_info *info;
 499
 500         struct intel_vgpu_workload *workload;
 501 };
 502
 503 #define gmadr_dw_number(s)      \
 504         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 505
 506 static unsigned long bypass_scan_mask = 0;
 507
 508 /* ring ALL, type = 0 */
 509 static const struct sub_op_bits sub_op_mi[] = {
 510         {31, 29},
 511         {28, 23},
 512 };
 513
 514 static const struct decode_info decode_info_mi = {
 515         "MI",
 516         OP_LEN_MI,
 517         ARRAY_SIZE(sub_op_mi),
 518         sub_op_mi,
 519 };
 520
 521 /* ring RCS, command type 2 */
 522 static const struct sub_op_bits sub_op_2d[] = {
 523         {31, 29},
 524         {28, 22},
 525 };
 526
 527 static const struct decode_info decode_info_2d = {
 528         "2D",
 529         OP_LEN_2D,
 530         ARRAY_SIZE(sub_op_2d),
 531         sub_op_2d,
 532 };
 533
 534 /* ring RCS, command type 3 */
 535 static const struct sub_op_bits sub_op_3d_media[] = {
 536         {31, 29},
 537         {28, 27},
 538         {26, 24},
 539         {23, 16},
 540 };
 541
 542 static const struct decode_info decode_info_3d_media = {
 543         "3D_Media",
 544         OP_LEN_3D_MEDIA,
 545         ARRAY_SIZE(sub_op_3d_media),
 546         sub_op_3d_media,
 547 };
 548
 549 /* ring VCS, command type 3 */
 550 static const struct sub_op_bits sub_op_mfx_vc[] = {
 551         {31, 29},
 552         {28, 27},
 553         {26, 24},
 554         {23, 21},
 555         {20, 16},
 556 };
 557
 558 static const struct decode_info decode_info_mfx_vc = {
 559         "MFX_VC",
 560         OP_LEN_MFX_VC,
 561         ARRAY_SIZE(sub_op_mfx_vc),
 562         sub_op_mfx_vc,
 563 };
 564
 565 /* ring VECS, command type 3 */
 566 static const struct sub_op_bits sub_op_vebox[] = {
 567         {31, 29},
 568         {28, 27},
 569         {26, 24},
 570         {23, 21},
 571         {20, 16},
 572 };
 573
 574 static const struct decode_info decode_info_vebox = {
 575         "VEBOX",
 576         OP_LEN_VEBOX,
 577         ARRAY_SIZE(sub_op_vebox),
 578         sub_op_vebox,
 579 };
 580
 581 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 582         [RCS0] = {
 583                 &decode_info_mi,
 584                 NULL,
 585                 NULL,
 586                 &decode_info_3d_media,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591         },
 592
 593         [VCS0] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_mfx_vc,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [BCS0] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 &decode_info_2d,
 608                 NULL,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614
 615         [VECS0] = {
 616                 &decode_info_mi,
 617                 NULL,
 618                 NULL,
 619                 &decode_info_vebox,
 620                 NULL,
 621                 NULL,
 622                 NULL,
 623                 NULL,
 624         },
 625
 626         [VCS1] = {
 627                 &decode_info_mi,
 628                 NULL,
 629                 NULL,
 630                 &decode_info_mfx_vc,
 631                 NULL,
 632                 NULL,
 633                 NULL,
 634                 NULL,
 635         },
 636 };
 637
 638 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
 639 {
 640         const struct decode_info *d_info;
 641
 642         d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 643         if (d_info == NULL)
 644                 return INVALID_OP;
 645
 646         return cmd >> (32 - d_info->op_len);
 647 }
 648
 649 static inline const struct cmd_info *
 650 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
 651                const struct intel_engine_cs *engine)
 652 {
 653         struct cmd_entry *e;
 654
 655         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 656                 if (opcode == e->info->opcode &&
 657                     e->info->rings & engine->mask)
 658                         return e->info;
 659         }
 660         return NULL;
 661 }
 662
 663 static inline const struct cmd_info *
 664 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
 665              const struct intel_engine_cs *engine)
 666 {
 667         u32 opcode;
 668
 669         opcode = get_opcode(cmd, engine);
 670         if (opcode == INVALID_OP)
 671                 return NULL;
 672
 673         return find_cmd_entry(gvt, opcode, engine);
 674 }
 675
 676 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 677 {
 678         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 679 }
 680
 681 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
 682 {
 683         const struct decode_info *d_info;
 684         int i;
 685
 686         d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 687         if (d_info == NULL)
 688                 return;
 689
 690         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 691                         cmd >> (32 - d_info->op_len), d_info->name);
 692
 693         for (i = 0; i < d_info->nr_sub_op; i++)
 694                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 695                                         d_info->sub_op[i].low));
 696
 697         pr_err("\n");
 698 }
 699
 700 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 701 {
 702         return s->ip_va + (index << 2);
 703 }
 704
 705 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 706 {
 707         return *cmd_ptr(s, index);
 708 }
 709
 710 static void parser_exec_state_dump(struct parser_exec_state *s)
 711 {
 712         int cnt = 0;
 713         int i;
 714
 715         gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
 716                     " ring_head(%08lx) ring_tail(%08lx)\n",
 717                     s->vgpu->id, s->engine->name,
 718                     s->ring_start, s->ring_start + s->ring_size,
 719                     s->ring_head, s->ring_tail);
 720
 721         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 722                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 723                         "RING_BUFFER" : "BATCH_BUFFER",
 724                         s->buf_addr_type == GTT_BUFFER ?
 725                         "GTT" : "PPGTT", s->ip_gma);
 726
 727         if (s->ip_va == NULL) {
 728                 gvt_dbg_cmd(" ip_va(NULL)");
 729                 return;
 730         }
 731
 732         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 733                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 734                         cmd_val(s, 2), cmd_val(s, 3));
 735
 736         print_opcode(cmd_val(s, 0), s->engine);
 737
 738         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 739
 740         while (cnt < 1024) {
 741                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 742                 for (i = 0; i < 8; i++)
 743                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 744                 gvt_dbg_cmd("\n");
 745
 746                 s->ip_va += 8 * sizeof(u32);
 747                 cnt += 8;
 748         }
 749 }
 750
 751 static inline void update_ip_va(struct parser_exec_state *s)
 752 {
 753         unsigned long len = 0;
 754
 755         if (WARN_ON(s->ring_head == s->ring_tail))
 756                 return;
 757
 758         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 759                 unsigned long ring_top = s->ring_start + s->ring_size;
 760
 761                 if (s->ring_head > s->ring_tail) {
 762                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 763                                 len = (s->ip_gma - s->ring_head);
 764                         else if (s->ip_gma >= s->ring_start &&
 765                                         s->ip_gma <= s->ring_tail)
 766                                 len = (ring_top - s->ring_head) +
 767                                         (s->ip_gma - s->ring_start);
 768                 } else
 769                         len = (s->ip_gma - s->ring_head);
 770
 771                 s->ip_va = s->rb_va + len;
 772         } else {/* shadow batch buffer */
 773                 s->ip_va = s->ret_bb_va;
 774         }
 775 }
 776
 777 static inline int ip_gma_set(struct parser_exec_state *s,
 778                 unsigned long ip_gma)
 779 {
 780         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 781
 782         s->ip_gma = ip_gma;
 783         update_ip_va(s);
 784         return 0;
 785 }
 786
 787 static inline int ip_gma_advance(struct parser_exec_state *s,
 788                 unsigned int dw_len)
 789 {
 790         s->ip_gma += (dw_len << 2);
 791
 792         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 793                 if (s->ip_gma >= s->ring_start + s->ring_size)
 794                         s->ip_gma -= s->ring_size;
 795                 update_ip_va(s);
 796         } else {
 797                 s->ip_va += (dw_len << 2);
 798         }
 799
 800         return 0;
 801 }
 802
 803 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 804 {
 805         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 806                 return info->len;
 807         else
 808                 return (cmd & ((1U << info->len) - 1)) + 2;
 809         return 0;
 810 }
 811
 812 static inline int cmd_length(struct parser_exec_state *s)
 813 {
 814         return get_cmd_length(s->info, cmd_val(s, 0));
 815 }
 816
 817 /* do not remove this, some platform may need clflush here */
 818 #define patch_value(s, addr, val) do { \
 819         *addr = val; \
 820 } while (0)
 821
 822 static bool is_shadowed_mmio(unsigned int offset)
 823 {
 824         bool ret = false;
 825
 826         if ((offset == 0x2168) || /*BB current head register UDW */
 827             (offset == 0x2140) || /*BB current header register */
 828             (offset == 0x211c) || /*second BB header register UDW */
 829             (offset == 0x2114)) { /*second BB header register UDW */
 830                 ret = true;
 831         }
 832         return ret;
 833 }
 834
 835 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 836 {
 837         return (offset >= 0x24d0 && offset < 0x2500);
 838 }
 839
 840 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 841                 unsigned int offset, unsigned int index, char *cmd)
 842 {
 843         struct intel_gvt *gvt = s->vgpu->gvt;
 844         unsigned int data;
 845         u32 ring_base;
 846         u32 nopid;
 847
 848         if (!strcmp(cmd, "lri"))
 849                 data = cmd_val(s, index + 1);
 850         else {
 851                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
 852                         offset, cmd);
 853                 return -EINVAL;
 854         }
 855
 856         ring_base = s->engine->mmio_base;
 857         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 858
 859         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
 860                         data != nopid) {
 861                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 862                         offset, data);
 863                 patch_value(s, cmd_ptr(s, index), nopid);
 864                 return 0;
 865         }
 866         return 0;
 867 }
 868
 869 static inline bool is_mocs_mmio(unsigned int offset)
 870 {
 871         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 872                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 873 }
 874
 875 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 876                                 unsigned int offset, unsigned int index)
 877 {
 878         if (!is_mocs_mmio(offset))
 879                 return -EINVAL;
 880         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 881         return 0;
 882 }
 883
 884 static int cmd_reg_handler(struct parser_exec_state *s,
 885         unsigned int offset, unsigned int index, char *cmd)
 886 {
 887         struct intel_vgpu *vgpu = s->vgpu;
 888         struct intel_gvt *gvt = vgpu->gvt;
 889         u32 ctx_sr_ctl;
 890
 891         if (offset + 4 > gvt->device_info.mmio_size) {
 892                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 893                                 cmd, offset);
 894                 return -EFAULT;
 895         }
 896
 897         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 898                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 899                                 cmd, offset);
 900                 return -EBADRQC;
 901         }
 902
 903         if (is_shadowed_mmio(offset)) {
 904                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 905                 return 0;
 906         }
 907
 908         if (is_mocs_mmio(offset) &&
 909             mocs_cmd_reg_handler(s, offset, index))
 910                 return -EINVAL;
 911
 912         if (is_force_nonpriv_mmio(offset) &&
 913                 force_nonpriv_reg_handler(s, offset, index, cmd))
 914                 return -EPERM;
 915
 916         if (offset == i915_mmio_reg_offset(DERRMR) ||
 917                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 918                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 919                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 920         }
 921
 922         /* TODO
 923          * In order to let workload with inhibit context to generate
 924          * correct image data into memory, vregs values will be loaded to
 925          * hw via LRIs in the workload with inhibit context. But as
 926          * indirect context is loaded prior to LRIs in workload, we don't
 927          * want reg values specified in indirect context overwritten by
 928          * LRIs in workloads. So, when scanning an indirect context, we
 929          * update reg values in it into vregs, so LRIs in workload with
 930          * inhibit context will restore with correct values
 931          */
 932         if (IS_GEN(s->engine->i915, 9) &&
 933             intel_gvt_mmio_is_in_ctx(gvt, offset) &&
 934             !strncmp(cmd, "lri", 3)) {
 935                 intel_gvt_hypervisor_read_gpa(s->vgpu,
 936                         s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
 937                 /* check inhibit context */
 938                 if (ctx_sr_ctl & 1) {
 939                         u32 data = cmd_val(s, index + 1);
 940
 941                         if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
 942                                 intel_vgpu_mask_mmio_write(vgpu,
 943                                                         offset, &data, 4);
 944                         else
 945                                 vgpu_vreg(vgpu, offset) = data;
 946                 }
 947         }
 948
 949         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 950         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 951         return 0;
 952 }
 953
 954 #define cmd_reg(s, i) \
 955         (cmd_val(s, i) & GENMASK(22, 2))
 956
 957 #define cmd_reg_inhibit(s, i) \
 958         (cmd_val(s, i) & GENMASK(22, 18))
 959
 960 #define cmd_gma(s, i) \
 961         (cmd_val(s, i) & GENMASK(31, 2))
 962
 963 #define cmd_gma_hi(s, i) \
 964         (cmd_val(s, i) & GENMASK(15, 0))
 965
 966 static int cmd_handler_lri(struct parser_exec_state *s)
 967 {
 968         int i, ret = 0;
 969         int cmd_len = cmd_length(s);
 970         u32 valid_len = CMD_LEN(1);
 971
 972         /*
 973          * Official intel docs are somewhat sloppy , check the definition of
 974          * MI_LOAD_REGISTER_IMM.
 975          */
 976         #define MAX_VALID_LEN 127
 977         if ((cmd_len < valid_len) || (cmd_len > MAX_VALID_LEN)) {
 978                 gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 979                         cmd_len, valid_len);
 980                 return -EFAULT;
 981         }
 982
 983         for (i = 1; i < cmd_len; i += 2) {
 984                 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
 985                         if (s->engine->id == BCS0 &&
 986                             cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
 987                                 ret |= 0;
 988                         else
 989                                 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
 990                 }
 991                 if (ret)
 992                         break;
 993                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 994                 if (ret)
 995                         break;
 996         }
 997         return ret;
 998 }
 999
1000 static int cmd_handler_lrr(struct parser_exec_state *s)
1001 {
1002         int i, ret = 0;
1003         int cmd_len = cmd_length(s);
1004
1005         for (i = 1; i < cmd_len; i += 2) {
1006                 if (IS_BROADWELL(s->engine->i915))
1007                         ret |= ((cmd_reg_inhibit(s, i) ||
1008                                  (cmd_reg_inhibit(s, i + 1)))) ?
1009                                 -EBADRQC : 0;
1010                 if (ret)
1011                         break;
1012                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1013                 if (ret)
1014                         break;
1015                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1016                 if (ret)
1017                         break;
1018         }
1019         return ret;
1020 }
1021
1022 static inline int cmd_address_audit(struct parser_exec_state *s,
1023                 unsigned long guest_gma, int op_size, bool index_mode);
1024
1025 static int cmd_handler_lrm(struct parser_exec_state *s)
1026 {
1027         struct intel_gvt *gvt = s->vgpu->gvt;
1028         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1029         unsigned long gma;
1030         int i, ret = 0;
1031         int cmd_len = cmd_length(s);
1032
1033         for (i = 1; i < cmd_len;) {
1034                 if (IS_BROADWELL(s->engine->i915))
1035                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1036                 if (ret)
1037                         break;
1038                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1039                 if (ret)
1040                         break;
1041                 if (cmd_val(s, 0) & (1 << 22)) {
1042                         gma = cmd_gma(s, i + 1);
1043                         if (gmadr_bytes == 8)
1044                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1045                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1046                         if (ret)
1047                                 break;
1048                 }
1049                 i += gmadr_dw_number(s) + 1;
1050         }
1051         return ret;
1052 }
1053
1054 static int cmd_handler_srm(struct parser_exec_state *s)
1055 {
1056         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1057         unsigned long gma;
1058         int i, ret = 0;
1059         int cmd_len = cmd_length(s);
1060
1061         for (i = 1; i < cmd_len;) {
1062                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1063                 if (ret)
1064                         break;
1065                 if (cmd_val(s, 0) & (1 << 22)) {
1066                         gma = cmd_gma(s, i + 1);
1067                         if (gmadr_bytes == 8)
1068                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1069                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1070                         if (ret)
1071                                 break;
1072                 }
1073                 i += gmadr_dw_number(s) + 1;
1074         }
1075         return ret;
1076 }
1077
1078 struct cmd_interrupt_event {
1079         int pipe_control_notify;
1080         int mi_flush_dw;
1081         int mi_user_interrupt;
1082 };
1083
1084 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1085         [RCS0] = {
1086                 .pipe_control_notify = RCS_PIPE_CONTROL,
1087                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1088                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1089         },
1090         [BCS0] = {
1091                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1092                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1093                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1094         },
1095         [VCS0] = {
1096                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1097                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1098                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1099         },
1100         [VCS1] = {
1101                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1102                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1103                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1104         },
1105         [VECS0] = {
1106                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1107                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1108                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1109         },
1110 };
1111
1112 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1113 {
1114         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1115         unsigned long gma;
1116         bool index_mode = false;
1117         unsigned int post_sync;
1118         int ret = 0;
1119         u32 hws_pga, val;
1120
1121         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1122
1123         /* LRI post sync */
1124         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1125                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1126         /* post sync */
1127         else if (post_sync) {
1128                 if (post_sync == 2)
1129                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1130                 else if (post_sync == 3)
1131                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1132                 else if (post_sync == 1) {
1133                         /* check ggtt*/
1134                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1135                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1136                                 if (gmadr_bytes == 8)
1137                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1138                                 /* Store Data Index */
1139                                 if (cmd_val(s, 1) & (1 << 21))
1140                                         index_mode = true;
1141                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1142                                                 index_mode);
1143                                 if (ret)
1144                                         return ret;
1145                                 if (index_mode) {
1146                                         hws_pga = s->vgpu->hws_pga[s->engine->id];
1147                                         gma = hws_pga + gma;
1148                                         patch_value(s, cmd_ptr(s, 2), gma);
1149                                         val = cmd_val(s, 1) & (~(1 << 21));
1150                                         patch_value(s, cmd_ptr(s, 1), val);
1151                                 }
1152                         }
1153                 }
1154         }
1155
1156         if (ret)
1157                 return ret;
1158
1159         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1160                 set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1161                         s->workload->pending_events);
1162         return 0;
1163 }
1164
1165 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1166 {
1167         set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1168                 s->workload->pending_events);
1169         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1170         return 0;
1171 }
1172
1173 static int cmd_advance_default(struct parser_exec_state *s)
1174 {
1175         return ip_gma_advance(s, cmd_length(s));
1176 }
1177
1178 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1179 {
1180         int ret;
1181
1182         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1183                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1184                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1185                 s->buf_addr_type = s->saved_buf_addr_type;
1186         } else {
1187                 s->buf_type = RING_BUFFER_INSTRUCTION;
1188                 s->buf_addr_type = GTT_BUFFER;
1189                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1190                         s->ret_ip_gma_ring -= s->ring_size;
1191                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1192         }
1193         return ret;
1194 }
1195
1196 struct mi_display_flip_command_info {
1197         int pipe;
1198         int plane;
1199         int event;
1200         i915_reg_t stride_reg;
1201         i915_reg_t ctrl_reg;
1202         i915_reg_t surf_reg;
1203         u64 stride_val;
1204         u64 tile_val;
1205         u64 surf_val;
1206         bool async_flip;
1207 };
1208
1209 struct plane_code_mapping {
1210         int pipe;
1211         int plane;
1212         int event;
1213 };
1214
1215 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1216                 struct mi_display_flip_command_info *info)
1217 {
1218         struct drm_i915_private *dev_priv = s->engine->i915;
1219         struct plane_code_mapping gen8_plane_code[] = {
1220                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1221                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1222                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1223                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1224                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1225                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1226         };
1227         u32 dword0, dword1, dword2;
1228         u32 v;
1229
1230         dword0 = cmd_val(s, 0);
1231         dword1 = cmd_val(s, 1);
1232         dword2 = cmd_val(s, 2);
1233
1234         v = (dword0 & GENMASK(21, 19)) >> 19;
1235         if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1236                 return -EBADRQC;
1237
1238         info->pipe = gen8_plane_code[v].pipe;
1239         info->plane = gen8_plane_code[v].plane;
1240         info->event = gen8_plane_code[v].event;
1241         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1242         info->tile_val = (dword1 & 0x1);
1243         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1244         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1245
1246         if (info->plane == PLANE_A) {
1247                 info->ctrl_reg = DSPCNTR(info->pipe);
1248                 info->stride_reg = DSPSTRIDE(info->pipe);
1249                 info->surf_reg = DSPSURF(info->pipe);
1250         } else if (info->plane == PLANE_B) {
1251                 info->ctrl_reg = SPRCTL(info->pipe);
1252                 info->stride_reg = SPRSTRIDE(info->pipe);
1253                 info->surf_reg = SPRSURF(info->pipe);
1254         } else {
1255                 drm_WARN_ON(&dev_priv->drm, 1);
1256                 return -EBADRQC;
1257         }
1258         return 0;
1259 }
1260
1261 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1262                 struct mi_display_flip_command_info *info)
1263 {
1264         struct drm_i915_private *dev_priv = s->engine->i915;
1265         struct intel_vgpu *vgpu = s->vgpu;
1266         u32 dword0 = cmd_val(s, 0);
1267         u32 dword1 = cmd_val(s, 1);
1268         u32 dword2 = cmd_val(s, 2);
1269         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1270
1271         info->plane = PRIMARY_PLANE;
1272
1273         switch (plane) {
1274         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1275                 info->pipe = PIPE_A;
1276                 info->event = PRIMARY_A_FLIP_DONE;
1277                 break;
1278         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1279                 info->pipe = PIPE_B;
1280                 info->event = PRIMARY_B_FLIP_DONE;
1281                 break;
1282         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1283                 info->pipe = PIPE_C;
1284                 info->event = PRIMARY_C_FLIP_DONE;
1285                 break;
1286
1287         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1288                 info->pipe = PIPE_A;
1289                 info->event = SPRITE_A_FLIP_DONE;
1290                 info->plane = SPRITE_PLANE;
1291                 break;
1292         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1293                 info->pipe = PIPE_B;
1294                 info->event = SPRITE_B_FLIP_DONE;
1295                 info->plane = SPRITE_PLANE;
1296                 break;
1297         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1298                 info->pipe = PIPE_C;
1299                 info->event = SPRITE_C_FLIP_DONE;
1300                 info->plane = SPRITE_PLANE;
1301                 break;
1302
1303         default:
1304                 gvt_vgpu_err("unknown plane code %d\n", plane);
1305                 return -EBADRQC;
1306         }
1307
1308         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1309         info->tile_val = (dword1 & GENMASK(2, 0));
1310         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1311         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1312
1313         info->ctrl_reg = DSPCNTR(info->pipe);
1314         info->stride_reg = DSPSTRIDE(info->pipe);
1315         info->surf_reg = DSPSURF(info->pipe);
1316
1317         return 0;
1318 }
1319
1320 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1321                 struct mi_display_flip_command_info *info)
1322 {
1323         u32 stride, tile;
1324
1325         if (!info->async_flip)
1326                 return 0;
1327
1328         if (INTEL_GEN(s->engine->i915) >= 9) {
1329                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1330                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1331                                 GENMASK(12, 10)) >> 10;
1332         } else {
1333                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1334                                 GENMASK(15, 6)) >> 6;
1335                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1336         }
1337
1338         if (stride != info->stride_val)
1339                 gvt_dbg_cmd("cannot change stride during async flip\n");
1340
1341         if (tile != info->tile_val)
1342                 gvt_dbg_cmd("cannot change tile during async flip\n");
1343
1344         return 0;
1345 }
1346
1347 static int gen8_update_plane_mmio_from_mi_display_flip(
1348                 struct parser_exec_state *s,
1349                 struct mi_display_flip_command_info *info)
1350 {
1351         struct drm_i915_private *dev_priv = s->engine->i915;
1352         struct intel_vgpu *vgpu = s->vgpu;
1353
1354         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1355                       info->surf_val << 12);
1356         if (INTEL_GEN(dev_priv) >= 9) {
1357                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1358                               info->stride_val);
1359                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1360                               info->tile_val << 10);
1361         } else {
1362                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1363                               info->stride_val << 6);
1364                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1365                               info->tile_val << 10);
1366         }
1367
1368         if (info->plane == PLANE_PRIMARY)
1369                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1370
1371         if (info->async_flip)
1372                 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1373         else
1374                 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1375
1376         return 0;
1377 }
1378
1379 static int decode_mi_display_flip(struct parser_exec_state *s,
1380                 struct mi_display_flip_command_info *info)
1381 {
1382         if (IS_BROADWELL(s->engine->i915))
1383                 return gen8_decode_mi_display_flip(s, info);
1384         if (INTEL_GEN(s->engine->i915) >= 9)
1385                 return skl_decode_mi_display_flip(s, info);
1386
1387         return -ENODEV;
1388 }
1389
1390 static int check_mi_display_flip(struct parser_exec_state *s,
1391                 struct mi_display_flip_command_info *info)
1392 {
1393         return gen8_check_mi_display_flip(s, info);
1394 }
1395
1396 static int update_plane_mmio_from_mi_display_flip(
1397                 struct parser_exec_state *s,
1398                 struct mi_display_flip_command_info *info)
1399 {
1400         return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1401 }
1402
1403 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1404 {
1405         struct mi_display_flip_command_info info;
1406         struct intel_vgpu *vgpu = s->vgpu;
1407         int ret;
1408         int i;
1409         int len = cmd_length(s);
1410         u32 valid_len = CMD_LEN(1);
1411
1412         /* Flip Type == Stereo 3D Flip */
1413         if (DWORD_FIELD(2, 1, 0) == 2)
1414                 valid_len++;
1415         ret = gvt_check_valid_cmd_length(cmd_length(s),
1416                         valid_len);
1417         if (ret)
1418                 return ret;
1419
1420         ret = decode_mi_display_flip(s, &info);
1421         if (ret) {
1422                 gvt_vgpu_err("fail to decode MI display flip command\n");
1423                 return ret;
1424         }
1425
1426         ret = check_mi_display_flip(s, &info);
1427         if (ret) {
1428                 gvt_vgpu_err("invalid MI display flip command\n");
1429                 return ret;
1430         }
1431
1432         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1433         if (ret) {
1434                 gvt_vgpu_err("fail to update plane mmio\n");
1435                 return ret;
1436         }
1437
1438         for (i = 0; i < len; i++)
1439                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1440         return 0;
1441 }
1442
1443 static bool is_wait_for_flip_pending(u32 cmd)
1444 {
1445         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1446                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1447                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1448                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1449                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1450                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1451 }
1452
1453 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1454 {
1455         u32 cmd = cmd_val(s, 0);
1456
1457         if (!is_wait_for_flip_pending(cmd))
1458                 return 0;
1459
1460         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1461         return 0;
1462 }
1463
1464 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1465 {
1466         unsigned long addr;
1467         unsigned long gma_high, gma_low;
1468         struct intel_vgpu *vgpu = s->vgpu;
1469         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1470
1471         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1472                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1473                 return INTEL_GVT_INVALID_ADDR;
1474         }
1475
1476         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1477         if (gmadr_bytes == 4) {
1478                 addr = gma_low;
1479         } else {
1480                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1481                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1482         }
1483         return addr;
1484 }
1485
1486 static inline int cmd_address_audit(struct parser_exec_state *s,
1487                 unsigned long guest_gma, int op_size, bool index_mode)
1488 {
1489         struct intel_vgpu *vgpu = s->vgpu;
1490         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1491         int i;
1492         int ret;
1493
1494         if (op_size > max_surface_size) {
1495                 gvt_vgpu_err("command address audit fail name %s\n",
1496                         s->info->name);
1497                 return -EFAULT;
1498         }
1499
1500         if (index_mode) {
1501                 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1502                         ret = -EFAULT;
1503                         goto err;
1504                 }
1505         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1506                 ret = -EFAULT;
1507                 goto err;
1508         }
1509
1510         return 0;
1511
1512 err:
1513         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1514                         s->info->name, guest_gma, op_size);
1515
1516         pr_err("cmd dump: ");
1517         for (i = 0; i < cmd_length(s); i++) {
1518                 if (!(i % 4))
1519                         pr_err("\n%08x ", cmd_val(s, i));
1520                 else
1521                         pr_err("%08x ", cmd_val(s, i));
1522         }
1523         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1524                         vgpu->id,
1525                         vgpu_aperture_gmadr_base(vgpu),
1526                         vgpu_aperture_gmadr_end(vgpu),
1527                         vgpu_hidden_gmadr_base(vgpu),
1528                         vgpu_hidden_gmadr_end(vgpu));
1529         return ret;
1530 }
1531
1532 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1533 {
1534         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1535         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1536         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1537         unsigned long gma, gma_low, gma_high;
1538         u32 valid_len = CMD_LEN(2);
1539         int ret = 0;
1540
1541         /* check ppggt */
1542         if (!(cmd_val(s, 0) & (1 << 22)))
1543                 return 0;
1544
1545         /* check if QWORD */
1546         if (DWORD_FIELD(0, 21, 21))
1547                 valid_len++;
1548         ret = gvt_check_valid_cmd_length(cmd_length(s),
1549                         valid_len);
1550         if (ret)
1551                 return ret;
1552
1553         gma = cmd_val(s, 2) & GENMASK(31, 2);
1554
1555         if (gmadr_bytes == 8) {
1556                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1557                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1558                 gma = (gma_high << 32) | gma_low;
1559                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1560         }
1561         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1562         return ret;
1563 }
1564
1565 static inline int unexpected_cmd(struct parser_exec_state *s)
1566 {
1567         struct intel_vgpu *vgpu = s->vgpu;
1568
1569         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1570
1571         return -EBADRQC;
1572 }
1573
1574 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1575 {
1576         return unexpected_cmd(s);
1577 }
1578
1579 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1580 {
1581         return unexpected_cmd(s);
1582 }
1583
1584 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1585 {
1586         return unexpected_cmd(s);
1587 }
1588
1589 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1590 {
1591         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1592         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1593                         sizeof(u32);
1594         unsigned long gma, gma_high;
1595         u32 valid_len = CMD_LEN(1);
1596         int ret = 0;
1597
1598         if (!(cmd_val(s, 0) & (1 << 22)))
1599                 return ret;
1600
1601         /* check inline data */
1602         if (cmd_val(s, 0) & BIT(18))
1603                 valid_len = CMD_LEN(9);
1604         ret = gvt_check_valid_cmd_length(cmd_length(s),
1605                         valid_len);
1606         if (ret)
1607                 return ret;
1608
1609         gma = cmd_val(s, 1) & GENMASK(31, 2);
1610         if (gmadr_bytes == 8) {
1611                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1612                 gma = (gma_high << 32) | gma;
1613         }
1614         ret = cmd_address_audit(s, gma, op_size, false);
1615         return ret;
1616 }
1617
1618 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1619 {
1620         return unexpected_cmd(s);
1621 }
1622
1623 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1624 {
1625         return unexpected_cmd(s);
1626 }
1627
1628 static int cmd_handler_mi_conditional_batch_buffer_end(
1629                 struct parser_exec_state *s)
1630 {
1631         return unexpected_cmd(s);
1632 }
1633
1634 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1635 {
1636         return unexpected_cmd(s);
1637 }
1638
1639 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1640 {
1641         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1642         unsigned long gma;
1643         bool index_mode = false;
1644         int ret = 0;
1645         u32 hws_pga, val;
1646         u32 valid_len = CMD_LEN(2);
1647
1648         ret = gvt_check_valid_cmd_length(cmd_length(s),
1649                         valid_len);
1650         if (ret) {
1651                 /* Check again for Qword */
1652                 ret = gvt_check_valid_cmd_length(cmd_length(s),
1653                         ++valid_len);
1654                 return ret;
1655         }
1656
1657         /* Check post-sync and ppgtt bit */
1658         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1659                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1660                 if (gmadr_bytes == 8)
1661                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1662                 /* Store Data Index */
1663                 if (cmd_val(s, 0) & (1 << 21))
1664                         index_mode = true;
1665                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1666                 if (ret)
1667                         return ret;
1668                 if (index_mode) {
1669                         hws_pga = s->vgpu->hws_pga[s->engine->id];
1670                         gma = hws_pga + gma;
1671                         patch_value(s, cmd_ptr(s, 1), gma);
1672                         val = cmd_val(s, 0) & (~(1 << 21));
1673                         patch_value(s, cmd_ptr(s, 0), val);
1674                 }
1675         }
1676         /* Check notify bit */
1677         if ((cmd_val(s, 0) & (1 << 8)))
1678                 set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1679                         s->workload->pending_events);
1680         return ret;
1681 }
1682
1683 static void addr_type_update_snb(struct parser_exec_state *s)
1684 {
1685         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1686                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1687                 s->buf_addr_type = PPGTT_BUFFER;
1688         }
1689 }
1690
1691
1692 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1693                 unsigned long gma, unsigned long end_gma, void *va)
1694 {
1695         unsigned long copy_len, offset;
1696         unsigned long len = 0;
1697         unsigned long gpa;
1698
1699         while (gma != end_gma) {
1700                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1701                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1702                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1703                         return -EFAULT;
1704                 }
1705
1706                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1707
1708                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1709                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1710
1711                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1712
1713                 len += copy_len;
1714                 gma += copy_len;
1715         }
1716         return len;
1717 }
1718
1719
1720 /*
1721  * Check whether a batch buffer needs to be scanned. Currently
1722  * the only criteria is based on privilege.
1723  */
1724 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1725 {
1726         /* Decide privilege based on address space */
1727         if (cmd_val(s, 0) & BIT(8) &&
1728             !(s->vgpu->scan_nonprivbb & s->engine->mask))
1729                 return 0;
1730
1731         return 1;
1732 }
1733
1734 static const char *repr_addr_type(unsigned int type)
1735 {
1736         return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1737 }
1738
1739 static int find_bb_size(struct parser_exec_state *s,
1740                         unsigned long *bb_size,
1741                         unsigned long *bb_end_cmd_offset)
1742 {
1743         unsigned long gma = 0;
1744         const struct cmd_info *info;
1745         u32 cmd_len = 0;
1746         bool bb_end = false;
1747         struct intel_vgpu *vgpu = s->vgpu;
1748         u32 cmd;
1749         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1750                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1751
1752         *bb_size = 0;
1753         *bb_end_cmd_offset = 0;
1754
1755         /* get the start gm address of the batch buffer */
1756         gma = get_gma_bb_from_cmd(s, 1);
1757         if (gma == INTEL_GVT_INVALID_ADDR)
1758                 return -EFAULT;
1759
1760         cmd = cmd_val(s, 0);
1761         info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1762         if (info == NULL) {
1763                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1764                              cmd, get_opcode(cmd, s->engine),
1765                              repr_addr_type(s->buf_addr_type),
1766                              s->engine->name, s->workload);
1767                 return -EBADRQC;
1768         }
1769         do {
1770                 if (copy_gma_to_hva(s->vgpu, mm,
1771                                     gma, gma + 4, &cmd) < 0)
1772                         return -EFAULT;
1773                 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1774                 if (info == NULL) {
1775                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1776                                      cmd, get_opcode(cmd, s->engine),
1777                                      repr_addr_type(s->buf_addr_type),
1778                                      s->engine->name, s->workload);
1779                         return -EBADRQC;
1780                 }
1781
1782                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1783                         bb_end = true;
1784                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1785                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1786                                 /* chained batch buffer */
1787                                 bb_end = true;
1788                 }
1789
1790                 if (bb_end)
1791                         *bb_end_cmd_offset = *bb_size;
1792
1793                 cmd_len = get_cmd_length(info, cmd) << 2;
1794                 *bb_size += cmd_len;
1795                 gma += cmd_len;
1796         } while (!bb_end);
1797
1798         return 0;
1799 }
1800
1801 static int audit_bb_end(struct parser_exec_state *s, void *va)
1802 {
1803         struct intel_vgpu *vgpu = s->vgpu;
1804         u32 cmd = *(u32 *)va;
1805         const struct cmd_info *info;
1806
1807         info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1808         if (info == NULL) {
1809                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1810                              cmd, get_opcode(cmd, s->engine),
1811                              repr_addr_type(s->buf_addr_type),
1812                              s->engine->name, s->workload);
1813                 return -EBADRQC;
1814         }
1815
1816         if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1817             ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1818              (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1819                 return 0;
1820
1821         return -EBADRQC;
1822 }
1823
1824 static int perform_bb_shadow(struct parser_exec_state *s)
1825 {
1826         struct intel_vgpu *vgpu = s->vgpu;
1827         struct intel_vgpu_shadow_bb *bb;
1828         unsigned long gma = 0;
1829         unsigned long bb_size;
1830         unsigned long bb_end_cmd_offset;
1831         int ret = 0;
1832         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1833                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1834         unsigned long start_offset = 0;
1835
1836         /* get the start gm address of the batch buffer */
1837         gma = get_gma_bb_from_cmd(s, 1);
1838         if (gma == INTEL_GVT_INVALID_ADDR)
1839                 return -EFAULT;
1840
1841         ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1842         if (ret)
1843                 return ret;
1844
1845         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1846         if (!bb)
1847                 return -ENOMEM;
1848
1849         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1850
1851         /* the start_offset stores the batch buffer's start gma's
1852          * offset relative to page boundary. so for non-privileged batch
1853          * buffer, the shadowed gem object holds exactly the same page
1854          * layout as original gem object. This is for the convience of
1855          * replacing the whole non-privilged batch buffer page to this
1856          * shadowed one in PPGTT at the same gma address. (this replacing
1857          * action is not implemented yet now, but may be necessary in
1858          * future).
1859          * for prileged batch buffer, we just change start gma address to
1860          * that of shadowed page.
1861          */
1862         if (bb->ppgtt)
1863                 start_offset = gma & ~I915_GTT_PAGE_MASK;
1864
1865         bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1866                                                round_up(bb_size + start_offset,
1867                                                         PAGE_SIZE));
1868         if (IS_ERR(bb->obj)) {
1869                 ret = PTR_ERR(bb->obj);
1870                 goto err_free_bb;
1871         }
1872
1873         ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush);
1874         if (ret)
1875                 goto err_free_obj;
1876
1877         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1878         if (IS_ERR(bb->va)) {
1879                 ret = PTR_ERR(bb->va);
1880                 goto err_finish_shmem_access;
1881         }
1882
1883         if (bb->clflush & CLFLUSH_BEFORE) {
1884                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1885                 bb->clflush &= ~CLFLUSH_BEFORE;
1886         }
1887
1888         ret = copy_gma_to_hva(s->vgpu, mm,
1889                               gma, gma + bb_size,
1890                               bb->va + start_offset);
1891         if (ret < 0) {
1892                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1893                 ret = -EFAULT;
1894                 goto err_unmap;
1895         }
1896
1897         ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1898         if (ret)
1899                 goto err_unmap;
1900
1901         INIT_LIST_HEAD(&bb->list);
1902         list_add(&bb->list, &s->workload->shadow_bb);
1903
1904         bb->accessing = true;
1905         bb->bb_start_cmd_va = s->ip_va;
1906
1907         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1908                 bb->bb_offset = s->ip_va - s->rb_va;
1909         else
1910                 bb->bb_offset = 0;
1911
1912         /*
1913          * ip_va saves the virtual address of the shadow batch buffer, while
1914          * ip_gma saves the graphics address of the original batch buffer.
1915          * As the shadow batch buffer is just a copy from the originial one,
1916          * it should be right to use shadow batch buffer'va and original batch
1917          * buffer's gma in pair. After all, we don't want to pin the shadow
1918          * buffer here (too early).
1919          */
1920         s->ip_va = bb->va + start_offset;
1921         s->ip_gma = gma;
1922         return 0;
1923 err_unmap:
1924         i915_gem_object_unpin_map(bb->obj);
1925 err_finish_shmem_access:
1926         i915_gem_object_finish_access(bb->obj);
1927 err_free_obj:
1928         i915_gem_object_put(bb->obj);
1929 err_free_bb:
1930         kfree(bb);
1931         return ret;
1932 }
1933
1934 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1935 {
1936         bool second_level;
1937         int ret = 0;
1938         struct intel_vgpu *vgpu = s->vgpu;
1939
1940         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1941                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1942                 return -EFAULT;
1943         }
1944
1945         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1946         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1947                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1948                 return -EFAULT;
1949         }
1950
1951         s->saved_buf_addr_type = s->buf_addr_type;
1952         addr_type_update_snb(s);
1953         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1954                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1955                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1956         } else if (second_level) {
1957                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1958                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1959                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1960         }
1961
1962         if (batch_buffer_needs_scan(s)) {
1963                 ret = perform_bb_shadow(s);
1964                 if (ret < 0)
1965                         gvt_vgpu_err("invalid shadow batch buffer\n");
1966         } else {
1967                 /* emulate a batch buffer end to do return right */
1968                 ret = cmd_handler_mi_batch_buffer_end(s);
1969                 if (ret < 0)
1970                         return ret;
1971         }
1972         return ret;
1973 }
1974
1975 static int mi_noop_index;
1976
1977 static const struct cmd_info cmd_info[] = {
1978         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1979
1980         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1981                 0, 1, NULL},
1982
1983         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1984                 0, 1, cmd_handler_mi_user_interrupt},
1985
1986         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1987                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1988
1989         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1990
1991         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1992                 NULL},
1993
1994         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1995                 NULL},
1996
1997         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1998                 NULL},
1999
2000         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2001                 NULL},
2002
2003         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2004                 D_ALL, 0, 1, NULL},
2005
2006         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2007                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2008                 cmd_handler_mi_batch_buffer_end},
2009
2010         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2011                 0, 1, NULL},
2012
2013         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2014                 NULL},
2015
2016         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2017                 D_ALL, 0, 1, NULL},
2018
2019         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2020                 NULL},
2021
2022         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2023                 NULL},
2024
2025         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2026                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2027
2028         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2029                 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2030
2031         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2032
2033         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2034                 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2035
2036         {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2037                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2038                 NULL, CMD_LEN(0)},
2039
2040         {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2041                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2042                 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2043
2044         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2045                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2046
2047         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2048                 0, 8, cmd_handler_mi_store_data_index},
2049
2050         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2051                 D_ALL, 0, 8, cmd_handler_lri},
2052
2053         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2054                 cmd_handler_mi_update_gtt},
2055
2056         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2057                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2058                 cmd_handler_srm, CMD_LEN(2)},
2059
2060         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2061                 cmd_handler_mi_flush_dw},
2062
2063         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2064                 10, cmd_handler_mi_clflush},
2065
2066         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2067                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2068                 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2069
2070         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2071                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2072                 cmd_handler_lrm, CMD_LEN(2)},
2073
2074         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2075                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2076                 cmd_handler_lrr, CMD_LEN(1)},
2077
2078         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2079                 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2080                 8, NULL, CMD_LEN(2)},
2081
2082         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2083                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2084
2085         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2086                 ADDR_FIX_1(2), 8, NULL},
2087
2088         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2089                 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2090
2091         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2092                 8, cmd_handler_mi_op_2f},
2093
2094         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2095                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2096                 cmd_handler_mi_batch_buffer_start},
2097
2098         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2099                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2100                 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2101
2102         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2103                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2104
2105         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2106                 ADDR_FIX_2(4, 7), 8, NULL},
2107
2108         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2109                 0, 8, NULL},
2110
2111         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2112                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2113
2114         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2115
2116         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2117                 0, 8, NULL},
2118
2119         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2120                 ADDR_FIX_1(3), 8, NULL},
2121
2122         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2123                 D_ALL, 0, 8, NULL},
2124
2125         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2126                 ADDR_FIX_1(4), 8, NULL},
2127
2128         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2129                 ADDR_FIX_2(4, 5), 8, NULL},
2130
2131         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2132                 ADDR_FIX_1(4), 8, NULL},
2133
2134         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2135                 ADDR_FIX_2(4, 7), 8, NULL},
2136
2137         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2138                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2139
2140         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2141
2142         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2143                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2144
2145         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2146                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2147
2148         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2149                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2150                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2151
2152         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2153                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2154
2155         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2156                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2157
2158         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2159                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2160
2161         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2162                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2163
2164         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2165                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2166
2167         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2168                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2169                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2170
2171         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2172                 ADDR_FIX_2(4, 5), 8, NULL},
2173
2174         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2175                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2176
2177         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2178                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2179                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2180
2181         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2182                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2183                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2184
2185         {"3DSTATE_BLEND_STATE_POINTERS",
2186                 OP_3DSTATE_BLEND_STATE_POINTERS,
2187                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2188
2189         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2190                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2191                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2192
2193         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2194                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2195                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2196
2197         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2198                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2199                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2200
2201         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2202                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2203                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2204
2205         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2206                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2207                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2208
2209         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2210                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2211                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2212
2213         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2214                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2215                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2216
2217         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2218                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2219                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2220
2221         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2222                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2223                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2224
2225         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2226                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2227                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2228
2229         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2230                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2231                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2232
2233         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2234                 0, 8, NULL},
2235
2236         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2237                 0, 8, NULL},
2238
2239         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2240                 0, 8, NULL},
2241
2242         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2243                 0, 8, NULL},
2244
2245         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2246                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2249                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2250
2251         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2252                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2253
2254         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2255                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2256
2257         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2258                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2259
2260         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2261                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2262
2263         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2264                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2265
2266         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2267                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2268
2269         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2270                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2271
2272         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2273                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2274
2275         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2276                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2279                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2280
2281         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2282                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2283
2284         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2285                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2286
2287         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2288                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2289
2290         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2291                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2292
2293         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2294                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2295
2296         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2297                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2298
2299         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2300                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2301
2302         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2303                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2304
2305         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2306                 D_BDW_PLUS, 0, 8, NULL},
2307
2308         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2309                 NULL},
2310
2311         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2312                 D_BDW_PLUS, 0, 8, NULL},
2313
2314         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2315                 D_BDW_PLUS, 0, 8, NULL},
2316
2317         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2318                 8, NULL},
2319
2320         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2321                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2322
2323         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2324                 8, NULL},
2325
2326         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2327                 NULL},
2328
2329         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2330                 NULL},
2331
2332         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2333                 NULL},
2334
2335         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2336                 D_BDW_PLUS, 0, 8, NULL},
2337
2338         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2339                 R_RCS, D_ALL, 0, 8, NULL},
2340
2341         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2342                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2343
2344         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2345                 R_RCS, D_ALL, 0, 1, NULL},
2346
2347         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2348
2349         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2350                 R_RCS, D_ALL, 0, 8, NULL},
2351
2352         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2353                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2354
2355         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2356
2357         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2358
2359         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2360
2361         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2362                 D_BDW_PLUS, 0, 8, NULL},
2363
2364         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2365                 D_BDW_PLUS, 0, 8, NULL},
2366
2367         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2368                 D_ALL, 0, 8, NULL},
2369
2370         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2371                 D_BDW_PLUS, 0, 8, NULL},
2372
2373         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2374                 D_BDW_PLUS, 0, 8, NULL},
2375
2376         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2377
2378         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2379
2380         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2381
2382         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2383                 D_ALL, 0, 8, NULL},
2384
2385         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2386
2387         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2388
2389         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2390                 R_RCS, D_ALL, 0, 8, NULL},
2391
2392         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2393                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2394
2395         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2396                 0, 8, NULL},
2397
2398         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2399                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2400
2401         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2402                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2403
2404         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2405                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2406
2407         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2408                 D_ALL, 0, 8, NULL},
2409
2410         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2411                 D_ALL, 0, 8, NULL},
2412
2413         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2414                 D_ALL, 0, 8, NULL},
2415
2416         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2417                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2418
2419         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2420                 D_BDW_PLUS, 0, 8, NULL},
2421
2422         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2423                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2424
2425         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2426                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2427
2428         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2429                 R_RCS, D_ALL, 0, 8, NULL},
2430
2431         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2432                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2433
2434         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2435                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2436
2437         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2438                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2439
2440         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2441                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2442
2443         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2444                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2445
2446         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2447                 R_RCS, D_ALL, 0, 8, NULL},
2448
2449         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2450                 D_ALL, 0, 9, NULL},
2451
2452         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2453                 ADDR_FIX_2(2, 4), 8, NULL},
2454
2455         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2456                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2457                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2458
2459         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2460                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2461
2462         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2463                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2464                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2465
2466         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2467                 D_BDW_PLUS, 0, 8, NULL},
2468
2469         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2470                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2471
2472         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2473
2474         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2475                 1, NULL},
2476
2477         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2478                 ADDR_FIX_1(1), 8, NULL},
2479
2480         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2481
2482         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2483                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2484
2485         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2486                 ADDR_FIX_1(1), 8, NULL},
2487
2488         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2489
2490         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2491
2492         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2493                 0, 8, NULL},
2494
2495         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2496                 D_SKL_PLUS, 0, 8, NULL},
2497
2498         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2499                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2500
2501         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2502                 0, 16, NULL},
2503
2504         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2505                 0, 16, NULL},
2506
2507         {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2508                 0, 16, NULL},
2509
2510         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2511
2512         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2513                 0, 16, NULL},
2514
2515         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2516                 0, 16, NULL},
2517
2518         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2519                 0, 16, NULL},
2520
2521         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2522                 0, 8, NULL},
2523
2524         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2525                 NULL},
2526
2527         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2528                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2529
2530         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2531                 R_VCS, D_ALL, 0, 12, NULL},
2532
2533         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2534                 R_VCS, D_ALL, 0, 12, NULL},
2535
2536         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2537                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2538
2539         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2540                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2541
2542         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2543                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2544
2545         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2546
2547         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2548                 R_VCS, D_ALL, 0, 12, NULL},
2549
2550         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2551                 R_VCS, D_ALL, 0, 12, NULL},
2552
2553         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2554                 R_VCS, D_ALL, 0, 12, NULL},
2555
2556         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2557                 R_VCS, D_ALL, 0, 12, NULL},
2558
2559         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2560                 R_VCS, D_ALL, 0, 12, NULL},
2561
2562         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2563                 R_VCS, D_ALL, 0, 12, NULL},
2564
2565         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2566                 R_VCS, D_ALL, 0, 6, NULL},
2567
2568         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2569                 R_VCS, D_ALL, 0, 12, NULL},
2570
2571         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2572                 R_VCS, D_ALL, 0, 12, NULL},
2573
2574         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2575                 R_VCS, D_ALL, 0, 12, NULL},
2576
2577         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2578                 R_VCS, D_ALL, 0, 12, NULL},
2579
2580         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2581                 R_VCS, D_ALL, 0, 12, NULL},
2582
2583         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2584                 R_VCS, D_ALL, 0, 12, NULL},
2585
2586         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2587                 R_VCS, D_ALL, 0, 12, NULL},
2588         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2589                 R_VCS, D_ALL, 0, 12, NULL},
2590
2591         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2592                 R_VCS, D_ALL, 0, 12, NULL},
2593
2594         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2595                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2596
2597         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2598                 R_VCS, D_ALL, 0, 12, NULL},
2599
2600         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2601                 R_VCS, D_ALL, 0, 12, NULL},
2602
2603         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2604                 R_VCS, D_ALL, 0, 12, NULL},
2605
2606         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2607                 R_VCS, D_ALL, 0, 12, NULL},
2608
2609         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2610                 R_VCS, D_ALL, 0, 12, NULL},
2611
2612         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2613                 R_VCS, D_ALL, 0, 12, NULL},
2614
2615         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2616                 R_VCS, D_ALL, 0, 12, NULL},
2617
2618         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2619                 R_VCS, D_ALL, 0, 12, NULL},
2620
2621         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2622                 R_VCS, D_ALL, 0, 12, NULL},
2623
2624         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2625                 R_VCS, D_ALL, 0, 12, NULL},
2626
2627         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2628                 R_VCS, D_ALL, 0, 12, NULL},
2629
2630         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2631                 0, 16, NULL},
2632
2633         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2634
2635         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2636
2637         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2638                 R_VCS, D_ALL, 0, 12, NULL},
2639
2640         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2641                 R_VCS, D_ALL, 0, 12, NULL},
2642
2643         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2644                 R_VCS, D_ALL, 0, 12, NULL},
2645
2646         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2647
2648         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2649                 0, 12, NULL},
2650
2651         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2652                 0, 12, NULL},
2653 };
2654
2655 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2656 {
2657         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2658 }
2659
2660 /* call the cmd handler, and advance ip */
2661 static int cmd_parser_exec(struct parser_exec_state *s)
2662 {
2663         struct intel_vgpu *vgpu = s->vgpu;
2664         const struct cmd_info *info;
2665         u32 cmd;
2666         int ret = 0;
2667
2668         cmd = cmd_val(s, 0);
2669
2670         /* fastpath for MI_NOOP */
2671         if (cmd == MI_NOOP)
2672                 info = &cmd_info[mi_noop_index];
2673         else
2674                 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2675
2676         if (info == NULL) {
2677                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2678                              cmd, get_opcode(cmd, s->engine),
2679                              repr_addr_type(s->buf_addr_type),
2680                              s->engine->name, s->workload);
2681                 return -EBADRQC;
2682         }
2683
2684         s->info = info;
2685
2686         trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2687                           cmd_length(s), s->buf_type, s->buf_addr_type,
2688                           s->workload, info->name);
2689
2690         if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2691                 ret = gvt_check_valid_cmd_length(cmd_length(s),
2692                                                  info->valid_len);
2693                 if (ret)
2694                         return ret;
2695         }
2696
2697         if (info->handler) {
2698                 ret = info->handler(s);
2699                 if (ret < 0) {
2700                         gvt_vgpu_err("%s handler error\n", info->name);
2701                         return ret;
2702                 }
2703         }
2704
2705         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2706                 ret = cmd_advance_default(s);
2707                 if (ret) {
2708                         gvt_vgpu_err("%s IP advance error\n", info->name);
2709                         return ret;
2710                 }
2711         }
2712         return 0;
2713 }
2714
2715 static inline bool gma_out_of_range(unsigned long gma,
2716                 unsigned long gma_head, unsigned int gma_tail)
2717 {
2718         if (gma_tail >= gma_head)
2719                 return (gma < gma_head) || (gma > gma_tail);
2720         else
2721                 return (gma > gma_tail) && (gma < gma_head);
2722 }
2723
2724 /* Keep the consistent return type, e.g EBADRQC for unknown
2725  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2726  * works as the input of VM healthy status.
2727  */
2728 static int command_scan(struct parser_exec_state *s,
2729                 unsigned long rb_head, unsigned long rb_tail,
2730                 unsigned long rb_start, unsigned long rb_len)
2731 {
2732
2733         unsigned long gma_head, gma_tail, gma_bottom;
2734         int ret = 0;
2735         struct intel_vgpu *vgpu = s->vgpu;
2736
2737         gma_head = rb_start + rb_head;
2738         gma_tail = rb_start + rb_tail;
2739         gma_bottom = rb_start +  rb_len;
2740
2741         while (s->ip_gma != gma_tail) {
2742                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2743                         if (!(s->ip_gma >= rb_start) ||
2744                                 !(s->ip_gma < gma_bottom)) {
2745                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2746                                         "(base:0x%lx, bottom: 0x%lx)\n",
2747                                         s->ip_gma, rb_start,
2748                                         gma_bottom);
2749                                 parser_exec_state_dump(s);
2750                                 return -EFAULT;
2751                         }
2752                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2753                                 gvt_vgpu_err("ip_gma %lx out of range."
2754                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2755                                         s->ip_gma, rb_start,
2756                                         rb_head, rb_tail);
2757                                 parser_exec_state_dump(s);
2758                                 break;
2759                         }
2760                 }
2761                 ret = cmd_parser_exec(s);
2762                 if (ret) {
2763                         gvt_vgpu_err("cmd parser error\n");
2764                         parser_exec_state_dump(s);
2765                         break;
2766                 }
2767         }
2768
2769         return ret;
2770 }
2771
2772 static int scan_workload(struct intel_vgpu_workload *workload)
2773 {
2774         unsigned long gma_head, gma_tail, gma_bottom;
2775         struct parser_exec_state s;
2776         int ret = 0;
2777
2778         /* ring base is page aligned */
2779         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2780                 return -EINVAL;
2781
2782         gma_head = workload->rb_start + workload->rb_head;
2783         gma_tail = workload->rb_start + workload->rb_tail;
2784         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2785
2786         s.buf_type = RING_BUFFER_INSTRUCTION;
2787         s.buf_addr_type = GTT_BUFFER;
2788         s.vgpu = workload->vgpu;
2789         s.engine = workload->engine;
2790         s.ring_start = workload->rb_start;
2791         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2792         s.ring_head = gma_head;
2793         s.ring_tail = gma_tail;
2794         s.rb_va = workload->shadow_ring_buffer_va;
2795         s.workload = workload;
2796         s.is_ctx_wa = false;
2797
2798         if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2799                 return 0;
2800
2801         ret = ip_gma_set(&s, gma_head);
2802         if (ret)
2803                 goto out;
2804
2805         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2806                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2807
2808 out:
2809         return ret;
2810 }
2811
2812 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2813 {
2814
2815         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2816         struct parser_exec_state s;
2817         int ret = 0;
2818         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2819                                 struct intel_vgpu_workload,
2820                                 wa_ctx);
2821
2822         /* ring base is page aligned */
2823         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2824                                         I915_GTT_PAGE_SIZE)))
2825                 return -EINVAL;
2826
2827         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2828         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2829                         PAGE_SIZE);
2830         gma_head = wa_ctx->indirect_ctx.guest_gma;
2831         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2832         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2833
2834         s.buf_type = RING_BUFFER_INSTRUCTION;
2835         s.buf_addr_type = GTT_BUFFER;
2836         s.vgpu = workload->vgpu;
2837         s.engine = workload->engine;
2838         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2839         s.ring_size = ring_size;
2840         s.ring_head = gma_head;
2841         s.ring_tail = gma_tail;
2842         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2843         s.workload = workload;
2844         s.is_ctx_wa = true;
2845
2846         ret = ip_gma_set(&s, gma_head);
2847         if (ret)
2848                 goto out;
2849
2850         ret = command_scan(&s, 0, ring_tail,
2851                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2852 out:
2853         return ret;
2854 }
2855
2856 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2857 {
2858         struct intel_vgpu *vgpu = workload->vgpu;
2859         struct intel_vgpu_submission *s = &vgpu->submission;
2860         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2861         void *shadow_ring_buffer_va;
2862         int ret;
2863
2864         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2865
2866         /* calculate workload ring buffer size */
2867         workload->rb_len = (workload->rb_tail + guest_rb_size -
2868                         workload->rb_head) % guest_rb_size;
2869
2870         gma_head = workload->rb_start + workload->rb_head;
2871         gma_tail = workload->rb_start + workload->rb_tail;
2872         gma_top = workload->rb_start + guest_rb_size;
2873
2874         if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2875                 void *p;
2876
2877                 /* realloc the new ring buffer if needed */
2878                 p = krealloc(s->ring_scan_buffer[workload->engine->id],
2879                              workload->rb_len, GFP_KERNEL);
2880                 if (!p) {
2881                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2882                         return -ENOMEM;
2883                 }
2884                 s->ring_scan_buffer[workload->engine->id] = p;
2885                 s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2886         }
2887
2888         shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2889
2890         /* get shadow ring buffer va */
2891         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2892
2893         /* head > tail --> copy head <-> top */
2894         if (gma_head > gma_tail) {
2895                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2896                                       gma_head, gma_top, shadow_ring_buffer_va);
2897                 if (ret < 0) {
2898                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2899                         return ret;
2900                 }
2901                 shadow_ring_buffer_va += ret;
2902                 gma_head = workload->rb_start;
2903         }
2904
2905         /* copy head or start <-> tail */
2906         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2907                                 shadow_ring_buffer_va);
2908         if (ret < 0) {
2909                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2910                 return ret;
2911         }
2912         return 0;
2913 }
2914
2915 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2916 {
2917         int ret;
2918         struct intel_vgpu *vgpu = workload->vgpu;
2919
2920         ret = shadow_workload_ring_buffer(workload);
2921         if (ret) {
2922                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2923                 return ret;
2924         }
2925
2926         ret = scan_workload(workload);
2927         if (ret) {
2928                 gvt_vgpu_err("scan workload error\n");
2929                 return ret;
2930         }
2931         return 0;
2932 }
2933
2934 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2935 {
2936         int ctx_size = wa_ctx->indirect_ctx.size;
2937         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2938         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2939                                         struct intel_vgpu_workload,
2940                                         wa_ctx);
2941         struct intel_vgpu *vgpu = workload->vgpu;
2942         struct drm_i915_gem_object *obj;
2943         int ret = 0;
2944         void *map;
2945
2946         obj = i915_gem_object_create_shmem(workload->engine->i915,
2947                                            roundup(ctx_size + CACHELINE_BYTES,
2948                                                    PAGE_SIZE));
2949         if (IS_ERR(obj))
2950                 return PTR_ERR(obj);
2951
2952         /* get the va of the shadow batch buffer */
2953         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2954         if (IS_ERR(map)) {
2955                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2956                 ret = PTR_ERR(map);
2957                 goto put_obj;
2958         }
2959
2960         i915_gem_object_lock(obj);
2961         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2962         i915_gem_object_unlock(obj);
2963         if (ret) {
2964                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2965                 goto unmap_src;
2966         }
2967
2968         ret = copy_gma_to_hva(workload->vgpu,
2969                                 workload->vgpu->gtt.ggtt_mm,
2970                                 guest_gma, guest_gma + ctx_size,
2971                                 map);
2972         if (ret < 0) {
2973                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2974                 goto unmap_src;
2975         }
2976
2977         wa_ctx->indirect_ctx.obj = obj;
2978         wa_ctx->indirect_ctx.shadow_va = map;
2979         return 0;
2980
2981 unmap_src:
2982         i915_gem_object_unpin_map(obj);
2983 put_obj:
2984         i915_gem_object_put(obj);
2985         return ret;
2986 }
2987
2988 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2989 {
2990         u32 per_ctx_start[CACHELINE_DWORDS] = {0};
2991         unsigned char *bb_start_sva;
2992
2993         if (!wa_ctx->per_ctx.valid)
2994                 return 0;
2995
2996         per_ctx_start[0] = 0x18800001;
2997         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2998
2999         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3000                                 wa_ctx->indirect_ctx.size;
3001
3002         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3003
3004         return 0;
3005 }
3006
3007 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3008 {
3009         int ret;
3010         struct intel_vgpu_workload *workload = container_of(wa_ctx,
3011                                         struct intel_vgpu_workload,
3012                                         wa_ctx);
3013         struct intel_vgpu *vgpu = workload->vgpu;
3014
3015         if (wa_ctx->indirect_ctx.size == 0)
3016                 return 0;
3017
3018         ret = shadow_indirect_ctx(wa_ctx);
3019         if (ret) {
3020                 gvt_vgpu_err("fail to shadow indirect ctx\n");
3021                 return ret;
3022         }
3023
3024         combine_wa_ctx(wa_ctx);
3025
3026         ret = scan_wa_ctx(wa_ctx);
3027         if (ret) {
3028                 gvt_vgpu_err("scan wa ctx error\n");
3029                 return ret;
3030         }
3031
3032         return 0;
3033 }
3034
3035 static int init_cmd_table(struct intel_gvt *gvt)
3036 {
3037         unsigned int gen_type = intel_gvt_get_device_type(gvt);
3038         int i;
3039
3040         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3041                 struct cmd_entry *e;
3042
3043                 if (!(cmd_info[i].devices & gen_type))
3044                         continue;
3045
3046                 e = kzalloc(sizeof(*e), GFP_KERNEL);
3047                 if (!e)
3048                         return -ENOMEM;
3049
3050                 e->info = &cmd_info[i];
3051                 if (cmd_info[i].opcode == OP_MI_NOOP)
3052                         mi_noop_index = i;
3053
3054                 INIT_HLIST_NODE(&e->hlist);
3055                 add_cmd_entry(gvt, e);
3056                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3057                             e->info->name, e->info->opcode, e->info->flag,
3058                             e->info->devices, e->info->rings);
3059         }
3060
3061         return 0;
3062 }
3063
3064 static void clean_cmd_table(struct intel_gvt *gvt)
3065 {
3066         struct hlist_node *tmp;
3067         struct cmd_entry *e;
3068         int i;
3069
3070         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3071                 kfree(e);
3072
3073         hash_init(gvt->cmd_table);
3074 }
3075
3076 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3077 {
3078         clean_cmd_table(gvt);
3079 }
3080
3081 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3082 {
3083         int ret;
3084
3085         ret = init_cmd_table(gvt);
3086         if (ret) {
3087                 intel_gvt_clean_cmd_parser(gvt);
3088                 return ret;
3089         }
3090         return 0;
3091 }