2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
37 #include <linux/slab.h>
40 #include "gt/intel_ring.h"
42 #include "i915_pvinfo.h"
45 #define INVALID_OP (~0U)
49 #define OP_LEN_3D_MEDIA 16
50 #define OP_LEN_MFX_VC 16
51 #define OP_LEN_VEBOX 16
53 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
63 const struct sub_op_bits *sub_op;
66 #define MAX_CMD_BUDGET 0x7fffffff
67 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
68 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
69 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
71 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
72 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
73 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
75 /* Render Command Map */
77 /* MI_* command Opcode (28:23) */
78 #define OP_MI_NOOP 0x0
79 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
80 #define OP_MI_USER_INTERRUPT 0x2
81 #define OP_MI_WAIT_FOR_EVENT 0x3
82 #define OP_MI_FLUSH 0x4
83 #define OP_MI_ARB_CHECK 0x5
84 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
85 #define OP_MI_REPORT_HEAD 0x7
86 #define OP_MI_ARB_ON_OFF 0x8
87 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
88 #define OP_MI_BATCH_BUFFER_END 0xA
89 #define OP_MI_SUSPEND_FLUSH 0xB
90 #define OP_MI_PREDICATE 0xC /* IVB+ */
91 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
92 #define OP_MI_SET_APPID 0xE /* IVB+ */
93 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
94 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
95 #define OP_MI_DISPLAY_FLIP 0x14
96 #define OP_MI_SEMAPHORE_MBOX 0x16
97 #define OP_MI_SET_CONTEXT 0x18
98 #define OP_MI_MATH 0x1A
99 #define OP_MI_URB_CLEAR 0x19
100 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
101 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
103 #define OP_MI_STORE_DATA_IMM 0x20
104 #define OP_MI_STORE_DATA_INDEX 0x21
105 #define OP_MI_LOAD_REGISTER_IMM 0x22
106 #define OP_MI_UPDATE_GTT 0x23
107 #define OP_MI_STORE_REGISTER_MEM 0x24
108 #define OP_MI_FLUSH_DW 0x26
109 #define OP_MI_CLFLUSH 0x27
110 #define OP_MI_REPORT_PERF_COUNT 0x28
111 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
112 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
113 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
114 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
115 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
116 #define OP_MI_2E 0x2E /* BDW+ */
117 #define OP_MI_2F 0x2F /* BDW+ */
118 #define OP_MI_BATCH_BUFFER_START 0x31
120 /* Bit definition for dword 0 */
121 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
123 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
125 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
126 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
127 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
128 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
130 /* 2D command: Opcode (28:22) */
131 #define OP_2D(x) ((2<<7) | x)
133 #define OP_XY_SETUP_BLT OP_2D(0x1)
134 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
135 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
136 #define OP_XY_PIXEL_BLT OP_2D(0x24)
137 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
138 #define OP_XY_TEXT_BLT OP_2D(0x26)
139 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
140 #define OP_XY_COLOR_BLT OP_2D(0x50)
141 #define OP_XY_PAT_BLT OP_2D(0x51)
142 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
143 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
144 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
145 #define OP_XY_FULL_BLT OP_2D(0x55)
146 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
147 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
148 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
149 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
150 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
151 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
152 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
153 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
154 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
155 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
156 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
158 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
159 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
160 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
162 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
164 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
165 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
166 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
167 #define OP_SWTESS_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x03)
169 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
171 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
173 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
174 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
175 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
176 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
177 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
178 #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5)
180 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
181 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
182 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
183 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
185 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
186 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
187 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
188 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
189 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
190 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
191 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
192 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
193 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
194 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
195 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
196 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
197 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
198 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
199 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
200 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
201 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
202 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
203 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
204 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
205 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
206 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
207 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
208 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
209 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
210 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
211 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
212 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
213 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
214 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
215 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
216 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
219 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
220 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
221 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
224 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
225 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
226 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
227 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
228 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
229 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
230 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
232 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
233 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
234 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
235 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
238 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
239 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
240 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
241 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
242 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
243 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
244 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
245 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
247 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
248 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
249 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
250 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
252 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
253 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
254 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
255 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
256 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
257 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
258 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
259 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
260 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
261 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
262 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
264 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
265 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
266 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
267 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
268 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
269 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
270 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
271 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
272 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
273 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
274 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
275 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
276 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
277 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
278 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
281 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
282 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
283 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
284 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
285 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
286 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
287 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
288 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
289 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
290 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
291 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
293 /* VCCP Command Parser */
296 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
297 * git://anongit.freedesktop.org/vaapi/intel-driver
302 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
309 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
310 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
311 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
312 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
313 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
314 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
315 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
316 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
317 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
318 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
319 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
321 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
323 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
324 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
325 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
326 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
327 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
328 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
329 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
330 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
331 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
332 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
333 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
334 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
336 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
337 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
338 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
339 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
340 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
342 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
343 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
344 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
345 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
346 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
348 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
349 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
350 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
352 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
353 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
354 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
356 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
363 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
364 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
365 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
367 struct parser_exec_state;
369 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
371 #define GVT_CMD_HASH_BITS 7
373 /* which DWords need address fix */
374 #define ADDR_FIX_1(x1) (1 << (x1))
375 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
376 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
377 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
378 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
380 #define DWORD_FIELD(dword, end, start) \
381 FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
383 #define OP_LENGTH_BIAS 2
384 #define CMD_LEN(value) (value + OP_LENGTH_BIAS)
386 static int gvt_check_valid_cmd_length(int len, int valid_len)
388 if (valid_len != len) {
389 gvt_err("len is not valid: len=%u valid_len=%u\n",
400 #define F_LEN_MASK 3U
401 #define F_LEN_CONST 1U
403 /* value is const although LEN maybe variable */
404 #define F_LEN_VAR_FIXED (1<<1)
407 * command has its own ip advance logic
408 * e.g. MI_BATCH_START, MI_BATCH_END
410 #define F_IP_ADVANCE_CUSTOM (1<<2)
413 #define R_RCS BIT(RCS0)
414 #define R_VCS1 BIT(VCS0)
415 #define R_VCS2 BIT(VCS1)
416 #define R_VCS (R_VCS1 | R_VCS2)
417 #define R_BCS BIT(BCS0)
418 #define R_VECS BIT(VECS0)
419 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
420 /* rings that support this cmd: BLT/RCS/VCS/VECS */
423 /* devices that support this cmd: SNB/IVB/HSW/... */
426 /* which DWords are address that need fix up.
427 * bit 0 means a 32-bit non address operand in command
428 * bit 1 means address operand, which could be 32-bit
429 * or 64-bit depending on different architectures.(
430 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
431 * No matter the address length, each address only takes
432 * one bit in the bitmap.
436 /* flag == F_LEN_CONST : command length
437 * flag == F_LEN_VAR : length bias bits
438 * Note: length is in DWord
442 parser_cmd_handler handler;
444 /* valid length in DWord */
449 struct hlist_node hlist;
450 const struct cmd_info *info;
454 RING_BUFFER_INSTRUCTION,
455 BATCH_BUFFER_INSTRUCTION,
456 BATCH_BUFFER_2ND_LEVEL,
464 struct parser_exec_state {
465 struct intel_vgpu *vgpu;
466 const struct intel_engine_cs *engine;
470 /* batch buffer address type */
473 /* graphics memory address of ring buffer start */
474 unsigned long ring_start;
475 unsigned long ring_size;
476 unsigned long ring_head;
477 unsigned long ring_tail;
479 /* instruction graphics memory address */
480 unsigned long ip_gma;
482 /* mapped va of the instr_gma */
487 /* next instruction when return from batch buffer to ring buffer */
488 unsigned long ret_ip_gma_ring;
490 /* next instruction when return from 2nd batch buffer to batch buffer */
491 unsigned long ret_ip_gma_bb;
493 /* batch buffer address type (GTT or PPGTT)
494 * used when ret from 2nd level batch buffer
496 int saved_buf_addr_type;
499 const struct cmd_info *info;
501 struct intel_vgpu_workload *workload;
504 #define gmadr_dw_number(s) \
505 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
507 static unsigned long bypass_scan_mask = 0;
509 /* ring ALL, type = 0 */
510 static const struct sub_op_bits sub_op_mi[] = {
515 static const struct decode_info decode_info_mi = {
518 ARRAY_SIZE(sub_op_mi),
522 /* ring RCS, command type 2 */
523 static const struct sub_op_bits sub_op_2d[] = {
528 static const struct decode_info decode_info_2d = {
531 ARRAY_SIZE(sub_op_2d),
535 /* ring RCS, command type 3 */
536 static const struct sub_op_bits sub_op_3d_media[] = {
543 static const struct decode_info decode_info_3d_media = {
546 ARRAY_SIZE(sub_op_3d_media),
550 /* ring VCS, command type 3 */
551 static const struct sub_op_bits sub_op_mfx_vc[] = {
559 static const struct decode_info decode_info_mfx_vc = {
562 ARRAY_SIZE(sub_op_mfx_vc),
566 /* ring VECS, command type 3 */
567 static const struct sub_op_bits sub_op_vebox[] = {
575 static const struct decode_info decode_info_vebox = {
578 ARRAY_SIZE(sub_op_vebox),
582 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
587 &decode_info_3d_media,
639 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
641 const struct decode_info *d_info;
643 d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
647 return cmd >> (32 - d_info->op_len);
650 static inline const struct cmd_info *
651 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
652 const struct intel_engine_cs *engine)
656 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
657 if (opcode == e->info->opcode &&
658 e->info->rings & engine->mask)
664 static inline const struct cmd_info *
665 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
666 const struct intel_engine_cs *engine)
670 opcode = get_opcode(cmd, engine);
671 if (opcode == INVALID_OP)
674 return find_cmd_entry(gvt, opcode, engine);
677 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
679 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
682 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
684 const struct decode_info *d_info;
687 d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
691 gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
692 cmd >> (32 - d_info->op_len), d_info->name);
694 for (i = 0; i < d_info->nr_sub_op; i++)
695 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
696 d_info->sub_op[i].low));
701 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
703 return s->ip_va + (index << 2);
706 static inline u32 cmd_val(struct parser_exec_state *s, int index)
708 return *cmd_ptr(s, index);
711 static void parser_exec_state_dump(struct parser_exec_state *s)
716 gvt_dbg_cmd(" vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
717 " ring_head(%08lx) ring_tail(%08lx)\n",
718 s->vgpu->id, s->engine->name,
719 s->ring_start, s->ring_start + s->ring_size,
720 s->ring_head, s->ring_tail);
722 gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
723 s->buf_type == RING_BUFFER_INSTRUCTION ?
724 "RING_BUFFER" : "BATCH_BUFFER",
725 s->buf_addr_type == GTT_BUFFER ?
726 "GTT" : "PPGTT", s->ip_gma);
728 if (s->ip_va == NULL) {
729 gvt_dbg_cmd(" ip_va(NULL)");
733 gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
734 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
735 cmd_val(s, 2), cmd_val(s, 3));
737 print_opcode(cmd_val(s, 0), s->engine);
739 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
742 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
743 for (i = 0; i < 8; i++)
744 gvt_dbg_cmd("%08x ", cmd_val(s, i));
747 s->ip_va += 8 * sizeof(u32);
752 static inline void update_ip_va(struct parser_exec_state *s)
754 unsigned long len = 0;
756 if (WARN_ON(s->ring_head == s->ring_tail))
759 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
760 unsigned long ring_top = s->ring_start + s->ring_size;
762 if (s->ring_head > s->ring_tail) {
763 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
764 len = (s->ip_gma - s->ring_head);
765 else if (s->ip_gma >= s->ring_start &&
766 s->ip_gma <= s->ring_tail)
767 len = (ring_top - s->ring_head) +
768 (s->ip_gma - s->ring_start);
770 len = (s->ip_gma - s->ring_head);
772 s->ip_va = s->rb_va + len;
773 } else {/* shadow batch buffer */
774 s->ip_va = s->ret_bb_va;
778 static inline int ip_gma_set(struct parser_exec_state *s,
779 unsigned long ip_gma)
781 WARN_ON(!IS_ALIGNED(ip_gma, 4));
788 static inline int ip_gma_advance(struct parser_exec_state *s,
791 s->ip_gma += (dw_len << 2);
793 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
794 if (s->ip_gma >= s->ring_start + s->ring_size)
795 s->ip_gma -= s->ring_size;
798 s->ip_va += (dw_len << 2);
804 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
806 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
809 return (cmd & ((1U << info->len) - 1)) + 2;
813 static inline int cmd_length(struct parser_exec_state *s)
815 return get_cmd_length(s->info, cmd_val(s, 0));
818 /* do not remove this, some platform may need clflush here */
819 #define patch_value(s, addr, val) do { \
823 static bool is_shadowed_mmio(unsigned int offset)
827 if ((offset == 0x2168) || /*BB current head register UDW */
828 (offset == 0x2140) || /*BB current header register */
829 (offset == 0x211c) || /*second BB header register UDW */
830 (offset == 0x2114)) { /*second BB header register UDW */
836 static inline bool is_force_nonpriv_mmio(unsigned int offset)
838 return (offset >= 0x24d0 && offset < 0x2500);
841 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
842 unsigned int offset, unsigned int index, char *cmd)
844 struct intel_gvt *gvt = s->vgpu->gvt;
849 if (!strcmp(cmd, "lri"))
850 data = cmd_val(s, index + 1);
852 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
857 ring_base = s->engine->mmio_base;
858 nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
860 if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
862 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
864 patch_value(s, cmd_ptr(s, index), nopid);
870 static inline bool is_mocs_mmio(unsigned int offset)
872 return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
873 ((offset >= 0xb020) && (offset <= 0xb0a0));
876 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
877 unsigned int offset, unsigned int index)
879 if (!is_mocs_mmio(offset))
881 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
885 static int is_cmd_update_pdps(unsigned int offset,
886 struct parser_exec_state *s)
888 u32 base = s->workload->engine->mmio_base;
889 return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
892 static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
893 unsigned int offset, unsigned int index)
895 struct intel_vgpu *vgpu = s->vgpu;
896 struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
897 struct intel_vgpu_mm *mm;
898 u64 pdps[GEN8_3LVL_PDPES];
900 if (shadow_mm->ppgtt_mm.root_entry_type ==
901 GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
902 pdps[0] = (u64)cmd_val(s, 2) << 32;
903 pdps[0] |= cmd_val(s, 4);
905 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
907 gvt_vgpu_err("failed to get the 4-level shadow vm\n");
910 intel_vgpu_mm_get(mm);
911 list_add_tail(&mm->ppgtt_mm.link,
912 &s->workload->lri_shadow_mm);
913 *cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
914 *cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
916 /* Currently all guests use PML4 table and now can't
917 * have a guest with 3-level table but uses LRI for
918 * PPGTT update. So this is simply un-testable. */
920 gvt_vgpu_err("invalid shared shadow vm type\n");
926 static int cmd_reg_handler(struct parser_exec_state *s,
927 unsigned int offset, unsigned int index, char *cmd)
929 struct intel_vgpu *vgpu = s->vgpu;
930 struct intel_gvt *gvt = vgpu->gvt;
933 if (offset + 4 > gvt->device_info.mmio_size) {
934 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
939 if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
940 gvt_vgpu_err("%s access to non-render register (%x)\n",
945 if (is_shadowed_mmio(offset)) {
946 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
950 if (is_mocs_mmio(offset) &&
951 mocs_cmd_reg_handler(s, offset, index))
954 if (is_force_nonpriv_mmio(offset) &&
955 force_nonpriv_reg_handler(s, offset, index, cmd))
958 if (offset == i915_mmio_reg_offset(DERRMR) ||
959 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
960 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
961 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
964 if (is_cmd_update_pdps(offset, s) &&
965 cmd_pdp_mmio_update_handler(s, offset, index))
969 * In order to let workload with inhibit context to generate
970 * correct image data into memory, vregs values will be loaded to
971 * hw via LRIs in the workload with inhibit context. But as
972 * indirect context is loaded prior to LRIs in workload, we don't
973 * want reg values specified in indirect context overwritten by
974 * LRIs in workloads. So, when scanning an indirect context, we
975 * update reg values in it into vregs, so LRIs in workload with
976 * inhibit context will restore with correct values
978 if (IS_GEN(s->engine->i915, 9) &&
979 intel_gvt_mmio_is_in_ctx(gvt, offset) &&
980 !strncmp(cmd, "lri", 3)) {
981 intel_gvt_hypervisor_read_gpa(s->vgpu,
982 s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
983 /* check inhibit context */
984 if (ctx_sr_ctl & 1) {
985 u32 data = cmd_val(s, index + 1);
987 if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
988 intel_vgpu_mask_mmio_write(vgpu,
991 vgpu_vreg(vgpu, offset) = data;
995 /* TODO: Update the global mask if this MMIO is a masked-MMIO */
996 intel_gvt_mmio_set_cmd_accessed(gvt, offset);
1000 #define cmd_reg(s, i) \
1001 (cmd_val(s, i) & GENMASK(22, 2))
1003 #define cmd_reg_inhibit(s, i) \
1004 (cmd_val(s, i) & GENMASK(22, 18))
1006 #define cmd_gma(s, i) \
1007 (cmd_val(s, i) & GENMASK(31, 2))
1009 #define cmd_gma_hi(s, i) \
1010 (cmd_val(s, i) & GENMASK(15, 0))
1012 static int cmd_handler_lri(struct parser_exec_state *s)
1015 int cmd_len = cmd_length(s);
1017 for (i = 1; i < cmd_len; i += 2) {
1018 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1019 if (s->engine->id == BCS0 &&
1020 cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1023 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1027 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1034 static int cmd_handler_lrr(struct parser_exec_state *s)
1037 int cmd_len = cmd_length(s);
1039 for (i = 1; i < cmd_len; i += 2) {
1040 if (IS_BROADWELL(s->engine->i915))
1041 ret |= ((cmd_reg_inhibit(s, i) ||
1042 (cmd_reg_inhibit(s, i + 1)))) ?
1046 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1049 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1056 static inline int cmd_address_audit(struct parser_exec_state *s,
1057 unsigned long guest_gma, int op_size, bool index_mode);
1059 static int cmd_handler_lrm(struct parser_exec_state *s)
1061 struct intel_gvt *gvt = s->vgpu->gvt;
1062 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1065 int cmd_len = cmd_length(s);
1067 for (i = 1; i < cmd_len;) {
1068 if (IS_BROADWELL(s->engine->i915))
1069 ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1072 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1075 if (cmd_val(s, 0) & (1 << 22)) {
1076 gma = cmd_gma(s, i + 1);
1077 if (gmadr_bytes == 8)
1078 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1079 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1083 i += gmadr_dw_number(s) + 1;
1088 static int cmd_handler_srm(struct parser_exec_state *s)
1090 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1093 int cmd_len = cmd_length(s);
1095 for (i = 1; i < cmd_len;) {
1096 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1099 if (cmd_val(s, 0) & (1 << 22)) {
1100 gma = cmd_gma(s, i + 1);
1101 if (gmadr_bytes == 8)
1102 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1103 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1107 i += gmadr_dw_number(s) + 1;
1112 struct cmd_interrupt_event {
1113 int pipe_control_notify;
1115 int mi_user_interrupt;
1118 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1120 .pipe_control_notify = RCS_PIPE_CONTROL,
1121 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1122 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1125 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1126 .mi_flush_dw = BCS_MI_FLUSH_DW,
1127 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1130 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1131 .mi_flush_dw = VCS_MI_FLUSH_DW,
1132 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1135 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1136 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1137 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1140 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1141 .mi_flush_dw = VECS_MI_FLUSH_DW,
1142 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1146 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1148 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1150 bool index_mode = false;
1151 unsigned int post_sync;
1155 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1158 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1159 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1161 else if (post_sync) {
1163 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1164 else if (post_sync == 3)
1165 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1166 else if (post_sync == 1) {
1168 if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1169 gma = cmd_val(s, 2) & GENMASK(31, 3);
1170 if (gmadr_bytes == 8)
1171 gma |= (cmd_gma_hi(s, 3)) << 32;
1172 /* Store Data Index */
1173 if (cmd_val(s, 1) & (1 << 21))
1175 ret |= cmd_address_audit(s, gma, sizeof(u64),
1180 hws_pga = s->vgpu->hws_pga[s->engine->id];
1181 gma = hws_pga + gma;
1182 patch_value(s, cmd_ptr(s, 2), gma);
1183 val = cmd_val(s, 1) & (~(1 << 21));
1184 patch_value(s, cmd_ptr(s, 1), val);
1193 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1194 set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1195 s->workload->pending_events);
1199 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1201 set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1202 s->workload->pending_events);
1203 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1207 static int cmd_advance_default(struct parser_exec_state *s)
1209 return ip_gma_advance(s, cmd_length(s));
1212 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1216 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1217 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1218 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1219 s->buf_addr_type = s->saved_buf_addr_type;
1221 s->buf_type = RING_BUFFER_INSTRUCTION;
1222 s->buf_addr_type = GTT_BUFFER;
1223 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1224 s->ret_ip_gma_ring -= s->ring_size;
1225 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1230 struct mi_display_flip_command_info {
1234 i915_reg_t stride_reg;
1235 i915_reg_t ctrl_reg;
1236 i915_reg_t surf_reg;
1243 struct plane_code_mapping {
1249 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1250 struct mi_display_flip_command_info *info)
1252 struct drm_i915_private *dev_priv = s->engine->i915;
1253 struct plane_code_mapping gen8_plane_code[] = {
1254 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1255 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1256 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1257 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1258 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1259 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1261 u32 dword0, dword1, dword2;
1264 dword0 = cmd_val(s, 0);
1265 dword1 = cmd_val(s, 1);
1266 dword2 = cmd_val(s, 2);
1268 v = (dword0 & GENMASK(21, 19)) >> 19;
1269 if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1272 info->pipe = gen8_plane_code[v].pipe;
1273 info->plane = gen8_plane_code[v].plane;
1274 info->event = gen8_plane_code[v].event;
1275 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1276 info->tile_val = (dword1 & 0x1);
1277 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1278 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1280 if (info->plane == PLANE_A) {
1281 info->ctrl_reg = DSPCNTR(info->pipe);
1282 info->stride_reg = DSPSTRIDE(info->pipe);
1283 info->surf_reg = DSPSURF(info->pipe);
1284 } else if (info->plane == PLANE_B) {
1285 info->ctrl_reg = SPRCTL(info->pipe);
1286 info->stride_reg = SPRSTRIDE(info->pipe);
1287 info->surf_reg = SPRSURF(info->pipe);
1289 drm_WARN_ON(&dev_priv->drm, 1);
1295 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1296 struct mi_display_flip_command_info *info)
1298 struct drm_i915_private *dev_priv = s->engine->i915;
1299 struct intel_vgpu *vgpu = s->vgpu;
1300 u32 dword0 = cmd_val(s, 0);
1301 u32 dword1 = cmd_val(s, 1);
1302 u32 dword2 = cmd_val(s, 2);
1303 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1305 info->plane = PRIMARY_PLANE;
1308 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1309 info->pipe = PIPE_A;
1310 info->event = PRIMARY_A_FLIP_DONE;
1312 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1313 info->pipe = PIPE_B;
1314 info->event = PRIMARY_B_FLIP_DONE;
1316 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1317 info->pipe = PIPE_C;
1318 info->event = PRIMARY_C_FLIP_DONE;
1321 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1322 info->pipe = PIPE_A;
1323 info->event = SPRITE_A_FLIP_DONE;
1324 info->plane = SPRITE_PLANE;
1326 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1327 info->pipe = PIPE_B;
1328 info->event = SPRITE_B_FLIP_DONE;
1329 info->plane = SPRITE_PLANE;
1331 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1332 info->pipe = PIPE_C;
1333 info->event = SPRITE_C_FLIP_DONE;
1334 info->plane = SPRITE_PLANE;
1338 gvt_vgpu_err("unknown plane code %d\n", plane);
1342 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1343 info->tile_val = (dword1 & GENMASK(2, 0));
1344 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1345 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1347 info->ctrl_reg = DSPCNTR(info->pipe);
1348 info->stride_reg = DSPSTRIDE(info->pipe);
1349 info->surf_reg = DSPSURF(info->pipe);
1354 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1355 struct mi_display_flip_command_info *info)
1359 if (!info->async_flip)
1362 if (INTEL_GEN(s->engine->i915) >= 9) {
1363 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1364 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1365 GENMASK(12, 10)) >> 10;
1367 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1368 GENMASK(15, 6)) >> 6;
1369 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1372 if (stride != info->stride_val)
1373 gvt_dbg_cmd("cannot change stride during async flip\n");
1375 if (tile != info->tile_val)
1376 gvt_dbg_cmd("cannot change tile during async flip\n");
1381 static int gen8_update_plane_mmio_from_mi_display_flip(
1382 struct parser_exec_state *s,
1383 struct mi_display_flip_command_info *info)
1385 struct drm_i915_private *dev_priv = s->engine->i915;
1386 struct intel_vgpu *vgpu = s->vgpu;
1388 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1389 info->surf_val << 12);
1390 if (INTEL_GEN(dev_priv) >= 9) {
1391 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1393 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1394 info->tile_val << 10);
1396 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1397 info->stride_val << 6);
1398 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1399 info->tile_val << 10);
1402 if (info->plane == PLANE_PRIMARY)
1403 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1405 if (info->async_flip)
1406 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1408 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1413 static int decode_mi_display_flip(struct parser_exec_state *s,
1414 struct mi_display_flip_command_info *info)
1416 if (IS_BROADWELL(s->engine->i915))
1417 return gen8_decode_mi_display_flip(s, info);
1418 if (INTEL_GEN(s->engine->i915) >= 9)
1419 return skl_decode_mi_display_flip(s, info);
1424 static int check_mi_display_flip(struct parser_exec_state *s,
1425 struct mi_display_flip_command_info *info)
1427 return gen8_check_mi_display_flip(s, info);
1430 static int update_plane_mmio_from_mi_display_flip(
1431 struct parser_exec_state *s,
1432 struct mi_display_flip_command_info *info)
1434 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1437 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1439 struct mi_display_flip_command_info info;
1440 struct intel_vgpu *vgpu = s->vgpu;
1443 int len = cmd_length(s);
1444 u32 valid_len = CMD_LEN(1);
1446 /* Flip Type == Stereo 3D Flip */
1447 if (DWORD_FIELD(2, 1, 0) == 2)
1449 ret = gvt_check_valid_cmd_length(cmd_length(s),
1454 ret = decode_mi_display_flip(s, &info);
1456 gvt_vgpu_err("fail to decode MI display flip command\n");
1460 ret = check_mi_display_flip(s, &info);
1462 gvt_vgpu_err("invalid MI display flip command\n");
1466 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1468 gvt_vgpu_err("fail to update plane mmio\n");
1472 for (i = 0; i < len; i++)
1473 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1477 static bool is_wait_for_flip_pending(u32 cmd)
1479 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1480 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1481 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1482 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1483 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1484 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1487 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1489 u32 cmd = cmd_val(s, 0);
1491 if (!is_wait_for_flip_pending(cmd))
1494 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1498 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1501 unsigned long gma_high, gma_low;
1502 struct intel_vgpu *vgpu = s->vgpu;
1503 int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1505 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1506 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1507 return INTEL_GVT_INVALID_ADDR;
1510 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1511 if (gmadr_bytes == 4) {
1514 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1515 addr = (((unsigned long)gma_high) << 32) | gma_low;
1520 static inline int cmd_address_audit(struct parser_exec_state *s,
1521 unsigned long guest_gma, int op_size, bool index_mode)
1523 struct intel_vgpu *vgpu = s->vgpu;
1524 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1528 if (op_size > max_surface_size) {
1529 gvt_vgpu_err("command address audit fail name %s\n",
1535 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1539 } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1547 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1548 s->info->name, guest_gma, op_size);
1550 pr_err("cmd dump: ");
1551 for (i = 0; i < cmd_length(s); i++) {
1553 pr_err("\n%08x ", cmd_val(s, i));
1555 pr_err("%08x ", cmd_val(s, i));
1557 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1559 vgpu_aperture_gmadr_base(vgpu),
1560 vgpu_aperture_gmadr_end(vgpu),
1561 vgpu_hidden_gmadr_base(vgpu),
1562 vgpu_hidden_gmadr_end(vgpu));
1566 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1568 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1569 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1570 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1571 unsigned long gma, gma_low, gma_high;
1572 u32 valid_len = CMD_LEN(2);
1576 if (!(cmd_val(s, 0) & (1 << 22)))
1579 /* check if QWORD */
1580 if (DWORD_FIELD(0, 21, 21))
1582 ret = gvt_check_valid_cmd_length(cmd_length(s),
1587 gma = cmd_val(s, 2) & GENMASK(31, 2);
1589 if (gmadr_bytes == 8) {
1590 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1591 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1592 gma = (gma_high << 32) | gma_low;
1593 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1595 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1599 static inline int unexpected_cmd(struct parser_exec_state *s)
1601 struct intel_vgpu *vgpu = s->vgpu;
1603 gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1608 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1610 return unexpected_cmd(s);
1613 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1615 return unexpected_cmd(s);
1618 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1620 return unexpected_cmd(s);
1623 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1625 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1626 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1628 unsigned long gma, gma_high;
1629 u32 valid_len = CMD_LEN(1);
1632 if (!(cmd_val(s, 0) & (1 << 22)))
1635 /* check inline data */
1636 if (cmd_val(s, 0) & BIT(18))
1637 valid_len = CMD_LEN(9);
1638 ret = gvt_check_valid_cmd_length(cmd_length(s),
1643 gma = cmd_val(s, 1) & GENMASK(31, 2);
1644 if (gmadr_bytes == 8) {
1645 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1646 gma = (gma_high << 32) | gma;
1648 ret = cmd_address_audit(s, gma, op_size, false);
1652 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1654 return unexpected_cmd(s);
1657 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1659 return unexpected_cmd(s);
1662 static int cmd_handler_mi_conditional_batch_buffer_end(
1663 struct parser_exec_state *s)
1665 return unexpected_cmd(s);
1668 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1670 return unexpected_cmd(s);
1673 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1675 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1677 bool index_mode = false;
1680 u32 valid_len = CMD_LEN(2);
1682 ret = gvt_check_valid_cmd_length(cmd_length(s),
1685 /* Check again for Qword */
1686 ret = gvt_check_valid_cmd_length(cmd_length(s),
1691 /* Check post-sync and ppgtt bit */
1692 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1693 gma = cmd_val(s, 1) & GENMASK(31, 3);
1694 if (gmadr_bytes == 8)
1695 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1696 /* Store Data Index */
1697 if (cmd_val(s, 0) & (1 << 21))
1699 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1703 hws_pga = s->vgpu->hws_pga[s->engine->id];
1704 gma = hws_pga + gma;
1705 patch_value(s, cmd_ptr(s, 1), gma);
1706 val = cmd_val(s, 0) & (~(1 << 21));
1707 patch_value(s, cmd_ptr(s, 0), val);
1710 /* Check notify bit */
1711 if ((cmd_val(s, 0) & (1 << 8)))
1712 set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1713 s->workload->pending_events);
1717 static void addr_type_update_snb(struct parser_exec_state *s)
1719 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1720 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1721 s->buf_addr_type = PPGTT_BUFFER;
1726 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1727 unsigned long gma, unsigned long end_gma, void *va)
1729 unsigned long copy_len, offset;
1730 unsigned long len = 0;
1733 while (gma != end_gma) {
1734 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1735 if (gpa == INTEL_GVT_INVALID_ADDR) {
1736 gvt_vgpu_err("invalid gma address: %lx\n", gma);
1740 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1742 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1743 I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1745 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1755 * Check whether a batch buffer needs to be scanned. Currently
1756 * the only criteria is based on privilege.
1758 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1760 /* Decide privilege based on address space */
1761 if (cmd_val(s, 0) & BIT(8) &&
1762 !(s->vgpu->scan_nonprivbb & s->engine->mask))
1768 static const char *repr_addr_type(unsigned int type)
1770 return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1773 static int find_bb_size(struct parser_exec_state *s,
1774 unsigned long *bb_size,
1775 unsigned long *bb_end_cmd_offset)
1777 unsigned long gma = 0;
1778 const struct cmd_info *info;
1780 bool bb_end = false;
1781 struct intel_vgpu *vgpu = s->vgpu;
1783 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1784 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1787 *bb_end_cmd_offset = 0;
1789 /* get the start gm address of the batch buffer */
1790 gma = get_gma_bb_from_cmd(s, 1);
1791 if (gma == INTEL_GVT_INVALID_ADDR)
1794 cmd = cmd_val(s, 0);
1795 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1797 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1798 cmd, get_opcode(cmd, s->engine),
1799 repr_addr_type(s->buf_addr_type),
1800 s->engine->name, s->workload);
1804 if (copy_gma_to_hva(s->vgpu, mm,
1805 gma, gma + 4, &cmd) < 0)
1807 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1809 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1810 cmd, get_opcode(cmd, s->engine),
1811 repr_addr_type(s->buf_addr_type),
1812 s->engine->name, s->workload);
1816 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1818 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1819 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1820 /* chained batch buffer */
1825 *bb_end_cmd_offset = *bb_size;
1827 cmd_len = get_cmd_length(info, cmd) << 2;
1828 *bb_size += cmd_len;
1835 static int audit_bb_end(struct parser_exec_state *s, void *va)
1837 struct intel_vgpu *vgpu = s->vgpu;
1838 u32 cmd = *(u32 *)va;
1839 const struct cmd_info *info;
1841 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1843 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1844 cmd, get_opcode(cmd, s->engine),
1845 repr_addr_type(s->buf_addr_type),
1846 s->engine->name, s->workload);
1850 if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1851 ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1852 (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1858 static int perform_bb_shadow(struct parser_exec_state *s)
1860 struct intel_vgpu *vgpu = s->vgpu;
1861 struct intel_vgpu_shadow_bb *bb;
1862 unsigned long gma = 0;
1863 unsigned long bb_size;
1864 unsigned long bb_end_cmd_offset;
1866 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1867 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1868 unsigned long start_offset = 0;
1870 /* get the start gm address of the batch buffer */
1871 gma = get_gma_bb_from_cmd(s, 1);
1872 if (gma == INTEL_GVT_INVALID_ADDR)
1875 ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1879 bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1883 bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1885 /* the start_offset stores the batch buffer's start gma's
1886 * offset relative to page boundary. so for non-privileged batch
1887 * buffer, the shadowed gem object holds exactly the same page
1888 * layout as original gem object. This is for the convience of
1889 * replacing the whole non-privilged batch buffer page to this
1890 * shadowed one in PPGTT at the same gma address. (this replacing
1891 * action is not implemented yet now, but may be necessary in
1893 * for prileged batch buffer, we just change start gma address to
1894 * that of shadowed page.
1897 start_offset = gma & ~I915_GTT_PAGE_MASK;
1899 bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1900 round_up(bb_size + start_offset,
1902 if (IS_ERR(bb->obj)) {
1903 ret = PTR_ERR(bb->obj);
1907 ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush);
1911 bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1912 if (IS_ERR(bb->va)) {
1913 ret = PTR_ERR(bb->va);
1914 goto err_finish_shmem_access;
1917 if (bb->clflush & CLFLUSH_BEFORE) {
1918 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1919 bb->clflush &= ~CLFLUSH_BEFORE;
1922 ret = copy_gma_to_hva(s->vgpu, mm,
1924 bb->va + start_offset);
1926 gvt_vgpu_err("fail to copy guest ring buffer\n");
1931 ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1935 INIT_LIST_HEAD(&bb->list);
1936 list_add(&bb->list, &s->workload->shadow_bb);
1938 bb->accessing = true;
1939 bb->bb_start_cmd_va = s->ip_va;
1941 if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1942 bb->bb_offset = s->ip_va - s->rb_va;
1947 * ip_va saves the virtual address of the shadow batch buffer, while
1948 * ip_gma saves the graphics address of the original batch buffer.
1949 * As the shadow batch buffer is just a copy from the originial one,
1950 * it should be right to use shadow batch buffer'va and original batch
1951 * buffer's gma in pair. After all, we don't want to pin the shadow
1952 * buffer here (too early).
1954 s->ip_va = bb->va + start_offset;
1958 i915_gem_object_unpin_map(bb->obj);
1959 err_finish_shmem_access:
1960 i915_gem_object_finish_access(bb->obj);
1962 i915_gem_object_put(bb->obj);
1968 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1972 struct intel_vgpu *vgpu = s->vgpu;
1974 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1975 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1979 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1980 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1981 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1985 s->saved_buf_addr_type = s->buf_addr_type;
1986 addr_type_update_snb(s);
1987 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1988 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1989 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1990 } else if (second_level) {
1991 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1992 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1993 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1996 if (batch_buffer_needs_scan(s)) {
1997 ret = perform_bb_shadow(s);
1999 gvt_vgpu_err("invalid shadow batch buffer\n");
2001 /* emulate a batch buffer end to do return right */
2002 ret = cmd_handler_mi_batch_buffer_end(s);
2009 static int mi_noop_index;
2011 static const struct cmd_info cmd_info[] = {
2012 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2014 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2017 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2018 0, 1, cmd_handler_mi_user_interrupt},
2020 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2021 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2023 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2025 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2028 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2031 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2034 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2037 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2040 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2041 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2042 cmd_handler_mi_batch_buffer_end},
2044 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2047 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2050 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2053 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2056 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2059 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2060 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2062 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2063 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2065 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2067 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2068 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2070 {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2071 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2074 {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2075 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2076 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2078 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2079 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2081 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2082 0, 8, cmd_handler_mi_store_data_index},
2084 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2085 D_ALL, 0, 8, cmd_handler_lri},
2087 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2088 cmd_handler_mi_update_gtt},
2090 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2091 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2092 cmd_handler_srm, CMD_LEN(2)},
2094 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2095 cmd_handler_mi_flush_dw},
2097 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2098 10, cmd_handler_mi_clflush},
2100 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2101 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2102 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2104 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2105 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2106 cmd_handler_lrm, CMD_LEN(2)},
2108 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2109 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2110 cmd_handler_lrr, CMD_LEN(1)},
2112 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2113 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2114 8, NULL, CMD_LEN(2)},
2116 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2117 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2119 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2120 ADDR_FIX_1(2), 8, NULL},
2122 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2123 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2125 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2126 8, cmd_handler_mi_op_2f},
2128 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2129 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2130 cmd_handler_mi_batch_buffer_start},
2132 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2133 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2134 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2136 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2137 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2139 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2140 ADDR_FIX_2(4, 7), 8, NULL},
2142 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2145 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2146 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2148 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2150 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2153 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2154 ADDR_FIX_1(3), 8, NULL},
2156 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2159 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2160 ADDR_FIX_1(4), 8, NULL},
2162 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2163 ADDR_FIX_2(4, 5), 8, NULL},
2165 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2166 ADDR_FIX_1(4), 8, NULL},
2168 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2169 ADDR_FIX_2(4, 7), 8, NULL},
2171 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2172 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2174 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2176 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2177 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2179 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2180 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2182 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2183 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2184 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2186 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2187 D_ALL, ADDR_FIX_1(4), 8, NULL},
2189 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2190 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2192 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2193 D_ALL, ADDR_FIX_1(4), 8, NULL},
2195 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2196 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2198 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2199 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2201 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2202 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2203 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2205 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2206 ADDR_FIX_2(4, 5), 8, NULL},
2208 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2209 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2211 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2212 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2213 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2215 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2216 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2217 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2219 {"3DSTATE_BLEND_STATE_POINTERS",
2220 OP_3DSTATE_BLEND_STATE_POINTERS,
2221 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2223 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2224 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2225 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2227 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2228 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2229 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2231 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2232 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2233 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2235 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2236 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2237 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2240 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2241 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2243 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2244 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2245 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2248 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2249 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2251 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2252 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2253 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2255 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2256 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2257 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2259 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2260 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2261 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2263 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2264 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2265 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2267 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2270 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2273 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2276 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2279 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2280 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2282 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2283 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2285 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2286 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2288 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2289 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2291 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2292 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2294 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2295 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2297 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2298 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2300 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2301 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2303 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2304 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2306 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2307 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2309 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2310 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2312 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2313 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2315 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2316 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2318 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2319 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2321 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2322 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2324 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2325 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2327 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2328 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2330 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2331 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2333 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2334 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2336 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2337 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2339 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2340 D_BDW_PLUS, 0, 8, NULL},
2342 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2345 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2346 D_BDW_PLUS, 0, 8, NULL},
2348 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2349 D_BDW_PLUS, 0, 8, NULL},
2351 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2354 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2355 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2357 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2360 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2363 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2366 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2369 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2370 D_BDW_PLUS, 0, 8, NULL},
2372 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2373 R_RCS, D_ALL, 0, 8, NULL},
2375 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2376 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2378 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2379 R_RCS, D_ALL, 0, 1, NULL},
2381 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2383 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2384 R_RCS, D_ALL, 0, 8, NULL},
2386 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2387 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2389 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2391 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2393 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2395 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2396 D_BDW_PLUS, 0, 8, NULL},
2398 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2399 D_BDW_PLUS, 0, 8, NULL},
2401 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2404 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2405 D_BDW_PLUS, 0, 8, NULL},
2407 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2408 D_BDW_PLUS, 0, 8, NULL},
2410 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2412 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2414 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2416 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2419 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2421 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2423 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2424 R_RCS, D_ALL, 0, 8, NULL},
2426 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2427 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2429 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2432 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2433 D_ALL, ADDR_FIX_1(2), 8, NULL},
2435 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2436 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2438 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2439 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2441 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2444 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2447 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2450 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2451 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2453 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2454 D_BDW_PLUS, 0, 8, NULL},
2456 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2457 D_ALL, ADDR_FIX_1(2), 8, NULL},
2459 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2460 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2462 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2463 R_RCS, D_ALL, 0, 8, NULL},
2465 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2466 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2468 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2469 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2471 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2472 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2474 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2475 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2477 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2478 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2480 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2481 R_RCS, D_ALL, 0, 8, NULL},
2483 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2486 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2487 ADDR_FIX_2(2, 4), 8, NULL},
2489 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2490 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2491 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2493 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2494 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2496 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2497 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2498 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2500 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2501 D_BDW_PLUS, 0, 8, NULL},
2503 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2504 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2506 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2508 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2511 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2512 ADDR_FIX_1(1), 8, NULL},
2514 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2516 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2517 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2519 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2520 ADDR_FIX_1(1), 8, NULL},
2522 {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2523 F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2525 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2527 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2529 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2532 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2533 D_SKL_PLUS, 0, 8, NULL},
2535 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2536 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2538 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2541 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2544 {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2547 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2549 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2552 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2555 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2558 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2561 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2564 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2565 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2567 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2568 R_VCS, D_ALL, 0, 12, NULL},
2570 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2571 R_VCS, D_ALL, 0, 12, NULL},
2573 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2574 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2576 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2577 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2579 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2580 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2582 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2584 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2585 R_VCS, D_ALL, 0, 12, NULL},
2587 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2588 R_VCS, D_ALL, 0, 12, NULL},
2590 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2591 R_VCS, D_ALL, 0, 12, NULL},
2593 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2594 R_VCS, D_ALL, 0, 12, NULL},
2596 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2597 R_VCS, D_ALL, 0, 12, NULL},
2599 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2600 R_VCS, D_ALL, 0, 12, NULL},
2602 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2603 R_VCS, D_ALL, 0, 6, NULL},
2605 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2606 R_VCS, D_ALL, 0, 12, NULL},
2608 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2609 R_VCS, D_ALL, 0, 12, NULL},
2611 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2612 R_VCS, D_ALL, 0, 12, NULL},
2614 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2615 R_VCS, D_ALL, 0, 12, NULL},
2617 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2618 R_VCS, D_ALL, 0, 12, NULL},
2620 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2621 R_VCS, D_ALL, 0, 12, NULL},
2623 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2624 R_VCS, D_ALL, 0, 12, NULL},
2625 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2626 R_VCS, D_ALL, 0, 12, NULL},
2628 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2629 R_VCS, D_ALL, 0, 12, NULL},
2631 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2632 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2634 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2635 R_VCS, D_ALL, 0, 12, NULL},
2637 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2638 R_VCS, D_ALL, 0, 12, NULL},
2640 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2641 R_VCS, D_ALL, 0, 12, NULL},
2643 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2644 R_VCS, D_ALL, 0, 12, NULL},
2646 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2647 R_VCS, D_ALL, 0, 12, NULL},
2649 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2650 R_VCS, D_ALL, 0, 12, NULL},
2652 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2653 R_VCS, D_ALL, 0, 12, NULL},
2655 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2656 R_VCS, D_ALL, 0, 12, NULL},
2658 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2659 R_VCS, D_ALL, 0, 12, NULL},
2661 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2662 R_VCS, D_ALL, 0, 12, NULL},
2664 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2665 R_VCS, D_ALL, 0, 12, NULL},
2667 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2670 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2672 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2674 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2675 R_VCS, D_ALL, 0, 12, NULL},
2677 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2678 R_VCS, D_ALL, 0, 12, NULL},
2680 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2681 R_VCS, D_ALL, 0, 12, NULL},
2683 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2685 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2688 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2692 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2694 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2697 /* call the cmd handler, and advance ip */
2698 static int cmd_parser_exec(struct parser_exec_state *s)
2700 struct intel_vgpu *vgpu = s->vgpu;
2701 const struct cmd_info *info;
2705 cmd = cmd_val(s, 0);
2707 /* fastpath for MI_NOOP */
2709 info = &cmd_info[mi_noop_index];
2711 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2714 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2715 cmd, get_opcode(cmd, s->engine),
2716 repr_addr_type(s->buf_addr_type),
2717 s->engine->name, s->workload);
2723 trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2724 cmd_length(s), s->buf_type, s->buf_addr_type,
2725 s->workload, info->name);
2727 if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2728 ret = gvt_check_valid_cmd_length(cmd_length(s),
2734 if (info->handler) {
2735 ret = info->handler(s);
2737 gvt_vgpu_err("%s handler error\n", info->name);
2742 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2743 ret = cmd_advance_default(s);
2745 gvt_vgpu_err("%s IP advance error\n", info->name);
2752 static inline bool gma_out_of_range(unsigned long gma,
2753 unsigned long gma_head, unsigned int gma_tail)
2755 if (gma_tail >= gma_head)
2756 return (gma < gma_head) || (gma > gma_tail);
2758 return (gma > gma_tail) && (gma < gma_head);
2761 /* Keep the consistent return type, e.g EBADRQC for unknown
2762 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2763 * works as the input of VM healthy status.
2765 static int command_scan(struct parser_exec_state *s,
2766 unsigned long rb_head, unsigned long rb_tail,
2767 unsigned long rb_start, unsigned long rb_len)
2770 unsigned long gma_head, gma_tail, gma_bottom;
2772 struct intel_vgpu *vgpu = s->vgpu;
2774 gma_head = rb_start + rb_head;
2775 gma_tail = rb_start + rb_tail;
2776 gma_bottom = rb_start + rb_len;
2778 while (s->ip_gma != gma_tail) {
2779 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2780 if (!(s->ip_gma >= rb_start) ||
2781 !(s->ip_gma < gma_bottom)) {
2782 gvt_vgpu_err("ip_gma %lx out of ring scope."
2783 "(base:0x%lx, bottom: 0x%lx)\n",
2784 s->ip_gma, rb_start,
2786 parser_exec_state_dump(s);
2789 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2790 gvt_vgpu_err("ip_gma %lx out of range."
2791 "base 0x%lx head 0x%lx tail 0x%lx\n",
2792 s->ip_gma, rb_start,
2794 parser_exec_state_dump(s);
2798 ret = cmd_parser_exec(s);
2800 gvt_vgpu_err("cmd parser error\n");
2801 parser_exec_state_dump(s);
2809 static int scan_workload(struct intel_vgpu_workload *workload)
2811 unsigned long gma_head, gma_tail, gma_bottom;
2812 struct parser_exec_state s;
2815 /* ring base is page aligned */
2816 if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2819 gma_head = workload->rb_start + workload->rb_head;
2820 gma_tail = workload->rb_start + workload->rb_tail;
2821 gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl);
2823 s.buf_type = RING_BUFFER_INSTRUCTION;
2824 s.buf_addr_type = GTT_BUFFER;
2825 s.vgpu = workload->vgpu;
2826 s.engine = workload->engine;
2827 s.ring_start = workload->rb_start;
2828 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2829 s.ring_head = gma_head;
2830 s.ring_tail = gma_tail;
2831 s.rb_va = workload->shadow_ring_buffer_va;
2832 s.workload = workload;
2833 s.is_ctx_wa = false;
2835 if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2838 ret = ip_gma_set(&s, gma_head);
2842 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2843 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2849 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2852 unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2853 struct parser_exec_state s;
2855 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2856 struct intel_vgpu_workload,
2859 /* ring base is page aligned */
2860 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2861 I915_GTT_PAGE_SIZE)))
2864 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2865 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2867 gma_head = wa_ctx->indirect_ctx.guest_gma;
2868 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2869 gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2871 s.buf_type = RING_BUFFER_INSTRUCTION;
2872 s.buf_addr_type = GTT_BUFFER;
2873 s.vgpu = workload->vgpu;
2874 s.engine = workload->engine;
2875 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2876 s.ring_size = ring_size;
2877 s.ring_head = gma_head;
2878 s.ring_tail = gma_tail;
2879 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2880 s.workload = workload;
2883 ret = ip_gma_set(&s, gma_head);
2887 ret = command_scan(&s, 0, ring_tail,
2888 wa_ctx->indirect_ctx.guest_gma, ring_size);
2893 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2895 struct intel_vgpu *vgpu = workload->vgpu;
2896 struct intel_vgpu_submission *s = &vgpu->submission;
2897 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2898 void *shadow_ring_buffer_va;
2901 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2903 /* calculate workload ring buffer size */
2904 workload->rb_len = (workload->rb_tail + guest_rb_size -
2905 workload->rb_head) % guest_rb_size;
2907 gma_head = workload->rb_start + workload->rb_head;
2908 gma_tail = workload->rb_start + workload->rb_tail;
2909 gma_top = workload->rb_start + guest_rb_size;
2911 if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2914 /* realloc the new ring buffer if needed */
2915 p = krealloc(s->ring_scan_buffer[workload->engine->id],
2916 workload->rb_len, GFP_KERNEL);
2918 gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2921 s->ring_scan_buffer[workload->engine->id] = p;
2922 s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2925 shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2927 /* get shadow ring buffer va */
2928 workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2930 /* head > tail --> copy head <-> top */
2931 if (gma_head > gma_tail) {
2932 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2933 gma_head, gma_top, shadow_ring_buffer_va);
2935 gvt_vgpu_err("fail to copy guest ring buffer\n");
2938 shadow_ring_buffer_va += ret;
2939 gma_head = workload->rb_start;
2942 /* copy head or start <-> tail */
2943 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2944 shadow_ring_buffer_va);
2946 gvt_vgpu_err("fail to copy guest ring buffer\n");
2952 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2955 struct intel_vgpu *vgpu = workload->vgpu;
2957 ret = shadow_workload_ring_buffer(workload);
2959 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2963 ret = scan_workload(workload);
2965 gvt_vgpu_err("scan workload error\n");
2971 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2973 int ctx_size = wa_ctx->indirect_ctx.size;
2974 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2975 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2976 struct intel_vgpu_workload,
2978 struct intel_vgpu *vgpu = workload->vgpu;
2979 struct drm_i915_gem_object *obj;
2983 obj = i915_gem_object_create_shmem(workload->engine->i915,
2984 roundup(ctx_size + CACHELINE_BYTES,
2987 return PTR_ERR(obj);
2989 /* get the va of the shadow batch buffer */
2990 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2992 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2997 i915_gem_object_lock(obj);
2998 ret = i915_gem_object_set_to_cpu_domain(obj, false);
2999 i915_gem_object_unlock(obj);
3001 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3005 ret = copy_gma_to_hva(workload->vgpu,
3006 workload->vgpu->gtt.ggtt_mm,
3007 guest_gma, guest_gma + ctx_size,
3010 gvt_vgpu_err("fail to copy guest indirect ctx\n");
3014 wa_ctx->indirect_ctx.obj = obj;
3015 wa_ctx->indirect_ctx.shadow_va = map;
3019 i915_gem_object_unpin_map(obj);
3021 i915_gem_object_put(obj);
3025 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3027 u32 per_ctx_start[CACHELINE_DWORDS] = {0};
3028 unsigned char *bb_start_sva;
3030 if (!wa_ctx->per_ctx.valid)
3033 per_ctx_start[0] = 0x18800001;
3034 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3036 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3037 wa_ctx->indirect_ctx.size;
3039 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3044 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3047 struct intel_vgpu_workload *workload = container_of(wa_ctx,
3048 struct intel_vgpu_workload,
3050 struct intel_vgpu *vgpu = workload->vgpu;
3052 if (wa_ctx->indirect_ctx.size == 0)
3055 ret = shadow_indirect_ctx(wa_ctx);
3057 gvt_vgpu_err("fail to shadow indirect ctx\n");
3061 combine_wa_ctx(wa_ctx);
3063 ret = scan_wa_ctx(wa_ctx);
3065 gvt_vgpu_err("scan wa ctx error\n");
3072 static int init_cmd_table(struct intel_gvt *gvt)
3074 unsigned int gen_type = intel_gvt_get_device_type(gvt);
3077 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3078 struct cmd_entry *e;
3080 if (!(cmd_info[i].devices & gen_type))
3083 e = kzalloc(sizeof(*e), GFP_KERNEL);
3087 e->info = &cmd_info[i];
3088 if (cmd_info[i].opcode == OP_MI_NOOP)
3091 INIT_HLIST_NODE(&e->hlist);
3092 add_cmd_entry(gvt, e);
3093 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3094 e->info->name, e->info->opcode, e->info->flag,
3095 e->info->devices, e->info->rings);
3101 static void clean_cmd_table(struct intel_gvt *gvt)
3103 struct hlist_node *tmp;
3104 struct cmd_entry *e;
3107 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3110 hash_init(gvt->cmd_table);
3113 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3115 clean_cmd_table(gvt);
3118 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3122 ret = init_cmd_table(gvt);
3124 intel_gvt_clean_cmd_parser(gvt);