drivers/gpu/drm/i915/gvt/aperture_gm.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Kevin Tian <kevin.tian@intel.com>
  25  *    Dexuan Cui
  26  *
  27  * Contributors:
  28  *    Pei Zhang <pei.zhang@intel.com>
  29  *    Min He <min.he@intel.com>
  30  *    Niu Bing <bing.niu@intel.com>
  31  *    Yulei Zhang <yulei.zhang@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include "i915_drv.h"
  38 #include "gvt.h"
  39
  40 #define MB_TO_BYTES(mb) ((mb) << 20ULL)
  41 #define BYTES_TO_MB(b) ((b) >> 20ULL)
  42
  43 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
  44 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
  45 #define HOST_FENCE 4
  46
  47 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
  48 {
  49         struct intel_gvt *gvt = vgpu->gvt;
  50         struct drm_i915_private *dev_priv = gvt->dev_priv;
  51         u32 alloc_flag, search_flag;
  52         u64 start, end, size;
  53         struct drm_mm_node *node;
  54         int retried = 0;
  55         int ret;
  56
  57         if (high_gm) {
  58                 search_flag = DRM_MM_SEARCH_BELOW;
  59                 alloc_flag = DRM_MM_CREATE_TOP;
  60                 node = &vgpu->gm.high_gm_node;
  61                 size = vgpu_hidden_sz(vgpu);
  62                 start = gvt_hidden_gmadr_base(gvt);
  63                 end = gvt_hidden_gmadr_end(gvt);
  64         } else {
  65                 search_flag = DRM_MM_SEARCH_DEFAULT;
  66                 alloc_flag = DRM_MM_CREATE_DEFAULT;
  67                 node = &vgpu->gm.low_gm_node;
  68                 size = vgpu_aperture_sz(vgpu);
  69                 start = gvt_aperture_gmadr_base(gvt);
  70                 end = gvt_aperture_gmadr_end(gvt);
  71         }
  72
  73         mutex_lock(&dev_priv->drm.struct_mutex);
  74 search_again:
  75         ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm,
  76                                                   node, size, 4096,
  77                                                   I915_COLOR_UNEVICTABLE,
  78                                                   start, end, search_flag,
  79                                                   alloc_flag);
  80         if (ret) {
  81                 ret = i915_gem_evict_something(&dev_priv->ggtt.base,
  82                                                size, 4096,
  83                                                I915_COLOR_UNEVICTABLE,
  84                                                start, end, 0);
  85                 if (ret == 0 && ++retried < 3)
  86                         goto search_again;
  87
  88                 gvt_err("fail to alloc %s gm space from host, retried %d\n",
  89                                 high_gm ? "high" : "low", retried);
  90         }
  91         mutex_unlock(&dev_priv->drm.struct_mutex);
  92         return ret;
  93 }
  94
  95 static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
  96 {
  97         struct intel_gvt *gvt = vgpu->gvt;
  98         struct drm_i915_private *dev_priv = gvt->dev_priv;
  99         int ret;
 100
 101         ret = alloc_gm(vgpu, false);
 102         if (ret)
 103                 return ret;
 104
 105         ret = alloc_gm(vgpu, true);
 106         if (ret)
 107                 goto out_free_aperture;
 108
 109         gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
 110                      vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
 111
 112         gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
 113                      vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
 114
 115         return 0;
 116 out_free_aperture:
 117         mutex_lock(&dev_priv->drm.struct_mutex);
 118         drm_mm_remove_node(&vgpu->gm.low_gm_node);
 119         mutex_unlock(&dev_priv->drm.struct_mutex);
 120         return ret;
 121 }
 122
 123 static void free_vgpu_gm(struct intel_vgpu *vgpu)
 124 {
 125         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 126
 127         mutex_lock(&dev_priv->drm.struct_mutex);
 128         drm_mm_remove_node(&vgpu->gm.low_gm_node);
 129         drm_mm_remove_node(&vgpu->gm.high_gm_node);
 130         mutex_unlock(&dev_priv->drm.struct_mutex);
 131 }
 132
 133 /**
 134  * intel_vgpu_write_fence - write fence registers owned by a vGPU
 135  * @vgpu: vGPU instance
 136  * @fence: vGPU fence register number
 137  * @value: Fence register value to be written
 138  *
 139  * This function is used to write fence registers owned by a vGPU. The vGPU
 140  * fence register number will be translated into HW fence register number.
 141  *
 142  */
 143 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
 144                 u32 fence, u64 value)
 145 {
 146         struct intel_gvt *gvt = vgpu->gvt;
 147         struct drm_i915_private *dev_priv = gvt->dev_priv;
 148         struct drm_i915_fence_reg *reg;
 149         i915_reg_t fence_reg_lo, fence_reg_hi;
 150
 151         assert_rpm_wakelock_held(dev_priv);
 152
 153         if (WARN_ON(fence > vgpu_fence_sz(vgpu)))
 154                 return;
 155
 156         reg = vgpu->fence.regs[fence];
 157         if (WARN_ON(!reg))
 158                 return;
 159
 160         fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
 161         fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
 162
 163         I915_WRITE(fence_reg_lo, 0);
 164         POSTING_READ(fence_reg_lo);
 165
 166         I915_WRITE(fence_reg_hi, upper_32_bits(value));
 167         I915_WRITE(fence_reg_lo, lower_32_bits(value));
 168         POSTING_READ(fence_reg_lo);
 169 }
 170
 171 static void free_vgpu_fence(struct intel_vgpu *vgpu)
 172 {
 173         struct intel_gvt *gvt = vgpu->gvt;
 174         struct drm_i915_private *dev_priv = gvt->dev_priv;
 175         struct drm_i915_fence_reg *reg;
 176         u32 i;
 177
 178         if (WARN_ON(!vgpu_fence_sz(vgpu)))
 179                 return;
 180
 181         intel_runtime_pm_get(dev_priv);
 182
 183         mutex_lock(&dev_priv->drm.struct_mutex);
 184         for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
 185                 reg = vgpu->fence.regs[i];
 186                 intel_vgpu_write_fence(vgpu, i, 0);
 187                 list_add_tail(&reg->link,
 188                               &dev_priv->mm.fence_list);
 189         }
 190         mutex_unlock(&dev_priv->drm.struct_mutex);
 191
 192         intel_runtime_pm_put(dev_priv);
 193 }
 194
 195 static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
 196 {
 197         struct intel_gvt *gvt = vgpu->gvt;
 198         struct drm_i915_private *dev_priv = gvt->dev_priv;
 199         struct drm_i915_fence_reg *reg;
 200         int i;
 201         struct list_head *pos, *q;
 202
 203         intel_runtime_pm_get(dev_priv);
 204
 205         /* Request fences from host */
 206         mutex_lock(&dev_priv->drm.struct_mutex);
 207         i = 0;
 208         list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
 209                 reg = list_entry(pos, struct drm_i915_fence_reg, link);
 210                 if (reg->pin_count || reg->vma)
 211                         continue;
 212                 list_del(pos);
 213                 vgpu->fence.regs[i] = reg;
 214                 intel_vgpu_write_fence(vgpu, i, 0);
 215                 if (++i == vgpu_fence_sz(vgpu))
 216                         break;
 217         }
 218         if (i != vgpu_fence_sz(vgpu))
 219                 goto out_free_fence;
 220
 221         mutex_unlock(&dev_priv->drm.struct_mutex);
 222         intel_runtime_pm_put(dev_priv);
 223         return 0;
 224 out_free_fence:
 225         /* Return fences to host, if fail */
 226         for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
 227                 reg = vgpu->fence.regs[i];
 228                 if (!reg)
 229                         continue;
 230                 list_add_tail(&reg->link,
 231                               &dev_priv->mm.fence_list);
 232         }
 233         mutex_unlock(&dev_priv->drm.struct_mutex);
 234         intel_runtime_pm_put(dev_priv);
 235         return -ENOSPC;
 236 }
 237
 238 static void free_resource(struct intel_vgpu *vgpu)
 239 {
 240         struct intel_gvt *gvt = vgpu->gvt;
 241
 242         gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
 243         gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
 244         gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
 245 }
 246
 247 static int alloc_resource(struct intel_vgpu *vgpu,
 248                 struct intel_vgpu_creation_params *param)
 249 {
 250         struct intel_gvt *gvt = vgpu->gvt;
 251         unsigned long request, avail, max, taken;
 252         const char *item;
 253
 254         if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {
 255                 gvt_err("Invalid vGPU creation params\n");
 256                 return -EINVAL;
 257         }
 258
 259         item = "low GM space";
 260         max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
 261         taken = gvt->gm.vgpu_allocated_low_gm_size;
 262         avail = max - taken;
 263         request = MB_TO_BYTES(param->low_gm_sz);
 264
 265         if (request > avail)
 266                 goto no_enough_resource;
 267
 268         vgpu_aperture_sz(vgpu) = request;
 269
 270         item = "high GM space";
 271         max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
 272         taken = gvt->gm.vgpu_allocated_high_gm_size;
 273         avail = max - taken;
 274         request = MB_TO_BYTES(param->high_gm_sz);
 275
 276         if (request > avail)
 277                 goto no_enough_resource;
 278
 279         vgpu_hidden_sz(vgpu) = request;
 280
 281         item = "fence";
 282         max = gvt_fence_sz(gvt) - HOST_FENCE;
 283         taken = gvt->fence.vgpu_allocated_fence_num;
 284         avail = max - taken;
 285         request = param->fence_sz;
 286
 287         if (request > avail)
 288                 goto no_enough_resource;
 289
 290         vgpu_fence_sz(vgpu) = request;
 291
 292         gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);
 293         gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);
 294         gvt->fence.vgpu_allocated_fence_num += param->fence_sz;
 295         return 0;
 296
 297 no_enough_resource:
 298         gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item);
 299         gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n",
 300                 vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail),
 301                 BYTES_TO_MB(max), BYTES_TO_MB(taken));
 302         return -ENOSPC;
 303 }
 304
 305 /**
 306  * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
 307  * @vgpu: a vGPU
 308  *
 309  * This function is used to free the HW resource owned by a vGPU.
 310  *
 311  */
 312 void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
 313 {
 314         free_vgpu_gm(vgpu);
 315         free_vgpu_fence(vgpu);
 316         free_resource(vgpu);
 317 }
 318
 319 /**
 320  * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
 321  * @vgpu: vGPU
 322  * @param: vGPU creation params
 323  *
 324  * This function is used to allocate HW resource for a vGPU. User specifies
 325  * the resource configuration through the creation params.
 326  *
 327  * Returns:
 328  * zero on success, negative error code if failed.
 329  *
 330  */
 331 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
 332                 struct intel_vgpu_creation_params *param)
 333 {
 334         int ret;
 335
 336         ret = alloc_resource(vgpu, param);
 337         if (ret)
 338                 return ret;
 339
 340         ret = alloc_vgpu_gm(vgpu);
 341         if (ret)
 342                 goto out_free_resource;
 343
 344         ret = alloc_vgpu_fence(vgpu);
 345         if (ret)
 346                 goto out_free_vgpu_gm;
 347
 348         return 0;
 349
 350 out_free_vgpu_gm:
 351         free_vgpu_gm(vgpu);
 352 out_free_resource:
 353         free_resource(vgpu);
 354         return ret;
 355 }