1 // SPDX-License-Identifier: MIT
3 * Copyright © 2016-2019 Intel Corporation
6 #include "gt/intel_gt.h"
7 #include "gt/intel_reset.h"
9 #include "intel_guc_ads.h"
10 #include "intel_guc_submission.h"
11 #include "gt/intel_rps.h"
16 static const struct intel_uc_ops uc_ops_off;
17 static const struct intel_uc_ops uc_ops_on;
19 static void uc_expand_default_options(struct intel_uc *uc)
21 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
23 if (i915->params.enable_guc != -1)
26 /* Don't enable GuC/HuC on pre-Gen12 */
27 if (GRAPHICS_VER(i915) < 12) {
28 i915->params.enable_guc = 0;
32 /* Don't enable GuC/HuC on older Gen12 platforms */
33 if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
34 i915->params.enable_guc = 0;
38 /* Intermediate platforms are HuC authentication only */
39 if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
40 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
44 /* Default: enable HuC authentication and GuC submission */
45 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
48 /* Reset GuC providing us with fresh state for both GuC and HuC.
50 static int __intel_uc_reset_hw(struct intel_uc *uc)
52 struct intel_gt *gt = uc_to_gt(uc);
56 ret = i915_inject_probe_error(gt->i915, -ENXIO);
60 ret = intel_reset_guc(gt);
62 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
66 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
67 WARN(!(guc_status & GS_MIA_IN_RESET),
68 "GuC status: 0x%x, MIA core expected to be in reset\n",
74 static void __confirm_options(struct intel_uc *uc)
76 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
79 "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
80 i915->params.enable_guc,
81 yesno(intel_uc_wants_guc(uc)),
82 yesno(intel_uc_wants_guc_submission(uc)),
83 yesno(intel_uc_wants_huc(uc)),
84 yesno(intel_uc_wants_guc_slpc(uc)));
86 if (i915->params.enable_guc == 0) {
87 GEM_BUG_ON(intel_uc_wants_guc(uc));
88 GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
89 GEM_BUG_ON(intel_uc_wants_huc(uc));
90 GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
94 if (!intel_uc_supports_guc(uc))
96 "Incompatible option enable_guc=%d - %s\n",
97 i915->params.enable_guc, "GuC is not supported!");
99 if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
100 !intel_uc_supports_huc(uc))
102 "Incompatible option enable_guc=%d - %s\n",
103 i915->params.enable_guc, "HuC is not supported!");
105 if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
106 !intel_uc_supports_guc_submission(uc))
108 "Incompatible option enable_guc=%d - %s\n",
109 i915->params.enable_guc, "GuC submission is N/A");
111 if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
113 "Incompatible option enable_guc=%d - %s\n",
114 i915->params.enable_guc, "undocumented flag");
117 void intel_uc_init_early(struct intel_uc *uc)
119 uc_expand_default_options(uc);
121 intel_guc_init_early(&uc->guc);
122 intel_huc_init_early(&uc->huc);
124 __confirm_options(uc);
126 if (intel_uc_wants_guc(uc))
127 uc->ops = &uc_ops_on;
129 uc->ops = &uc_ops_off;
132 void intel_uc_init_late(struct intel_uc *uc)
134 intel_guc_init_late(&uc->guc);
137 void intel_uc_driver_late_release(struct intel_uc *uc)
142 * intel_uc_init_mmio - setup uC MMIO access
143 * @uc: the intel_uc structure
145 * Setup minimal state necessary for MMIO accesses later in the
146 * initialization sequence.
148 void intel_uc_init_mmio(struct intel_uc *uc)
150 intel_guc_init_send_regs(&uc->guc);
153 static void __uc_capture_load_err_log(struct intel_uc *uc)
155 struct intel_guc *guc = &uc->guc;
157 if (guc->log.vma && !uc->load_err_log)
158 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
161 static void __uc_free_load_err_log(struct intel_uc *uc)
163 struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
166 i915_gem_object_put(log);
169 void intel_uc_driver_remove(struct intel_uc *uc)
171 intel_uc_fini_hw(uc);
173 __uc_free_load_err_log(uc);
177 * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
178 * register using the same bits used in the CT message payload. Since our
179 * communication channel with guc is turned off at this point, we can save the
180 * message and handle it after we turn it back on.
182 static void guc_clear_mmio_msg(struct intel_guc *guc)
184 intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
187 static void guc_get_mmio_msg(struct intel_guc *guc)
191 spin_lock_irq(&guc->irq_lock);
193 val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
194 guc->mmio_msg |= val & guc->msg_enabled_mask;
197 * clear all events, including the ones we're not currently servicing,
198 * to make sure we don't try to process a stale message if we enable
199 * handling of more events later.
201 guc_clear_mmio_msg(guc);
203 spin_unlock_irq(&guc->irq_lock);
206 static void guc_handle_mmio_msg(struct intel_guc *guc)
208 /* we need communication to be enabled to reply to GuC */
209 GEM_BUG_ON(!intel_guc_ct_enabled(&guc->ct));
211 spin_lock_irq(&guc->irq_lock);
213 intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
216 spin_unlock_irq(&guc->irq_lock);
219 static int guc_enable_communication(struct intel_guc *guc)
221 struct intel_gt *gt = guc_to_gt(guc);
222 struct drm_i915_private *i915 = gt->i915;
225 GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct));
227 ret = i915_inject_probe_error(i915, -ENXIO);
231 ret = intel_guc_ct_enable(&guc->ct);
235 /* check for mmio messages received before/during the CT enable */
236 guc_get_mmio_msg(guc);
237 guc_handle_mmio_msg(guc);
239 intel_guc_enable_interrupts(guc);
241 /* check for CT messages received before we enabled interrupts */
242 spin_lock_irq(>->irq_lock);
243 intel_guc_ct_event_handler(&guc->ct);
244 spin_unlock_irq(>->irq_lock);
246 drm_dbg(&i915->drm, "GuC communication enabled\n");
251 static void guc_disable_communication(struct intel_guc *guc)
253 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
256 * Events generated during or after CT disable are logged by guc in
257 * via mmio. Make sure the register is clear before disabling CT since
258 * all events we cared about have already been processed via CT.
260 guc_clear_mmio_msg(guc);
262 intel_guc_disable_interrupts(guc);
264 intel_guc_ct_disable(&guc->ct);
267 * Check for messages received during/after the CT disable. We do not
268 * expect any messages to have arrived via CT between the interrupt
269 * disable and the CT disable because GuC should've been idle until we
270 * triggered the CT disable protocol.
272 guc_get_mmio_msg(guc);
274 drm_dbg(&i915->drm, "GuC communication disabled\n");
277 static void __uc_fetch_firmwares(struct intel_uc *uc)
281 GEM_BUG_ON(!intel_uc_wants_guc(uc));
283 err = intel_uc_fw_fetch(&uc->guc.fw);
285 /* Make sure we transition out of transient "SELECTED" state */
286 if (intel_uc_wants_huc(uc)) {
287 drm_dbg(&uc_to_gt(uc)->i915->drm,
288 "Failed to fetch GuC: %d disabling HuC\n", err);
289 intel_uc_fw_change_status(&uc->huc.fw,
290 INTEL_UC_FIRMWARE_ERROR);
296 if (intel_uc_wants_huc(uc))
297 intel_uc_fw_fetch(&uc->huc.fw);
300 static void __uc_cleanup_firmwares(struct intel_uc *uc)
302 intel_uc_fw_cleanup_fetch(&uc->huc.fw);
303 intel_uc_fw_cleanup_fetch(&uc->guc.fw);
306 static int __uc_init(struct intel_uc *uc)
308 struct intel_guc *guc = &uc->guc;
309 struct intel_huc *huc = &uc->huc;
312 GEM_BUG_ON(!intel_uc_wants_guc(uc));
314 if (!intel_uc_uses_guc(uc))
317 if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
320 ret = intel_guc_init(guc);
324 if (intel_uc_uses_huc(uc)) {
325 ret = intel_huc_init(huc);
337 static void __uc_fini(struct intel_uc *uc)
339 intel_huc_fini(&uc->huc);
340 intel_guc_fini(&uc->guc);
343 static int __uc_sanitize(struct intel_uc *uc)
345 struct intel_guc *guc = &uc->guc;
346 struct intel_huc *huc = &uc->huc;
348 GEM_BUG_ON(!intel_uc_supports_guc(uc));
350 intel_huc_sanitize(huc);
351 intel_guc_sanitize(guc);
353 return __intel_uc_reset_hw(uc);
356 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
357 static int uc_init_wopcm(struct intel_uc *uc)
359 struct intel_gt *gt = uc_to_gt(uc);
360 struct intel_uncore *uncore = gt->uncore;
361 u32 base = intel_wopcm_guc_base(>->i915->wopcm);
362 u32 size = intel_wopcm_guc_size(>->i915->wopcm);
363 u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
367 if (unlikely(!base || !size)) {
368 i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
372 GEM_BUG_ON(!intel_uc_supports_guc(uc));
373 GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
374 GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
375 GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
376 GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
378 err = i915_inject_probe_error(gt->i915, -ENXIO);
382 mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
383 err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
384 size | GUC_WOPCM_SIZE_LOCKED);
388 mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
389 err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
390 base | huc_agent, mask,
392 GUC_WOPCM_OFFSET_VALID);
399 i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
400 i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
401 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
402 intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
403 i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
404 i915_mmio_reg_offset(GUC_WOPCM_SIZE),
405 intel_uncore_read(uncore, GUC_WOPCM_SIZE));
410 static bool uc_is_wopcm_locked(struct intel_uc *uc)
412 struct intel_gt *gt = uc_to_gt(uc);
413 struct intel_uncore *uncore = gt->uncore;
415 return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
416 (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
419 static int __uc_check_hw(struct intel_uc *uc)
421 if (!intel_uc_supports_guc(uc))
425 * We can silently continue without GuC only if it was never enabled
426 * before on this system after reboot, otherwise we risk GPU hangs.
427 * To check if GuC was loaded before we look at WOPCM registers.
429 if (uc_is_wopcm_locked(uc))
435 static void print_fw_ver(struct intel_uc *uc, struct intel_uc_fw *fw)
437 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
439 drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
440 intel_uc_fw_type_repr(fw->type), fw->path,
441 fw->major_ver_found, fw->minor_ver_found);
444 static int __uc_init_hw(struct intel_uc *uc)
446 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
447 struct intel_guc *guc = &uc->guc;
448 struct intel_huc *huc = &uc->huc;
451 GEM_BUG_ON(!intel_uc_supports_guc(uc));
452 GEM_BUG_ON(!intel_uc_wants_guc(uc));
454 print_fw_ver(uc, &guc->fw);
456 if (intel_uc_uses_huc(uc))
457 print_fw_ver(uc, &huc->fw);
459 if (!intel_uc_fw_is_loadable(&guc->fw)) {
460 ret = __uc_check_hw(uc) ||
461 intel_uc_fw_is_overridden(&guc->fw) ||
462 intel_uc_wants_guc_submission(uc) ?
463 intel_uc_fw_status_to_error(guc->fw.status) : 0;
467 ret = uc_init_wopcm(uc);
471 intel_guc_reset_interrupts(guc);
473 /* WaEnableuKernelHeaderValidFix:skl */
474 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
475 if (GRAPHICS_VER(i915) == 9)
480 intel_rps_raise_unslice(&uc_to_gt(uc)->rps);
484 * Always reset the GuC just before (re)loading, so
485 * that the state and timing are fairly predictable
487 ret = __uc_sanitize(uc);
491 intel_huc_fw_upload(huc);
492 intel_guc_ads_reset(guc);
493 intel_guc_write_params(guc);
494 ret = intel_guc_fw_upload(guc);
498 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
499 "retry %d more time(s)\n", ret, attempts);
502 /* Did we succeded or run out of retries? */
504 goto err_log_capture;
506 ret = guc_enable_communication(guc);
508 goto err_log_capture;
512 if (intel_uc_uses_guc_submission(uc))
513 intel_guc_submission_enable(guc);
515 if (intel_uc_uses_guc_slpc(uc)) {
516 ret = intel_guc_slpc_enable(&guc->slpc);
520 /* Restore GT back to RPn for non-SLPC path */
521 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
524 drm_info(&i915->drm, "GuC submission %s\n",
525 enableddisabled(intel_uc_uses_guc_submission(uc)));
526 drm_info(&i915->drm, "GuC SLPC %s\n",
527 enableddisabled(intel_uc_uses_guc_slpc(uc)));
532 * We've failed to load the firmware :(
535 intel_guc_submission_disable(guc);
537 __uc_capture_load_err_log(uc);
539 /* Return GT back to RPn */
540 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
545 drm_notice(&i915->drm, "GuC is uninitialized\n");
546 /* We want to run without GuC submission */
550 i915_probe_error(i915, "GuC initialization failed %d\n", ret);
552 /* We want to keep KMS alive */
556 static void __uc_fini_hw(struct intel_uc *uc)
558 struct intel_guc *guc = &uc->guc;
560 if (!intel_guc_is_fw_running(guc))
563 if (intel_uc_uses_guc_submission(uc))
564 intel_guc_submission_disable(guc);
570 * intel_uc_reset_prepare - Prepare for reset
571 * @uc: the intel_uc structure
573 * Preparing for full gpu reset.
575 void intel_uc_reset_prepare(struct intel_uc *uc)
577 struct intel_guc *guc = &uc->guc;
579 uc->reset_in_progress = true;
581 /* Nothing to do if GuC isn't supported */
582 if (!intel_uc_supports_guc(uc))
585 /* Firmware expected to be running when this function is called */
586 if (!intel_guc_is_ready(guc))
589 if (intel_uc_uses_guc_submission(uc))
590 intel_guc_submission_reset_prepare(guc);
596 void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled)
598 struct intel_guc *guc = &uc->guc;
600 /* Firmware can not be running when this function is called */
601 if (intel_uc_uses_guc_submission(uc))
602 intel_guc_submission_reset(guc, stalled);
605 void intel_uc_reset_finish(struct intel_uc *uc)
607 struct intel_guc *guc = &uc->guc;
609 uc->reset_in_progress = false;
611 /* Firmware expected to be running when this function is called */
612 if (intel_guc_is_fw_running(guc) && intel_uc_uses_guc_submission(uc))
613 intel_guc_submission_reset_finish(guc);
616 void intel_uc_cancel_requests(struct intel_uc *uc)
618 struct intel_guc *guc = &uc->guc;
620 /* Firmware can not be running when this function is called */
621 if (intel_uc_uses_guc_submission(uc))
622 intel_guc_submission_cancel_requests(guc);
625 void intel_uc_runtime_suspend(struct intel_uc *uc)
627 struct intel_guc *guc = &uc->guc;
629 if (!intel_guc_is_ready(guc))
633 * Wait for any outstanding CTB before tearing down communication /w the
636 #define OUTSTANDING_CTB_TIMEOUT_PERIOD (HZ / 5)
637 intel_guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
638 false, OUTSTANDING_CTB_TIMEOUT_PERIOD);
639 GEM_WARN_ON(atomic_read(&guc->outstanding_submission_g2h));
641 guc_disable_communication(guc);
644 void intel_uc_suspend(struct intel_uc *uc)
646 struct intel_guc *guc = &uc->guc;
647 intel_wakeref_t wakeref;
650 if (!intel_guc_is_ready(guc))
653 with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
654 err = intel_guc_suspend(guc);
656 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
660 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
662 struct intel_guc *guc = &uc->guc;
663 struct intel_gt *gt = guc_to_gt(guc);
666 if (!intel_guc_is_fw_running(guc))
669 /* Make sure we enable communication if and only if it's disabled */
670 GEM_BUG_ON(enable_communication == intel_guc_ct_enabled(&guc->ct));
672 if (enable_communication)
673 guc_enable_communication(guc);
675 /* If we are only resuming GuC communication but not reloading
676 * GuC, we need to ensure the ARAT timer interrupt is enabled
677 * again. In case of GuC reload, it is enabled during SLPC enable.
679 if (enable_communication && intel_uc_uses_guc_slpc(uc))
680 intel_guc_pm_intrmsk_enable(gt);
682 err = intel_guc_resume(guc);
684 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
691 int intel_uc_resume(struct intel_uc *uc)
694 * When coming out of S3/S4 we sanitize and re-init the HW, so
695 * communication is already re-enabled at this point.
697 return __uc_resume(uc, false);
700 int intel_uc_runtime_resume(struct intel_uc *uc)
703 * During runtime resume we don't sanitize, so we need to re-init
704 * communication as well.
706 return __uc_resume(uc, true);
709 static const struct intel_uc_ops uc_ops_off = {
710 .init_hw = __uc_check_hw,
713 static const struct intel_uc_ops uc_ops_on = {
714 .sanitize = __uc_sanitize,
716 .init_fw = __uc_fetch_firmwares,
717 .fini_fw = __uc_cleanup_firmwares,
722 .init_hw = __uc_init_hw,
723 .fini_hw = __uc_fini_hw,