drivers/gpu/drm/i915/gt/selftest_mocs.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #include "gt/intel_engine_pm.h"
   8 #include "i915_selftest.h"
   9
  10 #include "gem/selftests/mock_context.h"
  11 #include "selftests/igt_reset.h"
  12 #include "selftests/igt_spinner.h"
  13
  14 struct live_mocs {
  15         struct drm_i915_mocs_table table;
  16         struct i915_vma *scratch;
  17         void *vaddr;
  18 };
  19
  20 static int request_add_sync(struct i915_request *rq, int err)
  21 {
  22         i915_request_get(rq);
  23         i915_request_add(rq);
  24         if (i915_request_wait(rq, 0, HZ / 5) < 0)
  25                 err = -ETIME;
  26         i915_request_put(rq);
  27
  28         return err;
  29 }
  30
  31 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
  32 {
  33         int err = 0;
  34
  35         i915_request_get(rq);
  36         i915_request_add(rq);
  37         if (spin && !igt_wait_for_spinner(spin, rq))
  38                 err = -ETIME;
  39         i915_request_put(rq);
  40
  41         return err;
  42 }
  43
  44 static struct i915_vma *create_scratch(struct intel_gt *gt)
  45 {
  46         struct drm_i915_gem_object *obj;
  47         struct i915_vma *vma;
  48         int err;
  49
  50         obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
  51         if (IS_ERR(obj))
  52                 return ERR_CAST(obj);
  53
  54         i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
  55
  56         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
  57         if (IS_ERR(vma)) {
  58                 i915_gem_object_put(obj);
  59                 return vma;
  60         }
  61
  62         err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
  63         if (err) {
  64                 i915_gem_object_put(obj);
  65                 return ERR_PTR(err);
  66         }
  67
  68         return vma;
  69 }
  70
  71 static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
  72 {
  73         int err;
  74
  75         if (!get_mocs_settings(gt->i915, &arg->table))
  76                 return -EINVAL;
  77
  78         arg->scratch = create_scratch(gt);
  79         if (IS_ERR(arg->scratch))
  80                 return PTR_ERR(arg->scratch);
  81
  82         arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
  83         if (IS_ERR(arg->vaddr)) {
  84                 err = PTR_ERR(arg->vaddr);
  85                 goto err_scratch;
  86         }
  87
  88         return 0;
  89
  90 err_scratch:
  91         i915_vma_unpin_and_release(&arg->scratch, 0);
  92         return err;
  93 }
  94
  95 static void live_mocs_fini(struct live_mocs *arg)
  96 {
  97         i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
  98 }
  99
 100 static int read_regs(struct i915_request *rq,
 101                      u32 addr, unsigned int count,
 102                      uint32_t *offset)
 103 {
 104         unsigned int i;
 105         u32 *cs;
 106
 107         GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
 108
 109         cs = intel_ring_begin(rq, 4 * count);
 110         if (IS_ERR(cs))
 111                 return PTR_ERR(cs);
 112
 113         for (i = 0; i < count; i++) {
 114                 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
 115                 *cs++ = addr;
 116                 *cs++ = *offset;
 117                 *cs++ = 0;
 118
 119                 addr += sizeof(u32);
 120                 *offset += sizeof(u32);
 121         }
 122
 123         intel_ring_advance(rq, cs);
 124
 125         return 0;
 126 }
 127
 128 static int read_mocs_table(struct i915_request *rq,
 129                            const struct drm_i915_mocs_table *table,
 130                            uint32_t *offset)
 131 {
 132         u32 addr;
 133
 134         if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
 135                 addr = global_mocs_offset();
 136         else
 137                 addr = mocs_offset(rq->engine);
 138
 139         return read_regs(rq, addr, table->n_entries, offset);
 140 }
 141
 142 static int read_l3cc_table(struct i915_request *rq,
 143                            const struct drm_i915_mocs_table *table,
 144                            uint32_t *offset)
 145 {
 146         u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
 147
 148         return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
 149 }
 150
 151 static int check_mocs_table(struct intel_engine_cs *engine,
 152                             const struct drm_i915_mocs_table *table,
 153                             uint32_t **vaddr)
 154 {
 155         unsigned int i;
 156         u32 expect;
 157
 158         for_each_mocs(expect, table, i) {
 159                 if (**vaddr != expect) {
 160                         pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
 161                                engine->name, i, **vaddr, expect);
 162                         return -EINVAL;
 163                 }
 164                 ++*vaddr;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 171 {
 172         /*
 173          * Registers in this range are affected by the MCR selector
 174          * which only controls CPU initiated MMIO. Routing does not
 175          * work for CS access so we cannot verify them on this path.
 176          */
 177         return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
 178 }
 179
 180 static int check_l3cc_table(struct intel_engine_cs *engine,
 181                             const struct drm_i915_mocs_table *table,
 182                             uint32_t **vaddr)
 183 {
 184         /* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
 185         u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
 186         unsigned int i;
 187         u32 expect;
 188
 189         for_each_l3cc(expect, table, i) {
 190                 if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
 191                         pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
 192                                engine->name, i, **vaddr, expect);
 193                         return -EINVAL;
 194                 }
 195                 ++*vaddr;
 196                 reg += 4;
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int check_mocs_engine(struct live_mocs *arg,
 203                              struct intel_context *ce)
 204 {
 205         struct i915_vma *vma = arg->scratch;
 206         struct i915_request *rq;
 207         u32 offset;
 208         u32 *vaddr;
 209         int err;
 210
 211         memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
 212
 213         rq = intel_context_create_request(ce);
 214         if (IS_ERR(rq))
 215                 return PTR_ERR(rq);
 216
 217         i915_vma_lock(vma);
 218         err = i915_request_await_object(rq, vma->obj, true);
 219         if (!err)
 220                 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
 221         i915_vma_unlock(vma);
 222
 223         /* Read the mocs tables back using SRM */
 224         offset = i915_ggtt_offset(vma);
 225         if (!err)
 226                 err = read_mocs_table(rq, &arg->table, &offset);
 227         if (!err && ce->engine->class == RENDER_CLASS)
 228                 err = read_l3cc_table(rq, &arg->table, &offset);
 229         offset -= i915_ggtt_offset(vma);
 230         GEM_BUG_ON(offset > PAGE_SIZE);
 231
 232         err = request_add_sync(rq, err);
 233         if (err)
 234                 return err;
 235
 236         /* Compare the results against the expected tables */
 237         vaddr = arg->vaddr;
 238         if (!err)
 239                 err = check_mocs_table(ce->engine, &arg->table, &vaddr);
 240         if (!err && ce->engine->class == RENDER_CLASS)
 241                 err = check_l3cc_table(ce->engine, &arg->table, &vaddr);
 242         if (err)
 243                 return err;
 244
 245         GEM_BUG_ON(arg->vaddr + offset != vaddr);
 246         return 0;
 247 }
 248
 249 static int live_mocs_kernel(void *arg)
 250 {
 251         struct intel_gt *gt = arg;
 252         struct intel_engine_cs *engine;
 253         enum intel_engine_id id;
 254         struct live_mocs mocs;
 255         int err;
 256
 257         /* Basic check the system is configured with the expected mocs table */
 258
 259         err = live_mocs_init(&mocs, gt);
 260         if (err)
 261                 return err;
 262
 263         for_each_engine(engine, gt, id) {
 264                 intel_engine_pm_get(engine);
 265                 err = check_mocs_engine(&mocs, engine->kernel_context);
 266                 intel_engine_pm_put(engine);
 267                 if (err)
 268                         break;
 269         }
 270
 271         live_mocs_fini(&mocs);
 272         return err;
 273 }
 274
 275 static int live_mocs_clean(void *arg)
 276 {
 277         struct intel_gt *gt = arg;
 278         struct intel_engine_cs *engine;
 279         enum intel_engine_id id;
 280         struct live_mocs mocs;
 281         int err;
 282
 283         /* Every new context should see the same mocs table */
 284
 285         err = live_mocs_init(&mocs, gt);
 286         if (err)
 287                 return err;
 288
 289         for_each_engine(engine, gt, id) {
 290                 struct intel_context *ce;
 291
 292                 ce = intel_context_create(engine->kernel_context->gem_context,
 293                                           engine);
 294                 if (IS_ERR(ce)) {
 295                         err = PTR_ERR(ce);
 296                         break;
 297                 }
 298
 299                 err = check_mocs_engine(&mocs, ce);
 300                 intel_context_put(ce);
 301                 if (err)
 302                         break;
 303         }
 304
 305         live_mocs_fini(&mocs);
 306         return err;
 307 }
 308
 309 static int active_engine_reset(struct intel_context *ce,
 310                                const char *reason)
 311 {
 312         struct igt_spinner spin;
 313         struct i915_request *rq;
 314         int err;
 315
 316         err = igt_spinner_init(&spin, ce->engine->gt);
 317         if (err)
 318                 return err;
 319
 320         rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
 321         if (IS_ERR(rq)) {
 322                 igt_spinner_fini(&spin);
 323                 return PTR_ERR(rq);
 324         }
 325
 326         err = request_add_spin(rq, &spin);
 327         if (err == 0)
 328                 err = intel_engine_reset(ce->engine, reason);
 329
 330         igt_spinner_end(&spin);
 331         igt_spinner_fini(&spin);
 332
 333         return err;
 334 }
 335
 336 static int __live_mocs_reset(struct live_mocs *mocs,
 337                              struct intel_context *ce)
 338 {
 339         int err;
 340
 341         err = intel_engine_reset(ce->engine, "mocs");
 342         if (err)
 343                 return err;
 344
 345         err = check_mocs_engine(mocs, ce);
 346         if (err)
 347                 return err;
 348
 349         err = active_engine_reset(ce, "mocs");
 350         if (err)
 351                 return err;
 352
 353         err = check_mocs_engine(mocs, ce);
 354         if (err)
 355                 return err;
 356
 357         intel_gt_reset(ce->engine->gt, ce->engine->mask, "mocs");
 358
 359         err = check_mocs_engine(mocs, ce);
 360         if (err)
 361                 return err;
 362
 363         return 0;
 364 }
 365
 366 static int live_mocs_reset(void *arg)
 367 {
 368         struct intel_gt *gt = arg;
 369         struct intel_engine_cs *engine;
 370         enum intel_engine_id id;
 371         struct live_mocs mocs;
 372         int err = 0;
 373
 374         /* Check the mocs setup is retained over per-engine and global resets */
 375
 376         if (!intel_has_reset_engine(gt))
 377                 return 0;
 378
 379         err = live_mocs_init(&mocs, gt);
 380         if (err)
 381                 return err;
 382
 383         igt_global_reset_lock(gt);
 384         for_each_engine(engine, gt, id) {
 385                 struct intel_context *ce;
 386
 387                 ce = intel_context_create(engine->kernel_context->gem_context,
 388                                           engine);
 389                 if (IS_ERR(ce)) {
 390                         err = PTR_ERR(ce);
 391                         break;
 392                 }
 393
 394                 intel_engine_pm_get(engine);
 395                 err = __live_mocs_reset(&mocs, ce);
 396                 intel_engine_pm_put(engine);
 397
 398                 intel_context_put(ce);
 399                 if (err)
 400                         break;
 401         }
 402         igt_global_reset_unlock(gt);
 403
 404         live_mocs_fini(&mocs);
 405         return err;
 406 }
 407
 408 int intel_mocs_live_selftests(struct drm_i915_private *i915)
 409 {
 410         static const struct i915_subtest tests[] = {
 411                 SUBTEST(live_mocs_kernel),
 412                 SUBTEST(live_mocs_clean),
 413                 SUBTEST(live_mocs_reset),
 414         };
 415         struct drm_i915_mocs_table table;
 416
 417         if (!get_mocs_settings(i915, &table))
 418                 return 0;
 419
 420         return intel_gt_live_subtests(tests, &i915->gt);
 421 }