drivers/gpu/drm/i915/gt/intel_workarounds.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2014-2018 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "i915_reg.h"
   8 #include "intel_context.h"
   9 #include "intel_engine_pm.h"
  10 #include "intel_engine_regs.h"
  11 #include "intel_gpu_commands.h"
  12 #include "intel_gt.h"
  13 #include "intel_gt_mcr.h"
  14 #include "intel_gt_print.h"
  15 #include "intel_gt_regs.h"
  16 #include "intel_ring.h"
  17 #include "intel_workarounds.h"
  18
  19 /**
  20  * DOC: Hardware workarounds
  21  *
  22  * Hardware workarounds are register programming documented to be executed in
  23  * the driver that fall outside of the normal programming sequences for a
  24  * platform. There are some basic categories of workarounds, depending on
  25  * how/when they are applied:
  26  *
  27  * - Context workarounds: workarounds that touch registers that are
  28  *   saved/restored to/from the HW context image. The list is emitted (via Load
  29  *   Register Immediate commands) once when initializing the device and saved in
  30  *   the default context. That default context is then used on every context
  31  *   creation to have a "primed golden context", i.e. a context image that
  32  *   already contains the changes needed to all the registers.
  33  *
  34  *   Context workarounds should be implemented in the \*_ctx_workarounds_init()
  35  *   variants respective to the targeted platforms.
  36  *
  37  * - Engine workarounds: the list of these WAs is applied whenever the specific
  38  *   engine is reset. It's also possible that a set of engine classes share a
  39  *   common power domain and they are reset together. This happens on some
  40  *   platforms with render and compute engines. In this case (at least) one of
  41  *   them need to keeep the workaround programming: the approach taken in the
  42  *   driver is to tie those workarounds to the first compute/render engine that
  43  *   is registered.  When executing with GuC submission, engine resets are
  44  *   outside of kernel driver control, hence the list of registers involved in
  45  *   written once, on engine initialization, and then passed to GuC, that
  46  *   saves/restores their values before/after the reset takes place. See
  47  *   ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference.
  48  *
  49  *   Workarounds for registers specific to RCS and CCS should be implemented in
  50  *   rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for
  51  *   registers belonging to BCS, VCS or VECS should be implemented in
  52  *   xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
  53  *   engine's MMIO range but that are part of of the common RCS/CCS reset domain
  54  *   should be implemented in general_render_compute_wa_init().
  55  *
  56  * - GT workarounds: the list of these WAs is applied whenever these registers
  57  *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
  58  *
  59  *   GT workarounds should be implemented in the \*_gt_workarounds_init()
  60  *   variants respective to the targeted platforms.
  61  *
  62  * - Register whitelist: some workarounds need to be implemented in userspace,
  63  *   but need to touch privileged registers. The whitelist in the kernel
  64  *   instructs the hardware to allow the access to happen. From the kernel side,
  65  *   this is just a special case of a MMIO workaround (as we write the list of
  66  *   these to/be-whitelisted registers to some special HW registers).
  67  *
  68  *   Register whitelisting should be done in the \*_whitelist_build() variants
  69  *   respective to the targeted platforms.
  70  *
  71  * - Workaround batchbuffers: buffers that get executed automatically by the
  72  *   hardware on every HW context restore. These buffers are created and
  73  *   programmed in the default context so the hardware always go through those
  74  *   programming sequences when switching contexts. The support for workaround
  75  *   batchbuffers is enabled these hardware mechanisms:
  76  *
  77  *   #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
  78  *      context, pointing the hardware to jump to that location when that offset
  79  *      is reached in the context restore. Workaround batchbuffer in the driver
  80  *      currently uses this mechanism for all platforms.
  81  *
  82  *   #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
  83  *      pointing the hardware to a buffer to continue executing after the
  84  *      engine registers are restored in a context restore sequence. This is
  85  *      currently not used in the driver.
  86  *
  87  * - Other:  There are WAs that, due to their nature, cannot be applied from a
  88  *   central place. Those are peppered around the rest of the code, as needed.
  89  *   Workarounds related to the display IP are the main example.
  90  *
  91  * .. [1] Technically, some registers are powercontext saved & restored, so they
  92  *    survive a suspend/resume. In practice, writing them again is not too
  93  *    costly and simplifies things, so it's the approach taken in the driver.
  94  */
  95
  96 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt,
  97                           const char *name, const char *engine_name)
  98 {
  99         wal->gt = gt;
 100         wal->name = name;
 101         wal->engine_name = engine_name;
 102 }
 103
 104 #define WA_LIST_CHUNK (1 << 4)
 105
 106 static void wa_init_finish(struct i915_wa_list *wal)
 107 {
 108         /* Trim unused entries. */
 109         if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
 110                 struct i915_wa *list = kmemdup(wal->list,
 111                                                wal->count * sizeof(*list),
 112                                                GFP_KERNEL);
 113
 114                 if (list) {
 115                         kfree(wal->list);
 116                         wal->list = list;
 117                 }
 118         }
 119
 120         if (!wal->count)
 121                 return;
 122
 123         gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n",
 124                wal->wa_count, wal->name, wal->engine_name);
 125 }
 126
 127 static enum forcewake_domains
 128 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 129 {
 130         enum forcewake_domains fw = 0;
 131         struct i915_wa *wa;
 132         unsigned int i;
 133
 134         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
 135                 fw |= intel_uncore_forcewake_for_reg(uncore,
 136                                                      wa->reg,
 137                                                      FW_REG_READ |
 138                                                      FW_REG_WRITE);
 139
 140         return fw;
 141 }
 142
 143 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 144 {
 145         unsigned int addr = i915_mmio_reg_offset(wa->reg);
 146         struct drm_i915_private *i915 = wal->gt->i915;
 147         unsigned int start = 0, end = wal->count;
 148         const unsigned int grow = WA_LIST_CHUNK;
 149         struct i915_wa *wa_;
 150
 151         GEM_BUG_ON(!is_power_of_2(grow));
 152
 153         if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
 154                 struct i915_wa *list;
 155
 156                 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
 157                                      GFP_KERNEL);
 158                 if (!list) {
 159                         drm_err(&i915->drm, "No space for workaround init!\n");
 160                         return;
 161                 }
 162
 163                 if (wal->list) {
 164                         memcpy(list, wal->list, sizeof(*wa) * wal->count);
 165                         kfree(wal->list);
 166                 }
 167
 168                 wal->list = list;
 169         }
 170
 171         while (start < end) {
 172                 unsigned int mid = start + (end - start) / 2;
 173
 174                 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
 175                         start = mid + 1;
 176                 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
 177                         end = mid;
 178                 } else {
 179                         wa_ = &wal->list[mid];
 180
 181                         if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
 182                                 drm_err(&i915->drm,
 183                                         "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
 184                                         i915_mmio_reg_offset(wa_->reg),
 185                                         wa_->clr, wa_->set);
 186
 187                                 wa_->set &= ~wa->clr;
 188                         }
 189
 190                         wal->wa_count++;
 191                         wa_->set |= wa->set;
 192                         wa_->clr |= wa->clr;
 193                         wa_->read |= wa->read;
 194                         return;
 195                 }
 196         }
 197
 198         wal->wa_count++;
 199         wa_ = &wal->list[wal->count++];
 200         *wa_ = *wa;
 201
 202         while (wa_-- > wal->list) {
 203                 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
 204                            i915_mmio_reg_offset(wa_[1].reg));
 205                 if (i915_mmio_reg_offset(wa_[1].reg) >
 206                     i915_mmio_reg_offset(wa_[0].reg))
 207                         break;
 208
 209                 swap(wa_[1], wa_[0]);
 210         }
 211 }
 212
 213 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
 214                    u32 clear, u32 set, u32 read_mask, bool masked_reg)
 215 {
 216         struct i915_wa wa = {
 217                 .reg  = reg,
 218                 .clr  = clear,
 219                 .set  = set,
 220                 .read = read_mask,
 221                 .masked_reg = masked_reg,
 222         };
 223
 224         _wa_add(wal, &wa);
 225 }
 226
 227 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
 228                        u32 clear, u32 set, u32 read_mask, bool masked_reg)
 229 {
 230         struct i915_wa wa = {
 231                 .mcr_reg = reg,
 232                 .clr  = clear,
 233                 .set  = set,
 234                 .read = read_mask,
 235                 .masked_reg = masked_reg,
 236                 .is_mcr = 1,
 237         };
 238
 239         _wa_add(wal, &wa);
 240 }
 241
 242 static void
 243 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 244 {
 245         wa_add(wal, reg, clear, set, clear | set, false);
 246 }
 247
 248 static void
 249 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
 250 {
 251         wa_mcr_add(wal, reg, clear, set, clear | set, false);
 252 }
 253
 254 static void
 255 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 256 {
 257         wa_write_clr_set(wal, reg, ~0, set);
 258 }
 259
 260 static void
 261 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
 262 {
 263         wa_mcr_write_clr_set(wal, reg, ~0, set);
 264 }
 265
 266 static void
 267 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 268 {
 269         wa_write_clr_set(wal, reg, set, set);
 270 }
 271
 272 static void
 273 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
 274 {
 275         wa_mcr_write_clr_set(wal, reg, set, set);
 276 }
 277
 278 static void
 279 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
 280 {
 281         wa_write_clr_set(wal, reg, clr, 0);
 282 }
 283
 284 static void
 285 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
 286 {
 287         wa_mcr_write_clr_set(wal, reg, clr, 0);
 288 }
 289
 290 /*
 291  * WA operations on "masked register". A masked register has the upper 16 bits
 292  * documented as "masked" in b-spec. Its purpose is to allow writing to just a
 293  * portion of the register without a rmw: you simply write in the upper 16 bits
 294  * the mask of bits you are going to modify.
 295  *
 296  * The wa_masked_* family of functions already does the necessary operations to
 297  * calculate the mask based on the parameters passed, so user only has to
 298  * provide the lower 16 bits of that register.
 299  */
 300
 301 static void
 302 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 303 {
 304         wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
 305 }
 306
 307 static void
 308 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
 309 {
 310         wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
 311 }
 312
 313 static void
 314 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 315 {
 316         wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
 317 }
 318
 319 static void
 320 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
 321 {
 322         wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
 323 }
 324
 325 static void
 326 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
 327                     u32 mask, u32 val)
 328 {
 329         wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
 330 }
 331
 332 static void
 333 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
 334                         u32 mask, u32 val)
 335 {
 336         wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
 337 }
 338
 339 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
 340                                       struct i915_wa_list *wal)
 341 {
 342         wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 343 }
 344
 345 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine,
 346                                       struct i915_wa_list *wal)
 347 {
 348         wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 349 }
 350
 351 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
 352                                       struct i915_wa_list *wal)
 353 {
 354         wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 355
 356         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 357         wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
 358
 359         /* WaDisablePartialInstShootdown:bdw,chv */
 360         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 361                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 362
 363         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 364          * workaround for a possible hang in the unlikely event a TLB
 365          * invalidation occurs during a PSD flush.
 366          */
 367         /* WaForceEnableNonCoherent:bdw,chv */
 368         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 369         wa_masked_en(wal, HDC_CHICKEN0,
 370                      HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 371                      HDC_FORCE_NON_COHERENT);
 372
 373         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 374          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 375          *  polygons in the same 8x4 pixel/sample area to be processed without
 376          *  stalling waiting for the earlier ones to write to Hierarchical Z
 377          *  buffer."
 378          *
 379          * This optimization is off by default for BDW and CHV; turn it on.
 380          */
 381         wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 382
 383         /* Wa4x4STCOptimizationDisable:bdw,chv */
 384         wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 385
 386         /*
 387          * BSpec recommends 8x4 when MSAA is used,
 388          * however in practice 16x4 seems fastest.
 389          *
 390          * Note that PS/WM thread counts depend on the WIZ hashing
 391          * disable bit, which we don't touch here, but it's good
 392          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 393          */
 394         wa_masked_field_set(wal, GEN7_GT_MODE,
 395                             GEN6_WIZ_HASHING_MASK,
 396                             GEN6_WIZ_HASHING_16x4);
 397 }
 398
 399 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
 400                                      struct i915_wa_list *wal)
 401 {
 402         struct drm_i915_private *i915 = engine->i915;
 403
 404         gen8_ctx_workarounds_init(engine, wal);
 405
 406         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 407         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 408
 409         /* WaDisableDopClockGating:bdw
 410          *
 411          * Also see the related UCGTCL1 write in bdw_init_clock_gating()
 412          * to disable EUTC clock gating.
 413          */
 414         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 415                          DOP_CLOCK_GATING_DISABLE);
 416
 417         wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
 418                          GEN8_SAMPLER_POWER_BYPASS_DIS);
 419
 420         wa_masked_en(wal, HDC_CHICKEN0,
 421                      /* WaForceContextSaveRestoreNonCoherent:bdw */
 422                      HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 423                      /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 424                      (IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 425 }
 426
 427 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
 428                                      struct i915_wa_list *wal)
 429 {
 430         gen8_ctx_workarounds_init(engine, wal);
 431
 432         /* WaDisableThreadStallDopClockGating:chv */
 433         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 434
 435         /* Improve HiZ throughput on CHV. */
 436         wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 437 }
 438
 439 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
 440                                       struct i915_wa_list *wal)
 441 {
 442         struct drm_i915_private *i915 = engine->i915;
 443
 444         if (HAS_LLC(i915)) {
 445                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 446                  *
 447                  * Must match Display Engine. See
 448                  * WaCompressedResourceDisplayNewHashMode.
 449                  */
 450                 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 451                              GEN9_PBE_COMPRESSED_HASH_SELECTION);
 452                 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 453                                  GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
 454         }
 455
 456         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
 457         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 458         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 459                          FLOW_CONTROL_ENABLE |
 460                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 461
 462         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
 463         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 464         wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 465                          GEN9_ENABLE_YV12_BUGFIX |
 466                          GEN9_ENABLE_GPGPU_PREEMPTION);
 467
 468         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
 469         /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 470         wa_masked_en(wal, CACHE_MODE_1,
 471                      GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 472                      GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 473
 474         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 475         wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
 476                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 477
 478         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 479         wa_masked_en(wal, HDC_CHICKEN0,
 480                      HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 481                      HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 482
 483         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 484          * both tied to WaForceContextSaveRestoreNonCoherent
 485          * in some hsds for skl. We keep the tie for all gen9. The
 486          * documentation is a bit hazy and so we want to get common behaviour,
 487          * even though there is no clear evidence we would need both on kbl/bxt.
 488          * This area has been source of system hangs so we play it safe
 489          * and mimic the skl regardless of what bspec says.
 490          *
 491          * Use Force Non-Coherent whenever executing a 3D context. This
 492          * is a workaround for a possible hang in the unlikely event
 493          * a TLB invalidation occurs during a PSD flush.
 494          */
 495
 496         /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 497         wa_masked_en(wal, HDC_CHICKEN0,
 498                      HDC_FORCE_NON_COHERENT);
 499
 500         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 501         if (IS_SKYLAKE(i915) ||
 502             IS_KABYLAKE(i915) ||
 503             IS_COFFEELAKE(i915) ||
 504             IS_COMETLAKE(i915))
 505                 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
 506                                  GEN8_SAMPLER_POWER_BYPASS_DIS);
 507
 508         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 509         wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 510
 511         /*
 512          * Supporting preemption with fine-granularity requires changes in the
 513          * batch buffer programming. Since we can't break old userspace, we
 514          * need to set our default preemption level to safe value. Userspace is
 515          * still able to use more fine-grained preemption levels, since in
 516          * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
 517          * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
 518          * not real HW workarounds, but merely a way to start using preemption
 519          * while maintaining old contract with userspace.
 520          */
 521
 522         /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
 523         wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 524
 525         /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
 526         wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
 527                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 528                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 529
 530         /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
 531         if (IS_GEN9_LP(i915))
 532                 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
 533 }
 534
 535 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
 536                                 struct i915_wa_list *wal)
 537 {
 538         struct intel_gt *gt = engine->gt;
 539         u8 vals[3] = { 0, 0, 0 };
 540         unsigned int i;
 541
 542         for (i = 0; i < 3; i++) {
 543                 u8 ss;
 544
 545                 /*
 546                  * Only consider slices where one, and only one, subslice has 7
 547                  * EUs
 548                  */
 549                 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
 550                         continue;
 551
 552                 /*
 553                  * subslice_7eu[i] != 0 (because of the check above) and
 554                  * ss_max == 4 (maximum number of subslices possible per slice)
 555                  *
 556                  * ->    0 <= ss <= 3;
 557                  */
 558                 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
 559                 vals[i] = 3 - ss;
 560         }
 561
 562         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 563                 return;
 564
 565         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 566         wa_masked_field_set(wal, GEN7_GT_MODE,
 567                             GEN9_IZ_HASHING_MASK(2) |
 568                             GEN9_IZ_HASHING_MASK(1) |
 569                             GEN9_IZ_HASHING_MASK(0),
 570                             GEN9_IZ_HASHING(2, vals[2]) |
 571                             GEN9_IZ_HASHING(1, vals[1]) |
 572                             GEN9_IZ_HASHING(0, vals[0]));
 573 }
 574
 575 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
 576                                      struct i915_wa_list *wal)
 577 {
 578         gen9_ctx_workarounds_init(engine, wal);
 579         skl_tune_iz_hashing(engine, wal);
 580 }
 581
 582 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
 583                                      struct i915_wa_list *wal)
 584 {
 585         gen9_ctx_workarounds_init(engine, wal);
 586
 587         /* WaDisableThreadStallDopClockGating:bxt */
 588         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 589                          STALL_DOP_GATING_DISABLE);
 590
 591         /* WaToEnableHwFixForPushConstHWBug:bxt */
 592         wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 593                      GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 594 }
 595
 596 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 597                                      struct i915_wa_list *wal)
 598 {
 599         struct drm_i915_private *i915 = engine->i915;
 600
 601         gen9_ctx_workarounds_init(engine, wal);
 602
 603         /* WaToEnableHwFixForPushConstHWBug:kbl */
 604         if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
 605                 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 606                              GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 607
 608         /* WaDisableSbeCacheDispatchPortSharing:kbl */
 609         wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 610                          GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 611 }
 612
 613 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
 614                                      struct i915_wa_list *wal)
 615 {
 616         gen9_ctx_workarounds_init(engine, wal);
 617
 618         /* WaToEnableHwFixForPushConstHWBug:glk */
 619         wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 620                      GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 621 }
 622
 623 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 624                                      struct i915_wa_list *wal)
 625 {
 626         gen9_ctx_workarounds_init(engine, wal);
 627
 628         /* WaToEnableHwFixForPushConstHWBug:cfl */
 629         wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 630                      GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 631
 632         /* WaDisableSbeCacheDispatchPortSharing:cfl */
 633         wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 634                          GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 635 }
 636
 637 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 638                                      struct i915_wa_list *wal)
 639 {
 640         /* Wa_1406697149 (WaDisableBankHangMode:icl) */
 641         wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
 642
 643         /* WaForceEnableNonCoherent:icl
 644          * This is not the same workaround as in early Gen9 platforms, where
 645          * lacking this could cause system hangs, but coherency performance
 646          * overhead is high and only a few compute workloads really need it
 647          * (the register is whitelisted in hardware now, so UMDs can opt in
 648          * for coherency if they have a good reason).
 649          */
 650         wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 651
 652         /* WaEnableFloatBlendOptimization:icl */
 653         wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
 654                    _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
 655                    0 /* write-only, so skip validation */,
 656                    true);
 657
 658         /* WaDisableGPGPUMidThreadPreemption:icl */
 659         wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
 660                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 661                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 662
 663         /* allow headerless messages for preemptible GPGPU context */
 664         wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 665                          GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 666
 667         /* Wa_1604278689:icl,ehl */
 668         wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
 669         wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
 670                          0,
 671                          0xFFFFFFFF);
 672
 673         /* Wa_1406306137:icl,ehl */
 674         wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 675 }
 676
 677 /*
 678  * These settings aren't actually workarounds, but general tuning settings that
 679  * need to be programmed on dg2 platform.
 680  */
 681 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 682                                    struct i915_wa_list *wal)
 683 {
 684         wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
 685         wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
 686                              REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
 687         wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 688                              FF_MODE2_TDS_TIMER_128);
 689 }
 690
 691 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
 692                                        struct i915_wa_list *wal)
 693 {
 694         struct drm_i915_private *i915 = engine->i915;
 695
 696         /*
 697          * Wa_1409142259:tgl,dg1,adl-p
 698          * Wa_1409347922:tgl,dg1,adl-p
 699          * Wa_1409252684:tgl,dg1,adl-p
 700          * Wa_1409217633:tgl,dg1,adl-p
 701          * Wa_1409207793:tgl,dg1,adl-p
 702          * Wa_1409178076:tgl,dg1,adl-p
 703          * Wa_1408979724:tgl,dg1,adl-p
 704          * Wa_14010443199:tgl,rkl,dg1,adl-p
 705          * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p
 706          * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p
 707          */
 708         wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
 709                      GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 710
 711         /* WaDisableGPGPUMidThreadPreemption:gen12 */
 712         wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
 713                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 714                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 715
 716         /*
 717          * Wa_16011163337 - GS_TIMER
 718          *
 719          * TDS_TIMER: Although some platforms refer to it as Wa_1604555607, we
 720          * need to program it even on those that don't explicitly list that
 721          * workaround.
 722          *
 723          * Note that the programming of GEN12_FF_MODE2 is further modified
 724          * according to the FF_MODE2 guidance given by Wa_1608008084.
 725          * Wa_1608008084 tells us the FF_MODE2 register will return the wrong
 726          * value when read from the CPU.
 727          *
 728          * The default value for this register is zero for all fields.
 729          * So instead of doing a RMW we should just write the desired values
 730          * for TDS and GS timers. Note that since the readback can't be trusted,
 731          * the clear mask is just set to ~0 to make sure other bits are not
 732          * inadvertently set. For the same reason read verification is ignored.
 733          */
 734         wa_add(wal,
 735                GEN12_FF_MODE2,
 736                ~0,
 737                FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224,
 738                0, false);
 739
 740         if (!IS_DG1(i915)) {
 741                 /* Wa_1806527549 */
 742                 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
 743
 744                 /* Wa_1606376872 */
 745                 wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
 746         }
 747 }
 748
 749 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
 750                                      struct i915_wa_list *wal)
 751 {
 752         gen12_ctx_workarounds_init(engine, wal);
 753
 754         /* Wa_1409044764 */
 755         wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3,
 756                       DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
 757
 758         /* Wa_22010493298 */
 759         wa_masked_en(wal, HIZ_CHICKEN,
 760                      DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
 761 }
 762
 763 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 764                                      struct i915_wa_list *wal)
 765 {
 766         dg2_ctx_gt_tuning_init(engine, wal);
 767
 768         /* Wa_16013271637:dg2 */
 769         wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
 770                          MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
 771
 772         /* Wa_14014947963:dg2 */
 773         wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
 774
 775         /* Wa_18018764978:dg2 */
 776         wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
 777
 778         /* Wa_18019271663:dg2 */
 779         wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 780 }
 781
 782 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 783                                      struct i915_wa_list *wal)
 784 {
 785         struct intel_gt *gt = engine->gt;
 786
 787         dg2_ctx_gt_tuning_init(engine, wal);
 788
 789         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
 790             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
 791                 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 792 }
 793
 794 static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
 795                                        struct i915_wa_list *wal)
 796 {
 797         struct intel_gt *gt = engine->gt;
 798
 799         xelpg_ctx_gt_tuning_init(engine, wal);
 800
 801         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
 802             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
 803                 /* Wa_14014947963 */
 804                 wa_masked_field_set(wal, VF_PREEMPTION,
 805                                     PREEMPTION_VERTEX_COUNT, 0x4000);
 806
 807                 /* Wa_16013271637 */
 808                 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
 809                                  MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
 810
 811                 /* Wa_18019627453 */
 812                 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
 813
 814                 /* Wa_18018764978 */
 815                 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
 816         }
 817
 818         /* Wa_18019271663 */
 819         wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 820 }
 821
 822 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
 823                                          struct i915_wa_list *wal)
 824 {
 825         /*
 826          * This is a "fake" workaround defined by software to ensure we
 827          * maintain reliable, backward-compatible behavior for userspace with
 828          * regards to how nested MI_BATCH_BUFFER_START commands are handled.
 829          *
 830          * The per-context setting of MI_MODE[12] determines whether the bits
 831          * of a nested MI_BATCH_BUFFER_START instruction should be interpreted
 832          * in the traditional manner or whether they should instead use a new
 833          * tgl+ meaning that breaks backward compatibility, but allows nesting
 834          * into 3rd-level batchbuffers.  When this new capability was first
 835          * added in TGL, it remained off by default unless a context
 836          * intentionally opted in to the new behavior.  However Xe_HPG now
 837          * flips this on by default and requires that we explicitly opt out if
 838          * we don't want the new behavior.
 839          *
 840          * From a SW perspective, we want to maintain the backward-compatible
 841          * behavior for userspace, so we'll apply a fake workaround to set it
 842          * back to the legacy behavior on platforms where the hardware default
 843          * is to break compatibility.  At the moment there is no Linux
 844          * userspace that utilizes third-level batchbuffers, so this will avoid
 845          * userspace from needing to make any changes.  using the legacy
 846          * meaning is the correct thing to do.  If/when we have userspace
 847          * consumers that want to utilize third-level batch nesting, we can
 848          * provide a context parameter to allow them to opt-in.
 849          */
 850         wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
 851 }
 852
 853 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine,
 854                                    struct i915_wa_list *wal)
 855 {
 856         u8 mocs;
 857
 858         /*
 859          * Some blitter commands do not have a field for MOCS, those
 860          * commands will use MOCS index pointed by BLIT_CCTL.
 861          * BLIT_CCTL registers are needed to be programmed to un-cached.
 862          */
 863         if (engine->class == COPY_ENGINE_CLASS) {
 864                 mocs = engine->gt->mocs.uc_index;
 865                 wa_write_clr_set(wal,
 866                                  BLIT_CCTL(engine->mmio_base),
 867                                  BLIT_CCTL_MASK,
 868                                  BLIT_CCTL_MOCS(mocs, mocs));
 869         }
 870 }
 871
 872 /*
 873  * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround
 874  * defined by the hardware team, but it programming general context registers.
 875  * Adding those context register programming in context workaround
 876  * allow us to use the wa framework for proper application and validation.
 877  */
 878 static void
 879 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine,
 880                           struct i915_wa_list *wal)
 881 {
 882         if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 883                 fakewa_disable_nestedbb_mode(engine, wal);
 884
 885         gen12_ctx_gt_mocs_init(engine, wal);
 886 }
 887
 888 static void
 889 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 890                            struct i915_wa_list *wal,
 891                            const char *name)
 892 {
 893         struct drm_i915_private *i915 = engine->i915;
 894
 895         wa_init_start(wal, engine->gt, name, engine->name);
 896
 897         /* Applies to all engines */
 898         /*
 899          * Fake workarounds are not the actual workaround but
 900          * programming of context registers using workaround framework.
 901          */
 902         if (GRAPHICS_VER(i915) >= 12)
 903                 gen12_ctx_gt_fake_wa_init(engine, wal);
 904
 905         if (engine->class != RENDER_CLASS)
 906                 goto done;
 907
 908         if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
 909                 xelpg_ctx_workarounds_init(engine, wal);
 910         else if (IS_PONTEVECCHIO(i915))
 911                 ; /* noop; none at this time */
 912         else if (IS_DG2(i915))
 913                 dg2_ctx_workarounds_init(engine, wal);
 914         else if (IS_XEHPSDV(i915))
 915                 ; /* noop; none at this time */
 916         else if (IS_DG1(i915))
 917                 dg1_ctx_workarounds_init(engine, wal);
 918         else if (GRAPHICS_VER(i915) == 12)
 919                 gen12_ctx_workarounds_init(engine, wal);
 920         else if (GRAPHICS_VER(i915) == 11)
 921                 icl_ctx_workarounds_init(engine, wal);
 922         else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
 923                 cfl_ctx_workarounds_init(engine, wal);
 924         else if (IS_GEMINILAKE(i915))
 925                 glk_ctx_workarounds_init(engine, wal);
 926         else if (IS_KABYLAKE(i915))
 927                 kbl_ctx_workarounds_init(engine, wal);
 928         else if (IS_BROXTON(i915))
 929                 bxt_ctx_workarounds_init(engine, wal);
 930         else if (IS_SKYLAKE(i915))
 931                 skl_ctx_workarounds_init(engine, wal);
 932         else if (IS_CHERRYVIEW(i915))
 933                 chv_ctx_workarounds_init(engine, wal);
 934         else if (IS_BROADWELL(i915))
 935                 bdw_ctx_workarounds_init(engine, wal);
 936         else if (GRAPHICS_VER(i915) == 7)
 937                 gen7_ctx_workarounds_init(engine, wal);
 938         else if (GRAPHICS_VER(i915) == 6)
 939                 gen6_ctx_workarounds_init(engine, wal);
 940         else if (GRAPHICS_VER(i915) < 8)
 941                 ;
 942         else
 943                 MISSING_CASE(GRAPHICS_VER(i915));
 944
 945 done:
 946         wa_init_finish(wal);
 947 }
 948
 949 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
 950 {
 951         __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
 952 }
 953
 954 int intel_engine_emit_ctx_wa(struct i915_request *rq)
 955 {
 956         struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
 957         struct intel_uncore *uncore = rq->engine->uncore;
 958         enum forcewake_domains fw;
 959         unsigned long flags;
 960         struct i915_wa *wa;
 961         unsigned int i;
 962         u32 *cs;
 963         int ret;
 964
 965         if (wal->count == 0)
 966                 return 0;
 967
 968         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 969         if (ret)
 970                 return ret;
 971
 972         cs = intel_ring_begin(rq, (wal->count * 2 + 2));
 973         if (IS_ERR(cs))
 974                 return PTR_ERR(cs);
 975
 976         fw = wal_get_fw_for_rmw(uncore, wal);
 977
 978         intel_gt_mcr_lock(wal->gt, &flags);
 979         spin_lock(&uncore->lock);
 980         intel_uncore_forcewake_get__locked(uncore, fw);
 981
 982         *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
 983         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 984                 u32 val;
 985
 986                 /* Skip reading the register if it's not really needed */
 987                 if (wa->masked_reg || (wa->clr | wa->set) == U32_MAX) {
 988                         val = wa->set;
 989                 } else {
 990                         val = wa->is_mcr ?
 991                                 intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) :
 992                                 intel_uncore_read_fw(uncore, wa->reg);
 993                         val &= ~wa->clr;
 994                         val |= wa->set;
 995                 }
 996
 997                 *cs++ = i915_mmio_reg_offset(wa->reg);
 998                 *cs++ = val;
 999         }
1000         *cs++ = MI_NOOP;
1001
1002         intel_uncore_forcewake_put__locked(uncore, fw);
1003         spin_unlock(&uncore->lock);
1004         intel_gt_mcr_unlock(wal->gt, flags);
1005
1006         intel_ring_advance(rq, cs);
1007
1008         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
1009         if (ret)
1010                 return ret;
1011
1012         return 0;
1013 }
1014
1015 static void
1016 gen4_gt_workarounds_init(struct intel_gt *gt,
1017                          struct i915_wa_list *wal)
1018 {
1019         /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
1020         wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
1021 }
1022
1023 static void
1024 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1025 {
1026         gen4_gt_workarounds_init(gt, wal);
1027
1028         /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
1029         wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
1030 }
1031
1032 static void
1033 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1034 {
1035         g4x_gt_workarounds_init(gt, wal);
1036
1037         wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
1038 }
1039
1040 static void
1041 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1042 {
1043 }
1044
1045 static void
1046 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1047 {
1048         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
1049         wa_masked_dis(wal,
1050                       GEN7_COMMON_SLICE_CHICKEN1,
1051                       GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1052
1053         /* WaApplyL3ControlAndL3ChickenMode:ivb */
1054         wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
1055         wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
1056
1057         /* WaForceL3Serialization:ivb */
1058         wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1059 }
1060
1061 static void
1062 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1063 {
1064         /* WaForceL3Serialization:vlv */
1065         wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1066
1067         /*
1068          * WaIncreaseL3CreditsForVLVB0:vlv
1069          * This is the hardware default actually.
1070          */
1071         wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
1072 }
1073
1074 static void
1075 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1076 {
1077         /* L3 caching of data atomics doesn't work -- disable it. */
1078         wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
1079
1080         wa_add(wal,
1081                HSW_ROW_CHICKEN3, 0,
1082                _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
1083                0 /* XXX does this reg exist? */, true);
1084
1085         /* WaVSRefCountFullforceMissDisable:hsw */
1086         wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
1087 }
1088
1089 static void
1090 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
1091 {
1092         const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
1093         unsigned int slice, subslice;
1094         u32 mcr, mcr_mask;
1095
1096         GEM_BUG_ON(GRAPHICS_VER(i915) != 9);
1097
1098         /*
1099          * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml
1100          * Before any MMIO read into slice/subslice specific registers, MCR
1101          * packet control register needs to be programmed to point to any
1102          * enabled s/ss pair. Otherwise, incorrect values will be returned.
1103          * This means each subsequent MMIO read will be forwarded to an
1104          * specific s/ss combination, but this is OK since these registers
1105          * are consistent across s/ss in almost all cases. In the rare
1106          * occasions, such as INSTDONE, where this value is dependent
1107          * on s/ss combo, the read should be done with read_subslice_reg.
1108          */
1109         slice = ffs(sseu->slice_mask) - 1;
1110         GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
1111         subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
1112         GEM_BUG_ON(!subslice);
1113         subslice--;
1114
1115         /*
1116          * We use GEN8_MCR..() macros to calculate the |mcr| value for
1117          * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads
1118          */
1119         mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1120         mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1121
1122         drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr);
1123
1124         wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
1125 }
1126
1127 static void
1128 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1129 {
1130         struct drm_i915_private *i915 = gt->i915;
1131
1132         /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */
1133         gen9_wa_init_mcr(i915, wal);
1134
1135         /* WaDisableKillLogic:bxt,skl,kbl */
1136         if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
1137                 wa_write_or(wal,
1138                             GAM_ECOCHK,
1139                             ECOCHK_DIS_TLB);
1140
1141         if (HAS_LLC(i915)) {
1142                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
1143                  *
1144                  * Must match Display Engine. See
1145                  * WaCompressedResourceDisplayNewHashMode.
1146                  */
1147                 wa_write_or(wal,
1148                             MMCD_MISC_CTRL,
1149                             MMCD_PCLA | MMCD_HOTSPOT_EN);
1150         }
1151
1152         /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
1153         wa_write_or(wal,
1154                     GAM_ECOCHK,
1155                     BDW_DISABLE_HDC_INVALIDATION);
1156 }
1157
1158 static void
1159 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1160 {
1161         gen9_gt_workarounds_init(gt, wal);
1162
1163         /* WaDisableGafsUnitClkGating:skl */
1164         wa_write_or(wal,
1165                     GEN7_UCGCTL4,
1166                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1167
1168         /* WaInPlaceDecompressionHang:skl */
1169         if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
1170                 wa_write_or(wal,
1171                             GEN9_GAMT_ECO_REG_RW_IA,
1172                             GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1173 }
1174
1175 static void
1176 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1177 {
1178         gen9_gt_workarounds_init(gt, wal);
1179
1180         /* WaDisableDynamicCreditSharing:kbl */
1181         if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
1182                 wa_write_or(wal,
1183                             GAMT_CHKN_BIT_REG,
1184                             GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1185
1186         /* WaDisableGafsUnitClkGating:kbl */
1187         wa_write_or(wal,
1188                     GEN7_UCGCTL4,
1189                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1190
1191         /* WaInPlaceDecompressionHang:kbl */
1192         wa_write_or(wal,
1193                     GEN9_GAMT_ECO_REG_RW_IA,
1194                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1195 }
1196
1197 static void
1198 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1199 {
1200         gen9_gt_workarounds_init(gt, wal);
1201 }
1202
1203 static void
1204 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1205 {
1206         gen9_gt_workarounds_init(gt, wal);
1207
1208         /* WaDisableGafsUnitClkGating:cfl */
1209         wa_write_or(wal,
1210                     GEN7_UCGCTL4,
1211                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1212
1213         /* WaInPlaceDecompressionHang:cfl */
1214         wa_write_or(wal,
1215                     GEN9_GAMT_ECO_REG_RW_IA,
1216                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1217 }
1218
1219 static void __set_mcr_steering(struct i915_wa_list *wal,
1220                                i915_reg_t steering_reg,
1221                                unsigned int slice, unsigned int subslice)
1222 {
1223         u32 mcr, mcr_mask;
1224
1225         mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1226         mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1227
1228         wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);
1229 }
1230
1231 static void debug_dump_steering(struct intel_gt *gt)
1232 {
1233         struct drm_printer p = drm_debug_printer("MCR Steering:");
1234
1235         if (drm_debug_enabled(DRM_UT_DRIVER))
1236                 intel_gt_mcr_report_steering(&p, gt, false);
1237 }
1238
1239 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
1240                          unsigned int slice, unsigned int subslice)
1241 {
1242         __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice);
1243
1244         gt->default_steering.groupid = slice;
1245         gt->default_steering.instanceid = subslice;
1246
1247         debug_dump_steering(gt);
1248 }
1249
1250 static void
1251 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1252 {
1253         const struct sseu_dev_info *sseu = &gt->info.sseu;
1254         unsigned int subslice;
1255
1256         GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
1257         GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
1258
1259         /*
1260          * Although a platform may have subslices, we need to always steer
1261          * reads to the lowest instance that isn't fused off.  When Render
1262          * Power Gating is enabled, grabbing forcewake will only power up a
1263          * single subslice (the "minconfig") if there isn't a real workload
1264          * that needs to be run; this means that if we steer register reads to
1265          * one of the higher subslices, we run the risk of reading back 0's or
1266          * random garbage.
1267          */
1268         subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
1269
1270         /*
1271          * If the subslice we picked above also steers us to a valid L3 bank,
1272          * then we can just rely on the default steering and won't need to
1273          * worry about explicitly re-steering L3BANK reads later.
1274          */
1275         if (gt->info.l3bank_mask & BIT(subslice))
1276                 gt->steering_table[L3BANK] = NULL;
1277
1278         __add_mcr_wa(gt, wal, 0, subslice);
1279 }
1280
1281 static void
1282 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1283 {
1284         const struct sseu_dev_info *sseu = &gt->info.sseu;
1285         unsigned long slice, subslice = 0, slice_mask = 0;
1286         u32 lncf_mask = 0;
1287         int i;
1288
1289         /*
1290          * On Xe_HP the steering increases in complexity. There are now several
1291          * more units that require steering and we're not guaranteed to be able
1292          * to find a common setting for all of them. These are:
1293          * - GSLICE (fusable)
1294          * - DSS (sub-unit within gslice; fusable)
1295          * - L3 Bank (fusable)
1296          * - MSLICE (fusable)
1297          * - LNCF (sub-unit within mslice; always present if mslice is present)
1298          *
1299          * We'll do our default/implicit steering based on GSLICE (in the
1300          * sliceid field) and DSS (in the subsliceid field).  If we can
1301          * find overlap between the valid MSLICE and/or LNCF values with
1302          * a suitable GSLICE, then we can just re-use the default value and
1303          * skip and explicit steering at runtime.
1304          *
1305          * We only need to look for overlap between GSLICE/MSLICE/LNCF to find
1306          * a valid sliceid value.  DSS steering is the only type of steering
1307          * that utilizes the 'subsliceid' bits.
1308          *
1309          * Also note that, even though the steering domain is called "GSlice"
1310          * and it is encoded in the register using the gslice format, the spec
1311          * says that the combined (geometry | compute) fuse should be used to
1312          * select the steering.
1313          */
1314
1315         /* Find the potential gslice candidates */
1316         slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
1317                                                        GEN_DSS_PER_GSLICE);
1318
1319         /*
1320          * Find the potential LNCF candidates.  Either LNCF within a valid
1321          * mslice is fine.
1322          */
1323         for_each_set_bit(i, &gt->info.mslice_mask, GEN12_MAX_MSLICES)
1324                 lncf_mask |= (0x3 << (i * 2));
1325
1326         /*
1327          * Are there any sliceid values that work for both GSLICE and LNCF
1328          * steering?
1329          */
1330         if (slice_mask & lncf_mask) {
1331                 slice_mask &= lncf_mask;
1332                 gt->steering_table[LNCF] = NULL;
1333         }
1334
1335         /* How about sliceid values that also work for MSLICE steering? */
1336         if (slice_mask & gt->info.mslice_mask) {
1337                 slice_mask &= gt->info.mslice_mask;
1338                 gt->steering_table[MSLICE] = NULL;
1339         }
1340
1341         if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0))
1342                 gt->steering_table[GAM] = NULL;
1343
1344         slice = __ffs(slice_mask);
1345         subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
1346                 GEN_DSS_PER_GSLICE;
1347
1348         __add_mcr_wa(gt, wal, slice, subslice);
1349
1350         /*
1351          * SQIDI ranges are special because they use different steering
1352          * registers than everything else we work with.  On XeHP SDV and
1353          * DG2-G10, any value in the steering registers will work fine since
1354          * all instances are present, but DG2-G11 only has SQIDI instances at
1355          * ID's 2 and 3, so we need to steer to one of those.  For simplicity
1356          * we'll just steer to a hardcoded "2" since that value will work
1357          * everywhere.
1358          */
1359         __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2);
1360         __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
1361
1362         /*
1363          * On DG2, GAM registers have a dedicated steering control register
1364          * and must always be programmed to a hardcoded groupid of "1."
1365          */
1366         if (IS_DG2(gt->i915))
1367                 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
1368 }
1369
1370 static void
1371 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1372 {
1373         unsigned int dss;
1374
1375         /*
1376          * Setup implicit steering for COMPUTE and DSS ranges to the first
1377          * non-fused-off DSS.  All other types of MCR registers will be
1378          * explicitly steered.
1379          */
1380         dss = intel_sseu_find_first_xehp_dss(&gt->info.sseu, 0, 0);
1381         __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE);
1382 }
1383
1384 static void
1385 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1386 {
1387         struct drm_i915_private *i915 = gt->i915;
1388
1389         icl_wa_init_mcr(gt, wal);
1390
1391         /* WaModifyGamTlbPartitioning:icl */
1392         wa_write_clr_set(wal,
1393                          GEN11_GACB_PERF_CTRL,
1394                          GEN11_HASH_CTRL_MASK,
1395                          GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
1396
1397         /* Wa_1405766107:icl
1398          * Formerly known as WaCL2SFHalfMaxAlloc
1399          */
1400         wa_write_or(wal,
1401                     GEN11_LSN_UNSLCVC,
1402                     GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
1403                     GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
1404
1405         /* Wa_220166154:icl
1406          * Formerly known as WaDisCtxReload
1407          */
1408         wa_write_or(wal,
1409                     GEN8_GAMW_ECO_DEV_RW_IA,
1410                     GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
1411
1412         /* Wa_1406463099:icl
1413          * Formerly known as WaGamTlbPendError
1414          */
1415         wa_write_or(wal,
1416                     GAMT_CHKN_BIT_REG,
1417                     GAMT_CHKN_DISABLE_L3_COH_PIPE);
1418
1419         /*
1420          * Wa_1408615072:icl,ehl  (vsunit)
1421          * Wa_1407596294:icl,ehl  (hsunit)
1422          */
1423         wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1424                     VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
1425
1426         /* Wa_1407352427:icl,ehl */
1427         wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1428                     PSDUNIT_CLKGATE_DIS);
1429
1430         /* Wa_1406680159:icl,ehl */
1431         wa_mcr_write_or(wal,
1432                         GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1433                         GWUNIT_CLKGATE_DIS);
1434
1435         /* Wa_1607087056:icl,ehl,jsl */
1436         if (IS_ICELAKE(i915) ||
1437                 ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1438                 IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)))
1439                 wa_write_or(wal,
1440                             GEN11_SLICE_UNIT_LEVEL_CLKGATE,
1441                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
1442
1443         /*
1444          * This is not a documented workaround, but rather an optimization
1445          * to reduce sampler power.
1446          */
1447         wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1448 }
1449
1450 /*
1451  * Though there are per-engine instances of these registers,
1452  * they retain their value through engine resets and should
1453  * only be provided on the GT workaround list rather than
1454  * the engine-specific workaround list.
1455  */
1456 static void
1457 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal)
1458 {
1459         struct intel_engine_cs *engine;
1460         int id;
1461
1462         for_each_engine(engine, gt, id) {
1463                 if (engine->class != VIDEO_DECODE_CLASS ||
1464                     (engine->instance % 2))
1465                         continue;
1466
1467                 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),
1468                             IECPUNIT_CLKGATE_DIS);
1469         }
1470 }
1471
1472 static void
1473 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1474 {
1475         icl_wa_init_mcr(gt, wal);
1476
1477         /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
1478         wa_14011060649(gt, wal);
1479
1480         /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
1481         wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1482
1483         /*
1484          * Wa_14015795083
1485          *
1486          * Firmware on some gen12 platforms locks the MISCCPCTL register,
1487          * preventing i915 from modifying it for this workaround.  Skip the
1488          * readback verification for this workaround on debug builds; if the
1489          * workaround doesn't stick due to firmware behavior, it's not an error
1490          * that we want CI to flag.
1491          */
1492         wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
1493                0, 0, false);
1494 }
1495
1496 static void
1497 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1498 {
1499         gen12_gt_workarounds_init(gt, wal);
1500
1501         /* Wa_1409420604:dg1 */
1502         wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
1503                         CPSSUNIT_CLKGATE_DIS);
1504
1505         /* Wa_1408615072:dg1 */
1506         /* Empirical testing shows this register is unaffected by engine reset. */
1507         wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
1508 }
1509
1510 static void
1511 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1512 {
1513         struct drm_i915_private *i915 = gt->i915;
1514
1515         xehp_init_mcr(gt, wal);
1516
1517         /* Wa_1409757795:xehpsdv */
1518         wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
1519
1520         /* Wa_18011725039:xehpsdv */
1521         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
1522                 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
1523                 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
1524         }
1525
1526         /* Wa_16011155590:xehpsdv */
1527         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
1528                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1529                             TSGUNIT_CLKGATE_DIS);
1530
1531         /* Wa_14011780169:xehpsdv */
1532         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) {
1533                 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
1534                             GAMTLBVDBOX7_CLKGATE_DIS |
1535                             GAMTLBVDBOX6_CLKGATE_DIS |
1536                             GAMTLBVDBOX5_CLKGATE_DIS |
1537                             GAMTLBVDBOX4_CLKGATE_DIS |
1538                             GAMTLBVDBOX3_CLKGATE_DIS |
1539                             GAMTLBVDBOX2_CLKGATE_DIS |
1540                             GAMTLBVDBOX1_CLKGATE_DIS |
1541                             GAMTLBVDBOX0_CLKGATE_DIS |
1542                             GAMTLBKCR_CLKGATE_DIS |
1543                             GAMTLBGUC_CLKGATE_DIS |
1544                             GAMTLBBLT_CLKGATE_DIS);
1545                 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
1546                             GAMTLBGFXA1_CLKGATE_DIS |
1547                             GAMTLBCOMPA0_CLKGATE_DIS |
1548                             GAMTLBCOMPA1_CLKGATE_DIS |
1549                             GAMTLBCOMPB0_CLKGATE_DIS |
1550                             GAMTLBCOMPB1_CLKGATE_DIS |
1551                             GAMTLBCOMPC0_CLKGATE_DIS |
1552                             GAMTLBCOMPC1_CLKGATE_DIS |
1553                             GAMTLBCOMPD0_CLKGATE_DIS |
1554                             GAMTLBCOMPD1_CLKGATE_DIS |
1555                             GAMTLBMERT_CLKGATE_DIS   |
1556                             GAMTLBVEBOX3_CLKGATE_DIS |
1557                             GAMTLBVEBOX2_CLKGATE_DIS |
1558                             GAMTLBVEBOX1_CLKGATE_DIS |
1559                             GAMTLBVEBOX0_CLKGATE_DIS);
1560         }
1561
1562         /* Wa_16012725990:xehpsdv */
1563         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
1564                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS);
1565
1566         /* Wa_14011060649:xehpsdv */
1567         wa_14011060649(gt, wal);
1568
1569         /* Wa_14012362059:xehpsdv */
1570         wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
1571
1572         /* Wa_14014368820:xehpsdv */
1573         wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
1574                         INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
1575
1576         /* Wa_14010670810:xehpsdv */
1577         wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
1578 }
1579
1580 static void
1581 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1582 {
1583         xehp_init_mcr(gt, wal);
1584
1585         /* Wa_14011060649:dg2 */
1586         wa_14011060649(gt, wal);
1587
1588         if (IS_DG2_G10(gt->i915)) {
1589                 /* Wa_22010523718:dg2 */
1590                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1591                             CG3DDISCFEG_CLKGATE_DIS);
1592
1593                 /* Wa_14011006942:dg2 */
1594                 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1595                                 DSS_ROUTER_CLKGATE_DIS);
1596         }
1597
1598         /* Wa_14014830051:dg2 */
1599         wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1600
1601         /*
1602          * Wa_14015795083
1603          * Skip verification for possibly locked register.
1604          */
1605         wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
1606                0, 0, false);
1607
1608         /* Wa_18018781329 */
1609         wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1610         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1611         wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1612         wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1613
1614         /* Wa_1509235366:dg2 */
1615         wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
1616                         INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
1617
1618         /* Wa_14010648519:dg2 */
1619         wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
1620 }
1621
1622 static void
1623 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1624 {
1625         pvc_init_mcr(gt, wal);
1626
1627         /* Wa_14015795083 */
1628         wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
1629
1630         /* Wa_18018781329 */
1631         wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1632         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1633         wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1634         wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1635
1636         /* Wa_16016694945 */
1637         wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
1638 }
1639
1640 static void
1641 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1642 {
1643         /* Wa_14018778641 / Wa_18018781329 */
1644         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1645
1646         /* Wa_22016670082 */
1647         wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
1648
1649         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
1650             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
1651                 /* Wa_14014830051 */
1652                 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1653
1654                 /* Wa_14015795083 */
1655                 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
1656         }
1657
1658         /*
1659          * Unlike older platforms, we no longer setup implicit steering here;
1660          * all MCR accesses are explicitly steered.
1661          */
1662         debug_dump_steering(gt);
1663 }
1664
1665 static void
1666 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1667 {
1668         /*
1669          * Wa_14018778641
1670          * Wa_18018781329
1671          *
1672          * Note that although these registers are MCR on the primary
1673          * GT, the media GT's versions are regular singleton registers.
1674          */
1675         wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
1676
1677         debug_dump_steering(gt);
1678 }
1679
1680 /*
1681  * The bspec performance guide has recommended MMIO tuning settings.  These
1682  * aren't truly "workarounds" but we want to program them through the
1683  * workaround infrastructure to make sure they're (re)applied at the proper
1684  * times.
1685  *
1686  * The programming in this function is for settings that persist through
1687  * engine resets and also are not part of any engine's register state context.
1688  * I.e., settings that only need to be re-applied in the event of a full GT
1689  * reset.
1690  */
1691 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
1692 {
1693         if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
1694                 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1695                 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1696         }
1697
1698         if (IS_PONTEVECCHIO(gt->i915)) {
1699                 wa_mcr_write(wal, XEHPC_L3SCRUB,
1700                              SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
1701                 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
1702         }
1703
1704         if (IS_DG2(gt->i915)) {
1705                 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1706                 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1707         }
1708 }
1709
1710 static void
1711 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
1712 {
1713         struct drm_i915_private *i915 = gt->i915;
1714
1715         gt_tuning_settings(gt, wal);
1716
1717         if (gt->type == GT_MEDIA) {
1718                 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0))
1719                         xelpmp_gt_workarounds_init(gt, wal);
1720                 else
1721                         MISSING_CASE(MEDIA_VER_FULL(i915));
1722
1723                 return;
1724         }
1725
1726         if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
1727                 xelpg_gt_workarounds_init(gt, wal);
1728         else if (IS_PONTEVECCHIO(i915))
1729                 pvc_gt_workarounds_init(gt, wal);
1730         else if (IS_DG2(i915))
1731                 dg2_gt_workarounds_init(gt, wal);
1732         else if (IS_XEHPSDV(i915))
1733                 xehpsdv_gt_workarounds_init(gt, wal);
1734         else if (IS_DG1(i915))
1735                 dg1_gt_workarounds_init(gt, wal);
1736         else if (GRAPHICS_VER(i915) == 12)
1737                 gen12_gt_workarounds_init(gt, wal);
1738         else if (GRAPHICS_VER(i915) == 11)
1739                 icl_gt_workarounds_init(gt, wal);
1740         else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
1741                 cfl_gt_workarounds_init(gt, wal);
1742         else if (IS_GEMINILAKE(i915))
1743                 glk_gt_workarounds_init(gt, wal);
1744         else if (IS_KABYLAKE(i915))
1745                 kbl_gt_workarounds_init(gt, wal);
1746         else if (IS_BROXTON(i915))
1747                 gen9_gt_workarounds_init(gt, wal);
1748         else if (IS_SKYLAKE(i915))
1749                 skl_gt_workarounds_init(gt, wal);
1750         else if (IS_HASWELL(i915))
1751                 hsw_gt_workarounds_init(gt, wal);
1752         else if (IS_VALLEYVIEW(i915))
1753                 vlv_gt_workarounds_init(gt, wal);
1754         else if (IS_IVYBRIDGE(i915))
1755                 ivb_gt_workarounds_init(gt, wal);
1756         else if (GRAPHICS_VER(i915) == 6)
1757                 snb_gt_workarounds_init(gt, wal);
1758         else if (GRAPHICS_VER(i915) == 5)
1759                 ilk_gt_workarounds_init(gt, wal);
1760         else if (IS_G4X(i915))
1761                 g4x_gt_workarounds_init(gt, wal);
1762         else if (GRAPHICS_VER(i915) == 4)
1763                 gen4_gt_workarounds_init(gt, wal);
1764         else if (GRAPHICS_VER(i915) <= 8)
1765                 ;
1766         else
1767                 MISSING_CASE(GRAPHICS_VER(i915));
1768 }
1769
1770 void intel_gt_init_workarounds(struct intel_gt *gt)
1771 {
1772         struct i915_wa_list *wal = &gt->wa_list;
1773
1774         wa_init_start(wal, gt, "GT", "global");
1775         gt_init_workarounds(gt, wal);
1776         wa_init_finish(wal);
1777 }
1778
1779 static bool
1780 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,
1781           const char *name, const char *from)
1782 {
1783         if ((cur ^ wa->set) & wa->read) {
1784                 gt_err(gt,
1785                        "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n",
1786                        name, from, i915_mmio_reg_offset(wa->reg),
1787                        cur, cur & wa->read, wa->set & wa->read);
1788
1789                 return false;
1790         }
1791
1792         return true;
1793 }
1794
1795 static void wa_list_apply(const struct i915_wa_list *wal)
1796 {
1797         struct intel_gt *gt = wal->gt;
1798         struct intel_uncore *uncore = gt->uncore;
1799         enum forcewake_domains fw;
1800         unsigned long flags;
1801         struct i915_wa *wa;
1802         unsigned int i;
1803
1804         if (!wal->count)
1805                 return;
1806
1807         fw = wal_get_fw_for_rmw(uncore, wal);
1808
1809         intel_gt_mcr_lock(gt, &flags);
1810         spin_lock(&uncore->lock);
1811         intel_uncore_forcewake_get__locked(uncore, fw);
1812
1813         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1814                 u32 val, old = 0;
1815
1816                 /* open-coded rmw due to steering */
1817                 if (wa->clr)
1818                         old = wa->is_mcr ?
1819                                 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1820                                 intel_uncore_read_fw(uncore, wa->reg);
1821                 val = (old & ~wa->clr) | wa->set;
1822                 if (val != old || !wa->clr) {
1823                         if (wa->is_mcr)
1824                                 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val);
1825                         else
1826                                 intel_uncore_write_fw(uncore, wa->reg, val);
1827                 }
1828
1829                 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
1830                         u32 val = wa->is_mcr ?
1831                                 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1832                                 intel_uncore_read_fw(uncore, wa->reg);
1833
1834                         wa_verify(gt, wa, val, wal->name, "application");
1835                 }
1836         }
1837
1838         intel_uncore_forcewake_put__locked(uncore, fw);
1839         spin_unlock(&uncore->lock);
1840         intel_gt_mcr_unlock(gt, flags);
1841 }
1842
1843 void intel_gt_apply_workarounds(struct intel_gt *gt)
1844 {
1845         wa_list_apply(&gt->wa_list);
1846 }
1847
1848 static bool wa_list_verify(struct intel_gt *gt,
1849                            const struct i915_wa_list *wal,
1850                            const char *from)
1851 {
1852         struct intel_uncore *uncore = gt->uncore;
1853         struct i915_wa *wa;
1854         enum forcewake_domains fw;
1855         unsigned long flags;
1856         unsigned int i;
1857         bool ok = true;
1858
1859         fw = wal_get_fw_for_rmw(uncore, wal);
1860
1861         intel_gt_mcr_lock(gt, &flags);
1862         spin_lock(&uncore->lock);
1863         intel_uncore_forcewake_get__locked(uncore, fw);
1864
1865         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1866                 ok &= wa_verify(wal->gt, wa, wa->is_mcr ?
1867                                 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1868                                 intel_uncore_read_fw(uncore, wa->reg),
1869                                 wal->name, from);
1870
1871         intel_uncore_forcewake_put__locked(uncore, fw);
1872         spin_unlock(&uncore->lock);
1873         intel_gt_mcr_unlock(gt, flags);
1874
1875         return ok;
1876 }
1877
1878 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1879 {
1880         return wa_list_verify(gt, &gt->wa_list, from);
1881 }
1882
1883 __maybe_unused
1884 static bool is_nonpriv_flags_valid(u32 flags)
1885 {
1886         /* Check only valid flag bits are set */
1887         if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1888                 return false;
1889
1890         /* NB: Only 3 out of 4 enum values are valid for access field */
1891         if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1892             RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1893                 return false;
1894
1895         return true;
1896 }
1897
1898 static void
1899 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1900 {
1901         struct i915_wa wa = {
1902                 .reg = reg
1903         };
1904
1905         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1906                 return;
1907
1908         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1909                 return;
1910
1911         wa.reg.reg |= flags;
1912         _wa_add(wal, &wa);
1913 }
1914
1915 static void
1916 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
1917 {
1918         struct i915_wa wa = {
1919                 .mcr_reg = reg,
1920                 .is_mcr = 1,
1921         };
1922
1923         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1924                 return;
1925
1926         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1927                 return;
1928
1929         wa.mcr_reg.reg |= flags;
1930         _wa_add(wal, &wa);
1931 }
1932
1933 static void
1934 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1935 {
1936         whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1937 }
1938
1939 static void
1940 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
1941 {
1942         whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1943 }
1944
1945 static void gen9_whitelist_build(struct i915_wa_list *w)
1946 {
1947         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1948         whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1949
1950         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1951         whitelist_reg(w, GEN8_CS_CHICKEN1);
1952
1953         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1954         whitelist_reg(w, GEN8_HDC_CHICKEN1);
1955
1956         /* WaSendPushConstantsFromMMIO:skl,bxt */
1957         whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1958 }
1959
1960 static void skl_whitelist_build(struct intel_engine_cs *engine)
1961 {
1962         struct i915_wa_list *w = &engine->whitelist;
1963
1964         if (engine->class != RENDER_CLASS)
1965                 return;
1966
1967         gen9_whitelist_build(w);
1968
1969         /* WaDisableLSQCROPERFforOCL:skl */
1970         whitelist_mcr_reg(w, GEN8_L3SQCREG4);
1971 }
1972
1973 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1974 {
1975         if (engine->class != RENDER_CLASS)
1976                 return;
1977
1978         gen9_whitelist_build(&engine->whitelist);
1979 }
1980
1981 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1982 {
1983         struct i915_wa_list *w = &engine->whitelist;
1984
1985         if (engine->class != RENDER_CLASS)
1986                 return;
1987
1988         gen9_whitelist_build(w);
1989
1990         /* WaDisableLSQCROPERFforOCL:kbl */
1991         whitelist_mcr_reg(w, GEN8_L3SQCREG4);
1992 }
1993
1994 static void glk_whitelist_build(struct intel_engine_cs *engine)
1995 {
1996         struct i915_wa_list *w = &engine->whitelist;
1997
1998         if (engine->class != RENDER_CLASS)
1999                 return;
2000
2001         gen9_whitelist_build(w);
2002
2003         /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
2004         whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
2005 }
2006
2007 static void cfl_whitelist_build(struct intel_engine_cs *engine)
2008 {
2009         struct i915_wa_list *w = &engine->whitelist;
2010
2011         if (engine->class != RENDER_CLASS)
2012                 return;
2013
2014         gen9_whitelist_build(w);
2015
2016         /*
2017          * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
2018          *
2019          * This covers 4 register which are next to one another :
2020          *   - PS_INVOCATION_COUNT
2021          *   - PS_INVOCATION_COUNT_UDW
2022          *   - PS_DEPTH_COUNT
2023          *   - PS_DEPTH_COUNT_UDW
2024          */
2025         whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2026                           RING_FORCE_TO_NONPRIV_ACCESS_RD |
2027                           RING_FORCE_TO_NONPRIV_RANGE_4);
2028 }
2029
2030 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine)
2031 {
2032         struct i915_wa_list *w = &engine->whitelist;
2033
2034         if (engine->class != RENDER_CLASS)
2035                 whitelist_reg_ext(w,
2036                                   RING_CTX_TIMESTAMP(engine->mmio_base),
2037                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2038 }
2039
2040 static void cml_whitelist_build(struct intel_engine_cs *engine)
2041 {
2042         allow_read_ctx_timestamp(engine);
2043
2044         cfl_whitelist_build(engine);
2045 }
2046
2047 static void icl_whitelist_build(struct intel_engine_cs *engine)
2048 {
2049         struct i915_wa_list *w = &engine->whitelist;
2050
2051         allow_read_ctx_timestamp(engine);
2052
2053         switch (engine->class) {
2054         case RENDER_CLASS:
2055                 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
2056                 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7);
2057
2058                 /* WaAllowUMDToModifySamplerMode:icl */
2059                 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE);
2060
2061                 /* WaEnableStateCacheRedirectToCS:icl */
2062                 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
2063
2064                 /*
2065                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
2066                  *
2067                  * This covers 4 register which are next to one another :
2068                  *   - PS_INVOCATION_COUNT
2069                  *   - PS_INVOCATION_COUNT_UDW
2070                  *   - PS_DEPTH_COUNT
2071                  *   - PS_DEPTH_COUNT_UDW
2072                  */
2073                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2074                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
2075                                   RING_FORCE_TO_NONPRIV_RANGE_4);
2076                 break;
2077
2078         case VIDEO_DECODE_CLASS:
2079                 /* hucStatusRegOffset */
2080                 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
2081                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2082                 /* hucUKernelHdrInfoRegOffset */
2083                 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
2084                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2085                 /* hucStatus2RegOffset */
2086                 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
2087                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2088                 break;
2089
2090         default:
2091                 break;
2092         }
2093 }
2094
2095 static void tgl_whitelist_build(struct intel_engine_cs *engine)
2096 {
2097         struct i915_wa_list *w = &engine->whitelist;
2098
2099         allow_read_ctx_timestamp(engine);
2100
2101         switch (engine->class) {
2102         case RENDER_CLASS:
2103                 /*
2104                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
2105                  * Wa_1408556865:tgl
2106                  *
2107                  * This covers 4 registers which are next to one another :
2108                  *   - PS_INVOCATION_COUNT
2109                  *   - PS_INVOCATION_COUNT_UDW
2110                  *   - PS_DEPTH_COUNT
2111                  *   - PS_DEPTH_COUNT_UDW
2112                  */
2113                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2114                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
2115                                   RING_FORCE_TO_NONPRIV_RANGE_4);
2116
2117                 /*
2118                  * Wa_1808121037:tgl
2119                  * Wa_14012131227:dg1
2120                  * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p
2121                  */
2122                 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
2123
2124                 /* Wa_1806527549:tgl */
2125                 whitelist_reg(w, HIZ_CHICKEN);
2126
2127                 /* Required by recommended tuning setting (not a workaround) */
2128                 whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);
2129
2130                 break;
2131         default:
2132                 break;
2133         }
2134 }
2135
2136 static void dg2_whitelist_build(struct intel_engine_cs *engine)
2137 {
2138         struct i915_wa_list *w = &engine->whitelist;
2139
2140         switch (engine->class) {
2141         case RENDER_CLASS:
2142                 /* Required by recommended tuning setting (not a workaround) */
2143                 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
2144
2145                 break;
2146         default:
2147                 break;
2148         }
2149 }
2150
2151 static void blacklist_trtt(struct intel_engine_cs *engine)
2152 {
2153         struct i915_wa_list *w = &engine->whitelist;
2154
2155         /*
2156          * Prevent read/write access to [0x4400, 0x4600) which covers
2157          * the TRTT range across all engines. Note that normally userspace
2158          * cannot access the other engines' trtt control, but for simplicity
2159          * we cover the entire range on each engine.
2160          */
2161         whitelist_reg_ext(w, _MMIO(0x4400),
2162                           RING_FORCE_TO_NONPRIV_DENY |
2163                           RING_FORCE_TO_NONPRIV_RANGE_64);
2164         whitelist_reg_ext(w, _MMIO(0x4500),
2165                           RING_FORCE_TO_NONPRIV_DENY |
2166                           RING_FORCE_TO_NONPRIV_RANGE_64);
2167 }
2168
2169 static void pvc_whitelist_build(struct intel_engine_cs *engine)
2170 {
2171         /* Wa_16014440446:pvc */
2172         blacklist_trtt(engine);
2173 }
2174
2175 static void xelpg_whitelist_build(struct intel_engine_cs *engine)
2176 {
2177         struct i915_wa_list *w = &engine->whitelist;
2178
2179         switch (engine->class) {
2180         case RENDER_CLASS:
2181                 /* Required by recommended tuning setting (not a workaround) */
2182                 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
2183
2184                 break;
2185         default:
2186                 break;
2187         }
2188 }
2189
2190 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
2191 {
2192         struct drm_i915_private *i915 = engine->i915;
2193         struct i915_wa_list *w = &engine->whitelist;
2194
2195         wa_init_start(w, engine->gt, "whitelist", engine->name);
2196
2197         if (engine->gt->type == GT_MEDIA)
2198                 ; /* none yet */
2199         else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
2200                 xelpg_whitelist_build(engine);
2201         else if (IS_PONTEVECCHIO(i915))
2202                 pvc_whitelist_build(engine);
2203         else if (IS_DG2(i915))
2204                 dg2_whitelist_build(engine);
2205         else if (IS_XEHPSDV(i915))
2206                 ; /* none needed */
2207         else if (GRAPHICS_VER(i915) == 12)
2208                 tgl_whitelist_build(engine);
2209         else if (GRAPHICS_VER(i915) == 11)
2210                 icl_whitelist_build(engine);
2211         else if (IS_COMETLAKE(i915))
2212                 cml_whitelist_build(engine);
2213         else if (IS_COFFEELAKE(i915))
2214                 cfl_whitelist_build(engine);
2215         else if (IS_GEMINILAKE(i915))
2216                 glk_whitelist_build(engine);
2217         else if (IS_KABYLAKE(i915))
2218                 kbl_whitelist_build(engine);
2219         else if (IS_BROXTON(i915))
2220                 bxt_whitelist_build(engine);
2221         else if (IS_SKYLAKE(i915))
2222                 skl_whitelist_build(engine);
2223         else if (GRAPHICS_VER(i915) <= 8)
2224                 ;
2225         else
2226                 MISSING_CASE(GRAPHICS_VER(i915));
2227
2228         wa_init_finish(w);
2229 }
2230
2231 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
2232 {
2233         const struct i915_wa_list *wal = &engine->whitelist;
2234         struct intel_uncore *uncore = engine->uncore;
2235         const u32 base = engine->mmio_base;
2236         struct i915_wa *wa;
2237         unsigned int i;
2238
2239         if (!wal->count)
2240                 return;
2241
2242         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
2243                 intel_uncore_write(uncore,
2244                                    RING_FORCE_TO_NONPRIV(base, i),
2245                                    i915_mmio_reg_offset(wa->reg));
2246
2247         /* And clear the rest just in case of garbage */
2248         for (; i < RING_MAX_NONPRIV_SLOTS; i++)
2249                 intel_uncore_write(uncore,
2250                                    RING_FORCE_TO_NONPRIV(base, i),
2251                                    i915_mmio_reg_offset(RING_NOPID(base)));
2252 }
2253
2254 /*
2255  * engine_fake_wa_init(), a place holder to program the registers
2256  * which are not part of an official workaround defined by the
2257  * hardware team.
2258  * Adding programming of those register inside workaround will
2259  * allow utilizing wa framework to proper application and verification.
2260  */
2261 static void
2262 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2263 {
2264         u8 mocs_w, mocs_r;
2265
2266         /*
2267          * RING_CMD_CCTL specifies the default MOCS entry that will be used
2268          * by the command streamer when executing commands that don't have
2269          * a way to explicitly specify a MOCS setting.  The default should
2270          * usually reference whichever MOCS entry corresponds to uncached
2271          * behavior, although use of a WB cached entry is recommended by the
2272          * spec in certain circumstances on specific platforms.
2273          */
2274         if (GRAPHICS_VER(engine->i915) >= 12) {
2275                 mocs_r = engine->gt->mocs.uc_index;
2276                 mocs_w = engine->gt->mocs.uc_index;
2277
2278                 if (HAS_L3_CCS_READ(engine->i915) &&
2279                     engine->class == COMPUTE_CLASS) {
2280                         mocs_r = engine->gt->mocs.wb_index;
2281
2282                         /*
2283                          * Even on the few platforms where MOCS 0 is a
2284                          * legitimate table entry, it's never the correct
2285                          * setting to use here; we can assume the MOCS init
2286                          * just forgot to initialize wb_index.
2287                          */
2288                         drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
2289                 }
2290
2291                 wa_masked_field_set(wal,
2292                                     RING_CMD_CCTL(engine->mmio_base),
2293                                     CMD_CCTL_MOCS_MASK,
2294                                     CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
2295         }
2296 }
2297
2298 static void
2299 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2300 {
2301         struct drm_i915_private *i915 = engine->i915;
2302         struct intel_gt *gt = engine->gt;
2303
2304         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2305             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
2306                 /* Wa_22014600077 */
2307                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2308                                  ENABLE_EU_COUNT_FOR_TDL_FLUSH);
2309         }
2310
2311         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2312             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
2313             IS_DG2(i915)) {
2314                 /* Wa_1509727124 */
2315                 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2316                                  SC_DISABLE_POWER_OPTIMIZATION_EBB);
2317         }
2318
2319         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2320             IS_DG2(i915)) {
2321                 /* Wa_22012856258 */
2322                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2323                                  GEN12_DISABLE_READ_SUPPRESSION);
2324         }
2325
2326         if (IS_DG2(i915)) {
2327                 /*
2328                  * Wa_22010960976:dg2
2329                  * Wa_14013347512:dg2
2330                  */
2331                 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
2332                                   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
2333         }
2334
2335         if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
2336             IS_DG2(i915)) {
2337                 /* Wa_14015150844 */
2338                 wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
2339                            _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
2340                            0, true);
2341         }
2342
2343         if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {
2344                 /* Wa_22014600077:dg2 */
2345                 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
2346                            _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
2347                            0 /* Wa_14012342262 write-only reg, so skip verification */,
2348                            true);
2349         }
2350
2351         if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
2352             IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2353                 /*
2354                  * Wa_1606700617:tgl,dg1,adl-p
2355                  * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
2356                  * Wa_14010826681:tgl,dg1,rkl,adl-p
2357                  * Wa_18019627453:dg2
2358                  */
2359                 wa_masked_en(wal,
2360                              GEN9_CS_DEBUG_MODE1,
2361                              FF_DOP_CLOCK_GATE_DISABLE);
2362         }
2363
2364         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
2365             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2366                 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
2367                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
2368
2369                 /*
2370                  * Wa_1407928979:tgl A*
2371                  * Wa_18011464164:tgl[B0+],dg1[B0+]
2372                  * Wa_22010931296:tgl[B0+],dg1[B0+]
2373                  * Wa_14010919138:rkl,dg1,adl-s,adl-p
2374                  */
2375                 wa_write_or(wal, GEN7_FF_THREAD_MODE,
2376                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
2377
2378                 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
2379                 wa_mcr_masked_en(wal,
2380                                  GEN10_SAMPLER_MODE,
2381                                  ENABLE_SMALLPL);
2382         }
2383
2384         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
2385             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2386                 /* Wa_1409804808 */
2387                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2388                                  GEN12_PUSH_CONST_DEREF_HOLD_DIS);
2389
2390                 /* Wa_14010229206 */
2391                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
2392         }
2393
2394         if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
2395                 /*
2396                  * Wa_1607297627
2397                  *
2398                  * On TGL and RKL there are multiple entries for this WA in the
2399                  * BSpec; some indicate this is an A0-only WA, others indicate
2400                  * it applies to all steppings so we trust the "all steppings."
2401                  */
2402                 wa_masked_en(wal,
2403                              RING_PSMI_CTL(RENDER_RING_BASE),
2404                              GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
2405                              GEN8_RC_SEMA_IDLE_MSG_DISABLE);
2406         }
2407
2408         if (GRAPHICS_VER(i915) == 11) {
2409                 /* This is not an Wa. Enable for better image quality */
2410                 wa_masked_en(wal,
2411                              _3D_CHICKEN3,
2412                              _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
2413
2414                 /*
2415                  * Wa_1405543622:icl
2416                  * Formerly known as WaGAPZPriorityScheme
2417                  */
2418                 wa_write_or(wal,
2419                             GEN8_GARBCNTL,
2420                             GEN11_ARBITRATION_PRIO_ORDER_MASK);
2421
2422                 /*
2423                  * Wa_1604223664:icl
2424                  * Formerly known as WaL3BankAddressHashing
2425                  */
2426                 wa_write_clr_set(wal,
2427                                  GEN8_GARBCNTL,
2428                                  GEN11_HASH_CTRL_EXCL_MASK,
2429                                  GEN11_HASH_CTRL_EXCL_BIT0);
2430                 wa_write_clr_set(wal,
2431                                  GEN11_GLBLINVL,
2432                                  GEN11_BANK_HASH_ADDR_EXCL_MASK,
2433                                  GEN11_BANK_HASH_ADDR_EXCL_BIT0);
2434
2435                 /*
2436                  * Wa_1405733216:icl
2437                  * Formerly known as WaDisableCleanEvicts
2438                  */
2439                 wa_mcr_write_or(wal,
2440                                 GEN8_L3SQCREG4,
2441                                 GEN11_LQSC_CLEAN_EVICT_DISABLE);
2442
2443                 /* Wa_1606682166:icl */
2444                 wa_write_or(wal,
2445                             GEN7_SARCHKMD,
2446                             GEN7_DISABLE_SAMPLER_PREFETCH);
2447
2448                 /* Wa_1409178092:icl */
2449                 wa_mcr_write_clr_set(wal,
2450                                      GEN11_SCRATCH2,
2451                                      GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
2452                                      0);
2453
2454                 /* WaEnable32PlaneMode:icl */
2455                 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
2456                              GEN11_ENABLE_32_PLANE_MODE);
2457
2458                 /*
2459                  * Wa_1408767742:icl[a2..forever],ehl[all]
2460                  * Wa_1605460711:icl[a0..c0]
2461                  */
2462                 wa_write_or(wal,
2463                             GEN7_FF_THREAD_MODE,
2464                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
2465
2466                 /* Wa_22010271021 */
2467                 wa_masked_en(wal,
2468                              GEN9_CS_DEBUG_MODE1,
2469                              FF_DOP_CLOCK_GATE_DISABLE);
2470         }
2471
2472         /*
2473          * Intel platforms that support fine-grained preemption (i.e., gen9 and
2474          * beyond) allow the kernel-mode driver to choose between two different
2475          * options for controlling preemption granularity and behavior.
2476          *
2477          * Option 1 (hardware default):
2478          *   Preemption settings are controlled in a global manner via
2479          *   kernel-only register CS_DEBUG_MODE1 (0x20EC).  Any granularity
2480          *   and settings chosen by the kernel-mode driver will apply to all
2481          *   userspace clients.
2482          *
2483          * Option 2:
2484          *   Preemption settings are controlled on a per-context basis via
2485          *   register CS_CHICKEN1 (0x2580).  CS_CHICKEN1 is saved/restored on
2486          *   context switch and is writable by userspace (e.g., via
2487          *   MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer)
2488          *   which allows different userspace drivers/clients to select
2489          *   different settings, or to change those settings on the fly in
2490          *   response to runtime needs.  This option was known by name
2491          *   "FtrPerCtxtPreemptionGranularityControl" at one time, although
2492          *   that name is somewhat misleading as other non-granularity
2493          *   preemption settings are also impacted by this decision.
2494          *
2495          * On Linux, our policy has always been to let userspace drivers
2496          * control preemption granularity/settings (Option 2).  This was
2497          * originally mandatory on gen9 to prevent ABI breakage (old gen9
2498          * userspace developed before object-level preemption was enabled would
2499          * not behave well if i915 were to go with Option 1 and enable that
2500          * preemption in a global manner).  On gen9 each context would have
2501          * object-level preemption disabled by default (see
2502          * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but
2503          * userspace drivers could opt-in to object-level preemption as they
2504          * saw fit.  For post-gen9 platforms, we continue to utilize Option 2;
2505          * even though it is no longer necessary for ABI compatibility when
2506          * enabling a new platform, it does ensure that userspace will be able
2507          * to implement any workarounds that show up requiring temporary
2508          * adjustments to preemption behavior at runtime.
2509          *
2510          * Notes/Workarounds:
2511          *  - Wa_14015141709:  On DG2 and early steppings of MTL,
2512          *      CS_CHICKEN1[0] does not disable object-level preemption as
2513          *      it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been
2514          *      using Option 1).  Effectively this means userspace is unable
2515          *      to disable object-level preemption on these platforms/steppings
2516          *      despite the setting here.
2517          *
2518          *  - Wa_16013994831:  May require that userspace program
2519          *      CS_CHICKEN1[10] when certain runtime conditions are true.
2520          *      Userspace requires Option 2 to be in effect for their update of
2521          *      CS_CHICKEN1[10] to be effective.
2522          *
2523          * Other workarounds may appear in the future that will also require
2524          * Option 2 behavior to allow proper userspace implementation.
2525          */
2526         if (GRAPHICS_VER(i915) >= 9)
2527                 wa_masked_en(wal,
2528                              GEN7_FF_SLICE_CS_CHICKEN1,
2529                              GEN9_FFSC_PERCTX_PREEMPT_CTRL);
2530
2531         if (IS_SKYLAKE(i915) ||
2532             IS_KABYLAKE(i915) ||
2533             IS_COFFEELAKE(i915) ||
2534             IS_COMETLAKE(i915)) {
2535                 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
2536                 wa_write_or(wal,
2537                             GEN8_GARBCNTL,
2538                             GEN9_GAPS_TSV_CREDIT_DISABLE);
2539         }
2540
2541         if (IS_BROXTON(i915)) {
2542                 /* WaDisablePooledEuLoadBalancingFix:bxt */
2543                 wa_masked_en(wal,
2544                              FF_SLICE_CS_CHICKEN2,
2545                              GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
2546         }
2547
2548         if (GRAPHICS_VER(i915) == 9) {
2549                 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
2550                 wa_masked_en(wal,
2551                              GEN9_CSFE_CHICKEN1_RCS,
2552                              GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
2553
2554                 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
2555                 wa_mcr_write_or(wal,
2556                                 BDW_SCRATCH1,
2557                                 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
2558
2559                 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
2560                 if (IS_GEN9_LP(i915))
2561                         wa_mcr_write_clr_set(wal,
2562                                              GEN8_L3SQCREG1,
2563                                              L3_PRIO_CREDITS_MASK,
2564                                              L3_GENERAL_PRIO_CREDITS(62) |
2565                                              L3_HIGH_PRIO_CREDITS(2));
2566
2567                 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
2568                 wa_mcr_write_or(wal,
2569                                 GEN8_L3SQCREG4,
2570                                 GEN8_LQSC_FLUSH_COHERENT_LINES);
2571
2572                 /* Disable atomics in L3 to prevent unrecoverable hangs */
2573                 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
2574                                  GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
2575                 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,
2576                                      GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
2577                 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,
2578                                      EVICTION_PERF_FIX_ENABLE, 0);
2579         }
2580
2581         if (IS_HASWELL(i915)) {
2582                 /* WaSampleCChickenBitEnable:hsw */
2583                 wa_masked_en(wal,
2584                              HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
2585
2586                 wa_masked_dis(wal,
2587                               CACHE_MODE_0_GEN7,
2588                               /* enable HiZ Raw Stall Optimization */
2589                               HIZ_RAW_STALL_OPT_DISABLE);
2590         }
2591
2592         if (IS_VALLEYVIEW(i915)) {
2593                 /* WaDisableEarlyCull:vlv */
2594                 wa_masked_en(wal,
2595                              _3D_CHICKEN3,
2596                              _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
2597
2598                 /*
2599                  * WaVSThreadDispatchOverride:ivb,vlv
2600                  *
2601                  * This actually overrides the dispatch
2602                  * mode for all thread types.
2603                  */
2604                 wa_write_clr_set(wal,
2605                                  GEN7_FF_THREAD_MODE,
2606                                  GEN7_FF_SCHED_MASK,
2607                                  GEN7_FF_TS_SCHED_HW |
2608                                  GEN7_FF_VS_SCHED_HW |
2609                                  GEN7_FF_DS_SCHED_HW);
2610
2611                 /* WaPsdDispatchEnable:vlv */
2612                 /* WaDisablePSDDualDispatchEnable:vlv */
2613                 wa_masked_en(wal,
2614                              GEN7_HALF_SLICE_CHICKEN1,
2615                              GEN7_MAX_PS_THREAD_DEP |
2616                              GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2617         }
2618
2619         if (IS_IVYBRIDGE(i915)) {
2620                 /* WaDisableEarlyCull:ivb */
2621                 wa_masked_en(wal,
2622                              _3D_CHICKEN3,
2623                              _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
2624
2625                 if (0) { /* causes HiZ corruption on ivb:gt1 */
2626                         /* enable HiZ Raw Stall Optimization */
2627                         wa_masked_dis(wal,
2628                                       CACHE_MODE_0_GEN7,
2629                                       HIZ_RAW_STALL_OPT_DISABLE);
2630                 }
2631
2632                 /*
2633                  * WaVSThreadDispatchOverride:ivb,vlv
2634                  *
2635                  * This actually overrides the dispatch
2636                  * mode for all thread types.
2637                  */
2638                 wa_write_clr_set(wal,
2639                                  GEN7_FF_THREAD_MODE,
2640                                  GEN7_FF_SCHED_MASK,
2641                                  GEN7_FF_TS_SCHED_HW |
2642                                  GEN7_FF_VS_SCHED_HW |
2643                                  GEN7_FF_DS_SCHED_HW);
2644
2645                 /* WaDisablePSDDualDispatchEnable:ivb */
2646                 if (IS_IVB_GT1(i915))
2647                         wa_masked_en(wal,
2648                                      GEN7_HALF_SLICE_CHICKEN1,
2649                                      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2650         }
2651
2652         if (GRAPHICS_VER(i915) == 7) {
2653                 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
2654                 wa_masked_en(wal,
2655                              RING_MODE_GEN7(RENDER_RING_BASE),
2656                              GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
2657
2658                 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
2659                 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
2660
2661                 /*
2662                  * BSpec says this must be set, even though
2663                  * WaDisable4x2SubspanOptimization:ivb,hsw
2664                  * WaDisable4x2SubspanOptimization isn't listed for VLV.
2665                  */
2666                 wa_masked_en(wal,
2667                              CACHE_MODE_1,
2668                              PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
2669
2670                 /*
2671                  * BSpec recommends 8x4 when MSAA is used,
2672                  * however in practice 16x4 seems fastest.
2673                  *
2674                  * Note that PS/WM thread counts depend on the WIZ hashing
2675                  * disable bit, which we don't touch here, but it's good
2676                  * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
2677                  */
2678                 wa_masked_field_set(wal,
2679                                     GEN7_GT_MODE,
2680                                     GEN6_WIZ_HASHING_MASK,
2681                                     GEN6_WIZ_HASHING_16x4);
2682         }
2683
2684         if (IS_GRAPHICS_VER(i915, 6, 7))
2685                 /*
2686                  * We need to disable the AsyncFlip performance optimisations in
2687                  * order to use MI_WAIT_FOR_EVENT within the CS. It should
2688                  * already be programmed to '1' on all products.
2689                  *
2690                  * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
2691                  */
2692                 wa_masked_en(wal,
2693                              RING_MI_MODE(RENDER_RING_BASE),
2694                              ASYNC_FLIP_PERF_DISABLE);
2695
2696         if (GRAPHICS_VER(i915) == 6) {
2697                 /*
2698                  * Required for the hardware to program scanline values for
2699                  * waiting
2700                  * WaEnableFlushTlbInvalidationMode:snb
2701                  */
2702                 wa_masked_en(wal,
2703                              GFX_MODE,
2704                              GFX_TLB_INVALIDATE_EXPLICIT);
2705
2706                 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
2707                 wa_masked_en(wal,
2708                              _3D_CHICKEN,
2709                              _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
2710
2711                 wa_masked_en(wal,
2712                              _3D_CHICKEN3,
2713                              /* WaStripsFansDisableFastClipPerformanceFix:snb */
2714                              _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
2715                              /*
2716                               * Bspec says:
2717                               * "This bit must be set if 3DSTATE_CLIP clip mode is set
2718                               * to normal and 3DSTATE_SF number of SF output attributes
2719                               * is more than 16."
2720                               */
2721                              _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
2722
2723                 /*
2724                  * BSpec recommends 8x4 when MSAA is used,
2725                  * however in practice 16x4 seems fastest.
2726                  *
2727                  * Note that PS/WM thread counts depend on the WIZ hashing
2728                  * disable bit, which we don't touch here, but it's good
2729                  * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
2730                  */
2731                 wa_masked_field_set(wal,
2732                                     GEN6_GT_MODE,
2733                                     GEN6_WIZ_HASHING_MASK,
2734                                     GEN6_WIZ_HASHING_16x4);
2735
2736                 /* WaDisable_RenderCache_OperationalFlush:snb */
2737                 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
2738
2739                 /*
2740                  * From the Sandybridge PRM, volume 1 part 3, page 24:
2741                  * "If this bit is set, STCunit will have LRA as replacement
2742                  *  policy. [...] This bit must be reset. LRA replacement
2743                  *  policy is not supported."
2744                  */
2745                 wa_masked_dis(wal,
2746                               CACHE_MODE_0,
2747                               CM0_STC_EVICT_DISABLE_LRA_SNB);
2748         }
2749
2750         if (IS_GRAPHICS_VER(i915, 4, 6))
2751                 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
2752                 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
2753                        0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
2754                        /* XXX bit doesn't stick on Broadwater */
2755                        IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);
2756
2757         if (GRAPHICS_VER(i915) == 4)
2758                 /*
2759                  * Disable CONSTANT_BUFFER before it is loaded from the context
2760                  * image. For as it is loaded, it is executed and the stored
2761                  * address may no longer be valid, leading to a GPU hang.
2762                  *
2763                  * This imposes the requirement that userspace reload their
2764                  * CONSTANT_BUFFER on every batch, fortunately a requirement
2765                  * they are already accustomed to from before contexts were
2766                  * enabled.
2767                  */
2768                 wa_add(wal, ECOSKPD(RENDER_RING_BASE),
2769                        0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
2770                        0 /* XXX bit doesn't stick on Broadwater */,
2771                        true);
2772 }
2773
2774 static void
2775 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2776 {
2777         struct drm_i915_private *i915 = engine->i915;
2778
2779         /* WaKBLVECSSemaphoreWaitPoll:kbl */
2780         if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
2781                 wa_write(wal,
2782                          RING_SEMA_WAIT_POLL(engine->mmio_base),
2783                          1);
2784         }
2785 }
2786
2787 static void
2788 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2789 {
2790         if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
2791                 /* Wa_14014999345:pvc */
2792                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
2793         }
2794 }
2795
2796 /*
2797  * The bspec performance guide has recommended MMIO tuning settings.  These
2798  * aren't truly "workarounds" but we want to program them with the same
2799  * workaround infrastructure to ensure that they're automatically added to
2800  * the GuC save/restore lists, re-applied at the right times, and checked for
2801  * any conflicting programming requested by real workarounds.
2802  *
2803  * Programming settings should be added here only if their registers are not
2804  * part of an engine's register state context.  If a register is part of a
2805  * context, then any tuning settings should be programmed in an appropriate
2806  * function invoked by __intel_engine_init_ctx_wa().
2807  */
2808 static void
2809 add_render_compute_tuning_settings(struct intel_gt *gt,
2810                                    struct i915_wa_list *wal)
2811 {
2812         struct drm_i915_private *i915 = gt->i915;
2813
2814         if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
2815                 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
2816
2817         /*
2818          * This tuning setting proves beneficial only on ATS-M designs; the
2819          * default "age based" setting is optimal on regular DG2 and other
2820          * platforms.
2821          */
2822         if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
2823                 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
2824                                         THREAD_EX_ARB_MODE_RR_AFTER_DEP);
2825
2826         if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
2827                 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
2828 }
2829
2830 /*
2831  * The workarounds in this function apply to shared registers in
2832  * the general render reset domain that aren't tied to a
2833  * specific engine.  Since all render+compute engines get reset
2834  * together, and the contents of these registers are lost during
2835  * the shared render domain reset, we'll define such workarounds
2836  * here and then add them to just a single RCS or CCS engine's
2837  * workaround list (whichever engine has the XXXX flag).
2838  */
2839 static void
2840 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2841 {
2842         struct drm_i915_private *i915 = engine->i915;
2843         struct intel_gt *gt = engine->gt;
2844
2845         add_render_compute_tuning_settings(gt, wal);
2846
2847         if (GRAPHICS_VER(i915) >= 11) {
2848                 /* This is not a Wa (although referred to as
2849                  * WaSetInidrectStateOverride in places), this allows
2850                  * applications that reference sampler states through
2851                  * the BindlessSamplerStateBaseAddress to have their
2852                  * border color relative to DynamicStateBaseAddress
2853                  * rather than BindlessSamplerStateBaseAddress.
2854                  *
2855                  * Otherwise SAMPLER_STATE border colors have to be
2856                  * copied in multiple heaps (DynamicStateBaseAddress &
2857                  * BindlessSamplerStateBaseAddress)
2858                  *
2859                  * BSpec: 46052
2860                  */
2861                 wa_mcr_masked_en(wal,
2862                                  GEN10_SAMPLER_MODE,
2863                                  GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
2864         }
2865
2866         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
2867             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
2868                 /* Wa_14017856879 */
2869                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
2870
2871         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2872             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
2873                 /*
2874                  * Wa_14017066071
2875                  * Wa_14017654203
2876                  */
2877                 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2878                                  MTL_DISABLE_SAMPLER_SC_OOO);
2879
2880         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
2881                 /* Wa_22015279794 */
2882                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2883                                  DISABLE_PREFETCH_INTO_IC);
2884
2885         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2886             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
2887             IS_DG2(i915)) {
2888                 /* Wa_22013037850 */
2889                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
2890                                 DISABLE_128B_EVICTION_COMMAND_UDW);
2891
2892                 /* Wa_18017747507 */
2893                 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
2894         }
2895
2896         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2897             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
2898             IS_PONTEVECCHIO(i915) ||
2899             IS_DG2(i915)) {
2900                 /* Wa_22014226127 */
2901                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
2902         }
2903
2904         if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
2905                 /* Wa_14015227452:dg2,pvc */
2906                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
2907
2908                 /* Wa_16015675438:dg2,pvc */
2909                 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
2910         }
2911
2912         if (IS_DG2(i915)) {
2913                 /*
2914                  * Wa_16011620976:dg2_g11
2915                  * Wa_22015475538:dg2
2916                  */
2917                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
2918         }
2919
2920         if (IS_DG2_G11(i915)) {
2921                 /*
2922                  * Wa_22012826095:dg2
2923                  * Wa_22013059131:dg2
2924                  */
2925                 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
2926                                      MAXREQS_PER_BANK,
2927                                      REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
2928
2929                 /* Wa_22013059131:dg2 */
2930                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
2931                                 FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
2932
2933                 /*
2934                  * Wa_22012654132
2935                  *
2936                  * Note that register 0xE420 is write-only and cannot be read
2937                  * back for verification on DG2 (due to Wa_14012342262), so
2938                  * we need to explicitly skip the readback.
2939                  */
2940                 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
2941                            _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
2942                            0 /* write-only, so skip validation */,
2943                            true);
2944         }
2945
2946         if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) {
2947                 /* Wa_18028616096 */
2948                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);
2949         }
2950
2951         if (IS_XEHPSDV(i915)) {
2952                 /* Wa_1409954639 */
2953                 wa_mcr_masked_en(wal,
2954                                  GEN8_ROW_CHICKEN,
2955                                  SYSTOLIC_DOP_CLOCK_GATING_DIS);
2956
2957                 /* Wa_1607196519 */
2958                 wa_mcr_masked_en(wal,
2959                                  GEN9_ROW_CHICKEN4,
2960                                  GEN12_DISABLE_GRF_CLEAR);
2961
2962                 /* Wa_14010449647:xehpsdv */
2963                 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
2964                                  GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2965         }
2966 }
2967
2968 static void
2969 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2970 {
2971         if (GRAPHICS_VER(engine->i915) < 4)
2972                 return;
2973
2974         engine_fake_wa_init(engine, wal);
2975
2976         /*
2977          * These are common workarounds that just need to applied
2978          * to a single RCS/CCS engine's workaround list since
2979          * they're reset as part of the general render domain reset.
2980          */
2981         if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
2982                 general_render_compute_wa_init(engine, wal);
2983
2984         if (engine->class == COMPUTE_CLASS)
2985                 ccs_engine_wa_init(engine, wal);
2986         else if (engine->class == RENDER_CLASS)
2987                 rcs_engine_wa_init(engine, wal);
2988         else
2989                 xcs_engine_wa_init(engine, wal);
2990 }
2991
2992 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
2993 {
2994         struct i915_wa_list *wal = &engine->wa_list;
2995
2996         wa_init_start(wal, engine->gt, "engine", engine->name);
2997         engine_init_workarounds(engine, wal);
2998         wa_init_finish(wal);
2999 }
3000
3001 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
3002 {
3003         wa_list_apply(&engine->wa_list);
3004 }
3005
3006 static const struct i915_range mcr_ranges_gen8[] = {
3007         { .start = 0x5500, .end = 0x55ff },
3008         { .start = 0x7000, .end = 0x7fff },
3009         { .start = 0x9400, .end = 0x97ff },
3010         { .start = 0xb000, .end = 0xb3ff },
3011         { .start = 0xe000, .end = 0xe7ff },
3012         {},
3013 };
3014
3015 static const struct i915_range mcr_ranges_gen12[] = {
3016         { .start =  0x8150, .end =  0x815f },
3017         { .start =  0x9520, .end =  0x955f },
3018         { .start =  0xb100, .end =  0xb3ff },
3019         { .start =  0xde80, .end =  0xe8ff },
3020         { .start = 0x24a00, .end = 0x24a7f },
3021         {},
3022 };
3023
3024 static const struct i915_range mcr_ranges_xehp[] = {
3025         { .start =  0x4000, .end =  0x4aff },
3026         { .start =  0x5200, .end =  0x52ff },
3027         { .start =  0x5400, .end =  0x7fff },
3028         { .start =  0x8140, .end =  0x815f },
3029         { .start =  0x8c80, .end =  0x8dff },
3030         { .start =  0x94d0, .end =  0x955f },
3031         { .start =  0x9680, .end =  0x96ff },
3032         { .start =  0xb000, .end =  0xb3ff },
3033         { .start =  0xc800, .end =  0xcfff },
3034         { .start =  0xd800, .end =  0xd8ff },
3035         { .start =  0xdc00, .end =  0xffff },
3036         { .start = 0x17000, .end = 0x17fff },
3037         { .start = 0x24a00, .end = 0x24a7f },
3038         {},
3039 };
3040
3041 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
3042 {
3043         const struct i915_range *mcr_ranges;
3044         int i;
3045
3046         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
3047                 mcr_ranges = mcr_ranges_xehp;
3048         else if (GRAPHICS_VER(i915) >= 12)
3049                 mcr_ranges = mcr_ranges_gen12;
3050         else if (GRAPHICS_VER(i915) >= 8)
3051                 mcr_ranges = mcr_ranges_gen8;
3052         else
3053                 return false;
3054
3055         /*
3056          * Registers in these ranges are affected by the MCR selector
3057          * which only controls CPU initiated MMIO. Routing does not
3058          * work for CS access so we cannot verify them on this path.
3059          */
3060         for (i = 0; mcr_ranges[i].start; i++)
3061                 if (offset >= mcr_ranges[i].start &&
3062                     offset <= mcr_ranges[i].end)
3063                         return true;
3064
3065         return false;
3066 }
3067
3068 static int
3069 wa_list_srm(struct i915_request *rq,
3070             const struct i915_wa_list *wal,
3071             struct i915_vma *vma)
3072 {
3073         struct drm_i915_private *i915 = rq->i915;
3074         unsigned int i, count = 0;
3075         const struct i915_wa *wa;
3076         u32 srm, *cs;
3077
3078         srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
3079         if (GRAPHICS_VER(i915) >= 8)
3080                 srm++;
3081
3082         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3083                 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
3084                         count++;
3085         }
3086
3087         cs = intel_ring_begin(rq, 4 * count);
3088         if (IS_ERR(cs))
3089                 return PTR_ERR(cs);
3090
3091         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3092                 u32 offset = i915_mmio_reg_offset(wa->reg);
3093
3094                 if (mcr_range(i915, offset))
3095                         continue;
3096
3097                 *cs++ = srm;
3098                 *cs++ = offset;
3099                 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
3100                 *cs++ = 0;
3101         }
3102         intel_ring_advance(rq, cs);
3103
3104         return 0;
3105 }
3106
3107 static int engine_wa_list_verify(struct intel_context *ce,
3108                                  const struct i915_wa_list * const wal,
3109                                  const char *from)
3110 {
3111         const struct i915_wa *wa;
3112         struct i915_request *rq;
3113         struct i915_vma *vma;
3114         struct i915_gem_ww_ctx ww;
3115         unsigned int i;
3116         u32 *results;
3117         int err;
3118
3119         if (!wal->count)
3120                 return 0;
3121
3122         vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm,
3123                                            wal->count * sizeof(u32));
3124         if (IS_ERR(vma))
3125                 return PTR_ERR(vma);
3126
3127         intel_engine_pm_get(ce->engine);
3128         i915_gem_ww_ctx_init(&ww, false);
3129 retry:
3130         err = i915_gem_object_lock(vma->obj, &ww);
3131         if (err == 0)
3132                 err = intel_context_pin_ww(ce, &ww);
3133         if (err)
3134                 goto err_pm;
3135
3136         err = i915_vma_pin_ww(vma, &ww, 0, 0,
3137                            i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
3138         if (err)
3139                 goto err_unpin;
3140
3141         rq = i915_request_create(ce);
3142         if (IS_ERR(rq)) {
3143                 err = PTR_ERR(rq);
3144                 goto err_vma;
3145         }
3146
3147         err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
3148         if (err == 0)
3149                 err = wa_list_srm(rq, wal, vma);
3150
3151         i915_request_get(rq);
3152         if (err)
3153                 i915_request_set_error_once(rq, err);
3154         i915_request_add(rq);
3155
3156         if (err)
3157                 goto err_rq;
3158
3159         if (i915_request_wait(rq, 0, HZ / 5) < 0) {
3160                 err = -ETIME;
3161                 goto err_rq;
3162         }
3163
3164         results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
3165         if (IS_ERR(results)) {
3166                 err = PTR_ERR(results);
3167                 goto err_rq;
3168         }
3169
3170         err = 0;
3171         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3172                 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
3173                         continue;
3174
3175                 if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
3176                         err = -ENXIO;
3177         }
3178
3179         i915_gem_object_unpin_map(vma->obj);
3180
3181 err_rq:
3182         i915_request_put(rq);
3183 err_vma:
3184         i915_vma_unpin(vma);
3185 err_unpin:
3186         intel_context_unpin(ce);
3187 err_pm:
3188         if (err == -EDEADLK) {
3189                 err = i915_gem_ww_ctx_backoff(&ww);
3190                 if (!err)
3191                         goto retry;
3192         }
3193         i915_gem_ww_ctx_fini(&ww);
3194         intel_engine_pm_put(ce->engine);
3195         i915_vma_put(vma);
3196         return err;
3197 }
3198
3199 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
3200                                     const char *from)
3201 {
3202         return engine_wa_list_verify(engine->kernel_context,
3203                                      &engine->wa_list,
3204                                      from);
3205 }
3206
3207 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3208 #include "selftest_workarounds.c"
3209 #endif