2 * Copyright (c) 2015 Intel Corporation
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include "intel_engine.h"
27 #include "intel_mocs.h"
28 #include "intel_lrc.h"
29 #include "intel_ring.h"
31 /* structures required */
32 struct drm_i915_mocs_entry {
38 struct drm_i915_mocs_table {
40 unsigned int n_entries;
41 const struct drm_i915_mocs_entry *table;
44 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
45 #define _LE_CACHEABILITY(value) ((value) << 0)
46 #define _LE_TGT_CACHE(value) ((value) << 2)
47 #define LE_LRUM(value) ((value) << 4)
48 #define LE_AOM(value) ((value) << 6)
49 #define LE_RSC(value) ((value) << 7)
50 #define LE_SCC(value) ((value) << 8)
51 #define LE_PFM(value) ((value) << 11)
52 #define LE_SCF(value) ((value) << 14)
53 #define LE_COS(value) ((value) << 15)
54 #define LE_SSE(value) ((value) << 17)
56 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
57 #define L3_ESC(value) ((value) << 0)
58 #define L3_SCC(value) ((value) << 1)
59 #define _L3_CACHEABILITY(value) ((value) << 4)
62 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
63 #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
65 /* (e)LLC caching options */
67 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
70 #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
71 #define LE_1_UC _LE_CACHEABILITY(1)
72 #define LE_2_WT _LE_CACHEABILITY(2)
73 #define LE_3_WB _LE_CACHEABILITY(3)
76 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
77 #define LE_TC_1_LLC _LE_TGT_CACHE(1)
78 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
79 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
81 /* L3 caching options */
82 #define L3_0_DIRECT _L3_CACHEABILITY(0)
83 #define L3_1_UC _L3_CACHEABILITY(1)
84 #define L3_2_RESERVED _L3_CACHEABILITY(2)
85 #define L3_3_WB _L3_CACHEABILITY(3)
87 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
89 .control_value = __control_value, \
90 .l3cc_value = __l3cc_value, \
97 * These are the MOCS tables that are programmed across all the rings.
98 * The control value is programmed to all the rings that support the
99 * MOCS registers. While the l3cc_values are only programmed to the
100 * LNCFCMOCS0 - LNCFCMOCS32 registers.
102 * These tables are intended to be kept reasonably consistent across
103 * HW platforms, and for ICL+, be identical across OSes. To achieve
104 * that, for Icelake and above, list of entries is published as part
107 * Entries not part of the following tables are undefined as far as
108 * userspace is concerned and shouldn't be relied upon. For Gen < 12
109 * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
110 * PTE and will be initialized to an invalid value.
112 * The last two entries are reserved by the hardware. For ICL+ they
113 * should be initialized according to bspec and never used, for older
114 * platforms they should never be written to.
116 * NOTE: These tables are part of bspec and defined as part of hardware
117 * interface for ICL+. For older platforms, they are part of kernel
118 * ABI. It is expected that, for specific hardware platform, existing
119 * entries will remain constant and the table will only be updated by
120 * adding new entries, filling unused positions.
122 #define GEN9_MOCS_ENTRIES \
123 MOCS_ENTRY(I915_MOCS_UNCACHED, \
124 LE_1_UC | LE_TC_2_LLC_ELLC, \
126 MOCS_ENTRY(I915_MOCS_PTE, \
127 LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
130 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
132 MOCS_ENTRY(I915_MOCS_CACHED,
133 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
137 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
138 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
140 MOCS_ENTRY(I915_MOCS_CACHED,
141 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
145 #define GEN11_MOCS_ENTRIES \
146 /* Entries 0 and 1 are defined per-platform */ \
147 /* Base - L3 + LLC */ \
149 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
151 /* Base - Uncached */ \
153 LE_1_UC | LE_TC_1_LLC, \
157 LE_1_UC | LE_TC_1_LLC, \
161 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
165 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
167 /* Age 0 - L3 + LLC */ \
169 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
171 /* Age: Don't Chg. - LLC */ \
173 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
175 /* Age: Don't Chg. - L3 + LLC */ \
177 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
181 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
183 /* No AOM - L3 + LLC */ \
185 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
187 /* No AOM; Age 0 - LLC */ \
189 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
191 /* No AOM; Age 0 - L3 + LLC */ \
193 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
195 /* No AOM; Age:DC - LLC */ \
197 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
199 /* No AOM; Age:DC - L3 + LLC */ \
201 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
203 /* Self-Snoop - L3 + LLC */ \
205 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
207 /* Skip Caching - L3 + LLC(12.5%) */ \
209 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
211 /* Skip Caching - L3 + LLC(25%) */ \
213 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
215 /* Skip Caching - L3 + LLC(50%) */ \
217 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
219 /* Skip Caching - L3 + LLC(75%) */ \
221 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
223 /* Skip Caching - L3 + LLC(87.5%) */ \
225 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
227 /* HW Reserved - SW program but never use */ \
229 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
231 /* HW Reserved - SW program but never use */ \
233 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
236 static const struct drm_i915_mocs_entry tigerlake_mocs_table[] = {
237 /* Base - Error (Reserved for Non-Use) */
238 MOCS_ENTRY(0, 0x0, 0x0),
239 /* Base - Reserved */
240 MOCS_ENTRY(1, 0x0, 0x0),
244 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
246 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
248 /* Implicitly enable L1 - HDC:L1 + L3 */
250 LE_1_UC | LE_TC_1_LLC,
252 /* Implicitly enable L1 - HDC:L1 + LLC */
254 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
256 /* Implicitly enable L1 - HDC:L1 */
258 LE_1_UC | LE_TC_1_LLC,
260 /* HW Special Case (CCS) */
262 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
264 /* HW Special Case (Displayable) */
266 LE_1_UC | LE_TC_1_LLC,
270 static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
271 /* Base - Uncached (Deprecated) */
272 MOCS_ENTRY(I915_MOCS_UNCACHED,
273 LE_1_UC | LE_TC_1_LLC,
275 /* Base - L3 + LeCC:PAT (Deprecated) */
276 MOCS_ENTRY(I915_MOCS_PTE,
277 LE_0_PAGETABLE | LE_TC_1_LLC,
283 static bool get_mocs_settings(const struct drm_i915_private *i915,
284 struct drm_i915_mocs_table *table)
288 if (INTEL_GEN(i915) >= 12) {
289 table->size = ARRAY_SIZE(tigerlake_mocs_table);
290 table->table = tigerlake_mocs_table;
291 table->n_entries = GEN11_NUM_MOCS_ENTRIES;
293 } else if (IS_GEN(i915, 11)) {
294 table->size = ARRAY_SIZE(icelake_mocs_table);
295 table->table = icelake_mocs_table;
296 table->n_entries = GEN11_NUM_MOCS_ENTRIES;
298 } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
299 table->size = ARRAY_SIZE(skylake_mocs_table);
300 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
301 table->table = skylake_mocs_table;
303 } else if (IS_GEN9_LP(i915)) {
304 table->size = ARRAY_SIZE(broxton_mocs_table);
305 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
306 table->table = broxton_mocs_table;
309 WARN_ONCE(INTEL_GEN(i915) >= 9,
310 "Platform that should have a MOCS table does not.\n");
313 /* WaDisableSkipCaching:skl,bxt,kbl,glk */
314 if (IS_GEN(i915, 9)) {
317 for (i = 0; i < table->size; i++)
318 if (WARN_ON(table->table[i].l3cc_value &
319 (L3_ESC(1) | L3_SCC(0x7))))
326 static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
328 switch (engine->id) {
330 return GEN9_GFX_MOCS(index);
332 return GEN9_MFX0_MOCS(index);
334 return GEN9_BLT_MOCS(index);
336 return GEN9_VEBOX_MOCS(index);
338 return GEN9_MFX1_MOCS(index);
340 return GEN11_MFX2_MOCS(index);
342 MISSING_CASE(engine->id);
343 return INVALID_MMIO_REG;
348 * Get control_value from MOCS entry taking into account when it's not used:
349 * I915_MOCS_PTE's value is returned in this case.
351 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
354 if (table->table[index].used)
355 return table->table[index].control_value;
357 return table->table[I915_MOCS_PTE].control_value;
360 static void init_mocs_table(struct intel_engine_cs *engine,
361 const struct drm_i915_mocs_table *table)
363 struct intel_uncore *uncore = engine->uncore;
364 u32 unused_value = table->table[I915_MOCS_PTE].control_value;
367 for (i = 0; i < table->size; i++)
368 intel_uncore_write_fw(uncore,
369 mocs_register(engine, i),
370 get_entry_control(table, i));
372 /* All remaining entries are unused */
373 for (; i < table->n_entries; i++)
374 intel_uncore_write_fw(uncore,
375 mocs_register(engine, i),
380 * Get l3cc_value from MOCS entry taking into account when it's not used:
381 * I915_MOCS_PTE's value is returned in this case.
383 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
386 if (table->table[index].used)
387 return table->table[index].l3cc_value;
389 return table->table[I915_MOCS_PTE].l3cc_value;
392 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
396 return low | (u32)high << 16;
399 static void init_l3cc_table(struct intel_engine_cs *engine,
400 const struct drm_i915_mocs_table *table)
402 struct intel_uncore *uncore = engine->uncore;
403 u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
406 for (i = 0; i < table->size / 2; i++) {
407 u16 low = get_entry_l3cc(table, 2 * i);
408 u16 high = get_entry_l3cc(table, 2 * i + 1);
410 intel_uncore_write(uncore,
412 l3cc_combine(table, low, high));
415 /* Odd table size - 1 left over */
416 if (table->size & 1) {
417 u16 low = get_entry_l3cc(table, 2 * i);
419 intel_uncore_write(uncore,
421 l3cc_combine(table, low, unused_value));
425 /* All remaining entries are also unused */
426 for (; i < table->n_entries / 2; i++)
427 intel_uncore_write(uncore,
429 l3cc_combine(table, unused_value,
433 void intel_mocs_init_engine(struct intel_engine_cs *engine)
435 struct drm_i915_mocs_table table;
437 /* Called under a blanket forcewake */
438 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
440 if (!get_mocs_settings(engine->i915, &table))
443 /* Platforms with global MOCS do not need per-engine initialization. */
444 if (!HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
445 init_mocs_table(engine, &table);
447 if (engine->class == RENDER_CLASS)
448 init_l3cc_table(engine, &table);
451 static void intel_mocs_init_global(struct intel_gt *gt)
453 struct intel_uncore *uncore = gt->uncore;
454 struct drm_i915_mocs_table table;
458 * LLC and eDRAM control values are not applicable to dgfx
460 if (IS_DGFX(gt->i915))
463 GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
465 if (!get_mocs_settings(gt->i915, &table))
468 if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
471 for (index = 0; index < table.size; index++)
472 intel_uncore_write(uncore,
473 GEN12_GLOBAL_MOCS(index),
474 table.table[index].control_value);
477 * Ok, now set the unused entries to the invalid entry (index 0). These
478 * entries are officially undefined and no contract for the contents and
479 * settings is given for these entries.
481 for (; index < table.n_entries; index++)
482 intel_uncore_write(uncore,
483 GEN12_GLOBAL_MOCS(index),
484 table.table[0].control_value);
487 void intel_mocs_init(struct intel_gt *gt)
489 if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
490 intel_mocs_init_global(gt);