1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
7 #include "intel_context.h"
8 #include "intel_gpu_commands.h"
10 #include "intel_gtt.h"
11 #include "intel_migrate.h"
12 #include "intel_ring.h"
13 #include "gem/i915_gem_lmem.h"
15 struct insert_pte_data {
19 #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
21 #define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \
22 DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0)
23 static bool engine_supports_migration(struct intel_engine_cs *engine)
29 * We need the ability to prevent aribtration (MI_ARB_ON_OFF),
30 * the ability to write PTE using inline data (MI_STORE_DATA)
31 * and of course the ability to do the block transfer (blits).
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS);
38 static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
39 struct i915_page_table *pt,
42 struct insert_pte_data *d = data;
45 * Insert a dummy PTE into every PT that will map to LMEM to ensure
46 * we have a correctly setup PDE structure for later use.
48 vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);
49 GEM_BUG_ON(!pt->is_compact);
53 static void xehpsdv_insert_pte(struct i915_address_space *vm,
54 struct i915_page_table *pt,
57 struct insert_pte_data *d = data;
60 * We are playing tricks here, since the actual pt, from the hw
61 * pov, is only 256bytes with 32 entries, or 4096bytes with 512
62 * entries, but we are still guaranteed that the physical
63 * alignment is 64K underneath for the pt, and we are careful
64 * not to access the space in the void.
66 vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
70 static void insert_pte(struct i915_address_space *vm,
71 struct i915_page_table *pt,
74 struct insert_pte_data *d = data;
76 vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
77 i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
78 d->offset += PAGE_SIZE;
81 static struct i915_address_space *migrate_vm(struct intel_gt *gt)
83 struct i915_vm_pt_stash stash = {};
84 struct i915_ppgtt *vm;
89 * We construct a very special VM for use by all migration contexts,
90 * it is kept pinned so that it can be used at any time. As we need
91 * to pre-allocate the page directories for the migration VM, this
92 * limits us to only using a small number of prepared vma.
94 * To be able to pipeline and reschedule migration operations while
95 * avoiding unnecessary contention on the vm itself, the PTE updates
96 * are inline with the blits. All the blits use the same fixed
97 * addresses, with the backing store redirection being updated on the
98 * fly. Only 2 implicit vma are used for all migration operations.
100 * We lay the ppGTT out as:
102 * [0, CHUNK_SZ) -> first object
103 * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object
104 * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE
106 * By exposing the dma addresses of the page directories themselves
107 * within the ppGTT, we are then able to rewrite the PTE prior to use.
108 * But the PTE update and subsequent migration operation must be atomic,
109 * i.e. within the same non-preemptible window so that we do not switch
110 * to another migration context that overwrites the PTE.
112 * This changes quite a bit on platforms with HAS_64K_PAGES support,
113 * where we instead have three windows, each CHUNK_SIZE in size. The
114 * first is reserved for mapping system-memory, and that just uses the
115 * 512 entry layout using 4K GTT pages. The other two windows just map
116 * lmem pages and must use the new compact 32 entry layout using 64K GTT
117 * pages, which ensures we can address any lmem object that the user
118 * throws at us. We then also use the xehpsdv_toggle_pdes as a way of
119 * just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
120 * compact layout for each of these page-tables, that fall within the
121 * [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
123 * We lay the ppGTT out as:
125 * [0, CHUNK_SZ) -> first window/object, maps smem
126 * [CHUNK_SZ, 2 * CHUNK_SZ) -> second window/object, maps lmem src
127 * [2 * CHUNK_SZ, 3 * CHUNK_SZ) -> third window/object, maps lmem dst
129 * For the PTE window it's also quite different, since each PTE must
130 * point to some 64K page, one for each PT(since it's in lmem), and yet
131 * each is only <= 4096bytes, but since the unused space within that PTE
132 * range is never touched, this should be fine.
134 * So basically each PT now needs 64K of virtual memory, instead of 4K,
137 * [3 * CHUNK_SZ, 3 * CHUNK_SZ + ((3 * CHUNK_SZ / SZ_2M) * SZ_64K)] -> PTE
140 vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
144 if (!vm->vm.allocate_va_range || !vm->vm.foreach) {
149 if (HAS_64K_PAGES(gt->i915))
150 stash.pt_sz = I915_GTT_PAGE_SIZE_64K;
153 * Each engine instance is assigned its own chunk in the VM, so
154 * that we can run multiple instances concurrently
156 for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
157 struct intel_engine_cs *engine;
158 u64 base = (u64)i << 32;
159 struct insert_pte_data d = {};
160 struct i915_gem_ww_ctx ww;
163 engine = gt->engine_class[COPY_ENGINE_CLASS][i];
164 if (!engine_supports_migration(engine))
168 * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
169 * 4x2 page directories for source/destination.
171 if (HAS_64K_PAGES(gt->i915))
175 d.offset = base + sz;
178 * We need another page directory setup so that we can write
179 * the 8x512 PTE in each chunk.
181 if (HAS_64K_PAGES(gt->i915))
182 sz += (sz / SZ_2M) * SZ_64K;
184 sz += (sz >> 12) * sizeof(u64);
186 err = i915_vm_alloc_pt_stash(&vm->vm, &stash, sz);
190 for_i915_gem_ww(&ww, err, true) {
191 err = i915_vm_lock_objects(&vm->vm, &ww);
194 err = i915_vm_map_pt_stash(&vm->vm, &stash);
198 vm->vm.allocate_va_range(&vm->vm, &stash, base, sz);
200 i915_vm_free_pt_stash(&vm->vm, &stash);
204 /* Now allow the GPU to rewrite the PTE via its own ppGTT */
205 if (HAS_64K_PAGES(gt->i915)) {
206 vm->vm.foreach(&vm->vm, base, d.offset - base,
207 xehpsdv_insert_pte, &d);
208 d.offset = base + CHUNK_SZ;
209 vm->vm.foreach(&vm->vm,
212 xehpsdv_toggle_pdes, &d);
214 vm->vm.foreach(&vm->vm, base, d.offset - base,
222 i915_vm_put(&vm->vm);
226 static struct intel_engine_cs *first_copy_engine(struct intel_gt *gt)
228 struct intel_engine_cs *engine;
231 for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
232 engine = gt->engine_class[COPY_ENGINE_CLASS][i];
233 if (engine_supports_migration(engine))
240 static struct intel_context *pinned_context(struct intel_gt *gt)
242 static struct lock_class_key key;
243 struct intel_engine_cs *engine;
244 struct i915_address_space *vm;
245 struct intel_context *ce;
247 engine = first_copy_engine(gt);
249 return ERR_PTR(-ENODEV);
255 ce = intel_engine_create_pinned_context(engine, vm, SZ_512K,
256 I915_GEM_HWS_MIGRATE,
262 int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt)
264 struct intel_context *ce;
266 memset(m, 0, sizeof(*m));
268 ce = pinned_context(gt);
276 static int random_index(unsigned int max)
278 return upper_32_bits(mul_u32_u32(get_random_u32(), max));
281 static struct intel_context *__migrate_engines(struct intel_gt *gt)
283 struct intel_engine_cs *engines[MAX_ENGINE_INSTANCE];
284 struct intel_engine_cs *engine;
285 unsigned int count, i;
288 for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
289 engine = gt->engine_class[COPY_ENGINE_CLASS][i];
290 if (engine_supports_migration(engine))
291 engines[count++] = engine;
294 return intel_context_create(engines[random_index(count)]);
297 struct intel_context *intel_migrate_create_context(struct intel_migrate *m)
299 struct intel_context *ce;
302 * We randomly distribute contexts across the engines upon constrction,
303 * as they all share the same pinned vm, and so in order to allow
304 * multiple blits to run in parallel, we must construct each blit
305 * to use a different range of the vm for its GTT. This has to be
306 * known at construction, so we can not use the late greedy load
307 * balancing of the virtual-engine.
309 ce = __migrate_engines(m->context->engine->gt);
314 ce->ring_size = SZ_256K;
317 ce->vm = i915_vm_get(m->context->vm);
322 static inline struct sgt_dma sg_sgt(struct scatterlist *sg)
324 dma_addr_t addr = sg_dma_address(sg);
326 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
329 static int emit_no_arbitration(struct i915_request *rq)
333 cs = intel_ring_begin(rq, 2);
337 /* Explicitly disable preemption for this request. */
338 *cs++ = MI_ARB_ON_OFF;
340 intel_ring_advance(rq, cs);
345 static int max_pte_pkt_size(struct i915_request *rq, int pkt)
347 struct intel_ring *ring = rq->ring;
349 pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32) + 5);
350 pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
355 static int emit_pte(struct i915_request *rq,
357 enum i915_cache_level cache_level,
362 bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
363 const u64 encode = rq->context->vm->pte_encode(0, cache_level,
364 is_lmem ? PTE_LM : 0);
365 struct intel_ring *ring = rq->ring;
366 int pkt, dword_length;
371 GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
373 page_size = I915_GTT_PAGE_SIZE;
374 dword_length = 0x400;
376 /* Compute the page directory offset for the target address range */
378 GEM_BUG_ON(!IS_ALIGNED(offset, SZ_2M));
382 offset += 3 * CHUNK_SZ;
385 page_size = I915_GTT_PAGE_SIZE_64K;
390 offset *= sizeof(u64);
391 offset += 2 * CHUNK_SZ;
394 offset += (u64)rq->engine->instance << 32;
396 cs = intel_ring_begin(rq, 6);
400 /* Pack as many PTE updates as possible into a single MI command */
401 pkt = max_pte_pkt_size(rq, dword_length);
404 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
405 *cs++ = lower_32_bits(offset);
406 *cs++ = upper_32_bits(offset);
409 if (cs - hdr >= pkt) {
412 *hdr += cs - hdr - 2;
415 ring->emit = (void *)cs - ring->vaddr;
416 intel_ring_advance(rq, cs);
417 intel_ring_update_space(ring);
419 cs = intel_ring_begin(rq, 6);
423 dword_rem = dword_length;
425 if (IS_ALIGNED(total, SZ_2M)) {
426 offset = round_up(offset, SZ_64K);
428 dword_rem = SZ_2M - (total & (SZ_2M - 1));
429 dword_rem /= page_size;
434 pkt = max_pte_pkt_size(rq, dword_rem);
437 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
438 *cs++ = lower_32_bits(offset);
439 *cs++ = upper_32_bits(offset);
442 GEM_BUG_ON(!IS_ALIGNED(it->dma, page_size));
444 *cs++ = lower_32_bits(encode | it->dma);
445 *cs++ = upper_32_bits(encode | it->dma);
450 it->dma += page_size;
451 if (it->dma >= it->max) {
452 it->sg = __sg_next(it->sg);
453 if (!it->sg || sg_dma_len(it->sg) == 0)
456 it->dma = sg_dma_address(it->sg);
457 it->max = it->dma + sg_dma_len(it->sg);
459 } while (total < length);
461 *hdr += cs - hdr - 2;
464 ring->emit = (void *)cs - ring->vaddr;
465 intel_ring_advance(rq, cs);
466 intel_ring_update_space(ring);
471 static bool wa_1209644611_applies(int ver, u32 size)
473 u32 height = size >> PAGE_SHIFT;
478 return height % 4 == 3 && height <= 8;
482 * DOC: Flat-CCS - Memory compression for Local memory
484 * On Xe-HP and later devices, we use dedicated compression control state (CCS)
485 * stored in local memory for each surface, to support the 3D and media
486 * compression formats.
488 * The memory required for the CCS of the entire local memory is 1/256 of the
489 * local memory size. So before the kernel boot, the required memory is reserved
490 * for the CCS data and a secure register will be programmed with the CCS base
493 * Flat CCS data needs to be cleared when a lmem object is allocated.
494 * And CCS data can be copied in and out of CCS region through
495 * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
497 * I915 supports Flat-CCS on lmem only objects. When an objects has smem in
498 * its preference list, on memory pressure, i915 needs to migrate the lmem
499 * content into smem. If the lmem object is Flat-CCS compressed by userspace,
500 * then i915 needs to decompress it. But I915 lack the required information
501 * for such decompression. Hence I915 supports Flat-CCS only on lmem only objects.
503 * When we exhaust the lmem, Flat-CCS capable objects' lmem backing memory can
504 * be temporarily evicted to smem, along with the auxiliary CCS state, where
505 * it can be potentially swapped-out at a later point, if required.
506 * If userspace later touches the evicted pages, then we always move
507 * the backing memory back to lmem, which includes restoring the saved CCS state,
508 * and potentially performing any required swap-in.
510 * For the migration of the lmem objects with smem in placement list, such as
511 * {lmem, smem}, objects are treated as non Flat-CCS capable objects.
514 static inline u32 *i915_flush_dw(u32 *cmd, u32 flags)
516 *cmd++ = MI_FLUSH_DW | flags;
523 static int emit_copy_ccs(struct i915_request *rq,
524 u32 dst_offset, u8 dst_access,
525 u32 src_offset, u8 src_access, int size)
527 struct drm_i915_private *i915 = rq->engine->i915;
528 int mocs = rq->engine->gt->mocs.uc_index << 1;
532 cs = intel_ring_begin(rq, 12);
536 num_ccs_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),
537 NUM_CCS_BYTES_PER_BLOCK);
538 GEM_BUG_ON(num_ccs_blks > NUM_CCS_BLKS_PER_XFER);
539 cs = i915_flush_dw(cs, MI_FLUSH_DW_LLC | MI_FLUSH_DW_CCS);
542 * The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
543 * data in and out of the CCS region.
545 * We can copy at most 1024 blocks of 256 bytes using one
546 * XY_CTRL_SURF_COPY_BLT instruction.
548 * In case we need to copy more than 1024 blocks, we need to add
549 * another instruction to the same batch buffer.
551 * 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
553 * 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
555 *cs++ = XY_CTRL_SURF_COPY_BLT |
556 src_access << SRC_ACCESS_TYPE_SHIFT |
557 dst_access << DST_ACCESS_TYPE_SHIFT |
558 ((num_ccs_blks - 1) & CCS_SIZE_MASK) << CCS_SIZE_SHIFT;
560 *cs++ = rq->engine->instance |
561 FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, mocs);
563 *cs++ = rq->engine->instance |
564 FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, mocs);
566 cs = i915_flush_dw(cs, MI_FLUSH_DW_LLC | MI_FLUSH_DW_CCS);
569 intel_ring_advance(rq, cs);
574 static int emit_copy(struct i915_request *rq,
575 u32 dst_offset, u32 src_offset, int size)
577 const int ver = GRAPHICS_VER(rq->engine->i915);
578 u32 instance = rq->engine->instance;
581 cs = intel_ring_begin(rq, ver >= 8 ? 10 : 6);
585 if (ver >= 9 && !wa_1209644611_applies(ver, size)) {
586 *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
587 *cs++ = BLT_DEPTH_32 | PAGE_SIZE;
589 *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
596 } else if (ver >= 8) {
597 *cs++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 - 2);
598 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
600 *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
608 GEM_BUG_ON(instance);
609 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
610 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
611 *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
617 intel_ring_advance(rq, cs);
621 static u64 scatter_list_length(struct scatterlist *sg)
625 while (sg && sg_dma_len(sg)) {
626 len += sg_dma_len(sg);
634 calculate_chunk_sz(struct drm_i915_private *i915, bool src_is_lmem,
635 u64 bytes_to_cpy, u64 ccs_bytes_to_cpy)
637 if (ccs_bytes_to_cpy && !src_is_lmem)
639 * When CHUNK_SZ is passed all the pages upto CHUNK_SZ
640 * will be taken for the blt. in Flat-ccs supported
641 * platform Smem obj will have more pages than required
642 * for main meory hence limit it to the required size
645 return min_t(u64, bytes_to_cpy, CHUNK_SZ);
650 static void get_ccs_sg_sgt(struct sgt_dma *it, u64 bytes_to_cpy)
655 GEM_BUG_ON(!it->sg || !sg_dma_len(it->sg));
656 len = it->max - it->dma;
657 if (len > bytes_to_cpy) {
658 it->dma += bytes_to_cpy;
664 it->sg = __sg_next(it->sg);
665 it->dma = sg_dma_address(it->sg);
666 it->max = it->dma + sg_dma_len(it->sg);
667 } while (bytes_to_cpy);
671 intel_context_migrate_copy(struct intel_context *ce,
672 const struct i915_deps *deps,
673 struct scatterlist *src,
674 enum i915_cache_level src_cache_level,
676 struct scatterlist *dst,
677 enum i915_cache_level dst_cache_level,
679 struct i915_request **out)
681 struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst), it_ccs;
682 struct drm_i915_private *i915 = ce->engine->i915;
683 u64 ccs_bytes_to_cpy = 0, bytes_to_cpy;
684 enum i915_cache_level ccs_cache_level;
685 u32 src_offset, dst_offset;
686 u8 src_access, dst_access;
687 struct i915_request *rq;
689 bool ccs_is_src, overwrite_ccs;
692 GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
693 GEM_BUG_ON(IS_DGFX(ce->engine->i915) && (!src_is_lmem && !dst_is_lmem));
696 GEM_BUG_ON(ce->ring->size < SZ_64K);
698 src_sz = scatter_list_length(src);
699 bytes_to_cpy = src_sz;
701 if (HAS_FLAT_CCS(i915) && src_is_lmem ^ dst_is_lmem) {
702 src_access = !src_is_lmem && dst_is_lmem;
703 dst_access = !src_access;
705 dst_sz = scatter_list_length(dst);
708 ccs_cache_level = dst_cache_level;
710 } else if (dst_is_lmem) {
711 bytes_to_cpy = dst_sz;
713 ccs_cache_level = src_cache_level;
718 * When there is a eviction of ccs needed smem will have the
719 * extra pages for the ccs data
721 * TO-DO: Want to move the size mismatch check to a WARN_ON,
722 * but still we have some requests of smem->lmem with same size.
725 ccs_bytes_to_cpy = src_sz != dst_sz ? GET_CCS_BYTES(i915, bytes_to_cpy) : 0;
726 if (ccs_bytes_to_cpy)
727 get_ccs_sg_sgt(&it_ccs, bytes_to_cpy);
730 overwrite_ccs = HAS_FLAT_CCS(i915) && !ccs_bytes_to_cpy && dst_is_lmem;
733 dst_offset = CHUNK_SZ;
734 if (HAS_64K_PAGES(ce->engine->i915)) {
738 src_offset = CHUNK_SZ;
740 dst_offset = 2 * CHUNK_SZ;
746 rq = i915_request_create(ce);
753 err = i915_request_await_deps(rq, deps);
757 if (rq->engine->emit_init_breadcrumb) {
758 err = rq->engine->emit_init_breadcrumb(rq);
766 /* The PTE updates + copy must not be interrupted. */
767 err = emit_no_arbitration(rq);
771 src_sz = calculate_chunk_sz(i915, src_is_lmem,
772 bytes_to_cpy, ccs_bytes_to_cpy);
774 len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem,
785 err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
794 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
798 err = emit_copy(rq, dst_offset, src_offset, len);
804 if (ccs_bytes_to_cpy) {
807 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
811 ccs_sz = GET_CCS_BYTES(i915, len);
812 err = emit_pte(rq, &it_ccs, ccs_cache_level, false,
813 ccs_is_src ? src_offset : dst_offset,
822 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
826 err = emit_copy_ccs(rq, dst_offset, dst_access,
827 src_offset, src_access, len);
831 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
834 ccs_bytes_to_cpy -= ccs_sz;
835 } else if (overwrite_ccs) {
836 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
842 * If the src is already in lmem, then we must
843 * be doing an lmem -> lmem transfer, and so
844 * should be safe to directly copy the CCS
845 * state. In this case we have either
846 * initialised the CCS aux state when first
847 * clearing the pages (since it is already
848 * allocated in lmem), or the user has
849 * potentially populated it, in which case we
850 * need to copy the CCS state as-is.
852 err = emit_copy_ccs(rq,
853 dst_offset, INDIRECT_ACCESS,
854 src_offset, INDIRECT_ACCESS,
858 * While we can't always restore/manage the CCS
859 * state, we still need to ensure we don't leak
860 * the CCS state from the previous user, so make
861 * sure we overwrite it with something.
863 err = emit_copy_ccs(rq,
864 dst_offset, INDIRECT_ACCESS,
865 dst_offset, DIRECT_ACCESS,
872 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
877 /* Arbitration is re-enabled between requests. */
880 i915_request_put(*out);
881 *out = i915_request_get(rq);
882 i915_request_add(rq);
887 if (!bytes_to_cpy && !ccs_bytes_to_cpy) {
889 WARN_ON(it_src.sg && sg_dma_len(it_src.sg));
891 WARN_ON(it_dst.sg && sg_dma_len(it_dst.sg));
895 if (WARN_ON(!it_src.sg || !sg_dma_len(it_src.sg) ||
896 !it_dst.sg || !sg_dma_len(it_dst.sg) ||
897 (ccs_bytes_to_cpy && (!it_ccs.sg ||
898 !sg_dma_len(it_ccs.sg))))) {
910 static int emit_clear(struct i915_request *rq, u32 offset, int size,
911 u32 value, bool is_lmem)
913 struct drm_i915_private *i915 = rq->engine->i915;
914 int mocs = rq->engine->gt->mocs.uc_index << 1;
915 const int ver = GRAPHICS_VER(i915);
919 GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
921 if (HAS_FLAT_CCS(i915) && ver >= 12)
922 ring_sz = XY_FAST_COLOR_BLT_DW;
928 cs = intel_ring_begin(rq, ring_sz);
932 if (HAS_FLAT_CCS(i915) && ver >= 12) {
933 *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
934 (XY_FAST_COLOR_BLT_DW - 2);
935 *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
938 *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
940 *cs++ = rq->engine->instance;
941 *cs++ = !is_lmem << XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT;
954 } else if (ver >= 8) {
955 *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
956 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
958 *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
960 *cs++ = rq->engine->instance;
964 *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
965 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
967 *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
972 intel_ring_advance(rq, cs);
977 intel_context_migrate_clear(struct intel_context *ce,
978 const struct i915_deps *deps,
979 struct scatterlist *sg,
980 enum i915_cache_level cache_level,
983 struct i915_request **out)
985 struct drm_i915_private *i915 = ce->engine->i915;
986 struct sgt_dma it = sg_sgt(sg);
987 struct i915_request *rq;
991 GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
994 GEM_BUG_ON(ce->ring->size < SZ_64K);
997 if (HAS_64K_PAGES(i915) && is_lmem)
1003 rq = i915_request_create(ce);
1010 err = i915_request_await_deps(rq, deps);
1014 if (rq->engine->emit_init_breadcrumb) {
1015 err = rq->engine->emit_init_breadcrumb(rq);
1023 /* The PTE updates + clear must not be interrupted. */
1024 err = emit_no_arbitration(rq);
1028 len = emit_pte(rq, &it, cache_level, is_lmem, offset, CHUNK_SZ);
1034 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
1038 err = emit_clear(rq, offset, len, value, is_lmem);
1042 if (HAS_FLAT_CCS(i915) && is_lmem && !value) {
1044 * copy the content of memory into corresponding
1047 err = emit_copy_ccs(rq, offset, INDIRECT_ACCESS, offset,
1048 DIRECT_ACCESS, len);
1053 err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
1055 /* Arbitration is re-enabled between requests. */
1058 i915_request_put(*out);
1059 *out = i915_request_get(rq);
1060 i915_request_add(rq);
1061 if (err || !it.sg || !sg_dma_len(it.sg))
1071 int intel_migrate_copy(struct intel_migrate *m,
1072 struct i915_gem_ww_ctx *ww,
1073 const struct i915_deps *deps,
1074 struct scatterlist *src,
1075 enum i915_cache_level src_cache_level,
1077 struct scatterlist *dst,
1078 enum i915_cache_level dst_cache_level,
1080 struct i915_request **out)
1082 struct intel_context *ce;
1089 ce = intel_migrate_create_context(m);
1091 ce = intel_context_get(m->context);
1092 GEM_BUG_ON(IS_ERR(ce));
1094 err = intel_context_pin_ww(ce, ww);
1098 err = intel_context_migrate_copy(ce, deps,
1099 src, src_cache_level, src_is_lmem,
1100 dst, dst_cache_level, dst_is_lmem,
1103 intel_context_unpin(ce);
1105 intel_context_put(ce);
1110 intel_migrate_clear(struct intel_migrate *m,
1111 struct i915_gem_ww_ctx *ww,
1112 const struct i915_deps *deps,
1113 struct scatterlist *sg,
1114 enum i915_cache_level cache_level,
1117 struct i915_request **out)
1119 struct intel_context *ce;
1126 ce = intel_migrate_create_context(m);
1128 ce = intel_context_get(m->context);
1129 GEM_BUG_ON(IS_ERR(ce));
1131 err = intel_context_pin_ww(ce, ww);
1135 err = intel_context_migrate_clear(ce, deps, sg, cache_level,
1136 is_lmem, value, out);
1138 intel_context_unpin(ce);
1140 intel_context_put(ce);
1144 void intel_migrate_fini(struct intel_migrate *m)
1146 struct intel_context *ce;
1148 ce = fetch_and_zero(&m->context);
1152 intel_engine_destroy_pinned_context(ce);
1155 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1156 #include "selftest_migrate.c"