1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022 Intel Corporation
6 #include <drm/drm_device.h>
7 #include <linux/sysfs.h>
8 #include <linux/printk.h>
12 #include "i915_sysfs.h"
14 #include "intel_gt_print.h"
15 #include "intel_gt_regs.h"
16 #include "intel_gt_sysfs.h"
17 #include "intel_gt_sysfs_pm.h"
18 #include "intel_pcode.h"
19 #include "intel_rc6.h"
20 #include "intel_rps.h"
22 enum intel_gt_sysfs_op {
23 INTEL_GT_SYSFS_MIN = 0,
28 sysfs_gt_attribute_w_func(struct kobject *kobj, struct attribute *attr,
29 int (func)(struct intel_gt *gt, u32 val), u32 val)
34 if (!is_object_gt(kobj)) {
36 struct device *dev = kobj_to_dev(kobj);
37 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
39 for_each_gt(gt, i915, i) {
45 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
53 sysfs_gt_attribute_r_func(struct kobject *kobj, struct attribute *attr,
54 u32 (func)(struct intel_gt *gt),
55 enum intel_gt_sysfs_op op)
60 ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
62 if (!is_object_gt(kobj)) {
64 struct device *dev = kobj_to_dev(kobj);
65 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
67 for_each_gt(gt, i915, i) {
71 case INTEL_GT_SYSFS_MIN:
76 case INTEL_GT_SYSFS_MAX:
83 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
90 /* RC6 interfaces will show the minimum RC6 residency value */
91 #define sysfs_gt_attribute_r_min_func(d, a, f) \
92 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
94 /* Frequency interfaces will show the maximum frequency value */
95 #define sysfs_gt_attribute_r_max_func(d, a, f) \
96 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
98 #define INTEL_GT_SYSFS_SHOW(_name, _attr_type) \
99 static ssize_t _name##_show_common(struct kobject *kobj, \
100 struct attribute *attr, char *buff) \
102 u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \
105 return sysfs_emit(buff, "%u\n", val); \
107 static ssize_t _name##_show(struct kobject *kobj, \
108 struct kobj_attribute *attr, char *buff) \
110 return _name ##_show_common(kobj, &attr->attr, buff); \
112 static ssize_t _name##_dev_show(struct device *dev, \
113 struct device_attribute *attr, char *buff) \
115 return _name##_show_common(&dev->kobj, &attr->attr, buff); \
118 #define INTEL_GT_SYSFS_STORE(_name, _func) \
119 static ssize_t _name##_store_common(struct kobject *kobj, \
120 struct attribute *attr, \
121 const char *buff, size_t count) \
126 ret = kstrtou32(buff, 0, &val); \
130 ret = sysfs_gt_attribute_w_func(kobj, attr, _func, val); \
132 return ret ?: count; \
134 static ssize_t _name##_store(struct kobject *kobj, \
135 struct kobj_attribute *attr, const char *buff, \
138 return _name##_store_common(kobj, &attr->attr, buff, count); \
140 static ssize_t _name##_dev_store(struct device *dev, \
141 struct device_attribute *attr, \
142 const char *buff, size_t count) \
144 return _name##_store_common(&dev->kobj, &attr->attr, buff, count); \
147 #define INTEL_GT_SYSFS_SHOW_MAX(_name) INTEL_GT_SYSFS_SHOW(_name, max)
148 #define INTEL_GT_SYSFS_SHOW_MIN(_name) INTEL_GT_SYSFS_SHOW(_name, min)
150 #define INTEL_GT_ATTR_RW(_name) \
151 static struct kobj_attribute attr_##_name = __ATTR_RW(_name)
153 #define INTEL_GT_ATTR_RO(_name) \
154 static struct kobj_attribute attr_##_name = __ATTR_RO(_name)
156 #define INTEL_GT_DUAL_ATTR_RW(_name) \
157 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644, \
159 _name##_dev_store); \
160 INTEL_GT_ATTR_RW(_name)
162 #define INTEL_GT_DUAL_ATTR_RO(_name) \
163 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444, \
166 INTEL_GT_ATTR_RO(_name)
168 static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
170 intel_wakeref_t wakeref;
173 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
174 res = intel_rc6_residency_us(>->rc6, id);
176 return DIV_ROUND_CLOSEST_ULL(res, 1000);
179 static ssize_t rc6_enable_show(struct kobject *kobj,
180 struct kobj_attribute *attr,
183 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
185 return sysfs_emit(buff, "%x\n", gt->rc6.enabled);
188 static ssize_t rc6_enable_dev_show(struct device *dev,
189 struct device_attribute *attr,
192 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(&dev->kobj, attr->attr.name);
194 return sysfs_emit(buff, "%x\n", gt->rc6.enabled);
197 static u32 __rc6_residency_ms_show(struct intel_gt *gt)
199 return get_residency(gt, INTEL_RC6_RES_RC6);
202 static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
204 return get_residency(gt, INTEL_RC6_RES_RC6p);
207 static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
209 return get_residency(gt, INTEL_RC6_RES_RC6pp);
212 static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
214 return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
217 INTEL_GT_SYSFS_SHOW_MIN(rc6_residency_ms);
218 INTEL_GT_SYSFS_SHOW_MIN(rc6p_residency_ms);
219 INTEL_GT_SYSFS_SHOW_MIN(rc6pp_residency_ms);
220 INTEL_GT_SYSFS_SHOW_MIN(media_rc6_residency_ms);
222 INTEL_GT_DUAL_ATTR_RO(rc6_enable);
223 INTEL_GT_DUAL_ATTR_RO(rc6_residency_ms);
224 INTEL_GT_DUAL_ATTR_RO(rc6p_residency_ms);
225 INTEL_GT_DUAL_ATTR_RO(rc6pp_residency_ms);
226 INTEL_GT_DUAL_ATTR_RO(media_rc6_residency_ms);
228 static struct attribute *rc6_attrs[] = {
229 &attr_rc6_enable.attr,
230 &attr_rc6_residency_ms.attr,
234 static struct attribute *rc6p_attrs[] = {
235 &attr_rc6p_residency_ms.attr,
236 &attr_rc6pp_residency_ms.attr,
240 static struct attribute *media_rc6_attrs[] = {
241 &attr_media_rc6_residency_ms.attr,
245 static struct attribute *rc6_dev_attrs[] = {
246 &dev_attr_rc6_enable.attr,
247 &dev_attr_rc6_residency_ms.attr,
251 static struct attribute *rc6p_dev_attrs[] = {
252 &dev_attr_rc6p_residency_ms.attr,
253 &dev_attr_rc6pp_residency_ms.attr,
257 static struct attribute *media_rc6_dev_attrs[] = {
258 &dev_attr_media_rc6_residency_ms.attr,
262 static const struct attribute_group rc6_attr_group[] = {
263 { .attrs = rc6_attrs, },
264 { .name = power_group_name, .attrs = rc6_dev_attrs, },
267 static const struct attribute_group rc6p_attr_group[] = {
268 { .attrs = rc6p_attrs, },
269 { .name = power_group_name, .attrs = rc6p_dev_attrs, },
272 static const struct attribute_group media_rc6_attr_group[] = {
273 { .attrs = media_rc6_attrs, },
274 { .name = power_group_name, .attrs = media_rc6_dev_attrs, },
277 static int __intel_gt_sysfs_create_group(struct kobject *kobj,
278 const struct attribute_group *grp)
280 return is_object_gt(kobj) ?
281 sysfs_create_group(kobj, &grp[0]) :
282 sysfs_merge_group(kobj, &grp[1]);
285 static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
289 if (!IS_ENABLED(CONFIG_PM) || !HAS_RC6(gt->i915))
292 ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
294 gt_warn(gt, "failed to create RC6 sysfs files (%pe)\n", ERR_PTR(ret));
297 * cannot use the is_visible() attribute because
298 * the upper object inherits from the parent group.
300 if (HAS_RC6p(gt->i915)) {
301 ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
303 gt_warn(gt, "failed to create RC6p sysfs files (%pe)\n", ERR_PTR(ret));
306 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
307 ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
309 gt_warn(gt, "failed to create media RC6 sysfs files (%pe)\n", ERR_PTR(ret));
313 static u32 __act_freq_mhz_show(struct intel_gt *gt)
315 return intel_rps_read_actual_frequency(>->rps);
318 static u32 __cur_freq_mhz_show(struct intel_gt *gt)
320 return intel_rps_get_requested_frequency(>->rps);
323 static u32 __boost_freq_mhz_show(struct intel_gt *gt)
325 return intel_rps_get_boost_frequency(>->rps);
328 static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
330 return intel_rps_set_boost_frequency(>->rps, val);
333 static u32 __RP0_freq_mhz_show(struct intel_gt *gt)
335 return intel_rps_get_rp0_frequency(>->rps);
338 static u32 __RPn_freq_mhz_show(struct intel_gt *gt)
340 return intel_rps_get_rpn_frequency(>->rps);
343 static u32 __RP1_freq_mhz_show(struct intel_gt *gt)
345 return intel_rps_get_rp1_frequency(>->rps);
348 static u32 __max_freq_mhz_show(struct intel_gt *gt)
350 return intel_rps_get_max_frequency(>->rps);
353 static int __set_max_freq(struct intel_gt *gt, u32 val)
355 return intel_rps_set_max_frequency(>->rps, val);
358 static u32 __min_freq_mhz_show(struct intel_gt *gt)
360 return intel_rps_get_min_frequency(>->rps);
363 static int __set_min_freq(struct intel_gt *gt, u32 val)
365 return intel_rps_set_min_frequency(>->rps, val);
368 static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
370 struct intel_rps *rps = >->rps;
372 return intel_gpu_freq(rps, rps->efficient_freq);
375 INTEL_GT_SYSFS_SHOW_MAX(act_freq_mhz);
376 INTEL_GT_SYSFS_SHOW_MAX(boost_freq_mhz);
377 INTEL_GT_SYSFS_SHOW_MAX(cur_freq_mhz);
378 INTEL_GT_SYSFS_SHOW_MAX(RP0_freq_mhz);
379 INTEL_GT_SYSFS_SHOW_MAX(RP1_freq_mhz);
380 INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);
381 INTEL_GT_SYSFS_SHOW_MAX(max_freq_mhz);
382 INTEL_GT_SYSFS_SHOW_MIN(min_freq_mhz);
383 INTEL_GT_SYSFS_SHOW_MAX(vlv_rpe_freq_mhz);
384 INTEL_GT_SYSFS_STORE(boost_freq_mhz, __boost_freq_mhz_store);
385 INTEL_GT_SYSFS_STORE(max_freq_mhz, __set_max_freq);
386 INTEL_GT_SYSFS_STORE(min_freq_mhz, __set_min_freq);
388 #define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, _store_dev) \
389 static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, \
390 _show_dev, _store_dev); \
391 static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, _mode, \
394 #define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
395 INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL, \
396 _name##_dev_show, NULL)
397 #define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
398 INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store, \
399 _name##_dev_show, _name##_dev_store)
401 /* The below macros generate static structures */
402 INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
403 INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
404 INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
405 INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
406 INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
407 INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
408 INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
409 INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
410 INTEL_GT_RPS_SYSFS_ATTR_RO(vlv_rpe_freq_mhz);
412 #define GEN6_ATTR(p, s) { \
413 &p##attr_##s##_act_freq_mhz.attr, \
414 &p##attr_##s##_cur_freq_mhz.attr, \
415 &p##attr_##s##_boost_freq_mhz.attr, \
416 &p##attr_##s##_max_freq_mhz.attr, \
417 &p##attr_##s##_min_freq_mhz.attr, \
418 &p##attr_##s##_RP0_freq_mhz.attr, \
419 &p##attr_##s##_RP1_freq_mhz.attr, \
420 &p##attr_##s##_RPn_freq_mhz.attr, \
424 #define GEN6_RPS_ATTR GEN6_ATTR(, rps)
425 #define GEN6_GT_ATTR GEN6_ATTR(dev_, gt)
427 static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
428 static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
430 static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
431 struct kobj_attribute *attr,
434 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
435 u32 preq = intel_rps_read_punit_req_frequency(>->rps);
437 return sysfs_emit(buff, "%u\n", preq);
440 static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
441 struct kobj_attribute *attr,
444 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
445 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
447 return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
450 static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
451 struct kobj_attribute *attr,
452 const char *buff, size_t count)
454 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
455 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
459 err = kstrtou32(buff, 0, &val);
463 err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
467 struct intel_gt_bool_throttle_attr {
468 struct attribute attr;
469 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
471 i915_reg_t (*reg32)(struct intel_gt *gt);
475 static ssize_t throttle_reason_bool_show(struct kobject *kobj,
476 struct kobj_attribute *attr,
479 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
480 struct intel_gt_bool_throttle_attr *t_attr =
481 (struct intel_gt_bool_throttle_attr *) attr;
482 bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask);
484 return sysfs_emit(buff, "%u\n", val);
487 #define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
488 struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
489 .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
490 .show = throttle_reason_bool_show, \
491 .reg32 = intel_gt_perf_limit_reasons_reg, \
495 INTEL_GT_ATTR_RO(punit_req_freq_mhz);
496 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
497 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
498 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
499 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
500 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
501 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
502 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
503 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
504 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
506 static const struct attribute *throttle_reason_attrs[] = {
507 &attr_throttle_reason_status.attr,
508 &attr_throttle_reason_pl1.attr,
509 &attr_throttle_reason_pl2.attr,
510 &attr_throttle_reason_pl4.attr,
511 &attr_throttle_reason_thermal.attr,
512 &attr_throttle_reason_prochot.attr,
513 &attr_throttle_reason_ratl.attr,
514 &attr_throttle_reason_vr_thermalert.attr,
515 &attr_throttle_reason_vr_tdc.attr,
520 * Scaling for multipliers (aka frequency factors).
521 * The format of the value in the register is u8.8.
523 * The presentation to userspace is inspired by the perf event framework.
525 * Documentation/ABI/testing/sysfs-bus-event_source-devices-events
526 * for description of:
527 * /sys/bus/event_source/devices/<pmu>/events/<event>.scale
529 * Summary: Expose two sysfs files for each multiplier.
531 * 1. File <attr> contains a raw hardware value.
532 * 2. File <attr>.scale contains the multiplicative scale factor to be
533 * used by userspace to compute the actual value.
535 * So userspace knows that to get the frequency_factor it multiplies the
536 * provided value by the specified scale factor and vice-versa.
538 * That way there is no precision loss in the kernel interface and API
539 * is future proof should one day the hardware register change to u16.u16,
540 * on some platform. (Or any other fixed point representation.)
543 * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
545 * - an integer part of 2
546 * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
547 * File <attr>.scale contains a string representation of floating point
548 * value 0.00390625 (which is (1 / 256)).
549 * Userspace computes the actual value:
550 * 0x0280 * 0.00390625 -> 2.5
551 * or converts an actual value to the value to be written into <attr>:
552 * 2.5 / 0.00390625 -> 0x0280
555 #define U8_8_VAL_MASK 0xffff
556 #define U8_8_SCALE_TO_VALUE "0.00390625"
558 static ssize_t freq_factor_scale_show(struct kobject *kobj,
559 struct kobj_attribute *attr,
562 return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
565 static u32 media_ratio_mode_to_factor(u32 mode)
567 /* 0 -> 0, 1 -> 256, 2 -> 128 */
568 return !mode ? mode : 256 / mode;
571 static ssize_t media_freq_factor_show(struct kobject *kobj,
572 struct kobj_attribute *attr,
575 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
576 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
577 intel_wakeref_t wakeref;
581 * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
582 * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
584 if (IS_XEHPSDV(gt->i915) &&
585 slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
587 * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
588 * the media_ratio_mode, just return the cached media ratio
590 mode = slpc->media_ratio_mode;
592 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
593 mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
594 mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
595 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
596 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
599 return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
602 static ssize_t media_freq_factor_store(struct kobject *kobj,
603 struct kobj_attribute *attr,
604 const char *buff, size_t count)
606 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
607 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
611 err = kstrtou32(buff, 0, &factor);
615 for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
616 mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
617 if (factor == media_ratio_mode_to_factor(mode))
620 if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
623 err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
625 slpc->media_ratio_mode = mode;
626 DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
631 static ssize_t media_RP0_freq_mhz_show(struct kobject *kobj,
632 struct kobj_attribute *attr,
635 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
639 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
640 PCODE_MBOX_FC_SC_READ_FUSED_P0,
641 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
646 /* Fused media RP0 read from pcode is in units of 50 MHz */
647 val *= GT_FREQUENCY_MULTIPLIER;
649 return sysfs_emit(buff, "%u\n", val);
652 static ssize_t media_RPn_freq_mhz_show(struct kobject *kobj,
653 struct kobj_attribute *attr,
656 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
660 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
661 PCODE_MBOX_FC_SC_READ_FUSED_PN,
662 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
667 /* Fused media RPn read from pcode is in units of 50 MHz */
668 val *= GT_FREQUENCY_MULTIPLIER;
670 return sysfs_emit(buff, "%u\n", val);
673 INTEL_GT_ATTR_RW(media_freq_factor);
674 static struct kobj_attribute attr_media_freq_factor_scale =
675 __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
676 INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
677 INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
679 INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
681 static const struct attribute *media_perf_power_attrs[] = {
682 &attr_media_freq_factor.attr,
683 &attr_media_freq_factor_scale.attr,
684 &attr_media_RP0_freq_mhz.attr,
685 &attr_media_RPn_freq_mhz.attr,
690 rps_up_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
693 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
694 struct intel_rps *rps = >->rps;
696 return sysfs_emit(buf, "%u\n", intel_rps_get_up_threshold(rps));
700 rps_up_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
701 const char *buf, size_t count)
703 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
704 struct intel_rps *rps = >->rps;
708 ret = kstrtou8(buf, 10, &val);
712 ret = intel_rps_set_up_threshold(rps, val);
714 return ret == 0 ? count : ret;
717 static struct kobj_attribute rps_up_threshold_pct =
718 __ATTR(rps_up_threshold_pct,
720 rps_up_threshold_pct_show,
721 rps_up_threshold_pct_store);
724 rps_down_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
727 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
728 struct intel_rps *rps = >->rps;
730 return sysfs_emit(buf, "%u\n", intel_rps_get_down_threshold(rps));
734 rps_down_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
735 const char *buf, size_t count)
737 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
738 struct intel_rps *rps = >->rps;
742 ret = kstrtou8(buf, 10, &val);
746 ret = intel_rps_set_down_threshold(rps, val);
748 return ret == 0 ? count : ret;
751 static struct kobj_attribute rps_down_threshold_pct =
752 __ATTR(rps_down_threshold_pct,
754 rps_down_threshold_pct_show,
755 rps_down_threshold_pct_store);
757 static const struct attribute * const gen6_gt_rps_attrs[] = {
758 &rps_up_threshold_pct.attr,
759 &rps_down_threshold_pct.attr,
764 default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
766 struct intel_gt *gt = kobj_to_gt(kobj->parent);
768 return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
771 static struct kobj_attribute default_min_freq_mhz =
772 __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
775 default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
777 struct intel_gt *gt = kobj_to_gt(kobj->parent);
779 return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
782 static struct kobj_attribute default_max_freq_mhz =
783 __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
786 default_rps_up_threshold_pct_show(struct kobject *kobj,
787 struct kobj_attribute *attr,
790 struct intel_gt *gt = kobj_to_gt(kobj->parent);
792 return sysfs_emit(buf, "%u\n", gt->defaults.rps_up_threshold);
795 static struct kobj_attribute default_rps_up_threshold_pct =
796 __ATTR(rps_up_threshold_pct, 0444, default_rps_up_threshold_pct_show, NULL);
799 default_rps_down_threshold_pct_show(struct kobject *kobj,
800 struct kobj_attribute *attr,
803 struct intel_gt *gt = kobj_to_gt(kobj->parent);
805 return sysfs_emit(buf, "%u\n", gt->defaults.rps_down_threshold);
808 static struct kobj_attribute default_rps_down_threshold_pct =
809 __ATTR(rps_down_threshold_pct, 0444, default_rps_down_threshold_pct_show, NULL);
811 static const struct attribute * const rps_defaults_attrs[] = {
812 &default_min_freq_mhz.attr,
813 &default_max_freq_mhz.attr,
814 &default_rps_up_threshold_pct.attr,
815 &default_rps_down_threshold_pct.attr,
819 static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
821 const struct attribute * const *attrs;
822 struct attribute *vlv_attr;
825 if (GRAPHICS_VER(gt->i915) < 6)
828 if (is_object_gt(kobj)) {
829 attrs = gen6_rps_attrs;
830 vlv_attr = &attr_rps_vlv_rpe_freq_mhz.attr;
832 attrs = gen6_gt_attrs;
833 vlv_attr = &dev_attr_gt_vlv_rpe_freq_mhz.attr;
836 ret = sysfs_create_files(kobj, attrs);
840 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
841 ret = sysfs_create_file(kobj, vlv_attr);
843 if (is_object_gt(kobj) && !intel_uc_uses_guc_slpc(>->uc)) {
844 ret = sysfs_create_files(kobj, gen6_gt_rps_attrs);
852 void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
856 intel_sysfs_rc6_init(gt, kobj);
858 ret = intel_sysfs_rps_init(gt, kobj);
860 gt_warn(gt, "failed to create RPS sysfs files (%pe)", ERR_PTR(ret));
862 /* end of the legacy interfaces */
863 if (!is_object_gt(kobj))
866 ret = sysfs_create_file(kobj, &attr_punit_req_freq_mhz.attr);
868 gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
870 if (intel_uc_uses_guc_slpc(>->uc)) {
871 ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
873 gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
876 if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
877 ret = sysfs_create_files(kobj, throttle_reason_attrs);
879 gt_warn(gt, "failed to create throttle sysfs files (%pe)", ERR_PTR(ret));
882 if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(>->uc)) {
883 ret = sysfs_create_files(kobj, media_perf_power_attrs);
885 gt_warn(gt, "failed to create media_perf_power_attrs sysfs (%pe)\n",
889 ret = sysfs_create_files(gt->sysfs_defaults, rps_defaults_attrs);
891 gt_warn(gt, "failed to add rps defaults (%pe)\n", ERR_PTR(ret));