drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include <drm/drm_managed.h>
   7 #include <drm/intel-gtt.h>
   8
   9 #include "gem/i915_gem_internal.h"
  10 #include "gem/i915_gem_lmem.h"
  11 #include "pxp/intel_pxp.h"
  12
  13 #include "i915_drv.h"
  14 #include "i915_perf_oa_regs.h"
  15 #include "intel_context.h"
  16 #include "intel_engine_pm.h"
  17 #include "intel_engine_regs.h"
  18 #include "intel_ggtt_gmch.h"
  19 #include "intel_gt.h"
  20 #include "intel_gt_buffer_pool.h"
  21 #include "intel_gt_clock_utils.h"
  22 #include "intel_gt_debugfs.h"
  23 #include "intel_gt_mcr.h"
  24 #include "intel_gt_pm.h"
  25 #include "intel_gt_regs.h"
  26 #include "intel_gt_requests.h"
  27 #include "intel_migrate.h"
  28 #include "intel_mocs.h"
  29 #include "intel_pm.h"
  30 #include "intel_rc6.h"
  31 #include "intel_renderstate.h"
  32 #include "intel_rps.h"
  33 #include "intel_gt_sysfs.h"
  34 #include "intel_uncore.h"
  35 #include "shmem_utils.h"
  36
  37 static void __intel_gt_init_early(struct intel_gt *gt)
  38 {
  39         spin_lock_init(&gt->irq_lock);
  40
  41         INIT_LIST_HEAD(&gt->closed_vma);
  42         spin_lock_init(&gt->closed_lock);
  43
  44         init_llist_head(&gt->watchdog.list);
  45         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  46
  47         intel_gt_init_buffer_pool(gt);
  48         intel_gt_init_reset(gt);
  49         intel_gt_init_requests(gt);
  50         intel_gt_init_timelines(gt);
  51         mutex_init(&gt->tlb.invalidate_lock);
  52         seqcount_mutex_init(&gt->tlb.seqno, &gt->tlb.invalidate_lock);
  53         intel_gt_pm_init_early(gt);
  54
  55         intel_uc_init_early(&gt->uc);
  56         intel_rps_init_early(&gt->rps);
  57 }
  58
  59 /* Preliminary initialization of Tile 0 */
  60 void intel_root_gt_init_early(struct drm_i915_private *i915)
  61 {
  62         struct intel_gt *gt = to_gt(i915);
  63
  64         gt->i915 = i915;
  65         gt->uncore = &i915->uncore;
  66
  67         __intel_gt_init_early(gt);
  68 }
  69
  70 static int intel_gt_probe_lmem(struct intel_gt *gt)
  71 {
  72         struct drm_i915_private *i915 = gt->i915;
  73         unsigned int instance = gt->info.id;
  74         int id = INTEL_REGION_LMEM_0 + instance;
  75         struct intel_memory_region *mem;
  76         int err;
  77
  78         mem = intel_gt_setup_lmem(gt);
  79         if (IS_ERR(mem)) {
  80                 err = PTR_ERR(mem);
  81                 if (err == -ENODEV)
  82                         return 0;
  83
  84                 drm_err(&i915->drm,
  85                         "Failed to setup region(%d) type=%d\n",
  86                         err, INTEL_MEMORY_LOCAL);
  87                 return err;
  88         }
  89
  90         mem->id = id;
  91         mem->instance = instance;
  92
  93         intel_memory_region_set_name(mem, "local%u", mem->instance);
  94
  95         GEM_BUG_ON(!HAS_REGION(i915, id));
  96         GEM_BUG_ON(i915->mm.regions[id]);
  97         i915->mm.regions[id] = mem;
  98
  99         return 0;
 100 }
 101
 102 int intel_gt_assign_ggtt(struct intel_gt *gt)
 103 {
 104         gt->ggtt = drmm_kzalloc(&gt->i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
 105
 106         return gt->ggtt ? 0 : -ENOMEM;
 107 }
 108
 109 int intel_gt_init_mmio(struct intel_gt *gt)
 110 {
 111         intel_gt_init_clock_frequency(gt);
 112
 113         intel_uc_init_mmio(&gt->uc);
 114         intel_sseu_info_init(gt);
 115         intel_gt_mcr_init(gt);
 116
 117         return intel_engines_init_mmio(gt);
 118 }
 119
 120 static void init_unused_ring(struct intel_gt *gt, u32 base)
 121 {
 122         struct intel_uncore *uncore = gt->uncore;
 123
 124         intel_uncore_write(uncore, RING_CTL(base), 0);
 125         intel_uncore_write(uncore, RING_HEAD(base), 0);
 126         intel_uncore_write(uncore, RING_TAIL(base), 0);
 127         intel_uncore_write(uncore, RING_START(base), 0);
 128 }
 129
 130 static void init_unused_rings(struct intel_gt *gt)
 131 {
 132         struct drm_i915_private *i915 = gt->i915;
 133
 134         if (IS_I830(i915)) {
 135                 init_unused_ring(gt, PRB1_BASE);
 136                 init_unused_ring(gt, SRB0_BASE);
 137                 init_unused_ring(gt, SRB1_BASE);
 138                 init_unused_ring(gt, SRB2_BASE);
 139                 init_unused_ring(gt, SRB3_BASE);
 140         } else if (GRAPHICS_VER(i915) == 2) {
 141                 init_unused_ring(gt, SRB0_BASE);
 142                 init_unused_ring(gt, SRB1_BASE);
 143         } else if (GRAPHICS_VER(i915) == 3) {
 144                 init_unused_ring(gt, PRB1_BASE);
 145                 init_unused_ring(gt, PRB2_BASE);
 146         }
 147 }
 148
 149 int intel_gt_init_hw(struct intel_gt *gt)
 150 {
 151         struct drm_i915_private *i915 = gt->i915;
 152         struct intel_uncore *uncore = gt->uncore;
 153         int ret;
 154
 155         gt->last_init_time = ktime_get();
 156
 157         /* Double layer security blanket, see i915_gem_init() */
 158         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 159
 160         if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
 161                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 162
 163         if (IS_HASWELL(i915))
 164                 intel_uncore_write(uncore,
 165                                    HSW_MI_PREDICATE_RESULT_2,
 166                                    IS_HSW_GT3(i915) ?
 167                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 168
 169         /* Apply the GT workarounds... */
 170         intel_gt_apply_workarounds(gt);
 171         /* ...and determine whether they are sticking. */
 172         intel_gt_verify_workarounds(gt, "init");
 173
 174         intel_gt_init_swizzling(gt);
 175
 176         /*
 177          * At least 830 can leave some of the unused rings
 178          * "active" (ie. head != tail) after resume which
 179          * will prevent c3 entry. Makes sure all unused rings
 180          * are totally idle.
 181          */
 182         init_unused_rings(gt);
 183
 184         ret = i915_ppgtt_init_hw(gt);
 185         if (ret) {
 186                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 187                 goto out;
 188         }
 189
 190         /* We can't enable contexts until all firmware is loaded */
 191         ret = intel_uc_init_hw(&gt->uc);
 192         if (ret) {
 193                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 194                 goto out;
 195         }
 196
 197         intel_mocs_init(gt);
 198
 199 out:
 200         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 201         return ret;
 202 }
 203
 204 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 205 {
 206         intel_uncore_rmw(uncore, reg, 0, set);
 207 }
 208
 209 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 210 {
 211         intel_uncore_rmw(uncore, reg, clr, 0);
 212 }
 213
 214 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 215 {
 216         intel_uncore_rmw(uncore, reg, 0, 0);
 217 }
 218
 219 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 220 {
 221         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 222         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 223 }
 224
 225 void
 226 intel_gt_clear_error_registers(struct intel_gt *gt,
 227                                intel_engine_mask_t engine_mask)
 228 {
 229         struct drm_i915_private *i915 = gt->i915;
 230         struct intel_uncore *uncore = gt->uncore;
 231         u32 eir;
 232
 233         if (GRAPHICS_VER(i915) != 2)
 234                 clear_register(uncore, PGTBL_ER);
 235
 236         if (GRAPHICS_VER(i915) < 4)
 237                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 238         else
 239                 clear_register(uncore, IPEIR_I965);
 240
 241         clear_register(uncore, EIR);
 242         eir = intel_uncore_read(uncore, EIR);
 243         if (eir) {
 244                 /*
 245                  * some errors might have become stuck,
 246                  * mask them.
 247                  */
 248                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 249                 rmw_set(uncore, EMR, eir);
 250                 intel_uncore_write(uncore, GEN2_IIR,
 251                                    I915_MASTER_ERROR_INTERRUPT);
 252         }
 253
 254         if (GRAPHICS_VER(i915) >= 12) {
 255                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 256                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 257         } else if (GRAPHICS_VER(i915) >= 8) {
 258                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 259                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 260         } else if (GRAPHICS_VER(i915) >= 6) {
 261                 struct intel_engine_cs *engine;
 262                 enum intel_engine_id id;
 263
 264                 for_each_engine_masked(engine, gt, engine_mask, id)
 265                         gen6_clear_engine_error_register(engine);
 266         }
 267 }
 268
 269 static void gen6_check_faults(struct intel_gt *gt)
 270 {
 271         struct intel_engine_cs *engine;
 272         enum intel_engine_id id;
 273         u32 fault;
 274
 275         for_each_engine(engine, gt, id) {
 276                 fault = GEN6_RING_FAULT_REG_READ(engine);
 277                 if (fault & RING_FAULT_VALID) {
 278                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 279                                 "\tAddr: 0x%08lx\n"
 280                                 "\tAddress space: %s\n"
 281                                 "\tSource ID: %d\n"
 282                                 "\tType: %d\n",
 283                                 fault & PAGE_MASK,
 284                                 fault & RING_FAULT_GTTSEL_MASK ?
 285                                 "GGTT" : "PPGTT",
 286                                 RING_FAULT_SRCID(fault),
 287                                 RING_FAULT_FAULT_TYPE(fault));
 288                 }
 289         }
 290 }
 291
 292 static void gen8_check_faults(struct intel_gt *gt)
 293 {
 294         struct intel_uncore *uncore = gt->uncore;
 295         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 296         u32 fault;
 297
 298         if (GRAPHICS_VER(gt->i915) >= 12) {
 299                 fault_reg = GEN12_RING_FAULT_REG;
 300                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 301                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 302         } else {
 303                 fault_reg = GEN8_RING_FAULT_REG;
 304                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 305                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 306         }
 307
 308         fault = intel_uncore_read(uncore, fault_reg);
 309         if (fault & RING_FAULT_VALID) {
 310                 u32 fault_data0, fault_data1;
 311                 u64 fault_addr;
 312
 313                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 314                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 315
 316                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 317                              ((u64)fault_data0 << 12);
 318
 319                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 320                         "\tAddr: 0x%08x_%08x\n"
 321                         "\tAddress space: %s\n"
 322                         "\tEngine ID: %d\n"
 323                         "\tSource ID: %d\n"
 324                         "\tType: %d\n",
 325                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 326                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 327                         GEN8_RING_FAULT_ENGINE_ID(fault),
 328                         RING_FAULT_SRCID(fault),
 329                         RING_FAULT_FAULT_TYPE(fault));
 330         }
 331 }
 332
 333 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 334 {
 335         struct drm_i915_private *i915 = gt->i915;
 336
 337         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 338         if (GRAPHICS_VER(i915) >= 8)
 339                 gen8_check_faults(gt);
 340         else if (GRAPHICS_VER(i915) >= 6)
 341                 gen6_check_faults(gt);
 342         else
 343                 return;
 344
 345         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 346 }
 347
 348 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 349 {
 350         struct intel_uncore *uncore = gt->uncore;
 351         intel_wakeref_t wakeref;
 352
 353         /*
 354          * No actual flushing is required for the GTT write domain for reads
 355          * from the GTT domain. Writes to it "immediately" go to main memory
 356          * as far as we know, so there's no chipset flush. It also doesn't
 357          * land in the GPU render cache.
 358          *
 359          * However, we do have to enforce the order so that all writes through
 360          * the GTT land before any writes to the device, such as updates to
 361          * the GATT itself.
 362          *
 363          * We also have to wait a bit for the writes to land from the GTT.
 364          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 365          * timing. This issue has only been observed when switching quickly
 366          * between GTT writes and CPU reads from inside the kernel on recent hw,
 367          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 368          * system agents we cannot reproduce this behaviour, until Cannonlake
 369          * that was!).
 370          */
 371
 372         wmb();
 373
 374         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 375                 return;
 376
 377         intel_gt_chipset_flush(gt);
 378
 379         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 380                 unsigned long flags;
 381
 382                 spin_lock_irqsave(&uncore->lock, flags);
 383                 intel_uncore_posting_read_fw(uncore,
 384                                              RING_HEAD(RENDER_RING_BASE));
 385                 spin_unlock_irqrestore(&uncore->lock, flags);
 386         }
 387 }
 388
 389 void intel_gt_chipset_flush(struct intel_gt *gt)
 390 {
 391         wmb();
 392         if (GRAPHICS_VER(gt->i915) < 6)
 393                 intel_ggtt_gmch_flush();
 394 }
 395
 396 void intel_gt_driver_register(struct intel_gt *gt)
 397 {
 398         intel_gsc_init(&gt->gsc, gt->i915);
 399
 400         intel_rps_driver_register(&gt->rps);
 401
 402         intel_gt_debugfs_register(gt);
 403         intel_gt_sysfs_register(gt);
 404 }
 405
 406 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 407 {
 408         struct drm_i915_private *i915 = gt->i915;
 409         struct drm_i915_gem_object *obj;
 410         struct i915_vma *vma;
 411         int ret;
 412
 413         obj = i915_gem_object_create_lmem(i915, size,
 414                                           I915_BO_ALLOC_VOLATILE |
 415                                           I915_BO_ALLOC_GPU_ONLY);
 416         if (IS_ERR(obj))
 417                 obj = i915_gem_object_create_stolen(i915, size);
 418         if (IS_ERR(obj))
 419                 obj = i915_gem_object_create_internal(i915, size);
 420         if (IS_ERR(obj)) {
 421                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 422                 return PTR_ERR(obj);
 423         }
 424
 425         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 426         if (IS_ERR(vma)) {
 427                 ret = PTR_ERR(vma);
 428                 goto err_unref;
 429         }
 430
 431         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 432         if (ret)
 433                 goto err_unref;
 434
 435         gt->scratch = i915_vma_make_unshrinkable(vma);
 436
 437         return 0;
 438
 439 err_unref:
 440         i915_gem_object_put(obj);
 441         return ret;
 442 }
 443
 444 static void intel_gt_fini_scratch(struct intel_gt *gt)
 445 {
 446         i915_vma_unpin_and_release(&gt->scratch, 0);
 447 }
 448
 449 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 450 {
 451         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 452                 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
 453         else
 454                 return i915_vm_get(&gt->ggtt->vm);
 455 }
 456
 457 static int __engines_record_defaults(struct intel_gt *gt)
 458 {
 459         struct i915_request *requests[I915_NUM_ENGINES] = {};
 460         struct intel_engine_cs *engine;
 461         enum intel_engine_id id;
 462         int err = 0;
 463
 464         /*
 465          * As we reset the gpu during very early sanitisation, the current
 466          * register state on the GPU should reflect its defaults values.
 467          * We load a context onto the hw (with restore-inhibit), then switch
 468          * over to a second context to save that default register state. We
 469          * can then prime every new context with that state so they all start
 470          * from the same default HW values.
 471          */
 472
 473         for_each_engine(engine, gt, id) {
 474                 struct intel_renderstate so;
 475                 struct intel_context *ce;
 476                 struct i915_request *rq;
 477
 478                 /* We must be able to switch to something! */
 479                 GEM_BUG_ON(!engine->kernel_context);
 480
 481                 ce = intel_context_create(engine);
 482                 if (IS_ERR(ce)) {
 483                         err = PTR_ERR(ce);
 484                         goto out;
 485                 }
 486
 487                 err = intel_renderstate_init(&so, ce);
 488                 if (err)
 489                         goto err;
 490
 491                 rq = i915_request_create(ce);
 492                 if (IS_ERR(rq)) {
 493                         err = PTR_ERR(rq);
 494                         goto err_fini;
 495                 }
 496
 497                 err = intel_engine_emit_ctx_wa(rq);
 498                 if (err)
 499                         goto err_rq;
 500
 501                 err = intel_renderstate_emit(&so, rq);
 502                 if (err)
 503                         goto err_rq;
 504
 505 err_rq:
 506                 requests[id] = i915_request_get(rq);
 507                 i915_request_add(rq);
 508 err_fini:
 509                 intel_renderstate_fini(&so, ce);
 510 err:
 511                 if (err) {
 512                         intel_context_put(ce);
 513                         goto out;
 514                 }
 515         }
 516
 517         /* Flush the default context image to memory, and enable powersaving. */
 518         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 519                 err = -EIO;
 520                 goto out;
 521         }
 522
 523         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 524                 struct i915_request *rq;
 525                 struct file *state;
 526
 527                 rq = requests[id];
 528                 if (!rq)
 529                         continue;
 530
 531                 if (rq->fence.error) {
 532                         err = -EIO;
 533                         goto out;
 534                 }
 535
 536                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 537                 if (!rq->context->state)
 538                         continue;
 539
 540                 /* Keep a copy of the state's backing pages; free the obj */
 541                 state = shmem_create_from_object(rq->context->state->obj);
 542                 if (IS_ERR(state)) {
 543                         err = PTR_ERR(state);
 544                         goto out;
 545                 }
 546                 rq->engine->default_state = state;
 547         }
 548
 549 out:
 550         /*
 551          * If we have to abandon now, we expect the engines to be idle
 552          * and ready to be torn-down. The quickest way we can accomplish
 553          * this is by declaring ourselves wedged.
 554          */
 555         if (err)
 556                 intel_gt_set_wedged(gt);
 557
 558         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 559                 struct intel_context *ce;
 560                 struct i915_request *rq;
 561
 562                 rq = requests[id];
 563                 if (!rq)
 564                         continue;
 565
 566                 ce = rq->context;
 567                 i915_request_put(rq);
 568                 intel_context_put(ce);
 569         }
 570         return err;
 571 }
 572
 573 static int __engines_verify_workarounds(struct intel_gt *gt)
 574 {
 575         struct intel_engine_cs *engine;
 576         enum intel_engine_id id;
 577         int err = 0;
 578
 579         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 580                 return 0;
 581
 582         for_each_engine(engine, gt, id) {
 583                 if (intel_engine_verify_workarounds(engine, "load"))
 584                         err = -EIO;
 585         }
 586
 587         /* Flush and restore the kernel context for safety */
 588         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 589                 err = -EIO;
 590
 591         return err;
 592 }
 593
 594 static void __intel_gt_disable(struct intel_gt *gt)
 595 {
 596         intel_gt_set_wedged_on_fini(gt);
 597
 598         intel_gt_suspend_prepare(gt);
 599         intel_gt_suspend_late(gt);
 600
 601         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 602 }
 603
 604 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
 605 {
 606         long remaining_timeout;
 607
 608         /* If the device is asleep, we have no requests outstanding */
 609         if (!intel_gt_pm_is_awake(gt))
 610                 return 0;
 611
 612         while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
 613                                                            &remaining_timeout)) > 0) {
 614                 cond_resched();
 615                 if (signal_pending(current))
 616                         return -EINTR;
 617         }
 618
 619         return timeout ? timeout : intel_uc_wait_for_idle(&gt->uc,
 620                                                           remaining_timeout);
 621 }
 622
 623 int intel_gt_init(struct intel_gt *gt)
 624 {
 625         int err;
 626
 627         err = i915_inject_probe_error(gt->i915, -ENODEV);
 628         if (err)
 629                 return err;
 630
 631         intel_gt_init_workarounds(gt);
 632
 633         /*
 634          * This is just a security blanket to placate dragons.
 635          * On some systems, we very sporadically observe that the first TLBs
 636          * used by the CS may be stale, despite us poking the TLB reset. If
 637          * we hold the forcewake during initialisation these problems
 638          * just magically go away.
 639          */
 640         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 641
 642         err = intel_gt_init_scratch(gt,
 643                                     GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
 644         if (err)
 645                 goto out_fw;
 646
 647         intel_gt_pm_init(gt);
 648
 649         gt->vm = kernel_vm(gt);
 650         if (!gt->vm) {
 651                 err = -ENOMEM;
 652                 goto err_pm;
 653         }
 654
 655         intel_set_mocs_index(gt);
 656
 657         err = intel_engines_init(gt);
 658         if (err)
 659                 goto err_engines;
 660
 661         err = intel_uc_init(&gt->uc);
 662         if (err)
 663                 goto err_engines;
 664
 665         err = intel_gt_resume(gt);
 666         if (err)
 667                 goto err_uc_init;
 668
 669         err = intel_gt_init_hwconfig(gt);
 670         if (err)
 671                 drm_err(&gt->i915->drm, "Failed to retrieve hwconfig table: %pe\n",
 672                         ERR_PTR(err));
 673
 674         err = __engines_record_defaults(gt);
 675         if (err)
 676                 goto err_gt;
 677
 678         err = __engines_verify_workarounds(gt);
 679         if (err)
 680                 goto err_gt;
 681
 682         intel_uc_init_late(&gt->uc);
 683
 684         err = i915_inject_probe_error(gt->i915, -EIO);
 685         if (err)
 686                 goto err_gt;
 687
 688         intel_migrate_init(&gt->migrate, gt);
 689
 690         intel_pxp_init(&gt->pxp);
 691
 692         goto out_fw;
 693 err_gt:
 694         __intel_gt_disable(gt);
 695         intel_uc_fini_hw(&gt->uc);
 696 err_uc_init:
 697         intel_uc_fini(&gt->uc);
 698 err_engines:
 699         intel_engines_release(gt);
 700         i915_vm_put(fetch_and_zero(&gt->vm));
 701 err_pm:
 702         intel_gt_pm_fini(gt);
 703         intel_gt_fini_scratch(gt);
 704 out_fw:
 705         if (err)
 706                 intel_gt_set_wedged_on_init(gt);
 707         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 708         return err;
 709 }
 710
 711 void intel_gt_driver_remove(struct intel_gt *gt)
 712 {
 713         __intel_gt_disable(gt);
 714
 715         intel_migrate_fini(&gt->migrate);
 716         intel_uc_driver_remove(&gt->uc);
 717
 718         intel_engines_release(gt);
 719
 720         intel_gt_flush_buffer_pool(gt);
 721 }
 722
 723 void intel_gt_driver_unregister(struct intel_gt *gt)
 724 {
 725         intel_wakeref_t wakeref;
 726
 727         intel_gt_sysfs_unregister(gt);
 728         intel_rps_driver_unregister(&gt->rps);
 729         intel_gsc_fini(&gt->gsc);
 730
 731         intel_pxp_fini(&gt->pxp);
 732
 733         /*
 734          * Upon unregistering the device to prevent any new users, cancel
 735          * all in-flight requests so that we can quickly unbind the active
 736          * resources.
 737          */
 738         intel_gt_set_wedged_on_fini(gt);
 739
 740         /* Scrub all HW state upon release */
 741         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 742                 __intel_gt_reset(gt, ALL_ENGINES);
 743 }
 744
 745 void intel_gt_driver_release(struct intel_gt *gt)
 746 {
 747         struct i915_address_space *vm;
 748
 749         vm = fetch_and_zero(&gt->vm);
 750         if (vm) /* FIXME being called twice on error paths :( */
 751                 i915_vm_put(vm);
 752
 753         intel_wa_list_free(&gt->wa_list);
 754         intel_gt_pm_fini(gt);
 755         intel_gt_fini_scratch(gt);
 756         intel_gt_fini_buffer_pool(gt);
 757         intel_gt_fini_hwconfig(gt);
 758 }
 759
 760 void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
 761 {
 762         struct intel_gt *gt;
 763         unsigned int id;
 764
 765         /* We need to wait for inflight RCU frees to release their grip */
 766         rcu_barrier();
 767
 768         for_each_gt(gt, i915, id) {
 769                 intel_uc_driver_late_release(&gt->uc);
 770                 intel_gt_fini_requests(gt);
 771                 intel_gt_fini_reset(gt);
 772                 intel_gt_fini_timelines(gt);
 773                 mutex_destroy(&gt->tlb.invalidate_lock);
 774                 intel_engines_free(gt);
 775         }
 776 }
 777
 778 static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
 779 {
 780         int ret;
 781
 782         if (!gt_is_root(gt)) {
 783                 struct intel_uncore_mmio_debug *mmio_debug;
 784                 struct intel_uncore *uncore;
 785
 786                 uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
 787                 if (!uncore)
 788                         return -ENOMEM;
 789
 790                 mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
 791                 if (!mmio_debug) {
 792                         kfree(uncore);
 793                         return -ENOMEM;
 794                 }
 795
 796                 gt->uncore = uncore;
 797                 gt->uncore->debug = mmio_debug;
 798
 799                 __intel_gt_init_early(gt);
 800         }
 801
 802         intel_uncore_init_early(gt->uncore, gt);
 803
 804         ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
 805         if (ret)
 806                 return ret;
 807
 808         gt->phys_addr = phys_addr;
 809
 810         return 0;
 811 }
 812
 813 static void
 814 intel_gt_tile_cleanup(struct intel_gt *gt)
 815 {
 816         intel_uncore_cleanup_mmio(gt->uncore);
 817
 818         if (!gt_is_root(gt)) {
 819                 kfree(gt->uncore->debug);
 820                 kfree(gt->uncore);
 821                 kfree(gt);
 822         }
 823 }
 824
 825 int intel_gt_probe_all(struct drm_i915_private *i915)
 826 {
 827         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 828         struct intel_gt *gt = &i915->gt0;
 829         phys_addr_t phys_addr;
 830         unsigned int mmio_bar;
 831         int ret;
 832
 833         mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
 834         phys_addr = pci_resource_start(pdev, mmio_bar);
 835
 836         /*
 837          * We always have at least one primary GT on any device
 838          * and it has been already initialized early during probe
 839          * in i915_driver_probe()
 840          */
 841         ret = intel_gt_tile_setup(gt, phys_addr);
 842         if (ret)
 843                 return ret;
 844
 845         i915->gt[0] = gt;
 846
 847         /* TODO: add more tiles */
 848         return 0;
 849 }
 850
 851 int intel_gt_tiles_init(struct drm_i915_private *i915)
 852 {
 853         struct intel_gt *gt;
 854         unsigned int id;
 855         int ret;
 856
 857         for_each_gt(gt, i915, id) {
 858                 ret = intel_gt_probe_lmem(gt);
 859                 if (ret)
 860                         return ret;
 861         }
 862
 863         return 0;
 864 }
 865
 866 void intel_gt_release_all(struct drm_i915_private *i915)
 867 {
 868         struct intel_gt *gt;
 869         unsigned int id;
 870
 871         for_each_gt(gt, i915, id) {
 872                 intel_gt_tile_cleanup(gt);
 873                 i915->gt[id] = NULL;
 874         }
 875 }
 876
 877 void intel_gt_info_print(const struct intel_gt_info *info,
 878                          struct drm_printer *p)
 879 {
 880         drm_printf(p, "available engines: %x\n", info->engine_mask);
 881
 882         intel_sseu_dump(&info->sseu, p);
 883 }
 884
 885 struct reg_and_bit {
 886         i915_reg_t reg;
 887         u32 bit;
 888 };
 889
 890 static struct reg_and_bit
 891 get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
 892                 const i915_reg_t *regs, const unsigned int num)
 893 {
 894         const unsigned int class = engine->class;
 895         struct reg_and_bit rb = { };
 896
 897         if (drm_WARN_ON_ONCE(&engine->i915->drm,
 898                              class >= num || !regs[class].reg))
 899                 return rb;
 900
 901         rb.reg = regs[class];
 902         if (gen8 && class == VIDEO_DECODE_CLASS)
 903                 rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */
 904         else
 905                 rb.bit = engine->instance;
 906
 907         rb.bit = BIT(rb.bit);
 908
 909         return rb;
 910 }
 911
 912 static void mmio_invalidate_full(struct intel_gt *gt)
 913 {
 914         static const i915_reg_t gen8_regs[] = {
 915                 [RENDER_CLASS]                  = GEN8_RTCR,
 916                 [VIDEO_DECODE_CLASS]            = GEN8_M1TCR, /* , GEN8_M2TCR */
 917                 [VIDEO_ENHANCEMENT_CLASS]       = GEN8_VTCR,
 918                 [COPY_ENGINE_CLASS]             = GEN8_BTCR,
 919         };
 920         static const i915_reg_t gen12_regs[] = {
 921                 [RENDER_CLASS]                  = GEN12_GFX_TLB_INV_CR,
 922                 [VIDEO_DECODE_CLASS]            = GEN12_VD_TLB_INV_CR,
 923                 [VIDEO_ENHANCEMENT_CLASS]       = GEN12_VE_TLB_INV_CR,
 924                 [COPY_ENGINE_CLASS]             = GEN12_BLT_TLB_INV_CR,
 925                 [COMPUTE_CLASS]                 = GEN12_COMPCTX_TLB_INV_CR,
 926         };
 927         struct drm_i915_private *i915 = gt->i915;
 928         struct intel_uncore *uncore = gt->uncore;
 929         struct intel_engine_cs *engine;
 930         intel_engine_mask_t awake, tmp;
 931         enum intel_engine_id id;
 932         const i915_reg_t *regs;
 933         unsigned int num = 0;
 934
 935         if (GRAPHICS_VER(i915) == 12) {
 936                 regs = gen12_regs;
 937                 num = ARRAY_SIZE(gen12_regs);
 938         } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
 939                 regs = gen8_regs;
 940                 num = ARRAY_SIZE(gen8_regs);
 941         } else if (GRAPHICS_VER(i915) < 8) {
 942                 return;
 943         }
 944
 945         if (drm_WARN_ONCE(&i915->drm, !num,
 946                           "Platform does not implement TLB invalidation!"))
 947                 return;
 948
 949         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 950
 951         spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */
 952
 953         awake = 0;
 954         for_each_engine(engine, gt, id) {
 955                 struct reg_and_bit rb;
 956
 957                 if (!intel_engine_pm_is_awake(engine))
 958                         continue;
 959
 960                 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 961                 if (!i915_mmio_reg_offset(rb.reg))
 962                         continue;
 963
 964                 intel_uncore_write_fw(uncore, rb.reg, rb.bit);
 965                 awake |= engine->mask;
 966         }
 967
 968         GT_TRACE(gt, "invalidated engines %08x\n", awake);
 969
 970         /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */
 971         if (awake &&
 972             (IS_TIGERLAKE(i915) ||
 973              IS_DG1(i915) ||
 974              IS_ROCKETLAKE(i915) ||
 975              IS_ALDERLAKE_S(i915) ||
 976              IS_ALDERLAKE_P(i915)))
 977                 intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
 978
 979         spin_unlock_irq(&uncore->lock);
 980
 981         for_each_engine_masked(engine, gt, awake, tmp) {
 982                 struct reg_and_bit rb;
 983
 984                 /*
 985                  * HW architecture suggest typical invalidation time at 40us,
 986                  * with pessimistic cases up to 100us and a recommendation to
 987                  * cap at 1ms. We go a bit higher just in case.
 988                  */
 989                 const unsigned int timeout_us = 100;
 990                 const unsigned int timeout_ms = 4;
 991
 992                 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 993                 if (__intel_wait_for_register_fw(uncore,
 994                                                  rb.reg, rb.bit, 0,
 995                                                  timeout_us, timeout_ms,
 996                                                  NULL))
 997                         drm_err_ratelimited(&gt->i915->drm,
 998                                             "%s TLB invalidation did not complete in %ums!\n",
 999                                             engine->name, timeout_ms);
1000         }
1001
1002         /*
1003          * Use delayed put since a) we mostly expect a flurry of TLB
1004          * invalidations so it is good to avoid paying the forcewake cost and
1005          * b) it works around a bug in Icelake which cannot cope with too rapid
1006          * transitions.
1007          */
1008         intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
1009 }
1010
1011 static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno)
1012 {
1013         u32 cur = intel_gt_tlb_seqno(gt);
1014
1015         /* Only skip if a *full* TLB invalidate barrier has passed */
1016         return (s32)(cur - ALIGN(seqno, 2)) > 0;
1017 }
1018
1019 void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno)
1020 {
1021         intel_wakeref_t wakeref;
1022
1023         if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
1024                 return;
1025
1026         if (intel_gt_is_wedged(gt))
1027                 return;
1028
1029         if (tlb_seqno_passed(gt, seqno))
1030                 return;
1031
1032         with_intel_gt_pm_if_awake(gt, wakeref) {
1033                 mutex_lock(&gt->tlb.invalidate_lock);
1034                 if (tlb_seqno_passed(gt, seqno))
1035                         goto unlock;
1036
1037                 mmio_invalidate_full(gt);
1038
1039                 write_seqcount_invalidate(&gt->tlb.seqno);
1040 unlock:
1041                 mutex_unlock(&gt->tlb.invalidate_lock);
1042         }
1043 }