drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "debugfs_gt.h"
   7 #include "i915_drv.h"
   8 #include "intel_context.h"
   9 #include "intel_gt.h"
  10 #include "intel_gt_pm.h"
  11 #include "intel_gt_requests.h"
  12 #include "intel_mocs.h"
  13 #include "intel_rc6.h"
  14 #include "intel_renderstate.h"
  15 #include "intel_rps.h"
  16 #include "intel_uncore.h"
  17 #include "intel_pm.h"
  18
  19 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  20 {
  21         gt->i915 = i915;
  22         gt->uncore = &i915->uncore;
  23
  24         spin_lock_init(&gt->irq_lock);
  25
  26         INIT_LIST_HEAD(&gt->closed_vma);
  27         spin_lock_init(&gt->closed_lock);
  28
  29         intel_gt_init_reset(gt);
  30         intel_gt_init_requests(gt);
  31         intel_gt_init_timelines(gt);
  32         intel_gt_pm_init_early(gt);
  33
  34         intel_rps_init_early(&gt->rps);
  35         intel_uc_init_early(&gt->uc);
  36 }
  37
  38 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  39 {
  40         gt->ggtt = ggtt;
  41
  42         intel_gt_sanitize(gt, false);
  43 }
  44
  45 static void init_unused_ring(struct intel_gt *gt, u32 base)
  46 {
  47         struct intel_uncore *uncore = gt->uncore;
  48
  49         intel_uncore_write(uncore, RING_CTL(base), 0);
  50         intel_uncore_write(uncore, RING_HEAD(base), 0);
  51         intel_uncore_write(uncore, RING_TAIL(base), 0);
  52         intel_uncore_write(uncore, RING_START(base), 0);
  53 }
  54
  55 static void init_unused_rings(struct intel_gt *gt)
  56 {
  57         struct drm_i915_private *i915 = gt->i915;
  58
  59         if (IS_I830(i915)) {
  60                 init_unused_ring(gt, PRB1_BASE);
  61                 init_unused_ring(gt, SRB0_BASE);
  62                 init_unused_ring(gt, SRB1_BASE);
  63                 init_unused_ring(gt, SRB2_BASE);
  64                 init_unused_ring(gt, SRB3_BASE);
  65         } else if (IS_GEN(i915, 2)) {
  66                 init_unused_ring(gt, SRB0_BASE);
  67                 init_unused_ring(gt, SRB1_BASE);
  68         } else if (IS_GEN(i915, 3)) {
  69                 init_unused_ring(gt, PRB1_BASE);
  70                 init_unused_ring(gt, PRB2_BASE);
  71         }
  72 }
  73
  74 int intel_gt_init_hw(struct intel_gt *gt)
  75 {
  76         struct drm_i915_private *i915 = gt->i915;
  77         struct intel_uncore *uncore = gt->uncore;
  78         int ret;
  79
  80         ret = intel_gt_terminally_wedged(gt);
  81         if (ret)
  82                 return ret;
  83
  84         gt->last_init_time = ktime_get();
  85
  86         /* Double layer security blanket, see i915_gem_init() */
  87         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
  88
  89         if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
  90                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
  91
  92         if (IS_HASWELL(i915))
  93                 intel_uncore_write(uncore,
  94                                    MI_PREDICATE_RESULT_2,
  95                                    IS_HSW_GT3(i915) ?
  96                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
  97
  98         /* Apply the GT workarounds... */
  99         intel_gt_apply_workarounds(gt);
 100         /* ...and determine whether they are sticking. */
 101         intel_gt_verify_workarounds(gt, "init");
 102
 103         intel_gt_init_swizzling(gt);
 104
 105         /*
 106          * At least 830 can leave some of the unused rings
 107          * "active" (ie. head != tail) after resume which
 108          * will prevent c3 entry. Makes sure all unused rings
 109          * are totally idle.
 110          */
 111         init_unused_rings(gt);
 112
 113         ret = i915_ppgtt_init_hw(gt);
 114         if (ret) {
 115                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 116                 goto out;
 117         }
 118
 119         /* We can't enable contexts until all firmware is loaded */
 120         ret = intel_uc_init_hw(&gt->uc);
 121         if (ret) {
 122                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 123                 goto out;
 124         }
 125
 126         intel_mocs_init(gt);
 127
 128 out:
 129         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 130         return ret;
 131 }
 132
 133 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 134 {
 135         intel_uncore_rmw(uncore, reg, 0, set);
 136 }
 137
 138 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 139 {
 140         intel_uncore_rmw(uncore, reg, clr, 0);
 141 }
 142
 143 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 144 {
 145         intel_uncore_rmw(uncore, reg, 0, 0);
 146 }
 147
 148 static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
 149 {
 150         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 151         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 152 }
 153
 154 void
 155 intel_gt_clear_error_registers(struct intel_gt *gt,
 156                                intel_engine_mask_t engine_mask)
 157 {
 158         struct drm_i915_private *i915 = gt->i915;
 159         struct intel_uncore *uncore = gt->uncore;
 160         u32 eir;
 161
 162         if (!IS_GEN(i915, 2))
 163                 clear_register(uncore, PGTBL_ER);
 164
 165         if (INTEL_GEN(i915) < 4)
 166                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 167         else
 168                 clear_register(uncore, IPEIR_I965);
 169
 170         clear_register(uncore, EIR);
 171         eir = intel_uncore_read(uncore, EIR);
 172         if (eir) {
 173                 /*
 174                  * some errors might have become stuck,
 175                  * mask them.
 176                  */
 177                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 178                 rmw_set(uncore, EMR, eir);
 179                 intel_uncore_write(uncore, GEN2_IIR,
 180                                    I915_MASTER_ERROR_INTERRUPT);
 181         }
 182
 183         if (INTEL_GEN(i915) >= 12) {
 184                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 185                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 186         } else if (INTEL_GEN(i915) >= 8) {
 187                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 188                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 189         } else if (INTEL_GEN(i915) >= 6) {
 190                 struct intel_engine_cs *engine;
 191                 enum intel_engine_id id;
 192
 193                 for_each_engine_masked(engine, gt, engine_mask, id)
 194                         gen8_clear_engine_error_register(engine);
 195         }
 196 }
 197
 198 static void gen6_check_faults(struct intel_gt *gt)
 199 {
 200         struct intel_engine_cs *engine;
 201         enum intel_engine_id id;
 202         u32 fault;
 203
 204         for_each_engine(engine, gt, id) {
 205                 fault = GEN6_RING_FAULT_REG_READ(engine);
 206                 if (fault & RING_FAULT_VALID) {
 207                         DRM_DEBUG_DRIVER("Unexpected fault\n"
 208                                          "\tAddr: 0x%08lx\n"
 209                                          "\tAddress space: %s\n"
 210                                          "\tSource ID: %d\n"
 211                                          "\tType: %d\n",
 212                                          fault & PAGE_MASK,
 213                                          fault & RING_FAULT_GTTSEL_MASK ?
 214                                          "GGTT" : "PPGTT",
 215                                          RING_FAULT_SRCID(fault),
 216                                          RING_FAULT_FAULT_TYPE(fault));
 217                 }
 218         }
 219 }
 220
 221 static void gen8_check_faults(struct intel_gt *gt)
 222 {
 223         struct intel_uncore *uncore = gt->uncore;
 224         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 225         u32 fault;
 226
 227         if (INTEL_GEN(gt->i915) >= 12) {
 228                 fault_reg = GEN12_RING_FAULT_REG;
 229                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 230                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 231         } else {
 232                 fault_reg = GEN8_RING_FAULT_REG;
 233                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 234                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 235         }
 236
 237         fault = intel_uncore_read(uncore, fault_reg);
 238         if (fault & RING_FAULT_VALID) {
 239                 u32 fault_data0, fault_data1;
 240                 u64 fault_addr;
 241
 242                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 243                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 244
 245                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 246                              ((u64)fault_data0 << 12);
 247
 248                 DRM_DEBUG_DRIVER("Unexpected fault\n"
 249                                  "\tAddr: 0x%08x_%08x\n"
 250                                  "\tAddress space: %s\n"
 251                                  "\tEngine ID: %d\n"
 252                                  "\tSource ID: %d\n"
 253                                  "\tType: %d\n",
 254                                  upper_32_bits(fault_addr),
 255                                  lower_32_bits(fault_addr),
 256                                  fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 257                                  GEN8_RING_FAULT_ENGINE_ID(fault),
 258                                  RING_FAULT_SRCID(fault),
 259                                  RING_FAULT_FAULT_TYPE(fault));
 260         }
 261 }
 262
 263 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 264 {
 265         struct drm_i915_private *i915 = gt->i915;
 266
 267         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 268         if (INTEL_GEN(i915) >= 8)
 269                 gen8_check_faults(gt);
 270         else if (INTEL_GEN(i915) >= 6)
 271                 gen6_check_faults(gt);
 272         else
 273                 return;
 274
 275         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 276 }
 277
 278 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 279 {
 280         struct intel_uncore *uncore = gt->uncore;
 281         intel_wakeref_t wakeref;
 282
 283         /*
 284          * No actual flushing is required for the GTT write domain for reads
 285          * from the GTT domain. Writes to it "immediately" go to main memory
 286          * as far as we know, so there's no chipset flush. It also doesn't
 287          * land in the GPU render cache.
 288          *
 289          * However, we do have to enforce the order so that all writes through
 290          * the GTT land before any writes to the device, such as updates to
 291          * the GATT itself.
 292          *
 293          * We also have to wait a bit for the writes to land from the GTT.
 294          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 295          * timing. This issue has only been observed when switching quickly
 296          * between GTT writes and CPU reads from inside the kernel on recent hw,
 297          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 298          * system agents we cannot reproduce this behaviour, until Cannonlake
 299          * that was!).
 300          */
 301
 302         wmb();
 303
 304         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 305                 return;
 306
 307         intel_gt_chipset_flush(gt);
 308
 309         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 310                 unsigned long flags;
 311
 312                 spin_lock_irqsave(&uncore->lock, flags);
 313                 intel_uncore_posting_read_fw(uncore,
 314                                              RING_HEAD(RENDER_RING_BASE));
 315                 spin_unlock_irqrestore(&uncore->lock, flags);
 316         }
 317 }
 318
 319 void intel_gt_chipset_flush(struct intel_gt *gt)
 320 {
 321         wmb();
 322         if (INTEL_GEN(gt->i915) < 6)
 323                 intel_gtt_chipset_flush();
 324 }
 325
 326 void intel_gt_driver_register(struct intel_gt *gt)
 327 {
 328         intel_rps_driver_register(&gt->rps);
 329
 330         debugfs_gt_register(gt);
 331 }
 332
 333 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 334 {
 335         struct drm_i915_private *i915 = gt->i915;
 336         struct drm_i915_gem_object *obj;
 337         struct i915_vma *vma;
 338         int ret;
 339
 340         obj = i915_gem_object_create_stolen(i915, size);
 341         if (IS_ERR(obj))
 342                 obj = i915_gem_object_create_internal(i915, size);
 343         if (IS_ERR(obj)) {
 344                 DRM_ERROR("Failed to allocate scratch page\n");
 345                 return PTR_ERR(obj);
 346         }
 347
 348         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 349         if (IS_ERR(vma)) {
 350                 ret = PTR_ERR(vma);
 351                 goto err_unref;
 352         }
 353
 354         ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
 355         if (ret)
 356                 goto err_unref;
 357
 358         gt->scratch = i915_vma_make_unshrinkable(vma);
 359
 360         return 0;
 361
 362 err_unref:
 363         i915_gem_object_put(obj);
 364         return ret;
 365 }
 366
 367 static void intel_gt_fini_scratch(struct intel_gt *gt)
 368 {
 369         i915_vma_unpin_and_release(&gt->scratch, 0);
 370 }
 371
 372 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 373 {
 374         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 375                 return &i915_ppgtt_create(gt->i915)->vm;
 376         else
 377                 return i915_vm_get(&gt->ggtt->vm);
 378 }
 379
 380 static int __intel_context_flush_retire(struct intel_context *ce)
 381 {
 382         struct intel_timeline *tl;
 383
 384         tl = intel_context_timeline_lock(ce);
 385         if (IS_ERR(tl))
 386                 return PTR_ERR(tl);
 387
 388         intel_context_timeline_unlock(tl);
 389         return 0;
 390 }
 391
 392 static int __engines_record_defaults(struct intel_gt *gt)
 393 {
 394         struct i915_request *requests[I915_NUM_ENGINES] = {};
 395         struct intel_engine_cs *engine;
 396         enum intel_engine_id id;
 397         int err = 0;
 398
 399         /*
 400          * As we reset the gpu during very early sanitisation, the current
 401          * register state on the GPU should reflect its defaults values.
 402          * We load a context onto the hw (with restore-inhibit), then switch
 403          * over to a second context to save that default register state. We
 404          * can then prime every new context with that state so they all start
 405          * from the same default HW values.
 406          */
 407
 408         for_each_engine(engine, gt, id) {
 409                 struct intel_renderstate so;
 410                 struct intel_context *ce;
 411                 struct i915_request *rq;
 412
 413                 err = intel_renderstate_init(&so, engine);
 414                 if (err)
 415                         goto out;
 416
 417                 /* We must be able to switch to something! */
 418                 GEM_BUG_ON(!engine->kernel_context);
 419                 engine->serial++; /* force the kernel context switch */
 420
 421                 ce = intel_context_create(engine);
 422                 if (IS_ERR(ce)) {
 423                         err = PTR_ERR(ce);
 424                         goto out;
 425                 }
 426
 427                 rq = intel_context_create_request(ce);
 428                 if (IS_ERR(rq)) {
 429                         err = PTR_ERR(rq);
 430                         intel_context_put(ce);
 431                         goto out;
 432                 }
 433
 434                 err = intel_engine_emit_ctx_wa(rq);
 435                 if (err)
 436                         goto err_rq;
 437
 438                 err = intel_renderstate_emit(&so, rq);
 439                 if (err)
 440                         goto err_rq;
 441
 442 err_rq:
 443                 requests[id] = i915_request_get(rq);
 444                 i915_request_add(rq);
 445                 intel_renderstate_fini(&so);
 446                 if (err)
 447                         goto out;
 448         }
 449
 450         /* Flush the default context image to memory, and enable powersaving. */
 451         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 452                 err = -EIO;
 453                 goto out;
 454         }
 455
 456         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 457                 struct i915_request *rq;
 458                 struct i915_vma *state;
 459                 void *vaddr;
 460
 461                 rq = requests[id];
 462                 if (!rq)
 463                         continue;
 464
 465                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 466                 state = rq->context->state;
 467                 if (!state)
 468                         continue;
 469
 470                 /* Serialise with retirement on another CPU */
 471                 GEM_BUG_ON(!i915_request_completed(rq));
 472                 err = __intel_context_flush_retire(rq->context);
 473                 if (err)
 474                         goto out;
 475
 476                 /* We want to be able to unbind the state from the GGTT */
 477                 GEM_BUG_ON(intel_context_is_pinned(rq->context));
 478
 479                 /*
 480                  * As we will hold a reference to the logical state, it will
 481                  * not be torn down with the context, and importantly the
 482                  * object will hold onto its vma (making it possible for a
 483                  * stray GTT write to corrupt our defaults). Unmap the vma
 484                  * from the GTT to prevent such accidents and reclaim the
 485                  * space.
 486                  */
 487                 err = i915_vma_unbind(state);
 488                 if (err)
 489                         goto out;
 490
 491                 i915_gem_object_lock(state->obj);
 492                 err = i915_gem_object_set_to_cpu_domain(state->obj, false);
 493                 i915_gem_object_unlock(state->obj);
 494                 if (err)
 495                         goto out;
 496
 497                 i915_gem_object_set_cache_coherency(state->obj, I915_CACHE_LLC);
 498
 499                 /* Check we can acquire the image of the context state */
 500                 vaddr = i915_gem_object_pin_map(state->obj, I915_MAP_FORCE_WB);
 501                 if (IS_ERR(vaddr)) {
 502                         err = PTR_ERR(vaddr);
 503                         goto out;
 504                 }
 505
 506                 rq->engine->default_state = i915_gem_object_get(state->obj);
 507                 i915_gem_object_unpin_map(state->obj);
 508         }
 509
 510 out:
 511         /*
 512          * If we have to abandon now, we expect the engines to be idle
 513          * and ready to be torn-down. The quickest way we can accomplish
 514          * this is by declaring ourselves wedged.
 515          */
 516         if (err)
 517                 intel_gt_set_wedged(gt);
 518
 519         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 520                 struct intel_context *ce;
 521                 struct i915_request *rq;
 522
 523                 rq = requests[id];
 524                 if (!rq)
 525                         continue;
 526
 527                 ce = rq->context;
 528                 i915_request_put(rq);
 529                 intel_context_put(ce);
 530         }
 531         return err;
 532 }
 533
 534 static int __engines_verify_workarounds(struct intel_gt *gt)
 535 {
 536         struct intel_engine_cs *engine;
 537         enum intel_engine_id id;
 538         int err = 0;
 539
 540         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 541                 return 0;
 542
 543         for_each_engine(engine, gt, id) {
 544                 if (intel_engine_verify_workarounds(engine, "load"))
 545                         err = -EIO;
 546         }
 547
 548         return err;
 549 }
 550
 551 static void __intel_gt_disable(struct intel_gt *gt)
 552 {
 553         intel_gt_set_wedged_on_init(gt);
 554
 555         intel_gt_suspend_prepare(gt);
 556         intel_gt_suspend_late(gt);
 557
 558         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 559 }
 560
 561 int intel_gt_init(struct intel_gt *gt)
 562 {
 563         int err;
 564
 565         err = i915_inject_probe_error(gt->i915, -ENODEV);
 566         if (err)
 567                 return err;
 568
 569         /*
 570          * This is just a security blanket to placate dragons.
 571          * On some systems, we very sporadically observe that the first TLBs
 572          * used by the CS may be stale, despite us poking the TLB reset. If
 573          * we hold the forcewake during initialisation these problems
 574          * just magically go away.
 575          */
 576         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 577
 578         err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
 579         if (err)
 580                 goto out_fw;
 581
 582         intel_gt_pm_init(gt);
 583
 584         gt->vm = kernel_vm(gt);
 585         if (!gt->vm) {
 586                 err = -ENOMEM;
 587                 goto err_pm;
 588         }
 589
 590         err = intel_engines_init(gt);
 591         if (err)
 592                 goto err_engines;
 593
 594         intel_uc_init(&gt->uc);
 595
 596         err = intel_gt_resume(gt);
 597         if (err)
 598                 goto err_uc_init;
 599
 600         err = __engines_record_defaults(gt);
 601         if (err)
 602                 goto err_gt;
 603
 604         err = __engines_verify_workarounds(gt);
 605         if (err)
 606                 goto err_gt;
 607
 608         err = i915_inject_probe_error(gt->i915, -EIO);
 609         if (err)
 610                 goto err_gt;
 611
 612         goto out_fw;
 613 err_gt:
 614         __intel_gt_disable(gt);
 615         intel_uc_fini_hw(&gt->uc);
 616 err_uc_init:
 617         intel_uc_fini(&gt->uc);
 618 err_engines:
 619         intel_engines_release(gt);
 620         i915_vm_put(fetch_and_zero(&gt->vm));
 621 err_pm:
 622         intel_gt_pm_fini(gt);
 623         intel_gt_fini_scratch(gt);
 624 out_fw:
 625         if (err)
 626                 intel_gt_set_wedged_on_init(gt);
 627         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 628         return err;
 629 }
 630
 631 void intel_gt_driver_remove(struct intel_gt *gt)
 632 {
 633         __intel_gt_disable(gt);
 634
 635         intel_uc_fini_hw(&gt->uc);
 636         intel_uc_fini(&gt->uc);
 637
 638         intel_engines_release(gt);
 639 }
 640
 641 void intel_gt_driver_unregister(struct intel_gt *gt)
 642 {
 643         intel_rps_driver_unregister(&gt->rps);
 644 }
 645
 646 void intel_gt_driver_release(struct intel_gt *gt)
 647 {
 648         struct i915_address_space *vm;
 649
 650         vm = fetch_and_zero(&gt->vm);
 651         if (vm) /* FIXME being called twice on error paths :( */
 652                 i915_vm_put(vm);
 653
 654         intel_gt_pm_fini(gt);
 655         intel_gt_fini_scratch(gt);
 656 }
 657
 658 void intel_gt_driver_late_release(struct intel_gt *gt)
 659 {
 660         intel_uc_driver_late_release(&gt->uc);
 661         intel_gt_fini_requests(gt);
 662         intel_gt_fini_reset(gt);
 663         intel_gt_fini_timelines(gt);
 664         intel_engines_free(gt);
 665 }