1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <linux/stop_machine.h>
8 #include <asm/set_memory.h>
11 #include <drm/i915_drm.h>
15 #include "i915_scatterlist.h"
16 #include "i915_vgpu.h"
18 #include "intel_gtt.h"
21 i915_get_ggtt_vma_pages(struct i915_vma *vma);
23 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
28 if (i915_node_color_differs(node, color))
29 *start += I915_GTT_PAGE_SIZE;
32 * Also leave a space between the unallocated reserved node after the
33 * GTT and any objects within the GTT, i.e. we use the color adjustment
34 * to insert a guard page to prevent prefetches crossing over the
37 node = list_next_entry(node, node_list);
38 if (node->color != color)
39 *end -= I915_GTT_PAGE_SIZE;
42 static int ggtt_init_hw(struct i915_ggtt *ggtt)
44 struct drm_i915_private *i915 = ggtt->vm.i915;
46 i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
48 ggtt->vm.is_ggtt = true;
50 /* Only VLV supports read-only GGTT mappings */
51 ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
53 if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
54 ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
56 if (ggtt->mappable_end) {
57 if (!io_mapping_init_wc(&ggtt->iomap,
59 ggtt->mappable_end)) {
60 ggtt->vm.cleanup(&ggtt->vm);
64 ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
68 intel_ggtt_init_fences(ggtt);
74 * i915_ggtt_init_hw - Initialize GGTT hardware
77 int i915_ggtt_init_hw(struct drm_i915_private *i915)
82 * Note that we use page colouring to enforce a guard page at the
83 * end of the address space. This is required as the CS may prefetch
84 * beyond the end of the batch buffer, across the page boundary,
85 * and beyond the end of the GTT if we do not provide a guard.
87 ret = ggtt_init_hw(&i915->ggtt);
95 * Certain Gen5 chipsets require require idling the GPU before
96 * unmapping anything from the GTT when VT-d is enabled.
98 static bool needs_idle_maps(struct drm_i915_private *i915)
101 * Query intel_iommu to see if we need the workaround. Presumably that
104 if (!intel_vtd_active())
107 if (IS_GEN(i915, 5) && IS_MOBILE(i915))
110 if (IS_GEN(i915, 12))
111 return true; /* XXX DMAR fault reason 7 */
116 void i915_ggtt_suspend(struct i915_ggtt *ggtt)
118 struct i915_vma *vma, *vn;
121 mutex_lock(&ggtt->vm.mutex);
123 /* Skip rewriting PTE on VMA unbind. */
124 open = atomic_xchg(&ggtt->vm.open, 0);
126 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
127 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
128 i915_vma_wait_for_bind(vma);
130 if (i915_vma_is_pinned(vma))
133 if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
134 __i915_vma_evict(vma);
135 drm_mm_remove_node(&vma->node);
139 ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
140 ggtt->invalidate(ggtt);
141 atomic_set(&ggtt->vm.open, open);
143 mutex_unlock(&ggtt->vm.mutex);
145 intel_gt_check_and_clear_faults(ggtt->vm.gt);
148 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
150 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
152 spin_lock_irq(&uncore->lock);
153 intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
154 intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
155 spin_unlock_irq(&uncore->lock);
158 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
160 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
163 * Note that as an uncached mmio write, this will flush the
164 * WCB of the writes into the GGTT before it triggers the invalidate.
166 intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
169 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
171 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
172 struct drm_i915_private *i915 = ggtt->vm.i915;
174 gen8_ggtt_invalidate(ggtt);
176 if (INTEL_GEN(i915) >= 12)
177 intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
178 GEN12_GUC_TLB_INV_CR_INVALIDATE);
180 intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
183 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
185 intel_gtt_chipset_flush();
188 static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
189 enum i915_cache_level level,
192 return addr | _PAGE_PRESENT;
195 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
200 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
203 enum i915_cache_level level,
206 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
207 gen8_pte_t __iomem *pte =
208 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
210 gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
212 ggtt->invalidate(ggtt);
215 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
216 struct i915_vma *vma,
217 enum i915_cache_level level,
220 const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);
221 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
222 gen8_pte_t __iomem *gte;
223 gen8_pte_t __iomem *end;
224 struct sgt_iter iter;
228 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
229 * not to allow the user to override access to a read only page.
232 gte = (gen8_pte_t __iomem *)ggtt->gsm;
233 gte += vma->node.start / I915_GTT_PAGE_SIZE;
234 end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
236 for_each_sgt_daddr(addr, iter, vma->pages)
237 gen8_set_pte(gte++, pte_encode | addr);
238 GEM_BUG_ON(gte > end);
240 /* Fill the allocated but "unused" space beyond the end of the buffer */
242 gen8_set_pte(gte++, vm->scratch[0]->encode);
245 * We want to flush the TLBs only after we're certain all the PTE
246 * updates have finished.
248 ggtt->invalidate(ggtt);
251 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
254 enum i915_cache_level level,
257 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
258 gen6_pte_t __iomem *pte =
259 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
261 iowrite32(vm->pte_encode(addr, level, flags), pte);
263 ggtt->invalidate(ggtt);
267 * Binds an object into the global gtt with the specified cache level.
268 * The object will be accessible to the GPU via commands whose operands
269 * reference offsets within the global GTT as well as accessible by the GPU
270 * through the GMADR mapped BAR (i915->mm.gtt->gtt).
272 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
273 struct i915_vma *vma,
274 enum i915_cache_level level,
277 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
278 gen6_pte_t __iomem *gte;
279 gen6_pte_t __iomem *end;
280 struct sgt_iter iter;
283 gte = (gen6_pte_t __iomem *)ggtt->gsm;
284 gte += vma->node.start / I915_GTT_PAGE_SIZE;
285 end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
287 for_each_sgt_daddr(addr, iter, vma->pages)
288 iowrite32(vm->pte_encode(addr, level, flags), gte++);
289 GEM_BUG_ON(gte > end);
291 /* Fill the allocated but "unused" space beyond the end of the buffer */
293 iowrite32(vm->scratch[0]->encode, gte++);
296 * We want to flush the TLBs only after we're certain all the PTE
297 * updates have finished.
299 ggtt->invalidate(ggtt);
302 static void nop_clear_range(struct i915_address_space *vm,
303 u64 start, u64 length)
307 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
308 u64 start, u64 length)
310 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
311 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
312 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
313 const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
314 gen8_pte_t __iomem *gtt_base =
315 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
316 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
319 if (WARN(num_entries > max_entries,
320 "First entry = %d; Num entries = %d (max=%d)\n",
321 first_entry, num_entries, max_entries))
322 num_entries = max_entries;
324 for (i = 0; i < num_entries; i++)
325 gen8_set_pte(>t_base[i], scratch_pte);
328 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
331 * Make sure the internal GAM fifo has been cleared of all GTT
332 * writes before exiting stop_machine(). This guarantees that
333 * any aperture accesses waiting to start in another process
334 * cannot back up behind the GTT writes causing a hang.
335 * The register can be any arbitrary GAM register.
337 intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
341 struct i915_address_space *vm;
344 enum i915_cache_level level;
347 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
349 struct insert_page *arg = _arg;
351 gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
352 bxt_vtd_ggtt_wa(arg->vm);
357 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
360 enum i915_cache_level level,
363 struct insert_page arg = { vm, addr, offset, level };
365 stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
368 struct insert_entries {
369 struct i915_address_space *vm;
370 struct i915_vma *vma;
371 enum i915_cache_level level;
375 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
377 struct insert_entries *arg = _arg;
379 gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, arg->flags);
380 bxt_vtd_ggtt_wa(arg->vm);
385 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
386 struct i915_vma *vma,
387 enum i915_cache_level level,
390 struct insert_entries arg = { vm, vma, level, flags };
392 stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
395 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
396 u64 start, u64 length)
398 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
399 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
400 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
401 gen6_pte_t scratch_pte, __iomem *gtt_base =
402 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
403 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
406 if (WARN(num_entries > max_entries,
407 "First entry = %d; Num entries = %d (max=%d)\n",
408 first_entry, num_entries, max_entries))
409 num_entries = max_entries;
411 scratch_pte = vm->scratch[0]->encode;
412 for (i = 0; i < num_entries; i++)
413 iowrite32(scratch_pte, >t_base[i]);
416 static void i915_ggtt_insert_page(struct i915_address_space *vm,
419 enum i915_cache_level cache_level,
422 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
423 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
425 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
428 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
429 struct i915_vma *vma,
430 enum i915_cache_level cache_level,
433 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
434 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
436 intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
440 static void i915_ggtt_clear_range(struct i915_address_space *vm,
441 u64 start, u64 length)
443 intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
446 static void ggtt_bind_vma(struct i915_address_space *vm,
447 struct i915_vm_pt_stash *stash,
448 struct i915_vma *vma,
449 enum i915_cache_level cache_level,
452 struct drm_i915_gem_object *obj = vma->obj;
455 if (i915_vma_is_bound(vma, ~flags & I915_VMA_BIND_MASK))
458 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
460 if (i915_gem_object_is_readonly(obj))
461 pte_flags |= PTE_READ_ONLY;
463 vm->insert_entries(vm, vma, cache_level, pte_flags);
464 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
467 static void ggtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
469 vm->clear_range(vm, vma->node.start, vma->size);
472 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
477 if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
480 GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
481 size = ggtt->vm.total - GUC_GGTT_TOP;
483 ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
484 GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
487 drm_dbg(&ggtt->vm.i915->drm,
488 "Failed to reserve top of GGTT for GuC\n");
493 static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
495 if (drm_mm_node_allocated(&ggtt->uc_fw))
496 drm_mm_remove_node(&ggtt->uc_fw);
499 static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
501 ggtt_release_guc_top(ggtt);
502 if (drm_mm_node_allocated(&ggtt->error_capture))
503 drm_mm_remove_node(&ggtt->error_capture);
504 mutex_destroy(&ggtt->error_mutex);
507 static int init_ggtt(struct i915_ggtt *ggtt)
510 * Let GEM Manage all of the aperture.
512 * However, leave one page at the end still bound to the scratch page.
513 * There are a number of places where the hardware apparently prefetches
514 * past the end of the object, and we've seen multiple hangs with the
515 * GPU head pointer stuck in a batchbuffer bound at the last page of the
516 * aperture. One page should be enough to keep any prefetching inside
519 unsigned long hole_start, hole_end;
520 struct drm_mm_node *entry;
524 * GuC requires all resources that we're sharing with it to be placed in
525 * non-WOPCM memory. If GuC is not present or not in use we still need a
526 * small bias as ring wraparound at offset 0 sometimes hangs. No idea
529 ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
530 intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
532 ret = intel_vgt_balloon(ggtt);
536 mutex_init(&ggtt->error_mutex);
537 if (ggtt->mappable_end) {
539 * Reserve a mappable slot for our lockless error capture.
541 * We strongly prefer taking address 0x0 in order to protect
542 * other critical buffers against accidental overwrites,
543 * as writing to address 0 is a very common mistake.
545 * Since 0 may already be in use by the system (e.g. the BIOS
546 * framebuffer), we let the reservation fail quietly and hope
547 * 0 remains reserved always.
549 * If we fail to reserve 0, and then fail to find any space
550 * for an error-capture, remain silent. We can afford not
551 * to reserve an error_capture node as we have fallback
552 * paths, and we trust that 0 will remain reserved. However,
553 * the only likely reason for failure to insert is a driver
554 * bug, which we expect to cause other failures...
556 ggtt->error_capture.size = I915_GTT_PAGE_SIZE;
557 ggtt->error_capture.color = I915_COLOR_UNEVICTABLE;
558 if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture))
559 drm_mm_insert_node_in_range(&ggtt->vm.mm,
560 &ggtt->error_capture,
561 ggtt->error_capture.size, 0,
562 ggtt->error_capture.color,
563 0, ggtt->mappable_end,
566 if (drm_mm_node_allocated(&ggtt->error_capture))
567 drm_dbg(&ggtt->vm.i915->drm,
568 "Reserved GGTT:[%llx, %llx] for use by error capture\n",
569 ggtt->error_capture.start,
570 ggtt->error_capture.start + ggtt->error_capture.size);
573 * The upper portion of the GuC address space has a sizeable hole
574 * (several MB) that is inaccessible by GuC. Reserve this range within
575 * GGTT as it can comfortably hold GuC/HuC firmware images.
577 ret = ggtt_reserve_guc_top(ggtt);
581 /* Clear any non-preallocated blocks */
582 drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
583 drm_dbg(&ggtt->vm.i915->drm,
584 "clearing unused GTT space: [%lx, %lx]\n",
585 hole_start, hole_end);
586 ggtt->vm.clear_range(&ggtt->vm, hole_start,
587 hole_end - hole_start);
590 /* And finally clear the reserved guard page */
591 ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
596 cleanup_init_ggtt(ggtt);
600 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
601 struct i915_vm_pt_stash *stash,
602 struct i915_vma *vma,
603 enum i915_cache_level cache_level,
608 /* Currently applicable only to VLV */
610 if (i915_gem_object_is_readonly(vma->obj))
611 pte_flags |= PTE_READ_ONLY;
613 if (flags & I915_VMA_LOCAL_BIND)
614 ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
615 stash, vma, cache_level, flags);
617 if (flags & I915_VMA_GLOBAL_BIND)
618 vm->insert_entries(vm, vma, cache_level, pte_flags);
621 static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
622 struct i915_vma *vma)
624 if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
625 vm->clear_range(vm, vma->node.start, vma->size);
627 if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
628 ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
631 static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
633 struct i915_vm_pt_stash stash = {};
634 struct i915_ppgtt *ppgtt;
637 ppgtt = i915_ppgtt_create(ggtt->vm.gt);
639 return PTR_ERR(ppgtt);
641 if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
646 err = i915_vm_alloc_pt_stash(&ppgtt->vm, &stash, ggtt->vm.total);
650 err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
655 * Note we only pre-allocate as far as the end of the global
656 * GTT. On 48b / 4-level page-tables, the difference is very,
657 * very significant! We have to preallocate as GVT/vgpu does
658 * not like the page directory disappearing.
660 ppgtt->vm.allocate_va_range(&ppgtt->vm, &stash, 0, ggtt->vm.total);
663 ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags;
665 GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
666 ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
668 GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
669 ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
671 i915_vm_free_pt_stash(&ppgtt->vm, &stash);
675 i915_vm_free_pt_stash(&ppgtt->vm, &stash);
677 i915_vm_put(&ppgtt->vm);
681 static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
683 struct i915_ppgtt *ppgtt;
685 ppgtt = fetch_and_zero(&ggtt->alias);
689 i915_vm_put(&ppgtt->vm);
691 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
692 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
695 int i915_init_ggtt(struct drm_i915_private *i915)
699 ret = init_ggtt(&i915->ggtt);
703 if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
704 ret = init_aliasing_ppgtt(&i915->ggtt);
706 cleanup_init_ggtt(&i915->ggtt);
712 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
714 struct i915_vma *vma, *vn;
716 atomic_set(&ggtt->vm.open, 0);
718 rcu_barrier(); /* flush the RCU'ed__i915_vm_release */
719 flush_workqueue(ggtt->vm.i915->wq);
721 mutex_lock(&ggtt->vm.mutex);
723 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
724 WARN_ON(__i915_vma_unbind(vma));
726 if (drm_mm_node_allocated(&ggtt->error_capture))
727 drm_mm_remove_node(&ggtt->error_capture);
728 mutex_destroy(&ggtt->error_mutex);
730 ggtt_release_guc_top(ggtt);
731 intel_vgt_deballoon(ggtt);
733 ggtt->vm.cleanup(&ggtt->vm);
735 mutex_unlock(&ggtt->vm.mutex);
736 i915_address_space_fini(&ggtt->vm);
738 arch_phys_wc_del(ggtt->mtrr);
740 if (ggtt->iomap.size)
741 io_mapping_fini(&ggtt->iomap);
745 * i915_ggtt_driver_release - Clean up GGTT hardware initialization
748 void i915_ggtt_driver_release(struct drm_i915_private *i915)
750 struct i915_ggtt *ggtt = &i915->ggtt;
752 fini_aliasing_ppgtt(ggtt);
754 intel_ggtt_fini_fences(ggtt);
755 ggtt_cleanup_hw(ggtt);
758 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
760 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
761 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
762 return snb_gmch_ctl << 20;
765 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
767 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
768 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
770 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
773 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
774 if (bdw_gmch_ctl > 4)
778 return bdw_gmch_ctl << 20;
781 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
783 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
784 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
787 return 1 << (20 + gmch_ctrl);
792 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
794 struct drm_i915_private *i915 = ggtt->vm.i915;
795 struct pci_dev *pdev = i915->drm.pdev;
796 phys_addr_t phys_addr;
799 /* For Modern GENs the PTEs and register space are split in the BAR */
800 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
803 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
804 * will be dropped. For WC mappings in general we have 64 byte burst
805 * writes when the WC buffer is flushed, so we can't use it, but have to
806 * resort to an uncached mapping. The WC issue is easily caught by the
807 * readback check when writing GTT PTE entries.
809 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
810 ggtt->gsm = ioremap(phys_addr, size);
812 ggtt->gsm = ioremap_wc(phys_addr, size);
814 drm_err(&i915->drm, "Failed to map the ggtt page table\n");
818 ret = setup_scratch_page(&ggtt->vm);
820 drm_err(&i915->drm, "Scratch setup failed\n");
821 /* iounmap will also get called at remove, but meh */
826 ggtt->vm.scratch[0]->encode =
827 ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
833 int ggtt_set_pages(struct i915_vma *vma)
837 GEM_BUG_ON(vma->pages);
839 ret = i915_get_ggtt_vma_pages(vma);
843 vma->page_sizes = vma->obj->mm.page_sizes;
848 static void gen6_gmch_remove(struct i915_address_space *vm)
850 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
856 static struct resource pci_resource(struct pci_dev *pdev, int bar)
858 return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
859 pci_resource_len(pdev, bar));
862 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
864 struct drm_i915_private *i915 = ggtt->vm.i915;
865 struct pci_dev *pdev = i915->drm.pdev;
869 /* TODO: We're not aware of mappable constraints on gen8 yet */
870 if (!HAS_LMEM(i915)) {
871 ggtt->gmadr = pci_resource(pdev, 2);
872 ggtt->mappable_end = resource_size(&ggtt->gmadr);
875 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
876 if (IS_CHERRYVIEW(i915))
877 size = chv_get_total_gtt_size(snb_gmch_ctl);
879 size = gen8_get_total_gtt_size(snb_gmch_ctl);
881 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
883 ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
884 ggtt->vm.cleanup = gen6_gmch_remove;
885 ggtt->vm.insert_page = gen8_ggtt_insert_page;
886 ggtt->vm.clear_range = nop_clear_range;
887 if (intel_scanout_needs_vtd_wa(i915))
888 ggtt->vm.clear_range = gen8_ggtt_clear_range;
890 ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
892 /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
893 if (intel_ggtt_update_needs_vtd_wa(i915) ||
894 IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) {
895 ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
896 ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
897 ggtt->vm.bind_async_flags =
898 I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
901 ggtt->invalidate = gen8_ggtt_invalidate;
903 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
904 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
905 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
906 ggtt->vm.vma_ops.clear_pages = clear_pages;
908 ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
910 setup_private_pat(ggtt->vm.gt->uncore);
912 return ggtt_probe_common(ggtt, size);
915 static u64 snb_pte_encode(dma_addr_t addr,
916 enum i915_cache_level level,
919 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
922 case I915_CACHE_L3_LLC:
924 pte |= GEN6_PTE_CACHE_LLC;
926 case I915_CACHE_NONE:
927 pte |= GEN6_PTE_UNCACHED;
936 static u64 ivb_pte_encode(dma_addr_t addr,
937 enum i915_cache_level level,
940 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
943 case I915_CACHE_L3_LLC:
944 pte |= GEN7_PTE_CACHE_L3_LLC;
947 pte |= GEN6_PTE_CACHE_LLC;
949 case I915_CACHE_NONE:
950 pte |= GEN6_PTE_UNCACHED;
959 static u64 byt_pte_encode(dma_addr_t addr,
960 enum i915_cache_level level,
963 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
965 if (!(flags & PTE_READ_ONLY))
966 pte |= BYT_PTE_WRITEABLE;
968 if (level != I915_CACHE_NONE)
969 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
974 static u64 hsw_pte_encode(dma_addr_t addr,
975 enum i915_cache_level level,
978 gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
980 if (level != I915_CACHE_NONE)
981 pte |= HSW_WB_LLC_AGE3;
986 static u64 iris_pte_encode(dma_addr_t addr,
987 enum i915_cache_level level,
990 gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
993 case I915_CACHE_NONE:
996 pte |= HSW_WT_ELLC_LLC_AGE3;
999 pte |= HSW_WB_ELLC_LLC_AGE3;
1006 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
1008 struct drm_i915_private *i915 = ggtt->vm.i915;
1009 struct pci_dev *pdev = i915->drm.pdev;
1013 ggtt->gmadr = pci_resource(pdev, 2);
1014 ggtt->mappable_end = resource_size(&ggtt->gmadr);
1017 * 64/512MB is the current min/max we actually know of, but this is
1018 * just a coarse sanity check.
1020 if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
1021 drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
1022 &ggtt->mappable_end);
1026 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1028 size = gen6_get_total_gtt_size(snb_gmch_ctl);
1029 ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
1031 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1033 ggtt->vm.clear_range = nop_clear_range;
1034 if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
1035 ggtt->vm.clear_range = gen6_ggtt_clear_range;
1036 ggtt->vm.insert_page = gen6_ggtt_insert_page;
1037 ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
1038 ggtt->vm.cleanup = gen6_gmch_remove;
1040 ggtt->invalidate = gen6_ggtt_invalidate;
1042 if (HAS_EDRAM(i915))
1043 ggtt->vm.pte_encode = iris_pte_encode;
1044 else if (IS_HASWELL(i915))
1045 ggtt->vm.pte_encode = hsw_pte_encode;
1046 else if (IS_VALLEYVIEW(i915))
1047 ggtt->vm.pte_encode = byt_pte_encode;
1048 else if (INTEL_GEN(i915) >= 7)
1049 ggtt->vm.pte_encode = ivb_pte_encode;
1051 ggtt->vm.pte_encode = snb_pte_encode;
1053 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
1054 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
1055 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
1056 ggtt->vm.vma_ops.clear_pages = clear_pages;
1058 return ggtt_probe_common(ggtt, size);
1061 static void i915_gmch_remove(struct i915_address_space *vm)
1063 intel_gmch_remove();
1066 static int i915_gmch_probe(struct i915_ggtt *ggtt)
1068 struct drm_i915_private *i915 = ggtt->vm.i915;
1069 phys_addr_t gmadr_base;
1072 ret = intel_gmch_probe(i915->bridge_dev, i915->drm.pdev, NULL);
1074 drm_err(&i915->drm, "failed to set up gmch\n");
1078 intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
1081 (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
1083 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1085 if (needs_idle_maps(i915)) {
1086 drm_notice(&i915->drm,
1087 "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
1088 ggtt->do_idle_maps = true;
1091 ggtt->vm.insert_page = i915_ggtt_insert_page;
1092 ggtt->vm.insert_entries = i915_ggtt_insert_entries;
1093 ggtt->vm.clear_range = i915_ggtt_clear_range;
1094 ggtt->vm.cleanup = i915_gmch_remove;
1096 ggtt->invalidate = gmch_ggtt_invalidate;
1098 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
1099 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
1100 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
1101 ggtt->vm.vma_ops.clear_pages = clear_pages;
1103 if (unlikely(ggtt->do_idle_maps))
1104 drm_notice(&i915->drm,
1105 "Applying Ironlake quirks for intel_iommu\n");
1110 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
1112 struct drm_i915_private *i915 = gt->i915;
1116 ggtt->vm.i915 = i915;
1117 ggtt->vm.dma = &i915->drm.pdev->dev;
1119 if (INTEL_GEN(i915) <= 5)
1120 ret = i915_gmch_probe(ggtt);
1121 else if (INTEL_GEN(i915) < 8)
1122 ret = gen6_gmch_probe(ggtt);
1124 ret = gen8_gmch_probe(ggtt);
1128 if ((ggtt->vm.total - 1) >> 32) {
1130 "We never expected a Global GTT with more than 32bits"
1131 " of address space! Found %lldM!\n",
1132 ggtt->vm.total >> 20);
1133 ggtt->vm.total = 1ULL << 32;
1134 ggtt->mappable_end =
1135 min_t(u64, ggtt->mappable_end, ggtt->vm.total);
1138 if (ggtt->mappable_end > ggtt->vm.total) {
1140 "mappable aperture extends past end of GGTT,"
1141 " aperture=%pa, total=%llx\n",
1142 &ggtt->mappable_end, ggtt->vm.total);
1143 ggtt->mappable_end = ggtt->vm.total;
1146 /* GMADR is the PCI mmio aperture into the global GTT. */
1147 drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
1148 drm_dbg(&i915->drm, "GMADR size = %lluM\n",
1149 (u64)ggtt->mappable_end >> 20);
1150 drm_dbg(&i915->drm, "DSM size = %lluM\n",
1151 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
1157 * i915_ggtt_probe_hw - Probe GGTT hardware location
1158 * @i915: i915 device
1160 int i915_ggtt_probe_hw(struct drm_i915_private *i915)
1164 ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
1168 if (intel_vtd_active())
1169 drm_info(&i915->drm, "VT-d active for gfx access\n");
1174 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
1176 if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
1182 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
1184 GEM_BUG_ON(ggtt->invalidate != gen8_ggtt_invalidate);
1186 ggtt->invalidate = guc_ggtt_invalidate;
1188 ggtt->invalidate(ggtt);
1191 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
1193 /* XXX Temporary pardon for error unload */
1194 if (ggtt->invalidate == gen8_ggtt_invalidate)
1197 /* We should only be called after i915_ggtt_enable_guc() */
1198 GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
1200 ggtt->invalidate = gen8_ggtt_invalidate;
1202 ggtt->invalidate(ggtt);
1205 void i915_ggtt_resume(struct i915_ggtt *ggtt)
1207 struct i915_vma *vma;
1211 intel_gt_check_and_clear_faults(ggtt->vm.gt);
1213 /* First fill our portion of the GTT with scratch pages */
1214 ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
1216 /* Skip rewriting PTE on VMA unbind. */
1217 open = atomic_xchg(&ggtt->vm.open, 0);
1219 /* clflush objects bound into the GGTT and rebind them. */
1220 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link) {
1221 struct drm_i915_gem_object *obj = vma->obj;
1222 unsigned int was_bound =
1223 atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
1225 GEM_BUG_ON(!was_bound);
1226 vma->ops->bind_vma(&ggtt->vm, NULL, vma,
1227 obj ? obj->cache_level : 0,
1229 if (obj) { /* only used during resume => exclusive access */
1230 flush |= fetch_and_zero(&obj->write_domain);
1231 obj->read_domains |= I915_GEM_DOMAIN_GTT;
1235 atomic_set(&ggtt->vm.open, open);
1236 ggtt->invalidate(ggtt);
1239 wbinvd_on_all_cpus();
1241 if (INTEL_GEN(ggtt->vm.i915) >= 8)
1242 setup_private_pat(ggtt->vm.gt->uncore);
1244 intel_ggtt_restore_fences(ggtt);
1247 static struct scatterlist *
1248 rotate_pages(struct drm_i915_gem_object *obj, unsigned int offset,
1249 unsigned int width, unsigned int height,
1250 unsigned int stride,
1251 struct sg_table *st, struct scatterlist *sg)
1253 unsigned int column, row;
1254 unsigned int src_idx;
1256 for (column = 0; column < width; column++) {
1257 src_idx = stride * (height - 1) + column + offset;
1258 for (row = 0; row < height; row++) {
1261 * We don't need the pages, but need to initialize
1262 * the entries so the sg list can be happily traversed.
1263 * The only thing we need are DMA addresses.
1265 sg_set_page(sg, NULL, I915_GTT_PAGE_SIZE, 0);
1266 sg_dma_address(sg) =
1267 i915_gem_object_get_dma_address(obj, src_idx);
1268 sg_dma_len(sg) = I915_GTT_PAGE_SIZE;
1277 static noinline struct sg_table *
1278 intel_rotate_pages(struct intel_rotation_info *rot_info,
1279 struct drm_i915_gem_object *obj)
1281 unsigned int size = intel_rotation_info_size(rot_info);
1282 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1283 struct sg_table *st;
1284 struct scatterlist *sg;
1288 /* Allocate target SG list. */
1289 st = kmalloc(sizeof(*st), GFP_KERNEL);
1293 ret = sg_alloc_table(st, size, GFP_KERNEL);
1300 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
1301 sg = rotate_pages(obj, rot_info->plane[i].offset,
1302 rot_info->plane[i].width, rot_info->plane[i].height,
1303 rot_info->plane[i].stride, st, sg);
1312 drm_dbg(&i915->drm, "Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
1313 obj->base.size, rot_info->plane[0].width,
1314 rot_info->plane[0].height, size);
1316 return ERR_PTR(ret);
1319 static struct scatterlist *
1320 remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
1321 unsigned int width, unsigned int height,
1322 unsigned int stride,
1323 struct sg_table *st, struct scatterlist *sg)
1327 for (row = 0; row < height; row++) {
1328 unsigned int left = width * I915_GTT_PAGE_SIZE;
1332 unsigned int length;
1335 * We don't need the pages, but need to initialize
1336 * the entries so the sg list can be happily traversed.
1337 * The only thing we need are DMA addresses.
1340 addr = i915_gem_object_get_dma_address_len(obj, offset, &length);
1342 length = min(left, length);
1346 sg_set_page(sg, NULL, length, 0);
1347 sg_dma_address(sg) = addr;
1348 sg_dma_len(sg) = length;
1351 offset += length / I915_GTT_PAGE_SIZE;
1355 offset += stride - width;
1361 static noinline struct sg_table *
1362 intel_remap_pages(struct intel_remapped_info *rem_info,
1363 struct drm_i915_gem_object *obj)
1365 unsigned int size = intel_remapped_info_size(rem_info);
1366 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1367 struct sg_table *st;
1368 struct scatterlist *sg;
1372 /* Allocate target SG list. */
1373 st = kmalloc(sizeof(*st), GFP_KERNEL);
1377 ret = sg_alloc_table(st, size, GFP_KERNEL);
1384 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
1385 sg = remap_pages(obj, rem_info->plane[i].offset,
1386 rem_info->plane[i].width, rem_info->plane[i].height,
1387 rem_info->plane[i].stride, st, sg);
1398 drm_dbg(&i915->drm, "Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
1399 obj->base.size, rem_info->plane[0].width,
1400 rem_info->plane[0].height, size);
1402 return ERR_PTR(ret);
1405 static noinline struct sg_table *
1406 intel_partial_pages(const struct i915_ggtt_view *view,
1407 struct drm_i915_gem_object *obj)
1409 struct sg_table *st;
1410 struct scatterlist *sg, *iter;
1411 unsigned int count = view->partial.size;
1412 unsigned int offset;
1415 st = kmalloc(sizeof(*st), GFP_KERNEL);
1419 ret = sg_alloc_table(st, count, GFP_KERNEL);
1423 iter = i915_gem_object_get_sg_dma(obj, view->partial.offset, &offset);
1431 len = min(sg_dma_len(iter) - (offset << PAGE_SHIFT),
1432 count << PAGE_SHIFT);
1433 sg_set_page(sg, NULL, len, 0);
1434 sg_dma_address(sg) =
1435 sg_dma_address(iter) + (offset << PAGE_SHIFT);
1436 sg_dma_len(sg) = len;
1439 count -= len >> PAGE_SHIFT;
1442 i915_sg_trim(st); /* Drop any unused tail entries. */
1448 iter = __sg_next(iter);
1455 return ERR_PTR(ret);
1459 i915_get_ggtt_vma_pages(struct i915_vma *vma)
1464 * The vma->pages are only valid within the lifespan of the borrowed
1465 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
1466 * must be the vma->pages. A simple rule is that vma->pages must only
1467 * be accessed when the obj->mm.pages are pinned.
1469 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
1471 switch (vma->ggtt_view.type) {
1473 GEM_BUG_ON(vma->ggtt_view.type);
1475 case I915_GGTT_VIEW_NORMAL:
1476 vma->pages = vma->obj->mm.pages;
1479 case I915_GGTT_VIEW_ROTATED:
1481 intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
1484 case I915_GGTT_VIEW_REMAPPED:
1486 intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
1489 case I915_GGTT_VIEW_PARTIAL:
1490 vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
1495 if (IS_ERR(vma->pages)) {
1496 ret = PTR_ERR(vma->pages);
1498 drm_err(&vma->vm->i915->drm,
1499 "Failed to get pages for VMA view type %u (%d)!\n",
1500 vma->ggtt_view.type, ret);