1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <asm/set_memory.h>
8 #include <linux/types.h>
9 #include <linux/stop_machine.h>
11 #include <drm/i915_drm.h>
12 #include <drm/intel-gtt.h>
14 #include "gem/i915_gem_lmem.h"
16 #include "intel_ggtt_gmch.h"
18 #include "intel_gt_regs.h"
19 #include "intel_pci_config.h"
22 #include "i915_scatterlist.h"
23 #include "i915_utils.h"
24 #include "i915_vgpu.h"
26 #include "intel_gtt.h"
27 #include "gen8_ppgtt.h"
29 static inline bool suspend_retains_ptes(struct i915_address_space *vm)
31 return GRAPHICS_VER(vm->i915) >= 8 &&
32 !HAS_LMEM(vm->i915) &&
36 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
41 if (i915_node_color_differs(node, color))
42 *start += I915_GTT_PAGE_SIZE;
45 * Also leave a space between the unallocated reserved node after the
46 * GTT and any objects within the GTT, i.e. we use the color adjustment
47 * to insert a guard page to prevent prefetches crossing over the
50 node = list_next_entry(node, node_list);
51 if (node->color != color)
52 *end -= I915_GTT_PAGE_SIZE;
55 static int ggtt_init_hw(struct i915_ggtt *ggtt)
57 struct drm_i915_private *i915 = ggtt->vm.i915;
59 i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
61 ggtt->vm.is_ggtt = true;
63 /* Only VLV supports read-only GGTT mappings */
64 ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
66 if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
67 ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
69 if (ggtt->mappable_end) {
70 if (!io_mapping_init_wc(&ggtt->iomap,
72 ggtt->mappable_end)) {
73 ggtt->vm.cleanup(&ggtt->vm);
77 ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
81 intel_ggtt_init_fences(ggtt);
87 * i915_ggtt_init_hw - Initialize GGTT hardware
90 int i915_ggtt_init_hw(struct drm_i915_private *i915)
95 * Note that we use page colouring to enforce a guard page at the
96 * end of the address space. This is required as the CS may prefetch
97 * beyond the end of the batch buffer, across the page boundary,
98 * and beyond the end of the GTT if we do not provide a guard.
100 ret = ggtt_init_hw(to_gt(i915)->ggtt);
108 * Return the value of the last GGTT pte cast to an u64, if
109 * the system is supposed to retain ptes across resume. 0 otherwise.
111 static u64 read_last_pte(struct i915_address_space *vm)
113 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
114 gen8_pte_t __iomem *ptep;
116 if (!suspend_retains_ptes(vm))
119 GEM_BUG_ON(GRAPHICS_VER(vm->i915) < 8);
120 ptep = (typeof(ptep))ggtt->gsm + (ggtt_total_entries(ggtt) - 1);
125 * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
126 * @vm: The VM to suspend the mappings for
128 * Suspend the memory mappings for all objects mapped to HW via the GGTT or a
131 void i915_ggtt_suspend_vm(struct i915_address_space *vm)
133 struct i915_vma *vma, *vn;
134 int save_skip_rewrite;
136 drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
139 i915_gem_drain_freed_objects(vm->i915);
141 mutex_lock(&vm->mutex);
144 * Skip rewriting PTE on VMA unbind.
145 * FIXME: Use an argument to i915_vma_unbind() instead?
147 save_skip_rewrite = vm->skip_pte_rewrite;
148 vm->skip_pte_rewrite = true;
150 list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
151 struct drm_i915_gem_object *obj = vma->obj;
153 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
155 if (i915_vma_is_pinned(vma) || !i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
158 /* unlikely to race when GPU is idle, so no worry about slowpath.. */
159 if (WARN_ON(!i915_gem_object_trylock(obj, NULL))) {
161 * No dead objects should appear here, GPU should be
162 * completely idle, and userspace suspended
164 i915_gem_object_get(obj);
166 mutex_unlock(&vm->mutex);
168 i915_gem_object_lock(obj, NULL);
169 GEM_WARN_ON(i915_vma_unbind(vma));
170 i915_gem_object_unlock(obj);
171 i915_gem_object_put(obj);
173 vm->skip_pte_rewrite = save_skip_rewrite;
177 if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
178 i915_vma_wait_for_bind(vma);
180 __i915_vma_evict(vma, false);
181 drm_mm_remove_node(&vma->node);
184 i915_gem_object_unlock(obj);
187 if (!suspend_retains_ptes(vm))
188 vm->clear_range(vm, 0, vm->total);
190 i915_vm_to_ggtt(vm)->probed_pte = read_last_pte(vm);
192 vm->skip_pte_rewrite = save_skip_rewrite;
194 mutex_unlock(&vm->mutex);
197 void i915_ggtt_suspend(struct i915_ggtt *ggtt)
199 i915_ggtt_suspend_vm(&ggtt->vm);
200 ggtt->invalidate(ggtt);
202 intel_gt_check_and_clear_faults(ggtt->vm.gt);
205 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
207 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
209 spin_lock_irq(&uncore->lock);
210 intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
211 intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
212 spin_unlock_irq(&uncore->lock);
215 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
217 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
220 * Note that as an uncached mmio write, this will flush the
221 * WCB of the writes into the GGTT before it triggers the invalidate.
223 intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
226 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
228 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
229 struct drm_i915_private *i915 = ggtt->vm.i915;
231 gen8_ggtt_invalidate(ggtt);
233 if (GRAPHICS_VER(i915) >= 12)
234 intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
235 GEN12_GUC_TLB_INV_CR_INVALIDATE);
237 intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
240 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
241 enum i915_cache_level level,
244 gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
247 pte |= GEN12_GGTT_PTE_LM;
252 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
257 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
260 enum i915_cache_level level,
263 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
264 gen8_pte_t __iomem *pte =
265 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
267 gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
269 ggtt->invalidate(ggtt);
272 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
273 struct i915_vma_resource *vma_res,
274 enum i915_cache_level level,
277 const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
278 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
279 gen8_pte_t __iomem *gte;
280 gen8_pte_t __iomem *end;
281 struct sgt_iter iter;
285 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
286 * not to allow the user to override access to a read only page.
289 gte = (gen8_pte_t __iomem *)ggtt->gsm;
290 gte += vma_res->start / I915_GTT_PAGE_SIZE;
291 end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
293 for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
294 gen8_set_pte(gte++, pte_encode | addr);
295 GEM_BUG_ON(gte > end);
297 /* Fill the allocated but "unused" space beyond the end of the buffer */
299 gen8_set_pte(gte++, vm->scratch[0]->encode);
302 * We want to flush the TLBs only after we're certain all the PTE
303 * updates have finished.
305 ggtt->invalidate(ggtt);
308 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
311 enum i915_cache_level level,
314 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
315 gen6_pte_t __iomem *pte =
316 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
318 iowrite32(vm->pte_encode(addr, level, flags), pte);
320 ggtt->invalidate(ggtt);
324 * Binds an object into the global gtt with the specified cache level.
325 * The object will be accessible to the GPU via commands whose operands
326 * reference offsets within the global GTT as well as accessible by the GPU
327 * through the GMADR mapped BAR (i915->mm.gtt->gtt).
329 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
330 struct i915_vma_resource *vma_res,
331 enum i915_cache_level level,
334 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
335 gen6_pte_t __iomem *gte;
336 gen6_pte_t __iomem *end;
337 struct sgt_iter iter;
340 gte = (gen6_pte_t __iomem *)ggtt->gsm;
341 gte += vma_res->start / I915_GTT_PAGE_SIZE;
342 end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
344 for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
345 iowrite32(vm->pte_encode(addr, level, flags), gte++);
346 GEM_BUG_ON(gte > end);
348 /* Fill the allocated but "unused" space beyond the end of the buffer */
350 iowrite32(vm->scratch[0]->encode, gte++);
353 * We want to flush the TLBs only after we're certain all the PTE
354 * updates have finished.
356 ggtt->invalidate(ggtt);
359 static void nop_clear_range(struct i915_address_space *vm,
360 u64 start, u64 length)
364 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
365 u64 start, u64 length)
367 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
368 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
369 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
370 const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
371 gen8_pte_t __iomem *gtt_base =
372 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
373 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
376 if (WARN(num_entries > max_entries,
377 "First entry = %d; Num entries = %d (max=%d)\n",
378 first_entry, num_entries, max_entries))
379 num_entries = max_entries;
381 for (i = 0; i < num_entries; i++)
382 gen8_set_pte(>t_base[i], scratch_pte);
385 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
388 * Make sure the internal GAM fifo has been cleared of all GTT
389 * writes before exiting stop_machine(). This guarantees that
390 * any aperture accesses waiting to start in another process
391 * cannot back up behind the GTT writes causing a hang.
392 * The register can be any arbitrary GAM register.
394 intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
398 struct i915_address_space *vm;
401 enum i915_cache_level level;
404 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
406 struct insert_page *arg = _arg;
408 gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
409 bxt_vtd_ggtt_wa(arg->vm);
414 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
417 enum i915_cache_level level,
420 struct insert_page arg = { vm, addr, offset, level };
422 stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
425 struct insert_entries {
426 struct i915_address_space *vm;
427 struct i915_vma_resource *vma_res;
428 enum i915_cache_level level;
432 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
434 struct insert_entries *arg = _arg;
436 gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
437 bxt_vtd_ggtt_wa(arg->vm);
442 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
443 struct i915_vma_resource *vma_res,
444 enum i915_cache_level level,
447 struct insert_entries arg = { vm, vma_res, level, flags };
449 stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
452 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
453 u64 start, u64 length)
455 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
456 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
457 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
458 gen6_pte_t scratch_pte, __iomem *gtt_base =
459 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
460 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
463 if (WARN(num_entries > max_entries,
464 "First entry = %d; Num entries = %d (max=%d)\n",
465 first_entry, num_entries, max_entries))
466 num_entries = max_entries;
468 scratch_pte = vm->scratch[0]->encode;
469 for (i = 0; i < num_entries; i++)
470 iowrite32(scratch_pte, >t_base[i]);
473 void intel_ggtt_bind_vma(struct i915_address_space *vm,
474 struct i915_vm_pt_stash *stash,
475 struct i915_vma_resource *vma_res,
476 enum i915_cache_level cache_level,
481 if (vma_res->bound_flags & (~flags & I915_VMA_BIND_MASK))
484 vma_res->bound_flags |= flags;
486 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
488 if (vma_res->bi.readonly)
489 pte_flags |= PTE_READ_ONLY;
490 if (vma_res->bi.lmem)
493 vm->insert_entries(vm, vma_res, cache_level, pte_flags);
494 vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
497 void intel_ggtt_unbind_vma(struct i915_address_space *vm,
498 struct i915_vma_resource *vma_res)
500 vm->clear_range(vm, vma_res->start, vma_res->vma_size);
503 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
508 if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
511 GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
512 size = ggtt->vm.total - GUC_GGTT_TOP;
514 ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &ggtt->uc_fw, size,
515 GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
518 drm_dbg(&ggtt->vm.i915->drm,
519 "Failed to reserve top of GGTT for GuC\n");
524 static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
526 if (drm_mm_node_allocated(&ggtt->uc_fw))
527 drm_mm_remove_node(&ggtt->uc_fw);
530 static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
532 ggtt_release_guc_top(ggtt);
533 if (drm_mm_node_allocated(&ggtt->error_capture))
534 drm_mm_remove_node(&ggtt->error_capture);
535 mutex_destroy(&ggtt->error_mutex);
538 static int init_ggtt(struct i915_ggtt *ggtt)
541 * Let GEM Manage all of the aperture.
543 * However, leave one page at the end still bound to the scratch page.
544 * There are a number of places where the hardware apparently prefetches
545 * past the end of the object, and we've seen multiple hangs with the
546 * GPU head pointer stuck in a batchbuffer bound at the last page of the
547 * aperture. One page should be enough to keep any prefetching inside
550 unsigned long hole_start, hole_end;
551 struct drm_mm_node *entry;
554 ggtt->pte_lost = true;
557 * GuC requires all resources that we're sharing with it to be placed in
558 * non-WOPCM memory. If GuC is not present or not in use we still need a
559 * small bias as ring wraparound at offset 0 sometimes hangs. No idea
562 ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
563 intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
565 ret = intel_vgt_balloon(ggtt);
569 mutex_init(&ggtt->error_mutex);
570 if (ggtt->mappable_end) {
572 * Reserve a mappable slot for our lockless error capture.
574 * We strongly prefer taking address 0x0 in order to protect
575 * other critical buffers against accidental overwrites,
576 * as writing to address 0 is a very common mistake.
578 * Since 0 may already be in use by the system (e.g. the BIOS
579 * framebuffer), we let the reservation fail quietly and hope
580 * 0 remains reserved always.
582 * If we fail to reserve 0, and then fail to find any space
583 * for an error-capture, remain silent. We can afford not
584 * to reserve an error_capture node as we have fallback
585 * paths, and we trust that 0 will remain reserved. However,
586 * the only likely reason for failure to insert is a driver
587 * bug, which we expect to cause other failures...
589 ggtt->error_capture.size = I915_GTT_PAGE_SIZE;
590 ggtt->error_capture.color = I915_COLOR_UNEVICTABLE;
591 if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture))
592 drm_mm_insert_node_in_range(&ggtt->vm.mm,
593 &ggtt->error_capture,
594 ggtt->error_capture.size, 0,
595 ggtt->error_capture.color,
596 0, ggtt->mappable_end,
599 if (drm_mm_node_allocated(&ggtt->error_capture))
600 drm_dbg(&ggtt->vm.i915->drm,
601 "Reserved GGTT:[%llx, %llx] for use by error capture\n",
602 ggtt->error_capture.start,
603 ggtt->error_capture.start + ggtt->error_capture.size);
606 * The upper portion of the GuC address space has a sizeable hole
607 * (several MB) that is inaccessible by GuC. Reserve this range within
608 * GGTT as it can comfortably hold GuC/HuC firmware images.
610 ret = ggtt_reserve_guc_top(ggtt);
614 /* Clear any non-preallocated blocks */
615 drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
616 drm_dbg(&ggtt->vm.i915->drm,
617 "clearing unused GTT space: [%lx, %lx]\n",
618 hole_start, hole_end);
619 ggtt->vm.clear_range(&ggtt->vm, hole_start,
620 hole_end - hole_start);
623 /* And finally clear the reserved guard page */
624 ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
629 cleanup_init_ggtt(ggtt);
633 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
634 struct i915_vm_pt_stash *stash,
635 struct i915_vma_resource *vma_res,
636 enum i915_cache_level cache_level,
641 /* Currently applicable only to VLV */
643 if (vma_res->bi.readonly)
644 pte_flags |= PTE_READ_ONLY;
646 if (flags & I915_VMA_LOCAL_BIND)
647 ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
648 stash, vma_res, cache_level, flags);
650 if (flags & I915_VMA_GLOBAL_BIND)
651 vm->insert_entries(vm, vma_res, cache_level, pte_flags);
653 vma_res->bound_flags |= flags;
656 static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
657 struct i915_vma_resource *vma_res)
659 if (vma_res->bound_flags & I915_VMA_GLOBAL_BIND)
660 vm->clear_range(vm, vma_res->start, vma_res->vma_size);
662 if (vma_res->bound_flags & I915_VMA_LOCAL_BIND)
663 ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma_res);
666 static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
668 struct i915_vm_pt_stash stash = {};
669 struct i915_ppgtt *ppgtt;
672 ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
674 return PTR_ERR(ppgtt);
676 if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
681 err = i915_vm_alloc_pt_stash(&ppgtt->vm, &stash, ggtt->vm.total);
685 i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
686 err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
687 i915_gem_object_unlock(ppgtt->vm.scratch[0]);
692 * Note we only pre-allocate as far as the end of the global
693 * GTT. On 48b / 4-level page-tables, the difference is very,
694 * very significant! We have to preallocate as GVT/vgpu does
695 * not like the page directory disappearing.
697 ppgtt->vm.allocate_va_range(&ppgtt->vm, &stash, 0, ggtt->vm.total);
700 ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags;
702 GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != intel_ggtt_bind_vma);
703 ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
705 GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != intel_ggtt_unbind_vma);
706 ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
708 i915_vm_free_pt_stash(&ppgtt->vm, &stash);
712 i915_vm_free_pt_stash(&ppgtt->vm, &stash);
714 i915_vm_put(&ppgtt->vm);
718 static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
720 struct i915_ppgtt *ppgtt;
722 ppgtt = fetch_and_zero(&ggtt->alias);
726 i915_vm_put(&ppgtt->vm);
728 ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma;
729 ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
732 int i915_init_ggtt(struct drm_i915_private *i915)
736 ret = init_ggtt(to_gt(i915)->ggtt);
740 if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
741 ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
743 cleanup_init_ggtt(to_gt(i915)->ggtt);
749 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
751 struct i915_vma *vma, *vn;
753 flush_workqueue(ggtt->vm.i915->wq);
754 i915_gem_drain_freed_objects(ggtt->vm.i915);
756 mutex_lock(&ggtt->vm.mutex);
758 ggtt->vm.skip_pte_rewrite = true;
760 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
761 struct drm_i915_gem_object *obj = vma->obj;
764 trylock = i915_gem_object_trylock(obj, NULL);
767 WARN_ON(__i915_vma_unbind(vma));
769 i915_gem_object_unlock(obj);
772 if (drm_mm_node_allocated(&ggtt->error_capture))
773 drm_mm_remove_node(&ggtt->error_capture);
774 mutex_destroy(&ggtt->error_mutex);
776 ggtt_release_guc_top(ggtt);
777 intel_vgt_deballoon(ggtt);
779 ggtt->vm.cleanup(&ggtt->vm);
781 mutex_unlock(&ggtt->vm.mutex);
782 i915_address_space_fini(&ggtt->vm);
784 arch_phys_wc_del(ggtt->mtrr);
786 if (ggtt->iomap.size)
787 io_mapping_fini(&ggtt->iomap);
791 * i915_ggtt_driver_release - Clean up GGTT hardware initialization
794 void i915_ggtt_driver_release(struct drm_i915_private *i915)
796 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
798 fini_aliasing_ppgtt(ggtt);
800 intel_ggtt_fini_fences(ggtt);
801 ggtt_cleanup_hw(ggtt);
805 * i915_ggtt_driver_late_release - Cleanup of GGTT that needs to be done after
806 * all free objects have been drained.
809 void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
811 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
813 GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
814 dma_resv_fini(&ggtt->vm._resv);
817 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
819 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
820 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
821 return snb_gmch_ctl << 20;
824 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
826 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
827 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
829 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
832 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
833 if (bdw_gmch_ctl > 4)
837 return bdw_gmch_ctl << 20;
840 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
842 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
843 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
846 return 1 << (20 + gmch_ctrl);
851 static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915)
854 * GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset
855 * GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset
857 GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
858 return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
861 static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
863 return gen6_gttmmadr_size(i915) / 2;
866 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
868 struct drm_i915_private *i915 = ggtt->vm.i915;
869 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
870 phys_addr_t phys_addr;
874 GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
875 phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915);
878 * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
879 * will be dropped. For WC mappings in general we have 64 byte burst
880 * writes when the WC buffer is flushed, so we can't use it, but have to
881 * resort to an uncached mapping. The WC issue is easily caught by the
882 * readback check when writing GTT PTE entries.
884 if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
885 ggtt->gsm = ioremap(phys_addr, size);
887 ggtt->gsm = ioremap_wc(phys_addr, size);
889 drm_err(&i915->drm, "Failed to map the ggtt page table\n");
893 kref_init(&ggtt->vm.resv_ref);
894 ret = setup_scratch_page(&ggtt->vm);
896 drm_err(&i915->drm, "Scratch setup failed\n");
897 /* iounmap will also get called at remove, but meh */
903 if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
906 ggtt->vm.scratch[0]->encode =
907 ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
908 I915_CACHE_NONE, pte_flags);
913 static void gen6_gmch_remove(struct i915_address_space *vm)
915 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
921 static struct resource pci_resource(struct pci_dev *pdev, int bar)
923 return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
924 pci_resource_len(pdev, bar));
927 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
929 struct drm_i915_private *i915 = ggtt->vm.i915;
930 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
934 if (!HAS_LMEM(i915)) {
935 if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
938 ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR);
939 ggtt->mappable_end = resource_size(&ggtt->gmadr);
942 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
943 if (IS_CHERRYVIEW(i915))
944 size = chv_get_total_gtt_size(snb_gmch_ctl);
946 size = gen8_get_total_gtt_size(snb_gmch_ctl);
948 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
949 ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
950 ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
952 ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
953 ggtt->vm.cleanup = gen6_gmch_remove;
954 ggtt->vm.insert_page = gen8_ggtt_insert_page;
955 ggtt->vm.clear_range = nop_clear_range;
956 if (intel_scanout_needs_vtd_wa(i915))
957 ggtt->vm.clear_range = gen8_ggtt_clear_range;
959 ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
962 * Serialize GTT updates with aperture access on BXT if VT-d is on,
965 if (intel_vm_no_concurrent_access_wa(i915)) {
966 ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
967 ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
970 * Calling stop_machine() version of GGTT update function
971 * at error capture/reset path will raise lockdep warning.
972 * Allow calling gen8_ggtt_insert_* directly at reset path
973 * which is safe from parallel GGTT updates.
975 ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
976 ggtt->vm.raw_insert_entries = gen8_ggtt_insert_entries;
978 ggtt->vm.bind_async_flags =
979 I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
982 ggtt->invalidate = gen8_ggtt_invalidate;
984 ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma;
985 ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
987 ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
989 setup_private_pat(ggtt->vm.gt->uncore);
991 return ggtt_probe_common(ggtt, size);
994 static u64 snb_pte_encode(dma_addr_t addr,
995 enum i915_cache_level level,
998 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1001 case I915_CACHE_L3_LLC:
1002 case I915_CACHE_LLC:
1003 pte |= GEN6_PTE_CACHE_LLC;
1005 case I915_CACHE_NONE:
1006 pte |= GEN6_PTE_UNCACHED;
1009 MISSING_CASE(level);
1015 static u64 ivb_pte_encode(dma_addr_t addr,
1016 enum i915_cache_level level,
1019 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1022 case I915_CACHE_L3_LLC:
1023 pte |= GEN7_PTE_CACHE_L3_LLC;
1025 case I915_CACHE_LLC:
1026 pte |= GEN6_PTE_CACHE_LLC;
1028 case I915_CACHE_NONE:
1029 pte |= GEN6_PTE_UNCACHED;
1032 MISSING_CASE(level);
1038 static u64 byt_pte_encode(dma_addr_t addr,
1039 enum i915_cache_level level,
1042 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1044 if (!(flags & PTE_READ_ONLY))
1045 pte |= BYT_PTE_WRITEABLE;
1047 if (level != I915_CACHE_NONE)
1048 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
1053 static u64 hsw_pte_encode(dma_addr_t addr,
1054 enum i915_cache_level level,
1057 gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1059 if (level != I915_CACHE_NONE)
1060 pte |= HSW_WB_LLC_AGE3;
1065 static u64 iris_pte_encode(dma_addr_t addr,
1066 enum i915_cache_level level,
1069 gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1072 case I915_CACHE_NONE:
1075 pte |= HSW_WT_ELLC_LLC_AGE3;
1078 pte |= HSW_WB_ELLC_LLC_AGE3;
1085 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
1087 struct drm_i915_private *i915 = ggtt->vm.i915;
1088 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1092 if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
1095 ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR);
1096 ggtt->mappable_end = resource_size(&ggtt->gmadr);
1099 * 64/512MB is the current min/max we actually know of, but this is
1100 * just a coarse sanity check.
1102 if (ggtt->mappable_end < (64 << 20) ||
1103 ggtt->mappable_end > (512 << 20)) {
1104 drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
1105 &ggtt->mappable_end);
1109 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1111 size = gen6_get_total_gtt_size(snb_gmch_ctl);
1112 ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
1114 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1115 ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
1117 ggtt->vm.clear_range = nop_clear_range;
1118 if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
1119 ggtt->vm.clear_range = gen6_ggtt_clear_range;
1120 ggtt->vm.insert_page = gen6_ggtt_insert_page;
1121 ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
1122 ggtt->vm.cleanup = gen6_gmch_remove;
1124 ggtt->invalidate = gen6_ggtt_invalidate;
1126 if (HAS_EDRAM(i915))
1127 ggtt->vm.pte_encode = iris_pte_encode;
1128 else if (IS_HASWELL(i915))
1129 ggtt->vm.pte_encode = hsw_pte_encode;
1130 else if (IS_VALLEYVIEW(i915))
1131 ggtt->vm.pte_encode = byt_pte_encode;
1132 else if (GRAPHICS_VER(i915) >= 7)
1133 ggtt->vm.pte_encode = ivb_pte_encode;
1135 ggtt->vm.pte_encode = snb_pte_encode;
1137 ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma;
1138 ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
1140 return ggtt_probe_common(ggtt, size);
1143 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
1145 struct drm_i915_private *i915 = gt->i915;
1149 ggtt->vm.i915 = i915;
1150 ggtt->vm.dma = i915->drm.dev;
1151 dma_resv_init(&ggtt->vm._resv);
1153 if (GRAPHICS_VER(i915) >= 8)
1154 ret = gen8_gmch_probe(ggtt);
1155 else if (GRAPHICS_VER(i915) >= 6)
1156 ret = gen6_gmch_probe(ggtt);
1158 ret = intel_ggtt_gmch_probe(ggtt);
1161 dma_resv_fini(&ggtt->vm._resv);
1165 if ((ggtt->vm.total - 1) >> 32) {
1167 "We never expected a Global GTT with more than 32bits"
1168 " of address space! Found %lldM!\n",
1169 ggtt->vm.total >> 20);
1170 ggtt->vm.total = 1ULL << 32;
1171 ggtt->mappable_end =
1172 min_t(u64, ggtt->mappable_end, ggtt->vm.total);
1175 if (ggtt->mappable_end > ggtt->vm.total) {
1177 "mappable aperture extends past end of GGTT,"
1178 " aperture=%pa, total=%llx\n",
1179 &ggtt->mappable_end, ggtt->vm.total);
1180 ggtt->mappable_end = ggtt->vm.total;
1183 /* GMADR is the PCI mmio aperture into the global GTT. */
1184 drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
1185 drm_dbg(&i915->drm, "GMADR size = %lluM\n",
1186 (u64)ggtt->mappable_end >> 20);
1187 drm_dbg(&i915->drm, "DSM size = %lluM\n",
1188 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
1194 * i915_ggtt_probe_hw - Probe GGTT hardware location
1195 * @i915: i915 device
1197 int i915_ggtt_probe_hw(struct drm_i915_private *i915)
1201 ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
1205 if (i915_vtd_active(i915))
1206 drm_info(&i915->drm, "VT-d active for gfx access\n");
1211 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
1213 if (GRAPHICS_VER(i915) < 6)
1214 return intel_ggtt_gmch_enable_hw(i915);
1219 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
1221 GEM_BUG_ON(ggtt->invalidate != gen8_ggtt_invalidate);
1223 ggtt->invalidate = guc_ggtt_invalidate;
1225 ggtt->invalidate(ggtt);
1228 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
1230 /* XXX Temporary pardon for error unload */
1231 if (ggtt->invalidate == gen8_ggtt_invalidate)
1234 /* We should only be called after i915_ggtt_enable_guc() */
1235 GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
1237 ggtt->invalidate = gen8_ggtt_invalidate;
1239 ggtt->invalidate(ggtt);
1243 * i915_ggtt_resume_vm - Restore the memory mappings for a GGTT or DPT VM
1244 * @vm: The VM to restore the mappings for
1246 * Restore the memory mappings for all objects mapped to HW via the GGTT or a
1249 * Returns %true if restoring the mapping for any object that was in a write
1250 * domain before suspend.
1252 bool i915_ggtt_resume_vm(struct i915_address_space *vm)
1254 struct i915_vma *vma;
1255 bool write_domain_objs = false;
1258 drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
1261 * First fill our portion of the GTT with scratch pages if
1262 * they were not retained across suspend.
1264 retained_ptes = suspend_retains_ptes(vm) &&
1265 !i915_vm_to_ggtt(vm)->pte_lost &&
1266 !GEM_WARN_ON(i915_vm_to_ggtt(vm)->probed_pte != read_last_pte(vm));
1269 vm->clear_range(vm, 0, vm->total);
1271 /* clflush objects bound into the GGTT and rebind them. */
1272 list_for_each_entry(vma, &vm->bound_list, vm_link) {
1273 struct drm_i915_gem_object *obj = vma->obj;
1274 unsigned int was_bound =
1275 atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
1277 GEM_BUG_ON(!was_bound);
1279 vma->ops->bind_vma(vm, NULL, vma->resource,
1280 obj ? obj->cache_level : 0,
1282 if (obj) { /* only used during resume => exclusive access */
1283 write_domain_objs |= fetch_and_zero(&obj->write_domain);
1284 obj->read_domains |= I915_GEM_DOMAIN_GTT;
1288 return write_domain_objs;
1291 void i915_ggtt_resume(struct i915_ggtt *ggtt)
1295 intel_gt_check_and_clear_faults(ggtt->vm.gt);
1297 flush = i915_ggtt_resume_vm(&ggtt->vm);
1299 ggtt->invalidate(ggtt);
1302 wbinvd_on_all_cpus();
1304 if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
1305 setup_private_pat(ggtt->vm.gt->uncore);
1307 intel_ggtt_restore_fences(ggtt);
1310 void i915_ggtt_mark_pte_lost(struct drm_i915_private *i915, bool val)
1312 to_gt(i915)->ggtt->pte_lost = val;