1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
8 #include "intel_context.h"
9 #include "intel_engine_pm.h"
10 #include "intel_gpu_commands.h"
11 #include "intel_lrc.h"
12 #include "intel_lrc_reg.h"
13 #include "intel_ring.h"
14 #include "intel_sseu.h"
16 static int gen8_emit_rpcs_config(struct i915_request *rq,
17 const struct intel_context *ce,
18 const struct intel_sseu sseu)
23 cs = intel_ring_begin(rq, 4);
27 offset = i915_ggtt_offset(ce->state) +
28 LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4;
30 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
31 *cs++ = lower_32_bits(offset);
32 *cs++ = upper_32_bits(offset);
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
35 intel_ring_advance(rq, cs);
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu)
43 struct i915_request *rq;
46 lockdep_assert_held(&ce->pin_mutex);
49 * If the context is not idle, we have to submit an ordered request to
50 * modify its context image via the kernel context (writing to our own
51 * image, or into the registers directory, does not stick). Pristine
52 * and idle contexts will be configured on pinning.
54 if (!intel_context_pin_if_active(ce))
57 rq = intel_engine_create_kernel_request(ce->engine);
63 /* Serialise with the remote context */
64 ret = intel_context_prepare_remote_request(ce, rq);
66 ret = gen8_emit_rpcs_config(rq, ce, sseu);
70 intel_context_unpin(ce);
75 intel_context_reconfigure_sseu(struct intel_context *ce,
76 const struct intel_sseu sseu)
80 GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
82 ret = intel_context_lock_pinned(ce);
86 /* Nothing to do if unmodified. */
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
90 ret = gen8_modify_rpcs(ce, sseu);
95 intel_context_unlock_pinned(ce);