1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include "gen6_engine_cs.h"
7 #include "intel_engine.h"
8 #include "intel_engine_regs.h"
9 #include "intel_gpu_commands.h"
11 #include "intel_gt_irq.h"
12 #include "intel_gt_pm_irq.h"
13 #include "intel_ring.h"
15 #define HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32))
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
19 * implementing two workarounds on gen6. From section 1.4.7.1
20 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
30 * And the workaround for these two requires this workaround first:
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
36 * And this last workaround is tricky because of the requirements on
37 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
40 * "1 of the following must also be set:
41 * - Render Target Cache Flush Enable ([12] of DW1)
42 * - Depth Cache Flush Enable ([0] of DW1)
43 * - Stall at Pixel Scoreboard ([1] of DW1)
44 * - Depth Stall ([13] of DW1)
45 * - Post-Sync Operation ([13] of DW1)
46 * - Notify Enable ([8] of DW1)"
48 * The cache flushes require the workaround flush that triggered this
49 * one, so we can't use it. Depth stall would trigger the same.
50 * Post-sync nonzero is what triggered this second workaround, so we
51 * can't use that one either. Notify enable is IRQs, which aren't
52 * really our business. That leaves only stall at scoreboard.
55 gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
58 intel_gt_scratch_offset(rq->engine->gt,
59 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
62 cs = intel_ring_begin(rq, 6);
66 *cs++ = GFX_OP_PIPE_CONTROL(5);
67 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
68 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
69 *cs++ = 0; /* low dword */
70 *cs++ = 0; /* high dword */
72 intel_ring_advance(rq, cs);
74 cs = intel_ring_begin(rq, 6);
78 *cs++ = GFX_OP_PIPE_CONTROL(5);
79 *cs++ = PIPE_CONTROL_QW_WRITE;
80 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
84 intel_ring_advance(rq, cs);
89 int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode)
92 intel_gt_scratch_offset(rq->engine->gt,
93 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
97 /* Force SNB workarounds for PIPE_CONTROL flushes */
98 ret = gen6_emit_post_sync_nonzero_flush(rq);
103 * Just flush everything. Experiments have shown that reducing the
104 * number of bits based on the write domains has little performance
105 * impact. And when rearranging requests, the order of flushes is
108 if (mode & EMIT_FLUSH) {
109 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
110 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
112 * Ensure that any following seqno writes only happen
113 * when the render cache is indeed flushed.
115 flags |= PIPE_CONTROL_CS_STALL;
117 if (mode & EMIT_INVALIDATE) {
118 flags |= PIPE_CONTROL_TLB_INVALIDATE;
119 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
120 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
121 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
122 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
123 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
125 * TLB invalidate requires a post-sync write.
127 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
130 cs = intel_ring_begin(rq, 4);
134 *cs++ = GFX_OP_PIPE_CONTROL(4);
136 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
138 intel_ring_advance(rq, cs);
143 u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
145 /* First we do the gen6_emit_post_sync_nonzero_flush w/a */
146 *cs++ = GFX_OP_PIPE_CONTROL(4);
147 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
151 *cs++ = GFX_OP_PIPE_CONTROL(4);
152 *cs++ = PIPE_CONTROL_QW_WRITE;
153 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
154 INTEL_GT_SCRATCH_FIELD_DEFAULT) |
155 PIPE_CONTROL_GLOBAL_GTT;
158 /* Finally we can flush and with it emit the breadcrumb */
159 *cs++ = GFX_OP_PIPE_CONTROL(4);
160 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
161 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
162 PIPE_CONTROL_DC_FLUSH_ENABLE |
163 PIPE_CONTROL_QW_WRITE |
164 PIPE_CONTROL_CS_STALL);
165 *cs++ = i915_request_active_seqno(rq) |
166 PIPE_CONTROL_GLOBAL_GTT;
167 *cs++ = rq->fence.seqno;
169 *cs++ = MI_USER_INTERRUPT;
172 rq->tail = intel_ring_offset(rq, cs);
173 assert_ring_tail_valid(rq->ring, rq->tail);
178 static int mi_flush_dw(struct i915_request *rq, u32 flags)
182 cs = intel_ring_begin(rq, 4);
189 * We always require a command barrier so that subsequent
190 * commands, such as breadcrumb interrupts, are strictly ordered
191 * wrt the contents of the write cache being flushed to memory
192 * (and thus being coherent from the CPU).
194 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
197 * Bspec vol 1c.3 - blitter engine command streamer:
198 * "If ENABLED, all TLBs will be invalidated once the flush
199 * operation is complete. This bit is only valid when the
200 * Post-Sync Operation field is a value of 1h or 3h."
205 *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
209 intel_ring_advance(rq, cs);
214 static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
216 return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
219 int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode)
221 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
224 int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode)
226 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
229 int gen6_emit_bb_start(struct i915_request *rq,
231 unsigned int dispatch_flags)
236 security = MI_BATCH_NON_SECURE_I965;
237 if (dispatch_flags & I915_DISPATCH_SECURE)
240 cs = intel_ring_begin(rq, 2);
244 cs = __gen6_emit_bb_start(cs, offset, security);
245 intel_ring_advance(rq, cs);
251 hsw_emit_bb_start(struct i915_request *rq,
253 unsigned int dispatch_flags)
258 security = MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW;
259 if (dispatch_flags & I915_DISPATCH_SECURE)
262 cs = intel_ring_begin(rq, 2);
266 cs = __gen6_emit_bb_start(cs, offset, security);
267 intel_ring_advance(rq, cs);
272 static int gen7_stall_cs(struct i915_request *rq)
276 cs = intel_ring_begin(rq, 4);
280 *cs++ = GFX_OP_PIPE_CONTROL(4);
281 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
284 intel_ring_advance(rq, cs);
289 int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode)
292 intel_gt_scratch_offset(rq->engine->gt,
293 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
297 * Ensure that any following seqno writes only happen when the render
298 * cache is indeed flushed.
300 * Workaround: 4th PIPE_CONTROL command (except the ones with only
301 * read-cache invalidate bits set) must have the CS_STALL bit set. We
302 * don't try to be clever and just set it unconditionally.
304 flags |= PIPE_CONTROL_CS_STALL;
307 * CS_STALL suggests at least a post-sync write.
309 flags |= PIPE_CONTROL_QW_WRITE;
310 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
313 * Just flush everything. Experiments have shown that reducing the
314 * number of bits based on the write domains has little performance
317 if (mode & EMIT_FLUSH) {
318 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
319 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
320 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
321 flags |= PIPE_CONTROL_FLUSH_ENABLE;
323 if (mode & EMIT_INVALIDATE) {
324 flags |= PIPE_CONTROL_TLB_INVALIDATE;
325 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
326 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
327 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
328 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
329 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
330 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
333 * Workaround: we must issue a pipe_control with CS-stall bit
334 * set before a pipe_control command that has the state cache
335 * invalidate bit set.
340 cs = intel_ring_begin(rq, 4);
344 *cs++ = GFX_OP_PIPE_CONTROL(4);
346 *cs++ = scratch_addr;
348 intel_ring_advance(rq, cs);
353 u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
355 *cs++ = GFX_OP_PIPE_CONTROL(4);
356 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
357 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
358 PIPE_CONTROL_DC_FLUSH_ENABLE |
359 PIPE_CONTROL_FLUSH_ENABLE |
360 PIPE_CONTROL_QW_WRITE |
361 PIPE_CONTROL_GLOBAL_GTT_IVB |
362 PIPE_CONTROL_CS_STALL);
363 *cs++ = i915_request_active_seqno(rq);
364 *cs++ = rq->fence.seqno;
366 *cs++ = MI_USER_INTERRUPT;
369 rq->tail = intel_ring_offset(rq, cs);
370 assert_ring_tail_valid(rq->ring, rq->tail);
375 u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
377 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
378 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
380 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
381 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
382 *cs++ = rq->fence.seqno;
384 *cs++ = MI_USER_INTERRUPT;
386 rq->tail = intel_ring_offset(rq, cs);
387 assert_ring_tail_valid(rq->ring, rq->tail);
392 #define GEN7_XCS_WA 32
393 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
397 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
398 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
400 *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
401 MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
402 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
403 *cs++ = rq->fence.seqno;
405 for (i = 0; i < GEN7_XCS_WA; i++) {
406 *cs++ = MI_STORE_DWORD_INDEX;
407 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
408 *cs++ = rq->fence.seqno;
415 *cs++ = MI_USER_INTERRUPT;
418 rq->tail = intel_ring_offset(rq, cs);
419 assert_ring_tail_valid(rq->ring, rq->tail);
425 void gen6_irq_enable(struct intel_engine_cs *engine)
427 ENGINE_WRITE(engine, RING_IMR,
428 ~(engine->irq_enable_mask | engine->irq_keep_mask));
430 /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
431 ENGINE_POSTING_READ(engine, RING_IMR);
433 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
436 void gen6_irq_disable(struct intel_engine_cs *engine)
438 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
439 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
442 void hsw_irq_enable_vecs(struct intel_engine_cs *engine)
444 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
446 /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
447 ENGINE_POSTING_READ(engine, RING_IMR);
449 gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask);
452 void hsw_irq_disable_vecs(struct intel_engine_cs *engine)
454 ENGINE_WRITE(engine, RING_IMR, ~0);
455 gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask);