2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017 Intel Corporation
7 #include <linux/prime_numbers.h>
9 #include "gem/i915_gem_pm.h"
10 #include "gt/intel_reset.h"
11 #include "i915_selftest.h"
13 #include "gem/selftests/igt_gem_utils.h"
14 #include "selftests/i915_random.h"
15 #include "selftests/igt_flush_test.h"
16 #include "selftests/igt_live_test.h"
17 #include "selftests/igt_reset.h"
18 #include "selftests/igt_spinner.h"
19 #include "selftests/mock_drm.h"
20 #include "selftests/mock_gem_device.h"
22 #include "huge_gem_object.h"
23 #include "igt_gem_utils.h"
25 #define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
27 static int live_nop_switch(void *arg)
29 const unsigned int nctx = 1024;
30 struct drm_i915_private *i915 = arg;
31 struct intel_engine_cs *engine;
32 struct i915_gem_context **ctx;
33 enum intel_engine_id id;
34 intel_wakeref_t wakeref;
35 struct igt_live_test t;
36 struct drm_file *file;
41 * Create as many contexts as we can feasibly get away with
42 * and check we can switch between them rapidly.
44 * Serves as very simple stress test for submission and HW switching
48 if (!DRIVER_CAPS(i915)->has_logical_contexts)
51 file = mock_file(i915);
55 mutex_lock(&i915->drm.struct_mutex);
56 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
58 ctx = kcalloc(nctx, sizeof(*ctx), GFP_KERNEL);
64 for (n = 0; n < nctx; n++) {
65 ctx[n] = live_context(i915, file);
67 err = PTR_ERR(ctx[n]);
72 for_each_engine(engine, i915, id) {
73 struct i915_request *rq;
74 unsigned long end_time, prime;
75 ktime_t times[2] = {};
77 times[0] = ktime_get_raw();
78 for (n = 0; n < nctx; n++) {
79 rq = igt_request_alloc(ctx[n], engine);
86 if (i915_request_wait(rq,
89 pr_err("Failed to populated %d contexts\n", nctx);
90 i915_gem_set_wedged(i915);
95 times[1] = ktime_get_raw();
97 pr_info("Populated %d contexts on %s in %lluns\n",
98 nctx, engine->name, ktime_to_ns(times[1] - times[0]));
100 err = igt_live_test_begin(&t, i915, __func__, engine->name);
104 end_time = jiffies + i915_selftest.timeout_jiffies;
105 for_each_prime_number_from(prime, 2, 8192) {
106 times[1] = ktime_get_raw();
108 for (n = 0; n < prime; n++) {
109 rq = igt_request_alloc(ctx[n % nctx], engine);
116 * This space is left intentionally blank.
118 * We do not actually want to perform any
119 * action with this request, we just want
120 * to measure the latency in allocation
121 * and submission of our breadcrumbs -
122 * ensuring that the bare request is sufficient
123 * for the system to work (i.e. proper HEAD
124 * tracking of the rings, interrupt handling,
125 * etc). It also gives us the lowest bounds
129 i915_request_add(rq);
131 if (i915_request_wait(rq,
134 pr_err("Switching between %ld contexts timed out\n",
136 i915_gem_set_wedged(i915);
140 times[1] = ktime_sub(ktime_get_raw(), times[1]);
144 if (__igt_timeout(end_time, NULL))
148 err = igt_live_test_end(&t);
152 pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
154 ktime_to_ns(times[0]),
155 prime - 1, div64_u64(ktime_to_ns(times[1]), prime - 1));
159 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
160 mutex_unlock(&i915->drm.struct_mutex);
161 mock_file_free(i915, file);
165 static struct i915_vma *
166 gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value)
168 struct drm_i915_gem_object *obj;
169 const int gen = INTEL_GEN(vma->vm->i915);
170 unsigned long n, size;
174 size = (4 * count + 1) * sizeof(u32);
175 size = round_up(size, PAGE_SIZE);
176 obj = i915_gem_object_create_internal(vma->vm->i915, size);
178 return ERR_CAST(obj);
180 cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
186 GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
187 offset += vma->node.start;
189 for (n = 0; n < count; n++) {
191 *cmd++ = MI_STORE_DWORD_IMM_GEN4;
192 *cmd++ = lower_32_bits(offset);
193 *cmd++ = upper_32_bits(offset);
195 } else if (gen >= 4) {
196 *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
197 (gen < 6 ? MI_USE_GGTT : 0);
202 *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
208 *cmd = MI_BATCH_BUFFER_END;
209 i915_gem_object_flush_map(obj);
210 i915_gem_object_unpin_map(obj);
212 vma = i915_vma_instance(obj, vma->vm, NULL);
218 err = i915_vma_pin(vma, 0, 0, PIN_USER);
225 i915_gem_object_put(obj);
229 static unsigned long real_page_count(struct drm_i915_gem_object *obj)
231 return huge_gem_object_phys_size(obj) >> PAGE_SHIFT;
234 static unsigned long fake_page_count(struct drm_i915_gem_object *obj)
236 return huge_gem_object_dma_size(obj) >> PAGE_SHIFT;
239 static int gpu_fill(struct drm_i915_gem_object *obj,
240 struct i915_gem_context *ctx,
241 struct intel_engine_cs *engine,
244 struct drm_i915_private *i915 = to_i915(obj->base.dev);
245 struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
246 struct i915_request *rq;
247 struct i915_vma *vma;
248 struct i915_vma *batch;
252 GEM_BUG_ON(obj->base.size > vm->total);
253 GEM_BUG_ON(!intel_engine_can_store_dword(engine));
255 vma = i915_vma_instance(obj, vm, NULL);
259 i915_gem_object_lock(obj);
260 err = i915_gem_object_set_to_gtt_domain(obj, false);
261 i915_gem_object_unlock(obj);
265 err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
269 /* Within the GTT the huge objects maps every page onto
270 * its 1024 real pages (using phys_pfn = dma_pfn % 1024).
271 * We set the nth dword within the page using the nth
272 * mapping via the GTT - this should exercise the GTT mapping
273 * whilst checking that each context provides a unique view
276 batch = gpu_fill_dw(vma,
277 (dw * real_page_count(obj)) << PAGE_SHIFT |
279 real_page_count(obj),
282 err = PTR_ERR(batch);
286 rq = igt_request_alloc(ctx, engine);
293 if (INTEL_GEN(vm->i915) <= 5)
294 flags |= I915_DISPATCH_SECURE;
296 err = engine->emit_bb_start(rq,
297 batch->node.start, batch->node.size,
302 i915_vma_lock(batch);
303 err = i915_vma_move_to_active(batch, rq, 0);
304 i915_vma_unlock(batch);
309 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
310 i915_vma_unlock(vma);
314 i915_request_add(rq);
316 i915_vma_unpin(batch);
317 i915_vma_close(batch);
325 i915_request_skip(rq, err);
327 i915_request_add(rq);
329 i915_vma_unpin(batch);
336 static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
338 const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
339 unsigned int n, m, need_flush;
342 err = i915_gem_object_prepare_write(obj, &need_flush);
346 for (n = 0; n < real_page_count(obj); n++) {
349 map = kmap_atomic(i915_gem_object_get_page(obj, n));
350 for (m = 0; m < DW_PER_PAGE; m++)
353 drm_clflush_virt_range(map, PAGE_SIZE);
357 i915_gem_object_finish_access(obj);
358 obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
359 obj->write_domain = 0;
363 static noinline int cpu_check(struct drm_i915_gem_object *obj,
364 unsigned int idx, unsigned int max)
366 unsigned int n, m, needs_flush;
369 err = i915_gem_object_prepare_read(obj, &needs_flush);
373 for (n = 0; n < real_page_count(obj); n++) {
376 map = kmap_atomic(i915_gem_object_get_page(obj, n));
377 if (needs_flush & CLFLUSH_BEFORE)
378 drm_clflush_virt_range(map, PAGE_SIZE);
380 for (m = 0; m < max; m++) {
382 pr_err("%pS: Invalid value at object %d page %d/%ld, offset %d/%d: found %x expected %x\n",
383 __builtin_return_address(0), idx,
384 n, real_page_count(obj), m, max,
391 for (; m < DW_PER_PAGE; m++) {
392 if (map[m] != STACK_MAGIC) {
393 pr_err("%pS: Invalid value at object %d page %d, offset %d: found %x expected %x (uninitialised)\n",
394 __builtin_return_address(0), idx, n, m,
395 map[m], STACK_MAGIC);
407 i915_gem_object_finish_access(obj);
411 static int file_add_object(struct drm_file *file,
412 struct drm_i915_gem_object *obj)
416 GEM_BUG_ON(obj->base.handle_count);
418 /* tie the object to the drm_file for easy reaping */
419 err = idr_alloc(&file->object_idr, &obj->base, 1, 0, GFP_KERNEL);
423 i915_gem_object_get(obj);
424 obj->base.handle_count++;
428 static struct drm_i915_gem_object *
429 create_test_object(struct i915_gem_context *ctx,
430 struct drm_file *file,
431 struct list_head *objects)
433 struct drm_i915_gem_object *obj;
434 struct i915_address_space *vm = ctx->vm ?: &ctx->i915->ggtt.vm;
438 size = min(vm->total / 2, 1024ull * DW_PER_PAGE * PAGE_SIZE);
439 size = round_down(size, DW_PER_PAGE * PAGE_SIZE);
441 obj = huge_gem_object(ctx->i915, DW_PER_PAGE * PAGE_SIZE, size);
445 err = file_add_object(file, obj);
446 i915_gem_object_put(obj);
450 err = cpu_fill(obj, STACK_MAGIC);
452 pr_err("Failed to fill object with cpu, err=%d\n",
457 list_add_tail(&obj->st_link, objects);
461 static unsigned long max_dwords(struct drm_i915_gem_object *obj)
463 unsigned long npages = fake_page_count(obj);
465 GEM_BUG_ON(!IS_ALIGNED(npages, DW_PER_PAGE));
466 return npages / DW_PER_PAGE;
469 static int igt_ctx_exec(void *arg)
471 struct drm_i915_private *i915 = arg;
472 struct intel_engine_cs *engine;
473 enum intel_engine_id id;
477 * Create a few different contexts (with different mm) and write
478 * through each ctx/mm using the GPU making sure those writes end
479 * up in the expected pages of our obj.
482 if (!DRIVER_CAPS(i915)->has_logical_contexts)
485 for_each_engine(engine, i915, id) {
486 struct drm_i915_gem_object *obj = NULL;
487 unsigned long ncontexts, ndwords, dw;
488 struct igt_live_test t;
489 struct drm_file *file;
490 IGT_TIMEOUT(end_time);
493 if (!intel_engine_can_store_dword(engine))
496 if (!engine->context_size)
497 continue; /* No logical context support in HW */
499 file = mock_file(i915);
501 return PTR_ERR(file);
503 mutex_lock(&i915->drm.struct_mutex);
505 err = igt_live_test_begin(&t, i915, __func__, engine->name);
512 while (!time_after(jiffies, end_time)) {
513 struct i915_gem_context *ctx;
514 intel_wakeref_t wakeref;
516 ctx = live_context(i915, file);
523 obj = create_test_object(ctx, file, &objects);
530 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
531 err = gpu_fill(obj, ctx, engine, dw);
533 pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
534 ndwords, dw, max_dwords(obj),
535 engine->name, ctx->hw_id,
536 yesno(!!ctx->vm), err);
540 if (++dw == max_dwords(obj)) {
549 pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
550 ncontexts, engine->name, ndwords);
553 list_for_each_entry(obj, &objects, st_link) {
555 min_t(unsigned int, ndwords - dw, max_dwords(obj));
557 err = cpu_check(obj, ncontexts++, rem);
565 if (igt_live_test_end(&t))
567 mutex_unlock(&i915->drm.struct_mutex);
569 mock_file_free(i915, file);
577 static int igt_shared_ctx_exec(void *arg)
579 struct drm_i915_private *i915 = arg;
580 struct i915_gem_context *parent;
581 struct intel_engine_cs *engine;
582 enum intel_engine_id id;
583 struct igt_live_test t;
584 struct drm_file *file;
588 * Create a few different contexts with the same mm and write
589 * through each ctx using the GPU making sure those writes end
590 * up in the expected pages of our obj.
592 if (!DRIVER_CAPS(i915)->has_logical_contexts)
595 file = mock_file(i915);
597 return PTR_ERR(file);
599 mutex_lock(&i915->drm.struct_mutex);
601 parent = live_context(i915, file);
602 if (IS_ERR(parent)) {
603 err = PTR_ERR(parent);
607 if (!parent->vm) { /* not full-ppgtt; nothing to share */
612 err = igt_live_test_begin(&t, i915, __func__, "");
616 for_each_engine(engine, i915, id) {
617 unsigned long ncontexts, ndwords, dw;
618 struct drm_i915_gem_object *obj = NULL;
619 IGT_TIMEOUT(end_time);
622 if (!intel_engine_can_store_dword(engine))
628 while (!time_after(jiffies, end_time)) {
629 struct i915_gem_context *ctx;
630 intel_wakeref_t wakeref;
632 ctx = kernel_context(i915);
638 __assign_ppgtt(ctx, parent->vm);
641 obj = create_test_object(parent, file, &objects);
644 kernel_context_close(ctx);
650 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
651 err = gpu_fill(obj, ctx, engine, dw);
653 pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
654 ndwords, dw, max_dwords(obj),
655 engine->name, ctx->hw_id,
656 yesno(!!ctx->vm), err);
657 kernel_context_close(ctx);
661 if (++dw == max_dwords(obj)) {
669 kernel_context_close(ctx);
671 pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
672 ncontexts, engine->name, ndwords);
675 list_for_each_entry(obj, &objects, st_link) {
677 min_t(unsigned int, ndwords - dw, max_dwords(obj));
679 err = cpu_check(obj, ncontexts++, rem);
687 if (igt_live_test_end(&t))
690 mutex_unlock(&i915->drm.struct_mutex);
692 mock_file_free(i915, file);
696 static struct i915_vma *rpcs_query_batch(struct i915_vma *vma)
698 struct drm_i915_gem_object *obj;
702 if (INTEL_GEN(vma->vm->i915) < 8)
703 return ERR_PTR(-EINVAL);
705 obj = i915_gem_object_create_internal(vma->vm->i915, PAGE_SIZE);
707 return ERR_CAST(obj);
709 cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
715 *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
716 *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
717 *cmd++ = lower_32_bits(vma->node.start);
718 *cmd++ = upper_32_bits(vma->node.start);
719 *cmd = MI_BATCH_BUFFER_END;
721 __i915_gem_object_flush_map(obj, 0, 64);
722 i915_gem_object_unpin_map(obj);
724 vma = i915_vma_instance(obj, vma->vm, NULL);
730 err = i915_vma_pin(vma, 0, 0, PIN_USER);
737 i915_gem_object_put(obj);
742 emit_rpcs_query(struct drm_i915_gem_object *obj,
743 struct intel_context *ce,
744 struct i915_request **rq_out)
746 struct i915_request *rq;
747 struct i915_vma *batch;
748 struct i915_vma *vma;
751 GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
753 vma = i915_vma_instance(obj, ce->gem_context->vm, NULL);
757 i915_gem_object_lock(obj);
758 err = i915_gem_object_set_to_gtt_domain(obj, false);
759 i915_gem_object_unlock(obj);
763 err = i915_vma_pin(vma, 0, 0, PIN_USER);
767 batch = rpcs_query_batch(vma);
769 err = PTR_ERR(batch);
773 rq = i915_request_create(ce);
779 err = rq->engine->emit_bb_start(rq,
780 batch->node.start, batch->node.size,
785 i915_vma_lock(batch);
786 err = i915_vma_move_to_active(batch, rq, 0);
787 i915_vma_unlock(batch);
792 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
793 i915_vma_unlock(vma);
797 i915_vma_unpin(batch);
798 i915_vma_close(batch);
803 *rq_out = i915_request_get(rq);
805 i915_request_add(rq);
810 i915_request_skip(rq, err);
812 i915_request_add(rq);
814 i915_vma_unpin(batch);
822 #define TEST_IDLE BIT(0)
823 #define TEST_BUSY BIT(1)
824 #define TEST_RESET BIT(2)
827 __sseu_prepare(struct drm_i915_private *i915,
830 struct intel_context *ce,
831 struct igt_spinner **spin)
833 struct i915_request *rq;
837 if (!(flags & (TEST_BUSY | TEST_RESET)))
840 *spin = kzalloc(sizeof(**spin), GFP_KERNEL);
844 ret = igt_spinner_init(*spin, i915);
848 rq = igt_spinner_create_request(*spin,
857 i915_request_add(rq);
859 if (!igt_wait_for_spinner(*spin, rq)) {
860 pr_err("%s: Spinner failed to start!\n", name);
868 igt_spinner_end(*spin);
870 igt_spinner_fini(*spin);
872 kfree(fetch_and_zero(spin));
877 __read_slice_count(struct drm_i915_private *i915,
878 struct intel_context *ce,
879 struct drm_i915_gem_object *obj,
880 struct igt_spinner *spin,
883 struct i915_request *rq = NULL;
889 ret = emit_rpcs_query(obj, ce, &rq);
894 igt_spinner_end(spin);
896 ret = i915_request_wait(rq, I915_WAIT_LOCKED, MAX_SCHEDULE_TIMEOUT);
897 i915_request_put(rq);
901 buf = i915_gem_object_pin_map(obj, I915_MAP_WB);
907 if (INTEL_GEN(i915) >= 11) {
908 s_mask = GEN11_RPCS_S_CNT_MASK;
909 s_shift = GEN11_RPCS_S_CNT_SHIFT;
911 s_mask = GEN8_RPCS_S_CNT_MASK;
912 s_shift = GEN8_RPCS_S_CNT_SHIFT;
916 cnt = (val & s_mask) >> s_shift;
919 i915_gem_object_unpin_map(obj);
925 __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected,
926 const char *prefix, const char *suffix)
928 if (slices == expected)
932 pr_err("%s: %s read slice count failed with %d%s\n",
933 name, prefix, slices, suffix);
937 pr_err("%s: %s slice count %d is not %u%s\n",
938 name, prefix, slices, expected, suffix);
940 pr_info("RPCS=0x%x; %u%sx%u%s\n",
942 (rpcs & GEN8_RPCS_S_CNT_ENABLE) ? "*" : "",
943 (rpcs & GEN8_RPCS_SS_CNT_MASK) >> GEN8_RPCS_SS_CNT_SHIFT,
944 (rpcs & GEN8_RPCS_SS_CNT_ENABLE) ? "*" : "");
950 __sseu_finish(struct drm_i915_private *i915,
953 struct intel_context *ce,
954 struct drm_i915_gem_object *obj,
955 unsigned int expected,
956 struct igt_spinner *spin)
958 unsigned int slices = hweight32(ce->engine->sseu.slice_mask);
962 if (flags & TEST_RESET) {
963 ret = i915_reset_engine(ce->engine, "sseu");
968 ret = __read_slice_count(i915, ce, obj,
969 flags & TEST_RESET ? NULL : spin, &rpcs);
970 ret = __check_rpcs(name, rpcs, ret, expected, "Context", "!");
974 ret = __read_slice_count(i915, ce->engine->kernel_context, obj,
976 ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!");
980 igt_spinner_end(spin);
982 if ((flags & TEST_IDLE) && ret == 0) {
983 ret = i915_gem_wait_for_idle(i915,
985 MAX_SCHEDULE_TIMEOUT);
989 ret = __read_slice_count(i915, ce, obj, NULL, &rpcs);
990 ret = __check_rpcs(name, rpcs, ret, expected,
991 "Context", " after idle!");
998 __sseu_test(struct drm_i915_private *i915,
1001 struct intel_context *ce,
1002 struct drm_i915_gem_object *obj,
1003 struct intel_sseu sseu)
1005 struct igt_spinner *spin = NULL;
1008 ret = __sseu_prepare(i915, name, flags, ce, &spin);
1012 ret = __intel_context_reconfigure_sseu(ce, sseu);
1016 ret = __sseu_finish(i915, name, flags, ce, obj,
1017 hweight32(sseu.slice_mask), spin);
1021 igt_spinner_end(spin);
1022 igt_spinner_fini(spin);
1029 __igt_ctx_sseu(struct drm_i915_private *i915,
1033 struct intel_engine_cs *engine = i915->engine[RCS0];
1034 struct intel_sseu default_sseu = engine->sseu;
1035 struct drm_i915_gem_object *obj;
1036 struct i915_gem_context *ctx;
1037 struct intel_context *ce;
1038 struct intel_sseu pg_sseu;
1039 intel_wakeref_t wakeref;
1040 struct drm_file *file;
1043 if (INTEL_GEN(i915) < 9)
1046 if (!RUNTIME_INFO(i915)->sseu.has_slice_pg)
1049 if (hweight32(default_sseu.slice_mask) < 2)
1053 * Gen11 VME friendly power-gated configuration with half enabled
1056 pg_sseu = default_sseu;
1057 pg_sseu.slice_mask = 1;
1058 pg_sseu.subslice_mask =
1059 ~(~0 << (hweight32(default_sseu.subslice_mask) / 2));
1061 pr_info("SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n",
1062 name, flags, hweight32(default_sseu.slice_mask),
1063 hweight32(pg_sseu.slice_mask));
1065 file = mock_file(i915);
1067 return PTR_ERR(file);
1069 if (flags & TEST_RESET)
1070 igt_global_reset_lock(i915);
1072 mutex_lock(&i915->drm.struct_mutex);
1074 ctx = live_context(i915, file);
1079 i915_gem_context_clear_bannable(ctx); /* to reset and beyond! */
1081 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1087 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1089 ce = i915_gem_context_get_engine(ctx, RCS0);
1095 ret = intel_context_pin(ce);
1099 /* First set the default mask. */
1100 ret = __sseu_test(i915, name, flags, ce, obj, default_sseu);
1104 /* Then set a power-gated configuration. */
1105 ret = __sseu_test(i915, name, flags, ce, obj, pg_sseu);
1109 /* Back to defaults. */
1110 ret = __sseu_test(i915, name, flags, ce, obj, default_sseu);
1114 /* One last power-gated configuration for the road. */
1115 ret = __sseu_test(i915, name, flags, ce, obj, pg_sseu);
1120 if (igt_flush_test(i915, I915_WAIT_LOCKED))
1123 intel_context_unpin(ce);
1125 intel_context_put(ce);
1127 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1128 i915_gem_object_put(obj);
1131 mutex_unlock(&i915->drm.struct_mutex);
1133 if (flags & TEST_RESET)
1134 igt_global_reset_unlock(i915);
1136 mock_file_free(i915, file);
1139 pr_err("%s: Failed with %d!\n", name, ret);
1144 static int igt_ctx_sseu(void *arg)
1149 } *phase, phases[] = {
1150 { .name = "basic", .flags = 0 },
1151 { .name = "idle", .flags = TEST_IDLE },
1152 { .name = "busy", .flags = TEST_BUSY },
1153 { .name = "busy-reset", .flags = TEST_BUSY | TEST_RESET },
1154 { .name = "busy-idle", .flags = TEST_BUSY | TEST_IDLE },
1155 { .name = "reset-idle", .flags = TEST_RESET | TEST_IDLE },
1160 for (i = 0, phase = phases; ret == 0 && i < ARRAY_SIZE(phases);
1162 ret = __igt_ctx_sseu(arg, phase->name, phase->flags);
1167 static int igt_ctx_readonly(void *arg)
1169 struct drm_i915_private *i915 = arg;
1170 struct drm_i915_gem_object *obj = NULL;
1171 struct i915_address_space *vm;
1172 struct i915_gem_context *ctx;
1173 unsigned long idx, ndwords, dw;
1174 struct igt_live_test t;
1175 struct drm_file *file;
1176 I915_RND_STATE(prng);
1177 IGT_TIMEOUT(end_time);
1182 * Create a few read-only objects (with the occasional writable object)
1183 * and try to write into these object checking that the GPU discards
1184 * any write to a read-only object.
1187 file = mock_file(i915);
1189 return PTR_ERR(file);
1191 mutex_lock(&i915->drm.struct_mutex);
1193 err = igt_live_test_begin(&t, i915, __func__, "");
1197 ctx = live_context(i915, file);
1203 vm = ctx->vm ?: &i915->mm.aliasing_ppgtt->vm;
1204 if (!vm || !vm->has_read_only) {
1211 while (!time_after(jiffies, end_time)) {
1212 struct intel_engine_cs *engine;
1215 for_each_engine(engine, i915, id) {
1216 intel_wakeref_t wakeref;
1218 if (!intel_engine_can_store_dword(engine))
1222 obj = create_test_object(ctx, file, &objects);
1228 if (prandom_u32_state(&prng) & 1)
1229 i915_gem_object_set_readonly(obj);
1233 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
1234 err = gpu_fill(obj, ctx, engine, dw);
1236 pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
1237 ndwords, dw, max_dwords(obj),
1238 engine->name, ctx->hw_id,
1239 yesno(!!ctx->vm), err);
1243 if (++dw == max_dwords(obj)) {
1250 pr_info("Submitted %lu dwords (across %u engines)\n",
1251 ndwords, RUNTIME_INFO(i915)->num_engines);
1255 list_for_each_entry(obj, &objects, st_link) {
1257 min_t(unsigned int, ndwords - dw, max_dwords(obj));
1258 unsigned int num_writes;
1261 if (i915_gem_object_is_readonly(obj))
1264 err = cpu_check(obj, idx++, num_writes);
1272 if (igt_live_test_end(&t))
1274 mutex_unlock(&i915->drm.struct_mutex);
1276 mock_file_free(i915, file);
1280 static int check_scratch(struct i915_gem_context *ctx, u64 offset)
1282 struct drm_mm_node *node =
1283 __drm_mm_interval_first(&ctx->vm->mm,
1284 offset, offset + sizeof(u32) - 1);
1285 if (!node || node->start > offset)
1288 GEM_BUG_ON(offset >= node->start + node->size);
1290 pr_err("Target offset 0x%08x_%08x overlaps with a node in the mm!\n",
1291 upper_32_bits(offset), lower_32_bits(offset));
1295 static int write_to_scratch(struct i915_gem_context *ctx,
1296 struct intel_engine_cs *engine,
1297 u64 offset, u32 value)
1299 struct drm_i915_private *i915 = ctx->i915;
1300 struct drm_i915_gem_object *obj;
1301 struct i915_request *rq;
1302 struct i915_vma *vma;
1306 GEM_BUG_ON(offset < I915_GTT_PAGE_SIZE);
1308 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1310 return PTR_ERR(obj);
1312 cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
1318 *cmd++ = MI_STORE_DWORD_IMM_GEN4;
1319 if (INTEL_GEN(i915) >= 8) {
1320 *cmd++ = lower_32_bits(offset);
1321 *cmd++ = upper_32_bits(offset);
1327 *cmd = MI_BATCH_BUFFER_END;
1328 __i915_gem_object_flush_map(obj, 0, 64);
1329 i915_gem_object_unpin_map(obj);
1331 vma = i915_vma_instance(obj, ctx->vm, NULL);
1337 err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_OFFSET_FIXED);
1341 err = check_scratch(ctx, offset);
1345 rq = igt_request_alloc(ctx, engine);
1351 err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
1356 err = i915_vma_move_to_active(vma, rq, 0);
1357 i915_vma_unlock(vma);
1361 i915_vma_unpin(vma);
1362 i915_vma_close(vma);
1365 i915_request_add(rq);
1370 i915_request_skip(rq, err);
1372 i915_request_add(rq);
1374 i915_vma_unpin(vma);
1376 i915_gem_object_put(obj);
1380 static int read_from_scratch(struct i915_gem_context *ctx,
1381 struct intel_engine_cs *engine,
1382 u64 offset, u32 *value)
1384 struct drm_i915_private *i915 = ctx->i915;
1385 struct drm_i915_gem_object *obj;
1386 const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
1387 const u32 result = 0x100;
1388 struct i915_request *rq;
1389 struct i915_vma *vma;
1393 GEM_BUG_ON(offset < I915_GTT_PAGE_SIZE);
1395 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1397 return PTR_ERR(obj);
1399 cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
1405 memset(cmd, POISON_INUSE, PAGE_SIZE);
1406 if (INTEL_GEN(i915) >= 8) {
1407 *cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
1409 *cmd++ = lower_32_bits(offset);
1410 *cmd++ = upper_32_bits(offset);
1411 *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
1416 *cmd++ = MI_LOAD_REGISTER_MEM;
1419 *cmd++ = MI_STORE_REGISTER_MEM;
1423 *cmd = MI_BATCH_BUFFER_END;
1425 i915_gem_object_flush_map(obj);
1426 i915_gem_object_unpin_map(obj);
1428 vma = i915_vma_instance(obj, ctx->vm, NULL);
1434 err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_OFFSET_FIXED);
1438 err = check_scratch(ctx, offset);
1442 rq = igt_request_alloc(ctx, engine);
1448 err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
1453 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1454 i915_vma_unlock(vma);
1458 i915_vma_unpin(vma);
1459 i915_vma_close(vma);
1461 i915_request_add(rq);
1463 i915_gem_object_lock(obj);
1464 err = i915_gem_object_set_to_cpu_domain(obj, false);
1465 i915_gem_object_unlock(obj);
1469 cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
1475 *value = cmd[result / sizeof(*cmd)];
1476 i915_gem_object_unpin_map(obj);
1477 i915_gem_object_put(obj);
1482 i915_request_skip(rq, err);
1484 i915_request_add(rq);
1486 i915_vma_unpin(vma);
1488 i915_gem_object_put(obj);
1492 static int igt_vm_isolation(void *arg)
1494 struct drm_i915_private *i915 = arg;
1495 struct i915_gem_context *ctx_a, *ctx_b;
1496 struct intel_engine_cs *engine;
1497 intel_wakeref_t wakeref;
1498 struct igt_live_test t;
1499 struct drm_file *file;
1500 I915_RND_STATE(prng);
1501 unsigned long count;
1506 if (INTEL_GEN(i915) < 7)
1510 * The simple goal here is that a write into one context is not
1511 * observed in a second (separate page tables and scratch).
1514 file = mock_file(i915);
1516 return PTR_ERR(file);
1518 mutex_lock(&i915->drm.struct_mutex);
1520 err = igt_live_test_begin(&t, i915, __func__, "");
1524 ctx_a = live_context(i915, file);
1525 if (IS_ERR(ctx_a)) {
1526 err = PTR_ERR(ctx_a);
1530 ctx_b = live_context(i915, file);
1531 if (IS_ERR(ctx_b)) {
1532 err = PTR_ERR(ctx_b);
1536 /* We can only test vm isolation, if the vm are distinct */
1537 if (ctx_a->vm == ctx_b->vm)
1540 vm_total = ctx_a->vm->total;
1541 GEM_BUG_ON(ctx_b->vm->total != vm_total);
1542 vm_total -= I915_GTT_PAGE_SIZE;
1544 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1547 for_each_engine(engine, i915, id) {
1548 IGT_TIMEOUT(end_time);
1549 unsigned long this = 0;
1551 if (!intel_engine_can_store_dword(engine))
1554 while (!__igt_timeout(end_time, NULL)) {
1555 u32 value = 0xc5c5c5c5;
1558 div64_u64_rem(i915_prandom_u64_state(&prng),
1560 offset &= -sizeof(u32);
1561 offset += I915_GTT_PAGE_SIZE;
1563 err = write_to_scratch(ctx_a, engine,
1564 offset, 0xdeadbeef);
1566 err = read_from_scratch(ctx_b, engine,
1572 pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
1573 engine->name, value,
1574 upper_32_bits(offset),
1575 lower_32_bits(offset),
1585 pr_info("Checked %lu scratch offsets across %d engines\n",
1586 count, RUNTIME_INFO(i915)->num_engines);
1589 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1591 if (igt_live_test_end(&t))
1593 mutex_unlock(&i915->drm.struct_mutex);
1595 mock_file_free(i915, file);
1599 static __maybe_unused const char *
1600 __engine_name(struct drm_i915_private *i915, intel_engine_mask_t engines)
1602 struct intel_engine_cs *engine;
1603 intel_engine_mask_t tmp;
1605 if (engines == ALL_ENGINES)
1608 for_each_engine_masked(engine, i915, engines, tmp)
1609 return engine->name;
1614 static bool skip_unused_engines(struct intel_context *ce, void *data)
1619 static void mock_barrier_task(void *data)
1621 unsigned int *counter = data;
1626 static int mock_context_barrier(void *arg)
1629 #define pr_fmt(x) "context_barrier_task():" # x
1630 struct drm_i915_private *i915 = arg;
1631 struct i915_gem_context *ctx;
1632 struct i915_request *rq;
1633 unsigned int counter;
1637 * The context barrier provides us with a callback after it emits
1638 * a request; useful for retiring old state after loading new.
1641 mutex_lock(&i915->drm.struct_mutex);
1643 ctx = mock_context(i915, "mock");
1650 err = context_barrier_task(ctx, 0,
1651 NULL, NULL, mock_barrier_task, &counter);
1653 pr_err("Failed at line %d, err=%d\n", __LINE__, err);
1657 pr_err("Did not retire immediately with 0 engines\n");
1663 err = context_barrier_task(ctx, ALL_ENGINES,
1664 skip_unused_engines,
1669 pr_err("Failed at line %d, err=%d\n", __LINE__, err);
1673 pr_err("Did not retire immediately for all unused engines\n");
1678 rq = igt_request_alloc(ctx, i915->engine[RCS0]);
1680 pr_err("Request allocation failed!\n");
1683 i915_request_add(rq);
1686 context_barrier_inject_fault = BIT(RCS0);
1687 err = context_barrier_task(ctx, ALL_ENGINES,
1688 NULL, NULL, mock_barrier_task, &counter);
1689 context_barrier_inject_fault = 0;
1693 pr_err("Did not hit fault injection!\n");
1695 pr_err("Invoked callback on error!\n");
1702 err = context_barrier_task(ctx, ALL_ENGINES,
1703 skip_unused_engines,
1708 pr_err("Failed at line %d, err=%d\n", __LINE__, err);
1711 mock_device_flush(i915);
1713 pr_err("Did not retire on each active engines\n");
1719 mock_context_close(ctx);
1721 mutex_unlock(&i915->drm.struct_mutex);
1727 int i915_gem_context_mock_selftests(void)
1729 static const struct i915_subtest tests[] = {
1730 SUBTEST(mock_context_barrier),
1732 struct drm_i915_private *i915;
1735 i915 = mock_gem_device();
1739 err = i915_subtests(tests, i915);
1741 drm_dev_put(&i915->drm);
1745 int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
1747 static const struct i915_subtest tests[] = {
1748 SUBTEST(live_nop_switch),
1749 SUBTEST(igt_ctx_exec),
1750 SUBTEST(igt_ctx_readonly),
1751 SUBTEST(igt_ctx_sseu),
1752 SUBTEST(igt_shared_ctx_exec),
1753 SUBTEST(igt_vm_isolation),
1756 if (i915_terminally_wedged(dev_priv))
1759 return i915_subtests(tests, dev_priv);