2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008,2010 Intel Corporation
7 #include <linux/intel-iommu.h>
8 #include <linux/reservation.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_syncobj.h>
13 #include <drm/i915_drm.h>
15 #include "display/intel_frontbuffer.h"
17 #include "gem/i915_gem_ioctls.h"
18 #include "gt/intel_context.h"
19 #include "gt/intel_gt_pm.h"
21 #include "i915_gem_ioctls.h"
22 #include "i915_gem_clflush.h"
23 #include "i915_gem_context.h"
24 #include "i915_trace.h"
25 #include "intel_drv.h"
31 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
34 #define __EXEC_OBJECT_HAS_REF BIT(31)
35 #define __EXEC_OBJECT_HAS_PIN BIT(30)
36 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
37 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
38 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
39 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
40 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
42 #define __EXEC_HAS_RELOC BIT(31)
43 #define __EXEC_VALIDATED BIT(30)
44 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
45 #define UPDATE PIN_OFFSET_FIXED
47 #define BATCH_OFFSET_BIAS (256*1024)
49 #define __I915_EXEC_ILLEGAL_FLAGS \
50 (__I915_EXEC_UNKNOWN_FLAGS | \
51 I915_EXEC_CONSTANTS_MASK | \
52 I915_EXEC_RESOURCE_STREAMER)
54 /* Catch emission of unexpected errors for CI! */
55 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
58 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
64 * DOC: User command execution
66 * Userspace submits commands to be executed on the GPU as an instruction
67 * stream within a GEM object we call a batchbuffer. This instructions may
68 * refer to other GEM objects containing auxiliary state such as kernels,
69 * samplers, render targets and even secondary batchbuffers. Userspace does
70 * not know where in the GPU memory these objects reside and so before the
71 * batchbuffer is passed to the GPU for execution, those addresses in the
72 * batchbuffer and auxiliary objects are updated. This is known as relocation,
73 * or patching. To try and avoid having to relocate each object on the next
74 * execution, userspace is told the location of those objects in this pass,
75 * but this remains just a hint as the kernel may choose a new location for
76 * any object in the future.
78 * At the level of talking to the hardware, submitting a batchbuffer for the
79 * GPU to execute is to add content to a buffer from which the HW
80 * command streamer is reading.
82 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
83 * Execlists, this command is not placed on the same buffer as the
86 * 2. Add a command to invalidate caches to the buffer.
88 * 3. Add a batchbuffer start command to the buffer; the start command is
89 * essentially a token together with the GPU address of the batchbuffer
92 * 4. Add a pipeline flush to the buffer.
94 * 5. Add a memory write command to the buffer to record when the GPU
95 * is done executing the batchbuffer. The memory write writes the
96 * global sequence number of the request, ``i915_request::global_seqno``;
97 * the i915 driver uses the current value in the register to determine
98 * if the GPU has completed the batchbuffer.
100 * 6. Add a user interrupt command to the buffer. This command instructs
101 * the GPU to issue an interrupt when the command, pipeline flush and
102 * memory write are completed.
104 * 7. Inform the hardware of the additional commands added to the buffer
105 * (by updating the tail pointer).
107 * Processing an execbuf ioctl is conceptually split up into a few phases.
109 * 1. Validation - Ensure all the pointers, handles and flags are valid.
110 * 2. Reservation - Assign GPU address space for every object
111 * 3. Relocation - Update any addresses to point to the final locations
112 * 4. Serialisation - Order the request with respect to its dependencies
113 * 5. Construction - Construct a request to execute the batchbuffer
114 * 6. Submission (at some point in the future execution)
116 * Reserving resources for the execbuf is the most complicated phase. We
117 * neither want to have to migrate the object in the address space, nor do
118 * we want to have to update any relocations pointing to this object. Ideally,
119 * we want to leave the object where it is and for all the existing relocations
120 * to match. If the object is given a new address, or if userspace thinks the
121 * object is elsewhere, we have to parse all the relocation entries and update
122 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
123 * all the target addresses in all of its objects match the value in the
124 * relocation entries and that they all match the presumed offsets given by the
125 * list of execbuffer objects. Using this knowledge, we know that if we haven't
126 * moved any buffers, all the relocation entries are valid and we can skip
127 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
128 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
130 * The addresses written in the objects must match the corresponding
131 * reloc.presumed_offset which in turn must match the corresponding
134 * Any render targets written to in the batch must be flagged with
137 * To avoid stalling, execobject.offset should match the current
138 * address of that object within the active context.
140 * The reservation is done is multiple phases. First we try and keep any
141 * object already bound in its current location - so as long as meets the
142 * constraints imposed by the new execbuffer. Any object left unbound after the
143 * first pass is then fitted into any available idle space. If an object does
144 * not fit, all objects are removed from the reservation and the process rerun
145 * after sorting the objects into a priority order (more difficult to fit
146 * objects are tried first). Failing that, the entire VM is cleared and we try
147 * to fit the execbuf once last time before concluding that it simply will not
150 * A small complication to all of this is that we allow userspace not only to
151 * specify an alignment and a size for the object in the address space, but
152 * we also allow userspace to specify the exact offset. This objects are
153 * simpler to place (the location is known a priori) all we have to do is make
154 * sure the space is available.
156 * Once all the objects are in place, patching up the buried pointers to point
157 * to the final locations is a fairly simple job of walking over the relocation
158 * entry arrays, looking up the right address and rewriting the value into
159 * the object. Simple! ... The relocation entries are stored in user memory
160 * and so to access them we have to copy them into a local buffer. That copy
161 * has to avoid taking any pagefaults as they may lead back to a GEM object
162 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
163 * the relocation into multiple passes. First we try to do everything within an
164 * atomic context (avoid the pagefaults) which requires that we never wait. If
165 * we detect that we may wait, or if we need to fault, then we have to fallback
166 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
167 * bells yet?) Dropping the mutex means that we lose all the state we have
168 * built up so far for the execbuf and we must reset any global data. However,
169 * we do leave the objects pinned in their final locations - which is a
170 * potential issue for concurrent execbufs. Once we have left the mutex, we can
171 * allocate and copy all the relocation entries into a large array at our
172 * leisure, reacquire the mutex, reclaim all the objects and other state and
173 * then proceed to update any incorrect addresses with the objects.
175 * As we process the relocation entries, we maintain a record of whether the
176 * object is being written to. Using NORELOC, we expect userspace to provide
177 * this information instead. We also check whether we can skip the relocation
178 * by comparing the expected value inside the relocation entry with the target's
179 * final address. If they differ, we have to map the current object and rewrite
180 * the 4 or 8 byte pointer within.
182 * Serialising an execbuf is quite simple according to the rules of the GEM
183 * ABI. Execution within each context is ordered by the order of submission.
184 * Writes to any GEM object are in order of submission and are exclusive. Reads
185 * from a GEM object are unordered with respect to other reads, but ordered by
186 * writes. A write submitted after a read cannot occur before the read, and
187 * similarly any read submitted after a write cannot occur before the write.
188 * Writes are ordered between engines such that only one write occurs at any
189 * time (completing any reads beforehand) - using semaphores where available
190 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
191 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
192 * reads before starting, and any read (either using set-domain or pread) must
193 * flush all GPU writes before starting. (Note we only employ a barrier before,
194 * we currently rely on userspace not concurrently starting a new execution
195 * whilst reading or writing to an object. This may be an advantage or not
196 * depending on how much you trust userspace not to shoot themselves in the
197 * foot.) Serialisation may just result in the request being inserted into
198 * a DAG awaiting its turn, but most simple is to wait on the CPU until
199 * all dependencies are resolved.
201 * After all of that, is just a matter of closing the request and handing it to
202 * the hardware (well, leaving it in a queue to be executed). However, we also
203 * offer the ability for batchbuffers to be run with elevated privileges so
204 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
205 * Before any batch is given extra privileges we first must check that it
206 * contains no nefarious instructions, we check that each instruction is from
207 * our whitelist and all registers are also from an allowed list. We first
208 * copy the user's batchbuffer to a shadow (so that the user doesn't have
209 * access to it, either by the CPU or GPU as we scan it) and then parse each
210 * instruction. If everything is ok, we set a flag telling the hardware to run
211 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
214 struct i915_execbuffer {
215 struct drm_i915_private *i915; /** i915 backpointer */
216 struct drm_file *file; /** per-file lookup tables and limits */
217 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
218 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
219 struct i915_vma **vma;
222 struct intel_engine_cs *engine; /** engine to queue the request to */
223 struct intel_context *context; /* logical state for the request */
224 struct i915_gem_context *gem_context; /** caller's context */
225 struct i915_address_space *vm; /** GTT and vma for the request */
227 struct i915_request *request; /** our request to build */
228 struct i915_vma *batch; /** identity of the batch obj/vma */
230 /** actual size of execobj[] as we may extend it for the cmdparser */
231 unsigned int buffer_count;
233 /** list of vma not yet bound during reservation phase */
234 struct list_head unbound;
236 /** list of vma that have execobj.relocation_count */
237 struct list_head relocs;
240 * Track the most recently used object for relocations, as we
241 * frequently have to perform multiple relocations within the same
245 struct drm_mm_node node; /** temporary GTT binding */
246 unsigned long vaddr; /** Current kmap address */
247 unsigned long page; /** Currently mapped page index */
248 unsigned int gen; /** Cached value of INTEL_GEN */
249 bool use_64bit_reloc : 1;
252 bool needs_unfenced : 1;
254 struct i915_request *rq;
256 unsigned int rq_size;
259 u64 invalid_flags; /** Set of execobj.flags that are invalid */
260 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
262 u32 batch_start_offset; /** Location within object of batch */
263 u32 batch_len; /** Length of batch within object */
264 u32 batch_flags; /** Flags composed for emit_bb_start() */
267 * Indicate either the size of the hastable used to resolve
268 * relocation handles, or if negative that we are using a direct
269 * index into the execobj[].
272 struct hlist_head *buckets; /** ht for relocation handles */
275 #define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
278 * Used to convert any address to canonical form.
279 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
280 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
281 * addresses to be in a canonical form:
282 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
283 * canonical form [63:48] == [47]."
285 #define GEN8_HIGH_ADDRESS_BIT 47
286 static inline u64 gen8_canonical_addr(u64 address)
288 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
291 static inline u64 gen8_noncanonical_addr(u64 address)
293 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
296 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
298 return intel_engine_needs_cmd_parser(eb->engine) && eb->batch_len;
301 static int eb_create(struct i915_execbuffer *eb)
303 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
304 unsigned int size = 1 + ilog2(eb->buffer_count);
307 * Without a 1:1 association between relocation handles and
308 * the execobject[] index, we instead create a hashtable.
309 * We size it dynamically based on available memory, starting
310 * first with 1:1 assocative hash and scaling back until
311 * the allocation succeeds.
313 * Later on we use a positive lut_size to indicate we are
314 * using this hashtable, and a negative value to indicate a
320 /* While we can still reduce the allocation size, don't
321 * raise a warning and allow the allocation to fail.
322 * On the last pass though, we want to try as hard
323 * as possible to perform the allocation and warn
328 flags |= __GFP_NORETRY | __GFP_NOWARN;
330 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
341 eb->lut_size = -eb->buffer_count;
348 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
349 const struct i915_vma *vma,
352 if (vma->node.size < entry->pad_to_size)
355 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
358 if (flags & EXEC_OBJECT_PINNED &&
359 vma->node.start != entry->offset)
362 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
363 vma->node.start < BATCH_OFFSET_BIAS)
366 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
367 (vma->node.start + vma->node.size - 1) >> 32)
370 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
371 !i915_vma_is_map_and_fenceable(vma))
378 eb_pin_vma(struct i915_execbuffer *eb,
379 const struct drm_i915_gem_exec_object2 *entry,
380 struct i915_vma *vma)
382 unsigned int exec_flags = *vma->exec_flags;
386 pin_flags = vma->node.start;
388 pin_flags = entry->offset & PIN_OFFSET_MASK;
390 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
391 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT))
392 pin_flags |= PIN_GLOBAL;
394 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
397 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
398 if (unlikely(i915_vma_pin_fence(vma))) {
404 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
407 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
408 return !eb_vma_misplaced(entry, vma, exec_flags);
411 static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
413 GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
415 if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
416 __i915_vma_unpin_fence(vma);
418 __i915_vma_unpin(vma);
422 eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags)
424 if (!(*flags & __EXEC_OBJECT_HAS_PIN))
427 __eb_unreserve_vma(vma, *flags);
428 *flags &= ~__EXEC_OBJECT_RESERVED;
432 eb_validate_vma(struct i915_execbuffer *eb,
433 struct drm_i915_gem_exec_object2 *entry,
434 struct i915_vma *vma)
436 if (unlikely(entry->flags & eb->invalid_flags))
439 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
443 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
444 * any non-page-aligned or non-canonical addresses.
446 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
447 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
450 /* pad_to_size was once a reserved field, so sanitize it */
451 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
452 if (unlikely(offset_in_page(entry->pad_to_size)))
455 entry->pad_to_size = 0;
458 if (unlikely(vma->exec_flags)) {
459 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
460 entry->handle, (int)(entry - eb->exec));
465 * From drm_mm perspective address space is continuous,
466 * so from this point we're always using non-canonical
469 entry->offset = gen8_noncanonical_addr(entry->offset);
471 if (!eb->reloc_cache.has_fence) {
472 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
474 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
475 eb->reloc_cache.needs_unfenced) &&
476 i915_gem_object_is_tiled(vma->obj))
477 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
480 if (!(entry->flags & EXEC_OBJECT_PINNED))
481 entry->flags |= eb->context_flags;
487 eb_add_vma(struct i915_execbuffer *eb,
488 unsigned int i, unsigned batch_idx,
489 struct i915_vma *vma)
491 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
494 GEM_BUG_ON(i915_vma_is_closed(vma));
496 if (!(eb->args->flags & __EXEC_VALIDATED)) {
497 err = eb_validate_vma(eb, entry, vma);
502 if (eb->lut_size > 0) {
503 vma->exec_handle = entry->handle;
504 hlist_add_head(&vma->exec_node,
505 &eb->buckets[hash_32(entry->handle,
509 if (entry->relocation_count)
510 list_add_tail(&vma->reloc_link, &eb->relocs);
513 * Stash a pointer from the vma to execobj, so we can query its flags,
514 * size, alignment etc as provided by the user. Also we stash a pointer
515 * to the vma inside the execobj so that we can use a direct lookup
516 * to find the right target VMA when doing relocations.
519 eb->flags[i] = entry->flags;
520 vma->exec_flags = &eb->flags[i];
523 * SNA is doing fancy tricks with compressing batch buffers, which leads
524 * to negative relocation deltas. Usually that works out ok since the
525 * relocate address is still positive, except when the batch is placed
526 * very low in the GTT. Ensure this doesn't happen.
528 * Note that actual hangs have only been observed on gen7, but for
529 * paranoia do it everywhere.
531 if (i == batch_idx) {
532 if (entry->relocation_count &&
533 !(eb->flags[i] & EXEC_OBJECT_PINNED))
534 eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
535 if (eb->reloc_cache.has_fence)
536 eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
542 if (eb_pin_vma(eb, entry, vma)) {
543 if (entry->offset != vma->node.start) {
544 entry->offset = vma->node.start | UPDATE;
545 eb->args->flags |= __EXEC_HAS_RELOC;
548 eb_unreserve_vma(vma, vma->exec_flags);
550 list_add_tail(&vma->exec_link, &eb->unbound);
551 if (drm_mm_node_allocated(&vma->node))
552 err = i915_vma_unbind(vma);
554 vma->exec_flags = NULL;
559 static inline int use_cpu_reloc(const struct reloc_cache *cache,
560 const struct drm_i915_gem_object *obj)
562 if (!i915_gem_object_has_struct_page(obj))
565 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
568 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
571 return (cache->has_llc ||
573 obj->cache_level != I915_CACHE_NONE);
576 static int eb_reserve_vma(const struct i915_execbuffer *eb,
577 struct i915_vma *vma)
579 struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
580 unsigned int exec_flags = *vma->exec_flags;
584 pin_flags = PIN_USER | PIN_NONBLOCK;
585 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
586 pin_flags |= PIN_GLOBAL;
589 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
590 * limit address to the first 4GBs for unflagged objects.
592 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
593 pin_flags |= PIN_ZONE_4G;
595 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
596 pin_flags |= PIN_MAPPABLE;
598 if (exec_flags & EXEC_OBJECT_PINNED) {
599 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
600 pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */
601 } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) {
602 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
605 err = i915_vma_pin(vma,
606 entry->pad_to_size, entry->alignment,
611 if (entry->offset != vma->node.start) {
612 entry->offset = vma->node.start | UPDATE;
613 eb->args->flags |= __EXEC_HAS_RELOC;
616 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
617 err = i915_vma_pin_fence(vma);
624 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
627 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
628 GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags));
633 static int eb_reserve(struct i915_execbuffer *eb)
635 const unsigned int count = eb->buffer_count;
636 struct list_head last;
637 struct i915_vma *vma;
638 unsigned int i, pass;
642 * Attempt to pin all of the buffers into the GTT.
643 * This is done in 3 phases:
645 * 1a. Unbind all objects that do not match the GTT constraints for
646 * the execbuffer (fenceable, mappable, alignment etc).
647 * 1b. Increment pin count for already bound objects.
648 * 2. Bind new objects.
649 * 3. Decrement pin count.
651 * This avoid unnecessary unbinding of later objects in order to make
652 * room for the earlier objects *unless* we need to defragment.
658 list_for_each_entry(vma, &eb->unbound, exec_link) {
659 err = eb_reserve_vma(eb, vma);
666 /* Resort *all* the objects into priority order */
667 INIT_LIST_HEAD(&eb->unbound);
668 INIT_LIST_HEAD(&last);
669 for (i = 0; i < count; i++) {
670 unsigned int flags = eb->flags[i];
671 struct i915_vma *vma = eb->vma[i];
673 if (flags & EXEC_OBJECT_PINNED &&
674 flags & __EXEC_OBJECT_HAS_PIN)
677 eb_unreserve_vma(vma, &eb->flags[i]);
679 if (flags & EXEC_OBJECT_PINNED)
680 /* Pinned must have their slot */
681 list_add(&vma->exec_link, &eb->unbound);
682 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
683 /* Map require the lowest 256MiB (aperture) */
684 list_add_tail(&vma->exec_link, &eb->unbound);
685 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
686 /* Prioritise 4GiB region for restricted bo */
687 list_add(&vma->exec_link, &last);
689 list_add_tail(&vma->exec_link, &last);
691 list_splice_tail(&last, &eb->unbound);
698 /* Too fragmented, unbind everything and retry */
699 err = i915_gem_evict_vm(eb->vm);
710 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
712 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
715 return eb->buffer_count - 1;
718 static int eb_select_context(struct i915_execbuffer *eb)
720 struct i915_gem_context *ctx;
722 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
726 eb->gem_context = ctx;
729 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
731 eb->vm = &eb->i915->ggtt.vm;
734 eb->context_flags = 0;
735 if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
736 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
741 static struct i915_request *__eb_wait_for_ring(struct intel_ring *ring)
743 struct i915_request *rq;
746 * Completely unscientific finger-in-the-air estimates for suitable
747 * maximum user request size (to avoid blocking) and then backoff.
749 if (intel_ring_update_space(ring) >= PAGE_SIZE)
753 * Find a request that after waiting upon, there will be at least half
754 * the ring available. The hysteresis allows us to compete for the
755 * shared ring and should mean that we sleep less often prior to
756 * claiming our resources, but not so long that the ring completely
757 * drains before we can submit our next request.
759 list_for_each_entry(rq, &ring->request_list, ring_link) {
760 if (__intel_ring_space(rq->postfix,
761 ring->emit, ring->size) > ring->size / 2)
764 if (&rq->ring_link == &ring->request_list)
765 return NULL; /* weird, we will check again later for real */
767 return i915_request_get(rq);
770 static int eb_wait_for_ring(const struct i915_execbuffer *eb)
772 struct i915_request *rq;
776 * Apply a light amount of backpressure to prevent excessive hogs
777 * from blocking waiting for space whilst holding struct_mutex and
778 * keeping all of their resources pinned.
781 rq = __eb_wait_for_ring(eb->context->ring);
783 mutex_unlock(&eb->i915->drm.struct_mutex);
785 if (i915_request_wait(rq,
786 I915_WAIT_INTERRUPTIBLE,
787 MAX_SCHEDULE_TIMEOUT) < 0)
790 i915_request_put(rq);
792 mutex_lock(&eb->i915->drm.struct_mutex);
798 static int eb_lookup_vmas(struct i915_execbuffer *eb)
800 struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
801 struct drm_i915_gem_object *obj;
802 unsigned int i, batch;
805 if (unlikely(i915_gem_context_is_banned(eb->gem_context)))
808 INIT_LIST_HEAD(&eb->relocs);
809 INIT_LIST_HEAD(&eb->unbound);
811 batch = eb_batch_index(eb);
813 mutex_lock(&eb->gem_context->mutex);
814 if (unlikely(i915_gem_context_is_closed(eb->gem_context))) {
819 for (i = 0; i < eb->buffer_count; i++) {
820 u32 handle = eb->exec[i].handle;
821 struct i915_lut_handle *lut;
822 struct i915_vma *vma;
824 vma = radix_tree_lookup(handles_vma, handle);
828 obj = i915_gem_object_lookup(eb->file, handle);
829 if (unlikely(!obj)) {
834 vma = i915_vma_instance(obj, eb->vm, NULL);
840 lut = i915_lut_handle_alloc();
841 if (unlikely(!lut)) {
846 err = radix_tree_insert(handles_vma, handle, vma);
848 i915_lut_handle_free(lut);
852 /* transfer ref to lut */
853 if (!atomic_fetch_inc(&vma->open_count))
854 i915_vma_reopen(vma);
855 lut->handle = handle;
856 lut->ctx = eb->gem_context;
858 i915_gem_object_lock(obj);
859 list_add(&lut->obj_link, &obj->lut_list);
860 i915_gem_object_unlock(obj);
863 err = eb_add_vma(eb, i, batch, vma);
867 GEM_BUG_ON(vma != eb->vma[i]);
868 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
869 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
870 eb_vma_misplaced(&eb->exec[i], vma, eb->flags[i]));
873 mutex_unlock(&eb->gem_context->mutex);
875 eb->args->flags |= __EXEC_VALIDATED;
876 return eb_reserve(eb);
879 i915_gem_object_put(obj);
883 mutex_unlock(&eb->gem_context->mutex);
887 static struct i915_vma *
888 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
890 if (eb->lut_size < 0) {
891 if (handle >= -eb->lut_size)
893 return eb->vma[handle];
895 struct hlist_head *head;
896 struct i915_vma *vma;
898 head = &eb->buckets[hash_32(handle, eb->lut_size)];
899 hlist_for_each_entry(vma, head, exec_node) {
900 if (vma->exec_handle == handle)
907 static void eb_release_vmas(const struct i915_execbuffer *eb)
909 const unsigned int count = eb->buffer_count;
912 for (i = 0; i < count; i++) {
913 struct i915_vma *vma = eb->vma[i];
914 unsigned int flags = eb->flags[i];
919 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
920 vma->exec_flags = NULL;
923 if (flags & __EXEC_OBJECT_HAS_PIN)
924 __eb_unreserve_vma(vma, flags);
926 if (flags & __EXEC_OBJECT_HAS_REF)
931 static void eb_reset_vmas(const struct i915_execbuffer *eb)
934 if (eb->lut_size > 0)
935 memset(eb->buckets, 0,
936 sizeof(struct hlist_head) << eb->lut_size);
939 static void eb_destroy(const struct i915_execbuffer *eb)
941 GEM_BUG_ON(eb->reloc_cache.rq);
943 if (eb->lut_size > 0)
948 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
949 const struct i915_vma *target)
951 return gen8_canonical_addr((int)reloc->delta + target->node.start);
954 static void reloc_cache_init(struct reloc_cache *cache,
955 struct drm_i915_private *i915)
959 /* Must be a variable in the struct to allow GCC to unroll. */
960 cache->gen = INTEL_GEN(i915);
961 cache->has_llc = HAS_LLC(i915);
962 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
963 cache->has_fence = cache->gen < 4;
964 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
965 cache->node.allocated = false;
970 static inline void *unmask_page(unsigned long p)
972 return (void *)(uintptr_t)(p & PAGE_MASK);
975 static inline unsigned int unmask_flags(unsigned long p)
977 return p & ~PAGE_MASK;
980 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
982 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
984 struct drm_i915_private *i915 =
985 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
989 static void reloc_gpu_flush(struct reloc_cache *cache)
991 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
992 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
994 __i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);
995 i915_gem_object_unpin_map(cache->rq->batch->obj);
997 i915_gem_chipset_flush(cache->rq->i915);
999 i915_request_add(cache->rq);
1003 static void reloc_cache_reset(struct reloc_cache *cache)
1008 reloc_gpu_flush(cache);
1013 vaddr = unmask_page(cache->vaddr);
1014 if (cache->vaddr & KMAP) {
1015 if (cache->vaddr & CLFLUSH_AFTER)
1018 kunmap_atomic(vaddr);
1019 i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm);
1022 io_mapping_unmap_atomic((void __iomem *)vaddr);
1023 if (cache->node.allocated) {
1024 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1026 ggtt->vm.clear_range(&ggtt->vm,
1029 drm_mm_remove_node(&cache->node);
1031 i915_vma_unpin((struct i915_vma *)cache->node.mm);
1039 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1040 struct reloc_cache *cache,
1046 kunmap_atomic(unmask_page(cache->vaddr));
1048 unsigned int flushes;
1051 err = i915_gem_object_prepare_write(obj, &flushes);
1053 return ERR_PTR(err);
1055 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1056 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1058 cache->vaddr = flushes | KMAP;
1059 cache->node.mm = (void *)obj;
1064 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
1065 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1071 static void *reloc_iomap(struct drm_i915_gem_object *obj,
1072 struct reloc_cache *cache,
1075 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1076 unsigned long offset;
1080 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1082 struct i915_vma *vma;
1085 if (use_cpu_reloc(cache, obj))
1088 i915_gem_object_lock(obj);
1089 err = i915_gem_object_set_to_gtt_domain(obj, true);
1090 i915_gem_object_unlock(obj);
1092 return ERR_PTR(err);
1094 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1099 memset(&cache->node, 0, sizeof(cache->node));
1100 err = drm_mm_insert_node_in_range
1101 (&ggtt->vm.mm, &cache->node,
1102 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1103 0, ggtt->mappable_end,
1105 if (err) /* no inactive aperture space, use cpu reloc */
1108 err = i915_vma_put_fence(vma);
1110 i915_vma_unpin(vma);
1111 return ERR_PTR(err);
1114 cache->node.start = vma->node.start;
1115 cache->node.mm = (void *)vma;
1119 offset = cache->node.start;
1120 if (cache->node.allocated) {
1122 ggtt->vm.insert_page(&ggtt->vm,
1123 i915_gem_object_get_dma_address(obj, page),
1124 offset, I915_CACHE_NONE, 0);
1126 offset += page << PAGE_SHIFT;
1129 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1132 cache->vaddr = (unsigned long)vaddr;
1137 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1138 struct reloc_cache *cache,
1143 if (cache->page == page) {
1144 vaddr = unmask_page(cache->vaddr);
1147 if ((cache->vaddr & KMAP) == 0)
1148 vaddr = reloc_iomap(obj, cache, page);
1150 vaddr = reloc_kmap(obj, cache, page);
1156 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1158 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1159 if (flushes & CLFLUSH_BEFORE) {
1167 * Writes to the same cacheline are serialised by the CPU
1168 * (including clflush). On the write path, we only require
1169 * that it hits memory in an orderly fashion and place
1170 * mb barriers at the start and end of the relocation phase
1171 * to ensure ordering of clflush wrt to the system.
1173 if (flushes & CLFLUSH_AFTER)
1179 static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
1181 struct drm_i915_gem_object *obj = vma->obj;
1186 if (obj->cache_dirty & ~obj->cache_coherent)
1187 i915_gem_clflush_object(obj, 0);
1188 obj->write_domain = 0;
1190 err = i915_request_await_object(rq, vma->obj, true);
1192 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1194 i915_vma_unlock(vma);
1199 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1200 struct i915_vma *vma,
1203 struct reloc_cache *cache = &eb->reloc_cache;
1204 struct drm_i915_gem_object *obj;
1205 struct i915_request *rq;
1206 struct i915_vma *batch;
1210 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
1212 return PTR_ERR(obj);
1214 cmd = i915_gem_object_pin_map(obj,
1218 i915_gem_object_unpin_pages(obj);
1220 return PTR_ERR(cmd);
1222 batch = i915_vma_instance(obj, vma->vm, NULL);
1223 if (IS_ERR(batch)) {
1224 err = PTR_ERR(batch);
1228 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1232 rq = i915_request_create(eb->context);
1238 err = reloc_move_to_gpu(rq, vma);
1242 err = eb->engine->emit_bb_start(rq,
1243 batch->node.start, PAGE_SIZE,
1244 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1248 i915_vma_lock(batch);
1249 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
1250 err = i915_vma_move_to_active(batch, rq, 0);
1251 i915_vma_unlock(batch);
1256 i915_vma_unpin(batch);
1259 cache->rq_cmd = cmd;
1262 /* Return with batch mapping (cmd) still pinned */
1266 i915_request_skip(rq, err);
1268 i915_request_add(rq);
1270 i915_vma_unpin(batch);
1272 i915_gem_object_unpin_map(obj);
1276 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1277 struct i915_vma *vma,
1280 struct reloc_cache *cache = &eb->reloc_cache;
1283 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1284 reloc_gpu_flush(cache);
1286 if (unlikely(!cache->rq)) {
1289 /* If we need to copy for the cmdparser, we will stall anyway */
1290 if (eb_use_cmdparser(eb))
1291 return ERR_PTR(-EWOULDBLOCK);
1293 if (!intel_engine_can_store_dword(eb->engine))
1294 return ERR_PTR(-ENODEV);
1296 err = __reloc_gpu_alloc(eb, vma, len);
1298 return ERR_PTR(err);
1301 cmd = cache->rq_cmd + cache->rq_size;
1302 cache->rq_size += len;
1308 relocate_entry(struct i915_vma *vma,
1309 const struct drm_i915_gem_relocation_entry *reloc,
1310 struct i915_execbuffer *eb,
1311 const struct i915_vma *target)
1313 u64 offset = reloc->offset;
1314 u64 target_offset = relocation_target(reloc, target);
1315 bool wide = eb->reloc_cache.use_64bit_reloc;
1318 if (!eb->reloc_cache.vaddr &&
1319 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1320 !reservation_object_test_signaled_rcu(vma->resv, true))) {
1321 const unsigned int gen = eb->reloc_cache.gen;
1327 len = offset & 7 ? 8 : 5;
1333 batch = reloc_gpu(eb, vma, len);
1337 addr = gen8_canonical_addr(vma->node.start + offset);
1340 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1341 *batch++ = lower_32_bits(addr);
1342 *batch++ = upper_32_bits(addr);
1343 *batch++ = lower_32_bits(target_offset);
1345 addr = gen8_canonical_addr(addr + 4);
1347 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1348 *batch++ = lower_32_bits(addr);
1349 *batch++ = upper_32_bits(addr);
1350 *batch++ = upper_32_bits(target_offset);
1352 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1353 *batch++ = lower_32_bits(addr);
1354 *batch++ = upper_32_bits(addr);
1355 *batch++ = lower_32_bits(target_offset);
1356 *batch++ = upper_32_bits(target_offset);
1358 } else if (gen >= 6) {
1359 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1362 *batch++ = target_offset;
1363 } else if (gen >= 4) {
1364 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1367 *batch++ = target_offset;
1369 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1371 *batch++ = target_offset;
1378 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1380 return PTR_ERR(vaddr);
1382 clflush_write32(vaddr + offset_in_page(offset),
1383 lower_32_bits(target_offset),
1384 eb->reloc_cache.vaddr);
1387 offset += sizeof(u32);
1388 target_offset >>= 32;
1394 return target->node.start | UPDATE;
1398 eb_relocate_entry(struct i915_execbuffer *eb,
1399 struct i915_vma *vma,
1400 const struct drm_i915_gem_relocation_entry *reloc)
1402 struct i915_vma *target;
1405 /* we've already hold a reference to all valid objects */
1406 target = eb_get_vma(eb, reloc->target_handle);
1407 if (unlikely(!target))
1410 /* Validate that the target is in a valid r/w GPU domain */
1411 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1412 DRM_DEBUG("reloc with multiple write domains: "
1413 "target %d offset %d "
1414 "read %08x write %08x",
1415 reloc->target_handle,
1416 (int) reloc->offset,
1417 reloc->read_domains,
1418 reloc->write_domain);
1421 if (unlikely((reloc->write_domain | reloc->read_domains)
1422 & ~I915_GEM_GPU_DOMAINS)) {
1423 DRM_DEBUG("reloc with read/write non-GPU domains: "
1424 "target %d offset %d "
1425 "read %08x write %08x",
1426 reloc->target_handle,
1427 (int) reloc->offset,
1428 reloc->read_domains,
1429 reloc->write_domain);
1433 if (reloc->write_domain) {
1434 *target->exec_flags |= EXEC_OBJECT_WRITE;
1437 * Sandybridge PPGTT errata: We need a global gtt mapping
1438 * for MI and pipe_control writes because the gpu doesn't
1439 * properly redirect them through the ppgtt for non_secure
1442 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1443 IS_GEN(eb->i915, 6)) {
1444 err = i915_vma_bind(target, target->obj->cache_level,
1447 "Unexpected failure to bind target VMA!"))
1453 * If the relocation already has the right value in it, no
1454 * more work needs to be done.
1456 if (!DBG_FORCE_RELOC &&
1457 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1460 /* Check that the relocation address is valid... */
1461 if (unlikely(reloc->offset >
1462 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1463 DRM_DEBUG("Relocation beyond object bounds: "
1464 "target %d offset %d size %d.\n",
1465 reloc->target_handle,
1470 if (unlikely(reloc->offset & 3)) {
1471 DRM_DEBUG("Relocation not 4-byte aligned: "
1472 "target %d offset %d.\n",
1473 reloc->target_handle,
1474 (int)reloc->offset);
1479 * If we write into the object, we need to force the synchronisation
1480 * barrier, either with an asynchronous clflush or if we executed the
1481 * patching using the GPU (though that should be serialised by the
1482 * timeline). To be completely sure, and since we are required to
1483 * do relocations we are already stalling, disable the user's opt
1484 * out of our synchronisation.
1486 *vma->exec_flags &= ~EXEC_OBJECT_ASYNC;
1488 /* and update the user's relocation entry */
1489 return relocate_entry(vma, reloc, eb, target);
1492 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1494 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1495 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1496 struct drm_i915_gem_relocation_entry __user *urelocs;
1497 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1498 unsigned int remain;
1500 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1501 remain = entry->relocation_count;
1502 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1506 * We must check that the entire relocation array is safe
1507 * to read. However, if the array is not writable the user loses
1508 * the updated relocation values.
1510 if (unlikely(!access_ok(urelocs, remain*sizeof(*urelocs))))
1514 struct drm_i915_gem_relocation_entry *r = stack;
1515 unsigned int count =
1516 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1517 unsigned int copied;
1520 * This is the fast path and we cannot handle a pagefault
1521 * whilst holding the struct mutex lest the user pass in the
1522 * relocations contained within a mmaped bo. For in such a case
1523 * we, the page fault handler would call i915_gem_fault() and
1524 * we would try to acquire the struct mutex again. Obviously
1525 * this is bad and so lockdep complains vehemently.
1527 pagefault_disable();
1528 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1530 if (unlikely(copied)) {
1537 u64 offset = eb_relocate_entry(eb, vma, r);
1539 if (likely(offset == 0)) {
1540 } else if ((s64)offset < 0) {
1541 remain = (int)offset;
1545 * Note that reporting an error now
1546 * leaves everything in an inconsistent
1547 * state as we have *already* changed
1548 * the relocation value inside the
1549 * object. As we have not changed the
1550 * reloc.presumed_offset or will not
1551 * change the execobject.offset, on the
1552 * call we may not rewrite the value
1553 * inside the object, leaving it
1554 * dangling and causing a GPU hang. Unless
1555 * userspace dynamically rebuilds the
1556 * relocations on each execbuf rather than
1557 * presume a static tree.
1559 * We did previously check if the relocations
1560 * were writable (access_ok), an error now
1561 * would be a strange race with mprotect,
1562 * having already demonstrated that we
1563 * can read from this userspace address.
1565 offset = gen8_canonical_addr(offset & ~UPDATE);
1566 if (unlikely(__put_user(offset, &urelocs[r-stack].presumed_offset))) {
1571 } while (r++, --count);
1572 urelocs += ARRAY_SIZE(stack);
1575 reloc_cache_reset(&eb->reloc_cache);
1580 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1582 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1583 struct drm_i915_gem_relocation_entry *relocs =
1584 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1588 for (i = 0; i < entry->relocation_count; i++) {
1589 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1591 if ((s64)offset < 0) {
1598 reloc_cache_reset(&eb->reloc_cache);
1602 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1604 const char __user *addr, *end;
1606 char __maybe_unused c;
1608 size = entry->relocation_count;
1612 if (size > N_RELOC(ULONG_MAX))
1615 addr = u64_to_user_ptr(entry->relocs_ptr);
1616 size *= sizeof(struct drm_i915_gem_relocation_entry);
1617 if (!access_ok(addr, size))
1621 for (; addr < end; addr += PAGE_SIZE) {
1622 int err = __get_user(c, addr);
1626 return __get_user(c, end - 1);
1629 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1631 struct drm_i915_gem_relocation_entry *relocs;
1632 const unsigned int count = eb->buffer_count;
1636 for (i = 0; i < count; i++) {
1637 const unsigned int nreloc = eb->exec[i].relocation_count;
1638 struct drm_i915_gem_relocation_entry __user *urelocs;
1640 unsigned long copied;
1645 err = check_relocations(&eb->exec[i]);
1649 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1650 size = nreloc * sizeof(*relocs);
1652 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1658 /* copy_from_user is limited to < 4GiB */
1662 min_t(u64, BIT_ULL(31), size - copied);
1664 if (__copy_from_user((char *)relocs + copied,
1665 (char __user *)urelocs + copied,
1670 } while (copied < size);
1673 * As we do not update the known relocation offsets after
1674 * relocating (due to the complexities in lock handling),
1675 * we need to mark them as invalid now so that we force the
1676 * relocation processing next time. Just in case the target
1677 * object is evicted and then rebound into its old
1678 * presumed_offset before the next execbuffer - if that
1679 * happened we would make the mistake of assuming that the
1680 * relocations were valid.
1682 if (!user_access_begin(urelocs, size))
1685 for (copied = 0; copied < nreloc; copied++)
1687 &urelocs[copied].presumed_offset,
1691 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1703 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1704 if (eb->exec[i].relocation_count)
1710 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1712 const unsigned int count = eb->buffer_count;
1715 if (unlikely(i915_modparams.prefault_disable))
1718 for (i = 0; i < count; i++) {
1721 err = check_relocations(&eb->exec[i]);
1729 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1731 struct drm_device *dev = &eb->i915->drm;
1732 bool have_copy = false;
1733 struct i915_vma *vma;
1737 if (signal_pending(current)) {
1742 /* We may process another execbuffer during the unlock... */
1744 mutex_unlock(&dev->struct_mutex);
1747 * We take 3 passes through the slowpatch.
1749 * 1 - we try to just prefault all the user relocation entries and
1750 * then attempt to reuse the atomic pagefault disabled fast path again.
1752 * 2 - we copy the user entries to a local buffer here outside of the
1753 * local and allow ourselves to wait upon any rendering before
1756 * 3 - we already have a local copy of the relocation entries, but
1757 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1760 err = eb_prefault_relocations(eb);
1761 } else if (!have_copy) {
1762 err = eb_copy_relocations(eb);
1763 have_copy = err == 0;
1769 mutex_lock(&dev->struct_mutex);
1773 /* A frequent cause for EAGAIN are currently unavailable client pages */
1774 flush_workqueue(eb->i915->mm.userptr_wq);
1776 err = i915_mutex_lock_interruptible(dev);
1778 mutex_lock(&dev->struct_mutex);
1782 /* reacquire the objects */
1783 err = eb_lookup_vmas(eb);
1787 GEM_BUG_ON(!eb->batch);
1789 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1791 pagefault_disable();
1792 err = eb_relocate_vma(eb, vma);
1797 err = eb_relocate_vma_slow(eb, vma);
1804 * Leave the user relocations as are, this is the painfully slow path,
1805 * and we want to avoid the complication of dropping the lock whilst
1806 * having buffers reserved in the aperture and so causing spurious
1807 * ENOSPC for random operations.
1816 const unsigned int count = eb->buffer_count;
1819 for (i = 0; i < count; i++) {
1820 const struct drm_i915_gem_exec_object2 *entry =
1822 struct drm_i915_gem_relocation_entry *relocs;
1824 if (!entry->relocation_count)
1827 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1835 static int eb_relocate(struct i915_execbuffer *eb)
1837 if (eb_lookup_vmas(eb))
1840 /* The objects are in their final locations, apply the relocations. */
1841 if (eb->args->flags & __EXEC_HAS_RELOC) {
1842 struct i915_vma *vma;
1844 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1845 if (eb_relocate_vma(eb, vma))
1853 return eb_relocate_slow(eb);
1856 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1858 const unsigned int count = eb->buffer_count;
1859 struct ww_acquire_ctx acquire;
1863 ww_acquire_init(&acquire, &reservation_ww_class);
1865 for (i = 0; i < count; i++) {
1866 struct i915_vma *vma = eb->vma[i];
1868 err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire);
1872 GEM_BUG_ON(err == -EALREADY); /* No duplicate vma */
1874 if (err == -EDEADLK) {
1879 ww_mutex_unlock(&eb->vma[j]->resv->lock);
1881 swap(eb->flags[i], eb->flags[j]);
1882 swap(eb->vma[i], eb->vma[j]);
1883 eb->vma[i]->exec_flags = &eb->flags[i];
1885 GEM_BUG_ON(vma != eb->vma[0]);
1886 vma->exec_flags = &eb->flags[0];
1888 err = ww_mutex_lock_slow_interruptible(&vma->resv->lock,
1894 ww_acquire_done(&acquire);
1897 unsigned int flags = eb->flags[i];
1898 struct i915_vma *vma = eb->vma[i];
1899 struct drm_i915_gem_object *obj = vma->obj;
1901 assert_vma_held(vma);
1903 if (flags & EXEC_OBJECT_CAPTURE) {
1904 struct i915_capture_list *capture;
1906 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1908 capture->next = eb->request->capture_list;
1910 eb->request->capture_list = capture;
1915 * If the GPU is not _reading_ through the CPU cache, we need
1916 * to make sure that any writes (both previous GPU writes from
1917 * before a change in snooping levels and normal CPU writes)
1918 * caught in that cache are flushed to main memory.
1921 * obj->cache_dirty &&
1922 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1923 * but gcc's optimiser doesn't handle that as well and emits
1924 * two jumps instead of one. Maybe one day...
1926 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1927 if (i915_gem_clflush_object(obj, 0))
1928 flags &= ~EXEC_OBJECT_ASYNC;
1931 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
1932 err = i915_request_await_object
1933 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1937 err = i915_vma_move_to_active(vma, eb->request, flags);
1939 i915_vma_unlock(vma);
1941 __eb_unreserve_vma(vma, flags);
1942 vma->exec_flags = NULL;
1944 if (unlikely(flags & __EXEC_OBJECT_HAS_REF))
1947 ww_acquire_fini(&acquire);
1954 /* Unconditionally flush any chipset caches (for streaming writes). */
1955 i915_gem_chipset_flush(eb->i915);
1959 i915_request_skip(eb->request, err);
1963 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1965 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1968 /* Kernel clipping was a DRI1 misfeature */
1969 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1970 if (exec->num_cliprects || exec->cliprects_ptr)
1974 if (exec->DR4 == 0xffffffff) {
1975 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1978 if (exec->DR1 || exec->DR4)
1981 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1987 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
1992 if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) {
1993 DRM_DEBUG("sol reset is gen7/rcs only\n");
1997 cs = intel_ring_begin(rq, 4 * 2 + 2);
2001 *cs++ = MI_LOAD_REGISTER_IMM(4);
2002 for (i = 0; i < 4; i++) {
2003 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2007 intel_ring_advance(rq, cs);
2012 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
2014 struct drm_i915_gem_object *shadow_batch_obj;
2015 struct i915_vma *vma;
2018 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
2019 PAGE_ALIGN(eb->batch_len));
2020 if (IS_ERR(shadow_batch_obj))
2021 return ERR_CAST(shadow_batch_obj);
2023 err = intel_engine_cmd_parser(eb->engine,
2026 eb->batch_start_offset,
2030 if (err == -EACCES) /* unhandled chained batch */
2037 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
2041 eb->vma[eb->buffer_count] = i915_vma_get(vma);
2042 eb->flags[eb->buffer_count] =
2043 __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
2044 vma->exec_flags = &eb->flags[eb->buffer_count];
2048 i915_gem_object_unpin_pages(shadow_batch_obj);
2053 add_to_client(struct i915_request *rq, struct drm_file *file)
2055 rq->file_priv = file->driver_priv;
2056 list_add_tail(&rq->client_link, &rq->file_priv->mm.request_list);
2059 static int eb_submit(struct i915_execbuffer *eb)
2063 err = eb_move_to_gpu(eb);
2067 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2068 err = i915_reset_gen7_sol_offsets(eb->request);
2074 * After we completed waiting for other engines (using HW semaphores)
2075 * then we can signal that this request/batch is ready to run. This
2076 * allows us to determine if the batch is still waiting on the GPU
2077 * or actually running by checking the breadcrumb.
2079 if (eb->engine->emit_init_breadcrumb) {
2080 err = eb->engine->emit_init_breadcrumb(eb->request);
2085 err = eb->engine->emit_bb_start(eb->request,
2086 eb->batch->node.start +
2087 eb->batch_start_offset,
2097 * Find one BSD ring to dispatch the corresponding BSD command.
2098 * The engine index is returned.
2101 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2102 struct drm_file *file)
2104 struct drm_i915_file_private *file_priv = file->driver_priv;
2106 /* Check whether the file_priv has already selected one ring. */
2107 if ((int)file_priv->bsd_engine < 0)
2108 file_priv->bsd_engine = atomic_fetch_xor(1,
2109 &dev_priv->mm.bsd_engine_dispatch_index);
2111 return file_priv->bsd_engine;
2114 static const enum intel_engine_id user_ring_map[] = {
2115 [I915_EXEC_DEFAULT] = RCS0,
2116 [I915_EXEC_RENDER] = RCS0,
2117 [I915_EXEC_BLT] = BCS0,
2118 [I915_EXEC_BSD] = VCS0,
2119 [I915_EXEC_VEBOX] = VECS0
2122 static int eb_pin_context(struct i915_execbuffer *eb, struct intel_context *ce)
2127 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2128 * EIO if the GPU is already wedged.
2130 err = i915_terminally_wedged(eb->i915);
2135 * Pinning the contexts may generate requests in order to acquire
2136 * GGTT space, so do this first before we reserve a seqno for
2139 err = intel_context_pin(ce);
2143 eb->engine = ce->engine;
2148 static void eb_unpin_context(struct i915_execbuffer *eb)
2150 intel_context_unpin(eb->context);
2154 eb_select_legacy_ring(struct i915_execbuffer *eb,
2155 struct drm_file *file,
2156 struct drm_i915_gem_execbuffer2 *args)
2158 struct drm_i915_private *i915 = eb->i915;
2159 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2161 if (user_ring_id != I915_EXEC_BSD &&
2162 (args->flags & I915_EXEC_BSD_MASK)) {
2163 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2164 "bsd dispatch flags: %d\n", (int)(args->flags));
2168 if (user_ring_id == I915_EXEC_BSD && HAS_ENGINE(i915, VCS1)) {
2169 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2171 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2172 bsd_idx = gen8_dispatch_bsd_engine(i915, file);
2173 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2174 bsd_idx <= I915_EXEC_BSD_RING2) {
2175 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2178 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2183 return _VCS(bsd_idx);
2186 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2187 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2191 return user_ring_map[user_ring_id];
2195 eb_select_engine(struct i915_execbuffer *eb,
2196 struct drm_file *file,
2197 struct drm_i915_gem_execbuffer2 *args)
2199 struct intel_context *ce;
2203 if (i915_gem_context_user_engines(eb->gem_context))
2204 idx = args->flags & I915_EXEC_RING_MASK;
2206 idx = eb_select_legacy_ring(eb, file, args);
2208 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2212 err = eb_pin_context(eb, ce);
2213 intel_context_put(ce);
2219 __free_fence_array(struct drm_syncobj **fences, unsigned int n)
2222 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2226 static struct drm_syncobj **
2227 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2228 struct drm_file *file)
2230 const unsigned long nfences = args->num_cliprects;
2231 struct drm_i915_gem_exec_fence __user *user;
2232 struct drm_syncobj **fences;
2236 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2239 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2240 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2241 if (nfences > min_t(unsigned long,
2242 ULONG_MAX / sizeof(*user),
2243 SIZE_MAX / sizeof(*fences)))
2244 return ERR_PTR(-EINVAL);
2246 user = u64_to_user_ptr(args->cliprects_ptr);
2247 if (!access_ok(user, nfences * sizeof(*user)))
2248 return ERR_PTR(-EFAULT);
2250 fences = kvmalloc_array(nfences, sizeof(*fences),
2251 __GFP_NOWARN | GFP_KERNEL);
2253 return ERR_PTR(-ENOMEM);
2255 for (n = 0; n < nfences; n++) {
2256 struct drm_i915_gem_exec_fence fence;
2257 struct drm_syncobj *syncobj;
2259 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2264 if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
2269 syncobj = drm_syncobj_find(file, fence.handle);
2271 DRM_DEBUG("Invalid syncobj handle provided\n");
2276 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2277 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2279 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2285 __free_fence_array(fences, n);
2286 return ERR_PTR(err);
2290 put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2291 struct drm_syncobj **fences)
2294 __free_fence_array(fences, args->num_cliprects);
2298 await_fence_array(struct i915_execbuffer *eb,
2299 struct drm_syncobj **fences)
2301 const unsigned int nfences = eb->args->num_cliprects;
2305 for (n = 0; n < nfences; n++) {
2306 struct drm_syncobj *syncobj;
2307 struct dma_fence *fence;
2310 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2311 if (!(flags & I915_EXEC_FENCE_WAIT))
2314 fence = drm_syncobj_fence_get(syncobj);
2318 err = i915_request_await_dma_fence(eb->request, fence);
2319 dma_fence_put(fence);
2328 signal_fence_array(struct i915_execbuffer *eb,
2329 struct drm_syncobj **fences)
2331 const unsigned int nfences = eb->args->num_cliprects;
2332 struct dma_fence * const fence = &eb->request->fence;
2335 for (n = 0; n < nfences; n++) {
2336 struct drm_syncobj *syncobj;
2339 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2340 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2343 drm_syncobj_replace_fence(syncobj, fence);
2348 i915_gem_do_execbuffer(struct drm_device *dev,
2349 struct drm_file *file,
2350 struct drm_i915_gem_execbuffer2 *args,
2351 struct drm_i915_gem_exec_object2 *exec,
2352 struct drm_syncobj **fences)
2354 struct i915_execbuffer eb;
2355 struct dma_fence *in_fence = NULL;
2356 struct dma_fence *exec_fence = NULL;
2357 struct sync_file *out_fence = NULL;
2358 int out_fence_fd = -1;
2361 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
2362 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2363 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2365 eb.i915 = to_i915(dev);
2368 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2369 args->flags |= __EXEC_HAS_RELOC;
2372 eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1);
2374 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
2376 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2377 reloc_cache_init(&eb.reloc_cache, eb.i915);
2379 eb.buffer_count = args->buffer_count;
2380 eb.batch_start_offset = args->batch_start_offset;
2381 eb.batch_len = args->batch_len;
2384 if (args->flags & I915_EXEC_SECURE) {
2385 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2388 eb.batch_flags |= I915_DISPATCH_SECURE;
2390 if (args->flags & I915_EXEC_IS_PINNED)
2391 eb.batch_flags |= I915_DISPATCH_PINNED;
2393 if (args->flags & I915_EXEC_FENCE_IN) {
2394 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2399 if (args->flags & I915_EXEC_FENCE_SUBMIT) {
2405 exec_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2412 if (args->flags & I915_EXEC_FENCE_OUT) {
2413 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2414 if (out_fence_fd < 0) {
2416 goto err_exec_fence;
2420 err = eb_create(&eb);
2424 GEM_BUG_ON(!eb.lut_size);
2426 err = eb_select_context(&eb);
2431 * Take a local wakeref for preparing to dispatch the execbuf as
2432 * we expect to access the hardware fairly frequently in the
2433 * process. Upon first dispatch, we acquire another prolonged
2434 * wakeref that we hold until the GPU has been idle for at least
2437 intel_gt_pm_get(eb.i915);
2439 err = i915_mutex_lock_interruptible(dev);
2443 err = eb_select_engine(&eb, file, args);
2447 err = eb_wait_for_ring(&eb); /* may temporarily drop struct_mutex */
2451 err = eb_relocate(&eb);
2454 * If the user expects the execobject.offset and
2455 * reloc.presumed_offset to be an exact match,
2456 * as for using NO_RELOC, then we cannot update
2457 * the execobject.offset until we have completed
2460 args->flags &= ~__EXEC_HAS_RELOC;
2464 if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) {
2465 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2469 if (eb.batch_start_offset > eb.batch->size ||
2470 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2471 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2476 if (eb_use_cmdparser(&eb)) {
2477 struct i915_vma *vma;
2479 vma = eb_parse(&eb, drm_is_current_master(file));
2487 * Batch parsed and accepted:
2489 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2490 * bit from MI_BATCH_BUFFER_START commands issued in
2491 * the dispatch_execbuffer implementations. We
2492 * specifically don't want that set on batches the
2493 * command parser has accepted.
2495 eb.batch_flags |= I915_DISPATCH_SECURE;
2496 eb.batch_start_offset = 0;
2501 if (eb.batch_len == 0)
2502 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2505 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2506 * batch" bit. Hence we need to pin secure batches into the global gtt.
2507 * hsw should have this fixed, but bdw mucks it up again. */
2508 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2509 struct i915_vma *vma;
2512 * So on first glance it looks freaky that we pin the batch here
2513 * outside of the reservation loop. But:
2514 * - The batch is already pinned into the relevant ppgtt, so we
2515 * already have the backing storage fully allocated.
2516 * - No other BO uses the global gtt (well contexts, but meh),
2517 * so we don't really have issues with multiple objects not
2518 * fitting due to fragmentation.
2519 * So this is actually safe.
2521 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2530 /* All GPU relocation batches must be submitted prior to the user rq */
2531 GEM_BUG_ON(eb.reloc_cache.rq);
2533 /* Allocate a request for this batch buffer nice and early. */
2534 eb.request = i915_request_create(eb.context);
2535 if (IS_ERR(eb.request)) {
2536 err = PTR_ERR(eb.request);
2537 goto err_batch_unpin;
2541 err = i915_request_await_dma_fence(eb.request, in_fence);
2547 err = i915_request_await_execution(eb.request, exec_fence,
2548 eb.engine->bond_execute);
2554 err = await_fence_array(&eb, fences);
2559 if (out_fence_fd != -1) {
2560 out_fence = sync_file_create(&eb.request->fence);
2568 * Whilst this request exists, batch_obj will be on the
2569 * active_list, and so will hold the active reference. Only when this
2570 * request is retired will the the batch_obj be moved onto the
2571 * inactive_list and lose its active reference. Hence we do not need
2572 * to explicitly hold another reference here.
2574 eb.request->batch = eb.batch;
2576 trace_i915_request_queue(eb.request, eb.batch_flags);
2577 err = eb_submit(&eb);
2579 add_to_client(eb.request, file);
2580 i915_request_add(eb.request);
2583 signal_fence_array(&eb, fences);
2587 fd_install(out_fence_fd, out_fence->file);
2588 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
2589 args->rsvd2 |= (u64)out_fence_fd << 32;
2592 fput(out_fence->file);
2597 if (eb.batch_flags & I915_DISPATCH_SECURE)
2598 i915_vma_unpin(eb.batch);
2601 eb_release_vmas(&eb);
2603 eb_unpin_context(&eb);
2605 mutex_unlock(&dev->struct_mutex);
2607 intel_gt_pm_put(eb.i915);
2608 i915_gem_context_put(eb.gem_context);
2612 if (out_fence_fd != -1)
2613 put_unused_fd(out_fence_fd);
2615 dma_fence_put(exec_fence);
2617 dma_fence_put(in_fence);
2621 static size_t eb_element_size(void)
2623 return (sizeof(struct drm_i915_gem_exec_object2) +
2624 sizeof(struct i915_vma *) +
2625 sizeof(unsigned int));
2628 static bool check_buffer_count(size_t count)
2630 const size_t sz = eb_element_size();
2633 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
2634 * array size (see eb_create()). Otherwise, we can accept an array as
2635 * large as can be addressed (though use large arrays at your peril)!
2638 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
2642 * Legacy execbuffer just creates an exec2 list from the original exec object
2643 * list array and passes it to the real function.
2646 i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2647 struct drm_file *file)
2649 struct drm_i915_gem_execbuffer *args = data;
2650 struct drm_i915_gem_execbuffer2 exec2;
2651 struct drm_i915_gem_exec_object *exec_list = NULL;
2652 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2653 const size_t count = args->buffer_count;
2657 if (!check_buffer_count(count)) {
2658 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2662 exec2.buffers_ptr = args->buffers_ptr;
2663 exec2.buffer_count = args->buffer_count;
2664 exec2.batch_start_offset = args->batch_start_offset;
2665 exec2.batch_len = args->batch_len;
2666 exec2.DR1 = args->DR1;
2667 exec2.DR4 = args->DR4;
2668 exec2.num_cliprects = args->num_cliprects;
2669 exec2.cliprects_ptr = args->cliprects_ptr;
2670 exec2.flags = I915_EXEC_RENDER;
2671 i915_execbuffer2_set_context_id(exec2, 0);
2673 if (!i915_gem_check_execbuffer(&exec2))
2676 /* Copy in the exec list from userland */
2677 exec_list = kvmalloc_array(count, sizeof(*exec_list),
2678 __GFP_NOWARN | GFP_KERNEL);
2679 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2680 __GFP_NOWARN | GFP_KERNEL);
2681 if (exec_list == NULL || exec2_list == NULL) {
2682 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2683 args->buffer_count);
2688 err = copy_from_user(exec_list,
2689 u64_to_user_ptr(args->buffers_ptr),
2690 sizeof(*exec_list) * count);
2692 DRM_DEBUG("copy %d exec entries failed %d\n",
2693 args->buffer_count, err);
2699 for (i = 0; i < args->buffer_count; i++) {
2700 exec2_list[i].handle = exec_list[i].handle;
2701 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2702 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2703 exec2_list[i].alignment = exec_list[i].alignment;
2704 exec2_list[i].offset = exec_list[i].offset;
2705 if (INTEL_GEN(to_i915(dev)) < 4)
2706 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2708 exec2_list[i].flags = 0;
2711 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2712 if (exec2.flags & __EXEC_HAS_RELOC) {
2713 struct drm_i915_gem_exec_object __user *user_exec_list =
2714 u64_to_user_ptr(args->buffers_ptr);
2716 /* Copy the new buffer offsets back to the user's exec list. */
2717 for (i = 0; i < args->buffer_count; i++) {
2718 if (!(exec2_list[i].offset & UPDATE))
2721 exec2_list[i].offset =
2722 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2723 exec2_list[i].offset &= PIN_OFFSET_MASK;
2724 if (__copy_to_user(&user_exec_list[i].offset,
2725 &exec2_list[i].offset,
2726 sizeof(user_exec_list[i].offset)))
2737 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2738 struct drm_file *file)
2740 struct drm_i915_gem_execbuffer2 *args = data;
2741 struct drm_i915_gem_exec_object2 *exec2_list;
2742 struct drm_syncobj **fences = NULL;
2743 const size_t count = args->buffer_count;
2746 if (!check_buffer_count(count)) {
2747 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2751 if (!i915_gem_check_execbuffer(args))
2754 /* Allocate an extra slot for use by the command parser */
2755 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2756 __GFP_NOWARN | GFP_KERNEL);
2757 if (exec2_list == NULL) {
2758 DRM_DEBUG("Failed to allocate exec list for %zd buffers\n",
2762 if (copy_from_user(exec2_list,
2763 u64_to_user_ptr(args->buffers_ptr),
2764 sizeof(*exec2_list) * count)) {
2765 DRM_DEBUG("copy %zd exec entries failed\n", count);
2770 if (args->flags & I915_EXEC_FENCE_ARRAY) {
2771 fences = get_fence_array(args, file);
2772 if (IS_ERR(fences)) {
2774 return PTR_ERR(fences);
2778 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
2781 * Now that we have begun execution of the batchbuffer, we ignore
2782 * any new error after this point. Also given that we have already
2783 * updated the associated relocations, we try to write out the current
2784 * object locations irrespective of any error.
2786 if (args->flags & __EXEC_HAS_RELOC) {
2787 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2788 u64_to_user_ptr(args->buffers_ptr);
2791 /* Copy the new buffer offsets back to the user's exec list. */
2793 * Note: count * sizeof(*user_exec_list) does not overflow,
2794 * because we checked 'count' in check_buffer_count().
2796 * And this range already got effectively checked earlier
2797 * when we did the "copy_from_user()" above.
2799 if (!user_access_begin(user_exec_list, count * sizeof(*user_exec_list)))
2802 for (i = 0; i < args->buffer_count; i++) {
2803 if (!(exec2_list[i].offset & UPDATE))
2806 exec2_list[i].offset =
2807 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2808 unsafe_put_user(exec2_list[i].offset,
2809 &user_exec_list[i].offset,
2817 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
2818 put_fence_array(args, fences);