2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008,2010 Intel Corporation
7 #include <linux/intel-iommu.h>
8 #include <linux/dma-resv.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_syncobj.h>
14 #include "display/intel_frontbuffer.h"
16 #include "gem/i915_gem_ioctls.h"
17 #include "gt/intel_context.h"
18 #include "gt/intel_gpu_commands.h"
19 #include "gt/intel_gt.h"
20 #include "gt/intel_gt_buffer_pool.h"
21 #include "gt/intel_gt_pm.h"
22 #include "gt/intel_ring.h"
24 #include "pxp/intel_pxp.h"
26 #include "i915_cmd_parser.h"
28 #include "i915_file_private.h"
29 #include "i915_gem_clflush.h"
30 #include "i915_gem_context.h"
31 #include "i915_gem_evict.h"
32 #include "i915_gem_ioctls.h"
33 #include "i915_trace.h"
34 #include "i915_user_extensions.h"
40 /** This vma's place in the execbuf reservation list */
41 struct drm_i915_gem_exec_object2 *exec;
42 struct list_head bind_link;
43 struct list_head reloc_link;
45 struct hlist_node node;
53 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
56 /* __EXEC_OBJECT_NO_RESERVE is BIT(31), defined in i915_vma.h */
57 #define __EXEC_OBJECT_HAS_PIN BIT(30)
58 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
59 #define __EXEC_OBJECT_USERPTR_INIT BIT(28)
60 #define __EXEC_OBJECT_NEEDS_MAP BIT(27)
61 #define __EXEC_OBJECT_NEEDS_BIAS BIT(26)
62 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 26) /* all of the above + */
63 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
65 #define __EXEC_HAS_RELOC BIT(31)
66 #define __EXEC_ENGINE_PINNED BIT(30)
67 #define __EXEC_USERPTR_USED BIT(29)
68 #define __EXEC_INTERNAL_FLAGS (~0u << 29)
69 #define UPDATE PIN_OFFSET_FIXED
71 #define BATCH_OFFSET_BIAS (256*1024)
73 #define __I915_EXEC_ILLEGAL_FLAGS \
74 (__I915_EXEC_UNKNOWN_FLAGS | \
75 I915_EXEC_CONSTANTS_MASK | \
76 I915_EXEC_RESOURCE_STREAMER)
78 /* Catch emission of unexpected errors for CI! */
79 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
82 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
88 * DOC: User command execution
90 * Userspace submits commands to be executed on the GPU as an instruction
91 * stream within a GEM object we call a batchbuffer. This instructions may
92 * refer to other GEM objects containing auxiliary state such as kernels,
93 * samplers, render targets and even secondary batchbuffers. Userspace does
94 * not know where in the GPU memory these objects reside and so before the
95 * batchbuffer is passed to the GPU for execution, those addresses in the
96 * batchbuffer and auxiliary objects are updated. This is known as relocation,
97 * or patching. To try and avoid having to relocate each object on the next
98 * execution, userspace is told the location of those objects in this pass,
99 * but this remains just a hint as the kernel may choose a new location for
100 * any object in the future.
102 * At the level of talking to the hardware, submitting a batchbuffer for the
103 * GPU to execute is to add content to a buffer from which the HW
104 * command streamer is reading.
106 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
107 * Execlists, this command is not placed on the same buffer as the
110 * 2. Add a command to invalidate caches to the buffer.
112 * 3. Add a batchbuffer start command to the buffer; the start command is
113 * essentially a token together with the GPU address of the batchbuffer
116 * 4. Add a pipeline flush to the buffer.
118 * 5. Add a memory write command to the buffer to record when the GPU
119 * is done executing the batchbuffer. The memory write writes the
120 * global sequence number of the request, ``i915_request::global_seqno``;
121 * the i915 driver uses the current value in the register to determine
122 * if the GPU has completed the batchbuffer.
124 * 6. Add a user interrupt command to the buffer. This command instructs
125 * the GPU to issue an interrupt when the command, pipeline flush and
126 * memory write are completed.
128 * 7. Inform the hardware of the additional commands added to the buffer
129 * (by updating the tail pointer).
131 * Processing an execbuf ioctl is conceptually split up into a few phases.
133 * 1. Validation - Ensure all the pointers, handles and flags are valid.
134 * 2. Reservation - Assign GPU address space for every object
135 * 3. Relocation - Update any addresses to point to the final locations
136 * 4. Serialisation - Order the request with respect to its dependencies
137 * 5. Construction - Construct a request to execute the batchbuffer
138 * 6. Submission (at some point in the future execution)
140 * Reserving resources for the execbuf is the most complicated phase. We
141 * neither want to have to migrate the object in the address space, nor do
142 * we want to have to update any relocations pointing to this object. Ideally,
143 * we want to leave the object where it is and for all the existing relocations
144 * to match. If the object is given a new address, or if userspace thinks the
145 * object is elsewhere, we have to parse all the relocation entries and update
146 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
147 * all the target addresses in all of its objects match the value in the
148 * relocation entries and that they all match the presumed offsets given by the
149 * list of execbuffer objects. Using this knowledge, we know that if we haven't
150 * moved any buffers, all the relocation entries are valid and we can skip
151 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
152 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
154 * The addresses written in the objects must match the corresponding
155 * reloc.presumed_offset which in turn must match the corresponding
158 * Any render targets written to in the batch must be flagged with
161 * To avoid stalling, execobject.offset should match the current
162 * address of that object within the active context.
164 * The reservation is done is multiple phases. First we try and keep any
165 * object already bound in its current location - so as long as meets the
166 * constraints imposed by the new execbuffer. Any object left unbound after the
167 * first pass is then fitted into any available idle space. If an object does
168 * not fit, all objects are removed from the reservation and the process rerun
169 * after sorting the objects into a priority order (more difficult to fit
170 * objects are tried first). Failing that, the entire VM is cleared and we try
171 * to fit the execbuf once last time before concluding that it simply will not
174 * A small complication to all of this is that we allow userspace not only to
175 * specify an alignment and a size for the object in the address space, but
176 * we also allow userspace to specify the exact offset. This objects are
177 * simpler to place (the location is known a priori) all we have to do is make
178 * sure the space is available.
180 * Once all the objects are in place, patching up the buried pointers to point
181 * to the final locations is a fairly simple job of walking over the relocation
182 * entry arrays, looking up the right address and rewriting the value into
183 * the object. Simple! ... The relocation entries are stored in user memory
184 * and so to access them we have to copy them into a local buffer. That copy
185 * has to avoid taking any pagefaults as they may lead back to a GEM object
186 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
187 * the relocation into multiple passes. First we try to do everything within an
188 * atomic context (avoid the pagefaults) which requires that we never wait. If
189 * we detect that we may wait, or if we need to fault, then we have to fallback
190 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
191 * bells yet?) Dropping the mutex means that we lose all the state we have
192 * built up so far for the execbuf and we must reset any global data. However,
193 * we do leave the objects pinned in their final locations - which is a
194 * potential issue for concurrent execbufs. Once we have left the mutex, we can
195 * allocate and copy all the relocation entries into a large array at our
196 * leisure, reacquire the mutex, reclaim all the objects and other state and
197 * then proceed to update any incorrect addresses with the objects.
199 * As we process the relocation entries, we maintain a record of whether the
200 * object is being written to. Using NORELOC, we expect userspace to provide
201 * this information instead. We also check whether we can skip the relocation
202 * by comparing the expected value inside the relocation entry with the target's
203 * final address. If they differ, we have to map the current object and rewrite
204 * the 4 or 8 byte pointer within.
206 * Serialising an execbuf is quite simple according to the rules of the GEM
207 * ABI. Execution within each context is ordered by the order of submission.
208 * Writes to any GEM object are in order of submission and are exclusive. Reads
209 * from a GEM object are unordered with respect to other reads, but ordered by
210 * writes. A write submitted after a read cannot occur before the read, and
211 * similarly any read submitted after a write cannot occur before the write.
212 * Writes are ordered between engines such that only one write occurs at any
213 * time (completing any reads beforehand) - using semaphores where available
214 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
215 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
216 * reads before starting, and any read (either using set-domain or pread) must
217 * flush all GPU writes before starting. (Note we only employ a barrier before,
218 * we currently rely on userspace not concurrently starting a new execution
219 * whilst reading or writing to an object. This may be an advantage or not
220 * depending on how much you trust userspace not to shoot themselves in the
221 * foot.) Serialisation may just result in the request being inserted into
222 * a DAG awaiting its turn, but most simple is to wait on the CPU until
223 * all dependencies are resolved.
225 * After all of that, is just a matter of closing the request and handing it to
226 * the hardware (well, leaving it in a queue to be executed). However, we also
227 * offer the ability for batchbuffers to be run with elevated privileges so
228 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
229 * Before any batch is given extra privileges we first must check that it
230 * contains no nefarious instructions, we check that each instruction is from
231 * our whitelist and all registers are also from an allowed list. We first
232 * copy the user's batchbuffer to a shadow (so that the user doesn't have
233 * access to it, either by the CPU or GPU as we scan it) and then parse each
234 * instruction. If everything is ok, we set a flag telling the hardware to run
235 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
239 struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
240 struct dma_fence *dma_fence;
242 struct dma_fence_chain *chain_fence;
245 struct i915_execbuffer {
246 struct drm_i915_private *i915; /** i915 backpointer */
247 struct drm_file *file; /** per-file lookup tables and limits */
248 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
249 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
252 struct intel_gt *gt; /* gt for the execbuf */
253 struct intel_context *context; /* logical state for the request */
254 struct i915_gem_context *gem_context; /** caller's context */
256 /** our requests to build */
257 struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];
258 /** identity of the batch obj/vma */
259 struct eb_vma *batches[MAX_ENGINE_INSTANCE + 1];
260 struct i915_vma *trampoline; /** trampoline used for chaining */
262 /** used for excl fence in dma_resv objects when > 1 BB submitted */
263 struct dma_fence *composite_fence;
265 /** actual size of execobj[] as we may extend it for the cmdparser */
266 unsigned int buffer_count;
268 /* number of batches in execbuf IOCTL */
269 unsigned int num_batches;
271 /** list of vma not yet bound during reservation phase */
272 struct list_head unbound;
274 /** list of vma that have execobj.relocation_count */
275 struct list_head relocs;
277 struct i915_gem_ww_ctx ww;
280 * Track the most recently used object for relocations, as we
281 * frequently have to perform multiple relocations within the same
285 struct drm_mm_node node; /** temporary GTT binding */
286 unsigned long vaddr; /** Current kmap address */
287 unsigned long page; /** Currently mapped page index */
288 unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */
289 bool use_64bit_reloc : 1;
292 bool needs_unfenced : 1;
295 u64 invalid_flags; /** Set of execobj.flags that are invalid */
297 /** Length of batch within object */
298 u64 batch_len[MAX_ENGINE_INSTANCE + 1];
299 u32 batch_start_offset; /** Location within object of batch */
300 u32 batch_flags; /** Flags composed for emit_bb_start() */
301 struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
304 * Indicate either the size of the hastable used to resolve
305 * relocation handles, or if negative that we are using a direct
306 * index into the execobj[].
309 struct hlist_head *buckets; /** ht for relocation handles */
311 struct eb_fence *fences;
312 unsigned long num_fences;
313 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
314 struct i915_capture_list *capture_lists[MAX_ENGINE_INSTANCE + 1];
318 static int eb_parse(struct i915_execbuffer *eb);
319 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle);
320 static void eb_unpin_engine(struct i915_execbuffer *eb);
321 static void eb_capture_release(struct i915_execbuffer *eb);
323 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
325 return intel_engine_requires_cmd_parser(eb->context->engine) ||
326 (intel_engine_using_cmd_parser(eb->context->engine) &&
327 eb->args->batch_len);
330 static int eb_create(struct i915_execbuffer *eb)
332 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
333 unsigned int size = 1 + ilog2(eb->buffer_count);
336 * Without a 1:1 association between relocation handles and
337 * the execobject[] index, we instead create a hashtable.
338 * We size it dynamically based on available memory, starting
339 * first with 1:1 assocative hash and scaling back until
340 * the allocation succeeds.
342 * Later on we use a positive lut_size to indicate we are
343 * using this hashtable, and a negative value to indicate a
349 /* While we can still reduce the allocation size, don't
350 * raise a warning and allow the allocation to fail.
351 * On the last pass though, we want to try as hard
352 * as possible to perform the allocation and warn
357 flags |= __GFP_NORETRY | __GFP_NOWARN;
359 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
370 eb->lut_size = -eb->buffer_count;
377 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
378 const struct i915_vma *vma,
381 if (vma->node.size < entry->pad_to_size)
384 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
387 if (flags & EXEC_OBJECT_PINNED &&
388 vma->node.start != entry->offset)
391 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
392 vma->node.start < BATCH_OFFSET_BIAS)
395 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
396 (vma->node.start + vma->node.size + 4095) >> 32)
399 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
400 !i915_vma_is_map_and_fenceable(vma))
406 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
407 unsigned int exec_flags)
411 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
412 pin_flags |= PIN_GLOBAL;
415 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
416 * limit address to the first 4GBs for unflagged objects.
418 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
419 pin_flags |= PIN_ZONE_4G;
421 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
422 pin_flags |= PIN_MAPPABLE;
424 if (exec_flags & EXEC_OBJECT_PINNED)
425 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
426 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
427 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
433 eb_pin_vma(struct i915_execbuffer *eb,
434 const struct drm_i915_gem_exec_object2 *entry,
437 struct i915_vma *vma = ev->vma;
442 pin_flags = vma->node.start;
444 pin_flags = entry->offset & PIN_OFFSET_MASK;
446 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED | PIN_VALIDATE;
447 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
448 pin_flags |= PIN_GLOBAL;
450 /* Attempt to reuse the current location if available */
451 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags);
456 if (entry->flags & EXEC_OBJECT_PINNED)
459 /* Failing that pick any _free_ space if suitable */
460 err = i915_vma_pin_ww(vma, &eb->ww,
463 eb_pin_flags(entry, ev->flags) |
464 PIN_USER | PIN_NOEVICT | PIN_VALIDATE);
469 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
470 err = i915_vma_pin_fence(vma);
475 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
478 ev->flags |= __EXEC_OBJECT_HAS_PIN;
479 if (eb_vma_misplaced(entry, vma, ev->flags))
486 eb_unreserve_vma(struct eb_vma *ev)
488 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
489 __i915_vma_unpin_fence(ev->vma);
491 ev->flags &= ~__EXEC_OBJECT_RESERVED;
495 eb_validate_vma(struct i915_execbuffer *eb,
496 struct drm_i915_gem_exec_object2 *entry,
497 struct i915_vma *vma)
499 /* Relocations are disallowed for all platforms after TGL-LP. This
500 * also covers all platforms with local memory.
502 if (entry->relocation_count &&
503 GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
506 if (unlikely(entry->flags & eb->invalid_flags))
509 if (unlikely(entry->alignment &&
510 !is_power_of_2_u64(entry->alignment)))
514 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
515 * any non-page-aligned or non-canonical addresses.
517 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
518 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
521 /* pad_to_size was once a reserved field, so sanitize it */
522 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
523 if (unlikely(offset_in_page(entry->pad_to_size)))
526 entry->pad_to_size = 0;
529 * From drm_mm perspective address space is continuous,
530 * so from this point we're always using non-canonical
533 entry->offset = gen8_noncanonical_addr(entry->offset);
535 if (!eb->reloc_cache.has_fence) {
536 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
538 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
539 eb->reloc_cache.needs_unfenced) &&
540 i915_gem_object_is_tiled(vma->obj))
541 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
548 is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx)
550 return eb->args->flags & I915_EXEC_BATCH_FIRST ?
551 buffer_idx < eb->num_batches :
552 buffer_idx >= eb->args->buffer_count - eb->num_batches;
556 eb_add_vma(struct i915_execbuffer *eb,
557 unsigned int *current_batch,
559 struct i915_vma *vma)
561 struct drm_i915_private *i915 = eb->i915;
562 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
563 struct eb_vma *ev = &eb->vma[i];
567 ev->flags = entry->flags;
569 if (eb->lut_size > 0) {
570 ev->handle = entry->handle;
571 hlist_add_head(&ev->node,
572 &eb->buckets[hash_32(entry->handle,
576 if (entry->relocation_count)
577 list_add_tail(&ev->reloc_link, &eb->relocs);
580 * SNA is doing fancy tricks with compressing batch buffers, which leads
581 * to negative relocation deltas. Usually that works out ok since the
582 * relocate address is still positive, except when the batch is placed
583 * very low in the GTT. Ensure this doesn't happen.
585 * Note that actual hangs have only been observed on gen7, but for
586 * paranoia do it everywhere.
588 if (is_batch_buffer(eb, i)) {
589 if (entry->relocation_count &&
590 !(ev->flags & EXEC_OBJECT_PINNED))
591 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
592 if (eb->reloc_cache.has_fence)
593 ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
595 eb->batches[*current_batch] = ev;
597 if (unlikely(ev->flags & EXEC_OBJECT_WRITE)) {
599 "Attempting to use self-modifying batch buffer\n");
603 if (range_overflows_t(u64,
604 eb->batch_start_offset,
607 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
611 if (eb->args->batch_len == 0)
612 eb->batch_len[*current_batch] = ev->vma->size -
613 eb->batch_start_offset;
615 eb->batch_len[*current_batch] = eb->args->batch_len;
616 if (unlikely(eb->batch_len[*current_batch] == 0)) { /* impossible! */
617 drm_dbg(&i915->drm, "Invalid batch length\n");
627 static inline int use_cpu_reloc(const struct reloc_cache *cache,
628 const struct drm_i915_gem_object *obj)
630 if (!i915_gem_object_has_struct_page(obj))
633 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
636 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
639 return (cache->has_llc ||
641 obj->cache_level != I915_CACHE_NONE);
644 static int eb_reserve_vma(struct i915_execbuffer *eb,
648 struct drm_i915_gem_exec_object2 *entry = ev->exec;
649 struct i915_vma *vma = ev->vma;
652 if (drm_mm_node_allocated(&vma->node) &&
653 eb_vma_misplaced(entry, vma, ev->flags)) {
654 err = i915_vma_unbind(vma);
659 err = i915_vma_pin_ww(vma, &eb->ww,
660 entry->pad_to_size, entry->alignment,
661 eb_pin_flags(entry, ev->flags) | pin_flags);
665 if (entry->offset != vma->node.start) {
666 entry->offset = vma->node.start | UPDATE;
667 eb->args->flags |= __EXEC_HAS_RELOC;
670 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
671 err = i915_vma_pin_fence(vma);
676 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
679 ev->flags |= __EXEC_OBJECT_HAS_PIN;
680 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
685 static bool eb_unbind(struct i915_execbuffer *eb, bool force)
687 const unsigned int count = eb->buffer_count;
689 struct list_head last;
690 bool unpinned = false;
692 /* Resort *all* the objects into priority order */
693 INIT_LIST_HEAD(&eb->unbound);
694 INIT_LIST_HEAD(&last);
696 for (i = 0; i < count; i++) {
697 struct eb_vma *ev = &eb->vma[i];
698 unsigned int flags = ev->flags;
700 if (!force && flags & EXEC_OBJECT_PINNED &&
701 flags & __EXEC_OBJECT_HAS_PIN)
705 eb_unreserve_vma(ev);
707 if (flags & EXEC_OBJECT_PINNED)
708 /* Pinned must have their slot */
709 list_add(&ev->bind_link, &eb->unbound);
710 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
711 /* Map require the lowest 256MiB (aperture) */
712 list_add_tail(&ev->bind_link, &eb->unbound);
713 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
714 /* Prioritise 4GiB region for restricted bo */
715 list_add(&ev->bind_link, &last);
717 list_add_tail(&ev->bind_link, &last);
720 list_splice_tail(&last, &eb->unbound);
724 static int eb_reserve(struct i915_execbuffer *eb)
732 * Attempt to pin all of the buffers into the GTT.
733 * This is done in 2 phases:
735 * 1. Unbind all objects that do not match the GTT constraints for
736 * the execbuffer (fenceable, mappable, alignment etc).
737 * 2. Bind new objects.
739 * This avoid unnecessary unbinding of later objects in order to make
740 * room for the earlier objects *unless* we need to defragment.
742 * Defragmenting is skipped if all objects are pinned at a fixed location.
744 for (pass = 0; pass <= 2; pass++) {
745 int pin_flags = PIN_USER | PIN_VALIDATE;
748 pin_flags |= PIN_NONBLOCK;
751 unpinned = eb_unbind(eb, pass == 2);
754 err = mutex_lock_interruptible(&eb->context->vm->mutex);
756 err = i915_gem_evict_vm(eb->context->vm, &eb->ww);
757 mutex_unlock(&eb->context->vm->mutex);
763 list_for_each_entry(ev, &eb->unbound, bind_link) {
764 err = eb_reserve_vma(eb, ev, pin_flags);
776 static int eb_select_context(struct i915_execbuffer *eb)
778 struct i915_gem_context *ctx;
780 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
781 if (unlikely(IS_ERR(ctx)))
784 eb->gem_context = ctx;
785 if (i915_gem_context_has_full_ppgtt(ctx))
786 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
791 static int __eb_add_lut(struct i915_execbuffer *eb,
792 u32 handle, struct i915_vma *vma)
794 struct i915_gem_context *ctx = eb->gem_context;
795 struct i915_lut_handle *lut;
798 lut = i915_lut_handle_alloc();
803 if (!atomic_fetch_inc(&vma->open_count))
804 i915_vma_reopen(vma);
805 lut->handle = handle;
808 /* Check that the context hasn't been closed in the meantime */
810 if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
811 if (likely(!i915_gem_context_is_closed(ctx)))
812 err = radix_tree_insert(&ctx->handles_vma, handle, vma);
815 if (err == 0) { /* And nor has this handle */
816 struct drm_i915_gem_object *obj = vma->obj;
818 spin_lock(&obj->lut_lock);
819 if (idr_find(&eb->file->object_idr, handle) == obj) {
820 list_add(&lut->obj_link, &obj->lut_list);
822 radix_tree_delete(&ctx->handles_vma, handle);
825 spin_unlock(&obj->lut_lock);
827 mutex_unlock(&ctx->lut_mutex);
837 i915_lut_handle_free(lut);
841 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
843 struct i915_address_space *vm = eb->context->vm;
846 struct drm_i915_gem_object *obj;
847 struct i915_vma *vma;
851 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
852 if (likely(vma && vma->vm == vm))
853 vma = i915_vma_tryget(vma);
858 obj = i915_gem_object_lookup(eb->file, handle);
860 return ERR_PTR(-ENOENT);
863 * If the user has opted-in for protected-object tracking, make
864 * sure the object encryption can be used.
865 * We only need to do this when the object is first used with
866 * this context, because the context itself will be banned when
867 * the protected objects become invalid.
869 if (i915_gem_context_uses_protected_content(eb->gem_context) &&
870 i915_gem_object_is_protected(obj)) {
871 err = intel_pxp_key_check(&vm->gt->pxp, obj, true);
873 i915_gem_object_put(obj);
878 vma = i915_vma_instance(obj, vm, NULL);
880 i915_gem_object_put(obj);
884 err = __eb_add_lut(eb, handle, vma);
888 i915_gem_object_put(obj);
894 static int eb_lookup_vmas(struct i915_execbuffer *eb)
896 unsigned int i, current_batch = 0;
899 INIT_LIST_HEAD(&eb->relocs);
901 for (i = 0; i < eb->buffer_count; i++) {
902 struct i915_vma *vma;
904 vma = eb_lookup_vma(eb, eb->exec[i].handle);
910 err = eb_validate_vma(eb, &eb->exec[i], vma);
916 err = eb_add_vma(eb, ¤t_batch, i, vma);
920 if (i915_gem_object_is_userptr(vma->obj)) {
921 err = i915_gem_object_userptr_submit_init(vma->obj);
923 if (i + 1 < eb->buffer_count) {
925 * Execbuffer code expects last vma entry to be NULL,
926 * since we already initialized this entry,
927 * set the next value to NULL or we mess up
930 eb->vma[i + 1].vma = NULL;
936 eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT;
937 eb->args->flags |= __EXEC_USERPTR_USED;
944 eb->vma[i].vma = NULL;
948 static int eb_lock_vmas(struct i915_execbuffer *eb)
953 for (i = 0; i < eb->buffer_count; i++) {
954 struct eb_vma *ev = &eb->vma[i];
955 struct i915_vma *vma = ev->vma;
957 err = i915_gem_object_lock(vma->obj, &eb->ww);
965 static int eb_validate_vmas(struct i915_execbuffer *eb)
970 INIT_LIST_HEAD(&eb->unbound);
972 err = eb_lock_vmas(eb);
976 for (i = 0; i < eb->buffer_count; i++) {
977 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
978 struct eb_vma *ev = &eb->vma[i];
979 struct i915_vma *vma = ev->vma;
981 err = eb_pin_vma(eb, entry, ev);
986 if (entry->offset != vma->node.start) {
987 entry->offset = vma->node.start | UPDATE;
988 eb->args->flags |= __EXEC_HAS_RELOC;
991 eb_unreserve_vma(ev);
993 list_add_tail(&ev->bind_link, &eb->unbound);
994 if (drm_mm_node_allocated(&vma->node)) {
995 err = i915_vma_unbind(vma);
1001 err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
1005 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
1006 eb_vma_misplaced(&eb->exec[i], vma, ev->flags));
1009 if (!list_empty(&eb->unbound))
1010 return eb_reserve(eb);
1015 static struct eb_vma *
1016 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
1018 if (eb->lut_size < 0) {
1019 if (handle >= -eb->lut_size)
1021 return &eb->vma[handle];
1023 struct hlist_head *head;
1026 head = &eb->buckets[hash_32(handle, eb->lut_size)];
1027 hlist_for_each_entry(ev, head, node) {
1028 if (ev->handle == handle)
1035 static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
1037 const unsigned int count = eb->buffer_count;
1040 for (i = 0; i < count; i++) {
1041 struct eb_vma *ev = &eb->vma[i];
1042 struct i915_vma *vma = ev->vma;
1047 eb_unreserve_vma(ev);
1053 eb_capture_release(eb);
1054 eb_unpin_engine(eb);
1057 static void eb_destroy(const struct i915_execbuffer *eb)
1059 if (eb->lut_size > 0)
1064 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
1065 const struct i915_vma *target)
1067 return gen8_canonical_addr((int)reloc->delta + target->node.start);
1070 static void reloc_cache_init(struct reloc_cache *cache,
1071 struct drm_i915_private *i915)
1075 /* Must be a variable in the struct to allow GCC to unroll. */
1076 cache->graphics_ver = GRAPHICS_VER(i915);
1077 cache->has_llc = HAS_LLC(i915);
1078 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
1079 cache->has_fence = cache->graphics_ver < 4;
1080 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
1081 cache->node.flags = 0;
1084 static inline void *unmask_page(unsigned long p)
1086 return (void *)(uintptr_t)(p & PAGE_MASK);
1089 static inline unsigned int unmask_flags(unsigned long p)
1091 return p & ~PAGE_MASK;
1094 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
1096 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1098 struct drm_i915_private *i915 =
1099 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
1100 return to_gt(i915)->ggtt;
1103 static void reloc_cache_unmap(struct reloc_cache *cache)
1110 vaddr = unmask_page(cache->vaddr);
1111 if (cache->vaddr & KMAP)
1112 kunmap_atomic(vaddr);
1114 io_mapping_unmap_atomic((void __iomem *)vaddr);
1117 static void reloc_cache_remap(struct reloc_cache *cache,
1118 struct drm_i915_gem_object *obj)
1125 if (cache->vaddr & KMAP) {
1126 struct page *page = i915_gem_object_get_page(obj, cache->page);
1128 vaddr = kmap_atomic(page);
1129 cache->vaddr = unmask_flags(cache->vaddr) |
1130 (unsigned long)vaddr;
1132 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1133 unsigned long offset;
1135 offset = cache->node.start;
1136 if (!drm_mm_node_allocated(&cache->node))
1137 offset += cache->page << PAGE_SHIFT;
1139 cache->vaddr = (unsigned long)
1140 io_mapping_map_atomic_wc(&ggtt->iomap, offset);
1144 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
1151 vaddr = unmask_page(cache->vaddr);
1152 if (cache->vaddr & KMAP) {
1153 struct drm_i915_gem_object *obj =
1154 (struct drm_i915_gem_object *)cache->node.mm;
1155 if (cache->vaddr & CLFLUSH_AFTER)
1158 kunmap_atomic(vaddr);
1159 i915_gem_object_finish_access(obj);
1161 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1163 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1164 io_mapping_unmap_atomic((void __iomem *)vaddr);
1166 if (drm_mm_node_allocated(&cache->node)) {
1167 ggtt->vm.clear_range(&ggtt->vm,
1170 mutex_lock(&ggtt->vm.mutex);
1171 drm_mm_remove_node(&cache->node);
1172 mutex_unlock(&ggtt->vm.mutex);
1174 i915_vma_unpin((struct i915_vma *)cache->node.mm);
1182 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1183 struct reloc_cache *cache,
1184 unsigned long pageno)
1190 kunmap_atomic(unmask_page(cache->vaddr));
1192 unsigned int flushes;
1195 err = i915_gem_object_prepare_write(obj, &flushes);
1197 return ERR_PTR(err);
1199 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1200 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1202 cache->vaddr = flushes | KMAP;
1203 cache->node.mm = (void *)obj;
1208 page = i915_gem_object_get_page(obj, pageno);
1210 set_page_dirty(page);
1212 vaddr = kmap_atomic(page);
1213 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1214 cache->page = pageno;
1219 static void *reloc_iomap(struct i915_vma *batch,
1220 struct i915_execbuffer *eb,
1223 struct drm_i915_gem_object *obj = batch->obj;
1224 struct reloc_cache *cache = &eb->reloc_cache;
1225 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1226 unsigned long offset;
1230 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1231 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1233 struct i915_vma *vma = ERR_PTR(-ENODEV);
1236 if (i915_gem_object_is_tiled(obj))
1237 return ERR_PTR(-EINVAL);
1239 if (use_cpu_reloc(cache, obj))
1242 err = i915_gem_object_set_to_gtt_domain(obj, true);
1244 return ERR_PTR(err);
1247 * i915_gem_object_ggtt_pin_ww may attempt to remove the batch
1248 * VMA from the object list because we no longer pin.
1250 * Only attempt to pin the batch buffer to ggtt if the current batch
1251 * is not inside ggtt, or the batch buffer is not misplaced.
1253 if (!i915_is_ggtt(batch->vm)) {
1254 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
1256 PIN_NONBLOCK /* NOWARN */ |
1258 } else if (i915_vma_is_map_and_fenceable(batch)) {
1259 __i915_vma_pin(batch);
1263 if (vma == ERR_PTR(-EDEADLK))
1267 memset(&cache->node, 0, sizeof(cache->node));
1268 mutex_lock(&ggtt->vm.mutex);
1269 err = drm_mm_insert_node_in_range
1270 (&ggtt->vm.mm, &cache->node,
1271 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1272 0, ggtt->mappable_end,
1274 mutex_unlock(&ggtt->vm.mutex);
1275 if (err) /* no inactive aperture space, use cpu reloc */
1278 cache->node.start = vma->node.start;
1279 cache->node.mm = (void *)vma;
1283 offset = cache->node.start;
1284 if (drm_mm_node_allocated(&cache->node)) {
1285 ggtt->vm.insert_page(&ggtt->vm,
1286 i915_gem_object_get_dma_address(obj, page),
1287 offset, I915_CACHE_NONE, 0);
1289 offset += page << PAGE_SHIFT;
1292 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1295 cache->vaddr = (unsigned long)vaddr;
1300 static void *reloc_vaddr(struct i915_vma *vma,
1301 struct i915_execbuffer *eb,
1304 struct reloc_cache *cache = &eb->reloc_cache;
1307 if (cache->page == page) {
1308 vaddr = unmask_page(cache->vaddr);
1311 if ((cache->vaddr & KMAP) == 0)
1312 vaddr = reloc_iomap(vma, eb, page);
1314 vaddr = reloc_kmap(vma->obj, cache, page);
1320 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1322 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1323 if (flushes & CLFLUSH_BEFORE)
1324 drm_clflush_virt_range(addr, sizeof(*addr));
1329 * Writes to the same cacheline are serialised by the CPU
1330 * (including clflush). On the write path, we only require
1331 * that it hits memory in an orderly fashion and place
1332 * mb barriers at the start and end of the relocation phase
1333 * to ensure ordering of clflush wrt to the system.
1335 if (flushes & CLFLUSH_AFTER)
1336 drm_clflush_virt_range(addr, sizeof(*addr));
1342 relocate_entry(struct i915_vma *vma,
1343 const struct drm_i915_gem_relocation_entry *reloc,
1344 struct i915_execbuffer *eb,
1345 const struct i915_vma *target)
1347 u64 target_addr = relocation_target(reloc, target);
1348 u64 offset = reloc->offset;
1349 bool wide = eb->reloc_cache.use_64bit_reloc;
1353 vaddr = reloc_vaddr(vma, eb,
1354 offset >> PAGE_SHIFT);
1356 return PTR_ERR(vaddr);
1358 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1359 clflush_write32(vaddr + offset_in_page(offset),
1360 lower_32_bits(target_addr),
1361 eb->reloc_cache.vaddr);
1364 offset += sizeof(u32);
1370 return target->node.start | UPDATE;
1374 eb_relocate_entry(struct i915_execbuffer *eb,
1376 const struct drm_i915_gem_relocation_entry *reloc)
1378 struct drm_i915_private *i915 = eb->i915;
1379 struct eb_vma *target;
1382 /* we've already hold a reference to all valid objects */
1383 target = eb_get_vma(eb, reloc->target_handle);
1384 if (unlikely(!target))
1387 /* Validate that the target is in a valid r/w GPU domain */
1388 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1389 drm_dbg(&i915->drm, "reloc with multiple write domains: "
1390 "target %d offset %d "
1391 "read %08x write %08x",
1392 reloc->target_handle,
1393 (int) reloc->offset,
1394 reloc->read_domains,
1395 reloc->write_domain);
1398 if (unlikely((reloc->write_domain | reloc->read_domains)
1399 & ~I915_GEM_GPU_DOMAINS)) {
1400 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1401 "target %d offset %d "
1402 "read %08x write %08x",
1403 reloc->target_handle,
1404 (int) reloc->offset,
1405 reloc->read_domains,
1406 reloc->write_domain);
1410 if (reloc->write_domain) {
1411 target->flags |= EXEC_OBJECT_WRITE;
1414 * Sandybridge PPGTT errata: We need a global gtt mapping
1415 * for MI and pipe_control writes because the gpu doesn't
1416 * properly redirect them through the ppgtt for non_secure
1419 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1420 GRAPHICS_VER(eb->i915) == 6 &&
1421 !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) {
1422 struct i915_vma *vma = target->vma;
1424 reloc_cache_unmap(&eb->reloc_cache);
1425 mutex_lock(&vma->vm->mutex);
1426 err = i915_vma_bind(target->vma,
1427 target->vma->obj->cache_level,
1428 PIN_GLOBAL, NULL, NULL);
1429 mutex_unlock(&vma->vm->mutex);
1430 reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
1437 * If the relocation already has the right value in it, no
1438 * more work needs to be done.
1440 if (!DBG_FORCE_RELOC &&
1441 gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
1444 /* Check that the relocation address is valid... */
1445 if (unlikely(reloc->offset >
1446 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1447 drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1448 "target %d offset %d size %d.\n",
1449 reloc->target_handle,
1451 (int)ev->vma->size);
1454 if (unlikely(reloc->offset & 3)) {
1455 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1456 "target %d offset %d.\n",
1457 reloc->target_handle,
1458 (int)reloc->offset);
1463 * If we write into the object, we need to force the synchronisation
1464 * barrier, either with an asynchronous clflush or if we executed the
1465 * patching using the GPU (though that should be serialised by the
1466 * timeline). To be completely sure, and since we are required to
1467 * do relocations we are already stalling, disable the user's opt
1468 * out of our synchronisation.
1470 ev->flags &= ~EXEC_OBJECT_ASYNC;
1472 /* and update the user's relocation entry */
1473 return relocate_entry(ev->vma, reloc, eb, target->vma);
1476 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1478 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1479 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1480 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1481 struct drm_i915_gem_relocation_entry __user *urelocs =
1482 u64_to_user_ptr(entry->relocs_ptr);
1483 unsigned long remain = entry->relocation_count;
1485 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1489 * We must check that the entire relocation array is safe
1490 * to read. However, if the array is not writable the user loses
1491 * the updated relocation values.
1493 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1497 struct drm_i915_gem_relocation_entry *r = stack;
1498 unsigned int count =
1499 min_t(unsigned long, remain, ARRAY_SIZE(stack));
1500 unsigned int copied;
1503 * This is the fast path and we cannot handle a pagefault
1504 * whilst holding the struct mutex lest the user pass in the
1505 * relocations contained within a mmaped bo. For in such a case
1506 * we, the page fault handler would call i915_gem_fault() and
1507 * we would try to acquire the struct mutex again. Obviously
1508 * this is bad and so lockdep complains vehemently.
1510 pagefault_disable();
1511 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1513 if (unlikely(copied)) {
1520 u64 offset = eb_relocate_entry(eb, ev, r);
1522 if (likely(offset == 0)) {
1523 } else if ((s64)offset < 0) {
1524 remain = (int)offset;
1528 * Note that reporting an error now
1529 * leaves everything in an inconsistent
1530 * state as we have *already* changed
1531 * the relocation value inside the
1532 * object. As we have not changed the
1533 * reloc.presumed_offset or will not
1534 * change the execobject.offset, on the
1535 * call we may not rewrite the value
1536 * inside the object, leaving it
1537 * dangling and causing a GPU hang. Unless
1538 * userspace dynamically rebuilds the
1539 * relocations on each execbuf rather than
1540 * presume a static tree.
1542 * We did previously check if the relocations
1543 * were writable (access_ok), an error now
1544 * would be a strange race with mprotect,
1545 * having already demonstrated that we
1546 * can read from this userspace address.
1548 offset = gen8_canonical_addr(offset & ~UPDATE);
1550 &urelocs[r - stack].presumed_offset);
1552 } while (r++, --count);
1553 urelocs += ARRAY_SIZE(stack);
1556 reloc_cache_reset(&eb->reloc_cache, eb);
1561 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
1563 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1564 struct drm_i915_gem_relocation_entry *relocs =
1565 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1569 for (i = 0; i < entry->relocation_count; i++) {
1570 u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
1572 if ((s64)offset < 0) {
1579 reloc_cache_reset(&eb->reloc_cache, eb);
1583 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1585 const char __user *addr, *end;
1587 char __maybe_unused c;
1589 size = entry->relocation_count;
1593 if (size > N_RELOC(ULONG_MAX))
1596 addr = u64_to_user_ptr(entry->relocs_ptr);
1597 size *= sizeof(struct drm_i915_gem_relocation_entry);
1598 if (!access_ok(addr, size))
1602 for (; addr < end; addr += PAGE_SIZE) {
1603 int err = __get_user(c, addr);
1607 return __get_user(c, end - 1);
1610 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1612 struct drm_i915_gem_relocation_entry *relocs;
1613 const unsigned int count = eb->buffer_count;
1617 for (i = 0; i < count; i++) {
1618 const unsigned int nreloc = eb->exec[i].relocation_count;
1619 struct drm_i915_gem_relocation_entry __user *urelocs;
1621 unsigned long copied;
1626 err = check_relocations(&eb->exec[i]);
1630 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1631 size = nreloc * sizeof(*relocs);
1633 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1639 /* copy_from_user is limited to < 4GiB */
1643 min_t(u64, BIT_ULL(31), size - copied);
1645 if (__copy_from_user((char *)relocs + copied,
1646 (char __user *)urelocs + copied,
1651 } while (copied < size);
1654 * As we do not update the known relocation offsets after
1655 * relocating (due to the complexities in lock handling),
1656 * we need to mark them as invalid now so that we force the
1657 * relocation processing next time. Just in case the target
1658 * object is evicted and then rebound into its old
1659 * presumed_offset before the next execbuffer - if that
1660 * happened we would make the mistake of assuming that the
1661 * relocations were valid.
1663 if (!user_access_begin(urelocs, size))
1666 for (copied = 0; copied < nreloc; copied++)
1668 &urelocs[copied].presumed_offset,
1672 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1684 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1685 if (eb->exec[i].relocation_count)
1691 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1693 const unsigned int count = eb->buffer_count;
1696 for (i = 0; i < count; i++) {
1699 err = check_relocations(&eb->exec[i]);
1707 static int eb_reinit_userptr(struct i915_execbuffer *eb)
1709 const unsigned int count = eb->buffer_count;
1713 if (likely(!(eb->args->flags & __EXEC_USERPTR_USED)))
1716 for (i = 0; i < count; i++) {
1717 struct eb_vma *ev = &eb->vma[i];
1719 if (!i915_gem_object_is_userptr(ev->vma->obj))
1722 ret = i915_gem_object_userptr_submit_init(ev->vma->obj);
1726 ev->flags |= __EXEC_OBJECT_USERPTR_INIT;
1732 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
1734 bool have_copy = false;
1739 if (signal_pending(current)) {
1744 /* We may process another execbuffer during the unlock... */
1745 eb_release_vmas(eb, false);
1746 i915_gem_ww_ctx_fini(&eb->ww);
1749 * We take 3 passes through the slowpatch.
1751 * 1 - we try to just prefault all the user relocation entries and
1752 * then attempt to reuse the atomic pagefault disabled fast path again.
1754 * 2 - we copy the user entries to a local buffer here outside of the
1755 * local and allow ourselves to wait upon any rendering before
1758 * 3 - we already have a local copy of the relocation entries, but
1759 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1762 err = eb_prefault_relocations(eb);
1763 } else if (!have_copy) {
1764 err = eb_copy_relocations(eb);
1765 have_copy = err == 0;
1772 err = eb_reinit_userptr(eb);
1774 i915_gem_ww_ctx_init(&eb->ww, true);
1778 /* reacquire the objects */
1780 err = eb_pin_engine(eb, false);
1784 err = eb_validate_vmas(eb);
1788 GEM_BUG_ON(!eb->batches[0]);
1790 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1792 err = eb_relocate_vma(eb, ev);
1796 err = eb_relocate_vma_slow(eb, ev);
1802 if (err == -EDEADLK)
1805 if (err && !have_copy)
1811 /* as last step, parse the command buffer */
1817 * Leave the user relocations as are, this is the painfully slow path,
1818 * and we want to avoid the complication of dropping the lock whilst
1819 * having buffers reserved in the aperture and so causing spurious
1820 * ENOSPC for random operations.
1824 if (err == -EDEADLK) {
1825 eb_release_vmas(eb, false);
1826 err = i915_gem_ww_ctx_backoff(&eb->ww);
1828 goto repeat_validate;
1836 const unsigned int count = eb->buffer_count;
1839 for (i = 0; i < count; i++) {
1840 const struct drm_i915_gem_exec_object2 *entry =
1842 struct drm_i915_gem_relocation_entry *relocs;
1844 if (!entry->relocation_count)
1847 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1855 static int eb_relocate_parse(struct i915_execbuffer *eb)
1858 bool throttle = true;
1861 err = eb_pin_engine(eb, throttle);
1863 if (err != -EDEADLK)
1869 /* only throttle once, even if we didn't need to throttle */
1872 err = eb_validate_vmas(eb);
1878 /* The objects are in their final locations, apply the relocations. */
1879 if (eb->args->flags & __EXEC_HAS_RELOC) {
1882 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1883 err = eb_relocate_vma(eb, ev);
1888 if (err == -EDEADLK)
1898 if (err == -EDEADLK) {
1899 eb_release_vmas(eb, false);
1900 err = i915_gem_ww_ctx_backoff(&eb->ww);
1908 err = eb_relocate_parse_slow(eb);
1911 * If the user expects the execobject.offset and
1912 * reloc.presumed_offset to be an exact match,
1913 * as for using NO_RELOC, then we cannot update
1914 * the execobject.offset until we have completed
1917 eb->args->flags &= ~__EXEC_HAS_RELOC;
1923 * Using two helper loops for the order of which requests / batches are created
1924 * and added the to backend. Requests are created in order from the parent to
1925 * the last child. Requests are added in the reverse order, from the last child
1926 * to parent. This is done for locking reasons as the timeline lock is acquired
1927 * during request creation and released when the request is added to the
1928 * backend. To make lockdep happy (see intel_context_timeline_lock) this must be
1931 #define for_each_batch_create_order(_eb, _i) \
1932 for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i))
1933 #define for_each_batch_add_order(_eb, _i) \
1934 BUILD_BUG_ON(!typecheck(int, _i)); \
1935 for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i))
1937 static struct i915_request *
1938 eb_find_first_request_added(struct i915_execbuffer *eb)
1942 for_each_batch_add_order(eb, i)
1943 if (eb->requests[i])
1944 return eb->requests[i];
1946 GEM_BUG_ON("Request not found");
1951 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1953 /* Stage with GFP_KERNEL allocations before we enter the signaling critical path */
1954 static void eb_capture_stage(struct i915_execbuffer *eb)
1956 const unsigned int count = eb->buffer_count;
1957 unsigned int i = count, j;
1960 struct eb_vma *ev = &eb->vma[i];
1961 struct i915_vma *vma = ev->vma;
1962 unsigned int flags = ev->flags;
1964 if (!(flags & EXEC_OBJECT_CAPTURE))
1967 for_each_batch_create_order(eb, j) {
1968 struct i915_capture_list *capture;
1970 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1974 capture->next = eb->capture_lists[j];
1975 capture->vma_res = i915_vma_resource_get(vma->resource);
1976 eb->capture_lists[j] = capture;
1981 /* Commit once we're in the critical path */
1982 static void eb_capture_commit(struct i915_execbuffer *eb)
1986 for_each_batch_create_order(eb, j) {
1987 struct i915_request *rq = eb->requests[j];
1992 rq->capture_list = eb->capture_lists[j];
1993 eb->capture_lists[j] = NULL;
1998 * Release anything that didn't get committed due to errors.
1999 * The capture_list will otherwise be freed at request retire.
2001 static void eb_capture_release(struct i915_execbuffer *eb)
2005 for_each_batch_create_order(eb, j) {
2006 if (eb->capture_lists[j]) {
2007 i915_request_free_capture_list(eb->capture_lists[j]);
2008 eb->capture_lists[j] = NULL;
2013 static void eb_capture_list_clear(struct i915_execbuffer *eb)
2015 memset(eb->capture_lists, 0, sizeof(eb->capture_lists));
2020 static void eb_capture_stage(struct i915_execbuffer *eb)
2024 static void eb_capture_commit(struct i915_execbuffer *eb)
2028 static void eb_capture_release(struct i915_execbuffer *eb)
2032 static void eb_capture_list_clear(struct i915_execbuffer *eb)
2038 static int eb_move_to_gpu(struct i915_execbuffer *eb)
2040 const unsigned int count = eb->buffer_count;
2041 unsigned int i = count;
2045 struct eb_vma *ev = &eb->vma[i];
2046 struct i915_vma *vma = ev->vma;
2047 unsigned int flags = ev->flags;
2048 struct drm_i915_gem_object *obj = vma->obj;
2050 assert_vma_held(vma);
2053 * If the GPU is not _reading_ through the CPU cache, we need
2054 * to make sure that any writes (both previous GPU writes from
2055 * before a change in snooping levels and normal CPU writes)
2056 * caught in that cache are flushed to main memory.
2059 * obj->cache_dirty &&
2060 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
2061 * but gcc's optimiser doesn't handle that as well and emits
2062 * two jumps instead of one. Maybe one day...
2064 * FIXME: There is also sync flushing in set_pages(), which
2065 * serves a different purpose(some of the time at least).
2067 * We should consider:
2069 * 1. Rip out the async flush code.
2071 * 2. Or make the sync flushing use the async clflush path
2072 * using mandatory fences underneath. Currently the below
2073 * async flush happens after we bind the object.
2075 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
2076 if (i915_gem_clflush_object(obj, 0))
2077 flags &= ~EXEC_OBJECT_ASYNC;
2080 /* We only need to await on the first request */
2081 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
2082 err = i915_request_await_object
2083 (eb_find_first_request_added(eb), obj,
2084 flags & EXEC_OBJECT_WRITE);
2087 for_each_batch_add_order(eb, j) {
2090 if (!eb->requests[j])
2093 err = _i915_vma_move_to_active(vma, eb->requests[j],
2095 eb->composite_fence ?
2096 eb->composite_fence :
2097 &eb->requests[j]->fence,
2098 flags | __EXEC_OBJECT_NO_RESERVE);
2102 #ifdef CONFIG_MMU_NOTIFIER
2103 if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) {
2104 read_lock(&eb->i915->mm.notifier_lock);
2107 * count is always at least 1, otherwise __EXEC_USERPTR_USED
2108 * could not have been set
2110 for (i = 0; i < count; i++) {
2111 struct eb_vma *ev = &eb->vma[i];
2112 struct drm_i915_gem_object *obj = ev->vma->obj;
2114 if (!i915_gem_object_is_userptr(obj))
2117 err = i915_gem_object_userptr_submit_done(obj);
2122 read_unlock(&eb->i915->mm.notifier_lock);
2129 /* Unconditionally flush any chipset caches (for streaming writes). */
2130 intel_gt_chipset_flush(eb->gt);
2131 eb_capture_commit(eb);
2136 for_each_batch_create_order(eb, j) {
2137 if (!eb->requests[j])
2140 i915_request_set_error_once(eb->requests[j], err);
2145 static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
2147 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
2150 /* Kernel clipping was a DRI1 misfeature */
2151 if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
2152 I915_EXEC_USE_EXTENSIONS))) {
2153 if (exec->num_cliprects || exec->cliprects_ptr)
2157 if (exec->DR4 == 0xffffffff) {
2158 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
2161 if (exec->DR1 || exec->DR4)
2164 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
2170 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
2175 if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
2176 drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
2180 cs = intel_ring_begin(rq, 4 * 2 + 2);
2184 *cs++ = MI_LOAD_REGISTER_IMM(4);
2185 for (i = 0; i < 4; i++) {
2186 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2190 intel_ring_advance(rq, cs);
2195 static struct i915_vma *
2196 shadow_batch_pin(struct i915_execbuffer *eb,
2197 struct drm_i915_gem_object *obj,
2198 struct i915_address_space *vm,
2201 struct i915_vma *vma;
2204 vma = i915_vma_instance(obj, vm, NULL);
2208 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags | PIN_VALIDATE);
2210 return ERR_PTR(err);
2215 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma)
2218 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2219 * batch" bit. Hence we need to pin secure batches into the global gtt.
2220 * hsw should have this fixed, but bdw mucks it up again. */
2221 if (eb->batch_flags & I915_DISPATCH_SECURE)
2222 return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, PIN_VALIDATE);
2227 static int eb_parse(struct i915_execbuffer *eb)
2229 struct drm_i915_private *i915 = eb->i915;
2230 struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
2231 struct i915_vma *shadow, *trampoline, *batch;
2235 if (!eb_use_cmdparser(eb)) {
2236 batch = eb_dispatch_secure(eb, eb->batches[0]->vma);
2238 return PTR_ERR(batch);
2243 if (intel_context_is_parallel(eb->context))
2246 len = eb->batch_len[0];
2247 if (!CMDPARSER_USES_GGTT(eb->i915)) {
2249 * ppGTT backed shadow buffers must be mapped RO, to prevent
2250 * post-scan tampering
2252 if (!eb->context->vm->has_read_only) {
2254 "Cannot prevent post-scan tampering without RO capable vm\n");
2258 len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2260 if (unlikely(len < eb->batch_len[0])) /* last paranoid check of overflow */
2264 pool = intel_gt_get_buffer_pool(eb->gt, len,
2267 return PTR_ERR(pool);
2268 eb->batch_pool = pool;
2271 err = i915_gem_object_lock(pool->obj, &eb->ww);
2275 shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);
2277 return PTR_ERR(shadow);
2279 intel_gt_buffer_pool_mark_used(pool);
2280 i915_gem_object_set_readonly(shadow->obj);
2281 shadow->private = pool;
2284 if (CMDPARSER_USES_GGTT(eb->i915)) {
2285 trampoline = shadow;
2287 shadow = shadow_batch_pin(eb, pool->obj,
2291 return PTR_ERR(shadow);
2293 shadow->private = pool;
2295 eb->batch_flags |= I915_DISPATCH_SECURE;
2298 batch = eb_dispatch_secure(eb, shadow);
2300 return PTR_ERR(batch);
2302 err = dma_resv_reserve_fences(shadow->obj->base.resv, 1);
2306 err = intel_engine_cmd_parser(eb->context->engine,
2307 eb->batches[0]->vma,
2308 eb->batch_start_offset,
2310 shadow, trampoline);
2314 eb->batches[0] = &eb->vma[eb->buffer_count++];
2315 eb->batches[0]->vma = i915_vma_get(shadow);
2316 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2318 eb->trampoline = trampoline;
2319 eb->batch_start_offset = 0;
2323 if (intel_context_is_parallel(eb->context))
2326 eb->batches[0] = &eb->vma[eb->buffer_count++];
2327 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2328 eb->batches[0]->vma = i915_vma_get(batch);
2333 static int eb_request_submit(struct i915_execbuffer *eb,
2334 struct i915_request *rq,
2335 struct i915_vma *batch,
2340 if (intel_context_nopreempt(rq->context))
2341 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags);
2343 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2344 err = i915_reset_gen7_sol_offsets(rq);
2350 * After we completed waiting for other engines (using HW semaphores)
2351 * then we can signal that this request/batch is ready to run. This
2352 * allows us to determine if the batch is still waiting on the GPU
2353 * or actually running by checking the breadcrumb.
2355 if (rq->context->engine->emit_init_breadcrumb) {
2356 err = rq->context->engine->emit_init_breadcrumb(rq);
2361 err = rq->context->engine->emit_bb_start(rq,
2363 eb->batch_start_offset,
2369 if (eb->trampoline) {
2370 GEM_BUG_ON(intel_context_is_parallel(rq->context));
2371 GEM_BUG_ON(eb->batch_start_offset);
2372 err = rq->context->engine->emit_bb_start(rq,
2373 eb->trampoline->node.start +
2382 static int eb_submit(struct i915_execbuffer *eb)
2387 err = eb_move_to_gpu(eb);
2389 for_each_batch_create_order(eb, i) {
2390 if (!eb->requests[i])
2393 trace_i915_request_queue(eb->requests[i], eb->batch_flags);
2395 err = eb_request_submit(eb, eb->requests[i],
2396 eb->batches[i]->vma,
2403 static int num_vcs_engines(struct drm_i915_private *i915)
2405 return hweight_long(VDBOX_MASK(to_gt(i915)));
2409 * Find one BSD ring to dispatch the corresponding BSD command.
2410 * The engine index is returned.
2413 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2414 struct drm_file *file)
2416 struct drm_i915_file_private *file_priv = file->driver_priv;
2418 /* Check whether the file_priv has already selected one ring. */
2419 if ((int)file_priv->bsd_engine < 0)
2420 file_priv->bsd_engine =
2421 get_random_int() % num_vcs_engines(dev_priv);
2423 return file_priv->bsd_engine;
2426 static const enum intel_engine_id user_ring_map[] = {
2427 [I915_EXEC_DEFAULT] = RCS0,
2428 [I915_EXEC_RENDER] = RCS0,
2429 [I915_EXEC_BLT] = BCS0,
2430 [I915_EXEC_BSD] = VCS0,
2431 [I915_EXEC_VEBOX] = VECS0
2434 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce)
2436 struct intel_ring *ring = ce->ring;
2437 struct intel_timeline *tl = ce->timeline;
2438 struct i915_request *rq;
2441 * Completely unscientific finger-in-the-air estimates for suitable
2442 * maximum user request size (to avoid blocking) and then backoff.
2444 if (intel_ring_update_space(ring) >= PAGE_SIZE)
2448 * Find a request that after waiting upon, there will be at least half
2449 * the ring available. The hysteresis allows us to compete for the
2450 * shared ring and should mean that we sleep less often prior to
2451 * claiming our resources, but not so long that the ring completely
2452 * drains before we can submit our next request.
2454 list_for_each_entry(rq, &tl->requests, link) {
2455 if (rq->ring != ring)
2458 if (__intel_ring_space(rq->postfix,
2459 ring->emit, ring->size) > ring->size / 2)
2462 if (&rq->link == &tl->requests)
2463 return NULL; /* weird, we will check again later for real */
2465 return i915_request_get(rq);
2468 static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce,
2471 struct intel_timeline *tl;
2472 struct i915_request *rq = NULL;
2475 * Take a local wakeref for preparing to dispatch the execbuf as
2476 * we expect to access the hardware fairly frequently in the
2477 * process, and require the engine to be kept awake between accesses.
2478 * Upon dispatch, we acquire another prolonged wakeref that we hold
2479 * until the timeline is idle, which in turn releases the wakeref
2480 * taken on the engine, and the parent device.
2482 tl = intel_context_timeline_lock(ce);
2486 intel_context_enter(ce);
2488 rq = eb_throttle(eb, ce);
2489 intel_context_timeline_unlock(tl);
2492 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2493 long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
2495 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
2497 i915_request_put(rq);
2500 * Error path, cannot use intel_context_timeline_lock as
2501 * that is user interruptable and this clean up step
2504 mutex_lock(&ce->timeline->mutex);
2505 intel_context_exit(ce);
2506 mutex_unlock(&ce->timeline->mutex);
2509 return -EWOULDBLOCK;
2513 i915_request_put(rq);
2519 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
2521 struct intel_context *ce = eb->context, *child;
2525 GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
2527 if (unlikely(intel_context_is_banned(ce)))
2531 * Pinning the contexts may generate requests in order to acquire
2532 * GGTT space, so do this first before we reserve a seqno for
2535 err = intel_context_pin_ww(ce, &eb->ww);
2538 for_each_child(ce, child) {
2539 err = intel_context_pin_ww(child, &eb->ww);
2540 GEM_BUG_ON(err); /* perma-pinned should incr a counter */
2543 for_each_child(ce, child) {
2544 err = eb_pin_timeline(eb, child, throttle);
2549 err = eb_pin_timeline(eb, ce, throttle);
2553 eb->args->flags |= __EXEC_ENGINE_PINNED;
2557 for_each_child(ce, child) {
2559 mutex_lock(&child->timeline->mutex);
2560 intel_context_exit(child);
2561 mutex_unlock(&child->timeline->mutex);
2564 for_each_child(ce, child)
2565 intel_context_unpin(child);
2566 intel_context_unpin(ce);
2570 static void eb_unpin_engine(struct i915_execbuffer *eb)
2572 struct intel_context *ce = eb->context, *child;
2574 if (!(eb->args->flags & __EXEC_ENGINE_PINNED))
2577 eb->args->flags &= ~__EXEC_ENGINE_PINNED;
2579 for_each_child(ce, child) {
2580 mutex_lock(&child->timeline->mutex);
2581 intel_context_exit(child);
2582 mutex_unlock(&child->timeline->mutex);
2584 intel_context_unpin(child);
2587 mutex_lock(&ce->timeline->mutex);
2588 intel_context_exit(ce);
2589 mutex_unlock(&ce->timeline->mutex);
2591 intel_context_unpin(ce);
2595 eb_select_legacy_ring(struct i915_execbuffer *eb)
2597 struct drm_i915_private *i915 = eb->i915;
2598 struct drm_i915_gem_execbuffer2 *args = eb->args;
2599 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2601 if (user_ring_id != I915_EXEC_BSD &&
2602 (args->flags & I915_EXEC_BSD_MASK)) {
2604 "execbuf with non bsd ring but with invalid "
2605 "bsd dispatch flags: %d\n", (int)(args->flags));
2609 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2610 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2612 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2613 bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
2614 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2615 bsd_idx <= I915_EXEC_BSD_RING2) {
2616 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2620 "execbuf with unknown bsd ring: %u\n",
2625 return _VCS(bsd_idx);
2628 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2629 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2634 return user_ring_map[user_ring_id];
2638 eb_select_engine(struct i915_execbuffer *eb)
2640 struct intel_context *ce, *child;
2644 if (i915_gem_context_user_engines(eb->gem_context))
2645 idx = eb->args->flags & I915_EXEC_RING_MASK;
2647 idx = eb_select_legacy_ring(eb);
2649 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2653 if (intel_context_is_parallel(ce)) {
2654 if (eb->buffer_count < ce->parallel.number_children + 1) {
2655 intel_context_put(ce);
2658 if (eb->batch_start_offset || eb->args->batch_len) {
2659 intel_context_put(ce);
2663 eb->num_batches = ce->parallel.number_children + 1;
2665 for_each_child(ce, child)
2666 intel_context_get(child);
2667 intel_gt_pm_get(ce->engine->gt);
2669 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
2670 err = intel_context_alloc_state(ce);
2674 for_each_child(ce, child) {
2675 if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) {
2676 err = intel_context_alloc_state(child);
2683 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2684 * EIO if the GPU is already wedged.
2686 err = intel_gt_terminally_wedged(ce->engine->gt);
2690 if (!i915_vm_tryget(ce->vm)) {
2696 eb->gt = ce->engine->gt;
2699 * Make sure engine pool stays alive even if we call intel_context_put
2700 * during ww handling. The pool is destroyed when last pm reference
2701 * is dropped, which breaks our -EDEADLK handling.
2706 intel_gt_pm_put(ce->engine->gt);
2707 for_each_child(ce, child)
2708 intel_context_put(child);
2709 intel_context_put(ce);
2714 eb_put_engine(struct i915_execbuffer *eb)
2716 struct intel_context *child;
2718 i915_vm_put(eb->context->vm);
2719 intel_gt_pm_put(eb->gt);
2720 for_each_child(eb->context, child)
2721 intel_context_put(child);
2722 intel_context_put(eb->context);
2726 __free_fence_array(struct eb_fence *fences, unsigned int n)
2729 drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
2730 dma_fence_put(fences[n].dma_fence);
2731 dma_fence_chain_free(fences[n].chain_fence);
2737 add_timeline_fence_array(struct i915_execbuffer *eb,
2738 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences)
2740 struct drm_i915_gem_exec_fence __user *user_fences;
2741 u64 __user *user_values;
2746 nfences = timeline_fences->fence_count;
2750 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2751 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2752 if (nfences > min_t(unsigned long,
2753 ULONG_MAX / sizeof(*user_fences),
2754 SIZE_MAX / sizeof(*f)) - eb->num_fences)
2757 user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
2758 if (!access_ok(user_fences, nfences * sizeof(*user_fences)))
2761 user_values = u64_to_user_ptr(timeline_fences->values_ptr);
2762 if (!access_ok(user_values, nfences * sizeof(*user_values)))
2765 f = krealloc(eb->fences,
2766 (eb->num_fences + nfences) * sizeof(*f),
2767 __GFP_NOWARN | GFP_KERNEL);
2772 f += eb->num_fences;
2774 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2775 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2778 struct drm_i915_gem_exec_fence user_fence;
2779 struct drm_syncobj *syncobj;
2780 struct dma_fence *fence = NULL;
2783 if (__copy_from_user(&user_fence,
2785 sizeof(user_fence)))
2788 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2791 if (__get_user(point, user_values++))
2794 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2796 DRM_DEBUG("Invalid syncobj handle provided\n");
2800 fence = drm_syncobj_fence_get(syncobj);
2802 if (!fence && user_fence.flags &&
2803 !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2804 DRM_DEBUG("Syncobj handle has no fence\n");
2805 drm_syncobj_put(syncobj);
2810 err = dma_fence_chain_find_seqno(&fence, point);
2812 if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2813 DRM_DEBUG("Syncobj handle missing requested point %llu\n", point);
2814 dma_fence_put(fence);
2815 drm_syncobj_put(syncobj);
2820 * A point might have been signaled already and
2821 * garbage collected from the timeline. In this case
2822 * just ignore the point and carry on.
2824 if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2825 drm_syncobj_put(syncobj);
2830 * For timeline syncobjs we need to preallocate chains for
2833 if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
2835 * Waiting and signaling the same point (when point !=
2836 * 0) would break the timeline.
2838 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2839 DRM_DEBUG("Trying to wait & signal the same timeline point.\n");
2840 dma_fence_put(fence);
2841 drm_syncobj_put(syncobj);
2845 f->chain_fence = dma_fence_chain_alloc();
2846 if (!f->chain_fence) {
2847 drm_syncobj_put(syncobj);
2848 dma_fence_put(fence);
2852 f->chain_fence = NULL;
2855 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2856 f->dma_fence = fence;
2865 static int add_fence_array(struct i915_execbuffer *eb)
2867 struct drm_i915_gem_execbuffer2 *args = eb->args;
2868 struct drm_i915_gem_exec_fence __user *user;
2869 unsigned long num_fences = args->num_cliprects;
2872 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2878 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2879 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2880 if (num_fences > min_t(unsigned long,
2881 ULONG_MAX / sizeof(*user),
2882 SIZE_MAX / sizeof(*f) - eb->num_fences))
2885 user = u64_to_user_ptr(args->cliprects_ptr);
2886 if (!access_ok(user, num_fences * sizeof(*user)))
2889 f = krealloc(eb->fences,
2890 (eb->num_fences + num_fences) * sizeof(*f),
2891 __GFP_NOWARN | GFP_KERNEL);
2896 f += eb->num_fences;
2897 while (num_fences--) {
2898 struct drm_i915_gem_exec_fence user_fence;
2899 struct drm_syncobj *syncobj;
2900 struct dma_fence *fence = NULL;
2902 if (__copy_from_user(&user_fence, user++, sizeof(user_fence)))
2905 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2908 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2910 DRM_DEBUG("Invalid syncobj handle provided\n");
2914 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2915 fence = drm_syncobj_fence_get(syncobj);
2917 DRM_DEBUG("Syncobj handle has no fence\n");
2918 drm_syncobj_put(syncobj);
2923 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2924 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2926 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2927 f->dma_fence = fence;
2929 f->chain_fence = NULL;
2937 static void put_fence_array(struct eb_fence *fences, int num_fences)
2940 __free_fence_array(fences, num_fences);
2944 await_fence_array(struct i915_execbuffer *eb,
2945 struct i915_request *rq)
2950 for (n = 0; n < eb->num_fences; n++) {
2951 struct drm_syncobj *syncobj;
2954 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
2956 if (!eb->fences[n].dma_fence)
2959 err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence);
2967 static void signal_fence_array(const struct i915_execbuffer *eb,
2968 struct dma_fence * const fence)
2972 for (n = 0; n < eb->num_fences; n++) {
2973 struct drm_syncobj *syncobj;
2976 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
2977 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2980 if (eb->fences[n].chain_fence) {
2981 drm_syncobj_add_point(syncobj,
2982 eb->fences[n].chain_fence,
2984 eb->fences[n].value);
2986 * The chain's ownership is transferred to the
2989 eb->fences[n].chain_fence = NULL;
2991 drm_syncobj_replace_fence(syncobj, fence);
2997 parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
2999 struct i915_execbuffer *eb = data;
3000 struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
3002 if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences)))
3005 return add_timeline_fence_array(eb, &timeline_fences);
3008 static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
3010 struct i915_request *rq, *rn;
3012 list_for_each_entry_safe(rq, rn, &tl->requests, link)
3013 if (rq == end || !i915_request_retire(rq))
3017 static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq,
3018 int err, bool last_parallel)
3020 struct intel_timeline * const tl = i915_request_timeline(rq);
3021 struct i915_sched_attr attr = {};
3022 struct i915_request *prev;
3024 lockdep_assert_held(&tl->mutex);
3025 lockdep_unpin_lock(&tl->mutex, rq->cookie);
3027 trace_i915_request_add(rq);
3029 prev = __i915_request_commit(rq);
3031 /* Check that the context wasn't destroyed before submission */
3032 if (likely(!intel_context_is_closed(eb->context))) {
3033 attr = eb->gem_context->sched;
3035 /* Serialise with context_close via the add_to_timeline */
3036 i915_request_set_error_once(rq, -ENOENT);
3037 __i915_request_skip(rq);
3038 err = -ENOENT; /* override any transient errors */
3041 if (intel_context_is_parallel(eb->context)) {
3043 __i915_request_skip(rq);
3044 set_bit(I915_FENCE_FLAG_SKIP_PARALLEL,
3048 set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL,
3052 __i915_request_queue(rq, &attr);
3054 /* Try to clean up the client's timeline after submitting the request */
3056 retire_requests(tl, prev);
3058 mutex_unlock(&tl->mutex);
3063 static int eb_requests_add(struct i915_execbuffer *eb, int err)
3068 * We iterate in reverse order of creation to release timeline mutexes in
3071 for_each_batch_add_order(eb, i) {
3072 struct i915_request *rq = eb->requests[i];
3076 err |= eb_request_add(eb, rq, err, i == 0);
3082 static const i915_user_extension_fn execbuf_extensions[] = {
3083 [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
3087 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
3088 struct i915_execbuffer *eb)
3090 if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
3093 /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
3094 * have another flag also using it at the same time.
3096 if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
3099 if (args->num_cliprects != 0)
3102 return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
3104 ARRAY_SIZE(execbuf_extensions),
3108 static void eb_requests_get(struct i915_execbuffer *eb)
3112 for_each_batch_create_order(eb, i) {
3113 if (!eb->requests[i])
3116 i915_request_get(eb->requests[i]);
3120 static void eb_requests_put(struct i915_execbuffer *eb)
3124 for_each_batch_create_order(eb, i) {
3125 if (!eb->requests[i])
3128 i915_request_put(eb->requests[i]);
3132 static struct sync_file *
3133 eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd)
3135 struct sync_file *out_fence = NULL;
3136 struct dma_fence_array *fence_array;
3137 struct dma_fence **fences;
3140 GEM_BUG_ON(!intel_context_is_parent(eb->context));
3142 fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL);
3144 return ERR_PTR(-ENOMEM);
3146 for_each_batch_create_order(eb, i) {
3147 fences[i] = &eb->requests[i]->fence;
3148 __set_bit(I915_FENCE_FLAG_COMPOSITE,
3149 &eb->requests[i]->fence.flags);
3152 fence_array = dma_fence_array_create(eb->num_batches,
3154 eb->context->parallel.fence_context,
3155 eb->context->parallel.seqno++,
3159 return ERR_PTR(-ENOMEM);
3162 /* Move ownership to the dma_fence_array created above */
3163 for_each_batch_create_order(eb, i)
3164 dma_fence_get(fences[i]);
3166 if (out_fence_fd != -1) {
3167 out_fence = sync_file_create(&fence_array->base);
3168 /* sync_file now owns fence_arry, drop creation ref */
3169 dma_fence_put(&fence_array->base);
3171 return ERR_PTR(-ENOMEM);
3174 eb->composite_fence = &fence_array->base;
3179 static struct sync_file *
3180 eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq,
3181 struct dma_fence *in_fence, int out_fence_fd)
3183 struct sync_file *out_fence = NULL;
3186 if (unlikely(eb->gem_context->syncobj)) {
3187 struct dma_fence *fence;
3189 fence = drm_syncobj_fence_get(eb->gem_context->syncobj);
3190 err = i915_request_await_dma_fence(rq, fence);
3191 dma_fence_put(fence);
3193 return ERR_PTR(err);
3197 if (eb->args->flags & I915_EXEC_FENCE_SUBMIT)
3198 err = i915_request_await_execution(rq, in_fence);
3200 err = i915_request_await_dma_fence(rq, in_fence);
3202 return ERR_PTR(err);
3206 err = await_fence_array(eb, rq);
3208 return ERR_PTR(err);
3211 if (intel_context_is_parallel(eb->context)) {
3212 out_fence = eb_composite_fence_create(eb, out_fence_fd);
3213 if (IS_ERR(out_fence))
3214 return ERR_PTR(-ENOMEM);
3215 } else if (out_fence_fd != -1) {
3216 out_fence = sync_file_create(&rq->fence);
3218 return ERR_PTR(-ENOMEM);
3224 static struct intel_context *
3225 eb_find_context(struct i915_execbuffer *eb, unsigned int context_number)
3227 struct intel_context *child;
3229 if (likely(context_number == 0))
3232 for_each_child(eb->context, child)
3233 if (!--context_number)
3236 GEM_BUG_ON("Context not found");
3241 static struct sync_file *
3242 eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence,
3245 struct sync_file *out_fence = NULL;
3248 for_each_batch_create_order(eb, i) {
3249 /* Allocate a request for this batch buffer nice and early. */
3250 eb->requests[i] = i915_request_create(eb_find_context(eb, i));
3251 if (IS_ERR(eb->requests[i])) {
3252 out_fence = ERR_CAST(eb->requests[i]);
3253 eb->requests[i] = NULL;
3258 * Only the first request added (committed to backend) has to
3259 * take the in fences into account as all subsequent requests
3260 * will have fences inserted inbetween them.
3262 if (i + 1 == eb->num_batches) {
3263 out_fence = eb_fences_add(eb, eb->requests[i],
3264 in_fence, out_fence_fd);
3265 if (IS_ERR(out_fence))
3270 * Not really on stack, but we don't want to call
3271 * kfree on the batch_snapshot when we put it, so use the
3272 * _onstack interface.
3274 if (eb->batches[i]->vma)
3275 eb->requests[i]->batch_res =
3276 i915_vma_resource_get(eb->batches[i]->vma->resource);
3277 if (eb->batch_pool) {
3278 GEM_BUG_ON(intel_context_is_parallel(eb->context));
3279 intel_gt_buffer_pool_mark_active(eb->batch_pool,
3288 i915_gem_do_execbuffer(struct drm_device *dev,
3289 struct drm_file *file,
3290 struct drm_i915_gem_execbuffer2 *args,
3291 struct drm_i915_gem_exec_object2 *exec)
3293 struct drm_i915_private *i915 = to_i915(dev);
3294 struct i915_execbuffer eb;
3295 struct dma_fence *in_fence = NULL;
3296 struct sync_file *out_fence = NULL;
3297 int out_fence_fd = -1;
3300 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
3301 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
3302 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
3307 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
3308 args->flags |= __EXEC_HAS_RELOC;
3311 eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3312 eb.vma[0].vma = NULL;
3313 eb.batch_pool = NULL;
3315 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
3316 reloc_cache_init(&eb.reloc_cache, eb.i915);
3318 eb.buffer_count = args->buffer_count;
3319 eb.batch_start_offset = args->batch_start_offset;
3320 eb.trampoline = NULL;
3325 eb_capture_list_clear(&eb);
3327 memset(eb.requests, 0, sizeof(struct i915_request *) *
3328 ARRAY_SIZE(eb.requests));
3329 eb.composite_fence = NULL;
3332 if (args->flags & I915_EXEC_SECURE) {
3333 if (GRAPHICS_VER(i915) >= 11)
3336 /* Return -EPERM to trigger fallback code on old binaries. */
3337 if (!HAS_SECURE_BATCHES(i915))
3340 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
3343 eb.batch_flags |= I915_DISPATCH_SECURE;
3345 if (args->flags & I915_EXEC_IS_PINNED)
3346 eb.batch_flags |= I915_DISPATCH_PINNED;
3348 err = parse_execbuf2_extensions(args, &eb);
3352 err = add_fence_array(&eb);
3356 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
3357 if (args->flags & IN_FENCES) {
3358 if ((args->flags & IN_FENCES) == IN_FENCES)
3361 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
3369 if (args->flags & I915_EXEC_FENCE_OUT) {
3370 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3371 if (out_fence_fd < 0) {
3377 err = eb_create(&eb);
3381 GEM_BUG_ON(!eb.lut_size);
3383 err = eb_select_context(&eb);
3387 err = eb_select_engine(&eb);
3391 err = eb_lookup_vmas(&eb);
3393 eb_release_vmas(&eb, true);
3397 i915_gem_ww_ctx_init(&eb.ww, true);
3399 err = eb_relocate_parse(&eb);
3402 * If the user expects the execobject.offset and
3403 * reloc.presumed_offset to be an exact match,
3404 * as for using NO_RELOC, then we cannot update
3405 * the execobject.offset until we have completed
3408 args->flags &= ~__EXEC_HAS_RELOC;
3412 ww_acquire_done(&eb.ww.ctx);
3413 eb_capture_stage(&eb);
3415 out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
3416 if (IS_ERR(out_fence)) {
3417 err = PTR_ERR(out_fence);
3425 err = eb_submit(&eb);
3428 eb_requests_get(&eb);
3429 err = eb_requests_add(&eb, err);
3432 signal_fence_array(&eb, eb.composite_fence ?
3433 eb.composite_fence :
3434 &eb.requests[0]->fence);
3438 fd_install(out_fence_fd, out_fence->file);
3439 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3440 args->rsvd2 |= (u64)out_fence_fd << 32;
3443 fput(out_fence->file);
3447 if (unlikely(eb.gem_context->syncobj)) {
3448 drm_syncobj_replace_fence(eb.gem_context->syncobj,
3449 eb.composite_fence ?
3450 eb.composite_fence :
3451 &eb.requests[0]->fence);
3454 if (!out_fence && eb.composite_fence)
3455 dma_fence_put(eb.composite_fence);
3457 eb_requests_put(&eb);
3460 eb_release_vmas(&eb, true);
3461 WARN_ON(err == -EDEADLK);
3462 i915_gem_ww_ctx_fini(&eb.ww);
3465 intel_gt_buffer_pool_put(eb.batch_pool);
3469 i915_gem_context_put(eb.gem_context);
3473 if (out_fence_fd != -1)
3474 put_unused_fd(out_fence_fd);
3476 dma_fence_put(in_fence);
3478 put_fence_array(eb.fences, eb.num_fences);
3482 static size_t eb_element_size(void)
3484 return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma);
3487 static bool check_buffer_count(size_t count)
3489 const size_t sz = eb_element_size();
3492 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
3493 * array size (see eb_create()). Otherwise, we can accept an array as
3494 * large as can be addressed (though use large arrays at your peril)!
3497 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
3501 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3502 struct drm_file *file)
3504 struct drm_i915_private *i915 = to_i915(dev);
3505 struct drm_i915_gem_execbuffer2 *args = data;
3506 struct drm_i915_gem_exec_object2 *exec2_list;
3507 const size_t count = args->buffer_count;
3510 if (!check_buffer_count(count)) {
3511 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3515 err = i915_gem_check_execbuffer(args);
3519 /* Allocate extra slots for use by the command parser */
3520 exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3521 __GFP_NOWARN | GFP_KERNEL);
3522 if (exec2_list == NULL) {
3523 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3527 if (copy_from_user(exec2_list,
3528 u64_to_user_ptr(args->buffers_ptr),
3529 sizeof(*exec2_list) * count)) {
3530 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3535 err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
3538 * Now that we have begun execution of the batchbuffer, we ignore
3539 * any new error after this point. Also given that we have already
3540 * updated the associated relocations, we try to write out the current
3541 * object locations irrespective of any error.
3543 if (args->flags & __EXEC_HAS_RELOC) {
3544 struct drm_i915_gem_exec_object2 __user *user_exec_list =
3545 u64_to_user_ptr(args->buffers_ptr);
3548 /* Copy the new buffer offsets back to the user's exec list. */
3550 * Note: count * sizeof(*user_exec_list) does not overflow,
3551 * because we checked 'count' in check_buffer_count().
3553 * And this range already got effectively checked earlier
3554 * when we did the "copy_from_user()" above.
3556 if (!user_write_access_begin(user_exec_list,
3557 count * sizeof(*user_exec_list)))
3560 for (i = 0; i < args->buffer_count; i++) {
3561 if (!(exec2_list[i].offset & UPDATE))
3564 exec2_list[i].offset =
3565 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3566 unsafe_put_user(exec2_list[i].offset,
3567 &user_exec_list[i].offset,
3571 user_write_access_end();
3575 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;