2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
35 #include <drm/display/drm_hdcp_helper.h>
36 #include <drm/display/drm_hdmi_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_edid.h>
41 #include <drm/intel_lpe_audio.h>
43 #include "i915_debugfs.h"
45 #include "intel_atomic.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
49 #include "intel_display_types.h"
51 #include "intel_gmbus.h"
52 #include "intel_hdcp.h"
53 #include "intel_hdmi.h"
54 #include "intel_lspcon.h"
55 #include "intel_panel.h"
56 #include "intel_snps_phy.h"
58 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
60 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
64 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
66 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
69 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
71 drm_WARN(&dev_priv->drm,
72 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
73 "HDMI port enabled, expecting disabled\n");
77 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
78 enum transcoder cpu_transcoder)
80 drm_WARN(&dev_priv->drm,
81 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
82 TRANS_DDI_FUNC_ENABLE,
83 "HDMI transcoder function enabled, expecting disabled\n");
86 static u32 g4x_infoframe_index(unsigned int type)
89 case HDMI_PACKET_TYPE_GAMUT_METADATA:
90 return VIDEO_DIP_SELECT_GAMUT;
91 case HDMI_INFOFRAME_TYPE_AVI:
92 return VIDEO_DIP_SELECT_AVI;
93 case HDMI_INFOFRAME_TYPE_SPD:
94 return VIDEO_DIP_SELECT_SPD;
95 case HDMI_INFOFRAME_TYPE_VENDOR:
96 return VIDEO_DIP_SELECT_VENDOR;
103 static u32 g4x_infoframe_enable(unsigned int type)
106 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
107 return VIDEO_DIP_ENABLE_GCP;
108 case HDMI_PACKET_TYPE_GAMUT_METADATA:
109 return VIDEO_DIP_ENABLE_GAMUT;
112 case HDMI_INFOFRAME_TYPE_AVI:
113 return VIDEO_DIP_ENABLE_AVI;
114 case HDMI_INFOFRAME_TYPE_SPD:
115 return VIDEO_DIP_ENABLE_SPD;
116 case HDMI_INFOFRAME_TYPE_VENDOR:
117 return VIDEO_DIP_ENABLE_VENDOR;
118 case HDMI_INFOFRAME_TYPE_DRM:
126 static u32 hsw_infoframe_enable(unsigned int type)
129 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
130 return VIDEO_DIP_ENABLE_GCP_HSW;
131 case HDMI_PACKET_TYPE_GAMUT_METADATA:
132 return VIDEO_DIP_ENABLE_GMP_HSW;
134 return VIDEO_DIP_ENABLE_VSC_HSW;
136 return VDIP_ENABLE_PPS;
137 case HDMI_INFOFRAME_TYPE_AVI:
138 return VIDEO_DIP_ENABLE_AVI_HSW;
139 case HDMI_INFOFRAME_TYPE_SPD:
140 return VIDEO_DIP_ENABLE_SPD_HSW;
141 case HDMI_INFOFRAME_TYPE_VENDOR:
142 return VIDEO_DIP_ENABLE_VS_HSW;
143 case HDMI_INFOFRAME_TYPE_DRM:
144 return VIDEO_DIP_ENABLE_DRM_GLK;
152 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
153 enum transcoder cpu_transcoder,
158 case HDMI_PACKET_TYPE_GAMUT_METADATA:
159 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
161 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
163 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
164 case HDMI_INFOFRAME_TYPE_AVI:
165 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_SPD:
167 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_VENDOR:
169 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
170 case HDMI_INFOFRAME_TYPE_DRM:
171 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
174 return INVALID_MMIO_REG;
178 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
183 return VIDEO_DIP_VSC_DATA_SIZE;
185 return VIDEO_DIP_PPS_DATA_SIZE;
186 case HDMI_PACKET_TYPE_GAMUT_METADATA:
187 if (DISPLAY_VER(dev_priv) >= 11)
188 return VIDEO_DIP_GMP_DATA_SIZE;
190 return VIDEO_DIP_DATA_SIZE;
192 return VIDEO_DIP_DATA_SIZE;
196 static void g4x_write_infoframe(struct intel_encoder *encoder,
197 const struct intel_crtc_state *crtc_state,
199 const void *frame, ssize_t len)
201 const u32 *data = frame;
202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
203 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
206 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
207 "Writing DIP with CTL reg disabled\n");
209 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
210 val |= g4x_infoframe_index(type);
212 val &= ~g4x_infoframe_enable(type);
214 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
216 for (i = 0; i < len; i += 4) {
217 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
220 /* Write every possible data byte to force correct ECC calculation. */
221 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
222 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
224 val |= g4x_infoframe_enable(type);
225 val &= ~VIDEO_DIP_FREQ_MASK;
226 val |= VIDEO_DIP_FREQ_VSYNC;
228 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
229 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
232 static void g4x_read_infoframe(struct intel_encoder *encoder,
233 const struct intel_crtc_state *crtc_state,
235 void *frame, ssize_t len)
237 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
238 u32 val, *data = frame;
241 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
243 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
244 val |= g4x_infoframe_index(type);
246 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
248 for (i = 0; i < len; i += 4)
249 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
252 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
253 const struct intel_crtc_state *pipe_config)
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
256 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
258 if ((val & VIDEO_DIP_ENABLE) == 0)
261 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
264 return val & (VIDEO_DIP_ENABLE_AVI |
265 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
268 static void ibx_write_infoframe(struct intel_encoder *encoder,
269 const struct intel_crtc_state *crtc_state,
271 const void *frame, ssize_t len)
273 const u32 *data = frame;
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
276 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
277 u32 val = intel_de_read(dev_priv, reg);
280 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
281 "Writing DIP with CTL reg disabled\n");
283 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
284 val |= g4x_infoframe_index(type);
286 val &= ~g4x_infoframe_enable(type);
288 intel_de_write(dev_priv, reg, val);
290 for (i = 0; i < len; i += 4) {
291 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
295 /* Write every possible data byte to force correct ECC calculation. */
296 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
297 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
299 val |= g4x_infoframe_enable(type);
300 val &= ~VIDEO_DIP_FREQ_MASK;
301 val |= VIDEO_DIP_FREQ_VSYNC;
303 intel_de_write(dev_priv, reg, val);
304 intel_de_posting_read(dev_priv, reg);
307 static void ibx_read_infoframe(struct intel_encoder *encoder,
308 const struct intel_crtc_state *crtc_state,
310 void *frame, ssize_t len)
312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
314 u32 val, *data = frame;
317 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
322 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
324 for (i = 0; i < len; i += 4)
325 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
328 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
329 const struct intel_crtc_state *pipe_config)
331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
332 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
333 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
334 u32 val = intel_de_read(dev_priv, reg);
336 if ((val & VIDEO_DIP_ENABLE) == 0)
339 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
342 return val & (VIDEO_DIP_ENABLE_AVI |
343 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
344 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
347 static void cpt_write_infoframe(struct intel_encoder *encoder,
348 const struct intel_crtc_state *crtc_state,
350 const void *frame, ssize_t len)
352 const u32 *data = frame;
353 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
354 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
355 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
356 u32 val = intel_de_read(dev_priv, reg);
359 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
360 "Writing DIP with CTL reg disabled\n");
362 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
363 val |= g4x_infoframe_index(type);
365 /* The DIP control register spec says that we need to update the AVI
366 * infoframe without clearing its enable bit */
367 if (type != HDMI_INFOFRAME_TYPE_AVI)
368 val &= ~g4x_infoframe_enable(type);
370 intel_de_write(dev_priv, reg, val);
372 for (i = 0; i < len; i += 4) {
373 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
377 /* Write every possible data byte to force correct ECC calculation. */
378 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
379 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
381 val |= g4x_infoframe_enable(type);
382 val &= ~VIDEO_DIP_FREQ_MASK;
383 val |= VIDEO_DIP_FREQ_VSYNC;
385 intel_de_write(dev_priv, reg, val);
386 intel_de_posting_read(dev_priv, reg);
389 static void cpt_read_infoframe(struct intel_encoder *encoder,
390 const struct intel_crtc_state *crtc_state,
392 void *frame, ssize_t len)
394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
396 u32 val, *data = frame;
399 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
401 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
402 val |= g4x_infoframe_index(type);
404 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
406 for (i = 0; i < len; i += 4)
407 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
410 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
411 const struct intel_crtc_state *pipe_config)
413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
414 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
415 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
417 if ((val & VIDEO_DIP_ENABLE) == 0)
420 return val & (VIDEO_DIP_ENABLE_AVI |
421 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
422 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
425 static void vlv_write_infoframe(struct intel_encoder *encoder,
426 const struct intel_crtc_state *crtc_state,
428 const void *frame, ssize_t len)
430 const u32 *data = frame;
431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
432 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
433 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
434 u32 val = intel_de_read(dev_priv, reg);
437 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
438 "Writing DIP with CTL reg disabled\n");
440 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
441 val |= g4x_infoframe_index(type);
443 val &= ~g4x_infoframe_enable(type);
445 intel_de_write(dev_priv, reg, val);
447 for (i = 0; i < len; i += 4) {
448 intel_de_write(dev_priv,
449 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
452 /* Write every possible data byte to force correct ECC calculation. */
453 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
454 intel_de_write(dev_priv,
455 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
457 val |= g4x_infoframe_enable(type);
458 val &= ~VIDEO_DIP_FREQ_MASK;
459 val |= VIDEO_DIP_FREQ_VSYNC;
461 intel_de_write(dev_priv, reg, val);
462 intel_de_posting_read(dev_priv, reg);
465 static void vlv_read_infoframe(struct intel_encoder *encoder,
466 const struct intel_crtc_state *crtc_state,
468 void *frame, ssize_t len)
470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
472 u32 val, *data = frame;
475 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
477 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
478 val |= g4x_infoframe_index(type);
480 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
482 for (i = 0; i < len; i += 4)
483 *data++ = intel_de_read(dev_priv,
484 VLV_TVIDEO_DIP_DATA(crtc->pipe));
487 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
488 const struct intel_crtc_state *pipe_config)
490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
491 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
492 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
494 if ((val & VIDEO_DIP_ENABLE) == 0)
497 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
500 return val & (VIDEO_DIP_ENABLE_AVI |
501 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
502 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
505 void hsw_write_infoframe(struct intel_encoder *encoder,
506 const struct intel_crtc_state *crtc_state,
508 const void *frame, ssize_t len)
510 const u32 *data = frame;
511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
513 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
516 u32 val = intel_de_read(dev_priv, ctl_reg);
518 data_size = hsw_dip_data_size(dev_priv, type);
520 drm_WARN_ON(&dev_priv->drm, len > data_size);
522 val &= ~hsw_infoframe_enable(type);
523 intel_de_write(dev_priv, ctl_reg, val);
525 for (i = 0; i < len; i += 4) {
526 intel_de_write(dev_priv,
527 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
531 /* Write every possible data byte to force correct ECC calculation. */
532 for (; i < data_size; i += 4)
533 intel_de_write(dev_priv,
534 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
538 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
542 val |= hsw_infoframe_enable(type);
543 intel_de_write(dev_priv, ctl_reg, val);
544 intel_de_posting_read(dev_priv, ctl_reg);
547 void hsw_read_infoframe(struct intel_encoder *encoder,
548 const struct intel_crtc_state *crtc_state,
549 unsigned int type, void *frame, ssize_t len)
551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
556 for (i = 0; i < len; i += 4)
557 *data++ = intel_de_read(dev_priv,
558 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
561 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
562 const struct intel_crtc_state *pipe_config)
564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
565 u32 val = intel_de_read(dev_priv,
566 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
569 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
570 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
571 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
573 if (DISPLAY_VER(dev_priv) >= 10)
574 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
579 static const u8 infoframe_type_to_idx[] = {
580 HDMI_PACKET_TYPE_GENERAL_CONTROL,
581 HDMI_PACKET_TYPE_GAMUT_METADATA,
583 HDMI_INFOFRAME_TYPE_AVI,
584 HDMI_INFOFRAME_TYPE_SPD,
585 HDMI_INFOFRAME_TYPE_VENDOR,
586 HDMI_INFOFRAME_TYPE_DRM,
589 u32 intel_hdmi_infoframe_enable(unsigned int type)
593 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
594 if (infoframe_type_to_idx[i] == type)
601 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
602 const struct intel_crtc_state *crtc_state)
604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
605 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
609 val = dig_port->infoframes_enabled(encoder, crtc_state);
611 /* map from hardware bits to dip idx */
612 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
613 unsigned int type = infoframe_type_to_idx[i];
615 if (HAS_DDI(dev_priv)) {
616 if (val & hsw_infoframe_enable(type))
619 if (val & g4x_infoframe_enable(type))
628 * The data we write to the DIP data buffer registers is 1 byte bigger than the
629 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
630 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
631 * used for both technologies.
633 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
634 * DW1: DB3 | DB2 | DB1 | DB0
635 * DW2: DB7 | DB6 | DB5 | DB4
638 * (HB is Header Byte, DB is Data Byte)
640 * The hdmi pack() functions don't know about that hardware specific hole so we
641 * trick them by giving an offset into the buffer and moving back the header
644 static void intel_write_infoframe(struct intel_encoder *encoder,
645 const struct intel_crtc_state *crtc_state,
646 enum hdmi_infoframe_type type,
647 const union hdmi_infoframe *frame)
649 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
650 u8 buffer[VIDEO_DIP_DATA_SIZE];
653 if ((crtc_state->infoframes.enable &
654 intel_hdmi_infoframe_enable(type)) == 0)
657 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
660 /* see comment above for the reason for this offset */
661 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
662 if (drm_WARN_ON(encoder->base.dev, len < 0))
665 /* Insert the 'hole' (see big comment above) at position 3 */
666 memmove(&buffer[0], &buffer[1], 3);
670 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
673 void intel_read_infoframe(struct intel_encoder *encoder,
674 const struct intel_crtc_state *crtc_state,
675 enum hdmi_infoframe_type type,
676 union hdmi_infoframe *frame)
678 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
679 u8 buffer[VIDEO_DIP_DATA_SIZE];
682 if ((crtc_state->infoframes.enable &
683 intel_hdmi_infoframe_enable(type)) == 0)
686 dig_port->read_infoframe(encoder, crtc_state,
687 type, buffer, sizeof(buffer));
689 /* Fill the 'hole' (see big comment above) at position 3 */
690 memmove(&buffer[1], &buffer[0], 3);
692 /* see comment above for the reason for this offset */
693 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
695 drm_dbg_kms(encoder->base.dev,
696 "Failed to unpack infoframe type 0x%02x\n", type);
700 if (frame->any.type != type)
701 drm_dbg_kms(encoder->base.dev,
702 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
703 frame->any.type, type);
707 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
708 struct intel_crtc_state *crtc_state,
709 struct drm_connector_state *conn_state)
711 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
712 const struct drm_display_mode *adjusted_mode =
713 &crtc_state->hw.adjusted_mode;
714 struct drm_connector *connector = conn_state->connector;
717 if (!crtc_state->has_infoframe)
720 crtc_state->infoframes.enable |=
721 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
723 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
728 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
729 frame->colorspace = HDMI_COLORSPACE_YUV420;
730 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
731 frame->colorspace = HDMI_COLORSPACE_YUV444;
733 frame->colorspace = HDMI_COLORSPACE_RGB;
735 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
737 /* nonsense combination */
738 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
739 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
741 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
742 drm_hdmi_avi_infoframe_quant_range(frame, connector,
744 crtc_state->limited_color_range ?
745 HDMI_QUANTIZATION_RANGE_LIMITED :
746 HDMI_QUANTIZATION_RANGE_FULL);
748 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
749 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
752 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
754 /* TODO: handle pixel repetition for YCBCR420 outputs */
756 ret = hdmi_avi_infoframe_check(frame);
757 if (drm_WARN_ON(encoder->base.dev, ret))
764 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
765 struct intel_crtc_state *crtc_state,
766 struct drm_connector_state *conn_state)
768 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
771 if (!crtc_state->has_infoframe)
774 crtc_state->infoframes.enable |=
775 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
777 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
778 if (drm_WARN_ON(encoder->base.dev, ret))
781 frame->sdi = HDMI_SPD_SDI_PC;
783 ret = hdmi_spd_infoframe_check(frame);
784 if (drm_WARN_ON(encoder->base.dev, ret))
791 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
792 struct intel_crtc_state *crtc_state,
793 struct drm_connector_state *conn_state)
795 struct hdmi_vendor_infoframe *frame =
796 &crtc_state->infoframes.hdmi.vendor.hdmi;
797 const struct drm_display_info *info =
798 &conn_state->connector->display_info;
801 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
804 crtc_state->infoframes.enable |=
805 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
807 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
808 conn_state->connector,
809 &crtc_state->hw.adjusted_mode);
810 if (drm_WARN_ON(encoder->base.dev, ret))
813 ret = hdmi_vendor_infoframe_check(frame);
814 if (drm_WARN_ON(encoder->base.dev, ret))
821 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
822 struct intel_crtc_state *crtc_state,
823 struct drm_connector_state *conn_state)
825 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
829 if (DISPLAY_VER(dev_priv) < 10)
832 if (!crtc_state->has_infoframe)
835 if (!conn_state->hdr_output_metadata)
838 crtc_state->infoframes.enable |=
839 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
841 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
843 drm_dbg_kms(&dev_priv->drm,
844 "couldn't set HDR metadata in infoframe\n");
848 ret = hdmi_drm_infoframe_check(frame);
849 if (drm_WARN_ON(&dev_priv->drm, ret))
855 static void g4x_set_infoframes(struct intel_encoder *encoder,
857 const struct intel_crtc_state *crtc_state,
858 const struct drm_connector_state *conn_state)
860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
861 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
862 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
863 i915_reg_t reg = VIDEO_DIP_CTL;
864 u32 val = intel_de_read(dev_priv, reg);
865 u32 port = VIDEO_DIP_PORT(encoder->port);
867 assert_hdmi_port_disabled(intel_hdmi);
869 /* If the registers were not initialized yet, they might be zeroes,
870 * which means we're selecting the AVI DIP and we're setting its
871 * frequency to once. This seems to really confuse the HW and make
872 * things stop working (the register spec says the AVI always needs to
873 * be sent every VSync). So here we avoid writing to the register more
874 * than we need and also explicitly select the AVI DIP and explicitly
875 * set its frequency to every VSync. Avoiding to write it twice seems to
876 * be enough to solve the problem, but being defensive shouldn't hurt us
878 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
881 if (!(val & VIDEO_DIP_ENABLE))
883 if (port != (val & VIDEO_DIP_PORT_MASK)) {
884 drm_dbg_kms(&dev_priv->drm,
885 "video DIP still enabled on port %c\n",
886 (val & VIDEO_DIP_PORT_MASK) >> 29);
889 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
890 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
891 intel_de_write(dev_priv, reg, val);
892 intel_de_posting_read(dev_priv, reg);
896 if (port != (val & VIDEO_DIP_PORT_MASK)) {
897 if (val & VIDEO_DIP_ENABLE) {
898 drm_dbg_kms(&dev_priv->drm,
899 "video DIP already enabled on port %c\n",
900 (val & VIDEO_DIP_PORT_MASK) >> 29);
903 val &= ~VIDEO_DIP_PORT_MASK;
907 val |= VIDEO_DIP_ENABLE;
908 val &= ~(VIDEO_DIP_ENABLE_AVI |
909 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
911 intel_de_write(dev_priv, reg, val);
912 intel_de_posting_read(dev_priv, reg);
914 intel_write_infoframe(encoder, crtc_state,
915 HDMI_INFOFRAME_TYPE_AVI,
916 &crtc_state->infoframes.avi);
917 intel_write_infoframe(encoder, crtc_state,
918 HDMI_INFOFRAME_TYPE_SPD,
919 &crtc_state->infoframes.spd);
920 intel_write_infoframe(encoder, crtc_state,
921 HDMI_INFOFRAME_TYPE_VENDOR,
922 &crtc_state->infoframes.hdmi);
926 * Determine if default_phase=1 can be indicated in the GCP infoframe.
928 * From HDMI specification 1.4a:
929 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
930 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
931 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
932 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
935 static bool gcp_default_phase_possible(int pipe_bpp,
936 const struct drm_display_mode *mode)
938 unsigned int pixels_per_group;
942 /* 4 pixels in 5 clocks */
943 pixels_per_group = 4;
946 /* 2 pixels in 3 clocks */
947 pixels_per_group = 2;
950 /* 1 pixel in 2 clocks */
951 pixels_per_group = 1;
954 /* phase information not relevant for 8bpc */
958 return mode->crtc_hdisplay % pixels_per_group == 0 &&
959 mode->crtc_htotal % pixels_per_group == 0 &&
960 mode->crtc_hblank_start % pixels_per_group == 0 &&
961 mode->crtc_hblank_end % pixels_per_group == 0 &&
962 mode->crtc_hsync_start % pixels_per_group == 0 &&
963 mode->crtc_hsync_end % pixels_per_group == 0 &&
964 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
965 mode->crtc_htotal/2 % pixels_per_group == 0);
968 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
969 const struct intel_crtc_state *crtc_state,
970 const struct drm_connector_state *conn_state)
972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
973 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
976 if ((crtc_state->infoframes.enable &
977 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
980 if (HAS_DDI(dev_priv))
981 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
982 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
983 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
984 else if (HAS_PCH_SPLIT(dev_priv))
985 reg = TVIDEO_DIP_GCP(crtc->pipe);
989 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
994 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
995 struct intel_crtc_state *crtc_state)
997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1001 if ((crtc_state->infoframes.enable &
1002 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1005 if (HAS_DDI(dev_priv))
1006 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1007 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1008 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1009 else if (HAS_PCH_SPLIT(dev_priv))
1010 reg = TVIDEO_DIP_GCP(crtc->pipe);
1014 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1017 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1018 struct intel_crtc_state *crtc_state,
1019 struct drm_connector_state *conn_state)
1021 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1023 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1026 crtc_state->infoframes.enable |=
1027 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1029 /* Indicate color indication for deep color mode */
1030 if (crtc_state->pipe_bpp > 24)
1031 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1033 /* Enable default_phase whenever the display mode is suitably aligned */
1034 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1035 &crtc_state->hw.adjusted_mode))
1036 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1039 static void ibx_set_infoframes(struct intel_encoder *encoder,
1041 const struct intel_crtc_state *crtc_state,
1042 const struct drm_connector_state *conn_state)
1044 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1045 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1046 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1047 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1048 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1049 u32 val = intel_de_read(dev_priv, reg);
1050 u32 port = VIDEO_DIP_PORT(encoder->port);
1052 assert_hdmi_port_disabled(intel_hdmi);
1054 /* See the big comment in g4x_set_infoframes() */
1055 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1058 if (!(val & VIDEO_DIP_ENABLE))
1060 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1061 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1062 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1063 intel_de_write(dev_priv, reg, val);
1064 intel_de_posting_read(dev_priv, reg);
1068 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1069 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1070 "DIP already enabled on port %c\n",
1071 (val & VIDEO_DIP_PORT_MASK) >> 29);
1072 val &= ~VIDEO_DIP_PORT_MASK;
1076 val |= VIDEO_DIP_ENABLE;
1077 val &= ~(VIDEO_DIP_ENABLE_AVI |
1078 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1079 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1081 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1082 val |= VIDEO_DIP_ENABLE_GCP;
1084 intel_de_write(dev_priv, reg, val);
1085 intel_de_posting_read(dev_priv, reg);
1087 intel_write_infoframe(encoder, crtc_state,
1088 HDMI_INFOFRAME_TYPE_AVI,
1089 &crtc_state->infoframes.avi);
1090 intel_write_infoframe(encoder, crtc_state,
1091 HDMI_INFOFRAME_TYPE_SPD,
1092 &crtc_state->infoframes.spd);
1093 intel_write_infoframe(encoder, crtc_state,
1094 HDMI_INFOFRAME_TYPE_VENDOR,
1095 &crtc_state->infoframes.hdmi);
1098 static void cpt_set_infoframes(struct intel_encoder *encoder,
1100 const struct intel_crtc_state *crtc_state,
1101 const struct drm_connector_state *conn_state)
1103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1104 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1105 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1106 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1107 u32 val = intel_de_read(dev_priv, reg);
1109 assert_hdmi_port_disabled(intel_hdmi);
1111 /* See the big comment in g4x_set_infoframes() */
1112 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1115 if (!(val & VIDEO_DIP_ENABLE))
1117 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1118 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1119 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1120 intel_de_write(dev_priv, reg, val);
1121 intel_de_posting_read(dev_priv, reg);
1125 /* Set both together, unset both together: see the spec. */
1126 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1127 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1128 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1130 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1131 val |= VIDEO_DIP_ENABLE_GCP;
1133 intel_de_write(dev_priv, reg, val);
1134 intel_de_posting_read(dev_priv, reg);
1136 intel_write_infoframe(encoder, crtc_state,
1137 HDMI_INFOFRAME_TYPE_AVI,
1138 &crtc_state->infoframes.avi);
1139 intel_write_infoframe(encoder, crtc_state,
1140 HDMI_INFOFRAME_TYPE_SPD,
1141 &crtc_state->infoframes.spd);
1142 intel_write_infoframe(encoder, crtc_state,
1143 HDMI_INFOFRAME_TYPE_VENDOR,
1144 &crtc_state->infoframes.hdmi);
1147 static void vlv_set_infoframes(struct intel_encoder *encoder,
1149 const struct intel_crtc_state *crtc_state,
1150 const struct drm_connector_state *conn_state)
1152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1153 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1154 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1155 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1156 u32 val = intel_de_read(dev_priv, reg);
1157 u32 port = VIDEO_DIP_PORT(encoder->port);
1159 assert_hdmi_port_disabled(intel_hdmi);
1161 /* See the big comment in g4x_set_infoframes() */
1162 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1165 if (!(val & VIDEO_DIP_ENABLE))
1167 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1168 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1169 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1170 intel_de_write(dev_priv, reg, val);
1171 intel_de_posting_read(dev_priv, reg);
1175 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1176 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1177 "DIP already enabled on port %c\n",
1178 (val & VIDEO_DIP_PORT_MASK) >> 29);
1179 val &= ~VIDEO_DIP_PORT_MASK;
1183 val |= VIDEO_DIP_ENABLE;
1184 val &= ~(VIDEO_DIP_ENABLE_AVI |
1185 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1186 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1188 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1189 val |= VIDEO_DIP_ENABLE_GCP;
1191 intel_de_write(dev_priv, reg, val);
1192 intel_de_posting_read(dev_priv, reg);
1194 intel_write_infoframe(encoder, crtc_state,
1195 HDMI_INFOFRAME_TYPE_AVI,
1196 &crtc_state->infoframes.avi);
1197 intel_write_infoframe(encoder, crtc_state,
1198 HDMI_INFOFRAME_TYPE_SPD,
1199 &crtc_state->infoframes.spd);
1200 intel_write_infoframe(encoder, crtc_state,
1201 HDMI_INFOFRAME_TYPE_VENDOR,
1202 &crtc_state->infoframes.hdmi);
1205 static void hsw_set_infoframes(struct intel_encoder *encoder,
1207 const struct intel_crtc_state *crtc_state,
1208 const struct drm_connector_state *conn_state)
1210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1211 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1212 u32 val = intel_de_read(dev_priv, reg);
1214 assert_hdmi_transcoder_func_disabled(dev_priv,
1215 crtc_state->cpu_transcoder);
1217 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1218 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1219 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1220 VIDEO_DIP_ENABLE_DRM_GLK);
1223 intel_de_write(dev_priv, reg, val);
1224 intel_de_posting_read(dev_priv, reg);
1228 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1229 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1231 intel_de_write(dev_priv, reg, val);
1232 intel_de_posting_read(dev_priv, reg);
1234 intel_write_infoframe(encoder, crtc_state,
1235 HDMI_INFOFRAME_TYPE_AVI,
1236 &crtc_state->infoframes.avi);
1237 intel_write_infoframe(encoder, crtc_state,
1238 HDMI_INFOFRAME_TYPE_SPD,
1239 &crtc_state->infoframes.spd);
1240 intel_write_infoframe(encoder, crtc_state,
1241 HDMI_INFOFRAME_TYPE_VENDOR,
1242 &crtc_state->infoframes.hdmi);
1243 intel_write_infoframe(encoder, crtc_state,
1244 HDMI_INFOFRAME_TYPE_DRM,
1245 &crtc_state->infoframes.drm);
1248 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1250 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1251 struct i2c_adapter *adapter;
1253 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1256 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1258 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1259 enable ? "Enabling" : "Disabling");
1261 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1264 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1265 unsigned int offset, void *buffer, size_t size)
1267 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1268 struct intel_hdmi *hdmi = &dig_port->hdmi;
1269 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1272 u8 start = offset & 0xff;
1273 struct i2c_msg msgs[] = {
1275 .addr = DRM_HDCP_DDC_ADDR,
1281 .addr = DRM_HDCP_DDC_ADDR,
1287 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1288 if (ret == ARRAY_SIZE(msgs))
1290 return ret >= 0 ? -EIO : ret;
1293 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1294 unsigned int offset, void *buffer, size_t size)
1296 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1297 struct intel_hdmi *hdmi = &dig_port->hdmi;
1298 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1304 write_buf = kzalloc(size + 1, GFP_KERNEL);
1308 write_buf[0] = offset & 0xff;
1309 memcpy(&write_buf[1], buffer, size);
1311 msg.addr = DRM_HDCP_DDC_ADDR;
1314 msg.buf = write_buf;
1316 ret = i2c_transfer(adapter, &msg, 1);
1327 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1330 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1331 struct intel_hdmi *hdmi = &dig_port->hdmi;
1332 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1336 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1339 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1344 ret = intel_gmbus_output_aksv(adapter);
1346 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1352 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1355 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1358 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1361 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1367 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1370 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1373 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1374 bstatus, DRM_HDCP_BSTATUS_LEN);
1376 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1382 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1383 bool *repeater_present)
1385 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1389 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1391 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1395 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1400 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1403 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1406 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1407 ri_prime, DRM_HDCP_RI_LEN);
1409 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1415 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1418 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1422 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1424 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1428 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1433 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1434 int num_downstream, u8 *ksv_fifo)
1436 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1438 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1439 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1441 drm_dbg_kms(&i915->drm,
1442 "Read ksv fifo over DDC failed (%d)\n", ret);
1449 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1452 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1455 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1458 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1459 part, DRM_HDCP_V_PRIME_PART_LEN);
1461 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1466 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1467 enum transcoder cpu_transcoder)
1469 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1470 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1471 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1476 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1477 if (scanline > 100 && scanline < 200)
1479 usleep_range(25, 50);
1482 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1483 false, TRANS_DDI_HDCP_SIGNALLING);
1485 drm_err(&dev_priv->drm,
1486 "Disable HDCP signalling failed (%d)\n", ret);
1490 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1491 true, TRANS_DDI_HDCP_SIGNALLING);
1493 drm_err(&dev_priv->drm,
1494 "Enable HDCP signalling failed (%d)\n", ret);
1502 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1503 enum transcoder cpu_transcoder,
1506 struct intel_hdmi *hdmi = &dig_port->hdmi;
1507 struct intel_connector *connector = hdmi->attached_connector;
1508 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1512 usleep_range(6, 60); /* Bspec says >= 6us */
1514 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1515 cpu_transcoder, enable,
1516 TRANS_DDI_HDCP_SIGNALLING);
1518 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1519 enable ? "Enable" : "Disable", ret);
1524 * WA: To fix incorrect positioning of the window of
1525 * opportunity and enc_en signalling in KABYLAKE.
1527 if (IS_KABYLAKE(dev_priv) && enable)
1528 return kbl_repositioning_enc_en_signal(connector,
1535 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1536 struct intel_connector *connector)
1538 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1539 enum port port = dig_port->base.port;
1540 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1544 u8 shim[DRM_HDCP_RI_LEN];
1547 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1551 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1553 /* Wait for Ri prime match */
1554 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1556 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1557 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1558 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1566 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1567 struct intel_connector *connector)
1569 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1572 for (retry = 0; retry < 3; retry++)
1573 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1576 drm_err(&i915->drm, "Link check failed\n");
1580 struct hdcp2_hdmi_msg_timeout {
1585 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1586 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1587 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1588 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1589 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1590 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1594 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1597 return intel_hdmi_hdcp_read(dig_port,
1598 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1600 HDCP_2_2_HDMI_RXSTATUS_LEN);
1603 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1607 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1609 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1611 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1614 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1615 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1616 return hdcp2_msg_timeout[i].timeout;
1623 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1624 u8 msg_id, bool *msg_ready,
1627 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1628 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1631 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1633 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1638 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1641 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1642 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1645 *msg_ready = *msg_sz;
1651 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1652 u8 msg_id, bool paired)
1654 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1655 bool msg_ready = false;
1659 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1663 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1666 !ret && msg_ready && msg_sz, timeout * 1000,
1669 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1670 msg_id, ret, timeout);
1672 return ret ? ret : msg_sz;
1676 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1677 void *buf, size_t size)
1679 unsigned int offset;
1681 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1682 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1686 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1687 u8 msg_id, void *buf, size_t size)
1689 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1690 struct intel_hdmi *hdmi = &dig_port->hdmi;
1691 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1692 unsigned int offset;
1695 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1701 * Available msg size should be equal to or lesser than the
1705 drm_dbg_kms(&i915->drm,
1706 "msg_sz(%zd) is more than exp size(%zu)\n",
1711 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1712 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1714 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1721 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1722 struct intel_connector *connector)
1724 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1727 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1732 * Re-auth request and Link Integrity Failures are represented by
1733 * same bit. i.e reauth_req.
1735 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1736 ret = HDCP_REAUTH_REQUEST;
1737 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1738 ret = HDCP_TOPOLOGY_CHANGE;
1744 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1751 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1752 &hdcp2_version, sizeof(hdcp2_version));
1753 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1759 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1760 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1761 .read_bksv = intel_hdmi_hdcp_read_bksv,
1762 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1763 .repeater_present = intel_hdmi_hdcp_repeater_present,
1764 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1765 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1766 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1767 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1768 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1769 .check_link = intel_hdmi_hdcp_check_link,
1770 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1771 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1772 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1773 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1774 .protocol = HDCP_PROTOCOL_HDMI,
1777 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1780 int max_tmds_clock, vbt_max_tmds_clock;
1782 if (DISPLAY_VER(dev_priv) >= 10)
1783 max_tmds_clock = 594000;
1784 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1785 max_tmds_clock = 300000;
1786 else if (DISPLAY_VER(dev_priv) >= 5)
1787 max_tmds_clock = 225000;
1789 max_tmds_clock = 165000;
1791 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1792 if (vbt_max_tmds_clock)
1793 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1795 return max_tmds_clock;
1798 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1799 const struct drm_connector_state *conn_state)
1801 return hdmi->has_hdmi_sink &&
1802 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1805 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1807 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1810 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1811 bool respect_downstream_limits,
1814 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1815 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1817 if (respect_downstream_limits) {
1818 struct intel_connector *connector = hdmi->attached_connector;
1819 const struct drm_display_info *info = &connector->base.display_info;
1821 if (hdmi->dp_dual_mode.max_tmds_clock)
1822 max_tmds_clock = min(max_tmds_clock,
1823 hdmi->dp_dual_mode.max_tmds_clock);
1825 if (info->max_tmds_clock)
1826 max_tmds_clock = min(max_tmds_clock,
1827 info->max_tmds_clock);
1828 else if (!has_hdmi_sink)
1829 max_tmds_clock = min(max_tmds_clock, 165000);
1832 return max_tmds_clock;
1835 static enum drm_mode_status
1836 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1837 int clock, bool respect_downstream_limits,
1840 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1841 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1844 return MODE_CLOCK_LOW;
1845 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1847 return MODE_CLOCK_HIGH;
1849 /* GLK DPLL can't generate 446-480 MHz */
1850 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1851 return MODE_CLOCK_RANGE;
1853 /* BXT/GLK DPLL can't generate 223-240 MHz */
1854 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1855 clock > 223333 && clock < 240000)
1856 return MODE_CLOCK_RANGE;
1858 /* CHV DPLL can't generate 216-240 MHz */
1859 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1860 return MODE_CLOCK_RANGE;
1862 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1863 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1864 return MODE_CLOCK_RANGE;
1866 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1867 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1868 return MODE_CLOCK_RANGE;
1871 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1872 * set of link rates.
1874 * FIXME: We will hopefully get an algorithmic way of programming
1875 * the MPLLB for HDMI in the future.
1877 if (IS_DG2(dev_priv))
1878 return intel_snps_phy_check_hdmi_link_rate(clock);
1883 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1885 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1886 if (ycbcr420_output)
1890 * Need to adjust the port link by:
1894 return clock * bpc / 8;
1897 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1901 return !HAS_GMCH(i915);
1903 return DISPLAY_VER(i915) >= 11;
1912 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1913 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1915 const struct drm_display_info *info = &connector->display_info;
1916 const struct drm_hdmi_info *hdmi = &info->hdmi;
1923 if (ycbcr420_output)
1924 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1926 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1931 if (ycbcr420_output)
1932 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1934 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1943 static enum drm_mode_status
1944 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1945 bool has_hdmi_sink, bool ycbcr420_output)
1947 struct drm_i915_private *i915 = to_i915(connector->dev);
1948 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1949 enum drm_mode_status status = MODE_OK;
1953 * Try all color depths since valid port clock range
1954 * can have holes. Any mode that can be used with at
1955 * least one color depth is accepted.
1957 for (bpc = 12; bpc >= 8; bpc -= 2) {
1958 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1960 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1963 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1966 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1967 if (status == MODE_OK)
1971 /* can never happen */
1972 drm_WARN_ON(&i915->drm, status == MODE_OK);
1977 static enum drm_mode_status
1978 intel_hdmi_mode_valid(struct drm_connector *connector,
1979 struct drm_display_mode *mode)
1981 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1982 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1983 enum drm_mode_status status;
1984 int clock = mode->clock;
1985 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1986 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1987 bool ycbcr_420_only;
1989 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1990 return MODE_NO_DBLESCAN;
1992 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1995 if (clock > max_dotclk)
1996 return MODE_CLOCK_HIGH;
1998 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2000 return MODE_CLOCK_LOW;
2005 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2006 * enumerated only if FRL is supported. Current platforms do not support
2007 * FRL so prune the higher resolution modes that require doctclock more
2011 return MODE_CLOCK_HIGH;
2013 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2015 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2016 if (status != MODE_OK) {
2017 if (ycbcr_420_only ||
2018 !connector->ycbcr_420_allowed ||
2019 !drm_mode_is_420_also(&connector->display_info, mode))
2022 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2023 if (status != MODE_OK)
2027 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2030 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2031 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2033 struct drm_atomic_state *state = crtc_state->uapi.state;
2034 struct drm_connector_state *connector_state;
2035 struct drm_connector *connector;
2038 for_each_new_connector_in_state(state, connector, connector_state, i) {
2039 if (connector_state->crtc != crtc_state->uapi.crtc)
2042 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2049 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2051 struct drm_i915_private *dev_priv =
2052 to_i915(crtc_state->uapi.crtc->dev);
2053 const struct drm_display_mode *adjusted_mode =
2054 &crtc_state->hw.adjusted_mode;
2056 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2060 * HDMI deep color affects the clocks, so it's only possible
2061 * when not cloning with other encoder types.
2063 if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2066 /* Display Wa_1405510057:icl,ehl */
2067 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2068 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2069 (adjusted_mode->crtc_hblank_end -
2070 adjusted_mode->crtc_hblank_start) % 8 == 2)
2073 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2074 intel_hdmi_is_ycbcr420(crtc_state));
2077 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2078 struct intel_crtc_state *crtc_state,
2079 int clock, bool respect_downstream_limits)
2081 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2082 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2086 * pipe_bpp could already be below 8bpc due to FDI
2087 * bandwidth constraints. HDMI minimum is 8bpc however.
2089 bpc = max(crtc_state->pipe_bpp / 3, 8);
2092 * We will never exceed downstream TMDS clock limits while
2093 * attempting deep color. If the user insists on forcing an
2094 * out of spec mode they will have to be satisfied with 8bpc.
2096 if (!respect_downstream_limits)
2099 for (; bpc >= 8; bpc -= 2) {
2100 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2102 if (hdmi_bpc_possible(crtc_state, bpc) &&
2103 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2104 respect_downstream_limits,
2105 crtc_state->has_hdmi_sink) == MODE_OK)
2112 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2113 struct intel_crtc_state *crtc_state,
2114 bool respect_downstream_limits)
2116 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2117 const struct drm_display_mode *adjusted_mode =
2118 &crtc_state->hw.adjusted_mode;
2119 int bpc, clock = adjusted_mode->crtc_clock;
2121 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2124 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2125 respect_downstream_limits);
2129 crtc_state->port_clock =
2130 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2133 * pipe_bpp could already be below 8bpc due to
2134 * FDI bandwidth constraints. We shouldn't bump it
2135 * back up to the HDMI minimum 8bpc in that case.
2137 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2139 drm_dbg_kms(&i915->drm,
2140 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2141 bpc, crtc_state->pipe_bpp);
2146 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2147 const struct drm_connector_state *conn_state)
2149 const struct intel_digital_connector_state *intel_conn_state =
2150 to_intel_digital_connector_state(conn_state);
2151 const struct drm_display_mode *adjusted_mode =
2152 &crtc_state->hw.adjusted_mode;
2155 * Our YCbCr output is always limited range.
2156 * crtc_state->limited_color_range only applies to RGB,
2157 * and it must never be set for YCbCr or we risk setting
2158 * some conflicting bits in PIPECONF which will mess up
2159 * the colors on the monitor.
2161 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2164 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2165 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2166 return crtc_state->has_hdmi_sink &&
2167 drm_default_rgb_quant_range(adjusted_mode) ==
2168 HDMI_QUANTIZATION_RANGE_LIMITED;
2170 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2174 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2175 const struct intel_crtc_state *crtc_state,
2176 const struct drm_connector_state *conn_state)
2178 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2179 const struct intel_digital_connector_state *intel_conn_state =
2180 to_intel_digital_connector_state(conn_state);
2182 if (!crtc_state->has_hdmi_sink)
2185 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2186 return intel_hdmi->has_audio;
2188 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2191 static enum intel_output_format
2192 intel_hdmi_output_format(struct intel_connector *connector,
2193 bool ycbcr_420_output)
2195 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2196 return INTEL_OUTPUT_FORMAT_YCBCR420;
2198 return INTEL_OUTPUT_FORMAT_RGB;
2201 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2202 struct intel_crtc_state *crtc_state,
2203 const struct drm_connector_state *conn_state,
2204 bool respect_downstream_limits)
2206 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2207 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2208 const struct drm_display_info *info = &connector->base.display_info;
2209 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2210 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2213 crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
2215 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2216 drm_dbg_kms(&i915->drm,
2217 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2218 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2221 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2223 if (intel_hdmi_is_ycbcr420(crtc_state) ||
2224 !connector->base.ycbcr_420_allowed ||
2225 !drm_mode_is_420_also(info, adjusted_mode))
2228 crtc_state->output_format = intel_hdmi_output_format(connector, true);
2229 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2235 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2236 struct intel_crtc_state *pipe_config,
2237 struct drm_connector_state *conn_state)
2239 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2241 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2242 struct drm_connector *connector = conn_state->connector;
2243 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2246 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2249 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2250 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2253 if (pipe_config->has_hdmi_sink)
2254 pipe_config->has_infoframe = true;
2256 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2257 pipe_config->pixel_multiplier = 2;
2259 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2260 pipe_config->has_pch_encoder = true;
2262 pipe_config->has_audio =
2263 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2266 * Try to respect downstream TMDS clock limits first, if
2267 * that fails assume the user might know something we don't.
2269 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2271 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2273 drm_dbg_kms(&dev_priv->drm,
2274 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2275 pipe_config->hw.adjusted_mode.crtc_clock);
2279 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2280 ret = intel_panel_fitting(pipe_config, conn_state);
2285 pipe_config->limited_color_range =
2286 intel_hdmi_limited_color_range(pipe_config, conn_state);
2288 if (conn_state->picture_aspect_ratio)
2289 adjusted_mode->picture_aspect_ratio =
2290 conn_state->picture_aspect_ratio;
2292 pipe_config->lane_count = 4;
2294 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2295 if (scdc->scrambling.low_rates)
2296 pipe_config->hdmi_scrambling = true;
2298 if (pipe_config->port_clock > 340000) {
2299 pipe_config->hdmi_scrambling = true;
2300 pipe_config->hdmi_high_tmds_clock_ratio = true;
2304 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2307 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2308 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2312 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2313 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2317 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2318 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2322 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2323 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2330 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2332 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2335 * Give a hand to buggy BIOSen which forget to turn
2336 * the TMDS output buffers back on after a reboot.
2338 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2342 intel_hdmi_unset_edid(struct drm_connector *connector)
2344 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2346 intel_hdmi->has_hdmi_sink = false;
2347 intel_hdmi->has_audio = false;
2349 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2350 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2352 kfree(to_intel_connector(connector)->detect_edid);
2353 to_intel_connector(connector)->detect_edid = NULL;
2357 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2359 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2360 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2361 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2362 struct i2c_adapter *adapter =
2363 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2364 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2367 * Type 1 DVI adaptors are not required to implement any
2368 * registers, so we can't always detect their presence.
2369 * Ideally we should be able to check the state of the
2370 * CONFIG1 pin, but no such luck on our hardware.
2372 * The only method left to us is to check the VBT to see
2373 * if the port is a dual mode capable DP port. But let's
2374 * only do that when we sucesfully read the EDID, to avoid
2375 * confusing log messages about DP dual mode adaptors when
2376 * there's nothing connected to the port.
2378 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2379 /* An overridden EDID imply that we want this port for testing.
2380 * Make sure not to set limits for that port.
2382 if (has_edid && !connector->override_edid &&
2383 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2384 drm_dbg_kms(&dev_priv->drm,
2385 "Assuming DP dual mode adaptor presence based on VBT\n");
2386 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2388 type = DRM_DP_DUAL_MODE_NONE;
2392 if (type == DRM_DP_DUAL_MODE_NONE)
2395 hdmi->dp_dual_mode.type = type;
2396 hdmi->dp_dual_mode.max_tmds_clock =
2397 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2399 drm_dbg_kms(&dev_priv->drm,
2400 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2401 drm_dp_get_dual_mode_type_name(type),
2402 hdmi->dp_dual_mode.max_tmds_clock);
2404 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2405 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2406 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2407 drm_dbg_kms(&dev_priv->drm,
2408 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2409 hdmi->dp_dual_mode.max_tmds_clock = 0;
2414 intel_hdmi_set_edid(struct drm_connector *connector)
2416 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2417 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2418 intel_wakeref_t wakeref;
2420 bool connected = false;
2421 struct i2c_adapter *i2c;
2423 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2425 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2427 edid = drm_get_edid(connector, i2c);
2429 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2430 drm_dbg_kms(&dev_priv->drm,
2431 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2432 intel_gmbus_force_bit(i2c, true);
2433 edid = drm_get_edid(connector, i2c);
2434 intel_gmbus_force_bit(i2c, false);
2437 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2439 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2441 to_intel_connector(connector)->detect_edid = edid;
2442 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2443 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2444 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2449 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2454 static enum drm_connector_status
2455 intel_hdmi_detect(struct drm_connector *connector, bool force)
2457 enum drm_connector_status status = connector_status_disconnected;
2458 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2459 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2460 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2461 intel_wakeref_t wakeref;
2463 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2464 connector->base.id, connector->name);
2466 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2467 return connector_status_disconnected;
2469 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2471 if (DISPLAY_VER(dev_priv) >= 11 &&
2472 !intel_digital_port_connected(encoder))
2475 intel_hdmi_unset_edid(connector);
2477 if (intel_hdmi_set_edid(connector))
2478 status = connector_status_connected;
2481 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2483 if (status != connector_status_connected)
2484 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2487 * Make sure the refs for power wells enabled during detect are
2488 * dropped to avoid a new detect cycle triggered by HPD polling.
2490 intel_display_power_flush_work(dev_priv);
2496 intel_hdmi_force(struct drm_connector *connector)
2498 struct drm_i915_private *i915 = to_i915(connector->dev);
2500 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2501 connector->base.id, connector->name);
2503 intel_hdmi_unset_edid(connector);
2505 if (connector->status != connector_status_connected)
2508 intel_hdmi_set_edid(connector);
2511 static int intel_hdmi_get_modes(struct drm_connector *connector)
2515 edid = to_intel_connector(connector)->detect_edid;
2519 return intel_connector_update_modes(connector, edid);
2522 static struct i2c_adapter *
2523 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2525 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2526 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2528 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2531 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2533 struct drm_i915_private *i915 = to_i915(connector->dev);
2534 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2535 struct kobject *i2c_kobj = &adapter->dev.kobj;
2536 struct kobject *connector_kobj = &connector->kdev->kobj;
2539 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2541 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2544 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2546 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2547 struct kobject *i2c_kobj = &adapter->dev.kobj;
2548 struct kobject *connector_kobj = &connector->kdev->kobj;
2550 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2554 intel_hdmi_connector_register(struct drm_connector *connector)
2558 ret = intel_connector_register(connector);
2562 intel_hdmi_create_i2c_symlink(connector);
2567 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2569 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2571 cec_notifier_conn_unregister(n);
2573 intel_hdmi_remove_i2c_symlink(connector);
2574 intel_connector_unregister(connector);
2577 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2578 .detect = intel_hdmi_detect,
2579 .force = intel_hdmi_force,
2580 .fill_modes = drm_helper_probe_single_connector_modes,
2581 .atomic_get_property = intel_digital_connector_atomic_get_property,
2582 .atomic_set_property = intel_digital_connector_atomic_set_property,
2583 .late_register = intel_hdmi_connector_register,
2584 .early_unregister = intel_hdmi_connector_unregister,
2585 .destroy = intel_connector_destroy,
2586 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2587 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2590 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2591 .get_modes = intel_hdmi_get_modes,
2592 .mode_valid = intel_hdmi_mode_valid,
2593 .atomic_check = intel_digital_connector_atomic_check,
2597 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2599 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2601 intel_attach_force_audio_property(connector);
2602 intel_attach_broadcast_rgb_property(connector);
2603 intel_attach_aspect_ratio_property(connector);
2605 intel_attach_hdmi_colorspace_property(connector);
2606 drm_connector_attach_content_type_property(connector);
2608 if (DISPLAY_VER(dev_priv) >= 10)
2609 drm_connector_attach_hdr_output_metadata_property(connector);
2611 if (!HAS_GMCH(dev_priv))
2612 drm_connector_attach_max_bpc_property(connector, 8, 12);
2616 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2617 * @encoder: intel_encoder
2618 * @connector: drm_connector
2619 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2620 * or reset the high tmds clock ratio for scrambling
2621 * @scrambling: bool to Indicate if the function needs to set or reset
2624 * This function handles scrambling on HDMI 2.0 capable sinks.
2625 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2626 * it enables scrambling. This should be called before enabling the HDMI
2627 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2628 * detect a scrambled clock within 100 ms.
2631 * True on success, false on failure.
2633 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2634 struct drm_connector *connector,
2635 bool high_tmds_clock_ratio,
2638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2639 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2640 struct drm_scrambling *sink_scrambling =
2641 &connector->display_info.hdmi.scdc.scrambling;
2642 struct i2c_adapter *adapter =
2643 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2645 if (!sink_scrambling->supported)
2648 drm_dbg_kms(&dev_priv->drm,
2649 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2650 connector->base.id, connector->name,
2651 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2653 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2654 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2655 high_tmds_clock_ratio) &&
2656 drm_scdc_set_scrambling(adapter, scrambling);
2659 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2665 ddc_pin = GMBUS_PIN_DPB;
2668 ddc_pin = GMBUS_PIN_DPC;
2671 ddc_pin = GMBUS_PIN_DPD_CHV;
2675 ddc_pin = GMBUS_PIN_DPB;
2681 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2687 ddc_pin = GMBUS_PIN_1_BXT;
2690 ddc_pin = GMBUS_PIN_2_BXT;
2694 ddc_pin = GMBUS_PIN_1_BXT;
2700 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2707 ddc_pin = GMBUS_PIN_1_BXT;
2710 ddc_pin = GMBUS_PIN_2_BXT;
2713 ddc_pin = GMBUS_PIN_4_CNP;
2716 ddc_pin = GMBUS_PIN_3_BXT;
2720 ddc_pin = GMBUS_PIN_1_BXT;
2726 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2728 enum phy phy = intel_port_to_phy(dev_priv, port);
2730 if (intel_phy_is_combo(dev_priv, phy))
2731 return GMBUS_PIN_1_BXT + port;
2732 else if (intel_phy_is_tc(dev_priv, phy))
2733 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2735 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2736 return GMBUS_PIN_2_BXT;
2739 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2741 enum phy phy = intel_port_to_phy(dev_priv, port);
2746 ddc_pin = GMBUS_PIN_1_BXT;
2749 ddc_pin = GMBUS_PIN_2_BXT;
2752 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2756 ddc_pin = GMBUS_PIN_1_BXT;
2762 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2764 enum phy phy = intel_port_to_phy(dev_priv, port);
2766 WARN_ON(port == PORT_C);
2769 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2770 * final two outputs use type-c pins, even though they're actually
2771 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2774 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2775 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2777 return GMBUS_PIN_1_BXT + phy;
2780 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2782 enum phy phy = intel_port_to_phy(i915, port);
2784 drm_WARN_ON(&i915->drm, port == PORT_A);
2787 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2788 * final two outputs use type-c pins, even though they're actually
2789 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2792 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2793 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2795 return GMBUS_PIN_1_BXT + phy;
2798 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2800 return intel_port_to_phy(dev_priv, port) + 1;
2803 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2805 enum phy phy = intel_port_to_phy(dev_priv, port);
2807 WARN_ON(port == PORT_B || port == PORT_C);
2810 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2811 * except first combo output.
2814 return GMBUS_PIN_1_BXT;
2816 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2819 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2826 ddc_pin = GMBUS_PIN_DPB;
2829 ddc_pin = GMBUS_PIN_DPC;
2832 ddc_pin = GMBUS_PIN_DPD;
2836 ddc_pin = GMBUS_PIN_DPB;
2842 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2844 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2845 enum port port = encoder->port;
2848 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2850 drm_dbg_kms(&dev_priv->drm,
2851 "Using DDC pin 0x%x for port %c (VBT)\n",
2852 ddc_pin, port_name(port));
2856 if (IS_ALDERLAKE_S(dev_priv))
2857 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2858 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2859 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2860 else if (IS_ROCKETLAKE(dev_priv))
2861 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2862 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2863 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2864 else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2865 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2866 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2867 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2868 else if (HAS_PCH_CNP(dev_priv))
2869 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2870 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2871 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2872 else if (IS_CHERRYVIEW(dev_priv))
2873 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2875 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2877 drm_dbg_kms(&dev_priv->drm,
2878 "Using DDC pin 0x%x for port %c (platform default)\n",
2879 ddc_pin, port_name(port));
2884 void intel_infoframe_init(struct intel_digital_port *dig_port)
2886 struct drm_i915_private *dev_priv =
2887 to_i915(dig_port->base.base.dev);
2889 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2890 dig_port->write_infoframe = vlv_write_infoframe;
2891 dig_port->read_infoframe = vlv_read_infoframe;
2892 dig_port->set_infoframes = vlv_set_infoframes;
2893 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2894 } else if (IS_G4X(dev_priv)) {
2895 dig_port->write_infoframe = g4x_write_infoframe;
2896 dig_port->read_infoframe = g4x_read_infoframe;
2897 dig_port->set_infoframes = g4x_set_infoframes;
2898 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2899 } else if (HAS_DDI(dev_priv)) {
2900 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2901 dig_port->write_infoframe = lspcon_write_infoframe;
2902 dig_port->read_infoframe = lspcon_read_infoframe;
2903 dig_port->set_infoframes = lspcon_set_infoframes;
2904 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2906 dig_port->write_infoframe = hsw_write_infoframe;
2907 dig_port->read_infoframe = hsw_read_infoframe;
2908 dig_port->set_infoframes = hsw_set_infoframes;
2909 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2911 } else if (HAS_PCH_IBX(dev_priv)) {
2912 dig_port->write_infoframe = ibx_write_infoframe;
2913 dig_port->read_infoframe = ibx_read_infoframe;
2914 dig_port->set_infoframes = ibx_set_infoframes;
2915 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2917 dig_port->write_infoframe = cpt_write_infoframe;
2918 dig_port->read_infoframe = cpt_read_infoframe;
2919 dig_port->set_infoframes = cpt_set_infoframes;
2920 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2924 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2925 struct intel_connector *intel_connector)
2927 struct drm_connector *connector = &intel_connector->base;
2928 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2929 struct intel_encoder *intel_encoder = &dig_port->base;
2930 struct drm_device *dev = intel_encoder->base.dev;
2931 struct drm_i915_private *dev_priv = to_i915(dev);
2932 struct i2c_adapter *ddc;
2933 enum port port = intel_encoder->port;
2934 struct cec_connector_info conn_info;
2936 drm_dbg_kms(&dev_priv->drm,
2937 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2938 intel_encoder->base.base.id, intel_encoder->base.name);
2940 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2943 if (drm_WARN(dev, dig_port->max_lanes < 4,
2944 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2945 dig_port->max_lanes, intel_encoder->base.base.id,
2946 intel_encoder->base.name))
2949 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2950 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2952 drm_connector_init_with_ddc(dev, connector,
2953 &intel_hdmi_connector_funcs,
2954 DRM_MODE_CONNECTOR_HDMIA,
2956 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2958 connector->interlace_allowed = 1;
2959 connector->doublescan_allowed = 0;
2960 connector->stereo_allowed = 1;
2962 if (DISPLAY_VER(dev_priv) >= 10)
2963 connector->ycbcr_420_allowed = true;
2965 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2967 if (HAS_DDI(dev_priv))
2968 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2970 intel_connector->get_hw_state = intel_connector_get_hw_state;
2972 intel_hdmi_add_properties(intel_hdmi, connector);
2974 intel_connector_attach_encoder(intel_connector, intel_encoder);
2975 intel_hdmi->attached_connector = intel_connector;
2977 if (is_hdcp_supported(dev_priv, port)) {
2978 int ret = intel_hdcp_init(intel_connector, dig_port,
2979 &intel_hdmi_hdcp_shim);
2981 drm_dbg_kms(&dev_priv->drm,
2982 "HDCP init failed, skipping.\n");
2985 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2986 * 0xd. Failure to do so will result in spurious interrupts being
2987 * generated on the port when a cable is not attached.
2989 if (IS_G45(dev_priv)) {
2990 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2991 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2992 (temp & ~0xf) | 0xd);
2995 cec_fill_conn_info_from_drm(&conn_info, connector);
2997 intel_hdmi->cec_notifier =
2998 cec_notifier_conn_register(dev->dev, port_identifier(port),
3000 if (!intel_hdmi->cec_notifier)
3001 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3005 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3006 * @vactive: Vactive of a display mode
3008 * @return: appropriate dsc slice height for a given mode.
3010 int intel_hdmi_dsc_get_slice_height(int vactive)
3015 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3016 * Select smallest slice height >=96, that results in a valid PPS and
3017 * requires minimum padding lines required for final slice.
3019 * Assumption : Vactive is even.
3021 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3022 if (vactive % slice_height == 0)
3023 return slice_height;
3029 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3030 * and dsc decoder capabilities
3032 * @crtc_state: intel crtc_state
3033 * @src_max_slices: maximum slices supported by the DSC encoder
3034 * @src_max_slice_width: maximum slice width supported by DSC encoder
3035 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3036 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3038 * @return: num of dsc slices that can be supported by the dsc encoder
3042 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3043 int src_max_slices, int src_max_slice_width,
3044 int hdmi_max_slices, int hdmi_throughput)
3046 /* Pixel rates in KPixels/sec */
3047 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3049 * Rates at which the source and sink are required to process pixels in each
3050 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3052 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3053 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3055 /* Spec limits the slice width to 2720 pixels */
3056 #define MAX_HDMI_SLICE_WIDTH 2720
3058 int adjusted_clk_khz;
3061 int max_throughput; /* max clock freq. in khz per slice */
3062 int max_slice_width;
3064 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3066 if (!hdmi_throughput)
3070 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3071 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3072 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3073 * dividing adjusted clock value by 10.
3075 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3076 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3082 * As per spec, the rate at which the source and the sink process
3083 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3084 * This depends upon the pixel clock rate and output formats
3086 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3087 * at max 340MHz, otherwise they can be processed at max 400MHz.
3090 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3092 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3093 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3095 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3098 * Taking into account the sink's capability for maximum
3099 * clock per slice (in MHz) as read from HF-VSDB.
3101 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3103 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3104 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3107 * Keep on increasing the num of slices/line, starting from min_slices
3108 * per line till we get such a number, for which the slice_width is
3109 * just less than max_slice_width. The slices/line selected should be
3110 * less than or equal to the max horizontal slices that the combination
3111 * of PCON encoder and HDMI decoder can support.
3113 slice_width = max_slice_width;
3116 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3118 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3120 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3122 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3124 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3126 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3131 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3132 if (slice_width >= max_slice_width)
3133 min_slices = target_slices + 1;
3134 } while (slice_width >= max_slice_width);
3136 return target_slices;
3140 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3141 * source and sink capabilities.
3143 * @src_fraction_bpp: fractional bpp supported by the source
3144 * @slice_width: dsc slice width supported by the source and sink
3145 * @num_slices: num of slices supported by the source and sink
3146 * @output_format: video output format
3147 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3148 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3150 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3153 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3154 int output_format, bool hdmi_all_bpp,
3155 int hdmi_max_chunk_bytes)
3157 int max_dsc_bpp, min_dsc_bpp;
3159 bool bpp_found = false;
3160 int bpp_decrement_x16;
3165 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3166 * Start with the max bpp and keep on decrementing with
3167 * fractional bpp, if supported by PCON DSC encoder
3169 * for each bpp we check if no of bytes can be supported by HDMI sink
3172 /* Assuming: bpc as 8*/
3173 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3175 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3176 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3177 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3179 max_dsc_bpp = 3 * 8; /* 3*bpc */
3181 /* Assuming 4:2:2 encoding */
3183 max_dsc_bpp = 2 * 8; /* 2*bpc */
3187 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3188 * Section 7.7.34 : Source shall not enable compressed Video
3189 * Transport with bpp_target settings above 12 bpp unless
3190 * DSC_all_bpp is set to 1.
3193 max_dsc_bpp = min(max_dsc_bpp, 12);
3196 * The Sink has a limit of compressed data in bytes for a scanline,
3197 * as described in max_chunk_bytes field in HFVSDB block of edid.
3198 * The no. of bytes depend on the target bits per pixel that the
3199 * source configures. So we start with the max_bpp and calculate
3200 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3201 * till we get the target_chunk_bytes just less than what the sink's
3202 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3204 * The decrement is according to the fractional support from PCON DSC
3205 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3207 * bpp_target_x16 = bpp_target * 16
3208 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3209 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3212 bpp_target = max_dsc_bpp;
3214 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3215 if (!src_fractional_bpp)
3216 src_fractional_bpp = 1;
3217 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3218 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3220 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3223 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3224 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3225 if (target_bytes <= hdmi_max_chunk_bytes) {
3229 bpp_target_x16 -= bpp_decrement_x16;
3232 return bpp_target_x16;