drivers/gpu/drm/i915/display/intel_gmbus.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29
  30 #include <linux/export.h>
  31 #include <linux/i2c-algo-bit.h>
  32 #include <linux/i2c.h>
  33
  34 #include <drm/drm_hdcp.h>
  35
  36 #include "i915_drv.h"
  37 #include "intel_display_types.h"
  38 #include "intel_gmbus.h"
  39
  40 struct gmbus_pin {
  41         const char *name;
  42         enum i915_gpio gpio;
  43 };
  44
  45 /* Map gmbus pin pairs to names and registers. */
  46 static const struct gmbus_pin gmbus_pins[] = {
  47         [GMBUS_PIN_SSC] = { "ssc", GPIOB },
  48         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  49         [GMBUS_PIN_PANEL] = { "panel", GPIOC },
  50         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  51         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  52         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  53 };
  54
  55 static const struct gmbus_pin gmbus_pins_bdw[] = {
  56         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  57         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  58         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  59         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  60 };
  61
  62 static const struct gmbus_pin gmbus_pins_skl[] = {
  63         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  64         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  65         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  66 };
  67
  68 static const struct gmbus_pin gmbus_pins_bxt[] = {
  69         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  70         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  71         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  72 };
  73
  74 static const struct gmbus_pin gmbus_pins_cnp[] = {
  75         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  76         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  77         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  78         [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
  79 };
  80
  81 static const struct gmbus_pin gmbus_pins_icp[] = {
  82         [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
  83         [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
  84         [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
  85         [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
  86         [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
  87         [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
  88         [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
  89         [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
  90         [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
  91 };
  92
  93 /* pin is expected to be valid */
  94 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
  95                                              unsigned int pin)
  96 {
  97         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
  98                 return &gmbus_pins_icp[pin];
  99         else if (HAS_PCH_CNP(dev_priv))
 100                 return &gmbus_pins_cnp[pin];
 101         else if (IS_GEN9_LP(dev_priv))
 102                 return &gmbus_pins_bxt[pin];
 103         else if (IS_GEN9_BC(dev_priv))
 104                 return &gmbus_pins_skl[pin];
 105         else if (IS_BROADWELL(dev_priv))
 106                 return &gmbus_pins_bdw[pin];
 107         else
 108                 return &gmbus_pins[pin];
 109 }
 110
 111 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 112                               unsigned int pin)
 113 {
 114         unsigned int size;
 115
 116         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 117                 size = ARRAY_SIZE(gmbus_pins_icp);
 118         else if (HAS_PCH_CNP(dev_priv))
 119                 size = ARRAY_SIZE(gmbus_pins_cnp);
 120         else if (IS_GEN9_LP(dev_priv))
 121                 size = ARRAY_SIZE(gmbus_pins_bxt);
 122         else if (IS_GEN9_BC(dev_priv))
 123                 size = ARRAY_SIZE(gmbus_pins_skl);
 124         else if (IS_BROADWELL(dev_priv))
 125                 size = ARRAY_SIZE(gmbus_pins_bdw);
 126         else
 127                 size = ARRAY_SIZE(gmbus_pins);
 128
 129         return pin < size && get_gmbus_pin(dev_priv, pin)->name;
 130 }
 131
 132 /* Intel GPIO access functions */
 133
 134 #define I2C_RISEFALL_TIME 10
 135
 136 static inline struct intel_gmbus *
 137 to_intel_gmbus(struct i2c_adapter *i2c)
 138 {
 139         return container_of(i2c, struct intel_gmbus, adapter);
 140 }
 141
 142 void
 143 intel_gmbus_reset(struct drm_i915_private *dev_priv)
 144 {
 145         intel_de_write(dev_priv, GMBUS0, 0);
 146         intel_de_write(dev_priv, GMBUS4, 0);
 147 }
 148
 149 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 150                                    bool enable)
 151 {
 152         u32 val;
 153
 154         /* When using bit bashing for I2C, this bit needs to be set to 1 */
 155         val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 156         if (!enable)
 157                 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 158         else
 159                 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 160         intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 161 }
 162
 163 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 164                                    bool enable)
 165 {
 166         u32 val;
 167
 168         val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
 169         if (!enable)
 170                 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
 171         else
 172                 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
 173         intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
 174 }
 175
 176 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 177                                    bool enable)
 178 {
 179         u32 val;
 180
 181         val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
 182         if (!enable)
 183                 val |= BXT_GMBUS_GATING_DIS;
 184         else
 185                 val &= ~BXT_GMBUS_GATING_DIS;
 186         intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
 187 }
 188
 189 static u32 get_reserved(struct intel_gmbus *bus)
 190 {
 191         struct drm_i915_private *i915 = bus->dev_priv;
 192         struct intel_uncore *uncore = &i915->uncore;
 193         u32 reserved = 0;
 194
 195         /* On most chips, these bits must be preserved in software. */
 196         if (!IS_I830(i915) && !IS_I845G(i915))
 197                 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
 198                            (GPIO_DATA_PULLUP_DISABLE |
 199                             GPIO_CLOCK_PULLUP_DISABLE);
 200
 201         return reserved;
 202 }
 203
 204 static int get_clock(void *data)
 205 {
 206         struct intel_gmbus *bus = data;
 207         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 208         u32 reserved = get_reserved(bus);
 209
 210         intel_uncore_write_notrace(uncore,
 211                                    bus->gpio_reg,
 212                                    reserved | GPIO_CLOCK_DIR_MASK);
 213         intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
 214
 215         return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
 216                 GPIO_CLOCK_VAL_IN) != 0;
 217 }
 218
 219 static int get_data(void *data)
 220 {
 221         struct intel_gmbus *bus = data;
 222         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 223         u32 reserved = get_reserved(bus);
 224
 225         intel_uncore_write_notrace(uncore,
 226                                    bus->gpio_reg,
 227                                    reserved | GPIO_DATA_DIR_MASK);
 228         intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
 229
 230         return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
 231                 GPIO_DATA_VAL_IN) != 0;
 232 }
 233
 234 static void set_clock(void *data, int state_high)
 235 {
 236         struct intel_gmbus *bus = data;
 237         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 238         u32 reserved = get_reserved(bus);
 239         u32 clock_bits;
 240
 241         if (state_high)
 242                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 243         else
 244                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 245                              GPIO_CLOCK_VAL_MASK;
 246
 247         intel_uncore_write_notrace(uncore,
 248                                    bus->gpio_reg,
 249                                    reserved | clock_bits);
 250         intel_uncore_posting_read(uncore, bus->gpio_reg);
 251 }
 252
 253 static void set_data(void *data, int state_high)
 254 {
 255         struct intel_gmbus *bus = data;
 256         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 257         u32 reserved = get_reserved(bus);
 258         u32 data_bits;
 259
 260         if (state_high)
 261                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 262         else
 263                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 264                         GPIO_DATA_VAL_MASK;
 265
 266         intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
 267         intel_uncore_posting_read(uncore, bus->gpio_reg);
 268 }
 269
 270 static int
 271 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 272 {
 273         struct intel_gmbus *bus = container_of(adapter,
 274                                                struct intel_gmbus,
 275                                                adapter);
 276         struct drm_i915_private *dev_priv = bus->dev_priv;
 277
 278         intel_gmbus_reset(dev_priv);
 279
 280         if (IS_PINEVIEW(dev_priv))
 281                 pnv_gmbus_clock_gating(dev_priv, false);
 282
 283         set_data(bus, 1);
 284         set_clock(bus, 1);
 285         udelay(I2C_RISEFALL_TIME);
 286         return 0;
 287 }
 288
 289 static void
 290 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 291 {
 292         struct intel_gmbus *bus = container_of(adapter,
 293                                                struct intel_gmbus,
 294                                                adapter);
 295         struct drm_i915_private *dev_priv = bus->dev_priv;
 296
 297         set_data(bus, 1);
 298         set_clock(bus, 1);
 299
 300         if (IS_PINEVIEW(dev_priv))
 301                 pnv_gmbus_clock_gating(dev_priv, true);
 302 }
 303
 304 static void
 305 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 306 {
 307         struct drm_i915_private *dev_priv = bus->dev_priv;
 308         struct i2c_algo_bit_data *algo;
 309
 310         algo = &bus->bit_algo;
 311
 312         bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
 313         bus->adapter.algo_data = algo;
 314         algo->setsda = set_data;
 315         algo->setscl = set_clock;
 316         algo->getsda = get_data;
 317         algo->getscl = get_clock;
 318         algo->pre_xfer = intel_gpio_pre_xfer;
 319         algo->post_xfer = intel_gpio_post_xfer;
 320         algo->udelay = I2C_RISEFALL_TIME;
 321         algo->timeout = usecs_to_jiffies(2200);
 322         algo->data = bus;
 323 }
 324
 325 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
 326 {
 327         DEFINE_WAIT(wait);
 328         u32 gmbus2;
 329         int ret;
 330
 331         /* Important: The hw handles only the first bit, so set only one! Since
 332          * we also need to check for NAKs besides the hw ready/idle signal, we
 333          * need to wake up periodically and check that ourselves.
 334          */
 335         if (!HAS_GMBUS_IRQ(dev_priv))
 336                 irq_en = 0;
 337
 338         add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 339         intel_de_write_fw(dev_priv, GMBUS4, irq_en);
 340
 341         status |= GMBUS_SATOER;
 342         ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
 343                           2);
 344         if (ret)
 345                 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
 346                                50);
 347
 348         intel_de_write_fw(dev_priv, GMBUS4, 0);
 349         remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 350
 351         if (gmbus2 & GMBUS_SATOER)
 352                 return -ENXIO;
 353
 354         return ret;
 355 }
 356
 357 static int
 358 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 359 {
 360         DEFINE_WAIT(wait);
 361         u32 irq_enable;
 362         int ret;
 363
 364         /* Important: The hw handles only the first bit, so set only one! */
 365         irq_enable = 0;
 366         if (HAS_GMBUS_IRQ(dev_priv))
 367                 irq_enable = GMBUS_IDLE_EN;
 368
 369         add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 370         intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
 371
 372         ret = intel_wait_for_register_fw(&dev_priv->uncore,
 373                                          GMBUS2, GMBUS_ACTIVE, 0,
 374                                          10);
 375
 376         intel_de_write_fw(dev_priv, GMBUS4, 0);
 377         remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 378
 379         return ret;
 380 }
 381
 382 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
 383 {
 384         return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
 385                GMBUS_BYTE_COUNT_MAX;
 386 }
 387
 388 static int
 389 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 390                       unsigned short addr, u8 *buf, unsigned int len,
 391                       u32 gmbus0_reg, u32 gmbus1_index)
 392 {
 393         unsigned int size = len;
 394         bool burst_read = len > gmbus_max_xfer_size(dev_priv);
 395         bool extra_byte_added = false;
 396
 397         if (burst_read) {
 398                 /*
 399                  * As per HW Spec, for 512Bytes need to read extra Byte and
 400                  * Ignore the extra byte read.
 401                  */
 402                 if (len == 512) {
 403                         extra_byte_added = true;
 404                         len++;
 405                 }
 406                 size = len % 256 + 256;
 407                 intel_de_write_fw(dev_priv, GMBUS0,
 408                                   gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
 409         }
 410
 411         intel_de_write_fw(dev_priv, GMBUS1,
 412                           gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 413         while (len) {
 414                 int ret;
 415                 u32 val, loop = 0;
 416
 417                 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 418                 if (ret)
 419                         return ret;
 420
 421                 val = intel_de_read_fw(dev_priv, GMBUS3);
 422                 do {
 423                         if (extra_byte_added && len == 1)
 424                                 break;
 425
 426                         *buf++ = val & 0xff;
 427                         val >>= 8;
 428                 } while (--len && ++loop < 4);
 429
 430                 if (burst_read && len == size - 4)
 431                         /* Reset the override bit */
 432                         intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
 433         }
 434
 435         return 0;
 436 }
 437
 438 /*
 439  * HW spec says that 512Bytes in Burst read need special treatment.
 440  * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
 441  * an I2C slave, which supports such a lengthy burst read too for experiments.
 442  *
 443  * So until things get clarified on HW support, to avoid the burst read length
 444  * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
 445  */
 446 #define INTEL_GMBUS_BURST_READ_MAX_LEN          767U
 447
 448 static int
 449 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 450                 u32 gmbus0_reg, u32 gmbus1_index)
 451 {
 452         u8 *buf = msg->buf;
 453         unsigned int rx_size = msg->len;
 454         unsigned int len;
 455         int ret;
 456
 457         do {
 458                 if (HAS_GMBUS_BURST_READ(dev_priv))
 459                         len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
 460                 else
 461                         len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 462
 463                 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
 464                                             gmbus0_reg, gmbus1_index);
 465                 if (ret)
 466                         return ret;
 467
 468                 rx_size -= len;
 469                 buf += len;
 470         } while (rx_size != 0);
 471
 472         return 0;
 473 }
 474
 475 static int
 476 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 477                        unsigned short addr, u8 *buf, unsigned int len,
 478                        u32 gmbus1_index)
 479 {
 480         unsigned int chunk_size = len;
 481         u32 val, loop;
 482
 483         val = loop = 0;
 484         while (len && loop < 4) {
 485                 val |= *buf++ << (8 * loop++);
 486                 len -= 1;
 487         }
 488
 489         intel_de_write_fw(dev_priv, GMBUS3, val);
 490         intel_de_write_fw(dev_priv, GMBUS1,
 491                           gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 492         while (len) {
 493                 int ret;
 494
 495                 val = loop = 0;
 496                 do {
 497                         val |= *buf++ << (8 * loop);
 498                 } while (--len && ++loop < 4);
 499
 500                 intel_de_write_fw(dev_priv, GMBUS3, val);
 501
 502                 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 503                 if (ret)
 504                         return ret;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int
 511 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 512                  u32 gmbus1_index)
 513 {
 514         u8 *buf = msg->buf;
 515         unsigned int tx_size = msg->len;
 516         unsigned int len;
 517         int ret;
 518
 519         do {
 520                 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
 521
 522                 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
 523                                              gmbus1_index);
 524                 if (ret)
 525                         return ret;
 526
 527                 buf += len;
 528                 tx_size -= len;
 529         } while (tx_size != 0);
 530
 531         return 0;
 532 }
 533
 534 /*
 535  * The gmbus controller can combine a 1 or 2 byte write with another read/write
 536  * that immediately follows it by using an "INDEX" cycle.
 537  */
 538 static bool
 539 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
 540 {
 541         return (i + 1 < num &&
 542                 msgs[i].addr == msgs[i + 1].addr &&
 543                 !(msgs[i].flags & I2C_M_RD) &&
 544                 (msgs[i].len == 1 || msgs[i].len == 2) &&
 545                 msgs[i + 1].len > 0);
 546 }
 547
 548 static int
 549 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
 550                  u32 gmbus0_reg)
 551 {
 552         u32 gmbus1_index = 0;
 553         u32 gmbus5 = 0;
 554         int ret;
 555
 556         if (msgs[0].len == 2)
 557                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 558                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 559         if (msgs[0].len == 1)
 560                 gmbus1_index = GMBUS_CYCLE_INDEX |
 561                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 562
 563         /* GMBUS5 holds 16-bit index */
 564         if (gmbus5)
 565                 intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
 566
 567         if (msgs[1].flags & I2C_M_RD)
 568                 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
 569                                       gmbus1_index);
 570         else
 571                 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
 572
 573         /* Clear GMBUS5 after each index transfer */
 574         if (gmbus5)
 575                 intel_de_write_fw(dev_priv, GMBUS5, 0);
 576
 577         return ret;
 578 }
 579
 580 static int
 581 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
 582               u32 gmbus0_source)
 583 {
 584         struct intel_gmbus *bus = container_of(adapter,
 585                                                struct intel_gmbus,
 586                                                adapter);
 587         struct drm_i915_private *dev_priv = bus->dev_priv;
 588         int i = 0, inc, try = 0;
 589         int ret = 0;
 590
 591         /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
 592         if (IS_GEN9_LP(dev_priv))
 593                 bxt_gmbus_clock_gating(dev_priv, false);
 594         else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
 595                 pch_gmbus_clock_gating(dev_priv, false);
 596
 597 retry:
 598         intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
 599
 600         for (; i < num; i += inc) {
 601                 inc = 1;
 602                 if (gmbus_is_index_xfer(msgs, i, num)) {
 603                         ret = gmbus_index_xfer(dev_priv, &msgs[i],
 604                                                gmbus0_source | bus->reg0);
 605                         inc = 2; /* an index transmission is two msgs */
 606                 } else if (msgs[i].flags & I2C_M_RD) {
 607                         ret = gmbus_xfer_read(dev_priv, &msgs[i],
 608                                               gmbus0_source | bus->reg0, 0);
 609                 } else {
 610                         ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
 611                 }
 612
 613                 if (!ret)
 614                         ret = gmbus_wait(dev_priv,
 615                                          GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
 616                 if (ret == -ETIMEDOUT)
 617                         goto timeout;
 618                 else if (ret)
 619                         goto clear_err;
 620         }
 621
 622         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 623          * a STOP on the very first cycle. To simplify the code we
 624          * unconditionally generate the STOP condition with an additional gmbus
 625          * cycle. */
 626         intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 627
 628         /* Mark the GMBUS interface as disabled after waiting for idle.
 629          * We will re-enable it at the start of the next xfer,
 630          * till then let it sleep.
 631          */
 632         if (gmbus_wait_idle(dev_priv)) {
 633                 drm_dbg_kms(&dev_priv->drm,
 634                             "GMBUS [%s] timed out waiting for idle\n",
 635                             adapter->name);
 636                 ret = -ETIMEDOUT;
 637         }
 638         intel_de_write_fw(dev_priv, GMBUS0, 0);
 639         ret = ret ?: i;
 640         goto out;
 641
 642 clear_err:
 643         /*
 644          * Wait for bus to IDLE before clearing NAK.
 645          * If we clear the NAK while bus is still active, then it will stay
 646          * active and the next transaction may fail.
 647          *
 648          * If no ACK is received during the address phase of a transaction, the
 649          * adapter must report -ENXIO. It is not clear what to return if no ACK
 650          * is received at other times. But we have to be careful to not return
 651          * spurious -ENXIO because that will prevent i2c and drm edid functions
 652          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 653          * timing out seems to happen when there _is_ a ddc chip present, but
 654          * it's slow responding and only answers on the 2nd retry.
 655          */
 656         ret = -ENXIO;
 657         if (gmbus_wait_idle(dev_priv)) {
 658                 drm_dbg_kms(&dev_priv->drm,
 659                             "GMBUS [%s] timed out after NAK\n",
 660                             adapter->name);
 661                 ret = -ETIMEDOUT;
 662         }
 663
 664         /* Toggle the Software Clear Interrupt bit. This has the effect
 665          * of resetting the GMBUS controller and so clearing the
 666          * BUS_ERROR raised by the slave's NAK.
 667          */
 668         intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
 669         intel_de_write_fw(dev_priv, GMBUS1, 0);
 670         intel_de_write_fw(dev_priv, GMBUS0, 0);
 671
 672         drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 673                     adapter->name, msgs[i].addr,
 674                     (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 675
 676         /*
 677          * Passive adapters sometimes NAK the first probe. Retry the first
 678          * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
 679          * has retries internally. See also the retry loop in
 680          * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
 681          */
 682         if (ret == -ENXIO && i == 0 && try++ == 0) {
 683                 drm_dbg_kms(&dev_priv->drm,
 684                             "GMBUS [%s] NAK on first message, retry\n",
 685                             adapter->name);
 686                 goto retry;
 687         }
 688
 689         goto out;
 690
 691 timeout:
 692         drm_dbg_kms(&dev_priv->drm,
 693                     "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 694                     bus->adapter.name, bus->reg0 & 0xff);
 695         intel_de_write_fw(dev_priv, GMBUS0, 0);
 696
 697         /*
 698          * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
 699          * instead. Use EAGAIN to have i2c core retry.
 700          */
 701         ret = -EAGAIN;
 702
 703 out:
 704         /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
 705         if (IS_GEN9_LP(dev_priv))
 706                 bxt_gmbus_clock_gating(dev_priv, true);
 707         else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
 708                 pch_gmbus_clock_gating(dev_priv, true);
 709
 710         return ret;
 711 }
 712
 713 static int
 714 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 715 {
 716         struct intel_gmbus *bus =
 717                 container_of(adapter, struct intel_gmbus, adapter);
 718         struct drm_i915_private *dev_priv = bus->dev_priv;
 719         intel_wakeref_t wakeref;
 720         int ret;
 721
 722         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 723
 724         if (bus->force_bit) {
 725                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 726                 if (ret < 0)
 727                         bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
 728         } else {
 729                 ret = do_gmbus_xfer(adapter, msgs, num, 0);
 730                 if (ret == -EAGAIN)
 731                         bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
 732         }
 733
 734         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
 735
 736         return ret;
 737 }
 738
 739 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
 740 {
 741         struct intel_gmbus *bus =
 742                 container_of(adapter, struct intel_gmbus, adapter);
 743         struct drm_i915_private *dev_priv = bus->dev_priv;
 744         u8 cmd = DRM_HDCP_DDC_AKSV;
 745         u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
 746         struct i2c_msg msgs[] = {
 747                 {
 748                         .addr = DRM_HDCP_DDC_ADDR,
 749                         .flags = 0,
 750                         .len = sizeof(cmd),
 751                         .buf = &cmd,
 752                 },
 753                 {
 754                         .addr = DRM_HDCP_DDC_ADDR,
 755                         .flags = 0,
 756                         .len = sizeof(buf),
 757                         .buf = buf,
 758                 }
 759         };
 760         intel_wakeref_t wakeref;
 761         int ret;
 762
 763         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 764         mutex_lock(&dev_priv->gmbus_mutex);
 765
 766         /*
 767          * In order to output Aksv to the receiver, use an indexed write to
 768          * pass the i2c command, and tell GMBUS to use the HW-provided value
 769          * instead of sourcing GMBUS3 for the data.
 770          */
 771         ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
 772
 773         mutex_unlock(&dev_priv->gmbus_mutex);
 774         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
 775
 776         return ret;
 777 }
 778
 779 static u32 gmbus_func(struct i2c_adapter *adapter)
 780 {
 781         return i2c_bit_algo.functionality(adapter) &
 782                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 783                 /* I2C_FUNC_10BIT_ADDR | */
 784                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 785                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 786 }
 787
 788 static const struct i2c_algorithm gmbus_algorithm = {
 789         .master_xfer    = gmbus_xfer,
 790         .functionality  = gmbus_func
 791 };
 792
 793 static void gmbus_lock_bus(struct i2c_adapter *adapter,
 794                            unsigned int flags)
 795 {
 796         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 797         struct drm_i915_private *dev_priv = bus->dev_priv;
 798
 799         mutex_lock(&dev_priv->gmbus_mutex);
 800 }
 801
 802 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
 803                              unsigned int flags)
 804 {
 805         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 806         struct drm_i915_private *dev_priv = bus->dev_priv;
 807
 808         return mutex_trylock(&dev_priv->gmbus_mutex);
 809 }
 810
 811 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
 812                              unsigned int flags)
 813 {
 814         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 815         struct drm_i915_private *dev_priv = bus->dev_priv;
 816
 817         mutex_unlock(&dev_priv->gmbus_mutex);
 818 }
 819
 820 static const struct i2c_lock_operations gmbus_lock_ops = {
 821         .lock_bus =    gmbus_lock_bus,
 822         .trylock_bus = gmbus_trylock_bus,
 823         .unlock_bus =  gmbus_unlock_bus,
 824 };
 825
 826 /**
 827  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 828  * @dev_priv: i915 device private
 829  */
 830 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
 831 {
 832         struct pci_dev *pdev = dev_priv->drm.pdev;
 833         struct intel_gmbus *bus;
 834         unsigned int pin;
 835         int ret;
 836
 837         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
 838                 return 0;
 839
 840         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 841                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 842         else if (!HAS_GMCH(dev_priv))
 843                 /*
 844                  * Broxton uses the same PCH offsets for South Display Engine,
 845                  * even though it doesn't have a PCH.
 846                  */
 847                 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
 848
 849         mutex_init(&dev_priv->gmbus_mutex);
 850         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 851
 852         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 853                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 854                         continue;
 855
 856                 bus = &dev_priv->gmbus[pin];
 857
 858                 bus->adapter.owner = THIS_MODULE;
 859                 bus->adapter.class = I2C_CLASS_DDC;
 860                 snprintf(bus->adapter.name,
 861                          sizeof(bus->adapter.name),
 862                          "i915 gmbus %s",
 863                          get_gmbus_pin(dev_priv, pin)->name);
 864
 865                 bus->adapter.dev.parent = &pdev->dev;
 866                 bus->dev_priv = dev_priv;
 867
 868                 bus->adapter.algo = &gmbus_algorithm;
 869                 bus->adapter.lock_ops = &gmbus_lock_ops;
 870
 871                 /*
 872                  * We wish to retry with bit banging
 873                  * after a timed out GMBUS attempt.
 874                  */
 875                 bus->adapter.retries = 1;
 876
 877                 /* By default use a conservative clock rate */
 878                 bus->reg0 = pin | GMBUS_RATE_100KHZ;
 879
 880                 /* gmbus seems to be broken on i830 */
 881                 if (IS_I830(dev_priv))
 882                         bus->force_bit = 1;
 883
 884                 intel_gpio_setup(bus, pin);
 885
 886                 ret = i2c_add_adapter(&bus->adapter);
 887                 if (ret)
 888                         goto err;
 889         }
 890
 891         intel_gmbus_reset(dev_priv);
 892
 893         return 0;
 894
 895 err:
 896         while (pin--) {
 897                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 898                         continue;
 899
 900                 bus = &dev_priv->gmbus[pin];
 901                 i2c_del_adapter(&bus->adapter);
 902         }
 903         return ret;
 904 }
 905
 906 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 907                                             unsigned int pin)
 908 {
 909         if (drm_WARN_ON(&dev_priv->drm,
 910                         !intel_gmbus_is_valid_pin(dev_priv, pin)))
 911                 return NULL;
 912
 913         return &dev_priv->gmbus[pin].adapter;
 914 }
 915
 916 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 917 {
 918         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 919
 920         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 921 }
 922
 923 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 924 {
 925         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 926         struct drm_i915_private *dev_priv = bus->dev_priv;
 927
 928         mutex_lock(&dev_priv->gmbus_mutex);
 929
 930         bus->force_bit += force_bit ? 1 : -1;
 931         drm_dbg_kms(&dev_priv->drm,
 932                     "%sabling bit-banging on %s. force bit now %d\n",
 933                     force_bit ? "en" : "dis", adapter->name,
 934                     bus->force_bit);
 935
 936         mutex_unlock(&dev_priv->gmbus_mutex);
 937 }
 938
 939 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
 940 {
 941         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 942
 943         return bus->force_bit;
 944 }
 945
 946 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
 947 {
 948         struct intel_gmbus *bus;
 949         unsigned int pin;
 950
 951         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 952                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 953                         continue;
 954
 955                 bus = &dev_priv->gmbus[pin];
 956                 i2c_del_adapter(&bus->adapter);
 957         }
 958 }