drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "i915_vgpu.h"
  46 #include "intel_display_types.h"
  47 #include "intel_fbc.h"
  48 #include "intel_frontbuffer.h"
  49
  50 /*
  51  * For SKL+, the plane source size used by the hardware is based on the value we
  52  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  53  * we wrote to PIPESRC.
  54  */
  55 static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
  56                                             int *width, int *height)
  57 {
  58         if (width)
  59                 *width = cache->plane.src_w;
  60         if (height)
  61                 *height = cache->plane.src_h;
  62 }
  63
  64 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  65                                         const struct intel_fbc_state_cache *cache)
  66 {
  67         int lines;
  68
  69         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  70         if (IS_GEN(dev_priv, 7))
  71                 lines = min(lines, 2048);
  72         else if (INTEL_GEN(dev_priv) >= 8)
  73                 lines = min(lines, 2560);
  74
  75         /* Hardware needs the full buffer stride, not just the active area. */
  76         return lines * cache->fb.stride;
  77 }
  78
  79 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  80 {
  81         u32 fbc_ctl;
  82
  83         /* Disable compression */
  84         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
  85         if ((fbc_ctl & FBC_CTL_EN) == 0)
  86                 return;
  87
  88         fbc_ctl &= ~FBC_CTL_EN;
  89         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
  90
  91         /* Wait for compressing bit to clear */
  92         if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
  93                                     FBC_STAT_COMPRESSING, 10)) {
  94                 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
  95                 return;
  96         }
  97 }
  98
  99 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 100 {
 101         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 102         int cfb_pitch;
 103         int i;
 104         u32 fbc_ctl;
 105
 106         /* Note: fbc.threshold == 1 for i8xx */
 107         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 108         if (params->fb.stride < cfb_pitch)
 109                 cfb_pitch = params->fb.stride;
 110
 111         /* FBC_CTL wants 32B or 64B units */
 112         if (IS_GEN(dev_priv, 2))
 113                 cfb_pitch = (cfb_pitch / 32) - 1;
 114         else
 115                 cfb_pitch = (cfb_pitch / 64) - 1;
 116
 117         /* Clear old tags */
 118         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 119                 intel_de_write(dev_priv, FBC_TAG(i), 0);
 120
 121         if (IS_GEN(dev_priv, 4)) {
 122                 u32 fbc_ctl2;
 123
 124                 /* Set it up... */
 125                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
 126                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 127                 if (params->fence_id >= 0)
 128                         fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 129                 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
 130                 intel_de_write(dev_priv, FBC_FENCE_OFF,
 131                                params->fence_y_offset);
 132         }
 133
 134         /* enable it... */
 135         fbc_ctl = FBC_CTL_INTERVAL(params->interval);
 136         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 137         if (IS_I945GM(dev_priv))
 138                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 139         fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff);
 140         if (params->fence_id >= 0)
 141                 fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
 142         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 143 }
 144
 145 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 146 {
 147         return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
 148 }
 149
 150 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 151 {
 152         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 153         u32 dpfc_ctl;
 154
 155         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 156         if (params->fb.format->cpp[0] == 2)
 157                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 158         else
 159                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 160
 161         if (params->fence_id >= 0) {
 162                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 163                 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
 164                                params->fence_y_offset);
 165         } else {
 166                 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
 167         }
 168
 169         /* enable it... */
 170         intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 171 }
 172
 173 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 174 {
 175         u32 dpfc_ctl;
 176
 177         /* Disable compression */
 178         dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
 179         if (dpfc_ctl & DPFC_CTL_EN) {
 180                 dpfc_ctl &= ~DPFC_CTL_EN;
 181                 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
 182         }
 183 }
 184
 185 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 186 {
 187         return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 188 }
 189
 190 static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
 191 {
 192         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 193         enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 194
 195         spin_lock_irq(&dev_priv->uncore.lock);
 196         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
 197                           intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
 198         spin_unlock_irq(&dev_priv->uncore.lock);
 199 }
 200
 201 static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
 202 {
 203         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 204         enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 205
 206         spin_lock_irq(&dev_priv->uncore.lock);
 207         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
 208                           intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
 209         spin_unlock_irq(&dev_priv->uncore.lock);
 210 }
 211
 212 /* This function forces a CFB recompression through the nuke operation. */
 213 static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
 214 {
 215         struct intel_fbc *fbc = &dev_priv->fbc;
 216
 217         trace_intel_fbc_nuke(fbc->crtc);
 218
 219         intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
 220         intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 221 }
 222
 223 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 224 {
 225         if (INTEL_GEN(dev_priv) >= 6)
 226                 snb_fbc_recompress(dev_priv);
 227         else if (INTEL_GEN(dev_priv) >= 4)
 228                 i965_fbc_recompress(dev_priv);
 229         else
 230                 i8xx_fbc_recompress(dev_priv);
 231 }
 232
 233 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 234 {
 235         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 236         u32 dpfc_ctl;
 237         int threshold = dev_priv->fbc.threshold;
 238
 239         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 240         if (params->fb.format->cpp[0] == 2)
 241                 threshold++;
 242
 243         switch (threshold) {
 244         case 4:
 245         case 3:
 246                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 247                 break;
 248         case 2:
 249                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 250                 break;
 251         case 1:
 252                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 253                 break;
 254         }
 255
 256         if (params->fence_id >= 0) {
 257                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 258                 if (IS_GEN(dev_priv, 5))
 259                         dpfc_ctl |= params->fence_id;
 260                 if (IS_GEN(dev_priv, 6)) {
 261                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 262                                        SNB_CPU_FENCE_ENABLE | params->fence_id);
 263                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 264                                        params->fence_y_offset);
 265                 }
 266         } else {
 267                 if (IS_GEN(dev_priv, 6)) {
 268                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 269                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 270                 }
 271         }
 272
 273         intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 274                        params->fence_y_offset);
 275         /* enable it... */
 276         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 277
 278         intel_fbc_recompress(dev_priv);
 279 }
 280
 281 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 282 {
 283         u32 dpfc_ctl;
 284
 285         /* Disable compression */
 286         dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 287         if (dpfc_ctl & DPFC_CTL_EN) {
 288                 dpfc_ctl &= ~DPFC_CTL_EN;
 289                 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
 290         }
 291 }
 292
 293 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 294 {
 295         return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 296 }
 297
 298 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 299 {
 300         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 301         u32 dpfc_ctl;
 302         int threshold = dev_priv->fbc.threshold;
 303
 304         /* Display WA #0529: skl, kbl, bxt. */
 305         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
 306                 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
 307
 308                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 309
 310                 if (params->gen9_wa_cfb_stride)
 311                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 312
 313                 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
 314         }
 315
 316         dpfc_ctl = 0;
 317         if (IS_IVYBRIDGE(dev_priv))
 318                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 319
 320         if (params->fb.format->cpp[0] == 2)
 321                 threshold++;
 322
 323         switch (threshold) {
 324         case 4:
 325         case 3:
 326                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 327                 break;
 328         case 2:
 329                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 330                 break;
 331         case 1:
 332                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 333                 break;
 334         }
 335
 336         if (params->fence_id >= 0) {
 337                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 338                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 339                                SNB_CPU_FENCE_ENABLE | params->fence_id);
 340                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 341                                params->fence_y_offset);
 342         } else if (dev_priv->ggtt.num_fences) {
 343                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 344                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 345         }
 346
 347         if (dev_priv->fbc.false_color)
 348                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 349
 350         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 351
 352         intel_fbc_recompress(dev_priv);
 353 }
 354
 355 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 356 {
 357         if (INTEL_GEN(dev_priv) >= 5)
 358                 return ilk_fbc_is_active(dev_priv);
 359         else if (IS_GM45(dev_priv))
 360                 return g4x_fbc_is_active(dev_priv);
 361         else
 362                 return i8xx_fbc_is_active(dev_priv);
 363 }
 364
 365 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 366 {
 367         struct intel_fbc *fbc = &dev_priv->fbc;
 368
 369         trace_intel_fbc_activate(fbc->crtc);
 370
 371         fbc->active = true;
 372         fbc->activated = true;
 373
 374         if (INTEL_GEN(dev_priv) >= 7)
 375                 gen7_fbc_activate(dev_priv);
 376         else if (INTEL_GEN(dev_priv) >= 5)
 377                 ilk_fbc_activate(dev_priv);
 378         else if (IS_GM45(dev_priv))
 379                 g4x_fbc_activate(dev_priv);
 380         else
 381                 i8xx_fbc_activate(dev_priv);
 382 }
 383
 384 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 385 {
 386         struct intel_fbc *fbc = &dev_priv->fbc;
 387
 388         trace_intel_fbc_deactivate(fbc->crtc);
 389
 390         fbc->active = false;
 391
 392         if (INTEL_GEN(dev_priv) >= 5)
 393                 ilk_fbc_deactivate(dev_priv);
 394         else if (IS_GM45(dev_priv))
 395                 g4x_fbc_deactivate(dev_priv);
 396         else
 397                 i8xx_fbc_deactivate(dev_priv);
 398 }
 399
 400 /**
 401  * intel_fbc_is_active - Is FBC active?
 402  * @dev_priv: i915 device instance
 403  *
 404  * This function is used to verify the current state of FBC.
 405  *
 406  * FIXME: This should be tracked in the plane config eventually
 407  * instead of queried at runtime for most callers.
 408  */
 409 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 410 {
 411         return dev_priv->fbc.active;
 412 }
 413
 414 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 415                                  const char *reason)
 416 {
 417         struct intel_fbc *fbc = &dev_priv->fbc;
 418
 419         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 420
 421         if (fbc->active)
 422                 intel_fbc_hw_deactivate(dev_priv);
 423
 424         fbc->no_fbc_reason = reason;
 425 }
 426
 427 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 428                                       struct drm_mm_node *node,
 429                                       unsigned int size,
 430                                       unsigned int fb_cpp)
 431 {
 432         int compression_threshold = 1;
 433         int ret;
 434         u64 end;
 435
 436         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 437          * reserved range size, so it always assumes the maximum (8mb) is used.
 438          * If we enable FBC using a CFB on that memory range we'll get FIFO
 439          * underruns, even if that range is not reserved by the BIOS. */
 440         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 441                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 442         else
 443                 end = U64_MAX;
 444
 445         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 446          * code changes, this code needs to change as well.
 447          *
 448          * The enable_fbc code will attempt to use one of our 2 compression
 449          * thresholds, therefore, in that case, we only have 1 resort.
 450          */
 451
 452         /* Try to over-allocate to reduce reallocations and fragmentation. */
 453         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 454                                                    4096, 0, end);
 455         if (ret == 0)
 456                 return compression_threshold;
 457
 458 again:
 459         /* HW's ability to limit the CFB is 1:4 */
 460         if (compression_threshold > 4 ||
 461             (fb_cpp == 2 && compression_threshold == 2))
 462                 return 0;
 463
 464         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 465                                                    4096, 0, end);
 466         if (ret && INTEL_GEN(dev_priv) <= 4) {
 467                 return 0;
 468         } else if (ret) {
 469                 compression_threshold <<= 1;
 470                 goto again;
 471         } else {
 472                 return compression_threshold;
 473         }
 474 }
 475
 476 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 477                                unsigned int size, unsigned int fb_cpp)
 478 {
 479         struct intel_fbc *fbc = &dev_priv->fbc;
 480         struct drm_mm_node *compressed_llb;
 481         int ret;
 482
 483         drm_WARN_ON(&dev_priv->drm,
 484                     drm_mm_node_allocated(&fbc->compressed_fb));
 485
 486         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 487                                          size, fb_cpp);
 488         if (!ret)
 489                 goto err_llb;
 490         else if (ret > 1) {
 491                 drm_info_once(&dev_priv->drm,
 492                               "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 493         }
 494
 495         fbc->threshold = ret;
 496
 497         if (INTEL_GEN(dev_priv) >= 5)
 498                 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
 499                                fbc->compressed_fb.start);
 500         else if (IS_GM45(dev_priv)) {
 501                 intel_de_write(dev_priv, DPFC_CB_BASE,
 502                                fbc->compressed_fb.start);
 503         } else {
 504                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 505                 if (!compressed_llb)
 506                         goto err_fb;
 507
 508                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 509                                                   4096, 4096);
 510                 if (ret)
 511                         goto err_fb;
 512
 513                 fbc->compressed_llb = compressed_llb;
 514
 515                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 516                                                  fbc->compressed_fb.start,
 517                                                  U32_MAX));
 518                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 519                                                  fbc->compressed_llb->start,
 520                                                  U32_MAX));
 521                 intel_de_write(dev_priv, FBC_CFB_BASE,
 522                                dev_priv->dsm.start + fbc->compressed_fb.start);
 523                 intel_de_write(dev_priv, FBC_LL_BASE,
 524                                dev_priv->dsm.start + compressed_llb->start);
 525         }
 526
 527         drm_dbg_kms(&dev_priv->drm,
 528                     "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 529                     fbc->compressed_fb.size, fbc->threshold);
 530
 531         return 0;
 532
 533 err_fb:
 534         kfree(compressed_llb);
 535         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 536 err_llb:
 537         if (drm_mm_initialized(&dev_priv->mm.stolen))
 538                 drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 539         return -ENOSPC;
 540 }
 541
 542 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 543 {
 544         struct intel_fbc *fbc = &dev_priv->fbc;
 545
 546         if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
 547                 return;
 548
 549         if (!drm_mm_node_allocated(&fbc->compressed_fb))
 550                 return;
 551
 552         if (fbc->compressed_llb) {
 553                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 554                 kfree(fbc->compressed_llb);
 555         }
 556
 557         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 558 }
 559
 560 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 561 {
 562         struct intel_fbc *fbc = &dev_priv->fbc;
 563
 564         if (!HAS_FBC(dev_priv))
 565                 return;
 566
 567         mutex_lock(&fbc->lock);
 568         __intel_fbc_cleanup_cfb(dev_priv);
 569         mutex_unlock(&fbc->lock);
 570 }
 571
 572 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 573                             u64 modifier, unsigned int stride)
 574 {
 575         /* This should have been caught earlier. */
 576         if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
 577                 return false;
 578
 579         /* Below are the additional FBC restrictions. */
 580         if (stride < 512)
 581                 return false;
 582
 583         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 584                 return stride == 4096 || stride == 8192;
 585
 586         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 587                 return false;
 588
 589         /* Display WA #1105: skl,bxt,kbl,cfl,glk */
 590         if (IS_GEN(dev_priv, 9) &&
 591             modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
 592                 return false;
 593
 594         if (stride > 16384)
 595                 return false;
 596
 597         return true;
 598 }
 599
 600 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 601                                   u32 pixel_format)
 602 {
 603         switch (pixel_format) {
 604         case DRM_FORMAT_XRGB8888:
 605         case DRM_FORMAT_XBGR8888:
 606                 return true;
 607         case DRM_FORMAT_XRGB1555:
 608         case DRM_FORMAT_RGB565:
 609                 /* 16bpp not supported on gen2 */
 610                 if (IS_GEN(dev_priv, 2))
 611                         return false;
 612                 /* WaFbcOnly1to1Ratio:ctg */
 613                 if (IS_G4X(dev_priv))
 614                         return false;
 615                 return true;
 616         default:
 617                 return false;
 618         }
 619 }
 620
 621 static bool rotation_is_valid(struct drm_i915_private *dev_priv,
 622                               u32 pixel_format, unsigned int rotation)
 623 {
 624         if (INTEL_GEN(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
 625             drm_rotation_90_or_270(rotation))
 626                 return false;
 627         else if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 628                  rotation != DRM_MODE_ROTATE_0)
 629                 return false;
 630
 631         return true;
 632 }
 633
 634 /*
 635  * For some reason, the hardware tracking starts looking at whatever we
 636  * programmed as the display plane base address register. It does not look at
 637  * the X and Y offset registers. That's why we include the src x/y offsets
 638  * instead of just looking at the plane size.
 639  */
 640 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 641 {
 642         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 643         struct intel_fbc *fbc = &dev_priv->fbc;
 644         unsigned int effective_w, effective_h, max_w, max_h;
 645
 646         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 647                 max_w = 5120;
 648                 max_h = 4096;
 649         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 650                 max_w = 4096;
 651                 max_h = 4096;
 652         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 653                 max_w = 4096;
 654                 max_h = 2048;
 655         } else {
 656                 max_w = 2048;
 657                 max_h = 1536;
 658         }
 659
 660         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 661                                         &effective_h);
 662         effective_w += fbc->state_cache.plane.adjusted_x;
 663         effective_h += fbc->state_cache.plane.adjusted_y;
 664
 665         return effective_w <= max_w && effective_h <= max_h;
 666 }
 667
 668 static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 669                             uint64_t modifier)
 670 {
 671         switch (modifier) {
 672         case DRM_FORMAT_MOD_LINEAR:
 673                 if (INTEL_GEN(dev_priv) >= 9)
 674                         return true;
 675                 return false;
 676         case I915_FORMAT_MOD_X_TILED:
 677         case I915_FORMAT_MOD_Y_TILED:
 678                 return true;
 679         default:
 680                 return false;
 681         }
 682 }
 683
 684 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 685                                          const struct intel_crtc_state *crtc_state,
 686                                          const struct intel_plane_state *plane_state)
 687 {
 688         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 689         struct intel_fbc *fbc = &dev_priv->fbc;
 690         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 691         struct drm_framebuffer *fb = plane_state->hw.fb;
 692
 693         cache->plane.visible = plane_state->uapi.visible;
 694         if (!cache->plane.visible)
 695                 return;
 696
 697         cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 698         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 699                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 700
 701         cache->plane.rotation = plane_state->hw.rotation;
 702         /*
 703          * Src coordinates are already rotated by 270 degrees for
 704          * the 90/270 degree plane rotation cases (to match the
 705          * GTT mapping), hence no need to account for rotation here.
 706          */
 707         cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 708         cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 709         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 710         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 711
 712         cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 713
 714         cache->fb.format = fb->format;
 715         cache->fb.modifier = fb->modifier;
 716
 717         /* FIXME is this correct? */
 718         cache->fb.stride = plane_state->color_plane[0].stride;
 719         if (drm_rotation_90_or_270(plane_state->hw.rotation))
 720                 cache->fb.stride *= fb->format->cpp[0];
 721
 722         /* FBC1 compression interval: arbitrary choice of 1 second */
 723         cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 724
 725         cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
 726
 727         drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
 728                     !plane_state->vma->fence);
 729
 730         if (plane_state->flags & PLANE_HAS_FENCE &&
 731             plane_state->vma->fence)
 732                 cache->fence_id = plane_state->vma->fence->id;
 733         else
 734                 cache->fence_id = -1;
 735 }
 736
 737 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
 738 {
 739         struct intel_fbc *fbc = &dev_priv->fbc;
 740
 741         return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 742                 fbc->compressed_fb.size * fbc->threshold;
 743 }
 744
 745 static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
 746 {
 747         struct intel_fbc *fbc = &dev_priv->fbc;
 748         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 749
 750         if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
 751             cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
 752                 return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
 753         else
 754                 return 0;
 755 }
 756
 757 static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
 758 {
 759         struct intel_fbc *fbc = &dev_priv->fbc;
 760
 761         return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
 762 }
 763
 764 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 765 {
 766         struct intel_fbc *fbc = &dev_priv->fbc;
 767
 768         if (intel_vgpu_active(dev_priv)) {
 769                 fbc->no_fbc_reason = "VGPU is active";
 770                 return false;
 771         }
 772
 773         if (!dev_priv->params.enable_fbc) {
 774                 fbc->no_fbc_reason = "disabled per module param or by default";
 775                 return false;
 776         }
 777
 778         if (fbc->underrun_detected) {
 779                 fbc->no_fbc_reason = "underrun detected";
 780                 return false;
 781         }
 782
 783         return true;
 784 }
 785
 786 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 787 {
 788         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 789         struct intel_fbc *fbc = &dev_priv->fbc;
 790         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 791
 792         if (!intel_fbc_can_enable(dev_priv))
 793                 return false;
 794
 795         if (!cache->plane.visible) {
 796                 fbc->no_fbc_reason = "primary plane not visible";
 797                 return false;
 798         }
 799
 800         /* We don't need to use a state cache here since this information is
 801          * global for all CRTC.
 802          */
 803         if (fbc->underrun_detected) {
 804                 fbc->no_fbc_reason = "underrun detected";
 805                 return false;
 806         }
 807
 808         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 809                 fbc->no_fbc_reason = "incompatible mode";
 810                 return false;
 811         }
 812
 813         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 814                 fbc->no_fbc_reason = "mode too large for compression";
 815                 return false;
 816         }
 817
 818         /* The use of a CPU fence is one of two ways to detect writes by the
 819          * CPU to the scanout and trigger updates to the FBC.
 820          *
 821          * The other method is by software tracking (see
 822          * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
 823          * the current compressed buffer and recompress it.
 824          *
 825          * Note that is possible for a tiled surface to be unmappable (and
 826          * so have no fence associated with it) due to aperture constraints
 827          * at the time of pinning.
 828          *
 829          * FIXME with 90/270 degree rotation we should use the fence on
 830          * the normal GTT view (the rotated view doesn't even have a
 831          * fence). Would need changes to the FBC fence Y offset as well.
 832          * For now this will effectively disable FBC with 90/270 degree
 833          * rotation.
 834          */
 835         if (INTEL_GEN(dev_priv) < 9 && cache->fence_id < 0) {
 836                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 837                 return false;
 838         }
 839
 840         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 841                 fbc->no_fbc_reason = "pixel format is invalid";
 842                 return false;
 843         }
 844
 845         if (!rotation_is_valid(dev_priv, cache->fb.format->format,
 846                                cache->plane.rotation)) {
 847                 fbc->no_fbc_reason = "rotation unsupported";
 848                 return false;
 849         }
 850
 851         if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
 852                 fbc->no_fbc_reason = "tiling unsupported";
 853                 return false;
 854         }
 855
 856         if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
 857                 fbc->no_fbc_reason = "framebuffer stride not supported";
 858                 return false;
 859         }
 860
 861         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 862             cache->fb.format->has_alpha) {
 863                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 864                 return false;
 865         }
 866
 867         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 868         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 869             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 870                 fbc->no_fbc_reason = "pixel rate is too big";
 871                 return false;
 872         }
 873
 874         /* It is possible for the required CFB size change without a
 875          * crtc->disable + crtc->enable since it is possible to change the
 876          * stride without triggering a full modeset. Since we try to
 877          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 878          * if this happens, but if we exceed the current CFB size we'll have to
 879          * disable FBC. Notice that it would be possible to disable FBC, wait
 880          * for a frame, free the stolen node, then try to reenable FBC in case
 881          * we didn't get any invalidate/deactivate calls, but this would require
 882          * a lot of tracking just for a specific case. If we conclude it's an
 883          * important case, we can implement it later. */
 884         if (intel_fbc_cfb_size_changed(dev_priv)) {
 885                 fbc->no_fbc_reason = "CFB requirements changed";
 886                 return false;
 887         }
 888
 889         /*
 890          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 891          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 892          * and screen flicker.
 893          */
 894         if (INTEL_GEN(dev_priv) >= 9 &&
 895             (fbc->state_cache.plane.adjusted_y & 3)) {
 896                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 897                 return false;
 898         }
 899
 900         return true;
 901 }
 902
 903 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 904                                      struct intel_fbc_reg_params *params)
 905 {
 906         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 907         struct intel_fbc *fbc = &dev_priv->fbc;
 908         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 909
 910         /* Since all our fields are integer types, use memset here so the
 911          * comparison function can rely on memcmp because the padding will be
 912          * zero. */
 913         memset(params, 0, sizeof(*params));
 914
 915         params->fence_id = cache->fence_id;
 916         params->fence_y_offset = cache->fence_y_offset;
 917
 918         params->interval = cache->interval;
 919
 920         params->crtc.pipe = crtc->pipe;
 921         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 922
 923         params->fb.format = cache->fb.format;
 924         params->fb.modifier = cache->fb.modifier;
 925         params->fb.stride = cache->fb.stride;
 926
 927         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 928
 929         params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 930
 931         params->plane_visible = cache->plane.visible;
 932 }
 933
 934 static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
 935 {
 936         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 937         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 938         const struct intel_fbc *fbc = &dev_priv->fbc;
 939         const struct intel_fbc_state_cache *cache = &fbc->state_cache;
 940         const struct intel_fbc_reg_params *params = &fbc->params;
 941
 942         if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 943                 return false;
 944
 945         if (!params->plane_visible)
 946                 return false;
 947
 948         if (!intel_fbc_can_activate(crtc))
 949                 return false;
 950
 951         if (params->fb.format != cache->fb.format)
 952                 return false;
 953
 954         if (params->fb.modifier != cache->fb.modifier)
 955                 return false;
 956
 957         if (params->fb.stride != cache->fb.stride)
 958                 return false;
 959
 960         if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
 961                 return false;
 962
 963         if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
 964                 return false;
 965
 966         return true;
 967 }
 968
 969 bool intel_fbc_pre_update(struct intel_atomic_state *state,
 970                           struct intel_crtc *crtc)
 971 {
 972         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 973         const struct intel_crtc_state *crtc_state =
 974                 intel_atomic_get_new_crtc_state(state, crtc);
 975         const struct intel_plane_state *plane_state =
 976                 intel_atomic_get_new_plane_state(state, plane);
 977         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 978         struct intel_fbc *fbc = &dev_priv->fbc;
 979         const char *reason = "update pending";
 980         bool need_vblank_wait = false;
 981
 982         if (!plane->has_fbc || !plane_state)
 983                 return need_vblank_wait;
 984
 985         mutex_lock(&fbc->lock);
 986
 987         if (fbc->crtc != crtc)
 988                 goto unlock;
 989
 990         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 991         fbc->flip_pending = true;
 992
 993         if (!intel_fbc_can_flip_nuke(crtc_state)) {
 994                 intel_fbc_deactivate(dev_priv, reason);
 995
 996                 /*
 997                  * Display WA #1198: glk+
 998                  * Need an extra vblank wait between FBC disable and most plane
 999                  * updates. Bspec says this is only needed for plane disable, but
1000                  * that is not true. Touching most plane registers will cause the
1001                  * corruption to appear. Also SKL/derivatives do not seem to be
1002                  * affected.
1003                  *
1004                  * TODO: could optimize this a bit by sampling the frame
1005                  * counter when we disable FBC (if it was already done earlier)
1006                  * and skipping the extra vblank wait before the plane update
1007                  * if at least one frame has already passed.
1008                  */
1009                 if (fbc->activated &&
1010                     (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
1011                         need_vblank_wait = true;
1012                 fbc->activated = false;
1013         }
1014 unlock:
1015         mutex_unlock(&fbc->lock);
1016
1017         return need_vblank_wait;
1018 }
1019
1020 /**
1021  * __intel_fbc_disable - disable FBC
1022  * @dev_priv: i915 device instance
1023  *
1024  * This is the low level function that actually disables FBC. Callers should
1025  * grab the FBC lock.
1026  */
1027 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1028 {
1029         struct intel_fbc *fbc = &dev_priv->fbc;
1030         struct intel_crtc *crtc = fbc->crtc;
1031
1032         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1033         drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
1034         drm_WARN_ON(&dev_priv->drm, fbc->active);
1035
1036         drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
1037                     pipe_name(crtc->pipe));
1038
1039         __intel_fbc_cleanup_cfb(dev_priv);
1040
1041         fbc->crtc = NULL;
1042 }
1043
1044 static void __intel_fbc_post_update(struct intel_crtc *crtc)
1045 {
1046         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1047         struct intel_fbc *fbc = &dev_priv->fbc;
1048
1049         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1050
1051         if (fbc->crtc != crtc)
1052                 return;
1053
1054         fbc->flip_pending = false;
1055
1056         if (!dev_priv->params.enable_fbc) {
1057                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1058                 __intel_fbc_disable(dev_priv);
1059
1060                 return;
1061         }
1062
1063         intel_fbc_get_reg_params(crtc, &fbc->params);
1064
1065         if (!intel_fbc_can_activate(crtc))
1066                 return;
1067
1068         if (!fbc->busy_bits)
1069                 intel_fbc_hw_activate(dev_priv);
1070         else
1071                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1072 }
1073
1074 void intel_fbc_post_update(struct intel_atomic_state *state,
1075                            struct intel_crtc *crtc)
1076 {
1077         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1078         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1079         const struct intel_plane_state *plane_state =
1080                 intel_atomic_get_new_plane_state(state, plane);
1081         struct intel_fbc *fbc = &dev_priv->fbc;
1082
1083         if (!plane->has_fbc || !plane_state)
1084                 return;
1085
1086         mutex_lock(&fbc->lock);
1087         __intel_fbc_post_update(crtc);
1088         mutex_unlock(&fbc->lock);
1089 }
1090
1091 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1092 {
1093         if (fbc->crtc)
1094                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1095         else
1096                 return fbc->possible_framebuffer_bits;
1097 }
1098
1099 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1100                           unsigned int frontbuffer_bits,
1101                           enum fb_op_origin origin)
1102 {
1103         struct intel_fbc *fbc = &dev_priv->fbc;
1104
1105         if (!HAS_FBC(dev_priv))
1106                 return;
1107
1108         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1109                 return;
1110
1111         mutex_lock(&fbc->lock);
1112
1113         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1114
1115         if (fbc->crtc && fbc->busy_bits)
1116                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1117
1118         mutex_unlock(&fbc->lock);
1119 }
1120
1121 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1122                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1123 {
1124         struct intel_fbc *fbc = &dev_priv->fbc;
1125
1126         if (!HAS_FBC(dev_priv))
1127                 return;
1128
1129         /*
1130          * GTT tracking does not nuke the entire cfb
1131          * so don't clear busy_bits set for some other
1132          * reason.
1133          */
1134         if (origin == ORIGIN_GTT)
1135                 return;
1136
1137         mutex_lock(&fbc->lock);
1138
1139         fbc->busy_bits &= ~frontbuffer_bits;
1140
1141         if (origin == ORIGIN_FLIP)
1142                 goto out;
1143
1144         if (!fbc->busy_bits && fbc->crtc &&
1145             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1146                 if (fbc->active)
1147                         intel_fbc_recompress(dev_priv);
1148                 else if (!fbc->flip_pending)
1149                         __intel_fbc_post_update(fbc->crtc);
1150         }
1151
1152 out:
1153         mutex_unlock(&fbc->lock);
1154 }
1155
1156 /**
1157  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1158  * @dev_priv: i915 device instance
1159  * @state: the atomic state structure
1160  *
1161  * This function looks at the proposed state for CRTCs and planes, then chooses
1162  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1163  * true.
1164  *
1165  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1166  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1167  */
1168 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1169                            struct intel_atomic_state *state)
1170 {
1171         struct intel_fbc *fbc = &dev_priv->fbc;
1172         struct intel_plane *plane;
1173         struct intel_plane_state *plane_state;
1174         bool crtc_chosen = false;
1175         int i;
1176
1177         mutex_lock(&fbc->lock);
1178
1179         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1180         if (fbc->crtc &&
1181             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1182                 goto out;
1183
1184         if (!intel_fbc_can_enable(dev_priv))
1185                 goto out;
1186
1187         /* Simply choose the first CRTC that is compatible and has a visible
1188          * plane. We could go for fancier schemes such as checking the plane
1189          * size, but this would just affect the few platforms that don't tie FBC
1190          * to pipe or plane A. */
1191         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1192                 struct intel_crtc_state *crtc_state;
1193                 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1194
1195                 if (!plane->has_fbc)
1196                         continue;
1197
1198                 if (!plane_state->uapi.visible)
1199                         continue;
1200
1201                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1202
1203                 crtc_state->enable_fbc = true;
1204                 crtc_chosen = true;
1205                 break;
1206         }
1207
1208         if (!crtc_chosen)
1209                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1210
1211 out:
1212         mutex_unlock(&fbc->lock);
1213 }
1214
1215 /**
1216  * intel_fbc_enable: tries to enable FBC on the CRTC
1217  * @crtc: the CRTC
1218  * @state: corresponding &drm_crtc_state for @crtc
1219  *
1220  * This function checks if the given CRTC was chosen for FBC, then enables it if
1221  * possible. Notice that it doesn't activate FBC. It is valid to call
1222  * intel_fbc_enable multiple times for the same pipe without an
1223  * intel_fbc_disable in the middle, as long as it is deactivated.
1224  */
1225 void intel_fbc_enable(struct intel_atomic_state *state,
1226                       struct intel_crtc *crtc)
1227 {
1228         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1229         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1230         const struct intel_crtc_state *crtc_state =
1231                 intel_atomic_get_new_crtc_state(state, crtc);
1232         const struct intel_plane_state *plane_state =
1233                 intel_atomic_get_new_plane_state(state, plane);
1234         struct intel_fbc *fbc = &dev_priv->fbc;
1235         struct intel_fbc_state_cache *cache = &fbc->state_cache;
1236
1237         if (!plane->has_fbc || !plane_state)
1238                 return;
1239
1240         mutex_lock(&fbc->lock);
1241
1242         if (fbc->crtc) {
1243                 if (fbc->crtc != crtc ||
1244                     (!intel_fbc_cfb_size_changed(dev_priv) &&
1245                      !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
1246                         goto out;
1247
1248                 __intel_fbc_disable(dev_priv);
1249         }
1250
1251         drm_WARN_ON(&dev_priv->drm, fbc->active);
1252
1253         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1254
1255         /* FIXME crtc_state->enable_fbc lies :( */
1256         if (!cache->plane.visible)
1257                 goto out;
1258
1259         if (intel_fbc_alloc_cfb(dev_priv,
1260                                 intel_fbc_calculate_cfb_size(dev_priv, cache),
1261                                 plane_state->hw.fb->format->cpp[0])) {
1262                 cache->plane.visible = false;
1263                 fbc->no_fbc_reason = "not enough stolen memory";
1264                 goto out;
1265         }
1266
1267         cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
1268
1269         drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1270                     pipe_name(crtc->pipe));
1271         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1272
1273         fbc->crtc = crtc;
1274 out:
1275         mutex_unlock(&fbc->lock);
1276 }
1277
1278 /**
1279  * intel_fbc_disable - disable FBC if it's associated with crtc
1280  * @crtc: the CRTC
1281  *
1282  * This function disables FBC if it's associated with the provided CRTC.
1283  */
1284 void intel_fbc_disable(struct intel_crtc *crtc)
1285 {
1286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1287         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1288         struct intel_fbc *fbc = &dev_priv->fbc;
1289
1290         if (!plane->has_fbc)
1291                 return;
1292
1293         mutex_lock(&fbc->lock);
1294         if (fbc->crtc == crtc)
1295                 __intel_fbc_disable(dev_priv);
1296         mutex_unlock(&fbc->lock);
1297 }
1298
1299 /**
1300  * intel_fbc_global_disable - globally disable FBC
1301  * @dev_priv: i915 device instance
1302  *
1303  * This function disables FBC regardless of which CRTC is associated with it.
1304  */
1305 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1306 {
1307         struct intel_fbc *fbc = &dev_priv->fbc;
1308
1309         if (!HAS_FBC(dev_priv))
1310                 return;
1311
1312         mutex_lock(&fbc->lock);
1313         if (fbc->crtc) {
1314                 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1315                 __intel_fbc_disable(dev_priv);
1316         }
1317         mutex_unlock(&fbc->lock);
1318 }
1319
1320 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1321 {
1322         struct drm_i915_private *dev_priv =
1323                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1324         struct intel_fbc *fbc = &dev_priv->fbc;
1325
1326         mutex_lock(&fbc->lock);
1327
1328         /* Maybe we were scheduled twice. */
1329         if (fbc->underrun_detected || !fbc->crtc)
1330                 goto out;
1331
1332         drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1333         fbc->underrun_detected = true;
1334
1335         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1336 out:
1337         mutex_unlock(&fbc->lock);
1338 }
1339
1340 /*
1341  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1342  * @dev_priv: i915 device instance
1343  *
1344  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1345  * want to re-enable FBC after an underrun to increase test coverage.
1346  */
1347 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1348 {
1349         int ret;
1350
1351         cancel_work_sync(&dev_priv->fbc.underrun_work);
1352
1353         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1354         if (ret)
1355                 return ret;
1356
1357         if (dev_priv->fbc.underrun_detected) {
1358                 drm_dbg_kms(&dev_priv->drm,
1359                             "Re-allowing FBC after fifo underrun\n");
1360                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1361         }
1362
1363         dev_priv->fbc.underrun_detected = false;
1364         mutex_unlock(&dev_priv->fbc.lock);
1365
1366         return 0;
1367 }
1368
1369 /**
1370  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1371  * @dev_priv: i915 device instance
1372  *
1373  * Without FBC, most underruns are harmless and don't really cause too many
1374  * problems, except for an annoying message on dmesg. With FBC, underruns can
1375  * become black screens or even worse, especially when paired with bad
1376  * watermarks. So in order for us to be on the safe side, completely disable FBC
1377  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1378  * already suggests that watermarks may be bad, so try to be as safe as
1379  * possible.
1380  *
1381  * This function is called from the IRQ handler.
1382  */
1383 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1384 {
1385         struct intel_fbc *fbc = &dev_priv->fbc;
1386
1387         if (!HAS_FBC(dev_priv))
1388                 return;
1389
1390         /* There's no guarantee that underrun_detected won't be set to true
1391          * right after this check and before the work is scheduled, but that's
1392          * not a problem since we'll check it again under the work function
1393          * while FBC is locked. This check here is just to prevent us from
1394          * unnecessarily scheduling the work, and it relies on the fact that we
1395          * never switch underrun_detect back to false after it's true. */
1396         if (READ_ONCE(fbc->underrun_detected))
1397                 return;
1398
1399         schedule_work(&fbc->underrun_work);
1400 }
1401
1402 /*
1403  * The DDX driver changes its behavior depending on the value it reads from
1404  * i915.enable_fbc, so sanitize it by translating the default value into either
1405  * 0 or 1 in order to allow it to know what's going on.
1406  *
1407  * Notice that this is done at driver initialization and we still allow user
1408  * space to change the value during runtime without sanitizing it again. IGT
1409  * relies on being able to change i915.enable_fbc at runtime.
1410  */
1411 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1412 {
1413         if (dev_priv->params.enable_fbc >= 0)
1414                 return !!dev_priv->params.enable_fbc;
1415
1416         if (!HAS_FBC(dev_priv))
1417                 return 0;
1418
1419         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1420                 return 1;
1421
1422         return 0;
1423 }
1424
1425 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1426 {
1427         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1428         if (intel_vtd_active() &&
1429             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1430                 drm_info(&dev_priv->drm,
1431                          "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1432                 return true;
1433         }
1434
1435         return false;
1436 }
1437
1438 /**
1439  * intel_fbc_init - Initialize FBC
1440  * @dev_priv: the i915 device
1441  *
1442  * This function might be called during PM init process.
1443  */
1444 void intel_fbc_init(struct drm_i915_private *dev_priv)
1445 {
1446         struct intel_fbc *fbc = &dev_priv->fbc;
1447
1448         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1449         mutex_init(&fbc->lock);
1450         fbc->active = false;
1451
1452         if (!drm_mm_initialized(&dev_priv->mm.stolen))
1453                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1454
1455         if (need_fbc_vtd_wa(dev_priv))
1456                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1457
1458         dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1459         drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1460                     dev_priv->params.enable_fbc);
1461
1462         if (!HAS_FBC(dev_priv)) {
1463                 fbc->no_fbc_reason = "unsupported by this chipset";
1464                 return;
1465         }
1466
1467         /* We still don't have any sort of hardware state readout for FBC, so
1468          * deactivate it in case the BIOS activated it to make sure software
1469          * matches the hardware state. */
1470         if (intel_fbc_hw_is_active(dev_priv))
1471                 intel_fbc_hw_deactivate(dev_priv);
1472 }