drivers/gpu/drm/i915/display/intel_fb.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2021 Intel Corporation
   4  */
   5
   6 #include <drm/drm_blend.h>
   7 #include <drm/drm_framebuffer.h>
   8 #include <drm/drm_modeset_helper.h>
   9
  10 #include "i915_drv.h"
  11 #include "intel_display.h"
  12 #include "intel_display_types.h"
  13 #include "intel_dpt.h"
  14 #include "intel_fb.h"
  15
  16 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
  17
  18 /*
  19  * From the Sky Lake PRM:
  20  * "The Color Control Surface (CCS) contains the compression status of
  21  *  the cache-line pairs. The compression state of the cache-line pair
  22  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
  23  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
  24  *  cache-line-pairs. CCS is always Y tiled."
  25  *
  26  * Since cache line pairs refers to horizontally adjacent cache lines,
  27  * each cache line in the CCS corresponds to an area of 32x16 cache
  28  * lines on the main surface. Since each pixel is 4 bytes, this gives
  29  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  30  * main surface.
  31  */
  32 static const struct drm_format_info skl_ccs_formats[] = {
  33         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
  34           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
  35         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
  36           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
  37         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
  38           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
  39         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
  40           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
  41 };
  42
  43 /*
  44  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
  45  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
  46  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
  47  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
  48  * the main surface.
  49  */
  50 static const struct drm_format_info gen12_ccs_formats[] = {
  51         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
  52           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  53           .hsub = 1, .vsub = 1, },
  54         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
  55           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  56           .hsub = 1, .vsub = 1, },
  57         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
  58           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  59           .hsub = 1, .vsub = 1, .has_alpha = true },
  60         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
  61           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  62           .hsub = 1, .vsub = 1, .has_alpha = true },
  63         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
  64           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  65           .hsub = 2, .vsub = 1, .is_yuv = true },
  66         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
  67           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  68           .hsub = 2, .vsub = 1, .is_yuv = true },
  69         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
  70           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  71           .hsub = 2, .vsub = 1, .is_yuv = true },
  72         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
  73           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  74           .hsub = 2, .vsub = 1, .is_yuv = true },
  75         { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
  76           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  77           .hsub = 1, .vsub = 1, .is_yuv = true },
  78         { .format = DRM_FORMAT_NV12, .num_planes = 4,
  79           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
  80           .hsub = 2, .vsub = 2, .is_yuv = true },
  81         { .format = DRM_FORMAT_P010, .num_planes = 4,
  82           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
  83           .hsub = 2, .vsub = 2, .is_yuv = true },
  84         { .format = DRM_FORMAT_P012, .num_planes = 4,
  85           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
  86           .hsub = 2, .vsub = 2, .is_yuv = true },
  87         { .format = DRM_FORMAT_P016, .num_planes = 4,
  88           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
  89           .hsub = 2, .vsub = 2, .is_yuv = true },
  90 };
  91
  92 /*
  93  * Same as gen12_ccs_formats[] above, but with additional surface used
  94  * to pass Clear Color information in plane 2 with 64 bits of data.
  95  */
  96 static const struct drm_format_info gen12_ccs_cc_formats[] = {
  97         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
  98           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
  99           .hsub = 1, .vsub = 1, },
 100         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 101           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 102           .hsub = 1, .vsub = 1, },
 103         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 104           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 105           .hsub = 1, .vsub = 1, .has_alpha = true },
 106         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 107           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 108           .hsub = 1, .vsub = 1, .has_alpha = true },
 109 };
 110
 111 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
 112         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 113           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 114           .hsub = 1, .vsub = 1, },
 115         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 116           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 117           .hsub = 1, .vsub = 1, },
 118         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 119           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 120           .hsub = 1, .vsub = 1, .has_alpha = true },
 121         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 122           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 123           .hsub = 1, .vsub = 1, .has_alpha = true },
 124 };
 125
 126 struct intel_modifier_desc {
 127         u64 modifier;
 128         struct {
 129                 u8 from;
 130                 u8 until;
 131         } display_ver;
 132 #define DISPLAY_VER_ALL         { 0, -1 }
 133
 134         const struct drm_format_info *formats;
 135         int format_count;
 136 #define FORMAT_OVERRIDE(format_list) \
 137         .formats = format_list, \
 138         .format_count = ARRAY_SIZE(format_list)
 139
 140         u8 plane_caps;
 141
 142         struct {
 143                 u8 cc_planes:3;
 144                 u8 packed_aux_planes:4;
 145                 u8 planar_aux_planes:4;
 146         } ccs;
 147 };
 148
 149 #define INTEL_PLANE_CAP_CCS_MASK        (INTEL_PLANE_CAP_CCS_RC | \
 150                                          INTEL_PLANE_CAP_CCS_RC_CC | \
 151                                          INTEL_PLANE_CAP_CCS_MC)
 152 #define INTEL_PLANE_CAP_TILING_MASK     (INTEL_PLANE_CAP_TILING_X | \
 153                                          INTEL_PLANE_CAP_TILING_Y | \
 154                                          INTEL_PLANE_CAP_TILING_Yf | \
 155                                          INTEL_PLANE_CAP_TILING_4)
 156 #define INTEL_PLANE_CAP_TILING_NONE     0
 157
 158 static const struct intel_modifier_desc intel_modifiers[] = {
 159         {
 160                 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
 161                 .display_ver = { 13, 13 },
 162                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
 163         }, {
 164                 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
 165                 .display_ver = { 13, 13 },
 166                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
 167
 168                 .ccs.cc_planes = BIT(1),
 169
 170                 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
 171         }, {
 172                 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
 173                 .display_ver = { 13, 13 },
 174                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
 175         }, {
 176                 .modifier = I915_FORMAT_MOD_4_TILED,
 177                 .display_ver = { 13, 13 },
 178                 .plane_caps = INTEL_PLANE_CAP_TILING_4,
 179         }, {
 180                 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 181                 .display_ver = { 12, 13 },
 182                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
 183
 184                 .ccs.packed_aux_planes = BIT(1),
 185                 .ccs.planar_aux_planes = BIT(2) | BIT(3),
 186
 187                 FORMAT_OVERRIDE(gen12_ccs_formats),
 188         }, {
 189                 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 190                 .display_ver = { 12, 13 },
 191                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
 192
 193                 .ccs.packed_aux_planes = BIT(1),
 194
 195                 FORMAT_OVERRIDE(gen12_ccs_formats),
 196         }, {
 197                 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 198                 .display_ver = { 12, 13 },
 199                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC,
 200
 201                 .ccs.cc_planes = BIT(2),
 202                 .ccs.packed_aux_planes = BIT(1),
 203
 204                 FORMAT_OVERRIDE(gen12_ccs_cc_formats),
 205         }, {
 206                 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
 207                 .display_ver = { 9, 11 },
 208                 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC,
 209
 210                 .ccs.packed_aux_planes = BIT(1),
 211
 212                 FORMAT_OVERRIDE(skl_ccs_formats),
 213         }, {
 214                 .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
 215                 .display_ver = { 9, 11 },
 216                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
 217
 218                 .ccs.packed_aux_planes = BIT(1),
 219
 220                 FORMAT_OVERRIDE(skl_ccs_formats),
 221         }, {
 222                 .modifier = I915_FORMAT_MOD_Yf_TILED,
 223                 .display_ver = { 9, 11 },
 224                 .plane_caps = INTEL_PLANE_CAP_TILING_Yf,
 225         }, {
 226                 .modifier = I915_FORMAT_MOD_Y_TILED,
 227                 .display_ver = { 9, 13 },
 228                 .plane_caps = INTEL_PLANE_CAP_TILING_Y,
 229         }, {
 230                 .modifier = I915_FORMAT_MOD_X_TILED,
 231                 .display_ver = DISPLAY_VER_ALL,
 232                 .plane_caps = INTEL_PLANE_CAP_TILING_X,
 233         }, {
 234                 .modifier = DRM_FORMAT_MOD_LINEAR,
 235                 .display_ver = DISPLAY_VER_ALL,
 236         },
 237 };
 238
 239 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
 240 {
 241         int i;
 242
 243         for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
 244                 if (intel_modifiers[i].modifier == modifier)
 245                         return &intel_modifiers[i];
 246
 247         return NULL;
 248 }
 249
 250 static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
 251 {
 252         const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
 253
 254         if (WARN_ON(!md))
 255                 return &intel_modifiers[0];
 256
 257         return md;
 258 }
 259
 260 static const struct drm_format_info *
 261 lookup_format_info(const struct drm_format_info formats[],
 262                    int num_formats, u32 format)
 263 {
 264         int i;
 265
 266         for (i = 0; i < num_formats; i++) {
 267                 if (formats[i].format == format)
 268                         return &formats[i];
 269         }
 270
 271         return NULL;
 272 }
 273
 274 /**
 275  * intel_fb_get_format_info: Get a modifier specific format information
 276  * @cmd: FB add command structure
 277  *
 278  * Returns:
 279  * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
 280  * or %NULL if the modifier doesn't override the format.
 281  */
 282 const struct drm_format_info *
 283 intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 284 {
 285         const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
 286
 287         if (!md || !md->formats)
 288                 return NULL;
 289
 290         return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
 291 }
 292
 293 static bool plane_caps_contain_any(u8 caps, u8 mask)
 294 {
 295         return caps & mask;
 296 }
 297
 298 static bool plane_caps_contain_all(u8 caps, u8 mask)
 299 {
 300         return (caps & mask) == mask;
 301 }
 302
 303 /**
 304  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
 305  * @modifier: Modifier to check
 306  *
 307  * Returns:
 308  * Returns %true if @modifier is a render, render with color clear or
 309  * media compression modifier.
 310  */
 311 bool intel_fb_is_ccs_modifier(u64 modifier)
 312 {
 313         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 314                                       INTEL_PLANE_CAP_CCS_MASK);
 315 }
 316
 317 /**
 318  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
 319  * @modifier: Modifier to check
 320  *
 321  * Returns:
 322  * Returns %true if @modifier is a render with color clear modifier.
 323  */
 324 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
 325 {
 326         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 327                                       INTEL_PLANE_CAP_CCS_RC_CC);
 328 }
 329
 330 /**
 331  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
 332  * @modifier: Modifier to check
 333  *
 334  * Returns:
 335  * Returns %true if @modifier is a media compression modifier.
 336  */
 337 bool intel_fb_is_mc_ccs_modifier(u64 modifier)
 338 {
 339         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 340                                       INTEL_PLANE_CAP_CCS_MC);
 341 }
 342
 343 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
 344                                              u8 display_ver_from, u8 display_ver_until)
 345 {
 346         return md->display_ver.from <= display_ver_until &&
 347                 display_ver_from <= md->display_ver.until;
 348 }
 349
 350 static bool plane_has_modifier(struct drm_i915_private *i915,
 351                                u8 plane_caps,
 352                                const struct intel_modifier_desc *md)
 353 {
 354         if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until))
 355                 return false;
 356
 357         if (!plane_caps_contain_all(plane_caps, md->plane_caps))
 358                 return false;
 359
 360         return true;
 361 }
 362
 363 /**
 364  * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities
 365  * @i915: i915 device instance
 366  * @plane_caps: capabilities for the plane the modifiers are queried for
 367  *
 368  * Returns:
 369  * Returns the list of modifiers allowed by the @i915 platform and @plane_caps.
 370  * The caller must free the returned buffer.
 371  */
 372 u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
 373                                   u8 plane_caps)
 374 {
 375         u64 *list, *p;
 376         int count = 1;          /* +1 for invalid modifier terminator */
 377         int i;
 378
 379         for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
 380                 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
 381                         count++;
 382         }
 383
 384         list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
 385         if (drm_WARN_ON(&i915->drm, !list))
 386                 return NULL;
 387
 388         p = list;
 389         for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
 390                 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
 391                         *p++ = intel_modifiers[i].modifier;
 392         }
 393         *p++ = DRM_FORMAT_MOD_INVALID;
 394
 395         return list;
 396 }
 397
 398 /**
 399  * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
 400  * @plane: Plane to check the modifier support for
 401  * @modifier: The modifier to check the support for
 402  *
 403  * Returns:
 404  * %true if the @modifier is supported on @plane.
 405  */
 406 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
 407 {
 408         int i;
 409
 410         for (i = 0; i < plane->base.modifier_count; i++)
 411                 if (plane->base.modifiers[i] == modifier)
 412                         return true;
 413
 414         return false;
 415 }
 416
 417 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
 418                                      const struct drm_format_info *info)
 419 {
 420         if (!info->is_yuv)
 421                 return false;
 422
 423         if (hweight8(md->ccs.planar_aux_planes) == 2)
 424                 return info->num_planes == 4;
 425         else
 426                 return info->num_planes == 2;
 427 }
 428
 429 /**
 430  * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar
 431  * @info: format to check
 432  * @modifier: modifier used with the format
 433  *
 434  * Returns:
 435  * %true if @info / @modifier is YUV semiplanar.
 436  */
 437 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
 438                                          u64 modifier)
 439 {
 440         return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
 441 }
 442
 443 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,
 444                              const struct drm_format_info *format)
 445 {
 446         if (format_is_yuv_semiplanar(md, format))
 447                 return md->ccs.planar_aux_planes;
 448         else
 449                 return md->ccs.packed_aux_planes;
 450 }
 451
 452 /**
 453  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
 454  * @fb: Framebuffer
 455  * @color_plane: color plane index to check
 456  *
 457  * Returns:
 458  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
 459  */
 460 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
 461 {
 462         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 463
 464         return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
 465 }
 466
 467 /**
 468  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
 469  * @fb: Framebuffer
 470  * @color_plane: color plane index to check
 471  *
 472  * Returns:
 473  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
 474  */
 475 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
 476 {
 477         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 478
 479         return check_modifier_display_ver_range(md, 12, 13) &&
 480                ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
 481 }
 482
 483 /**
 484  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
 485  * @fb: Framebuffer
 486  *
 487  * Returns:
 488  * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
 489  * framebuffer using a render compression/color clear modifier.
 490  */
 491 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
 492 {
 493         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 494
 495         if (!md->ccs.cc_planes)
 496                 return -1;
 497
 498         drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
 499
 500         return ilog2((int)md->ccs.cc_planes);
 501 }
 502
 503 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)
 504 {
 505         return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
 506 }
 507
 508 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
 509 {
 510         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
 511                 color_plane == 1;
 512 }
 513
 514 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 515 {
 516         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
 517                intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) ||
 518                is_gen12_ccs_cc_plane(fb, color_plane);
 519 }
 520
 521 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
 522 {
 523         drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
 524                     (main_plane && main_plane >= fb->format->num_planes / 2));
 525
 526         return fb->format->num_planes / 2 + main_plane;
 527 }
 528
 529 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
 530 {
 531         drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
 532                     ccs_plane < fb->format->num_planes / 2);
 533
 534         if (is_gen12_ccs_cc_plane(fb, ccs_plane))
 535                 return 0;
 536
 537         return ccs_plane - fb->format->num_planes / 2;
 538 }
 539
 540 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane)
 541 {
 542         int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane);
 543         unsigned int main_stride = fb->base.pitches[main_plane];
 544         unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane);
 545
 546         return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;
 547 }
 548
 549 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 550 {
 551         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 552         struct drm_i915_private *i915 = to_i915(fb->dev);
 553
 554         if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
 555                 return main_to_ccs_plane(fb, main_plane);
 556         else if (DISPLAY_VER(i915) < 11 &&
 557                  format_is_yuv_semiplanar(md, fb->format))
 558                 return 1;
 559         else
 560                 return 0;
 561 }
 562
 563 unsigned int intel_tile_size(const struct drm_i915_private *i915)
 564 {
 565         return DISPLAY_VER(i915) == 2 ? 2048 : 4096;
 566 }
 567
 568 unsigned int
 569 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 570 {
 571         struct drm_i915_private *dev_priv = to_i915(fb->dev);
 572         unsigned int cpp = fb->format->cpp[color_plane];
 573
 574         switch (fb->modifier) {
 575         case DRM_FORMAT_MOD_LINEAR:
 576                 return intel_tile_size(dev_priv);
 577         case I915_FORMAT_MOD_X_TILED:
 578                 if (DISPLAY_VER(dev_priv) == 2)
 579                         return 128;
 580                 else
 581                         return 512;
 582         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 583         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 584         case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 585         case I915_FORMAT_MOD_4_TILED:
 586                 /*
 587                  * Each 4K tile consists of 64B(8*8) subtiles, with
 588                  * same shape as Y Tile(i.e 4*16B OWords)
 589                  */
 590                 return 128;
 591         case I915_FORMAT_MOD_Y_TILED_CCS:
 592                 if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 593                         return 128;
 594                 fallthrough;
 595         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 596         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 597         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 598                 if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||
 599                     is_gen12_ccs_cc_plane(fb, color_plane))
 600                         return 64;
 601                 fallthrough;
 602         case I915_FORMAT_MOD_Y_TILED:
 603                 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
 604                         return 128;
 605                 else
 606                         return 512;
 607         case I915_FORMAT_MOD_Yf_TILED_CCS:
 608                 if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 609                         return 128;
 610                 fallthrough;
 611         case I915_FORMAT_MOD_Yf_TILED:
 612                 switch (cpp) {
 613                 case 1:
 614                         return 64;
 615                 case 2:
 616                 case 4:
 617                         return 128;
 618                 case 8:
 619                 case 16:
 620                         return 256;
 621                 default:
 622                         MISSING_CASE(cpp);
 623                         return cpp;
 624                 }
 625                 break;
 626         default:
 627                 MISSING_CASE(fb->modifier);
 628                 return cpp;
 629         }
 630 }
 631
 632 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 633 {
 634         return intel_tile_size(to_i915(fb->dev)) /
 635                 intel_tile_width_bytes(fb, color_plane);
 636 }
 637
 638 /*
 639  * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT
 640  * page tile size.
 641  */
 642 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
 643                             unsigned int *tile_width,
 644                             unsigned int *tile_height)
 645 {
 646         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
 647         unsigned int cpp = fb->format->cpp[color_plane];
 648
 649         *tile_width = tile_width_bytes / cpp;
 650         *tile_height = intel_tile_height(fb, color_plane);
 651 }
 652
 653 /*
 654  * Return the tile dimensions in pixel units, based on the tile block size.
 655  * The block covers the full GTT page sized tile on all tiled surfaces and
 656  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
 657  */
 658 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane,
 659                                   unsigned int *tile_width,
 660                                   unsigned int *tile_height)
 661 {
 662         intel_tile_dims(fb, color_plane, tile_width, tile_height);
 663
 664         if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane))
 665                 *tile_height = 1;
 666 }
 667
 668 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane)
 669 {
 670         unsigned int tile_width, tile_height;
 671
 672         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
 673
 674         return fb->pitches[color_plane] * tile_height;
 675 }
 676
 677 unsigned int
 678 intel_fb_align_height(const struct drm_framebuffer *fb,
 679                       int color_plane, unsigned int height)
 680 {
 681         unsigned int tile_height = intel_tile_height(fb, color_plane);
 682
 683         return ALIGN(height, tile_height);
 684 }
 685
 686 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 687 {
 688         u8 tiling_caps = lookup_modifier(fb_modifier)->plane_caps &
 689                          INTEL_PLANE_CAP_TILING_MASK;
 690
 691         switch (tiling_caps) {
 692         case INTEL_PLANE_CAP_TILING_Y:
 693                 return I915_TILING_Y;
 694         case INTEL_PLANE_CAP_TILING_X:
 695                 return I915_TILING_X;
 696         case INTEL_PLANE_CAP_TILING_4:
 697         case INTEL_PLANE_CAP_TILING_Yf:
 698         case INTEL_PLANE_CAP_TILING_NONE:
 699                 return I915_TILING_NONE;
 700         default:
 701                 MISSING_CASE(tiling_caps);
 702                 return I915_TILING_NONE;
 703         }
 704 }
 705
 706 static bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
 707 {
 708         return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
 709 }
 710
 711 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
 712 {
 713         return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 714 }
 715
 716 unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
 717 {
 718         if (IS_I830(i915))
 719                 return 16 * 1024;
 720         else if (IS_I85X(i915))
 721                 return 256;
 722         else if (IS_I845G(i915) || IS_I865G(i915))
 723                 return 32;
 724         else
 725                 return 4 * 1024;
 726 }
 727
 728 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
 729 {
 730         if (DISPLAY_VER(dev_priv) >= 9)
 731                 return 256 * 1024;
 732         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
 733                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 734                 return 128 * 1024;
 735         else if (DISPLAY_VER(dev_priv) >= 4)
 736                 return 4 * 1024;
 737         else
 738                 return 0;
 739 }
 740
 741 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 742                                   int color_plane)
 743 {
 744         struct drm_i915_private *dev_priv = to_i915(fb->dev);
 745
 746         if (intel_fb_uses_dpt(fb))
 747                 return 512 * 4096;
 748
 749         /* AUX_DIST needs only 4K alignment */
 750         if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 751                 return 4096;
 752
 753         if (is_semiplanar_uv_plane(fb, color_plane)) {
 754                 /*
 755                  * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
 756                  * alignment for linear UV planes on all platforms.
 757                  */
 758                 if (DISPLAY_VER(dev_priv) >= 12) {
 759                         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
 760                                 return intel_linear_alignment(dev_priv);
 761
 762                         return intel_tile_row_size(fb, color_plane);
 763                 }
 764
 765                 return 4096;
 766         }
 767
 768         drm_WARN_ON(&dev_priv->drm, color_plane != 0);
 769
 770         switch (fb->modifier) {
 771         case DRM_FORMAT_MOD_LINEAR:
 772                 return intel_linear_alignment(dev_priv);
 773         case I915_FORMAT_MOD_X_TILED:
 774                 if (HAS_ASYNC_FLIPS(dev_priv))
 775                         return 256 * 1024;
 776                 return 0;
 777         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 778         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 779         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 780                 return 16 * 1024;
 781         case I915_FORMAT_MOD_Y_TILED_CCS:
 782         case I915_FORMAT_MOD_Yf_TILED_CCS:
 783         case I915_FORMAT_MOD_Y_TILED:
 784         case I915_FORMAT_MOD_4_TILED:
 785         case I915_FORMAT_MOD_Yf_TILED:
 786                 return 1 * 1024 * 1024;
 787         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 788         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 789         case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 790                 return 16 * 1024;
 791         default:
 792                 MISSING_CASE(fb->modifier);
 793                 return 0;
 794         }
 795 }
 796
 797 void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
 798                                     const struct drm_framebuffer *fb,
 799                                     int color_plane)
 800 {
 801         int main_plane;
 802
 803         if (color_plane == 0) {
 804                 *hsub = 1;
 805                 *vsub = 1;
 806
 807                 return;
 808         }
 809
 810         /*
 811          * TODO: Deduct the subsampling from the char block for all CCS
 812          * formats and planes.
 813          */
 814         if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) {
 815                 *hsub = fb->format->hsub;
 816                 *vsub = fb->format->vsub;
 817
 818                 return;
 819         }
 820
 821         main_plane = skl_ccs_to_main_plane(fb, color_plane);
 822         *hsub = drm_format_info_block_width(fb->format, color_plane) /
 823                 drm_format_info_block_width(fb->format, main_plane);
 824
 825         /*
 826          * The min stride check in the core framebuffer_check() function
 827          * assumes that format->hsub applies to every plane except for the
 828          * first plane. That's incorrect for the CCS AUX plane of the first
 829          * plane, but for the above check to pass we must define the block
 830          * width with that subsampling applied to it. Adjust the width here
 831          * accordingly, so we can calculate the actual subsampling factor.
 832          */
 833         if (main_plane == 0)
 834                 *hsub *= fb->format->hsub;
 835
 836         *vsub = 32;
 837 }
 838
 839 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
 840 {
 841         int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ?
 842                          skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
 843         unsigned int main_width = fb->base.width;
 844         unsigned int main_height = fb->base.height;
 845         int main_hsub, main_vsub;
 846         int hsub, vsub;
 847
 848         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane);
 849         intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane);
 850
 851         *w = DIV_ROUND_UP(main_width, main_hsub * hsub);
 852         *h = DIV_ROUND_UP(main_height, main_vsub * vsub);
 853 }
 854
 855 static u32 intel_adjust_tile_offset(int *x, int *y,
 856                                     unsigned int tile_width,
 857                                     unsigned int tile_height,
 858                                     unsigned int tile_size,
 859                                     unsigned int pitch_tiles,
 860                                     u32 old_offset,
 861                                     u32 new_offset)
 862 {
 863         unsigned int pitch_pixels = pitch_tiles * tile_width;
 864         unsigned int tiles;
 865
 866         WARN_ON(old_offset & (tile_size - 1));
 867         WARN_ON(new_offset & (tile_size - 1));
 868         WARN_ON(new_offset > old_offset);
 869
 870         tiles = (old_offset - new_offset) / tile_size;
 871
 872         *y += tiles / pitch_tiles * tile_height;
 873         *x += tiles % pitch_tiles * tile_width;
 874
 875         /* minimize x in case it got needlessly big */
 876         *y += *x / pitch_pixels * tile_height;
 877         *x %= pitch_pixels;
 878
 879         return new_offset;
 880 }
 881
 882 static u32 intel_adjust_linear_offset(int *x, int *y,
 883                                       unsigned int cpp,
 884                                       unsigned int pitch,
 885                                       u32 old_offset,
 886                                       u32 new_offset)
 887 {
 888         old_offset += *y * pitch + *x * cpp;
 889
 890         *y = (old_offset - new_offset) / pitch;
 891         *x = ((old_offset - new_offset) - *y * pitch) / cpp;
 892
 893         return new_offset;
 894 }
 895
 896 static u32 intel_adjust_aligned_offset(int *x, int *y,
 897                                        const struct drm_framebuffer *fb,
 898                                        int color_plane,
 899                                        unsigned int rotation,
 900                                        unsigned int pitch,
 901                                        u32 old_offset, u32 new_offset)
 902 {
 903         struct drm_i915_private *i915 = to_i915(fb->dev);
 904         unsigned int cpp = fb->format->cpp[color_plane];
 905
 906         drm_WARN_ON(&i915->drm, new_offset > old_offset);
 907
 908         if (!is_surface_linear(fb, color_plane)) {
 909                 unsigned int tile_size, tile_width, tile_height;
 910                 unsigned int pitch_tiles;
 911
 912                 tile_size = intel_tile_size(i915);
 913                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
 914
 915                 if (drm_rotation_90_or_270(rotation)) {
 916                         pitch_tiles = pitch / tile_height;
 917                         swap(tile_width, tile_height);
 918                 } else {
 919                         pitch_tiles = pitch / (tile_width * cpp);
 920                 }
 921
 922                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
 923                                          tile_size, pitch_tiles,
 924                                          old_offset, new_offset);
 925         } else {
 926                 intel_adjust_linear_offset(x, y, cpp, pitch,
 927                                            old_offset, new_offset);
 928         }
 929
 930         return new_offset;
 931 }
 932
 933 /*
 934  * Adjust the tile offset by moving the difference into
 935  * the x/y offsets.
 936  */
 937 u32 intel_plane_adjust_aligned_offset(int *x, int *y,
 938                                       const struct intel_plane_state *state,
 939                                       int color_plane,
 940                                       u32 old_offset, u32 new_offset)
 941 {
 942         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
 943                                            state->hw.rotation,
 944                                            state->view.color_plane[color_plane].mapping_stride,
 945                                            old_offset, new_offset);
 946 }
 947
 948 /*
 949  * Computes the aligned offset to the base tile and adjusts
 950  * x, y. bytes per pixel is assumed to be a power-of-two.
 951  *
 952  * In the 90/270 rotated case, x and y are assumed
 953  * to be already rotated to match the rotated GTT view, and
 954  * pitch is the tile_height aligned framebuffer height.
 955  *
 956  * This function is used when computing the derived information
 957  * under intel_framebuffer, so using any of that information
 958  * here is not allowed. Anything under drm_framebuffer can be
 959  * used. This is why the user has to pass in the pitch since it
 960  * is specified in the rotated orientation.
 961  */
 962 static u32 intel_compute_aligned_offset(struct drm_i915_private *i915,
 963                                         int *x, int *y,
 964                                         const struct drm_framebuffer *fb,
 965                                         int color_plane,
 966                                         unsigned int pitch,
 967                                         unsigned int rotation,
 968                                         u32 alignment)
 969 {
 970         unsigned int cpp = fb->format->cpp[color_plane];
 971         u32 offset, offset_aligned;
 972
 973         if (!is_surface_linear(fb, color_plane)) {
 974                 unsigned int tile_size, tile_width, tile_height;
 975                 unsigned int tile_rows, tiles, pitch_tiles;
 976
 977                 tile_size = intel_tile_size(i915);
 978                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
 979
 980                 if (drm_rotation_90_or_270(rotation)) {
 981                         pitch_tiles = pitch / tile_height;
 982                         swap(tile_width, tile_height);
 983                 } else {
 984                         pitch_tiles = pitch / (tile_width * cpp);
 985                 }
 986
 987                 tile_rows = *y / tile_height;
 988                 *y %= tile_height;
 989
 990                 tiles = *x / tile_width;
 991                 *x %= tile_width;
 992
 993                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
 994
 995                 offset_aligned = offset;
 996                 if (alignment)
 997                         offset_aligned = rounddown(offset_aligned, alignment);
 998
 999                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1000                                          tile_size, pitch_tiles,
1001                                          offset, offset_aligned);
1002         } else {
1003                 offset = *y * pitch + *x * cpp;
1004                 offset_aligned = offset;
1005                 if (alignment) {
1006                         offset_aligned = rounddown(offset_aligned, alignment);
1007                         *y = (offset % alignment) / pitch;
1008                         *x = ((offset % alignment) - *y * pitch) / cpp;
1009                 } else {
1010                         *y = *x = 0;
1011                 }
1012         }
1013
1014         return offset_aligned;
1015 }
1016
1017 u32 intel_plane_compute_aligned_offset(int *x, int *y,
1018                                        const struct intel_plane_state *state,
1019                                        int color_plane)
1020 {
1021         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
1022         struct drm_i915_private *i915 = to_i915(intel_plane->base.dev);
1023         const struct drm_framebuffer *fb = state->hw.fb;
1024         unsigned int rotation = state->hw.rotation;
1025         int pitch = state->view.color_plane[color_plane].mapping_stride;
1026         u32 alignment;
1027
1028         if (intel_plane->id == PLANE_CURSOR)
1029                 alignment = intel_cursor_alignment(i915);
1030         else
1031                 alignment = intel_surf_alignment(fb, color_plane);
1032
1033         return intel_compute_aligned_offset(i915, x, y, fb, color_plane,
1034                                             pitch, rotation, alignment);
1035 }
1036
1037 /* Convert the fb->offset[] into x/y offsets */
1038 static int intel_fb_offset_to_xy(int *x, int *y,
1039                                  const struct drm_framebuffer *fb,
1040                                  int color_plane)
1041 {
1042         struct drm_i915_private *i915 = to_i915(fb->dev);
1043         unsigned int height;
1044         u32 alignment;
1045
1046         if (DISPLAY_VER(i915) >= 12 &&
1047             !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
1048             is_semiplanar_uv_plane(fb, color_plane))
1049                 alignment = intel_tile_row_size(fb, color_plane);
1050         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1051                 alignment = intel_tile_size(i915);
1052         else
1053                 alignment = 0;
1054
1055         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1056                 drm_dbg_kms(&i915->drm,
1057                             "Misaligned offset 0x%08x for color plane %d\n",
1058                             fb->offsets[color_plane], color_plane);
1059                 return -EINVAL;
1060         }
1061
1062         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
1063         height = ALIGN(height, intel_tile_height(fb, color_plane));
1064
1065         /* Catch potential overflows early */
1066         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
1067                             fb->offsets[color_plane])) {
1068                 drm_dbg_kms(&i915->drm,
1069                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
1070                             fb->offsets[color_plane], fb->pitches[color_plane],
1071                             color_plane);
1072                 return -ERANGE;
1073         }
1074
1075         *x = 0;
1076         *y = 0;
1077
1078         intel_adjust_aligned_offset(x, y,
1079                                     fb, color_plane, DRM_MODE_ROTATE_0,
1080                                     fb->pitches[color_plane],
1081                                     fb->offsets[color_plane], 0);
1082
1083         return 0;
1084 }
1085
1086 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y)
1087 {
1088         struct drm_i915_private *i915 = to_i915(fb->dev);
1089         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1090         int main_plane;
1091         int hsub, vsub;
1092         int tile_width, tile_height;
1093         int ccs_x, ccs_y;
1094         int main_x, main_y;
1095
1096         if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1097                 return 0;
1098
1099         /*
1100          * While all the tile dimensions are based on a 2k or 4k GTT page size
1101          * here the main and CCS coordinates must match only within a (64 byte
1102          * on TGL+) block inside the tile.
1103          */
1104         intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height);
1105         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1106
1107         tile_width *= hsub;
1108         tile_height *= vsub;
1109
1110         ccs_x = (x * hsub) % tile_width;
1111         ccs_y = (y * vsub) % tile_height;
1112
1113         main_plane = skl_ccs_to_main_plane(fb, ccs_plane);
1114         main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width;
1115         main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height;
1116
1117         /*
1118          * CCS doesn't have its own x/y offset register, so the intra CCS tile
1119          * x/y offsets must match between CCS and the main surface.
1120          */
1121         if (main_x != ccs_x || main_y != ccs_y) {
1122                 drm_dbg_kms(&i915->drm,
1123                               "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
1124                               main_x, main_y,
1125                               ccs_x, ccs_y,
1126                               intel_fb->normal_view.color_plane[main_plane].x,
1127                               intel_fb->normal_view.color_plane[main_plane].y,
1128                               x, y);
1129                 return -EINVAL;
1130         }
1131
1132         return 0;
1133 }
1134
1135 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1136 {
1137         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1138         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1139         const struct drm_framebuffer *fb = plane_state->hw.fb;
1140         int i;
1141
1142         /* We don't want to deal with remapping with cursors */
1143         if (plane->id == PLANE_CURSOR)
1144                 return false;
1145
1146         /*
1147          * The display engine limits already match/exceed the
1148          * render engine limits, so not much point in remapping.
1149          * Would also need to deal with the fence POT alignment
1150          * and gen2 2KiB GTT tile size.
1151          */
1152         if (DISPLAY_VER(i915) < 4)
1153                 return false;
1154
1155         /*
1156          * The new CCS hash mode isn't compatible with remapping as
1157          * the virtual address of the pages affects the compressed data.
1158          */
1159         if (intel_fb_is_ccs_modifier(fb->modifier))
1160                 return false;
1161
1162         /* Linear needs a page aligned stride for remapping */
1163         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1164                 unsigned int alignment = intel_tile_size(i915) - 1;
1165
1166                 for (i = 0; i < fb->format->num_planes; i++) {
1167                         if (fb->pitches[i] & alignment)
1168                                 return false;
1169                 }
1170         }
1171
1172         return true;
1173 }
1174
1175 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
1176 {
1177         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1178
1179         return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR;
1180 }
1181
1182 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
1183 {
1184         if (drm_rotation_90_or_270(rotation))
1185                 return fb->rotated_view.color_plane[color_plane].mapping_stride;
1186         else if (intel_fb_needs_pot_stride_remap(fb))
1187                 return fb->remapped_view.color_plane[color_plane].mapping_stride;
1188         else
1189                 return fb->normal_view.color_plane[color_plane].mapping_stride;
1190 }
1191
1192 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
1193 {
1194         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1195         const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
1196         unsigned int rotation = plane_state->hw.rotation;
1197         u32 stride, max_stride;
1198
1199         /*
1200          * No remapping for invisible planes since we don't have
1201          * an actual source viewport to remap.
1202          */
1203         if (!plane_state->uapi.visible)
1204                 return false;
1205
1206         if (!intel_plane_can_remap(plane_state))
1207                 return false;
1208
1209         /*
1210          * FIXME: aux plane limits on gen9+ are
1211          * unclear in Bspec, for now no checking.
1212          */
1213         stride = intel_fb_pitch(fb, 0, rotation);
1214         max_stride = plane->max_stride(plane, fb->base.format->format,
1215                                        fb->base.modifier, rotation);
1216
1217         return stride > max_stride;
1218 }
1219
1220 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane,
1221                                       int plane_width, int *x, int *y)
1222 {
1223         struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1224         int ret;
1225
1226         ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane);
1227         if (ret) {
1228                 drm_dbg_kms(fb->base.dev,
1229                             "bad fb plane %d offset: 0x%x\n",
1230                             color_plane, fb->base.offsets[color_plane]);
1231                 return ret;
1232         }
1233
1234         ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y);
1235         if (ret)
1236                 return ret;
1237
1238         /*
1239          * The fence (if used) is aligned to the start of the object
1240          * so having the framebuffer wrap around across the edge of the
1241          * fenced region doesn't really work. We have no API to configure
1242          * the fence start offset within the object (nor could we probably
1243          * on gen2/3). So it's just easier if we just require that the
1244          * fb layout agrees with the fence layout. We already check that the
1245          * fb stride matches the fence stride elsewhere.
1246          */
1247         if (color_plane == 0 && i915_gem_object_is_tiled(obj) &&
1248             (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) {
1249                 drm_dbg_kms(fb->base.dev,
1250                             "bad fb plane %d offset: 0x%x\n",
1251                             color_plane, fb->base.offsets[color_plane]);
1252                 return -EINVAL;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)
1259 {
1260         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1261         unsigned int tile_size = intel_tile_size(i915);
1262         u32 offset;
1263
1264         offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane,
1265                                               fb->base.pitches[color_plane],
1266                                               DRM_MODE_ROTATE_0,
1267                                               tile_size);
1268
1269         return offset / tile_size;
1270 }
1271
1272 struct fb_plane_view_dims {
1273         unsigned int width, height;
1274         unsigned int tile_width, tile_height;
1275 };
1276
1277 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane,
1278                                  unsigned int width, unsigned int height,
1279                                  struct fb_plane_view_dims *dims)
1280 {
1281         dims->width = width;
1282         dims->height = height;
1283
1284         intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height);
1285 }
1286
1287 static unsigned int
1288 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1289                             const struct fb_plane_view_dims *dims)
1290 {
1291         return DIV_ROUND_UP(fb->base.pitches[color_plane],
1292                             dims->tile_width * fb->base.format->cpp[color_plane]);
1293 }
1294
1295 static unsigned int
1296 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1297                             unsigned int pitch_tiles)
1298 {
1299         if (intel_fb_needs_pot_stride_remap(fb)) {
1300                 /*
1301                  * ADL_P, the only platform needing a POT stride has a minimum
1302                  * of 8 main surface tiles.
1303                  */
1304                 return roundup_pow_of_two(max(pitch_tiles, 8u));
1305         } else {
1306                 return pitch_tiles;
1307         }
1308 }
1309
1310 static unsigned int
1311 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
1312                           unsigned int tile_width,
1313                           unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
1314 {
1315         unsigned int stride_tiles;
1316
1317         if (IS_ALDERLAKE_P(to_i915(fb->base.dev)))
1318                 stride_tiles = src_stride_tiles;
1319         else
1320                 stride_tiles = dst_stride_tiles;
1321
1322         return stride_tiles * tile_width * fb->base.format->cpp[color_plane];
1323 }
1324
1325 static unsigned int
1326 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane,
1327                        const struct fb_plane_view_dims *dims,
1328                        int x)
1329 {
1330         return DIV_ROUND_UP(x + dims->width, dims->tile_width);
1331 }
1332
1333 static unsigned int
1334 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane,
1335                         const struct fb_plane_view_dims *dims,
1336                         int y)
1337 {
1338         return DIV_ROUND_UP(y + dims->height, dims->tile_height);
1339 }
1340
1341 static unsigned int
1342 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane,
1343                         const struct fb_plane_view_dims *dims,
1344                         int x, int y)
1345 {
1346         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1347         unsigned int size;
1348
1349         size = (y + dims->height) * fb->base.pitches[color_plane] +
1350                 x * fb->base.format->cpp[color_plane];
1351
1352         return DIV_ROUND_UP(size, intel_tile_size(i915));
1353 }
1354
1355 #define assign_chk_ovf(i915, var, val) ({ \
1356         drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \
1357         (var) = (val); \
1358 })
1359
1360 #define assign_bfld_chk_ovf(i915, var, val) ({ \
1361         (var) = (val); \
1362         drm_WARN_ON(&(i915)->drm, (var) != (val)); \
1363         (var); \
1364 })
1365
1366 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,
1367                                  const struct fb_plane_view_dims *dims,
1368                                  u32 obj_offset, u32 gtt_offset, int x, int y,
1369                                  struct intel_fb_view *view)
1370 {
1371         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1372         struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];
1373         struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane];
1374         unsigned int tile_width = dims->tile_width;
1375         unsigned int tile_height = dims->tile_height;
1376         unsigned int tile_size = intel_tile_size(i915);
1377         struct drm_rect r;
1378         u32 size = 0;
1379
1380         assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset);
1381
1382         if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) {
1383                 remap_info->linear = 1;
1384
1385                 assign_chk_ovf(i915, remap_info->size,
1386                                plane_view_linear_tiles(fb, color_plane, dims, x, y));
1387         } else {
1388                 remap_info->linear = 0;
1389
1390                 assign_chk_ovf(i915, remap_info->src_stride,
1391                                plane_view_src_stride_tiles(fb, color_plane, dims));
1392                 assign_chk_ovf(i915, remap_info->width,
1393                                plane_view_width_tiles(fb, color_plane, dims, x));
1394                 assign_chk_ovf(i915, remap_info->height,
1395                                plane_view_height_tiles(fb, color_plane, dims, y));
1396         }
1397
1398         if (view->gtt.type == I915_GTT_VIEW_ROTATED) {
1399                 drm_WARN_ON(&i915->drm, remap_info->linear);
1400                 check_array_bounds(i915, view->gtt.rotated.plane, color_plane);
1401
1402                 assign_chk_ovf(i915, remap_info->dst_stride,
1403                                plane_view_dst_stride_tiles(fb, color_plane, remap_info->height));
1404
1405                 /* rotate the x/y offsets to match the GTT view */
1406                 drm_rect_init(&r, x, y, dims->width, dims->height);
1407                 drm_rect_rotate(&r,
1408                                 remap_info->width * tile_width,
1409                                 remap_info->height * tile_height,
1410                                 DRM_MODE_ROTATE_270);
1411
1412                 color_plane_info->x = r.x1;
1413                 color_plane_info->y = r.y1;
1414
1415                 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height;
1416                 color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1417
1418                 size += remap_info->dst_stride * remap_info->width;
1419
1420                 /* rotate the tile dimensions to match the GTT view */
1421                 swap(tile_width, tile_height);
1422         } else {
1423                 drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);
1424
1425                 check_array_bounds(i915, view->gtt.remapped.plane, color_plane);
1426
1427                 if (view->gtt.remapped.plane_alignment) {
1428                         unsigned int aligned_offset = ALIGN(gtt_offset,
1429                                                             view->gtt.remapped.plane_alignment);
1430
1431                         size += aligned_offset - gtt_offset;
1432                         gtt_offset = aligned_offset;
1433                 }
1434
1435                 color_plane_info->x = x;
1436                 color_plane_info->y = y;
1437
1438                 if (remap_info->linear) {
1439                         color_plane_info->mapping_stride = fb->base.pitches[color_plane];
1440                         color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1441
1442                         size += remap_info->size;
1443                 } else {
1444                         unsigned int dst_stride = plane_view_dst_stride_tiles(fb, color_plane,
1445                                                                               remap_info->width);
1446
1447                         assign_chk_ovf(i915, remap_info->dst_stride, dst_stride);
1448                         color_plane_info->mapping_stride = dst_stride *
1449                                                            tile_width *
1450                                                            fb->base.format->cpp[color_plane];
1451                         color_plane_info->scanout_stride =
1452                                 plane_view_scanout_stride(fb, color_plane, tile_width,
1453                                                           remap_info->src_stride,
1454                                                           dst_stride);
1455
1456                         size += dst_stride * remap_info->height;
1457                 }
1458         }
1459
1460         /*
1461          * We only keep the x/y offsets, so push all of the gtt offset into
1462          * the x/y offsets.  x,y will hold the first pixel of the framebuffer
1463          * plane from the start of the remapped/rotated gtt mapping.
1464          */
1465         if (remap_info->linear)
1466                 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y,
1467                                            fb->base.format->cpp[color_plane],
1468                                            color_plane_info->mapping_stride,
1469                                            gtt_offset * tile_size, 0);
1470         else
1471                 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y,
1472                                          tile_width, tile_height,
1473                                          tile_size, remap_info->dst_stride,
1474                                          gtt_offset * tile_size, 0);
1475
1476         return size;
1477 }
1478
1479 #undef assign_chk_ovf
1480
1481 /* Return number of tiles @color_plane needs. */
1482 static unsigned int
1483 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,
1484                        const struct fb_plane_view_dims *dims,
1485                        int x, int y)
1486 {
1487         unsigned int tiles;
1488
1489         if (is_surface_linear(&fb->base, color_plane)) {
1490                 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);
1491         } else {
1492                 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *
1493                         plane_view_height_tiles(fb, color_plane, dims, y);
1494                 /*
1495                  * If the plane isn't horizontally tile aligned,
1496                  * we need one more tile.
1497                  */
1498                 if (x != 0)
1499                         tiles++;
1500         }
1501
1502         return tiles;
1503 }
1504
1505 static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view,
1506                                enum i915_gtt_view_type view_type)
1507 {
1508         memset(view, 0, sizeof(*view));
1509         view->gtt.type = view_type;
1510
1511         if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
1512                 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
1513 }
1514
1515 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
1516 {
1517         if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)
1518                 return false;
1519
1520         return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
1521                fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
1522 }
1523
1524 int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
1525 {
1526         struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1527         u32 gtt_offset_rotated = 0;
1528         u32 gtt_offset_remapped = 0;
1529         unsigned int max_size = 0;
1530         int i, num_planes = fb->base.format->num_planes;
1531         unsigned int tile_size = intel_tile_size(i915);
1532
1533         intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL);
1534
1535         drm_WARN_ON(&i915->drm,
1536                     intel_fb_supports_90_270_rotation(fb) &&
1537                     intel_fb_needs_pot_stride_remap(fb));
1538
1539         if (intel_fb_supports_90_270_rotation(fb))
1540                 intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED);
1541         if (intel_fb_needs_pot_stride_remap(fb))
1542                 intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);
1543
1544         for (i = 0; i < num_planes; i++) {
1545                 struct fb_plane_view_dims view_dims;
1546                 unsigned int width, height;
1547                 unsigned int cpp, size;
1548                 u32 offset;
1549                 int x, y;
1550                 int ret;
1551
1552                 /*
1553                  * Plane 2 of Render Compression with Clear Color fb modifier
1554                  * is consumed by the driver and not passed to DE. Skip the
1555                  * arithmetic related to alignment and offset calculation.
1556                  */
1557                 if (is_gen12_ccs_cc_plane(&fb->base, i)) {
1558                         if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
1559                                 continue;
1560                         else
1561                                 return -EINVAL;
1562                 }
1563
1564                 cpp = fb->base.format->cpp[i];
1565                 intel_fb_plane_dims(fb, i, &width, &height);
1566
1567                 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);
1568                 if (ret)
1569                         return ret;
1570
1571                 init_plane_view_dims(fb, i, width, height, &view_dims);
1572
1573                 /*
1574                  * First pixel of the framebuffer from
1575                  * the start of the normal gtt mapping.
1576                  */
1577                 fb->normal_view.color_plane[i].x = x;
1578                 fb->normal_view.color_plane[i].y = y;
1579                 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i];
1580                 fb->normal_view.color_plane[i].scanout_stride =
1581                         fb->normal_view.color_plane[i].mapping_stride;
1582
1583                 offset = calc_plane_aligned_offset(fb, i, &x, &y);
1584
1585                 if (intel_fb_supports_90_270_rotation(fb))
1586                         gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
1587                                                                     offset, gtt_offset_rotated, x, y,
1588                                                                     &fb->rotated_view);
1589
1590                 if (intel_fb_needs_pot_stride_remap(fb))
1591                         gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims,
1592                                                                      offset, gtt_offset_remapped, x, y,
1593                                                                      &fb->remapped_view);
1594
1595                 size = calc_plane_normal_size(fb, i, &view_dims, x, y);
1596                 /* how many tiles in total needed in the bo */
1597                 max_size = max(max_size, offset + size);
1598         }
1599
1600         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
1601                 drm_dbg_kms(&i915->drm,
1602                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
1603                             mul_u32_u32(max_size, tile_size), obj->base.size);
1604                 return -EINVAL;
1605         }
1606
1607         return 0;
1608 }
1609
1610 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
1611 {
1612         struct drm_i915_private *i915 =
1613                 to_i915(plane_state->uapi.plane->dev);
1614         struct drm_framebuffer *fb = plane_state->hw.fb;
1615         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1616         unsigned int rotation = plane_state->hw.rotation;
1617         int i, num_planes = fb->format->num_planes;
1618         unsigned int src_x, src_y;
1619         unsigned int src_w, src_h;
1620         u32 gtt_offset = 0;
1621
1622         intel_fb_view_init(i915, &plane_state->view,
1623                            drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED :
1624                                                               I915_GTT_VIEW_REMAPPED);
1625
1626         src_x = plane_state->uapi.src.x1 >> 16;
1627         src_y = plane_state->uapi.src.y1 >> 16;
1628         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1629         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1630
1631         drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
1632
1633         /* Make src coordinates relative to the viewport */
1634         drm_rect_translate(&plane_state->uapi.src,
1635                            -(src_x << 16), -(src_y << 16));
1636
1637         /* Rotate src coordinates to match rotated GTT view */
1638         if (drm_rotation_90_or_270(rotation))
1639                 drm_rect_rotate(&plane_state->uapi.src,
1640                                 src_w << 16, src_h << 16,
1641                                 DRM_MODE_ROTATE_270);
1642
1643         for (i = 0; i < num_planes; i++) {
1644                 unsigned int hsub = i ? fb->format->hsub : 1;
1645                 unsigned int vsub = i ? fb->format->vsub : 1;
1646                 struct fb_plane_view_dims view_dims;
1647                 unsigned int width, height;
1648                 unsigned int x, y;
1649                 u32 offset;
1650
1651                 x = src_x / hsub;
1652                 y = src_y / vsub;
1653                 width = src_w / hsub;
1654                 height = src_h / vsub;
1655
1656                 init_plane_view_dims(intel_fb, i, width, height, &view_dims);
1657
1658                 /*
1659                  * First pixel of the src viewport from the
1660                  * start of the normal gtt mapping.
1661                  */
1662                 x += intel_fb->normal_view.color_plane[i].x;
1663                 y += intel_fb->normal_view.color_plane[i].y;
1664
1665                 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y);
1666
1667                 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims,
1668                                                     offset, gtt_offset, x, y,
1669                                                     &plane_state->view);
1670         }
1671 }
1672
1673 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
1674                         struct intel_fb_view *view)
1675 {
1676         if (drm_rotation_90_or_270(rotation))
1677                 *view = fb->rotated_view;
1678         else if (intel_fb_needs_pot_stride_remap(fb))
1679                 *view = fb->remapped_view;
1680         else
1681                 *view = fb->normal_view;
1682 }
1683
1684 static
1685 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1686                         u32 pixel_format, u64 modifier)
1687 {
1688         /*
1689          * Arbitrary limit for gen4+ chosen to match the
1690          * render engine max stride.
1691          *
1692          * The new CCS hash mode makes remapping impossible
1693          */
1694         if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
1695             intel_modifier_uses_dpt(dev_priv, modifier))
1696                 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1697         else if (DISPLAY_VER(dev_priv) >= 7)
1698                 return 256 * 1024;
1699         else
1700                 return 128 * 1024;
1701 }
1702
1703 static u32
1704 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1705 {
1706         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1707         u32 tile_width;
1708
1709         if (is_surface_linear(fb, color_plane)) {
1710                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1711                                                            fb->format->format,
1712                                                            fb->modifier);
1713
1714                 /*
1715                  * To make remapping with linear generally feasible
1716                  * we need the stride to be page aligned.
1717                  */
1718                 if (fb->pitches[color_plane] > max_stride &&
1719                     !intel_fb_is_ccs_modifier(fb->modifier))
1720                         return intel_tile_size(dev_priv);
1721                 else
1722                         return 64;
1723         }
1724
1725         tile_width = intel_tile_width_bytes(fb, color_plane);
1726         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1727                 /*
1728                  * On TGL the surface stride must be 4 tile aligned, mapped by
1729                  * one 64 byte cacheline on the CCS AUX surface.
1730                  */
1731                 if (DISPLAY_VER(dev_priv) >= 12)
1732                         tile_width *= 4;
1733                 /*
1734                  * Display WA #0531: skl,bxt,kbl,glk
1735                  *
1736                  * Render decompression and plane width > 3840
1737                  * combined with horizontal panning requires the
1738                  * plane stride to be a multiple of 4. We'll just
1739                  * require the entire fb to accommodate that to avoid
1740                  * potential runtime errors at plane configuration time.
1741                  */
1742                 else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1743                          color_plane == 0 && fb->width > 3840)
1744                         tile_width *= 4;
1745         }
1746         return tile_width;
1747 }
1748
1749 static int intel_plane_check_stride(const struct intel_plane_state *plane_state)
1750 {
1751         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1752         const struct drm_framebuffer *fb = plane_state->hw.fb;
1753         unsigned int rotation = plane_state->hw.rotation;
1754         u32 stride, max_stride;
1755
1756         /*
1757          * We ignore stride for all invisible planes that
1758          * can be remapped. Otherwise we could end up
1759          * with a false positive when the remapping didn't
1760          * kick in due the plane being invisible.
1761          */
1762         if (intel_plane_can_remap(plane_state) &&
1763             !plane_state->uapi.visible)
1764                 return 0;
1765
1766         /* FIXME other color planes? */
1767         stride = plane_state->view.color_plane[0].mapping_stride;
1768         max_stride = plane->max_stride(plane, fb->format->format,
1769                                        fb->modifier, rotation);
1770
1771         if (stride > max_stride) {
1772                 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
1773                               fb->base.id, stride,
1774                               plane->base.base.id, plane->base.name, max_stride);
1775                 return -EINVAL;
1776         }
1777
1778         return 0;
1779 }
1780
1781 int intel_plane_compute_gtt(struct intel_plane_state *plane_state)
1782 {
1783         const struct intel_framebuffer *fb =
1784                 to_intel_framebuffer(plane_state->hw.fb);
1785         unsigned int rotation = plane_state->hw.rotation;
1786
1787         if (!fb)
1788                 return 0;
1789
1790         if (intel_plane_needs_remap(plane_state)) {
1791                 intel_plane_remap_gtt(plane_state);
1792
1793                 /*
1794                  * Sometimes even remapping can't overcome
1795                  * the stride limitations :( Can happen with
1796                  * big plane sizes and suitably misaligned
1797                  * offsets.
1798                  */
1799                 return intel_plane_check_stride(plane_state);
1800         }
1801
1802         intel_fb_fill_view(fb, rotation, &plane_state->view);
1803
1804         /* Rotate src coordinates to match rotated GTT view */
1805         if (drm_rotation_90_or_270(rotation))
1806                 drm_rect_rotate(&plane_state->uapi.src,
1807                                 fb->base.width << 16, fb->base.height << 16,
1808                                 DRM_MODE_ROTATE_270);
1809
1810         return intel_plane_check_stride(plane_state);
1811 }
1812
1813 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1814 {
1815         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1816
1817         drm_framebuffer_cleanup(fb);
1818
1819         if (intel_fb_uses_dpt(fb))
1820                 intel_dpt_destroy(intel_fb->dpt_vm);
1821
1822         intel_frontbuffer_put(intel_fb->frontbuffer);
1823
1824         kfree(intel_fb);
1825 }
1826
1827 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1828                                                 struct drm_file *file,
1829                                                 unsigned int *handle)
1830 {
1831         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1832         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1833
1834         if (i915_gem_object_is_userptr(obj)) {
1835                 drm_dbg(&i915->drm,
1836                         "attempting to use a userptr for a framebuffer, denied\n");
1837                 return -EINVAL;
1838         }
1839
1840         return drm_gem_handle_create(file, &obj->base, handle);
1841 }
1842
1843 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
1844                                         struct drm_file *file,
1845                                         unsigned int flags, unsigned int color,
1846                                         struct drm_clip_rect *clips,
1847                                         unsigned int num_clips)
1848 {
1849         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1850
1851         i915_gem_object_flush_if_display(obj);
1852         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
1853
1854         return 0;
1855 }
1856
1857 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1858         .destroy = intel_user_framebuffer_destroy,
1859         .create_handle = intel_user_framebuffer_create_handle,
1860         .dirty = intel_user_framebuffer_dirty,
1861 };
1862
1863 int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
1864                            struct drm_i915_gem_object *obj,
1865                            struct drm_mode_fb_cmd2 *mode_cmd)
1866 {
1867         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
1868         struct drm_framebuffer *fb = &intel_fb->base;
1869         u32 max_stride;
1870         unsigned int tiling, stride;
1871         int ret = -EINVAL;
1872         int i;
1873
1874         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
1875         if (!intel_fb->frontbuffer)
1876                 return -ENOMEM;
1877
1878         i915_gem_object_lock(obj, NULL);
1879         tiling = i915_gem_object_get_tiling(obj);
1880         stride = i915_gem_object_get_stride(obj);
1881         i915_gem_object_unlock(obj);
1882
1883         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
1884                 /*
1885                  * If there's a fence, enforce that
1886                  * the fb modifier and tiling mode match.
1887                  */
1888                 if (tiling != I915_TILING_NONE &&
1889                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
1890                         drm_dbg_kms(&dev_priv->drm,
1891                                     "tiling_mode doesn't match fb modifier\n");
1892                         goto err;
1893                 }
1894         } else {
1895                 if (tiling == I915_TILING_X) {
1896                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
1897                 } else if (tiling == I915_TILING_Y) {
1898                         drm_dbg_kms(&dev_priv->drm,
1899                                     "No Y tiling for legacy addfb\n");
1900                         goto err;
1901                 }
1902         }
1903
1904         if (!drm_any_plane_has_format(&dev_priv->drm,
1905                                       mode_cmd->pixel_format,
1906                                       mode_cmd->modifier[0])) {
1907                 drm_dbg_kms(&dev_priv->drm,
1908                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
1909                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1910                 goto err;
1911         }
1912
1913         /*
1914          * gen2/3 display engine uses the fence if present,
1915          * so the tiling mode must match the fb modifier exactly.
1916          */
1917         if (DISPLAY_VER(dev_priv) < 4 &&
1918             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
1919                 drm_dbg_kms(&dev_priv->drm,
1920                             "tiling_mode must match fb modifier exactly on gen2/3\n");
1921                 goto err;
1922         }
1923
1924         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
1925                                          mode_cmd->modifier[0]);
1926         if (mode_cmd->pitches[0] > max_stride) {
1927                 drm_dbg_kms(&dev_priv->drm,
1928                             "%s pitch (%u) must be at most %d\n",
1929                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
1930                             "tiled" : "linear",
1931                             mode_cmd->pitches[0], max_stride);
1932                 goto err;
1933         }
1934
1935         /*
1936          * If there's a fence, enforce that
1937          * the fb pitch and fence stride match.
1938          */
1939         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
1940                 drm_dbg_kms(&dev_priv->drm,
1941                             "pitch (%d) must match tiling stride (%d)\n",
1942                             mode_cmd->pitches[0], stride);
1943                 goto err;
1944         }
1945
1946         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
1947         if (mode_cmd->offsets[0] != 0) {
1948                 drm_dbg_kms(&dev_priv->drm,
1949                             "plane 0 offset (0x%08x) must be 0\n",
1950                             mode_cmd->offsets[0]);
1951                 goto err;
1952         }
1953
1954         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
1955
1956         for (i = 0; i < fb->format->num_planes; i++) {
1957                 u32 stride_alignment;
1958
1959                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1960                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
1961                                     i);
1962                         goto err;
1963                 }
1964
1965                 stride_alignment = intel_fb_stride_alignment(fb, i);
1966                 if (fb->pitches[i] & (stride_alignment - 1)) {
1967                         drm_dbg_kms(&dev_priv->drm,
1968                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
1969                                     i, fb->pitches[i], stride_alignment);
1970                         goto err;
1971                 }
1972
1973                 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {
1974                         int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
1975
1976                         if (fb->pitches[i] != ccs_aux_stride) {
1977                                 drm_dbg_kms(&dev_priv->drm,
1978                                             "ccs aux plane %d pitch (%d) must be %d\n",
1979                                             i,
1980                                             fb->pitches[i], ccs_aux_stride);
1981                                 goto err;
1982                         }
1983                 }
1984
1985                 fb->obj[i] = &obj->base;
1986         }
1987
1988         ret = intel_fill_fb_info(dev_priv, intel_fb);
1989         if (ret)
1990                 goto err;
1991
1992         if (intel_fb_uses_dpt(fb)) {
1993                 struct i915_address_space *vm;
1994
1995                 vm = intel_dpt_create(intel_fb);
1996                 if (IS_ERR(vm)) {
1997                         ret = PTR_ERR(vm);
1998                         goto err;
1999                 }
2000
2001                 intel_fb->dpt_vm = vm;
2002         }
2003
2004         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
2005         if (ret) {
2006                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
2007                 goto err;
2008         }
2009
2010         return 0;
2011
2012 err:
2013         intel_frontbuffer_put(intel_fb->frontbuffer);
2014         return ret;
2015 }
2016
2017 struct drm_framebuffer *
2018 intel_user_framebuffer_create(struct drm_device *dev,
2019                               struct drm_file *filp,
2020                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
2021 {
2022         struct drm_framebuffer *fb;
2023         struct drm_i915_gem_object *obj;
2024         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
2025         struct drm_i915_private *i915;
2026
2027         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
2028         if (!obj)
2029                 return ERR_PTR(-ENOENT);
2030
2031         /* object is backed with LMEM for discrete */
2032         i915 = to_i915(obj->base.dev);
2033         if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
2034                 /* object is "remote", not in local memory */
2035                 i915_gem_object_put(obj);
2036                 return ERR_PTR(-EREMOTE);
2037         }
2038
2039         fb = intel_framebuffer_create(obj, &mode_cmd);
2040         i915_gem_object_put(obj);
2041
2042         return fb;
2043 }
2044
2045 struct drm_framebuffer *
2046 intel_framebuffer_create(struct drm_i915_gem_object *obj,
2047                          struct drm_mode_fb_cmd2 *mode_cmd)
2048 {
2049         struct intel_framebuffer *intel_fb;
2050         int ret;
2051
2052         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2053         if (!intel_fb)
2054                 return ERR_PTR(-ENOMEM);
2055
2056         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
2057         if (ret)
2058                 goto err;
2059
2060         return &intel_fb->base;
2061
2062 err:
2063         kfree(intel_fb);
2064         return ERR_PTR(ret);
2065 }