2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_display_types.h"
26 #include "intel_dp_link_training.h"
29 intel_dp_dump_link_status(struct drm_device *drm,
30 const u8 link_status[DP_LINK_STATUS_SIZE])
33 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
34 link_status[0], link_status[1], link_status[2],
35 link_status[3], link_status[4], link_status[5]);
38 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
40 memset(&intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
43 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
45 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
46 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
49 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
50 char *buf, size_t buf_size)
52 if (dp_phy == DP_PHY_DPRX)
53 snprintf(buf, buf_size, "DPRX");
55 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
60 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
61 enum drm_dp_phy dp_phy)
63 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
66 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
67 enum drm_dp_phy dp_phy)
69 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
72 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
74 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
75 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
76 "failed to read the PHY caps for %s\n",
81 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
82 "%s PHY capabilities: %*ph\n",
84 (int)sizeof(intel_dp->lttpr_phy_caps[0]),
88 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
90 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
92 if (intel_dp_is_edp(intel_dp))
96 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
97 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
99 if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
102 if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
103 intel_dp->lttpr_common_caps) < 0)
106 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
107 "LTTPR common capabilities: %*ph\n",
108 (int)sizeof(intel_dp->lttpr_common_caps),
109 intel_dp->lttpr_common_caps);
111 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
112 if (intel_dp->lttpr_common_caps[0] < 0x14)
118 intel_dp_reset_lttpr_common_caps(intel_dp);
123 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
125 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
126 DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
128 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
132 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
133 * @intel_dp: Intel DP struct
135 * Read the LTTPR common and DPRX capabilities and switch to non-transparent
136 * link training mode if any is detected and read the PHY capabilities for all
137 * detected LTTPRs. In case of an LTTPR detection error or if the number of
138 * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
139 * transparent mode link training mode.
142 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The
143 * DPRX capabilities are read out.
144 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
145 * detection failure and the transparent LT mode was set. The DPRX
146 * capabilities are read out.
147 * <0 Reading out the DPRX capabilities failed.
149 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
155 ret = intel_dp_read_lttpr_common_caps(intel_dp);
157 /* The DPTX shall read the DPRX caps after LTTPR detection. */
158 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
159 intel_dp_reset_lttpr_common_caps(intel_dp);
167 * The 0xF0000-0xF02FF range is only valid if the DPCD revision is
170 if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) {
171 intel_dp_reset_lttpr_common_caps(intel_dp);
175 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
177 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
178 * detected as this breaks link training at least on the Dell WD19TB
181 if (lttpr_count == 0)
185 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
186 * non-transparent mode and the disable->enable non-transparent mode
189 intel_dp_set_lttpr_transparent_mode(intel_dp, true);
192 * In case of unsupported number of LTTPRs or failing to switch to
193 * non-transparent mode fall-back to transparent link training mode,
194 * still taking into account any LTTPR common lane- rate/count limits.
199 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
200 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
201 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
203 intel_dp_set_lttpr_transparent_mode(intel_dp, true);
204 intel_dp_reset_lttpr_count(intel_dp);
209 for (i = 0; i < lttpr_count; i++)
210 intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
214 EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);
216 static u8 dp_voltage_max(u8 preemph)
218 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
219 case DP_TRAIN_PRE_EMPH_LEVEL_0:
220 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
221 case DP_TRAIN_PRE_EMPH_LEVEL_1:
222 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
223 case DP_TRAIN_PRE_EMPH_LEVEL_2:
224 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
225 case DP_TRAIN_PRE_EMPH_LEVEL_3:
227 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
231 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
232 enum drm_dp_phy dp_phy)
234 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
236 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
237 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
239 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
242 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
243 enum drm_dp_phy dp_phy)
245 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
247 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
248 return DP_TRAIN_PRE_EMPH_LEVEL_3;
250 return DP_TRAIN_PRE_EMPH_LEVEL_2;
254 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
255 enum drm_dp_phy dp_phy)
257 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
258 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
260 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
262 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
265 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
266 const struct intel_crtc_state *crtc_state,
267 enum drm_dp_phy dp_phy)
269 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
273 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
274 * the DPRX_PHY we train.
276 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
277 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
279 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
281 drm_WARN_ON_ONCE(&i915->drm,
282 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
283 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
288 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
289 enum drm_dp_phy dp_phy)
291 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
295 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
296 * the DPRX_PHY we train.
298 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
299 preemph_max = intel_dp->preemph_max(intel_dp);
301 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
303 drm_WARN_ON_ONCE(&i915->drm,
304 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
305 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
311 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
312 const struct intel_crtc_state *crtc_state,
313 enum drm_dp_phy dp_phy,
314 const u8 link_status[DP_LINK_STATUS_SIZE])
322 for (lane = 0; lane < crtc_state->lane_count; lane++) {
323 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
324 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
327 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
328 if (p >= preemph_max)
329 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
331 v = min(v, dp_voltage_max(p));
333 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
334 if (v >= voltage_max)
335 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
337 for (lane = 0; lane < 4; lane++)
338 intel_dp->train_set[lane] = v | p;
341 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
342 enum drm_dp_phy dp_phy)
344 return dp_phy == DP_PHY_DPRX ?
345 DP_TRAINING_PATTERN_SET :
346 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
350 intel_dp_set_link_train(struct intel_dp *intel_dp,
351 const struct intel_crtc_state *crtc_state,
352 enum drm_dp_phy dp_phy,
355 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
356 u8 buf[sizeof(intel_dp->train_set) + 1];
359 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
362 buf[0] = dp_train_pat;
363 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
364 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
365 len = crtc_state->lane_count + 1;
367 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
370 static char dp_training_pattern_name(u8 train_pat)
373 case DP_TRAINING_PATTERN_1:
374 case DP_TRAINING_PATTERN_2:
375 case DP_TRAINING_PATTERN_3:
376 return '0' + train_pat;
377 case DP_TRAINING_PATTERN_4:
380 MISSING_CASE(train_pat);
386 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
387 const struct intel_crtc_state *crtc_state,
390 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
391 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
392 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
394 if (train_pat != DP_TRAINING_PATTERN_DISABLE)
395 drm_dbg_kms(&dev_priv->drm,
396 "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
397 encoder->base.base.id, encoder->base.name,
398 dp_training_pattern_name(train_pat));
400 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
403 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
404 const struct intel_crtc_state *crtc_state,
405 enum drm_dp_phy dp_phy)
407 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
408 u8 train_set = intel_dp->train_set[0];
411 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
412 train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
413 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
414 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
415 DP_TRAIN_PRE_EMPHASIS_SHIFT,
416 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
418 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
420 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
421 intel_dp->set_signal_levels(intel_dp, crtc_state);
425 intel_dp_reset_link_train(struct intel_dp *intel_dp,
426 const struct intel_crtc_state *crtc_state,
427 enum drm_dp_phy dp_phy,
430 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
431 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
432 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
436 intel_dp_update_link_train(struct intel_dp *intel_dp,
437 const struct intel_crtc_state *crtc_state,
438 enum drm_dp_phy dp_phy)
440 int reg = dp_phy == DP_PHY_DPRX ?
441 DP_TRAINING_LANE0_SET :
442 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
445 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
447 ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
448 intel_dp->train_set, crtc_state->lane_count);
450 return ret == crtc_state->lane_count;
453 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
454 const struct intel_crtc_state *crtc_state)
458 for (lane = 0; lane < crtc_state->lane_count; lane++)
459 if ((intel_dp->train_set[lane] &
460 DP_TRAIN_MAX_SWING_REACHED) == 0)
467 * Prepare link training by configuring the link parameters. On DDI platforms
468 * also enable the port here.
471 intel_dp_prepare_link_train(struct intel_dp *intel_dp,
472 const struct intel_crtc_state *crtc_state)
474 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
476 u8 link_bw, rate_select;
478 if (intel_dp->prepare_link_retrain)
479 intel_dp->prepare_link_retrain(intel_dp, crtc_state);
481 intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
482 &link_bw, &rate_select);
485 drm_dbg_kms(&i915->drm,
486 "Using LINK_BW_SET value %02x\n", link_bw);
488 drm_dbg_kms(&i915->drm,
489 "Using LINK_RATE_SET value %02x\n", rate_select);
491 /* Write the link configuration data */
492 link_config[0] = link_bw;
493 link_config[1] = crtc_state->lane_count;
494 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
495 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
496 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
498 /* eDP 1.4 rate select method. */
500 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
503 link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
504 link_config[1] = DP_SET_ANSI_8B10B;
505 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
507 intel_dp->DP |= DP_PORT_EN;
512 static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp,
513 enum drm_dp_phy dp_phy)
515 if (dp_phy == DP_PHY_DPRX)
516 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
518 drm_dp_lttpr_link_train_clock_recovery_delay();
522 * Perform the link training clock recovery phase on the given DP PHY using
523 * training pattern 1.
526 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
527 const struct intel_crtc_state *crtc_state,
528 enum drm_dp_phy dp_phy)
530 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
532 int voltage_tries, cr_tries, max_cr_tries;
533 bool max_vswing_reached = false;
536 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
537 DP_TRAINING_PATTERN_1 |
538 DP_LINK_SCRAMBLING_DISABLE)) {
539 drm_err(&i915->drm, "failed to enable link training\n");
544 * The DP 1.4 spec defines the max clock recovery retries value
545 * as 10 but for pre-DP 1.4 devices we set a very tolerant
546 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
547 * x 5 identical voltage retries). Since the previous specs didn't
548 * define a limit and created the possibility of an infinite loop
549 * we want to prevent any sync from triggering that corner case.
551 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
557 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
558 u8 link_status[DP_LINK_STATUS_SIZE];
560 intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
562 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
564 drm_err(&i915->drm, "failed to get link status\n");
568 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
569 drm_dbg_kms(&i915->drm, "clock recovery OK\n");
573 if (voltage_tries == 5) {
574 drm_dbg_kms(&i915->drm,
575 "Same voltage tried 5 times\n");
579 if (max_vswing_reached) {
580 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
584 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
586 /* Update training set as requested by target */
587 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
589 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
591 "failed to update link training\n");
595 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
601 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
602 max_vswing_reached = true;
606 "Failed clock recovery %d times, giving up!\n", max_cr_tries);
611 * Pick training pattern for channel equalization. Training pattern 4 for HBR3
612 * or for 1.4 devices that support it, training Pattern 3 for HBR2
613 * or 1.2 devices that support it, Training Pattern 2 otherwise.
615 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
616 const struct intel_crtc_state *crtc_state,
617 enum drm_dp_phy dp_phy)
619 bool source_tps3, sink_tps3, source_tps4, sink_tps4;
622 * Intel platforms that support HBR3 also support TPS4. It is mandatory
623 * for all downstream devices that support HBR3. There are no known eDP
624 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
626 * LTTPRs must support TPS4.
628 source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
629 sink_tps4 = dp_phy != DP_PHY_DPRX ||
630 drm_dp_tps4_supported(intel_dp->dpcd);
631 if (source_tps4 && sink_tps4) {
632 return DP_TRAINING_PATTERN_4;
633 } else if (crtc_state->port_clock == 810000) {
635 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
636 "8.1 Gbps link rate without source HBR3/TPS4 support\n");
638 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
639 "8.1 Gbps link rate without sink TPS4 support\n");
642 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
643 * also mandatory for downstream devices that support HBR2. However, not
644 * all sinks follow the spec.
646 source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
647 sink_tps3 = dp_phy != DP_PHY_DPRX ||
648 drm_dp_tps3_supported(intel_dp->dpcd);
649 if (source_tps3 && sink_tps3) {
650 return DP_TRAINING_PATTERN_3;
651 } else if (crtc_state->port_clock >= 540000) {
653 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
654 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
656 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
657 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
660 return DP_TRAINING_PATTERN_2;
664 intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
665 enum drm_dp_phy dp_phy)
667 if (dp_phy == DP_PHY_DPRX) {
668 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
670 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
672 drm_dp_lttpr_link_train_channel_eq_delay(phy_caps);
677 * Perform the link training channel equalization phase on the given DP PHY
678 * using one of training pattern 2, 3 or 4 depending on the source and
682 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
683 const struct intel_crtc_state *crtc_state,
684 enum drm_dp_phy dp_phy)
686 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
688 u32 training_pattern;
689 u8 link_status[DP_LINK_STATUS_SIZE];
690 bool channel_eq = false;
692 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
693 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
694 if (training_pattern != DP_TRAINING_PATTERN_4)
695 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
697 /* channel equalization */
698 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
700 drm_err(&i915->drm, "failed to start channel equalization\n");
704 for (tries = 0; tries < 5; tries++) {
705 intel_dp_link_training_channel_equalization_delay(intel_dp,
707 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
710 "failed to get link status\n");
714 /* Make sure clock is still ok */
715 if (!drm_dp_clock_recovery_ok(link_status,
716 crtc_state->lane_count)) {
717 intel_dp_dump_link_status(&i915->drm, link_status);
718 drm_dbg_kms(&i915->drm,
719 "Clock recovery check failed, cannot "
720 "continue channel equalization\n");
724 if (drm_dp_channel_eq_ok(link_status,
725 crtc_state->lane_count)) {
727 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
732 /* Update training set as requested by target */
733 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
735 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
737 "failed to update link training\n");
742 /* Try 5 times, else fail and try at lower BW */
744 intel_dp_dump_link_status(&i915->drm, link_status);
745 drm_dbg_kms(&i915->drm,
746 "Channel equalization failed 5 times\n");
752 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
753 enum drm_dp_phy dp_phy)
755 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
756 u8 val = DP_TRAINING_PATTERN_DISABLE;
758 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
762 * intel_dp_stop_link_train - stop link training
763 * @intel_dp: DP struct
764 * @crtc_state: state for CRTC attached to the encoder
766 * Stop the link training of the @intel_dp port, disabling the training
767 * pattern in the sink's DPCD, and disabling the test pattern symbol
768 * generation on the port.
770 * What symbols are output on the port after this point is
771 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
772 * with the pipe being disabled, on older platforms it's HW specific if/how an
773 * idle pattern is generated, as the pipe is already enabled here for those.
775 * This function must be called after intel_dp_start_link_train().
777 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
778 const struct intel_crtc_state *crtc_state)
780 intel_dp->link_trained = true;
782 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
783 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
784 DP_TRAINING_PATTERN_DISABLE);
788 intel_dp_link_train_phy(struct intel_dp *intel_dp,
789 const struct intel_crtc_state *crtc_state,
790 enum drm_dp_phy dp_phy)
792 struct intel_connector *intel_connector = intel_dp->attached_connector;
796 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
799 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
805 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
806 "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s\n",
807 intel_connector->base.base.id,
808 intel_connector->base.name,
809 ret ? "passed" : "failed",
810 crtc_state->port_clock, crtc_state->lane_count,
811 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
816 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
817 const struct intel_crtc_state *crtc_state)
819 struct intel_connector *intel_connector = intel_dp->attached_connector;
821 if (intel_dp->hobl_active) {
822 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
823 "Link Training failed with HOBL active, not enabling it from now on");
824 intel_dp->hobl_failed = true;
825 } else if (intel_dp_get_link_train_fallback_values(intel_dp,
826 crtc_state->port_clock,
827 crtc_state->lane_count)) {
831 /* Schedule a Hotplug Uevent to userspace to start modeset */
832 schedule_work(&intel_connector->modeset_retry_work);
835 /* Perform the link training on all LTTPRs and the DPRX on a link. */
837 intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
838 const struct intel_crtc_state *crtc_state,
844 intel_dp_prepare_link_train(intel_dp, crtc_state);
846 for (i = lttpr_count - 1; i >= 0; i--) {
847 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
849 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
850 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
857 intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
859 if (intel_dp->set_idle_link_train)
860 intel_dp->set_idle_link_train(intel_dp, crtc_state);
866 * intel_dp_start_link_train - start link training
867 * @intel_dp: DP struct
868 * @crtc_state: state for CRTC attached to the encoder
870 * Start the link training of the @intel_dp port, scheduling a fallback
871 * retraining with reduced link rate/lane parameters if the link training
873 * After calling this function intel_dp_stop_link_train() must be called.
875 void intel_dp_start_link_train(struct intel_dp *intel_dp,
876 const struct intel_crtc_state *crtc_state)
879 * TODO: Reiniting LTTPRs here won't be needed once proper connector
880 * HW state readout is added.
882 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
885 /* Still continue with enabling the port and link training. */
888 if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
889 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);