drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_drv.h"
  48 #include "i915_irq.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_cx0_phy.h"
  57 #include "intel_ddi.h"
  58 #include "intel_de.h"
  59 #include "intel_display_driver.h"
  60 #include "intel_display_types.h"
  61 #include "intel_dp.h"
  62 #include "intel_dp_aux.h"
  63 #include "intel_dp_hdcp.h"
  64 #include "intel_dp_link_training.h"
  65 #include "intel_dp_mst.h"
  66 #include "intel_dpio_phy.h"
  67 #include "intel_dpll.h"
  68 #include "intel_fifo_underrun.h"
  69 #include "intel_hdcp.h"
  70 #include "intel_hdmi.h"
  71 #include "intel_hotplug.h"
  72 #include "intel_hotplug_irq.h"
  73 #include "intel_lspcon.h"
  74 #include "intel_lvds.h"
  75 #include "intel_panel.h"
  76 #include "intel_pch_display.h"
  77 #include "intel_pps.h"
  78 #include "intel_psr.h"
  79 #include "intel_tc.h"
  80 #include "intel_vdsc.h"
  81 #include "intel_vrr.h"
  82 #include "intel_crtc_state_dump.h"
  83
  84 /* DP DSC throughput values used for slice count calculations KPixels/s */
  85 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  86 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  87 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  88
  89 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
  90 #define DP_DSC_FEC_OVERHEAD_FACTOR              1028530
  91
  92 /* Compliance test status bits  */
  93 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  94 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  95 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  96 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  97
  98
  99 /* Constants for DP DSC configurations */
 100 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 101
 102 /* With Single pipe configuration, HW is capable of supporting maximum
 103  * of 4 slices per line.
 104  */
 105 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 106
 107 /**
 108  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 109  * @intel_dp: DP struct
 110  *
 111  * If a CPU or PCH DP output is attached to an eDP panel, this function
 112  * will return true, and false otherwise.
 113  *
 114  * This function is not safe to use prior to encoder type being set.
 115  */
 116 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 117 {
 118         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 119
 120         return dig_port->base.type == INTEL_OUTPUT_EDP;
 121 }
 122
 123 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 124
 125 /* Is link rate UHBR and thus 128b/132b? */
 126 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 127 {
 128         return drm_dp_is_uhbr_rate(crtc_state->port_clock);
 129 }
 130
 131 /**
 132  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
 133  * @rate: link rate in 10kbit/s units
 134  *
 135  * Returns the link symbol size in bits/symbol units depending on the link
 136  * rate -> channel coding.
 137  */
 138 int intel_dp_link_symbol_size(int rate)
 139 {
 140         return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
 141 }
 142
 143 /**
 144  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
 145  * @rate: link rate in 10kbit/s units
 146  *
 147  * Returns the link symbol clock frequency in kHz units depending on the
 148  * link rate and channel coding.
 149  */
 150 int intel_dp_link_symbol_clock(int rate)
 151 {
 152         return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 153 }
 154
 155 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 156 {
 157         intel_dp->sink_rates[0] = 162000;
 158         intel_dp->num_sink_rates = 1;
 159 }
 160
 161 /* update sink rates from dpcd */
 162 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 163 {
 164         static const int dp_rates[] = {
 165                 162000, 270000, 540000, 810000
 166         };
 167         int i, max_rate;
 168         int max_lttpr_rate;
 169
 170         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 171                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 172                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 173
 174                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 175                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 176
 177                 return;
 178         }
 179
 180         /*
 181          * Sink rates for 8b/10b.
 182          */
 183         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 184         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 185         if (max_lttpr_rate)
 186                 max_rate = min(max_rate, max_lttpr_rate);
 187
 188         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 189                 if (dp_rates[i] > max_rate)
 190                         break;
 191                 intel_dp->sink_rates[i] = dp_rates[i];
 192         }
 193
 194         /*
 195          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 196          * rates and 10 Gbps.
 197          */
 198         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 199                 u8 uhbr_rates = 0;
 200
 201                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 202
 203                 drm_dp_dpcd_readb(&intel_dp->aux,
 204                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 205
 206                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 207                         /* We have a repeater */
 208                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 209                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 210                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 211                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 212                                 /* Repeater supports 128b/132b, valid UHBR rates */
 213                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 214                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 215                         } else {
 216                                 /* Does not support 128b/132b */
 217                                 uhbr_rates = 0;
 218                         }
 219                 }
 220
 221                 if (uhbr_rates & DP_UHBR10)
 222                         intel_dp->sink_rates[i++] = 1000000;
 223                 if (uhbr_rates & DP_UHBR13_5)
 224                         intel_dp->sink_rates[i++] = 1350000;
 225                 if (uhbr_rates & DP_UHBR20)
 226                         intel_dp->sink_rates[i++] = 2000000;
 227         }
 228
 229         intel_dp->num_sink_rates = i;
 230 }
 231
 232 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 233 {
 234         struct intel_connector *connector = intel_dp->attached_connector;
 235         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 236         struct intel_encoder *encoder = &intel_dig_port->base;
 237
 238         intel_dp_set_dpcd_sink_rates(intel_dp);
 239
 240         if (intel_dp->num_sink_rates)
 241                 return;
 242
 243         drm_err(&dp_to_i915(intel_dp)->drm,
 244                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 245                 connector->base.base.id, connector->base.name,
 246                 encoder->base.base.id, encoder->base.name);
 247
 248         intel_dp_set_default_sink_rates(intel_dp);
 249 }
 250
 251 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 252 {
 253         intel_dp->max_sink_lane_count = 1;
 254 }
 255
 256 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 257 {
 258         struct intel_connector *connector = intel_dp->attached_connector;
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261
 262         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 263
 264         switch (intel_dp->max_sink_lane_count) {
 265         case 1:
 266         case 2:
 267         case 4:
 268                 return;
 269         }
 270
 271         drm_err(&dp_to_i915(intel_dp)->drm,
 272                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 273                 connector->base.base.id, connector->base.name,
 274                 encoder->base.base.id, encoder->base.name,
 275                 intel_dp->max_sink_lane_count);
 276
 277         intel_dp_set_default_max_sink_lane_count(intel_dp);
 278 }
 279
 280 /* Get length of rates array potentially limited by max_rate. */
 281 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 282 {
 283         int i;
 284
 285         /* Limit results by potentially reduced max rate */
 286         for (i = 0; i < len; i++) {
 287                 if (rates[len - i - 1] <= max_rate)
 288                         return len - i;
 289         }
 290
 291         return 0;
 292 }
 293
 294 /* Get length of common rates array potentially limited by max_rate. */
 295 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 296                                           int max_rate)
 297 {
 298         return intel_dp_rate_limit_len(intel_dp->common_rates,
 299                                        intel_dp->num_common_rates, max_rate);
 300 }
 301
 302 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 303 {
 304         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 305                         index < 0 || index >= intel_dp->num_common_rates))
 306                 return 162000;
 307
 308         return intel_dp->common_rates[index];
 309 }
 310
 311 /* Theoretical max between source and sink */
 312 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 313 {
 314         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 315 }
 316
 317 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 318 {
 319         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 320         int max_lanes = dig_port->max_lanes;
 321
 322         if (vbt_max_lanes)
 323                 max_lanes = min(max_lanes, vbt_max_lanes);
 324
 325         return max_lanes;
 326 }
 327
 328 /* Theoretical max between source and sink */
 329 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 330 {
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         int source_max = intel_dp_max_source_lane_count(dig_port);
 333         int sink_max = intel_dp->max_sink_lane_count;
 334         int lane_max = intel_tc_port_max_lane_count(dig_port);
 335         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 336
 337         if (lttpr_max)
 338                 sink_max = min(sink_max, lttpr_max);
 339
 340         return min3(source_max, sink_max, lane_max);
 341 }
 342
 343 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 344 {
 345         switch (intel_dp->max_link_lane_count) {
 346         case 1:
 347         case 2:
 348         case 4:
 349                 return intel_dp->max_link_lane_count;
 350         default:
 351                 MISSING_CASE(intel_dp->max_link_lane_count);
 352                 return 1;
 353         }
 354 }
 355
 356 /*
 357  * The required data bandwidth for a mode with given pixel clock and bpp. This
 358  * is the required net bandwidth independent of the data bandwidth efficiency.
 359  *
 360  * TODO: check if callers of this functions should use
 361  * intel_dp_effective_data_rate() instead.
 362  */
 363 int
 364 intel_dp_link_required(int pixel_clock, int bpp)
 365 {
 366         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 367         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 368 }
 369
 370 /**
 371  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
 372  * @pixel_clock: pixel clock in kHz
 373  * @bpp_x16: bits per pixel .4 fixed point format
 374  * @bw_overhead: BW allocation overhead in 1ppm units
 375  *
 376  * Return the effective pixel data rate in kB/sec units taking into account
 377  * the provided SSC, FEC, DSC BW allocation overhead.
 378  */
 379 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 380                                  int bw_overhead)
 381 {
 382         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
 383                                 1000000 * 16 * 8);
 384 }
 385
 386 /*
 387  * Given a link rate and lanes, get the data bandwidth.
 388  *
 389  * Data bandwidth is the actual payload rate, which depends on the data
 390  * bandwidth efficiency and the link rate.
 391  *
 392  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 393  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 394  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 395  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 396  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 397  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 398  *
 399  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 400  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 401  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 402  * does not match the symbol clock, the port clock (not even if you think in
 403  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 404  * rate in units of 10000 bps.
 405  */
 406 int
 407 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 408 {
 409         int ch_coding_efficiency =
 410                 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
 411         int max_link_rate_kbps = max_link_rate * 10;
 412
 413         /*
 414          * UHBR rates always use 128b/132b channel encoding, and have
 415          * 97.71% data bandwidth efficiency. Consider max_link_rate the
 416          * link bit rate in units of 10000 bps.
 417          */
 418         /*
 419          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 420          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 421          * out to be a nop by coincidence:
 422          *
 423          *      int max_link_rate_kbps = max_link_rate * 10;
 424          *      max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10);
 425          *      max_link_rate = max_link_rate_kbps / 8;
 426          */
 427         return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
 428                                               ch_coding_efficiency),
 429                                   1000000 * 8);
 430 }
 431
 432 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 433 {
 434         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 435         struct intel_encoder *encoder = &intel_dig_port->base;
 436         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 437
 438         return DISPLAY_VER(dev_priv) >= 12 ||
 439                 (DISPLAY_VER(dev_priv) == 11 &&
 440                  encoder->port != PORT_A);
 441 }
 442
 443 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 444 {
 445         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 446 }
 447
 448 static int icl_max_source_rate(struct intel_dp *intel_dp)
 449 {
 450         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 451         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 452         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 453
 454         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 455                 return 540000;
 456
 457         return 810000;
 458 }
 459
 460 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 461 {
 462         if (intel_dp_is_edp(intel_dp))
 463                 return 540000;
 464
 465         return 810000;
 466 }
 467
 468 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 469 {
 470         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 471         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 472         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 473
 474         if (intel_is_c10phy(i915, phy))
 475                 return 810000;
 476
 477         return 2000000;
 478 }
 479
 480 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 481 {
 482         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 483         int max_rate;
 484
 485         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 486
 487         if (intel_dp_is_edp(intel_dp)) {
 488                 struct intel_connector *connector = intel_dp->attached_connector;
 489                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 490
 491                 if (max_rate && edp_max_rate)
 492                         max_rate = min(max_rate, edp_max_rate);
 493                 else if (edp_max_rate)
 494                         max_rate = edp_max_rate;
 495         }
 496
 497         return max_rate;
 498 }
 499
 500 static void
 501 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 502 {
 503         /* The values must be in increasing order */
 504         static const int mtl_rates[] = {
 505                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 506                 810000, 1000000, 1350000, 2000000,
 507         };
 508         static const int icl_rates[] = {
 509                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 510                 1000000, 1350000,
 511         };
 512         static const int bxt_rates[] = {
 513                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 514         };
 515         static const int skl_rates[] = {
 516                 162000, 216000, 270000, 324000, 432000, 540000
 517         };
 518         static const int hsw_rates[] = {
 519                 162000, 270000, 540000
 520         };
 521         static const int g4x_rates[] = {
 522                 162000, 270000
 523         };
 524         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 525         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 526         const int *source_rates;
 527         int size, max_rate = 0, vbt_max_rate;
 528
 529         /* This should only be done once */
 530         drm_WARN_ON(&dev_priv->drm,
 531                     intel_dp->source_rates || intel_dp->num_source_rates);
 532
 533         if (DISPLAY_VER(dev_priv) >= 14) {
 534                 source_rates = mtl_rates;
 535                 size = ARRAY_SIZE(mtl_rates);
 536                 max_rate = mtl_max_source_rate(intel_dp);
 537         } else if (DISPLAY_VER(dev_priv) >= 11) {
 538                 source_rates = icl_rates;
 539                 size = ARRAY_SIZE(icl_rates);
 540                 if (IS_DG2(dev_priv))
 541                         max_rate = dg2_max_source_rate(intel_dp);
 542                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 543                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 544                         max_rate = 810000;
 545                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 546                         max_rate = ehl_max_source_rate(intel_dp);
 547                 else
 548                         max_rate = icl_max_source_rate(intel_dp);
 549         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 550                 source_rates = bxt_rates;
 551                 size = ARRAY_SIZE(bxt_rates);
 552         } else if (DISPLAY_VER(dev_priv) == 9) {
 553                 source_rates = skl_rates;
 554                 size = ARRAY_SIZE(skl_rates);
 555         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 556                    IS_BROADWELL(dev_priv)) {
 557                 source_rates = hsw_rates;
 558                 size = ARRAY_SIZE(hsw_rates);
 559         } else {
 560                 source_rates = g4x_rates;
 561                 size = ARRAY_SIZE(g4x_rates);
 562         }
 563
 564         vbt_max_rate = vbt_max_link_rate(intel_dp);
 565         if (max_rate && vbt_max_rate)
 566                 max_rate = min(max_rate, vbt_max_rate);
 567         else if (vbt_max_rate)
 568                 max_rate = vbt_max_rate;
 569
 570         if (max_rate)
 571                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 572
 573         intel_dp->source_rates = source_rates;
 574         intel_dp->num_source_rates = size;
 575 }
 576
 577 static int intersect_rates(const int *source_rates, int source_len,
 578                            const int *sink_rates, int sink_len,
 579                            int *common_rates)
 580 {
 581         int i = 0, j = 0, k = 0;
 582
 583         while (i < source_len && j < sink_len) {
 584                 if (source_rates[i] == sink_rates[j]) {
 585                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 586                                 return k;
 587                         common_rates[k] = source_rates[i];
 588                         ++k;
 589                         ++i;
 590                         ++j;
 591                 } else if (source_rates[i] < sink_rates[j]) {
 592                         ++i;
 593                 } else {
 594                         ++j;
 595                 }
 596         }
 597         return k;
 598 }
 599
 600 /* return index of rate in rates array, or -1 if not found */
 601 static int intel_dp_rate_index(const int *rates, int len, int rate)
 602 {
 603         int i;
 604
 605         for (i = 0; i < len; i++)
 606                 if (rate == rates[i])
 607                         return i;
 608
 609         return -1;
 610 }
 611
 612 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 613 {
 614         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 615
 616         drm_WARN_ON(&i915->drm,
 617                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 618
 619         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 620                                                      intel_dp->num_source_rates,
 621                                                      intel_dp->sink_rates,
 622                                                      intel_dp->num_sink_rates,
 623                                                      intel_dp->common_rates);
 624
 625         /* Paranoia, there should always be something in common. */
 626         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 627                 intel_dp->common_rates[0] = 162000;
 628                 intel_dp->num_common_rates = 1;
 629         }
 630 }
 631
 632 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 633                                        u8 lane_count)
 634 {
 635         /*
 636          * FIXME: we need to synchronize the current link parameters with
 637          * hardware readout. Currently fast link training doesn't work on
 638          * boot-up.
 639          */
 640         if (link_rate == 0 ||
 641             link_rate > intel_dp->max_link_rate)
 642                 return false;
 643
 644         if (lane_count == 0 ||
 645             lane_count > intel_dp_max_lane_count(intel_dp))
 646                 return false;
 647
 648         return true;
 649 }
 650
 651 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 652                                                      int link_rate,
 653                                                      u8 lane_count)
 654 {
 655         /* FIXME figure out what we actually want here */
 656         const struct drm_display_mode *fixed_mode =
 657                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 658         int mode_rate, max_rate;
 659
 660         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 661         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 662         if (mode_rate > max_rate)
 663                 return false;
 664
 665         return true;
 666 }
 667
 668 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 669                                             int link_rate, u8 lane_count)
 670 {
 671         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 672         int index;
 673
 674         /*
 675          * TODO: Enable fallback on MST links once MST link compute can handle
 676          * the fallback params.
 677          */
 678         if (intel_dp->is_mst) {
 679                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 680                 return -1;
 681         }
 682
 683         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 684                 drm_dbg_kms(&i915->drm,
 685                             "Retrying Link training for eDP with max parameters\n");
 686                 intel_dp->use_max_params = true;
 687                 return 0;
 688         }
 689
 690         index = intel_dp_rate_index(intel_dp->common_rates,
 691                                     intel_dp->num_common_rates,
 692                                     link_rate);
 693         if (index > 0) {
 694                 if (intel_dp_is_edp(intel_dp) &&
 695                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 696                                                               intel_dp_common_rate(intel_dp, index - 1),
 697                                                               lane_count)) {
 698                         drm_dbg_kms(&i915->drm,
 699                                     "Retrying Link training for eDP with same parameters\n");
 700                         return 0;
 701                 }
 702                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 703                 intel_dp->max_link_lane_count = lane_count;
 704         } else if (lane_count > 1) {
 705                 if (intel_dp_is_edp(intel_dp) &&
 706                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 707                                                               intel_dp_max_common_rate(intel_dp),
 708                                                               lane_count >> 1)) {
 709                         drm_dbg_kms(&i915->drm,
 710                                     "Retrying Link training for eDP with same parameters\n");
 711                         return 0;
 712                 }
 713                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 714                 intel_dp->max_link_lane_count = lane_count >> 1;
 715         } else {
 716                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 717                 return -1;
 718         }
 719
 720         return 0;
 721 }
 722
 723 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 724 {
 725         return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
 726                        1000000U);
 727 }
 728
 729 int intel_dp_bw_fec_overhead(bool fec_enabled)
 730 {
 731         /*
 732          * TODO: Calculate the actual overhead for a given mode.
 733          * The hard-coded 1/0.972261=2.853% overhead factor
 734          * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
 735          * 0.453% DSC overhead. This is enough for a 3840 width mode,
 736          * which has a DSC overhead of up to ~0.2%, but may not be
 737          * enough for a 1024 width mode where this is ~0.8% (on a 4
 738          * lane DP link, with 2 DSC slices and 8 bpp color depth).
 739          */
 740         return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
 741 }
 742
 743 static int
 744 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 745 {
 746         if (DISPLAY_VER(i915) >= 13)
 747                 return 17280 * 8;
 748         else if (DISPLAY_VER(i915) >= 11)
 749                 return 7680 * 8;
 750         else
 751                 return 6144 * 8;
 752 }
 753
 754 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 755 {
 756         u32 bits_per_pixel = bpp;
 757         int i;
 758
 759         /* Error out if the max bpp is less than smallest allowed valid bpp */
 760         if (bits_per_pixel < valid_dsc_bpp[0]) {
 761                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 762                             bits_per_pixel, valid_dsc_bpp[0]);
 763                 return 0;
 764         }
 765
 766         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 767         if (DISPLAY_VER(i915) >= 13) {
 768                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 769
 770                 /*
 771                  * According to BSpec, 27 is the max DSC output bpp,
 772                  * 8 is the min DSC output bpp.
 773                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 774                  * if it is required to oompress up to bpp < 8, means we can't do
 775                  * that and probably means we can't fit the required mode, even with
 776                  * DSC enabled.
 777                  */
 778                 if (bits_per_pixel < 8) {
 779                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 780                                     bits_per_pixel);
 781                         return 0;
 782                 }
 783                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 784         } else {
 785                 /* Find the nearest match in the array of known BPPs from VESA */
 786                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 787                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 788                                 break;
 789                 }
 790                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 791                             bits_per_pixel, valid_dsc_bpp[i]);
 792
 793                 bits_per_pixel = valid_dsc_bpp[i];
 794         }
 795
 796         return bits_per_pixel;
 797 }
 798
 799 static
 800 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 801                                        u32 mode_clock, u32 mode_hdisplay,
 802                                        bool bigjoiner)
 803 {
 804         u32 max_bpp_small_joiner_ram;
 805
 806         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 807         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 808
 809         if (bigjoiner) {
 810                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
 811                 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 812                 int ppc = 2;
 813                 u32 max_bpp_bigjoiner =
 814                         i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
 815                         intel_dp_mode_to_fec_clock(mode_clock);
 816
 817                 max_bpp_small_joiner_ram *= 2;
 818
 819                 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
 820         }
 821
 822         return max_bpp_small_joiner_ram;
 823 }
 824
 825 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 826                                         u32 link_clock, u32 lane_count,
 827                                         u32 mode_clock, u32 mode_hdisplay,
 828                                         bool bigjoiner,
 829                                         enum intel_output_format output_format,
 830                                         u32 pipe_bpp,
 831                                         u32 timeslots)
 832 {
 833         u32 bits_per_pixel, joiner_max_bpp;
 834
 835         /*
 836          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 837          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 838          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 839          * for MST -> TimeSlots has to be calculated, based on mode requirements
 840          *
 841          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 842          * To support the given mode:
 843          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 844          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 845          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 846          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 847          *                     (ModeClock / FEC Overhead)
 848          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 849          *                     (ModeClock / FEC Overhead * 8)
 850          */
 851         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 852                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 853
 854         /* Bandwidth required for 420 is half, that of 444 format */
 855         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 856                 bits_per_pixel *= 2;
 857
 858         /*
 859          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 860          * supported PPS value can be 63.9375 and with the further
 861          * mention that for 420, 422 formats, bpp should be programmed double
 862          * the target bpp restricting our target bpp to be 31.9375 at max.
 863          */
 864         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 865                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 866
 867         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 868                                 "total bw %u pixel clock %u\n",
 869                                 bits_per_pixel, timeslots,
 870                                 (link_clock * lane_count * 8),
 871                                 intel_dp_mode_to_fec_clock(mode_clock));
 872
 873         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 874                                                             mode_hdisplay, bigjoiner);
 875         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 876
 877         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 878
 879         return bits_per_pixel;
 880 }
 881
 882 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 883                                 int mode_clock, int mode_hdisplay,
 884                                 bool bigjoiner)
 885 {
 886         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 887         u8 min_slice_count, i;
 888         int max_slice_width;
 889
 890         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 891                 min_slice_count = DIV_ROUND_UP(mode_clock,
 892                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 893         else
 894                 min_slice_count = DIV_ROUND_UP(mode_clock,
 895                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 896
 897         /*
 898          * Due to some DSC engine BW limitations, we need to enable second
 899          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 900          */
 901         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 902                 min_slice_count = max_t(u8, min_slice_count, 2);
 903
 904         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
 905         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 906                 drm_dbg_kms(&i915->drm,
 907                             "Unsupported slice width %d by DP DSC Sink device\n",
 908                             max_slice_width);
 909                 return 0;
 910         }
 911         /* Also take into account max slice width */
 912         min_slice_count = max_t(u8, min_slice_count,
 913                                 DIV_ROUND_UP(mode_hdisplay,
 914                                              max_slice_width));
 915
 916         /* Find the closest match to the valid slice count values */
 917         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 918                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 919
 920                 if (test_slice_count >
 921                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 922                         break;
 923
 924                 /* big joiner needs small joiner to be enabled */
 925                 if (bigjoiner && test_slice_count < 4)
 926                         continue;
 927
 928                 if (min_slice_count <= test_slice_count)
 929                         return test_slice_count;
 930         }
 931
 932         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 933                     min_slice_count);
 934         return 0;
 935 }
 936
 937 static bool source_can_output(struct intel_dp *intel_dp,
 938                               enum intel_output_format format)
 939 {
 940         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 941
 942         switch (format) {
 943         case INTEL_OUTPUT_FORMAT_RGB:
 944                 return true;
 945
 946         case INTEL_OUTPUT_FORMAT_YCBCR444:
 947                 /*
 948                  * No YCbCr output support on gmch platforms.
 949                  * Also, ILK doesn't seem capable of DP YCbCr output.
 950                  * The displayed image is severly corrupted. SNB+ is fine.
 951                  */
 952                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 953
 954         case INTEL_OUTPUT_FORMAT_YCBCR420:
 955                 /* Platform < Gen 11 cannot output YCbCr420 format */
 956                 return DISPLAY_VER(i915) >= 11;
 957
 958         default:
 959                 MISSING_CASE(format);
 960                 return false;
 961         }
 962 }
 963
 964 static bool
 965 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 966                          enum intel_output_format sink_format)
 967 {
 968         if (!drm_dp_is_branch(intel_dp->dpcd))
 969                 return false;
 970
 971         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 972                 return intel_dp->dfp.rgb_to_ycbcr;
 973
 974         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 975                 return intel_dp->dfp.rgb_to_ycbcr &&
 976                         intel_dp->dfp.ycbcr_444_to_420;
 977
 978         return false;
 979 }
 980
 981 static bool
 982 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 983                               enum intel_output_format sink_format)
 984 {
 985         if (!drm_dp_is_branch(intel_dp->dpcd))
 986                 return false;
 987
 988         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 989                 return intel_dp->dfp.ycbcr_444_to_420;
 990
 991         return false;
 992 }
 993
 994 static bool
 995 dfp_can_convert(struct intel_dp *intel_dp,
 996                 enum intel_output_format output_format,
 997                 enum intel_output_format sink_format)
 998 {
 999         switch (output_format) {
1000         case INTEL_OUTPUT_FORMAT_RGB:
1001                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1002         case INTEL_OUTPUT_FORMAT_YCBCR444:
1003                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1004         default:
1005                 MISSING_CASE(output_format);
1006                 return false;
1007         }
1008
1009         return false;
1010 }
1011
1012 static enum intel_output_format
1013 intel_dp_output_format(struct intel_connector *connector,
1014                        enum intel_output_format sink_format)
1015 {
1016         struct intel_dp *intel_dp = intel_attached_dp(connector);
1017         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1018         enum intel_output_format force_dsc_output_format =
1019                 intel_dp->force_dsc_output_format;
1020         enum intel_output_format output_format;
1021         if (force_dsc_output_format) {
1022                 if (source_can_output(intel_dp, force_dsc_output_format) &&
1023                     (!drm_dp_is_branch(intel_dp->dpcd) ||
1024                      sink_format != force_dsc_output_format ||
1025                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1026                         return force_dsc_output_format;
1027
1028                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1029         }
1030
1031         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1032             dfp_can_convert_from_rgb(intel_dp, sink_format))
1033                 output_format = INTEL_OUTPUT_FORMAT_RGB;
1034
1035         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1036                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1037                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1038
1039         else
1040                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1041
1042         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1043
1044         return output_format;
1045 }
1046
1047 int intel_dp_min_bpp(enum intel_output_format output_format)
1048 {
1049         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1050                 return 6 * 3;
1051         else
1052                 return 8 * 3;
1053 }
1054
1055 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1056 {
1057         /*
1058          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1059          * format of the number of bytes per pixel will be half the number
1060          * of bytes of RGB pixel.
1061          */
1062         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1063                 bpp /= 2;
1064
1065         return bpp;
1066 }
1067
1068 static enum intel_output_format
1069 intel_dp_sink_format(struct intel_connector *connector,
1070                      const struct drm_display_mode *mode)
1071 {
1072         const struct drm_display_info *info = &connector->base.display_info;
1073
1074         if (drm_mode_is_420_only(info, mode))
1075                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1076
1077         return INTEL_OUTPUT_FORMAT_RGB;
1078 }
1079
1080 static int
1081 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1082                              const struct drm_display_mode *mode)
1083 {
1084         enum intel_output_format output_format, sink_format;
1085
1086         sink_format = intel_dp_sink_format(connector, mode);
1087
1088         output_format = intel_dp_output_format(connector, sink_format);
1089
1090         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1091 }
1092
1093 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1094                                   int hdisplay)
1095 {
1096         /*
1097          * Older platforms don't like hdisplay==4096 with DP.
1098          *
1099          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1100          * and frame counter increment), but we don't get vblank interrupts,
1101          * and the pipe underruns immediately. The link also doesn't seem
1102          * to get trained properly.
1103          *
1104          * On CHV the vblank interrupts don't seem to disappear but
1105          * otherwise the symptoms are similar.
1106          *
1107          * TODO: confirm the behaviour on HSW+
1108          */
1109         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1110 }
1111
1112 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1113 {
1114         struct intel_connector *connector = intel_dp->attached_connector;
1115         const struct drm_display_info *info = &connector->base.display_info;
1116         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1117
1118         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1119         if (max_tmds_clock && info->max_tmds_clock)
1120                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1121
1122         return max_tmds_clock;
1123 }
1124
1125 static enum drm_mode_status
1126 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1127                           int clock, int bpc,
1128                           enum intel_output_format sink_format,
1129                           bool respect_downstream_limits)
1130 {
1131         int tmds_clock, min_tmds_clock, max_tmds_clock;
1132
1133         if (!respect_downstream_limits)
1134                 return MODE_OK;
1135
1136         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1137
1138         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1139         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1140
1141         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1142                 return MODE_CLOCK_LOW;
1143
1144         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1145                 return MODE_CLOCK_HIGH;
1146
1147         return MODE_OK;
1148 }
1149
1150 static enum drm_mode_status
1151 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1152                                const struct drm_display_mode *mode,
1153                                int target_clock)
1154 {
1155         struct intel_dp *intel_dp = intel_attached_dp(connector);
1156         const struct drm_display_info *info = &connector->base.display_info;
1157         enum drm_mode_status status;
1158         enum intel_output_format sink_format;
1159
1160         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1161         if (intel_dp->dfp.pcon_max_frl_bw) {
1162                 int target_bw;
1163                 int max_frl_bw;
1164                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1165
1166                 target_bw = bpp * target_clock;
1167
1168                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1169
1170                 /* converting bw from Gbps to Kbps*/
1171                 max_frl_bw = max_frl_bw * 1000000;
1172
1173                 if (target_bw > max_frl_bw)
1174                         return MODE_CLOCK_HIGH;
1175
1176                 return MODE_OK;
1177         }
1178
1179         if (intel_dp->dfp.max_dotclock &&
1180             target_clock > intel_dp->dfp.max_dotclock)
1181                 return MODE_CLOCK_HIGH;
1182
1183         sink_format = intel_dp_sink_format(connector, mode);
1184
1185         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1186         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1187                                            8, sink_format, true);
1188
1189         if (status != MODE_OK) {
1190                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1191                     !connector->base.ycbcr_420_allowed ||
1192                     !drm_mode_is_420_also(info, mode))
1193                         return status;
1194                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1195                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1196                                                    8, sink_format, true);
1197                 if (status != MODE_OK)
1198                         return status;
1199         }
1200
1201         return MODE_OK;
1202 }
1203
1204 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1205                              int hdisplay, int clock)
1206 {
1207         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1208
1209         if (!intel_dp_can_bigjoiner(intel_dp))
1210                 return false;
1211
1212         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1213 }
1214
1215 static enum drm_mode_status
1216 intel_dp_mode_valid(struct drm_connector *_connector,
1217                     struct drm_display_mode *mode)
1218 {
1219         struct intel_connector *connector = to_intel_connector(_connector);
1220         struct intel_dp *intel_dp = intel_attached_dp(connector);
1221         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1222         const struct drm_display_mode *fixed_mode;
1223         int target_clock = mode->clock;
1224         int max_rate, mode_rate, max_lanes, max_link_clock;
1225         int max_dotclk = dev_priv->max_dotclk_freq;
1226         u16 dsc_max_compressed_bpp = 0;
1227         u8 dsc_slice_count = 0;
1228         enum drm_mode_status status;
1229         bool dsc = false, bigjoiner = false;
1230
1231         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1232         if (status != MODE_OK)
1233                 return status;
1234
1235         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1236                 return MODE_H_ILLEGAL;
1237
1238         fixed_mode = intel_panel_fixed_mode(connector, mode);
1239         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1240                 status = intel_panel_mode_valid(connector, mode);
1241                 if (status != MODE_OK)
1242                         return status;
1243
1244                 target_clock = fixed_mode->clock;
1245         }
1246
1247         if (mode->clock < 10000)
1248                 return MODE_CLOCK_LOW;
1249
1250         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1251                 bigjoiner = true;
1252                 max_dotclk *= 2;
1253         }
1254         if (target_clock > max_dotclk)
1255                 return MODE_CLOCK_HIGH;
1256
1257         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1258                 return MODE_H_ILLEGAL;
1259
1260         max_link_clock = intel_dp_max_link_rate(intel_dp);
1261         max_lanes = intel_dp_max_lane_count(intel_dp);
1262
1263         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1264         mode_rate = intel_dp_link_required(target_clock,
1265                                            intel_dp_mode_min_output_bpp(connector, mode));
1266
1267         if (HAS_DSC(dev_priv) &&
1268             drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1269                 enum intel_output_format sink_format, output_format;
1270                 int pipe_bpp;
1271
1272                 sink_format = intel_dp_sink_format(connector, mode);
1273                 output_format = intel_dp_output_format(connector, sink_format);
1274                 /*
1275                  * TBD pass the connector BPC,
1276                  * for now U8_MAX so that max BPC on that platform would be picked
1277                  */
1278                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1279
1280                 /*
1281                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1282                  * integer value since we support only integer values of bpp.
1283                  */
1284                 if (intel_dp_is_edp(intel_dp)) {
1285                         dsc_max_compressed_bpp =
1286                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1287                         dsc_slice_count =
1288                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1289                                                                 true);
1290                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1291                         dsc_max_compressed_bpp =
1292                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1293                                                                     max_link_clock,
1294                                                                     max_lanes,
1295                                                                     target_clock,
1296                                                                     mode->hdisplay,
1297                                                                     bigjoiner,
1298                                                                     output_format,
1299                                                                     pipe_bpp, 64);
1300                         dsc_slice_count =
1301                                 intel_dp_dsc_get_slice_count(connector,
1302                                                              target_clock,
1303                                                              mode->hdisplay,
1304                                                              bigjoiner);
1305                 }
1306
1307                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1308         }
1309
1310         /*
1311          * Big joiner configuration needs DSC for TGL which is not true for
1312          * XE_LPD where uncompressed joiner is supported.
1313          */
1314         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1315                 return MODE_CLOCK_HIGH;
1316
1317         if (mode_rate > max_rate && !dsc)
1318                 return MODE_CLOCK_HIGH;
1319
1320         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1321         if (status != MODE_OK)
1322                 return status;
1323
1324         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1325 }
1326
1327 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1328 {
1329         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1330 }
1331
1332 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1333 {
1334         return DISPLAY_VER(i915) >= 10;
1335 }
1336
1337 static void snprintf_int_array(char *str, size_t len,
1338                                const int *array, int nelem)
1339 {
1340         int i;
1341
1342         str[0] = '\0';
1343
1344         for (i = 0; i < nelem; i++) {
1345                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1346                 if (r >= len)
1347                         return;
1348                 str += r;
1349                 len -= r;
1350         }
1351 }
1352
1353 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1354 {
1355         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1356         char str[128]; /* FIXME: too big for stack? */
1357
1358         if (!drm_debug_enabled(DRM_UT_KMS))
1359                 return;
1360
1361         snprintf_int_array(str, sizeof(str),
1362                            intel_dp->source_rates, intel_dp->num_source_rates);
1363         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1364
1365         snprintf_int_array(str, sizeof(str),
1366                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1367         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1368
1369         snprintf_int_array(str, sizeof(str),
1370                            intel_dp->common_rates, intel_dp->num_common_rates);
1371         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1372 }
1373
1374 int
1375 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1376 {
1377         int len;
1378
1379         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1380
1381         return intel_dp_common_rate(intel_dp, len - 1);
1382 }
1383
1384 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1385 {
1386         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1387         int i = intel_dp_rate_index(intel_dp->sink_rates,
1388                                     intel_dp->num_sink_rates, rate);
1389
1390         if (drm_WARN_ON(&i915->drm, i < 0))
1391                 i = 0;
1392
1393         return i;
1394 }
1395
1396 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1397                            u8 *link_bw, u8 *rate_select)
1398 {
1399         /* eDP 1.4 rate select method. */
1400         if (intel_dp->use_rate_select) {
1401                 *link_bw = 0;
1402                 *rate_select =
1403                         intel_dp_rate_select(intel_dp, port_clock);
1404         } else {
1405                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1406                 *rate_select = 0;
1407         }
1408 }
1409
1410 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1411 {
1412         struct intel_connector *connector = intel_dp->attached_connector;
1413
1414         return connector->base.display_info.is_hdmi;
1415 }
1416
1417 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1418                                          const struct intel_crtc_state *pipe_config)
1419 {
1420         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1421         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1422
1423         if (DISPLAY_VER(dev_priv) >= 12)
1424                 return true;
1425
1426         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1427                 return true;
1428
1429         return false;
1430 }
1431
1432 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1433                            const struct intel_connector *connector,
1434                            const struct intel_crtc_state *pipe_config)
1435 {
1436         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1437                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1438 }
1439
1440 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1441                                   const struct intel_crtc_state *crtc_state)
1442 {
1443         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1444                 return false;
1445
1446         return intel_dsc_source_support(crtc_state) &&
1447                 connector->dp.dsc_decompression_aux &&
1448                 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1449 }
1450
1451 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1452                                      const struct intel_crtc_state *crtc_state,
1453                                      int bpc, bool respect_downstream_limits)
1454 {
1455         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1456
1457         /*
1458          * Current bpc could already be below 8bpc due to
1459          * FDI bandwidth constraints or other limits.
1460          * HDMI minimum is 8bpc however.
1461          */
1462         bpc = max(bpc, 8);
1463
1464         /*
1465          * We will never exceed downstream TMDS clock limits while
1466          * attempting deep color. If the user insists on forcing an
1467          * out of spec mode they will have to be satisfied with 8bpc.
1468          */
1469         if (!respect_downstream_limits)
1470                 bpc = 8;
1471
1472         for (; bpc >= 8; bpc -= 2) {
1473                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1474                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1475                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1476                                               respect_downstream_limits) == MODE_OK)
1477                         return bpc;
1478         }
1479
1480         return -EINVAL;
1481 }
1482
1483 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1484                             const struct intel_crtc_state *crtc_state,
1485                             bool respect_downstream_limits)
1486 {
1487         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1488         struct intel_connector *intel_connector = intel_dp->attached_connector;
1489         int bpp, bpc;
1490
1491         bpc = crtc_state->pipe_bpp / 3;
1492
1493         if (intel_dp->dfp.max_bpc)
1494                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1495
1496         if (intel_dp->dfp.min_tmds_clock) {
1497                 int max_hdmi_bpc;
1498
1499                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1500                                                          respect_downstream_limits);
1501                 if (max_hdmi_bpc < 0)
1502                         return 0;
1503
1504                 bpc = min(bpc, max_hdmi_bpc);
1505         }
1506
1507         bpp = bpc * 3;
1508         if (intel_dp_is_edp(intel_dp)) {
1509                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1510                 if (intel_connector->base.display_info.bpc == 0 &&
1511                     intel_connector->panel.vbt.edp.bpp &&
1512                     intel_connector->panel.vbt.edp.bpp < bpp) {
1513                         drm_dbg_kms(&dev_priv->drm,
1514                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1515                                     intel_connector->panel.vbt.edp.bpp);
1516                         bpp = intel_connector->panel.vbt.edp.bpp;
1517                 }
1518         }
1519
1520         return bpp;
1521 }
1522
1523 /* Adjust link config limits based on compliance test requests. */
1524 void
1525 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1526                                   struct intel_crtc_state *pipe_config,
1527                                   struct link_config_limits *limits)
1528 {
1529         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1530
1531         /* For DP Compliance we override the computed bpp for the pipe */
1532         if (intel_dp->compliance.test_data.bpc != 0) {
1533                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1534
1535                 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1536                 pipe_config->dither_force_disable = bpp == 6 * 3;
1537
1538                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1539         }
1540
1541         /* Use values requested by Compliance Test Request */
1542         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1543                 int index;
1544
1545                 /* Validate the compliance test data since max values
1546                  * might have changed due to link train fallback.
1547                  */
1548                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1549                                                intel_dp->compliance.test_lane_count)) {
1550                         index = intel_dp_rate_index(intel_dp->common_rates,
1551                                                     intel_dp->num_common_rates,
1552                                                     intel_dp->compliance.test_link_rate);
1553                         if (index >= 0)
1554                                 limits->min_rate = limits->max_rate =
1555                                         intel_dp->compliance.test_link_rate;
1556                         limits->min_lane_count = limits->max_lane_count =
1557                                 intel_dp->compliance.test_lane_count;
1558                 }
1559         }
1560 }
1561
1562 static bool has_seamless_m_n(struct intel_connector *connector)
1563 {
1564         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1565
1566         /*
1567          * Seamless M/N reprogramming only implemented
1568          * for BDW+ double buffered M/N registers so far.
1569          */
1570         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1571                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1572 }
1573
1574 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1575                                const struct drm_connector_state *conn_state)
1576 {
1577         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1578         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1579
1580         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1581         if (has_seamless_m_n(connector))
1582                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1583         else
1584                 return adjusted_mode->crtc_clock;
1585 }
1586
1587 /* Optimize link config in order: max bpp, min clock, min lanes */
1588 static int
1589 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1590                                   struct intel_crtc_state *pipe_config,
1591                                   const struct drm_connector_state *conn_state,
1592                                   const struct link_config_limits *limits)
1593 {
1594         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1595         int mode_rate, link_rate, link_avail;
1596
1597         for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1598              bpp >= to_bpp_int(limits->link.min_bpp_x16);
1599              bpp -= 2 * 3) {
1600                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1601
1602                 mode_rate = intel_dp_link_required(clock, link_bpp);
1603
1604                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1605                         link_rate = intel_dp_common_rate(intel_dp, i);
1606                         if (link_rate < limits->min_rate ||
1607                             link_rate > limits->max_rate)
1608                                 continue;
1609
1610                         for (lane_count = limits->min_lane_count;
1611                              lane_count <= limits->max_lane_count;
1612                              lane_count <<= 1) {
1613                                 link_avail = intel_dp_max_data_rate(link_rate,
1614                                                                     lane_count);
1615
1616                                 if (mode_rate <= link_avail) {
1617                                         pipe_config->lane_count = lane_count;
1618                                         pipe_config->pipe_bpp = bpp;
1619                                         pipe_config->port_clock = link_rate;
1620
1621                                         return 0;
1622                                 }
1623                         }
1624                 }
1625         }
1626
1627         return -EINVAL;
1628 }
1629
1630 static
1631 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1632 {
1633         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1634         if (DISPLAY_VER(i915) >= 12)
1635                 return 12;
1636         if (DISPLAY_VER(i915) == 11)
1637                 return 10;
1638
1639         return 0;
1640 }
1641
1642 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1643                                  u8 max_req_bpc)
1644 {
1645         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1646         int i, num_bpc;
1647         u8 dsc_bpc[3] = {};
1648         u8 dsc_max_bpc;
1649
1650         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1651
1652         if (!dsc_max_bpc)
1653                 return dsc_max_bpc;
1654
1655         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1656
1657         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1658                                                        dsc_bpc);
1659         for (i = 0; i < num_bpc; i++) {
1660                 if (dsc_max_bpc >= dsc_bpc[i])
1661                         return dsc_bpc[i] * 3;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1668 {
1669         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1670 }
1671
1672 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1673 {
1674         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1675                 DP_DSC_MINOR_SHIFT;
1676 }
1677
1678 static int intel_dp_get_slice_height(int vactive)
1679 {
1680         int slice_height;
1681
1682         /*
1683          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1684          * lines is an optimal slice height, but any size can be used as long as
1685          * vertical active integer multiple and maximum vertical slice count
1686          * requirements are met.
1687          */
1688         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1689                 if (vactive % slice_height == 0)
1690                         return slice_height;
1691
1692         /*
1693          * Highly unlikely we reach here as most of the resolutions will end up
1694          * finding appropriate slice_height in above loop but returning
1695          * slice_height as 2 here as it should work with all resolutions.
1696          */
1697         return 2;
1698 }
1699
1700 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1701                                        struct intel_crtc_state *crtc_state)
1702 {
1703         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1704         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1705         u8 line_buf_depth;
1706         int ret;
1707
1708         /*
1709          * RC_MODEL_SIZE is currently a constant across all configurations.
1710          *
1711          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1712          * DP_DSC_RC_BUF_SIZE for this.
1713          */
1714         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1715         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1716
1717         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1718
1719         ret = intel_dsc_compute_params(crtc_state);
1720         if (ret)
1721                 return ret;
1722
1723         vdsc_cfg->dsc_version_major =
1724                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1725                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1726         vdsc_cfg->dsc_version_minor =
1727                 min(intel_dp_source_dsc_version_minor(i915),
1728                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1729         if (vdsc_cfg->convert_rgb)
1730                 vdsc_cfg->convert_rgb =
1731                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1732                         DP_DSC_RGB;
1733
1734         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1735         if (!line_buf_depth) {
1736                 drm_dbg_kms(&i915->drm,
1737                             "DSC Sink Line Buffer Depth invalid\n");
1738                 return -EINVAL;
1739         }
1740
1741         if (vdsc_cfg->dsc_version_minor == 2)
1742                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1743                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1744         else
1745                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1746                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1747
1748         vdsc_cfg->block_pred_enable =
1749                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1750                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1751
1752         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1753 }
1754
1755 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1756                                          enum intel_output_format output_format)
1757 {
1758         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1759         u8 sink_dsc_format;
1760
1761         switch (output_format) {
1762         case INTEL_OUTPUT_FORMAT_RGB:
1763                 sink_dsc_format = DP_DSC_RGB;
1764                 break;
1765         case INTEL_OUTPUT_FORMAT_YCBCR444:
1766                 sink_dsc_format = DP_DSC_YCbCr444;
1767                 break;
1768         case INTEL_OUTPUT_FORMAT_YCBCR420:
1769                 if (min(intel_dp_source_dsc_version_minor(i915),
1770                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1771                         return false;
1772                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1773                 break;
1774         default:
1775                 return false;
1776         }
1777
1778         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1779 }
1780
1781 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1782                                             u32 lane_count, u32 mode_clock,
1783                                             enum intel_output_format output_format,
1784                                             int timeslots)
1785 {
1786         u32 available_bw, required_bw;
1787
1788         available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
1789         required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1790
1791         return available_bw > required_bw;
1792 }
1793
1794 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1795                                    struct intel_crtc_state *pipe_config,
1796                                    struct link_config_limits *limits,
1797                                    u16 compressed_bppx16,
1798                                    int timeslots)
1799 {
1800         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1801         int link_rate, lane_count;
1802         int i;
1803
1804         for (i = 0; i < intel_dp->num_common_rates; i++) {
1805                 link_rate = intel_dp_common_rate(intel_dp, i);
1806                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1807                         continue;
1808
1809                 for (lane_count = limits->min_lane_count;
1810                      lane_count <= limits->max_lane_count;
1811                      lane_count <<= 1) {
1812                         if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1813                                                              lane_count, adjusted_mode->clock,
1814                                                              pipe_config->output_format,
1815                                                              timeslots))
1816                                 continue;
1817
1818                         pipe_config->lane_count = lane_count;
1819                         pipe_config->port_clock = link_rate;
1820
1821                         return 0;
1822                 }
1823         }
1824
1825         return -EINVAL;
1826 }
1827
1828 static
1829 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1830                                             struct intel_crtc_state *pipe_config,
1831                                             int bpc)
1832 {
1833         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1834
1835         if (max_bppx16)
1836                 return max_bppx16;
1837         /*
1838          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1839          * values as given in spec Table 2-157 DP v2.0
1840          */
1841         switch (pipe_config->output_format) {
1842         case INTEL_OUTPUT_FORMAT_RGB:
1843         case INTEL_OUTPUT_FORMAT_YCBCR444:
1844                 return (3 * bpc) << 4;
1845         case INTEL_OUTPUT_FORMAT_YCBCR420:
1846                 return (3 * (bpc / 2)) << 4;
1847         default:
1848                 MISSING_CASE(pipe_config->output_format);
1849                 break;
1850         }
1851
1852         return 0;
1853 }
1854
1855 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1856 {
1857         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1858         switch (pipe_config->output_format) {
1859         case INTEL_OUTPUT_FORMAT_RGB:
1860         case INTEL_OUTPUT_FORMAT_YCBCR444:
1861                 return 8;
1862         case INTEL_OUTPUT_FORMAT_YCBCR420:
1863                 return 6;
1864         default:
1865                 MISSING_CASE(pipe_config->output_format);
1866                 break;
1867         }
1868
1869         return 0;
1870 }
1871
1872 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1873                                          struct intel_crtc_state *pipe_config,
1874                                          int bpc)
1875 {
1876         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1877                                                        pipe_config, bpc) >> 4;
1878 }
1879
1880 static int dsc_src_min_compressed_bpp(void)
1881 {
1882         /* Min Compressed bpp supported by source is 8 */
1883         return 8;
1884 }
1885
1886 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1887 {
1888         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1889
1890         /*
1891          * Max Compressed bpp for Gen 13+ is 27bpp.
1892          * For earlier platform is 23bpp. (Bspec:49259).
1893          */
1894         if (DISPLAY_VER(i915) < 13)
1895                 return 23;
1896         else
1897                 return 27;
1898 }
1899
1900 /*
1901  * From a list of valid compressed bpps try different compressed bpp and find a
1902  * suitable link configuration that can support it.
1903  */
1904 static int
1905 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1906                             struct intel_crtc_state *pipe_config,
1907                             struct link_config_limits *limits,
1908                             int dsc_max_bpp,
1909                             int dsc_min_bpp,
1910                             int pipe_bpp,
1911                             int timeslots)
1912 {
1913         int i, ret;
1914
1915         /* Compressed BPP should be less than the Input DSC bpp */
1916         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1917
1918         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1919                 if (valid_dsc_bpp[i] < dsc_min_bpp ||
1920                     valid_dsc_bpp[i] > dsc_max_bpp)
1921                         break;
1922
1923                 ret = dsc_compute_link_config(intel_dp,
1924                                               pipe_config,
1925                                               limits,
1926                                               valid_dsc_bpp[i] << 4,
1927                                               timeslots);
1928                 if (ret == 0) {
1929                         pipe_config->dsc.compressed_bpp_x16 =
1930                                 to_bpp_x16(valid_dsc_bpp[i]);
1931                         return 0;
1932                 }
1933         }
1934
1935         return -EINVAL;
1936 }
1937
1938 /*
1939  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1940  * uncompressed bpp-1. So we start from max compressed bpp and see if any
1941  * link configuration is able to support that compressed bpp, if not we
1942  * step down and check for lower compressed bpp.
1943  */
1944 static int
1945 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1946                               const struct intel_connector *connector,
1947                               struct intel_crtc_state *pipe_config,
1948                               struct link_config_limits *limits,
1949                               int dsc_max_bpp,
1950                               int dsc_min_bpp,
1951                               int pipe_bpp,
1952                               int timeslots)
1953 {
1954         u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1955         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1956         u16 compressed_bppx16;
1957         u8 bppx16_step;
1958         int ret;
1959
1960         if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1961                 bppx16_step = 16;
1962         else
1963                 bppx16_step = 16 / bppx16_incr;
1964
1965         /* Compressed BPP should be less than the Input DSC bpp */
1966         dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1967         dsc_min_bpp = dsc_min_bpp << 4;
1968
1969         for (compressed_bppx16 = dsc_max_bpp;
1970              compressed_bppx16 >= dsc_min_bpp;
1971              compressed_bppx16 -= bppx16_step) {
1972                 if (intel_dp->force_dsc_fractional_bpp_en &&
1973                     !to_bpp_frac(compressed_bppx16))
1974                         continue;
1975                 ret = dsc_compute_link_config(intel_dp,
1976                                               pipe_config,
1977                                               limits,
1978                                               compressed_bppx16,
1979                                               timeslots);
1980                 if (ret == 0) {
1981                         pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1982                         if (intel_dp->force_dsc_fractional_bpp_en &&
1983                             to_bpp_frac(compressed_bppx16))
1984                                 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1985
1986                         return 0;
1987                 }
1988         }
1989         return -EINVAL;
1990 }
1991
1992 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1993                                       const struct intel_connector *connector,
1994                                       struct intel_crtc_state *pipe_config,
1995                                       struct link_config_limits *limits,
1996                                       int pipe_bpp,
1997                                       int timeslots)
1998 {
1999         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2000         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2001         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2002         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2003         int dsc_joiner_max_bpp;
2004
2005         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2006         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2007         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2008         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2009
2010         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2011         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2012                                                                 pipe_config,
2013                                                                 pipe_bpp / 3);
2014         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2015
2016         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2017                                                                 adjusted_mode->hdisplay,
2018                                                                 pipe_config->bigjoiner_pipes);
2019         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2020         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2021
2022         if (DISPLAY_VER(i915) >= 13)
2023                 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2024                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2025         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2026                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2027 }
2028
2029 static
2030 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2031 {
2032         /* Min DSC Input BPC for ICL+ is 8 */
2033         return HAS_DSC(i915) ? 8 : 0;
2034 }
2035
2036 static
2037 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2038                                 struct drm_connector_state *conn_state,
2039                                 struct link_config_limits *limits,
2040                                 int pipe_bpp)
2041 {
2042         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2043
2044         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2045         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2046
2047         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2048         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2049
2050         return pipe_bpp >= dsc_min_pipe_bpp &&
2051                pipe_bpp <= dsc_max_pipe_bpp;
2052 }
2053
2054 static
2055 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2056                                 struct drm_connector_state *conn_state,
2057                                 struct link_config_limits *limits)
2058 {
2059         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2060         int forced_bpp;
2061
2062         if (!intel_dp->force_dsc_bpc)
2063                 return 0;
2064
2065         forced_bpp = intel_dp->force_dsc_bpc * 3;
2066
2067         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2068                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2069                 return forced_bpp;
2070         }
2071
2072         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2073                     intel_dp->force_dsc_bpc);
2074
2075         return 0;
2076 }
2077
2078 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2079                                          struct intel_crtc_state *pipe_config,
2080                                          struct drm_connector_state *conn_state,
2081                                          struct link_config_limits *limits,
2082                                          int timeslots)
2083 {
2084         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2085         const struct intel_connector *connector =
2086                 to_intel_connector(conn_state->connector);
2087         u8 max_req_bpc = conn_state->max_requested_bpc;
2088         u8 dsc_max_bpc, dsc_max_bpp;
2089         u8 dsc_min_bpc, dsc_min_bpp;
2090         u8 dsc_bpc[3] = {};
2091         int forced_bpp, pipe_bpp;
2092         int num_bpc, i, ret;
2093
2094         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2095
2096         if (forced_bpp) {
2097                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2098                                                  limits, forced_bpp, timeslots);
2099                 if (ret == 0) {
2100                         pipe_config->pipe_bpp = forced_bpp;
2101                         return 0;
2102                 }
2103         }
2104
2105         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2106         if (!dsc_max_bpc)
2107                 return -EINVAL;
2108
2109         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2110         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2111
2112         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2113         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2114
2115         /*
2116          * Get the maximum DSC bpc that will be supported by any valid
2117          * link configuration and compressed bpp.
2118          */
2119         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2120         for (i = 0; i < num_bpc; i++) {
2121                 pipe_bpp = dsc_bpc[i] * 3;
2122                 if (pipe_bpp < dsc_min_bpp)
2123                         break;
2124                 if (pipe_bpp > dsc_max_bpp)
2125                         continue;
2126                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2127                                                  limits, pipe_bpp, timeslots);
2128                 if (ret == 0) {
2129                         pipe_config->pipe_bpp = pipe_bpp;
2130                         return 0;
2131                 }
2132         }
2133
2134         return -EINVAL;
2135 }
2136
2137 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2138                                           struct intel_crtc_state *pipe_config,
2139                                           struct drm_connector_state *conn_state,
2140                                           struct link_config_limits *limits)
2141 {
2142         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2143         struct intel_connector *connector =
2144                 to_intel_connector(conn_state->connector);
2145         int pipe_bpp, forced_bpp;
2146         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2147         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2148
2149         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2150
2151         if (forced_bpp) {
2152                 pipe_bpp = forced_bpp;
2153         } else {
2154                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2155
2156                 /* For eDP use max bpp that can be supported with DSC. */
2157                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2158                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2159                         drm_dbg_kms(&i915->drm,
2160                                     "Computed BPC is not in DSC BPC limits\n");
2161                         return -EINVAL;
2162                 }
2163         }
2164         pipe_config->port_clock = limits->max_rate;
2165         pipe_config->lane_count = limits->max_lane_count;
2166
2167         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2168         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2169         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2170         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2171
2172         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2173         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2174                                                                 pipe_config,
2175                                                                 pipe_bpp / 3);
2176         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2177         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2178
2179         /* Compressed BPP should be less than the Input DSC bpp */
2180         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2181
2182         pipe_config->dsc.compressed_bpp_x16 =
2183                 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2184
2185         pipe_config->pipe_bpp = pipe_bpp;
2186
2187         return 0;
2188 }
2189
2190 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2191                                 struct intel_crtc_state *pipe_config,
2192                                 struct drm_connector_state *conn_state,
2193                                 struct link_config_limits *limits,
2194                                 int timeslots,
2195                                 bool compute_pipe_bpp)
2196 {
2197         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2198         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2199         const struct intel_connector *connector =
2200                 to_intel_connector(conn_state->connector);
2201         const struct drm_display_mode *adjusted_mode =
2202                 &pipe_config->hw.adjusted_mode;
2203         int ret;
2204
2205         pipe_config->fec_enable = pipe_config->fec_enable ||
2206                 (!intel_dp_is_edp(intel_dp) &&
2207                  intel_dp_supports_fec(intel_dp, connector, pipe_config));
2208
2209         if (!intel_dp_supports_dsc(connector, pipe_config))
2210                 return -EINVAL;
2211
2212         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2213                 return -EINVAL;
2214
2215         /*
2216          * compute pipe bpp is set to false for DP MST DSC case
2217          * and compressed_bpp is calculated same time once
2218          * vpci timeslots are allocated, because overall bpp
2219          * calculation procedure is bit different for MST case.
2220          */
2221         if (compute_pipe_bpp) {
2222                 if (intel_dp_is_edp(intel_dp))
2223                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2224                                                              conn_state, limits);
2225                 else
2226                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2227                                                             conn_state, limits, timeslots);
2228                 if (ret) {
2229                         drm_dbg_kms(&dev_priv->drm,
2230                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2231                         return ret;
2232                 }
2233         }
2234
2235         /* Calculate Slice count */
2236         if (intel_dp_is_edp(intel_dp)) {
2237                 pipe_config->dsc.slice_count =
2238                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2239                                                         true);
2240                 if (!pipe_config->dsc.slice_count) {
2241                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2242                                     pipe_config->dsc.slice_count);
2243                         return -EINVAL;
2244                 }
2245         } else {
2246                 u8 dsc_dp_slice_count;
2247
2248                 dsc_dp_slice_count =
2249                         intel_dp_dsc_get_slice_count(connector,
2250                                                      adjusted_mode->crtc_clock,
2251                                                      adjusted_mode->crtc_hdisplay,
2252                                                      pipe_config->bigjoiner_pipes);
2253                 if (!dsc_dp_slice_count) {
2254                         drm_dbg_kms(&dev_priv->drm,
2255                                     "Compressed Slice Count not supported\n");
2256                         return -EINVAL;
2257                 }
2258
2259                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2260         }
2261         /*
2262          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2263          * is greater than the maximum Cdclock and if slice count is even
2264          * then we need to use 2 VDSC instances.
2265          */
2266         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2267                 pipe_config->dsc.dsc_split = true;
2268
2269         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2270         if (ret < 0) {
2271                 drm_dbg_kms(&dev_priv->drm,
2272                             "Cannot compute valid DSC parameters for Input Bpp = %d"
2273                             "Compressed BPP = " BPP_X16_FMT "\n",
2274                             pipe_config->pipe_bpp,
2275                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2276                 return ret;
2277         }
2278
2279         pipe_config->dsc.compression_enable = true;
2280         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2281                     "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2282                     pipe_config->pipe_bpp,
2283                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2284                     pipe_config->dsc.slice_count);
2285
2286         return 0;
2287 }
2288
2289 /**
2290  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2291  * @intel_dp: intel DP
2292  * @crtc_state: crtc state
2293  * @dsc: DSC compression mode
2294  * @limits: link configuration limits
2295  *
2296  * Calculates the output link min, max bpp values in @limits based on the
2297  * pipe bpp range, @crtc_state and @dsc mode.
2298  *
2299  * Returns %true in case of success.
2300  */
2301 bool
2302 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2303                                         const struct intel_crtc_state *crtc_state,
2304                                         bool dsc,
2305                                         struct link_config_limits *limits)
2306 {
2307         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2308         const struct drm_display_mode *adjusted_mode =
2309                 &crtc_state->hw.adjusted_mode;
2310         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2311         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2312         int max_link_bpp_x16;
2313
2314         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2315                                to_bpp_x16(limits->pipe.max_bpp));
2316
2317         if (!dsc) {
2318                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2319
2320                 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2321                         return false;
2322
2323                 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2324         } else {
2325                 /*
2326                  * TODO: set the DSC link limits already here, atm these are
2327                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2328                  * intel_dp_dsc_compute_pipe_bpp()
2329                  */
2330                 limits->link.min_bpp_x16 = 0;
2331         }
2332
2333         limits->link.max_bpp_x16 = max_link_bpp_x16;
2334
2335         drm_dbg_kms(&i915->drm,
2336                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2337                     encoder->base.base.id, encoder->base.name,
2338                     crtc->base.base.id, crtc->base.name,
2339                     adjusted_mode->crtc_clock,
2340                     dsc ? "on" : "off",
2341                     limits->max_lane_count,
2342                     limits->max_rate,
2343                     limits->pipe.max_bpp,
2344                     BPP_X16_ARGS(limits->link.max_bpp_x16));
2345
2346         return true;
2347 }
2348
2349 static bool
2350 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2351                                struct intel_crtc_state *crtc_state,
2352                                bool respect_downstream_limits,
2353                                bool dsc,
2354                                struct link_config_limits *limits)
2355 {
2356         limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2357         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2358
2359         limits->min_lane_count = 1;
2360         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2361
2362         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2363         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2364                                                      respect_downstream_limits);
2365
2366         if (intel_dp->use_max_params) {
2367                 /*
2368                  * Use the maximum clock and number of lanes the eDP panel
2369                  * advertizes being capable of in case the initial fast
2370                  * optimal params failed us. The panels are generally
2371                  * designed to support only a single clock and lane
2372                  * configuration, and typically on older panels these
2373                  * values correspond to the native resolution of the panel.
2374                  */
2375                 limits->min_lane_count = limits->max_lane_count;
2376                 limits->min_rate = limits->max_rate;
2377         }
2378
2379         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2380
2381         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2382                                                        crtc_state,
2383                                                        dsc,
2384                                                        limits);
2385 }
2386
2387 static int
2388 intel_dp_compute_link_config(struct intel_encoder *encoder,
2389                              struct intel_crtc_state *pipe_config,
2390                              struct drm_connector_state *conn_state,
2391                              bool respect_downstream_limits)
2392 {
2393         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2394         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2395         const struct intel_connector *connector =
2396                 to_intel_connector(conn_state->connector);
2397         const struct drm_display_mode *adjusted_mode =
2398                 &pipe_config->hw.adjusted_mode;
2399         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2400         struct link_config_limits limits;
2401         bool joiner_needs_dsc = false;
2402         bool dsc_needed;
2403         int ret = 0;
2404
2405         if (pipe_config->fec_enable &&
2406             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2407                 return -EINVAL;
2408
2409         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2410                                     adjusted_mode->crtc_clock))
2411                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2412
2413         /*
2414          * Pipe joiner needs compression up to display 12 due to bandwidth
2415          * limitation. DG2 onwards pipe joiner can be enabled without
2416          * compression.
2417          */
2418         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2419
2420         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2421                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2422                                                      respect_downstream_limits,
2423                                                      false,
2424                                                      &limits);
2425
2426         if (!dsc_needed) {
2427                 /*
2428                  * Optimize for slow and wide for everything, because there are some
2429                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2430                  */
2431                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2432                                                         conn_state, &limits);
2433                 if (ret)
2434                         dsc_needed = true;
2435         }
2436
2437         if (dsc_needed) {
2438                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2439                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2440                             str_yes_no(intel_dp->force_dsc_en));
2441
2442                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2443                                                     respect_downstream_limits,
2444                                                     true,
2445                                                     &limits))
2446                         return -EINVAL;
2447
2448                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2449                                                   conn_state, &limits, 64, true);
2450                 if (ret < 0)
2451                         return ret;
2452         }
2453
2454         if (pipe_config->dsc.compression_enable) {
2455                 drm_dbg_kms(&i915->drm,
2456                             "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
2457                             pipe_config->lane_count, pipe_config->port_clock,
2458                             pipe_config->pipe_bpp,
2459                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2460
2461                 drm_dbg_kms(&i915->drm,
2462                             "DP link rate required %i available %i\n",
2463                             intel_dp_link_required(adjusted_mode->crtc_clock,
2464                                                    to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
2465                             intel_dp_max_data_rate(pipe_config->port_clock,
2466                                                    pipe_config->lane_count));
2467         } else {
2468                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2469                             pipe_config->lane_count, pipe_config->port_clock,
2470                             pipe_config->pipe_bpp);
2471
2472                 drm_dbg_kms(&i915->drm,
2473                             "DP link rate required %i available %i\n",
2474                             intel_dp_link_required(adjusted_mode->crtc_clock,
2475                                                    pipe_config->pipe_bpp),
2476                             intel_dp_max_data_rate(pipe_config->port_clock,
2477                                                    pipe_config->lane_count));
2478         }
2479         return 0;
2480 }
2481
2482 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2483                                   const struct drm_connector_state *conn_state)
2484 {
2485         const struct intel_digital_connector_state *intel_conn_state =
2486                 to_intel_digital_connector_state(conn_state);
2487         const struct drm_display_mode *adjusted_mode =
2488                 &crtc_state->hw.adjusted_mode;
2489
2490         /*
2491          * Our YCbCr output is always limited range.
2492          * crtc_state->limited_color_range only applies to RGB,
2493          * and it must never be set for YCbCr or we risk setting
2494          * some conflicting bits in TRANSCONF which will mess up
2495          * the colors on the monitor.
2496          */
2497         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2498                 return false;
2499
2500         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2501                 /*
2502                  * See:
2503                  * CEA-861-E - 5.1 Default Encoding Parameters
2504                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2505                  */
2506                 return crtc_state->pipe_bpp != 18 &&
2507                         drm_default_rgb_quant_range(adjusted_mode) ==
2508                         HDMI_QUANTIZATION_RANGE_LIMITED;
2509         } else {
2510                 return intel_conn_state->broadcast_rgb ==
2511                         INTEL_BROADCAST_RGB_LIMITED;
2512         }
2513 }
2514
2515 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2516                                     enum port port)
2517 {
2518         if (IS_G4X(dev_priv))
2519                 return false;
2520         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2521                 return false;
2522
2523         return true;
2524 }
2525
2526 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2527                                              const struct drm_connector_state *conn_state,
2528                                              struct drm_dp_vsc_sdp *vsc)
2529 {
2530         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2532
2533         if (crtc_state->has_panel_replay) {
2534                 /*
2535                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2536                  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2537                  * Encoding/Colorimetry Format indication.
2538                  */
2539                 vsc->revision = 0x7;
2540         } else {
2541                 /*
2542                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2543                  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2544                  * Colorimetry Format indication.
2545                  */
2546                 vsc->revision = 0x5;
2547         }
2548
2549         vsc->length = 0x13;
2550
2551         /* DP 1.4a spec, Table 2-120 */
2552         switch (crtc_state->output_format) {
2553         case INTEL_OUTPUT_FORMAT_YCBCR444:
2554                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2555                 break;
2556         case INTEL_OUTPUT_FORMAT_YCBCR420:
2557                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2558                 break;
2559         case INTEL_OUTPUT_FORMAT_RGB:
2560         default:
2561                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2562         }
2563
2564         switch (conn_state->colorspace) {
2565         case DRM_MODE_COLORIMETRY_BT709_YCC:
2566                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2567                 break;
2568         case DRM_MODE_COLORIMETRY_XVYCC_601:
2569                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2570                 break;
2571         case DRM_MODE_COLORIMETRY_XVYCC_709:
2572                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2573                 break;
2574         case DRM_MODE_COLORIMETRY_SYCC_601:
2575                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2576                 break;
2577         case DRM_MODE_COLORIMETRY_OPYCC_601:
2578                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2579                 break;
2580         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2581                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2582                 break;
2583         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2584                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2585                 break;
2586         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2587                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2588                 break;
2589         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2590         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2591                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2592                 break;
2593         default:
2594                 /*
2595                  * RGB->YCBCR color conversion uses the BT.709
2596                  * color space.
2597                  */
2598                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2599                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2600                 else
2601                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2602                 break;
2603         }
2604
2605         vsc->bpc = crtc_state->pipe_bpp / 3;
2606
2607         /* only RGB pixelformat supports 6 bpc */
2608         drm_WARN_ON(&dev_priv->drm,
2609                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2610
2611         /* all YCbCr are always limited range */
2612         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2613         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2614 }
2615
2616 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2617                                      struct intel_crtc_state *crtc_state,
2618                                      const struct drm_connector_state *conn_state)
2619 {
2620         struct drm_dp_vsc_sdp *vsc;
2621
2622         if ((!intel_dp->colorimetry_support ||
2623              !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2624             !crtc_state->has_psr)
2625                 return;
2626
2627         vsc = &crtc_state->infoframes.vsc;
2628
2629         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2630         vsc->sdp_type = DP_SDP_VSC;
2631
2632         /* Needs colorimetry */
2633         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2634                 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2635                                                  vsc);
2636         } else if (crtc_state->has_psr2) {
2637                 /*
2638                  * [PSR2 without colorimetry]
2639                  * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2640                  * 3D stereo + PSR/PSR2 + Y-coordinate.
2641                  */
2642                 vsc->revision = 0x4;
2643                 vsc->length = 0xe;
2644         } else if (crtc_state->has_panel_replay) {
2645                 /*
2646                  * [Panel Replay without colorimetry info]
2647                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2648                  * VSC SDP supporting 3D stereo + Panel Replay.
2649                  */
2650                 vsc->revision = 0x6;
2651                 vsc->length = 0x10;
2652         } else {
2653                 /*
2654                  * [PSR1]
2655                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2656                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2657                  * higher).
2658                  */
2659                 vsc->revision = 0x2;
2660                 vsc->length = 0x8;
2661         }
2662 }
2663
2664 static void
2665 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2666                                             struct intel_crtc_state *crtc_state,
2667                                             const struct drm_connector_state *conn_state)
2668 {
2669         int ret;
2670         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2671         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2672
2673         if (!conn_state->hdr_output_metadata)
2674                 return;
2675
2676         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2677
2678         if (ret) {
2679                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2680                 return;
2681         }
2682
2683         crtc_state->infoframes.enable |=
2684                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2685 }
2686
2687 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2688                                     enum transcoder cpu_transcoder)
2689 {
2690         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2691                 return true;
2692
2693         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2694 }
2695
2696 static bool can_enable_drrs(struct intel_connector *connector,
2697                             const struct intel_crtc_state *pipe_config,
2698                             const struct drm_display_mode *downclock_mode)
2699 {
2700         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2701
2702         if (pipe_config->vrr.enable)
2703                 return false;
2704
2705         /*
2706          * DRRS and PSR can't be enable together, so giving preference to PSR
2707          * as it allows more power-savings by complete shutting down display,
2708          * so to guarantee this, intel_drrs_compute_config() must be called
2709          * after intel_psr_compute_config().
2710          */
2711         if (pipe_config->has_psr)
2712                 return false;
2713
2714         /* FIXME missing FDI M2/N2 etc. */
2715         if (pipe_config->has_pch_encoder)
2716                 return false;
2717
2718         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2719                 return false;
2720
2721         return downclock_mode &&
2722                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2723 }
2724
2725 static void
2726 intel_dp_drrs_compute_config(struct intel_connector *connector,
2727                              struct intel_crtc_state *pipe_config,
2728                              int link_bpp_x16)
2729 {
2730         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2731         const struct drm_display_mode *downclock_mode =
2732                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2733         int pixel_clock;
2734
2735         if (has_seamless_m_n(connector))
2736                 pipe_config->update_m_n = true;
2737
2738         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2739                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2740                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2741                 return;
2742         }
2743
2744         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2745                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2746
2747         pipe_config->has_drrs = true;
2748
2749         pixel_clock = downclock_mode->clock;
2750         if (pipe_config->splitter.enable)
2751                 pixel_clock /= pipe_config->splitter.link_count;
2752
2753         intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2754                                pipe_config->port_clock,
2755                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2756                                &pipe_config->dp_m2_n2);
2757
2758         /* FIXME: abstract this better */
2759         if (pipe_config->splitter.enable)
2760                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2761 }
2762
2763 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2764                                struct intel_crtc_state *crtc_state,
2765                                const struct drm_connector_state *conn_state)
2766 {
2767         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2768         const struct intel_digital_connector_state *intel_conn_state =
2769                 to_intel_digital_connector_state(conn_state);
2770         struct intel_connector *connector =
2771                 to_intel_connector(conn_state->connector);
2772
2773         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2774             !intel_dp_port_has_audio(i915, encoder->port))
2775                 return false;
2776
2777         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2778                 return connector->base.display_info.has_audio;
2779         else
2780                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2781 }
2782
2783 static int
2784 intel_dp_compute_output_format(struct intel_encoder *encoder,
2785                                struct intel_crtc_state *crtc_state,
2786                                struct drm_connector_state *conn_state,
2787                                bool respect_downstream_limits)
2788 {
2789         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2790         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2791         struct intel_connector *connector = intel_dp->attached_connector;
2792         const struct drm_display_info *info = &connector->base.display_info;
2793         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2794         bool ycbcr_420_only;
2795         int ret;
2796
2797         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2798
2799         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2800                 drm_dbg_kms(&i915->drm,
2801                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2802                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2803         } else {
2804                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2805         }
2806
2807         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2808
2809         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2810                                            respect_downstream_limits);
2811         if (ret) {
2812                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2813                     !connector->base.ycbcr_420_allowed ||
2814                     !drm_mode_is_420_also(info, adjusted_mode))
2815                         return ret;
2816
2817                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2818                 crtc_state->output_format = intel_dp_output_format(connector,
2819                                                                    crtc_state->sink_format);
2820                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2821                                                    respect_downstream_limits);
2822         }
2823
2824         return ret;
2825 }
2826
2827 void
2828 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2829                               struct intel_crtc_state *pipe_config,
2830                               struct drm_connector_state *conn_state)
2831 {
2832         pipe_config->has_audio =
2833                 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2834                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2835
2836         pipe_config->sdp_split_enable = pipe_config->has_audio &&
2837                                         intel_dp_is_uhbr(pipe_config);
2838 }
2839
2840 int
2841 intel_dp_compute_config(struct intel_encoder *encoder,
2842                         struct intel_crtc_state *pipe_config,
2843                         struct drm_connector_state *conn_state)
2844 {
2845         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2846         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2847         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2848         const struct drm_display_mode *fixed_mode;
2849         struct intel_connector *connector = intel_dp->attached_connector;
2850         int ret = 0, link_bpp_x16;
2851
2852         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2853                 pipe_config->has_pch_encoder = true;
2854
2855         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2856         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2857                 ret = intel_panel_compute_config(connector, adjusted_mode);
2858                 if (ret)
2859                         return ret;
2860         }
2861
2862         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2863                 return -EINVAL;
2864
2865         if (!connector->base.interlace_allowed &&
2866             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2867                 return -EINVAL;
2868
2869         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2870                 return -EINVAL;
2871
2872         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2873                 return -EINVAL;
2874
2875         /*
2876          * Try to respect downstream TMDS clock limits first, if
2877          * that fails assume the user might know something we don't.
2878          */
2879         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2880         if (ret)
2881                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2882         if (ret)
2883                 return ret;
2884
2885         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2886             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2887                 ret = intel_panel_fitting(pipe_config, conn_state);
2888                 if (ret)
2889                         return ret;
2890         }
2891
2892         pipe_config->limited_color_range =
2893                 intel_dp_limited_color_range(pipe_config, conn_state);
2894
2895         pipe_config->enhanced_framing =
2896                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2897
2898         if (pipe_config->dsc.compression_enable)
2899                 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2900         else
2901                 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2902                                                               pipe_config->pipe_bpp));
2903
2904         if (intel_dp->mso_link_count) {
2905                 int n = intel_dp->mso_link_count;
2906                 int overlap = intel_dp->mso_pixel_overlap;
2907
2908                 pipe_config->splitter.enable = true;
2909                 pipe_config->splitter.link_count = n;
2910                 pipe_config->splitter.pixel_overlap = overlap;
2911
2912                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2913                             n, overlap);
2914
2915                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2916                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2917                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2918                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2919                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2920                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2921                 adjusted_mode->crtc_clock /= n;
2922         }
2923
2924         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2925
2926         intel_link_compute_m_n(link_bpp_x16,
2927                                pipe_config->lane_count,
2928                                adjusted_mode->crtc_clock,
2929                                pipe_config->port_clock,
2930                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2931                                &pipe_config->dp_m_n);
2932
2933         /* FIXME: abstract this better */
2934         if (pipe_config->splitter.enable)
2935                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2936
2937         if (!HAS_DDI(dev_priv))
2938                 g4x_dp_set_clock(encoder, pipe_config);
2939
2940         intel_vrr_compute_config(pipe_config, conn_state);
2941         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2942         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
2943         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2944         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2945
2946         return 0;
2947 }
2948
2949 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2950                               int link_rate, int lane_count)
2951 {
2952         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2953         intel_dp->link_trained = false;
2954         intel_dp->link_rate = link_rate;
2955         intel_dp->lane_count = lane_count;
2956 }
2957
2958 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2959 {
2960         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2961         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2962 }
2963
2964 /* Enable backlight PWM and backlight PP control. */
2965 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2966                             const struct drm_connector_state *conn_state)
2967 {
2968         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2969         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2970
2971         if (!intel_dp_is_edp(intel_dp))
2972                 return;
2973
2974         drm_dbg_kms(&i915->drm, "\n");
2975
2976         intel_backlight_enable(crtc_state, conn_state);
2977         intel_pps_backlight_on(intel_dp);
2978 }
2979
2980 /* Disable backlight PP control and backlight PWM. */
2981 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2982 {
2983         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2984         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2985
2986         if (!intel_dp_is_edp(intel_dp))
2987                 return;
2988
2989         drm_dbg_kms(&i915->drm, "\n");
2990
2991         intel_pps_backlight_off(intel_dp);
2992         intel_backlight_disable(old_conn_state);
2993 }
2994
2995 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2996 {
2997         /*
2998          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2999          * be capable of signalling downstream hpd with a long pulse.
3000          * Whether or not that means D3 is safe to use is not clear,
3001          * but let's assume so until proven otherwise.
3002          *
3003          * FIXME should really check all downstream ports...
3004          */
3005         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3006                 drm_dp_is_branch(intel_dp->dpcd) &&
3007                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3008 }
3009
3010 static int
3011 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3012 {
3013         int err;
3014         u8 val;
3015
3016         err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3017         if (err < 0)
3018                 return err;
3019
3020         if (set)
3021                 val |= flag;
3022         else
3023                 val &= ~flag;
3024
3025         return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3026 }
3027
3028 static void
3029 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3030                                     bool enable)
3031 {
3032         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3033
3034         if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3035                                          DP_DECOMPRESSION_EN, enable) < 0)
3036                 drm_dbg_kms(&i915->drm,
3037                             "Failed to %s sink decompression state\n",
3038                             str_enable_disable(enable));
3039 }
3040
3041 static void
3042 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3043                                   bool enable)
3044 {
3045         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3046         struct drm_dp_aux *aux = connector->port ?
3047                                  connector->port->passthrough_aux : NULL;
3048
3049         if (!aux)
3050                 return;
3051
3052         if (write_dsc_decompression_flag(aux,
3053                                          DP_DSC_PASSTHROUGH_EN, enable) < 0)
3054                 drm_dbg_kms(&i915->drm,
3055                             "Failed to %s sink compression passthrough state\n",
3056                             str_enable_disable(enable));
3057 }
3058
3059 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3060                                       const struct intel_connector *connector,
3061                                       bool for_get_ref)
3062 {
3063         struct drm_i915_private *i915 = to_i915(state->base.dev);
3064         struct drm_connector *_connector_iter;
3065         struct drm_connector_state *old_conn_state;
3066         struct drm_connector_state *new_conn_state;
3067         int ref_count = 0;
3068         int i;
3069
3070         /*
3071          * On SST the decompression AUX device won't be shared, each connector
3072          * uses for this its own AUX targeting the sink device.
3073          */
3074         if (!connector->mst_port)
3075                 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3076
3077         for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3078                                            old_conn_state, new_conn_state, i) {
3079                 const struct intel_connector *
3080                         connector_iter = to_intel_connector(_connector_iter);
3081
3082                 if (connector_iter->mst_port != connector->mst_port)
3083                         continue;
3084
3085                 if (!connector_iter->dp.dsc_decompression_enabled)
3086                         continue;
3087
3088                 drm_WARN_ON(&i915->drm,
3089                             (for_get_ref && !new_conn_state->crtc) ||
3090                             (!for_get_ref && !old_conn_state->crtc));
3091
3092                 if (connector_iter->dp.dsc_decompression_aux ==
3093                     connector->dp.dsc_decompression_aux)
3094                         ref_count++;
3095         }
3096
3097         return ref_count;
3098 }
3099
3100 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3101                                      struct intel_connector *connector)
3102 {
3103         bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3104
3105         connector->dp.dsc_decompression_enabled = true;
3106
3107         return ret;
3108 }
3109
3110 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3111                                      struct intel_connector *connector)
3112 {
3113         connector->dp.dsc_decompression_enabled = false;
3114
3115         return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3116 }
3117
3118 /**
3119  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3120  * @state: atomic state
3121  * @connector: connector to enable the decompression for
3122  * @new_crtc_state: new state for the CRTC driving @connector
3123  *
3124  * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3125  * register of the appropriate sink/branch device. On SST this is always the
3126  * sink device, whereas on MST based on each device's DSC capabilities it's
3127  * either the last branch device (enabling decompression in it) or both the
3128  * last branch device (enabling passthrough in it) and the sink device
3129  * (enabling decompression in it).
3130  */
3131 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3132                                         struct intel_connector *connector,
3133                                         const struct intel_crtc_state *new_crtc_state)
3134 {
3135         struct drm_i915_private *i915 = to_i915(state->base.dev);
3136
3137         if (!new_crtc_state->dsc.compression_enable)
3138                 return;
3139
3140         if (drm_WARN_ON(&i915->drm,
3141                         !connector->dp.dsc_decompression_aux ||
3142                         connector->dp.dsc_decompression_enabled))
3143                 return;
3144
3145         if (!intel_dp_dsc_aux_get_ref(state, connector))
3146                 return;
3147
3148         intel_dp_sink_set_dsc_passthrough(connector, true);
3149         intel_dp_sink_set_dsc_decompression(connector, true);
3150 }
3151
3152 /**
3153  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3154  * @state: atomic state
3155  * @connector: connector to disable the decompression for
3156  * @old_crtc_state: old state for the CRTC driving @connector
3157  *
3158  * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3159  * register of the appropriate sink/branch device, corresponding to the
3160  * sequence in intel_dp_sink_enable_decompression().
3161  */
3162 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3163                                          struct intel_connector *connector,
3164                                          const struct intel_crtc_state *old_crtc_state)
3165 {
3166         struct drm_i915_private *i915 = to_i915(state->base.dev);
3167
3168         if (!old_crtc_state->dsc.compression_enable)
3169                 return;
3170
3171         if (drm_WARN_ON(&i915->drm,
3172                         !connector->dp.dsc_decompression_aux ||
3173                         !connector->dp.dsc_decompression_enabled))
3174                 return;
3175
3176         if (!intel_dp_dsc_aux_put_ref(state, connector))
3177                 return;
3178
3179         intel_dp_sink_set_dsc_decompression(connector, false);
3180         intel_dp_sink_set_dsc_passthrough(connector, false);
3181 }
3182
3183 static void
3184 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3185 {
3186         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3187         u8 oui[] = { 0x00, 0xaa, 0x01 };
3188         u8 buf[3] = {};
3189
3190         /*
3191          * During driver init, we want to be careful and avoid changing the source OUI if it's
3192          * already set to what we want, so as to avoid clearing any state by accident
3193          */
3194         if (careful) {
3195                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3196                         drm_err(&i915->drm, "Failed to read source OUI\n");
3197
3198                 if (memcmp(oui, buf, sizeof(oui)) == 0)
3199                         return;
3200         }
3201
3202         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3203                 drm_err(&i915->drm, "Failed to write source OUI\n");
3204
3205         intel_dp->last_oui_write = jiffies;
3206 }
3207
3208 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3209 {
3210         struct intel_connector *connector = intel_dp->attached_connector;
3211         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3212
3213         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3214                     connector->base.base.id, connector->base.name,
3215                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3216
3217         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3218                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3219 }
3220
3221 /* If the device supports it, try to set the power state appropriately */
3222 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3223 {
3224         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3225         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3226         int ret, i;
3227
3228         /* Should have a valid DPCD by this point */
3229         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3230                 return;
3231
3232         if (mode != DP_SET_POWER_D0) {
3233                 if (downstream_hpd_needs_d0(intel_dp))
3234                         return;
3235
3236                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3237         } else {
3238                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3239
3240                 lspcon_resume(dp_to_dig_port(intel_dp));
3241
3242                 /* Write the source OUI as early as possible */
3243                 if (intel_dp_is_edp(intel_dp))
3244                         intel_edp_init_source_oui(intel_dp, false);
3245
3246                 /*
3247                  * When turning on, we need to retry for 1ms to give the sink
3248                  * time to wake up.
3249                  */
3250                 for (i = 0; i < 3; i++) {
3251                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3252                         if (ret == 1)
3253                                 break;
3254                         msleep(1);
3255                 }
3256
3257                 if (ret == 1 && lspcon->active)
3258                         lspcon_wait_pcon_mode(lspcon);
3259         }
3260
3261         if (ret != 1)
3262                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3263                             encoder->base.base.id, encoder->base.name,
3264                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3265 }
3266
3267 static bool
3268 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3269
3270 /**
3271  * intel_dp_sync_state - sync the encoder state during init/resume
3272  * @encoder: intel encoder to sync
3273  * @crtc_state: state for the CRTC connected to the encoder
3274  *
3275  * Sync any state stored in the encoder wrt. HW state during driver init
3276  * and system resume.
3277  */
3278 void intel_dp_sync_state(struct intel_encoder *encoder,
3279                          const struct intel_crtc_state *crtc_state)
3280 {
3281         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3282
3283         if (!crtc_state)
3284                 return;
3285
3286         /*
3287          * Don't clobber DPCD if it's been already read out during output
3288          * setup (eDP) or detect.
3289          */
3290         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3291                 intel_dp_get_dpcd(intel_dp);
3292
3293         intel_dp_reset_max_link_params(intel_dp);
3294 }
3295
3296 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3297                                     struct intel_crtc_state *crtc_state)
3298 {
3299         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3300         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3301         bool fastset = true;
3302
3303         /*
3304          * If BIOS has set an unsupported or non-standard link rate for some
3305          * reason force an encoder recompute and full modeset.
3306          */
3307         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3308                                 crtc_state->port_clock) < 0) {
3309                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3310                             encoder->base.base.id, encoder->base.name);
3311                 crtc_state->uapi.connectors_changed = true;
3312                 fastset = false;
3313         }
3314
3315         /*
3316          * FIXME hack to force full modeset when DSC is being used.
3317          *
3318          * As long as we do not have full state readout and config comparison
3319          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3320          * Remove once we have readout for DSC.
3321          */
3322         if (crtc_state->dsc.compression_enable) {
3323                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3324                             encoder->base.base.id, encoder->base.name);
3325                 crtc_state->uapi.mode_changed = true;
3326                 fastset = false;
3327         }
3328
3329         return fastset;
3330 }
3331
3332 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3333 {
3334         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3335
3336         /* Clear the cached register set to avoid using stale values */
3337
3338         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3339
3340         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3341                              intel_dp->pcon_dsc_dpcd,
3342                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3343                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3344                         DP_PCON_DSC_ENCODER);
3345
3346         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3347                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3348 }
3349
3350 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3351 {
3352         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3353         int i;
3354
3355         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3356                 if (frl_bw_mask & (1 << i))
3357                         return bw_gbps[i];
3358         }
3359         return 0;
3360 }
3361
3362 static int intel_dp_pcon_set_frl_mask(int max_frl)
3363 {
3364         switch (max_frl) {
3365         case 48:
3366                 return DP_PCON_FRL_BW_MASK_48GBPS;
3367         case 40:
3368                 return DP_PCON_FRL_BW_MASK_40GBPS;
3369         case 32:
3370                 return DP_PCON_FRL_BW_MASK_32GBPS;
3371         case 24:
3372                 return DP_PCON_FRL_BW_MASK_24GBPS;
3373         case 18:
3374                 return DP_PCON_FRL_BW_MASK_18GBPS;
3375         case 9:
3376                 return DP_PCON_FRL_BW_MASK_9GBPS;
3377         }
3378
3379         return 0;
3380 }
3381
3382 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3383 {
3384         struct intel_connector *intel_connector = intel_dp->attached_connector;
3385         struct drm_connector *connector = &intel_connector->base;
3386         int max_frl_rate;
3387         int max_lanes, rate_per_lane;
3388         int max_dsc_lanes, dsc_rate_per_lane;
3389
3390         max_lanes = connector->display_info.hdmi.max_lanes;
3391         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3392         max_frl_rate = max_lanes * rate_per_lane;
3393
3394         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3395                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3396                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3397                 if (max_dsc_lanes && dsc_rate_per_lane)
3398                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3399         }
3400
3401         return max_frl_rate;
3402 }
3403
3404 static bool
3405 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3406                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3407 {
3408         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3409             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3410             *frl_trained_mask >= max_frl_bw_mask)
3411                 return true;
3412
3413         return false;
3414 }
3415
3416 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3417 {
3418 #define TIMEOUT_FRL_READY_MS 500
3419 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3420
3421         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3422         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3423         u8 max_frl_bw_mask = 0, frl_trained_mask;
3424         bool is_active;
3425
3426         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3427         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3428
3429         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3430         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3431
3432         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3433
3434         if (max_frl_bw <= 0)
3435                 return -EINVAL;
3436
3437         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3438         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3439
3440         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3441                 goto frl_trained;
3442
3443         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3444         if (ret < 0)
3445                 return ret;
3446         /* Wait for PCON to be FRL Ready */
3447         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3448
3449         if (!is_active)
3450                 return -ETIMEDOUT;
3451
3452         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3453                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3454         if (ret < 0)
3455                 return ret;
3456         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3457                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3458         if (ret < 0)
3459                 return ret;
3460         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3461         if (ret < 0)
3462                 return ret;
3463         /*
3464          * Wait for FRL to be completed
3465          * Check if the HDMI Link is up and active.
3466          */
3467         wait_for(is_active =
3468                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3469                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3470
3471         if (!is_active)
3472                 return -ETIMEDOUT;
3473
3474 frl_trained:
3475         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3476         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3477         intel_dp->frl.is_trained = true;
3478         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3479
3480         return 0;
3481 }
3482
3483 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3484 {
3485         if (drm_dp_is_branch(intel_dp->dpcd) &&
3486             intel_dp_has_hdmi_sink(intel_dp) &&
3487             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3488                 return true;
3489
3490         return false;
3491 }
3492
3493 static
3494 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3495 {
3496         int ret;
3497         u8 buf = 0;
3498
3499         /* Set PCON source control mode */
3500         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3501
3502         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3503         if (ret < 0)
3504                 return ret;
3505
3506         /* Set HDMI LINK ENABLE */
3507         buf |= DP_PCON_ENABLE_HDMI_LINK;
3508         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3509         if (ret < 0)
3510                 return ret;
3511
3512         return 0;
3513 }
3514
3515 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3516 {
3517         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3518
3519         /*
3520          * Always go for FRL training if:
3521          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3522          * -sink is HDMI2.1
3523          */
3524         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3525             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3526             intel_dp->frl.is_trained)
3527                 return;
3528
3529         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3530                 int ret, mode;
3531
3532                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3533                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3534                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3535
3536                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3537                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3538         } else {
3539                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3540         }
3541 }
3542
3543 static int
3544 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3545 {
3546         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3547
3548         return intel_hdmi_dsc_get_slice_height(vactive);
3549 }
3550
3551 static int
3552 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3553                              const struct intel_crtc_state *crtc_state)
3554 {
3555         struct intel_connector *intel_connector = intel_dp->attached_connector;
3556         struct drm_connector *connector = &intel_connector->base;
3557         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3558         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3559         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3560         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3561
3562         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3563                                              pcon_max_slice_width,
3564                                              hdmi_max_slices, hdmi_throughput);
3565 }
3566
3567 static int
3568 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3569                           const struct intel_crtc_state *crtc_state,
3570                           int num_slices, int slice_width)
3571 {
3572         struct intel_connector *intel_connector = intel_dp->attached_connector;
3573         struct drm_connector *connector = &intel_connector->base;
3574         int output_format = crtc_state->output_format;
3575         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3576         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3577         int hdmi_max_chunk_bytes =
3578                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3579
3580         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3581                                       num_slices, output_format, hdmi_all_bpp,
3582                                       hdmi_max_chunk_bytes);
3583 }
3584
3585 void
3586 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3587                             const struct intel_crtc_state *crtc_state)
3588 {
3589         u8 pps_param[6];
3590         int slice_height;
3591         int slice_width;
3592         int num_slices;
3593         int bits_per_pixel;
3594         int ret;
3595         struct intel_connector *intel_connector = intel_dp->attached_connector;
3596         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3597         struct drm_connector *connector;
3598         bool hdmi_is_dsc_1_2;
3599
3600         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3601                 return;
3602
3603         if (!intel_connector)
3604                 return;
3605         connector = &intel_connector->base;
3606         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3607
3608         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3609             !hdmi_is_dsc_1_2)
3610                 return;
3611
3612         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3613         if (!slice_height)
3614                 return;
3615
3616         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3617         if (!num_slices)
3618                 return;
3619
3620         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3621                                    num_slices);
3622
3623         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3624                                                    num_slices, slice_width);
3625         if (!bits_per_pixel)
3626                 return;
3627
3628         pps_param[0] = slice_height & 0xFF;
3629         pps_param[1] = slice_height >> 8;
3630         pps_param[2] = slice_width & 0xFF;
3631         pps_param[3] = slice_width >> 8;
3632         pps_param[4] = bits_per_pixel & 0xFF;
3633         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3634
3635         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3636         if (ret < 0)
3637                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3638 }
3639
3640 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3641                                            const struct intel_crtc_state *crtc_state)
3642 {
3643         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3644         bool ycbcr444_to_420 = false;
3645         bool rgb_to_ycbcr = false;
3646         u8 tmp;
3647
3648         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3649                 return;
3650
3651         if (!drm_dp_is_branch(intel_dp->dpcd))
3652                 return;
3653
3654         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3655
3656         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3657                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3658                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3659                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3660
3661         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3662                 switch (crtc_state->output_format) {
3663                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3664                         break;
3665                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3666                         ycbcr444_to_420 = true;
3667                         break;
3668                 case INTEL_OUTPUT_FORMAT_RGB:
3669                         rgb_to_ycbcr = true;
3670                         ycbcr444_to_420 = true;
3671                         break;
3672                 default:
3673                         MISSING_CASE(crtc_state->output_format);
3674                         break;
3675                 }
3676         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3677                 switch (crtc_state->output_format) {
3678                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3679                         break;
3680                 case INTEL_OUTPUT_FORMAT_RGB:
3681                         rgb_to_ycbcr = true;
3682                         break;
3683                 default:
3684                         MISSING_CASE(crtc_state->output_format);
3685                         break;
3686                 }
3687         }
3688
3689         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3690
3691         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3692                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3693                 drm_dbg_kms(&i915->drm,
3694                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3695                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3696
3697         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3698
3699         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3700                 drm_dbg_kms(&i915->drm,
3701                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3702                             str_enable_disable(tmp));
3703 }
3704
3705 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3706 {
3707         u8 dprx = 0;
3708
3709         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3710                               &dprx) != 1)
3711                 return false;
3712         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3713 }
3714
3715 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3716                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3717 {
3718         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3719                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3720                 drm_err(aux->drm_dev,
3721                         "Failed to read DPCD register 0x%x\n",
3722                         DP_DSC_SUPPORT);
3723                 return;
3724         }
3725
3726         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3727                     DP_DSC_RECEIVER_CAP_SIZE,
3728                     dsc_dpcd);
3729 }
3730
3731 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3732 {
3733         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3734
3735         /*
3736          * Clear the cached register set to avoid using stale values
3737          * for the sinks that do not support DSC.
3738          */
3739         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3740
3741         /* Clear fec_capable to avoid using stale values */
3742         connector->dp.fec_capability = 0;
3743
3744         if (dpcd_rev < DP_DPCD_REV_14)
3745                 return;
3746
3747         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3748                                connector->dp.dsc_dpcd);
3749
3750         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3751                               &connector->dp.fec_capability) < 0) {
3752                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3753                 return;
3754         }
3755
3756         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3757                     connector->dp.fec_capability);
3758 }
3759
3760 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3761 {
3762         if (edp_dpcd_rev < DP_EDP_14)
3763                 return;
3764
3765         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3766 }
3767
3768 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3769                                      struct drm_display_mode *mode)
3770 {
3771         struct intel_dp *intel_dp = intel_attached_dp(connector);
3772         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3773         int n = intel_dp->mso_link_count;
3774         int overlap = intel_dp->mso_pixel_overlap;
3775
3776         if (!mode || !n)
3777                 return;
3778
3779         mode->hdisplay = (mode->hdisplay - overlap) * n;
3780         mode->hsync_start = (mode->hsync_start - overlap) * n;
3781         mode->hsync_end = (mode->hsync_end - overlap) * n;
3782         mode->htotal = (mode->htotal - overlap) * n;
3783         mode->clock *= n;
3784
3785         drm_mode_set_name(mode);
3786
3787         drm_dbg_kms(&i915->drm,
3788                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3789                     connector->base.base.id, connector->base.name,
3790                     DRM_MODE_ARG(mode));
3791 }
3792
3793 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3794 {
3795         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3796         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3797         struct intel_connector *connector = intel_dp->attached_connector;
3798
3799         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3800                 /*
3801                  * This is a big fat ugly hack.
3802                  *
3803                  * Some machines in UEFI boot mode provide us a VBT that has 18
3804                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3805                  * unknown we fail to light up. Yet the same BIOS boots up with
3806                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3807                  * max, not what it tells us to use.
3808                  *
3809                  * Note: This will still be broken if the eDP panel is not lit
3810                  * up by the BIOS, and thus we can't get the mode at module
3811                  * load.
3812                  */
3813                 drm_dbg_kms(&dev_priv->drm,
3814                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3815                             pipe_bpp, connector->panel.vbt.edp.bpp);
3816                 connector->panel.vbt.edp.bpp = pipe_bpp;
3817         }
3818 }
3819
3820 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3821 {
3822         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3823         struct intel_connector *connector = intel_dp->attached_connector;
3824         struct drm_display_info *info = &connector->base.display_info;
3825         u8 mso;
3826
3827         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3828                 return;
3829
3830         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3831                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3832                 return;
3833         }
3834
3835         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3836         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3837         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3838                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3839                 mso = 0;
3840         }
3841
3842         if (mso) {
3843                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3844                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3845                             info->mso_pixel_overlap);
3846                 if (!HAS_MSO(i915)) {
3847                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3848                         mso = 0;
3849                 }
3850         }
3851
3852         intel_dp->mso_link_count = mso;
3853         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3854 }
3855
3856 static bool
3857 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3858 {
3859         struct drm_i915_private *dev_priv =
3860                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3861
3862         /* this function is meant to be called only once */
3863         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3864
3865         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3866                 return false;
3867
3868         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3869                          drm_dp_is_branch(intel_dp->dpcd));
3870
3871         /*
3872          * Read the eDP display control registers.
3873          *
3874          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3875          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3876          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3877          * method). The display control registers should read zero if they're
3878          * not supported anyway.
3879          */
3880         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3881                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3882                              sizeof(intel_dp->edp_dpcd)) {
3883                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3884                             (int)sizeof(intel_dp->edp_dpcd),
3885                             intel_dp->edp_dpcd);
3886
3887                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3888         }
3889
3890         /*
3891          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3892          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3893          */
3894         intel_psr_init_dpcd(intel_dp);
3895
3896         /* Clear the default sink rates */
3897         intel_dp->num_sink_rates = 0;
3898
3899         /* Read the eDP 1.4+ supported link rates. */
3900         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3901                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3902                 int i;
3903
3904                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3905                                 sink_rates, sizeof(sink_rates));
3906
3907                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3908                         int val = le16_to_cpu(sink_rates[i]);
3909
3910                         if (val == 0)
3911                                 break;
3912
3913                         /* Value read multiplied by 200kHz gives the per-lane
3914                          * link rate in kHz. The source rates are, however,
3915                          * stored in terms of LS_Clk kHz. The full conversion
3916                          * back to symbols is
3917                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3918                          */
3919                         intel_dp->sink_rates[i] = (val * 200) / 10;
3920                 }
3921                 intel_dp->num_sink_rates = i;
3922         }
3923
3924         /*
3925          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3926          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3927          */
3928         if (intel_dp->num_sink_rates)
3929                 intel_dp->use_rate_select = true;
3930         else
3931                 intel_dp_set_sink_rates(intel_dp);
3932         intel_dp_set_max_sink_lane_count(intel_dp);
3933
3934         /* Read the eDP DSC DPCD registers */
3935         if (HAS_DSC(dev_priv))
3936                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3937                                            connector);
3938
3939         /*
3940          * If needed, program our source OUI so we can make various Intel-specific AUX services
3941          * available (such as HDR backlight controls)
3942          */
3943         intel_edp_init_source_oui(intel_dp, true);
3944
3945         return true;
3946 }
3947
3948 static bool
3949 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3950 {
3951         if (!intel_dp->attached_connector)
3952                 return false;
3953
3954         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3955                                           intel_dp->dpcd,
3956                                           &intel_dp->desc);
3957 }
3958
3959 static bool
3960 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3961 {
3962         int ret;
3963
3964         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3965                 return false;
3966
3967         /*
3968          * Don't clobber cached eDP rates. Also skip re-reading
3969          * the OUI/ID since we know it won't change.
3970          */
3971         if (!intel_dp_is_edp(intel_dp)) {
3972                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3973                                  drm_dp_is_branch(intel_dp->dpcd));
3974
3975                 intel_dp_set_sink_rates(intel_dp);
3976                 intel_dp_set_max_sink_lane_count(intel_dp);
3977                 intel_dp_set_common_rates(intel_dp);
3978         }
3979
3980         if (intel_dp_has_sink_count(intel_dp)) {
3981                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3982                 if (ret < 0)
3983                         return false;
3984
3985                 /*
3986                  * Sink count can change between short pulse hpd hence
3987                  * a member variable in intel_dp will track any changes
3988                  * between short pulse interrupts.
3989                  */
3990                 intel_dp->sink_count = ret;
3991
3992                 /*
3993                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3994                  * a dongle is present but no display. Unless we require to know
3995                  * if a dongle is present or not, we don't need to update
3996                  * downstream port information. So, an early return here saves
3997                  * time from performing other operations which are not required.
3998                  */
3999                 if (!intel_dp->sink_count)
4000                         return false;
4001         }
4002
4003         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4004                                            intel_dp->downstream_ports) == 0;
4005 }
4006
4007 static bool
4008 intel_dp_can_mst(struct intel_dp *intel_dp)
4009 {
4010         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4011
4012         return i915->display.params.enable_dp_mst &&
4013                 intel_dp_mst_source_support(intel_dp) &&
4014                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4015 }
4016
4017 static void
4018 intel_dp_configure_mst(struct intel_dp *intel_dp)
4019 {
4020         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4021         struct intel_encoder *encoder =
4022                 &dp_to_dig_port(intel_dp)->base;
4023         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4024
4025         drm_dbg_kms(&i915->drm,
4026                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4027                     encoder->base.base.id, encoder->base.name,
4028                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
4029                     str_yes_no(sink_can_mst),
4030                     str_yes_no(i915->display.params.enable_dp_mst));
4031
4032         if (!intel_dp_mst_source_support(intel_dp))
4033                 return;
4034
4035         intel_dp->is_mst = sink_can_mst &&
4036                 i915->display.params.enable_dp_mst;
4037
4038         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4039                                         intel_dp->is_mst);
4040 }
4041
4042 static bool
4043 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4044 {
4045         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4046 }
4047
4048 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4049 {
4050         int retry;
4051
4052         for (retry = 0; retry < 3; retry++) {
4053                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4054                                       &esi[1], 3) == 3)
4055                         return true;
4056         }
4057
4058         return false;
4059 }
4060
4061 bool
4062 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4063                        const struct drm_connector_state *conn_state)
4064 {
4065         /*
4066          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4067          * of Color Encoding Format and Content Color Gamut], in order to
4068          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4069          */
4070         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4071                 return true;
4072
4073         switch (conn_state->colorspace) {
4074         case DRM_MODE_COLORIMETRY_SYCC_601:
4075         case DRM_MODE_COLORIMETRY_OPYCC_601:
4076         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4077         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4078         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4079                 return true;
4080         default:
4081                 break;
4082         }
4083
4084         return false;
4085 }
4086
4087 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4088                                      struct dp_sdp *sdp, size_t size)
4089 {
4090         size_t length = sizeof(struct dp_sdp);
4091
4092         if (size < length)
4093                 return -ENOSPC;
4094
4095         memset(sdp, 0, size);
4096
4097         /*
4098          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4099          * VSC SDP Header Bytes
4100          */
4101         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4102         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4103         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4104         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4105
4106         if (vsc->revision == 0x6) {
4107                 sdp->db[0] = 1;
4108                 sdp->db[3] = 1;
4109         }
4110
4111         /*
4112          * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
4113          * Format as per DP 1.4a spec and DP 2.0 respectively.
4114          */
4115         if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
4116                 goto out;
4117
4118         /* VSC SDP Payload for DB16 through DB18 */
4119         /* Pixel Encoding and Colorimetry Formats  */
4120         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4121         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4122
4123         switch (vsc->bpc) {
4124         case 6:
4125                 /* 6bpc: 0x0 */
4126                 break;
4127         case 8:
4128                 sdp->db[17] = 0x1; /* DB17[3:0] */
4129                 break;
4130         case 10:
4131                 sdp->db[17] = 0x2;
4132                 break;
4133         case 12:
4134                 sdp->db[17] = 0x3;
4135                 break;
4136         case 16:
4137                 sdp->db[17] = 0x4;
4138                 break;
4139         default:
4140                 MISSING_CASE(vsc->bpc);
4141                 break;
4142         }
4143         /* Dynamic Range and Component Bit Depth */
4144         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4145                 sdp->db[17] |= 0x80;  /* DB17[7] */
4146
4147         /* Content Type */
4148         sdp->db[18] = vsc->content_type & 0x7;
4149
4150 out:
4151         return length;
4152 }
4153
4154 static ssize_t
4155 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4156                                          const struct hdmi_drm_infoframe *drm_infoframe,
4157                                          struct dp_sdp *sdp,
4158                                          size_t size)
4159 {
4160         size_t length = sizeof(struct dp_sdp);
4161         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4162         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4163         ssize_t len;
4164
4165         if (size < length)
4166                 return -ENOSPC;
4167
4168         memset(sdp, 0, size);
4169
4170         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4171         if (len < 0) {
4172                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4173                 return -ENOSPC;
4174         }
4175
4176         if (len != infoframe_size) {
4177                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4178                 return -ENOSPC;
4179         }
4180
4181         /*
4182          * Set up the infoframe sdp packet for HDR static metadata.
4183          * Prepare VSC Header for SU as per DP 1.4a spec,
4184          * Table 2-100 and Table 2-101
4185          */
4186
4187         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4188         sdp->sdp_header.HB0 = 0;
4189         /*
4190          * Packet Type 80h + Non-audio INFOFRAME Type value
4191          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4192          * - 80h + Non-audio INFOFRAME Type value
4193          * - InfoFrame Type: 0x07
4194          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4195          */
4196         sdp->sdp_header.HB1 = drm_infoframe->type;
4197         /*
4198          * Least Significant Eight Bits of (Data Byte Count – 1)
4199          * infoframe_size - 1
4200          */
4201         sdp->sdp_header.HB2 = 0x1D;
4202         /* INFOFRAME SDP Version Number */
4203         sdp->sdp_header.HB3 = (0x13 << 2);
4204         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4205         sdp->db[0] = drm_infoframe->version;
4206         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4207         sdp->db[1] = drm_infoframe->length;
4208         /*
4209          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4210          * HDMI_INFOFRAME_HEADER_SIZE
4211          */
4212         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4213         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4214                HDMI_DRM_INFOFRAME_SIZE);
4215
4216         /*
4217          * Size of DP infoframe sdp packet for HDR static metadata consists of
4218          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4219          * - Two Data Blocks: 2 bytes
4220          *    CTA Header Byte2 (INFOFRAME Version Number)
4221          *    CTA Header Byte3 (Length of INFOFRAME)
4222          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4223          *
4224          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4225          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4226          * will pad rest of the size.
4227          */
4228         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4229 }
4230
4231 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4232                                const struct intel_crtc_state *crtc_state,
4233                                unsigned int type)
4234 {
4235         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4236         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4237         struct dp_sdp sdp = {};
4238         ssize_t len;
4239
4240         if ((crtc_state->infoframes.enable &
4241              intel_hdmi_infoframe_enable(type)) == 0)
4242                 return;
4243
4244         switch (type) {
4245         case DP_SDP_VSC:
4246                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4247                                             sizeof(sdp));
4248                 break;
4249         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4250                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4251                                                                &crtc_state->infoframes.drm.drm,
4252                                                                &sdp, sizeof(sdp));
4253                 break;
4254         default:
4255                 MISSING_CASE(type);
4256                 return;
4257         }
4258
4259         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4260                 return;
4261
4262         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4263 }
4264
4265 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4266                              bool enable,
4267                              const struct intel_crtc_state *crtc_state,
4268                              const struct drm_connector_state *conn_state)
4269 {
4270         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4271         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4272         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4273                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4274                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4275         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4276
4277         /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4278         if (!enable && HAS_DSC(dev_priv))
4279                 val &= ~VDIP_ENABLE_PPS;
4280
4281         /* When PSR is enabled, this routine doesn't disable VSC DIP */
4282         if (!crtc_state->has_psr)
4283                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4284
4285         intel_de_write(dev_priv, reg, val);
4286         intel_de_posting_read(dev_priv, reg);
4287
4288         if (!enable)
4289                 return;
4290
4291         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4292
4293         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4294 }
4295
4296 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4297                                    const void *buffer, size_t size)
4298 {
4299         const struct dp_sdp *sdp = buffer;
4300
4301         if (size < sizeof(struct dp_sdp))
4302                 return -EINVAL;
4303
4304         memset(vsc, 0, sizeof(*vsc));
4305
4306         if (sdp->sdp_header.HB0 != 0)
4307                 return -EINVAL;
4308
4309         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4310                 return -EINVAL;
4311
4312         vsc->sdp_type = sdp->sdp_header.HB1;
4313         vsc->revision = sdp->sdp_header.HB2;
4314         vsc->length = sdp->sdp_header.HB3;
4315
4316         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4317             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4318                 /*
4319                  * - HB2 = 0x2, HB3 = 0x8
4320                  *   VSC SDP supporting 3D stereo + PSR
4321                  * - HB2 = 0x4, HB3 = 0xe
4322                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4323                  *   first scan line of the SU region (applies to eDP v1.4b
4324                  *   and higher).
4325                  */
4326                 return 0;
4327         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4328                 /*
4329                  * - HB2 = 0x5, HB3 = 0x13
4330                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4331                  *   Format.
4332                  */
4333                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4334                 vsc->colorimetry = sdp->db[16] & 0xf;
4335                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4336
4337                 switch (sdp->db[17] & 0x7) {
4338                 case 0x0:
4339                         vsc->bpc = 6;
4340                         break;
4341                 case 0x1:
4342                         vsc->bpc = 8;
4343                         break;
4344                 case 0x2:
4345                         vsc->bpc = 10;
4346                         break;
4347                 case 0x3:
4348                         vsc->bpc = 12;
4349                         break;
4350                 case 0x4:
4351                         vsc->bpc = 16;
4352                         break;
4353                 default:
4354                         MISSING_CASE(sdp->db[17] & 0x7);
4355                         return -EINVAL;
4356                 }
4357
4358                 vsc->content_type = sdp->db[18] & 0x7;
4359         } else {
4360                 return -EINVAL;
4361         }
4362
4363         return 0;
4364 }
4365
4366 static int
4367 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4368                                            const void *buffer, size_t size)
4369 {
4370         int ret;
4371
4372         const struct dp_sdp *sdp = buffer;
4373
4374         if (size < sizeof(struct dp_sdp))
4375                 return -EINVAL;
4376
4377         if (sdp->sdp_header.HB0 != 0)
4378                 return -EINVAL;
4379
4380         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4381                 return -EINVAL;
4382
4383         /*
4384          * Least Significant Eight Bits of (Data Byte Count – 1)
4385          * 1Dh (i.e., Data Byte Count = 30 bytes).
4386          */
4387         if (sdp->sdp_header.HB2 != 0x1D)
4388                 return -EINVAL;
4389
4390         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4391         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4392                 return -EINVAL;
4393
4394         /* INFOFRAME SDP Version Number */
4395         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4396                 return -EINVAL;
4397
4398         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4399         if (sdp->db[0] != 1)
4400                 return -EINVAL;
4401
4402         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4403         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4404                 return -EINVAL;
4405
4406         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4407                                              HDMI_DRM_INFOFRAME_SIZE);
4408
4409         return ret;
4410 }
4411
4412 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4413                                   struct intel_crtc_state *crtc_state,
4414                                   struct drm_dp_vsc_sdp *vsc)
4415 {
4416         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4417         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4418         unsigned int type = DP_SDP_VSC;
4419         struct dp_sdp sdp = {};
4420         int ret;
4421
4422         if ((crtc_state->infoframes.enable &
4423              intel_hdmi_infoframe_enable(type)) == 0)
4424                 return;
4425
4426         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4427
4428         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4429
4430         if (ret)
4431                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4432 }
4433
4434 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4435                                                      struct intel_crtc_state *crtc_state,
4436                                                      struct hdmi_drm_infoframe *drm_infoframe)
4437 {
4438         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4439         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4440         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4441         struct dp_sdp sdp = {};
4442         int ret;
4443
4444         if ((crtc_state->infoframes.enable &
4445             intel_hdmi_infoframe_enable(type)) == 0)
4446                 return;
4447
4448         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4449                                  sizeof(sdp));
4450
4451         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4452                                                          sizeof(sdp));
4453
4454         if (ret)
4455                 drm_dbg_kms(&dev_priv->drm,
4456                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4457 }
4458
4459 void intel_read_dp_sdp(struct intel_encoder *encoder,
4460                        struct intel_crtc_state *crtc_state,
4461                        unsigned int type)
4462 {
4463         switch (type) {
4464         case DP_SDP_VSC:
4465                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4466                                       &crtc_state->infoframes.vsc);
4467                 break;
4468         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4469                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4470                                                          &crtc_state->infoframes.drm.drm);
4471                 break;
4472         default:
4473                 MISSING_CASE(type);
4474                 break;
4475         }
4476 }
4477
4478 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4479 {
4480         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4481         int status = 0;
4482         int test_link_rate;
4483         u8 test_lane_count, test_link_bw;
4484         /* (DP CTS 1.2)
4485          * 4.3.1.11
4486          */
4487         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4488         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4489                                    &test_lane_count);
4490
4491         if (status <= 0) {
4492                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4493                 return DP_TEST_NAK;
4494         }
4495         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4496
4497         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4498                                    &test_link_bw);
4499         if (status <= 0) {
4500                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4501                 return DP_TEST_NAK;
4502         }
4503         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4504
4505         /* Validate the requested link rate and lane count */
4506         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4507                                         test_lane_count))
4508                 return DP_TEST_NAK;
4509
4510         intel_dp->compliance.test_lane_count = test_lane_count;
4511         intel_dp->compliance.test_link_rate = test_link_rate;
4512
4513         return DP_TEST_ACK;
4514 }
4515
4516 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4517 {
4518         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4519         u8 test_pattern;
4520         u8 test_misc;
4521         __be16 h_width, v_height;
4522         int status = 0;
4523
4524         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4525         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4526                                    &test_pattern);
4527         if (status <= 0) {
4528                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4529                 return DP_TEST_NAK;
4530         }
4531         if (test_pattern != DP_COLOR_RAMP)
4532                 return DP_TEST_NAK;
4533
4534         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4535                                   &h_width, 2);
4536         if (status <= 0) {
4537                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4538                 return DP_TEST_NAK;
4539         }
4540
4541         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4542                                   &v_height, 2);
4543         if (status <= 0) {
4544                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4545                 return DP_TEST_NAK;
4546         }
4547
4548         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4549                                    &test_misc);
4550         if (status <= 0) {
4551                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4552                 return DP_TEST_NAK;
4553         }
4554         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4555                 return DP_TEST_NAK;
4556         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4557                 return DP_TEST_NAK;
4558         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4559         case DP_TEST_BIT_DEPTH_6:
4560                 intel_dp->compliance.test_data.bpc = 6;
4561                 break;
4562         case DP_TEST_BIT_DEPTH_8:
4563                 intel_dp->compliance.test_data.bpc = 8;
4564                 break;
4565         default:
4566                 return DP_TEST_NAK;
4567         }
4568
4569         intel_dp->compliance.test_data.video_pattern = test_pattern;
4570         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4571         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4572         /* Set test active flag here so userspace doesn't interrupt things */
4573         intel_dp->compliance.test_active = true;
4574
4575         return DP_TEST_ACK;
4576 }
4577
4578 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4579 {
4580         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4581         u8 test_result = DP_TEST_ACK;
4582         struct intel_connector *intel_connector = intel_dp->attached_connector;
4583         struct drm_connector *connector = &intel_connector->base;
4584
4585         if (intel_connector->detect_edid == NULL ||
4586             connector->edid_corrupt ||
4587             intel_dp->aux.i2c_defer_count > 6) {
4588                 /* Check EDID read for NACKs, DEFERs and corruption
4589                  * (DP CTS 1.2 Core r1.1)
4590                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4591                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4592                  *    4.2.2.6 : EDID corruption detected
4593                  * Use failsafe mode for all cases
4594                  */
4595                 if (intel_dp->aux.i2c_nack_count > 0 ||
4596                         intel_dp->aux.i2c_defer_count > 0)
4597                         drm_dbg_kms(&i915->drm,
4598                                     "EDID read had %d NACKs, %d DEFERs\n",
4599                                     intel_dp->aux.i2c_nack_count,
4600                                     intel_dp->aux.i2c_defer_count);
4601                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4602         } else {
4603                 /* FIXME: Get rid of drm_edid_raw() */
4604                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4605
4606                 /* We have to write the checksum of the last block read */
4607                 block += block->extensions;
4608
4609                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4610                                        block->checksum) <= 0)
4611                         drm_dbg_kms(&i915->drm,
4612                                     "Failed to write EDID checksum\n");
4613
4614                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4615                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4616         }
4617
4618         /* Set test active flag here so userspace doesn't interrupt things */
4619         intel_dp->compliance.test_active = true;
4620
4621         return test_result;
4622 }
4623
4624 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4625                                         const struct intel_crtc_state *crtc_state)
4626 {
4627         struct drm_i915_private *dev_priv =
4628                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4629         struct drm_dp_phy_test_params *data =
4630                         &intel_dp->compliance.test_data.phytest;
4631         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4632         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4633         enum pipe pipe = crtc->pipe;
4634         u32 pattern_val;
4635
4636         switch (data->phy_pattern) {
4637         case DP_LINK_QUAL_PATTERN_DISABLE:
4638                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4639                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4640                 if (DISPLAY_VER(dev_priv) >= 10)
4641                         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4642                                      DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4643                                      DP_TP_CTL_LINK_TRAIN_NORMAL);
4644                 break;
4645         case DP_LINK_QUAL_PATTERN_D10_2:
4646                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4647                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4648                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4649                 break;
4650         case DP_LINK_QUAL_PATTERN_ERROR_RATE:
4651                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4652                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4653                                DDI_DP_COMP_CTL_ENABLE |
4654                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4655                 break;
4656         case DP_LINK_QUAL_PATTERN_PRBS7:
4657                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4658                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4659                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4660                 break;
4661         case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:
4662                 /*
4663                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4664                  * current firmware of DPR-100 could not set it, so hardcoding
4665                  * now for complaince test.
4666                  */
4667                 drm_dbg_kms(&dev_priv->drm,
4668                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4669                 pattern_val = 0x3e0f83e0;
4670                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4671                 pattern_val = 0x0f83e0f8;
4672                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4673                 pattern_val = 0x0000f83e;
4674                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4675                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4676                                DDI_DP_COMP_CTL_ENABLE |
4677                                DDI_DP_COMP_CTL_CUSTOM80);
4678                 break;
4679         case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:
4680                 /*
4681                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4682                  * current firmware of DPR-100 could not set it, so hardcoding
4683                  * now for complaince test.
4684                  */
4685                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4686                 pattern_val = 0xFB;
4687                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4688                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4689                                pattern_val);
4690                 break;
4691         case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:
4692                 if (DISPLAY_VER(dev_priv) < 10)  {
4693                         drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");
4694                         break;
4695                 }
4696                 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");
4697                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4698                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4699                              DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4700                              DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);
4701                 break;
4702         default:
4703                 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");
4704         }
4705 }
4706
4707 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4708                                          const struct intel_crtc_state *crtc_state)
4709 {
4710         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4711         struct drm_dp_phy_test_params *data =
4712                 &intel_dp->compliance.test_data.phytest;
4713         u8 link_status[DP_LINK_STATUS_SIZE];
4714
4715         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4716                                              link_status) < 0) {
4717                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4718                 return;
4719         }
4720
4721         /* retrieve vswing & pre-emphasis setting */
4722         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4723                                   link_status);
4724
4725         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4726
4727         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4728
4729         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4730                           intel_dp->train_set, crtc_state->lane_count);
4731
4732         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4733                                     intel_dp->dpcd[DP_DPCD_REV]);
4734 }
4735
4736 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4737 {
4738         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4739         struct drm_dp_phy_test_params *data =
4740                 &intel_dp->compliance.test_data.phytest;
4741
4742         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4743                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4744                 return DP_TEST_NAK;
4745         }
4746
4747         /* Set test active flag here so userspace doesn't interrupt things */
4748         intel_dp->compliance.test_active = true;
4749
4750         return DP_TEST_ACK;
4751 }
4752
4753 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4754 {
4755         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4756         u8 response = DP_TEST_NAK;
4757         u8 request = 0;
4758         int status;
4759
4760         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4761         if (status <= 0) {
4762                 drm_dbg_kms(&i915->drm,
4763                             "Could not read test request from sink\n");
4764                 goto update_status;
4765         }
4766
4767         switch (request) {
4768         case DP_TEST_LINK_TRAINING:
4769                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4770                 response = intel_dp_autotest_link_training(intel_dp);
4771                 break;
4772         case DP_TEST_LINK_VIDEO_PATTERN:
4773                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4774                 response = intel_dp_autotest_video_pattern(intel_dp);
4775                 break;
4776         case DP_TEST_LINK_EDID_READ:
4777                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4778                 response = intel_dp_autotest_edid(intel_dp);
4779                 break;
4780         case DP_TEST_LINK_PHY_TEST_PATTERN:
4781                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4782                 response = intel_dp_autotest_phy_pattern(intel_dp);
4783                 break;
4784         default:
4785                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4786                             request);
4787                 break;
4788         }
4789
4790         if (response & DP_TEST_ACK)
4791                 intel_dp->compliance.test_type = request;
4792
4793 update_status:
4794         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4795         if (status <= 0)
4796                 drm_dbg_kms(&i915->drm,
4797                             "Could not write test response to sink\n");
4798 }
4799
4800 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4801                              u8 link_status[DP_LINK_STATUS_SIZE])
4802 {
4803         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4804         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4805         bool uhbr = intel_dp->link_rate >= 1000000;
4806         bool ok;
4807
4808         if (uhbr)
4809                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4810                                                           intel_dp->lane_count);
4811         else
4812                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4813
4814         if (ok)
4815                 return true;
4816
4817         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4818         drm_dbg_kms(&i915->drm,
4819                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4820                     encoder->base.base.id, encoder->base.name,
4821                     uhbr ? "128b/132b" : "8b/10b");
4822
4823         return false;
4824 }
4825
4826 static void
4827 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4828 {
4829         bool handled = false;
4830
4831         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4832
4833         if (esi[1] & DP_CP_IRQ) {
4834                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4835                 ack[1] |= DP_CP_IRQ;
4836         }
4837 }
4838
4839 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4840 {
4841         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4842         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4843         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4844         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4845
4846         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4847                              esi_link_status_size) != esi_link_status_size) {
4848                 drm_err(&i915->drm,
4849                         "[ENCODER:%d:%s] Failed to read link status\n",
4850                         encoder->base.base.id, encoder->base.name);
4851                 return false;
4852         }
4853
4854         return intel_dp_link_ok(intel_dp, link_status);
4855 }
4856
4857 /**
4858  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4859  * @intel_dp: Intel DP struct
4860  *
4861  * Read any pending MST interrupts, call MST core to handle these and ack the
4862  * interrupts. Check if the main and AUX link state is ok.
4863  *
4864  * Returns:
4865  * - %true if pending interrupts were serviced (or no interrupts were
4866  *   pending) w/o detecting an error condition.
4867  * - %false if an error condition - like AUX failure or a loss of link - is
4868  *   detected, which needs servicing from the hotplug work.
4869  */
4870 static bool
4871 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4872 {
4873         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4874         bool link_ok = true;
4875
4876         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4877
4878         for (;;) {
4879                 u8 esi[4] = {};
4880                 u8 ack[4] = {};
4881
4882                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4883                         drm_dbg_kms(&i915->drm,
4884                                     "failed to get ESI - device may have failed\n");
4885                         link_ok = false;
4886
4887                         break;
4888                 }
4889
4890                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4891
4892                 if (intel_dp->active_mst_links > 0 && link_ok &&
4893                     esi[3] & LINK_STATUS_CHANGED) {
4894                         if (!intel_dp_mst_link_status(intel_dp))
4895                                 link_ok = false;
4896                         ack[3] |= LINK_STATUS_CHANGED;
4897                 }
4898
4899                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4900
4901                 if (!memchr_inv(ack, 0, sizeof(ack)))
4902                         break;
4903
4904                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4905                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4906
4907                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4908                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4909         }
4910
4911         return link_ok;
4912 }
4913
4914 static void
4915 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4916 {
4917         bool is_active;
4918         u8 buf = 0;
4919
4920         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4921         if (intel_dp->frl.is_trained && !is_active) {
4922                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4923                         return;
4924
4925                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4926                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4927                         return;
4928
4929                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4930
4931                 intel_dp->frl.is_trained = false;
4932
4933                 /* Restart FRL training or fall back to TMDS mode */
4934                 intel_dp_check_frl_training(intel_dp);
4935         }
4936 }
4937
4938 static bool
4939 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4940 {
4941         u8 link_status[DP_LINK_STATUS_SIZE];
4942
4943         if (!intel_dp->link_trained)
4944                 return false;
4945
4946         /*
4947          * While PSR source HW is enabled, it will control main-link sending
4948          * frames, enabling and disabling it so trying to do a retrain will fail
4949          * as the link would or not be on or it could mix training patterns
4950          * and frame data at the same time causing retrain to fail.
4951          * Also when exiting PSR, HW will retrain the link anyways fixing
4952          * any link status error.
4953          */
4954         if (intel_psr_enabled(intel_dp))
4955                 return false;
4956
4957         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4958                                              link_status) < 0)
4959                 return false;
4960
4961         /*
4962          * Validate the cached values of intel_dp->link_rate and
4963          * intel_dp->lane_count before attempting to retrain.
4964          *
4965          * FIXME would be nice to user the crtc state here, but since
4966          * we need to call this from the short HPD handler that seems
4967          * a bit hard.
4968          */
4969         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4970                                         intel_dp->lane_count))
4971                 return false;
4972
4973         /* Retrain if link not ok */
4974         return !intel_dp_link_ok(intel_dp, link_status);
4975 }
4976
4977 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4978                                    const struct drm_connector_state *conn_state)
4979 {
4980         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4981         struct intel_encoder *encoder;
4982         enum pipe pipe;
4983
4984         if (!conn_state->best_encoder)
4985                 return false;
4986
4987         /* SST */
4988         encoder = &dp_to_dig_port(intel_dp)->base;
4989         if (conn_state->best_encoder == &encoder->base)
4990                 return true;
4991
4992         /* MST */
4993         for_each_pipe(i915, pipe) {
4994                 encoder = &intel_dp->mst_encoders[pipe]->base;
4995                 if (conn_state->best_encoder == &encoder->base)
4996                         return true;
4997         }
4998
4999         return false;
5000 }
5001
5002 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5003                               struct drm_modeset_acquire_ctx *ctx,
5004                               u8 *pipe_mask)
5005 {
5006         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5007         struct drm_connector_list_iter conn_iter;
5008         struct intel_connector *connector;
5009         int ret = 0;
5010
5011         *pipe_mask = 0;
5012
5013         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5014         for_each_intel_connector_iter(connector, &conn_iter) {
5015                 struct drm_connector_state *conn_state =
5016                         connector->base.state;
5017                 struct intel_crtc_state *crtc_state;
5018                 struct intel_crtc *crtc;
5019
5020                 if (!intel_dp_has_connector(intel_dp, conn_state))
5021                         continue;
5022
5023                 crtc = to_intel_crtc(conn_state->crtc);
5024                 if (!crtc)
5025                         continue;
5026
5027                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5028                 if (ret)
5029                         break;
5030
5031                 crtc_state = to_intel_crtc_state(crtc->base.state);
5032
5033                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5034
5035                 if (!crtc_state->hw.active)
5036                         continue;
5037
5038                 if (conn_state->commit &&
5039                     !try_wait_for_completion(&conn_state->commit->hw_done))
5040                         continue;
5041
5042                 *pipe_mask |= BIT(crtc->pipe);
5043         }
5044         drm_connector_list_iter_end(&conn_iter);
5045
5046         return ret;
5047 }
5048
5049 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5050 {
5051         struct intel_connector *connector = intel_dp->attached_connector;
5052
5053         return connector->base.status == connector_status_connected ||
5054                 intel_dp->is_mst;
5055 }
5056
5057 int intel_dp_retrain_link(struct intel_encoder *encoder,
5058                           struct drm_modeset_acquire_ctx *ctx)
5059 {
5060         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5061         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5062         struct intel_crtc *crtc;
5063         u8 pipe_mask;
5064         int ret;
5065
5066         if (!intel_dp_is_connected(intel_dp))
5067                 return 0;
5068
5069         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5070                                ctx);
5071         if (ret)
5072                 return ret;
5073
5074         if (!intel_dp_needs_link_retrain(intel_dp))
5075                 return 0;
5076
5077         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5078         if (ret)
5079                 return ret;
5080
5081         if (pipe_mask == 0)
5082                 return 0;
5083
5084         if (!intel_dp_needs_link_retrain(intel_dp))
5085                 return 0;
5086
5087         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5088                     encoder->base.base.id, encoder->base.name);
5089
5090         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5091                 const struct intel_crtc_state *crtc_state =
5092                         to_intel_crtc_state(crtc->base.state);
5093
5094                 /* Suppress underruns caused by re-training */
5095                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5096                 if (crtc_state->has_pch_encoder)
5097                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5098                                                               intel_crtc_pch_transcoder(crtc), false);
5099         }
5100
5101         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5102                 const struct intel_crtc_state *crtc_state =
5103                         to_intel_crtc_state(crtc->base.state);
5104
5105                 /* retrain on the MST master transcoder */
5106                 if (DISPLAY_VER(dev_priv) >= 12 &&
5107                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5108                     !intel_dp_mst_is_master_trans(crtc_state))
5109                         continue;
5110
5111                 intel_dp_check_frl_training(intel_dp);
5112                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5113                 intel_dp_start_link_train(intel_dp, crtc_state);
5114                 intel_dp_stop_link_train(intel_dp, crtc_state);
5115                 break;
5116         }
5117
5118         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5119                 const struct intel_crtc_state *crtc_state =
5120                         to_intel_crtc_state(crtc->base.state);
5121
5122                 /* Keep underrun reporting disabled until things are stable */
5123                 intel_crtc_wait_for_next_vblank(crtc);
5124
5125                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5126                 if (crtc_state->has_pch_encoder)
5127                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5128                                                               intel_crtc_pch_transcoder(crtc), true);
5129         }
5130
5131         return 0;
5132 }
5133
5134 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5135                                   struct drm_modeset_acquire_ctx *ctx,
5136                                   u8 *pipe_mask)
5137 {
5138         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5139         struct drm_connector_list_iter conn_iter;
5140         struct intel_connector *connector;
5141         int ret = 0;
5142
5143         *pipe_mask = 0;
5144
5145         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5146         for_each_intel_connector_iter(connector, &conn_iter) {
5147                 struct drm_connector_state *conn_state =
5148                         connector->base.state;
5149                 struct intel_crtc_state *crtc_state;
5150                 struct intel_crtc *crtc;
5151
5152                 if (!intel_dp_has_connector(intel_dp, conn_state))
5153                         continue;
5154
5155                 crtc = to_intel_crtc(conn_state->crtc);
5156                 if (!crtc)
5157                         continue;
5158
5159                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5160                 if (ret)
5161                         break;
5162
5163                 crtc_state = to_intel_crtc_state(crtc->base.state);
5164
5165                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5166
5167                 if (!crtc_state->hw.active)
5168                         continue;
5169
5170                 if (conn_state->commit &&
5171                     !try_wait_for_completion(&conn_state->commit->hw_done))
5172                         continue;
5173
5174                 *pipe_mask |= BIT(crtc->pipe);
5175         }
5176         drm_connector_list_iter_end(&conn_iter);
5177
5178         return ret;
5179 }
5180
5181 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5182                                 struct drm_modeset_acquire_ctx *ctx)
5183 {
5184         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5185         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5186         struct intel_crtc *crtc;
5187         u8 pipe_mask;
5188         int ret;
5189
5190         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5191                                ctx);
5192         if (ret)
5193                 return ret;
5194
5195         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5196         if (ret)
5197                 return ret;
5198
5199         if (pipe_mask == 0)
5200                 return 0;
5201
5202         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5203                     encoder->base.base.id, encoder->base.name);
5204
5205         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5206                 const struct intel_crtc_state *crtc_state =
5207                         to_intel_crtc_state(crtc->base.state);
5208
5209                 /* test on the MST master transcoder */
5210                 if (DISPLAY_VER(dev_priv) >= 12 &&
5211                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5212                     !intel_dp_mst_is_master_trans(crtc_state))
5213                         continue;
5214
5215                 intel_dp_process_phy_request(intel_dp, crtc_state);
5216                 break;
5217         }
5218
5219         return 0;
5220 }
5221
5222 void intel_dp_phy_test(struct intel_encoder *encoder)
5223 {
5224         struct drm_modeset_acquire_ctx ctx;
5225         int ret;
5226
5227         drm_modeset_acquire_init(&ctx, 0);
5228
5229         for (;;) {
5230                 ret = intel_dp_do_phy_test(encoder, &ctx);
5231
5232                 if (ret == -EDEADLK) {
5233                         drm_modeset_backoff(&ctx);
5234                         continue;
5235                 }
5236
5237                 break;
5238         }
5239
5240         drm_modeset_drop_locks(&ctx);
5241         drm_modeset_acquire_fini(&ctx);
5242         drm_WARN(encoder->base.dev, ret,
5243                  "Acquiring modeset locks failed with %i\n", ret);
5244 }
5245
5246 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5247 {
5248         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5249         u8 val;
5250
5251         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5252                 return;
5253
5254         if (drm_dp_dpcd_readb(&intel_dp->aux,
5255                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5256                 return;
5257
5258         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5259
5260         if (val & DP_AUTOMATED_TEST_REQUEST)
5261                 intel_dp_handle_test_request(intel_dp);
5262
5263         if (val & DP_CP_IRQ)
5264                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5265
5266         if (val & DP_SINK_SPECIFIC_IRQ)
5267                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5268 }
5269
5270 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5271 {
5272         u8 val;
5273
5274         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5275                 return;
5276
5277         if (drm_dp_dpcd_readb(&intel_dp->aux,
5278                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5279                 return;
5280
5281         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5282                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5283                 return;
5284
5285         if (val & HDMI_LINK_STATUS_CHANGED)
5286                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5287 }
5288
5289 /*
5290  * According to DP spec
5291  * 5.1.2:
5292  *  1. Read DPCD
5293  *  2. Configure link according to Receiver Capabilities
5294  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5295  *  4. Check link status on receipt of hot-plug interrupt
5296  *
5297  * intel_dp_short_pulse -  handles short pulse interrupts
5298  * when full detection is not required.
5299  * Returns %true if short pulse is handled and full detection
5300  * is NOT required and %false otherwise.
5301  */
5302 static bool
5303 intel_dp_short_pulse(struct intel_dp *intel_dp)
5304 {
5305         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5306         u8 old_sink_count = intel_dp->sink_count;
5307         bool ret;
5308
5309         /*
5310          * Clearing compliance test variables to allow capturing
5311          * of values for next automated test request.
5312          */
5313         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5314
5315         /*
5316          * Now read the DPCD to see if it's actually running
5317          * If the current value of sink count doesn't match with
5318          * the value that was stored earlier or dpcd read failed
5319          * we need to do full detection
5320          */
5321         ret = intel_dp_get_dpcd(intel_dp);
5322
5323         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5324                 /* No need to proceed if we are going to do full detect */
5325                 return false;
5326         }
5327
5328         intel_dp_check_device_service_irq(intel_dp);
5329         intel_dp_check_link_service_irq(intel_dp);
5330
5331         /* Handle CEC interrupts, if any */
5332         drm_dp_cec_irq(&intel_dp->aux);
5333
5334         /* defer to the hotplug work for link retraining if needed */
5335         if (intel_dp_needs_link_retrain(intel_dp))
5336                 return false;
5337
5338         intel_psr_short_pulse(intel_dp);
5339
5340         switch (intel_dp->compliance.test_type) {
5341         case DP_TEST_LINK_TRAINING:
5342                 drm_dbg_kms(&dev_priv->drm,
5343                             "Link Training Compliance Test requested\n");
5344                 /* Send a Hotplug Uevent to userspace to start modeset */
5345                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5346                 break;
5347         case DP_TEST_LINK_PHY_TEST_PATTERN:
5348                 drm_dbg_kms(&dev_priv->drm,
5349                             "PHY test pattern Compliance Test requested\n");
5350                 /*
5351                  * Schedule long hpd to do the test
5352                  *
5353                  * FIXME get rid of the ad-hoc phy test modeset code
5354                  * and properly incorporate it into the normal modeset.
5355                  */
5356                 return false;
5357         }
5358
5359         return true;
5360 }
5361
5362 /* XXX this is probably wrong for multiple downstream ports */
5363 static enum drm_connector_status
5364 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5365 {
5366         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5367         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5368         u8 *dpcd = intel_dp->dpcd;
5369         u8 type;
5370
5371         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5372                 return connector_status_connected;
5373
5374         lspcon_resume(dig_port);
5375
5376         if (!intel_dp_get_dpcd(intel_dp))
5377                 return connector_status_disconnected;
5378
5379         /* if there's no downstream port, we're done */
5380         if (!drm_dp_is_branch(dpcd))
5381                 return connector_status_connected;
5382
5383         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5384         if (intel_dp_has_sink_count(intel_dp) &&
5385             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5386                 return intel_dp->sink_count ?
5387                 connector_status_connected : connector_status_disconnected;
5388         }
5389
5390         if (intel_dp_can_mst(intel_dp))
5391                 return connector_status_connected;
5392
5393         /* If no HPD, poke DDC gently */
5394         if (drm_probe_ddc(&intel_dp->aux.ddc))
5395                 return connector_status_connected;
5396
5397         /* Well we tried, say unknown for unreliable port types */
5398         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5399                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5400                 if (type == DP_DS_PORT_TYPE_VGA ||
5401                     type == DP_DS_PORT_TYPE_NON_EDID)
5402                         return connector_status_unknown;
5403         } else {
5404                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5405                         DP_DWN_STRM_PORT_TYPE_MASK;
5406                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5407                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5408                         return connector_status_unknown;
5409         }
5410
5411         /* Anything else is out of spec, warn and ignore */
5412         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5413         return connector_status_disconnected;
5414 }
5415
5416 static enum drm_connector_status
5417 edp_detect(struct intel_dp *intel_dp)
5418 {
5419         return connector_status_connected;
5420 }
5421
5422 void intel_digital_port_lock(struct intel_encoder *encoder)
5423 {
5424         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5425
5426         if (dig_port->lock)
5427                 dig_port->lock(dig_port);
5428 }
5429
5430 void intel_digital_port_unlock(struct intel_encoder *encoder)
5431 {
5432         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5433
5434         if (dig_port->unlock)
5435                 dig_port->unlock(dig_port);
5436 }
5437
5438 /*
5439  * intel_digital_port_connected_locked - is the specified port connected?
5440  * @encoder: intel_encoder
5441  *
5442  * In cases where there's a connector physically connected but it can't be used
5443  * by our hardware we also return false, since the rest of the driver should
5444  * pretty much treat the port as disconnected. This is relevant for type-C
5445  * (starting on ICL) where there's ownership involved.
5446  *
5447  * The caller must hold the lock acquired by calling intel_digital_port_lock()
5448  * when calling this function.
5449  *
5450  * Return %true if port is connected, %false otherwise.
5451  */
5452 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5453 {
5454         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5455         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5456         bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5457         bool is_connected = false;
5458         intel_wakeref_t wakeref;
5459
5460         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5461                 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5462
5463                 do {
5464                         is_connected = dig_port->connected(encoder);
5465                         if (is_connected || is_glitch_free)
5466                                 break;
5467                         usleep_range(10, 30);
5468                 } while (time_before(jiffies, wait_expires));
5469         }
5470
5471         return is_connected;
5472 }
5473
5474 bool intel_digital_port_connected(struct intel_encoder *encoder)
5475 {
5476         bool ret;
5477
5478         intel_digital_port_lock(encoder);
5479         ret = intel_digital_port_connected_locked(encoder);
5480         intel_digital_port_unlock(encoder);
5481
5482         return ret;
5483 }
5484
5485 static const struct drm_edid *
5486 intel_dp_get_edid(struct intel_dp *intel_dp)
5487 {
5488         struct intel_connector *connector = intel_dp->attached_connector;
5489         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5490
5491         /* Use panel fixed edid if we have one */
5492         if (fixed_edid) {
5493                 /* invalid edid */
5494                 if (IS_ERR(fixed_edid))
5495                         return NULL;
5496
5497                 return drm_edid_dup(fixed_edid);
5498         }
5499
5500         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5501 }
5502
5503 static void
5504 intel_dp_update_dfp(struct intel_dp *intel_dp,
5505                     const struct drm_edid *drm_edid)
5506 {
5507         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5508         struct intel_connector *connector = intel_dp->attached_connector;
5509
5510         intel_dp->dfp.max_bpc =
5511                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5512                                           intel_dp->downstream_ports, drm_edid);
5513
5514         intel_dp->dfp.max_dotclock =
5515                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5516                                                intel_dp->downstream_ports);
5517
5518         intel_dp->dfp.min_tmds_clock =
5519                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5520                                                  intel_dp->downstream_ports,
5521                                                  drm_edid);
5522         intel_dp->dfp.max_tmds_clock =
5523                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5524                                                  intel_dp->downstream_ports,
5525                                                  drm_edid);
5526
5527         intel_dp->dfp.pcon_max_frl_bw =
5528                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5529                                            intel_dp->downstream_ports);
5530
5531         drm_dbg_kms(&i915->drm,
5532                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5533                     connector->base.base.id, connector->base.name,
5534                     intel_dp->dfp.max_bpc,
5535                     intel_dp->dfp.max_dotclock,
5536                     intel_dp->dfp.min_tmds_clock,
5537                     intel_dp->dfp.max_tmds_clock,
5538                     intel_dp->dfp.pcon_max_frl_bw);
5539
5540         intel_dp_get_pcon_dsc_cap(intel_dp);
5541 }
5542
5543 static bool
5544 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5545 {
5546         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5547             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5548                 return true;
5549
5550         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5551             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5552                 return true;
5553
5554         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5555             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5556                 return true;
5557
5558         return false;
5559 }
5560
5561 static void
5562 intel_dp_update_420(struct intel_dp *intel_dp)
5563 {
5564         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5565         struct intel_connector *connector = intel_dp->attached_connector;
5566
5567         intel_dp->dfp.ycbcr420_passthrough =
5568                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5569                                                   intel_dp->downstream_ports);
5570         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5571         intel_dp->dfp.ycbcr_444_to_420 =
5572                 dp_to_dig_port(intel_dp)->lspcon.active ||
5573                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5574                                                         intel_dp->downstream_ports);
5575         intel_dp->dfp.rgb_to_ycbcr =
5576                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5577                                                           intel_dp->downstream_ports,
5578                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5579
5580         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5581
5582         drm_dbg_kms(&i915->drm,
5583                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5584                     connector->base.base.id, connector->base.name,
5585                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5586                     str_yes_no(connector->base.ycbcr_420_allowed),
5587                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5588 }
5589
5590 static void
5591 intel_dp_set_edid(struct intel_dp *intel_dp)
5592 {
5593         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5594         struct intel_connector *connector = intel_dp->attached_connector;
5595         const struct drm_edid *drm_edid;
5596         bool vrr_capable;
5597
5598         intel_dp_unset_edid(intel_dp);
5599         drm_edid = intel_dp_get_edid(intel_dp);
5600         connector->detect_edid = drm_edid;
5601
5602         /* Below we depend on display info having been updated */
5603         drm_edid_connector_update(&connector->base, drm_edid);
5604
5605         vrr_capable = intel_vrr_is_capable(connector);
5606         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5607                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5608         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5609
5610         intel_dp_update_dfp(intel_dp, drm_edid);
5611         intel_dp_update_420(intel_dp);
5612
5613         drm_dp_cec_attach(&intel_dp->aux,
5614                           connector->base.display_info.source_physical_address);
5615 }
5616
5617 static void
5618 intel_dp_unset_edid(struct intel_dp *intel_dp)
5619 {
5620         struct intel_connector *connector = intel_dp->attached_connector;
5621
5622         drm_dp_cec_unset_edid(&intel_dp->aux);
5623         drm_edid_free(connector->detect_edid);
5624         connector->detect_edid = NULL;
5625
5626         intel_dp->dfp.max_bpc = 0;
5627         intel_dp->dfp.max_dotclock = 0;
5628         intel_dp->dfp.min_tmds_clock = 0;
5629         intel_dp->dfp.max_tmds_clock = 0;
5630
5631         intel_dp->dfp.pcon_max_frl_bw = 0;
5632
5633         intel_dp->dfp.ycbcr_444_to_420 = false;
5634         connector->base.ycbcr_420_allowed = false;
5635
5636         drm_connector_set_vrr_capable_property(&connector->base,
5637                                                false);
5638 }
5639
5640 static void
5641 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5642 {
5643         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5644
5645         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5646         if (!HAS_DSC(i915))
5647                 return;
5648
5649         if (intel_dp_is_edp(intel_dp))
5650                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5651                                            connector);
5652         else
5653                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5654                                           connector);
5655 }
5656
5657 static int
5658 intel_dp_detect(struct drm_connector *connector,
5659                 struct drm_modeset_acquire_ctx *ctx,
5660                 bool force)
5661 {
5662         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5663         struct intel_connector *intel_connector =
5664                 to_intel_connector(connector);
5665         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5666         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5667         struct intel_encoder *encoder = &dig_port->base;
5668         enum drm_connector_status status;
5669
5670         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5671                     connector->base.id, connector->name);
5672         drm_WARN_ON(&dev_priv->drm,
5673                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5674
5675         if (!intel_display_device_enabled(dev_priv))
5676                 return connector_status_disconnected;
5677
5678         if (!intel_display_driver_check_access(dev_priv))
5679                 return connector->status;
5680
5681         /* Can't disconnect eDP */
5682         if (intel_dp_is_edp(intel_dp))
5683                 status = edp_detect(intel_dp);
5684         else if (intel_digital_port_connected(encoder))
5685                 status = intel_dp_detect_dpcd(intel_dp);
5686         else
5687                 status = connector_status_disconnected;
5688
5689         if (status == connector_status_disconnected) {
5690                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5691                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5692                 intel_dp->psr.sink_panel_replay_support = false;
5693
5694                 if (intel_dp->is_mst) {
5695                         drm_dbg_kms(&dev_priv->drm,
5696                                     "MST device may have disappeared %d vs %d\n",
5697                                     intel_dp->is_mst,
5698                                     intel_dp->mst_mgr.mst_state);
5699                         intel_dp->is_mst = false;
5700                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5701                                                         intel_dp->is_mst);
5702                 }
5703
5704                 goto out;
5705         }
5706
5707         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5708
5709         intel_dp_configure_mst(intel_dp);
5710
5711         /*
5712          * TODO: Reset link params when switching to MST mode, until MST
5713          * supports link training fallback params.
5714          */
5715         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5716                 intel_dp_reset_max_link_params(intel_dp);
5717                 intel_dp->reset_link_params = false;
5718         }
5719
5720         intel_dp_print_rates(intel_dp);
5721
5722         if (intel_dp->is_mst) {
5723                 /*
5724                  * If we are in MST mode then this connector
5725                  * won't appear connected or have anything
5726                  * with EDID on it
5727                  */
5728                 status = connector_status_disconnected;
5729                 goto out;
5730         }
5731
5732         /*
5733          * Some external monitors do not signal loss of link synchronization
5734          * with an IRQ_HPD, so force a link status check.
5735          */
5736         if (!intel_dp_is_edp(intel_dp)) {
5737                 int ret;
5738
5739                 ret = intel_dp_retrain_link(encoder, ctx);
5740                 if (ret)
5741                         return ret;
5742         }
5743
5744         /*
5745          * Clearing NACK and defer counts to get their exact values
5746          * while reading EDID which are required by Compliance tests
5747          * 4.2.2.4 and 4.2.2.5
5748          */
5749         intel_dp->aux.i2c_nack_count = 0;
5750         intel_dp->aux.i2c_defer_count = 0;
5751
5752         intel_dp_set_edid(intel_dp);
5753         if (intel_dp_is_edp(intel_dp) ||
5754             to_intel_connector(connector)->detect_edid)
5755                 status = connector_status_connected;
5756
5757         intel_dp_check_device_service_irq(intel_dp);
5758
5759 out:
5760         if (status != connector_status_connected && !intel_dp->is_mst)
5761                 intel_dp_unset_edid(intel_dp);
5762
5763         if (!intel_dp_is_edp(intel_dp))
5764                 drm_dp_set_subconnector_property(connector,
5765                                                  status,
5766                                                  intel_dp->dpcd,
5767                                                  intel_dp->downstream_ports);
5768         return status;
5769 }
5770
5771 static void
5772 intel_dp_force(struct drm_connector *connector)
5773 {
5774         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5775         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5776         struct intel_encoder *intel_encoder = &dig_port->base;
5777         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5778
5779         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5780                     connector->base.id, connector->name);
5781
5782         if (!intel_display_driver_check_access(dev_priv))
5783                 return;
5784
5785         intel_dp_unset_edid(intel_dp);
5786
5787         if (connector->status != connector_status_connected)
5788                 return;
5789
5790         intel_dp_set_edid(intel_dp);
5791 }
5792
5793 static int intel_dp_get_modes(struct drm_connector *connector)
5794 {
5795         struct intel_connector *intel_connector = to_intel_connector(connector);
5796         int num_modes;
5797
5798         /* drm_edid_connector_update() done in ->detect() or ->force() */
5799         num_modes = drm_edid_connector_add_modes(connector);
5800
5801         /* Also add fixed mode, which may or may not be present in EDID */
5802         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5803                 num_modes += intel_panel_get_modes(intel_connector);
5804
5805         if (num_modes)
5806                 return num_modes;
5807
5808         if (!intel_connector->detect_edid) {
5809                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5810                 struct drm_display_mode *mode;
5811
5812                 mode = drm_dp_downstream_mode(connector->dev,
5813                                               intel_dp->dpcd,
5814                                               intel_dp->downstream_ports);
5815                 if (mode) {
5816                         drm_mode_probed_add(connector, mode);
5817                         num_modes++;
5818                 }
5819         }
5820
5821         return num_modes;
5822 }
5823
5824 static int
5825 intel_dp_connector_register(struct drm_connector *connector)
5826 {
5827         struct drm_i915_private *i915 = to_i915(connector->dev);
5828         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5829         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5830         struct intel_lspcon *lspcon = &dig_port->lspcon;
5831         int ret;
5832
5833         ret = intel_connector_register(connector);
5834         if (ret)
5835                 return ret;
5836
5837         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5838                     intel_dp->aux.name, connector->kdev->kobj.name);
5839
5840         intel_dp->aux.dev = connector->kdev;
5841         ret = drm_dp_aux_register(&intel_dp->aux);
5842         if (!ret)
5843                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5844
5845         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5846                 return ret;
5847
5848         /*
5849          * ToDo: Clean this up to handle lspcon init and resume more
5850          * efficiently and streamlined.
5851          */
5852         if (lspcon_init(dig_port)) {
5853                 lspcon_detect_hdr_capability(lspcon);
5854                 if (lspcon->hdr_supported)
5855                         drm_connector_attach_hdr_output_metadata_property(connector);
5856         }
5857
5858         return ret;
5859 }
5860
5861 static void
5862 intel_dp_connector_unregister(struct drm_connector *connector)
5863 {
5864         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5865
5866         drm_dp_cec_unregister_connector(&intel_dp->aux);
5867         drm_dp_aux_unregister(&intel_dp->aux);
5868         intel_connector_unregister(connector);
5869 }
5870
5871 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5872 {
5873         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5874         struct intel_dp *intel_dp = &dig_port->dp;
5875
5876         intel_dp_mst_encoder_cleanup(dig_port);
5877
5878         intel_pps_vdd_off_sync(intel_dp);
5879
5880         /*
5881          * Ensure power off delay is respected on module remove, so that we can
5882          * reduce delays at driver probe. See pps_init_timestamps().
5883          */
5884         intel_pps_wait_power_cycle(intel_dp);
5885
5886         intel_dp_aux_fini(intel_dp);
5887 }
5888
5889 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5890 {
5891         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5892
5893         intel_pps_vdd_off_sync(intel_dp);
5894 }
5895
5896 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5897 {
5898         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5899
5900         intel_pps_wait_power_cycle(intel_dp);
5901 }
5902
5903 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5904                                     int tile_group_id)
5905 {
5906         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5907         struct drm_connector_list_iter conn_iter;
5908         struct drm_connector *connector;
5909         int ret = 0;
5910
5911         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5912         drm_for_each_connector_iter(connector, &conn_iter) {
5913                 struct drm_connector_state *conn_state;
5914                 struct intel_crtc_state *crtc_state;
5915                 struct intel_crtc *crtc;
5916
5917                 if (!connector->has_tile ||
5918                     connector->tile_group->id != tile_group_id)
5919                         continue;
5920
5921                 conn_state = drm_atomic_get_connector_state(&state->base,
5922                                                             connector);
5923                 if (IS_ERR(conn_state)) {
5924                         ret = PTR_ERR(conn_state);
5925                         break;
5926                 }
5927
5928                 crtc = to_intel_crtc(conn_state->crtc);
5929
5930                 if (!crtc)
5931                         continue;
5932
5933                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5934                 crtc_state->uapi.mode_changed = true;
5935
5936                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5937                 if (ret)
5938                         break;
5939         }
5940         drm_connector_list_iter_end(&conn_iter);
5941
5942         return ret;
5943 }
5944
5945 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5946 {
5947         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5948         struct intel_crtc *crtc;
5949
5950         if (transcoders == 0)
5951                 return 0;
5952
5953         for_each_intel_crtc(&dev_priv->drm, crtc) {
5954                 struct intel_crtc_state *crtc_state;
5955                 int ret;
5956
5957                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5958                 if (IS_ERR(crtc_state))
5959                         return PTR_ERR(crtc_state);
5960
5961                 if (!crtc_state->hw.enable)
5962                         continue;
5963
5964                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5965                         continue;
5966
5967                 crtc_state->uapi.mode_changed = true;
5968
5969                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5970                 if (ret)
5971                         return ret;
5972
5973                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5974                 if (ret)
5975                         return ret;
5976
5977                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5978         }
5979
5980         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5981
5982         return 0;
5983 }
5984
5985 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5986                                       struct drm_connector *connector)
5987 {
5988         const struct drm_connector_state *old_conn_state =
5989                 drm_atomic_get_old_connector_state(&state->base, connector);
5990         const struct intel_crtc_state *old_crtc_state;
5991         struct intel_crtc *crtc;
5992         u8 transcoders;
5993
5994         crtc = to_intel_crtc(old_conn_state->crtc);
5995         if (!crtc)
5996                 return 0;
5997
5998         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5999
6000         if (!old_crtc_state->hw.active)
6001                 return 0;
6002
6003         transcoders = old_crtc_state->sync_mode_slaves_mask;
6004         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6005                 transcoders |= BIT(old_crtc_state->master_transcoder);
6006
6007         return intel_modeset_affected_transcoders(state,
6008                                                   transcoders);
6009 }
6010
6011 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6012                                            struct drm_atomic_state *_state)
6013 {
6014         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6015         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6016         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6017         struct intel_connector *intel_conn = to_intel_connector(conn);
6018         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6019         int ret;
6020
6021         ret = intel_digital_connector_atomic_check(conn, &state->base);
6022         if (ret)
6023                 return ret;
6024
6025         if (intel_dp_mst_source_support(intel_dp)) {
6026                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6027                 if (ret)
6028                         return ret;
6029         }
6030
6031         /*
6032          * We don't enable port sync on BDW due to missing w/as and
6033          * due to not having adjusted the modeset sequence appropriately.
6034          */
6035         if (DISPLAY_VER(dev_priv) < 9)
6036                 return 0;
6037
6038         if (!intel_connector_needs_modeset(state, conn))
6039                 return 0;
6040
6041         if (conn->has_tile) {
6042                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6043                 if (ret)
6044                         return ret;
6045         }
6046
6047         return intel_modeset_synced_crtcs(state, conn);
6048 }
6049
6050 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6051                                        enum drm_connector_status hpd_state)
6052 {
6053         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6054         struct drm_i915_private *i915 = to_i915(connector->dev);
6055         bool hpd_high = hpd_state == connector_status_connected;
6056         unsigned int hpd_pin = encoder->hpd_pin;
6057         bool need_work = false;
6058
6059         spin_lock_irq(&i915->irq_lock);
6060         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6061                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6062
6063                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6064                 need_work = true;
6065         }
6066         spin_unlock_irq(&i915->irq_lock);
6067
6068         if (need_work)
6069                 intel_hpd_schedule_detection(i915);
6070 }
6071
6072 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6073         .force = intel_dp_force,
6074         .fill_modes = drm_helper_probe_single_connector_modes,
6075         .atomic_get_property = intel_digital_connector_atomic_get_property,
6076         .atomic_set_property = intel_digital_connector_atomic_set_property,
6077         .late_register = intel_dp_connector_register,
6078         .early_unregister = intel_dp_connector_unregister,
6079         .destroy = intel_connector_destroy,
6080         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6081         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6082         .oob_hotplug_event = intel_dp_oob_hotplug_event,
6083 };
6084
6085 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6086         .detect_ctx = intel_dp_detect,
6087         .get_modes = intel_dp_get_modes,
6088         .mode_valid = intel_dp_mode_valid,
6089         .atomic_check = intel_dp_connector_atomic_check,
6090 };
6091
6092 enum irqreturn
6093 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6094 {
6095         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6096         struct intel_dp *intel_dp = &dig_port->dp;
6097
6098         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6099             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6100                 /*
6101                  * vdd off can generate a long/short pulse on eDP which
6102                  * would require vdd on to handle it, and thus we
6103                  * would end up in an endless cycle of
6104                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6105                  */
6106                 drm_dbg_kms(&i915->drm,
6107                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6108                             long_hpd ? "long" : "short",
6109                             dig_port->base.base.base.id,
6110                             dig_port->base.base.name);
6111                 return IRQ_HANDLED;
6112         }
6113
6114         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6115                     dig_port->base.base.base.id,
6116                     dig_port->base.base.name,
6117                     long_hpd ? "long" : "short");
6118
6119         if (long_hpd) {
6120                 intel_dp->reset_link_params = true;
6121                 return IRQ_NONE;
6122         }
6123
6124         if (intel_dp->is_mst) {
6125                 if (!intel_dp_check_mst_status(intel_dp))
6126                         return IRQ_NONE;
6127         } else if (!intel_dp_short_pulse(intel_dp)) {
6128                 return IRQ_NONE;
6129         }
6130
6131         return IRQ_HANDLED;
6132 }
6133
6134 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6135                                   const struct intel_bios_encoder_data *devdata,
6136                                   enum port port)
6137 {
6138         /*
6139          * eDP not supported on g4x. so bail out early just
6140          * for a bit extra safety in case the VBT is bonkers.
6141          */
6142         if (DISPLAY_VER(dev_priv) < 5)
6143                 return false;
6144
6145         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6146                 return true;
6147
6148         return devdata && intel_bios_encoder_supports_edp(devdata);
6149 }
6150
6151 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6152 {
6153         const struct intel_bios_encoder_data *devdata =
6154                 intel_bios_encoder_data_lookup(i915, port);
6155
6156         return _intel_dp_is_port_edp(i915, devdata, port);
6157 }
6158
6159 static bool
6160 has_gamut_metadata_dip(struct intel_encoder *encoder)
6161 {
6162         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6163         enum port port = encoder->port;
6164
6165         if (intel_bios_encoder_is_lspcon(encoder->devdata))
6166                 return false;
6167
6168         if (DISPLAY_VER(i915) >= 11)
6169                 return true;
6170
6171         if (port == PORT_A)
6172                 return false;
6173
6174         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6175             DISPLAY_VER(i915) >= 9)
6176                 return true;
6177
6178         return false;
6179 }
6180
6181 static void
6182 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6183 {
6184         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6185         enum port port = dp_to_dig_port(intel_dp)->base.port;
6186
6187         if (!intel_dp_is_edp(intel_dp))
6188                 drm_connector_attach_dp_subconnector_property(connector);
6189
6190         if (!IS_G4X(dev_priv) && port != PORT_A)
6191                 intel_attach_force_audio_property(connector);
6192
6193         intel_attach_broadcast_rgb_property(connector);
6194         if (HAS_GMCH(dev_priv))
6195                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6196         else if (DISPLAY_VER(dev_priv) >= 5)
6197                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6198
6199         /* Register HDMI colorspace for case of lspcon */
6200         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6201                 drm_connector_attach_content_type_property(connector);
6202                 intel_attach_hdmi_colorspace_property(connector);
6203         } else {
6204                 intel_attach_dp_colorspace_property(connector);
6205         }
6206
6207         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6208                 drm_connector_attach_hdr_output_metadata_property(connector);
6209
6210         if (HAS_VRR(dev_priv))
6211                 drm_connector_attach_vrr_capable_property(connector);
6212 }
6213
6214 static void
6215 intel_edp_add_properties(struct intel_dp *intel_dp)
6216 {
6217         struct intel_connector *connector = intel_dp->attached_connector;
6218         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6219         const struct drm_display_mode *fixed_mode =
6220                 intel_panel_preferred_fixed_mode(connector);
6221
6222         intel_attach_scaling_mode_property(&connector->base);
6223
6224         drm_connector_set_panel_orientation_with_quirk(&connector->base,
6225                                                        i915->display.vbt.orientation,
6226                                                        fixed_mode->hdisplay,
6227                                                        fixed_mode->vdisplay);
6228 }
6229
6230 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6231                                       struct intel_connector *connector)
6232 {
6233         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6234         enum pipe pipe = INVALID_PIPE;
6235
6236         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6237                 /*
6238                  * Figure out the current pipe for the initial backlight setup.
6239                  * If the current pipe isn't valid, try the PPS pipe, and if that
6240                  * fails just assume pipe A.
6241                  */
6242                 pipe = vlv_active_pipe(intel_dp);
6243
6244                 if (pipe != PIPE_A && pipe != PIPE_B)
6245                         pipe = intel_dp->pps.pps_pipe;
6246
6247                 if (pipe != PIPE_A && pipe != PIPE_B)
6248                         pipe = PIPE_A;
6249         }
6250
6251         intel_backlight_setup(connector, pipe);
6252 }
6253
6254 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6255                                      struct intel_connector *intel_connector)
6256 {
6257         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6258         struct drm_connector *connector = &intel_connector->base;
6259         struct drm_display_mode *fixed_mode;
6260         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6261         bool has_dpcd;
6262         const struct drm_edid *drm_edid;
6263
6264         if (!intel_dp_is_edp(intel_dp))
6265                 return true;
6266
6267         /*
6268          * On IBX/CPT we may get here with LVDS already registered. Since the
6269          * driver uses the only internal power sequencer available for both
6270          * eDP and LVDS bail out early in this case to prevent interfering
6271          * with an already powered-on LVDS power sequencer.
6272          */
6273         if (intel_get_lvds_encoder(dev_priv)) {
6274                 drm_WARN_ON(&dev_priv->drm,
6275                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6276                 drm_info(&dev_priv->drm,
6277                          "LVDS was detected, not registering eDP\n");
6278
6279                 return false;
6280         }
6281
6282         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6283                                     encoder->devdata);
6284
6285         if (!intel_pps_init(intel_dp)) {
6286                 drm_info(&dev_priv->drm,
6287                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6288                          encoder->base.base.id, encoder->base.name);
6289                 /*
6290                  * The BIOS may have still enabled VDD on the PPS even
6291                  * though it's unusable. Make sure we turn it back off
6292                  * and to release the power domain references/etc.
6293                  */
6294                 goto out_vdd_off;
6295         }
6296
6297         /*
6298          * Enable HPD sense for live status check.
6299          * intel_hpd_irq_setup() will turn it off again
6300          * if it's no longer needed later.
6301          *
6302          * The DPCD probe below will make sure VDD is on.
6303          */
6304         intel_hpd_enable_detection(encoder);
6305
6306         /* Cache DPCD and EDID for edp. */
6307         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6308
6309         if (!has_dpcd) {
6310                 /* if this fails, presume the device is a ghost */
6311                 drm_info(&dev_priv->drm,
6312                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6313                          encoder->base.base.id, encoder->base.name);
6314                 goto out_vdd_off;
6315         }
6316
6317         /*
6318          * VBT and straps are liars. Also check HPD as that seems
6319          * to be the most reliable piece of information available.
6320          *
6321          * ... expect on devices that forgot to hook HPD up for eDP
6322          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6323          * ports are attempting to use the same AUX CH, according to VBT.
6324          */
6325         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6326                 /*
6327                  * If this fails, presume the DPCD answer came
6328                  * from some other port using the same AUX CH.
6329                  *
6330                  * FIXME maybe cleaner to check this before the
6331                  * DPCD read? Would need sort out the VDD handling...
6332                  */
6333                 if (!intel_digital_port_connected(encoder)) {
6334                         drm_info(&dev_priv->drm,
6335                                  "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6336                                  encoder->base.base.id, encoder->base.name);
6337                         goto out_vdd_off;
6338                 }
6339
6340                 /*
6341                  * Unfortunately even the HPD based detection fails on
6342                  * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6343                  * back to checking for a VGA branch device. Only do this
6344                  * on known affected platforms to minimize false positives.
6345                  */
6346                 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6347                     (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6348                     DP_DWN_STRM_PORT_TYPE_ANALOG) {
6349                         drm_info(&dev_priv->drm,
6350                                  "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6351                                  encoder->base.base.id, encoder->base.name);
6352                         goto out_vdd_off;
6353                 }
6354         }
6355
6356         mutex_lock(&dev_priv->drm.mode_config.mutex);
6357         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6358         if (!drm_edid) {
6359                 /* Fallback to EDID from ACPI OpRegion, if any */
6360                 drm_edid = intel_opregion_get_edid(intel_connector);
6361                 if (drm_edid)
6362                         drm_dbg_kms(&dev_priv->drm,
6363                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6364                                     connector->base.id, connector->name);
6365         }
6366         if (drm_edid) {
6367                 if (drm_edid_connector_update(connector, drm_edid) ||
6368                     !drm_edid_connector_add_modes(connector)) {
6369                         drm_edid_connector_update(connector, NULL);
6370                         drm_edid_free(drm_edid);
6371                         drm_edid = ERR_PTR(-EINVAL);
6372                 }
6373         } else {
6374                 drm_edid = ERR_PTR(-ENOENT);
6375         }
6376
6377         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6378                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6379
6380         intel_panel_add_edid_fixed_modes(intel_connector, true);
6381
6382         /* MSO requires information from the EDID */
6383         intel_edp_mso_init(intel_dp);
6384
6385         /* multiply the mode clock and horizontal timings for MSO */
6386         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6387                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6388
6389         /* fallback to VBT if available for eDP */
6390         if (!intel_panel_preferred_fixed_mode(intel_connector))
6391                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6392
6393         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6394
6395         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6396                 drm_info(&dev_priv->drm,
6397                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6398                          encoder->base.base.id, encoder->base.name);
6399                 goto out_vdd_off;
6400         }
6401
6402         intel_panel_init(intel_connector, drm_edid);
6403
6404         intel_edp_backlight_setup(intel_dp, intel_connector);
6405
6406         intel_edp_add_properties(intel_dp);
6407
6408         intel_pps_init_late(intel_dp);
6409
6410         return true;
6411
6412 out_vdd_off:
6413         intel_pps_vdd_off_sync(intel_dp);
6414
6415         return false;
6416 }
6417
6418 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6419 {
6420         struct intel_connector *intel_connector;
6421         struct drm_connector *connector;
6422
6423         intel_connector = container_of(work, typeof(*intel_connector),
6424                                        modeset_retry_work);
6425         connector = &intel_connector->base;
6426         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6427                     connector->name);
6428
6429         /* Grab the locks before changing connector property*/
6430         mutex_lock(&connector->dev->mode_config.mutex);
6431         /* Set connector link status to BAD and send a Uevent to notify
6432          * userspace to do a modeset.
6433          */
6434         drm_connector_set_link_status_property(connector,
6435                                                DRM_MODE_LINK_STATUS_BAD);
6436         mutex_unlock(&connector->dev->mode_config.mutex);
6437         /* Send Hotplug uevent so userspace can reprobe */
6438         drm_kms_helper_connector_hotplug_event(connector);
6439 }
6440
6441 bool
6442 intel_dp_init_connector(struct intel_digital_port *dig_port,
6443                         struct intel_connector *intel_connector)
6444 {
6445         struct drm_connector *connector = &intel_connector->base;
6446         struct intel_dp *intel_dp = &dig_port->dp;
6447         struct intel_encoder *intel_encoder = &dig_port->base;
6448         struct drm_device *dev = intel_encoder->base.dev;
6449         struct drm_i915_private *dev_priv = to_i915(dev);
6450         enum port port = intel_encoder->port;
6451         enum phy phy = intel_port_to_phy(dev_priv, port);
6452         int type;
6453
6454         /* Initialize the work for modeset in case of link train failure */
6455         INIT_WORK(&intel_connector->modeset_retry_work,
6456                   intel_dp_modeset_retry_work_fn);
6457
6458         if (drm_WARN(dev, dig_port->max_lanes < 1,
6459                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6460                      dig_port->max_lanes, intel_encoder->base.base.id,
6461                      intel_encoder->base.name))
6462                 return false;
6463
6464         intel_dp->reset_link_params = true;
6465         intel_dp->pps.pps_pipe = INVALID_PIPE;
6466         intel_dp->pps.active_pipe = INVALID_PIPE;
6467
6468         /* Preserve the current hw state. */
6469         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6470         intel_dp->attached_connector = intel_connector;
6471
6472         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6473                 /*
6474                  * Currently we don't support eDP on TypeC ports, although in
6475                  * theory it could work on TypeC legacy ports.
6476                  */
6477                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6478                 type = DRM_MODE_CONNECTOR_eDP;
6479                 intel_encoder->type = INTEL_OUTPUT_EDP;
6480
6481                 /* eDP only on port B and/or C on vlv/chv */
6482                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6483                                       IS_CHERRYVIEW(dev_priv)) &&
6484                                 port != PORT_B && port != PORT_C))
6485                         return false;
6486         } else {
6487                 type = DRM_MODE_CONNECTOR_DisplayPort;
6488         }
6489
6490         intel_dp_set_default_sink_rates(intel_dp);
6491         intel_dp_set_default_max_sink_lane_count(intel_dp);
6492
6493         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6494                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6495
6496         intel_dp_aux_init(intel_dp);
6497         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6498
6499         drm_dbg_kms(&dev_priv->drm,
6500                     "Adding %s connector on [ENCODER:%d:%s]\n",
6501                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6502                     intel_encoder->base.base.id, intel_encoder->base.name);
6503
6504         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6505                                     type, &intel_dp->aux.ddc);
6506         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6507
6508         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6509                 connector->interlace_allowed = true;
6510
6511         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6512         intel_connector->base.polled = intel_connector->polled;
6513
6514         intel_connector_attach_encoder(intel_connector, intel_encoder);
6515
6516         if (HAS_DDI(dev_priv))
6517                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6518         else
6519                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6520
6521         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6522                 intel_dp_aux_fini(intel_dp);
6523                 goto fail;
6524         }
6525
6526         intel_dp_set_source_rates(intel_dp);
6527         intel_dp_set_common_rates(intel_dp);
6528         intel_dp_reset_max_link_params(intel_dp);
6529
6530         /* init MST on ports that can support it */
6531         intel_dp_mst_encoder_init(dig_port,
6532                                   intel_connector->base.base.id);
6533
6534         intel_dp_add_properties(intel_dp, connector);
6535
6536         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6537                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6538                 if (ret)
6539                         drm_dbg_kms(&dev_priv->drm,
6540                                     "HDCP init failed, skipping.\n");
6541         }
6542
6543         intel_dp->colorimetry_support =
6544                 intel_dp_get_colorimetry_status(intel_dp);
6545
6546         intel_dp->frl.is_trained = false;
6547         intel_dp->frl.trained_rate_gbps = 0;
6548
6549         intel_psr_init(intel_dp);
6550
6551         return true;
6552
6553 fail:
6554         intel_display_power_flush_work(dev_priv);
6555         drm_connector_cleanup(connector);
6556
6557         return false;
6558 }
6559
6560 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6561 {
6562         struct intel_encoder *encoder;
6563
6564         if (!HAS_DISPLAY(dev_priv))
6565                 return;
6566
6567         for_each_intel_encoder(&dev_priv->drm, encoder) {
6568                 struct intel_dp *intel_dp;
6569
6570                 if (encoder->type != INTEL_OUTPUT_DDI)
6571                         continue;
6572
6573                 intel_dp = enc_to_intel_dp(encoder);
6574
6575                 if (!intel_dp_mst_source_support(intel_dp))
6576                         continue;
6577
6578                 if (intel_dp->is_mst)
6579                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6580         }
6581 }
6582
6583 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6584 {
6585         struct intel_encoder *encoder;
6586
6587         if (!HAS_DISPLAY(dev_priv))
6588                 return;
6589
6590         for_each_intel_encoder(&dev_priv->drm, encoder) {
6591                 struct intel_dp *intel_dp;
6592                 int ret;
6593
6594                 if (encoder->type != INTEL_OUTPUT_DDI)
6595                         continue;
6596
6597                 intel_dp = enc_to_intel_dp(encoder);
6598
6599                 if (!intel_dp_mst_source_support(intel_dp))
6600                         continue;
6601
6602                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6603                                                      true);
6604                 if (ret) {
6605                         intel_dp->is_mst = false;
6606                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6607                                                         false);
6608                 }
6609         }
6610 }