2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_dp_helper.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_probe_helper.h>
43 #include "i915_debugfs.h"
45 #include "intel_atomic.h"
46 #include "intel_audio.h"
47 #include "intel_connector.h"
48 #include "intel_ddi.h"
50 #include "intel_display_types.h"
52 #include "intel_dp_aux.h"
53 #include "intel_dp_hdcp.h"
54 #include "intel_dp_link_training.h"
55 #include "intel_dp_mst.h"
56 #include "intel_dpio_phy.h"
57 #include "intel_dpll.h"
58 #include "intel_fifo_underrun.h"
59 #include "intel_hdcp.h"
60 #include "intel_hdmi.h"
61 #include "intel_hotplug.h"
62 #include "intel_lspcon.h"
63 #include "intel_lvds.h"
64 #include "intel_panel.h"
65 #include "intel_pps.h"
66 #include "intel_psr.h"
67 #include "intel_sideband.h"
69 #include "intel_vdsc.h"
70 #include "intel_vrr.h"
72 #define DP_DPRX_ESI_LEN 14
74 /* DP DSC throughput values used for slice count calculations KPixels/s */
75 #define DP_DSC_PEAK_PIXEL_RATE 2720000
76 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
77 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
79 /* DP DSC FEC Overhead factor = 1/(0.972261) */
80 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
82 /* Compliance test status bits */
83 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
84 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
85 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
86 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
89 /* Constants for DP DSC configurations */
90 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
92 /* With Single pipe configuration, HW is capable of supporting maximum
93 * of 4 slices per line.
95 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
98 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
99 * @intel_dp: DP struct
101 * If a CPU or PCH DP output is attached to an eDP panel, this function
102 * will return true, and false otherwise.
104 bool intel_dp_is_edp(struct intel_dp *intel_dp)
106 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
108 return dig_port->base.type == INTEL_OUTPUT_EDP;
111 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
112 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
114 /* update sink rates from dpcd */
115 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
117 static const int dp_rates[] = {
118 162000, 270000, 540000, 810000
123 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
124 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
125 static const int quirk_rates[] = { 162000, 270000, 324000 };
127 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
128 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
133 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
134 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
136 max_rate = min(max_rate, max_lttpr_rate);
138 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
139 if (dp_rates[i] > max_rate)
141 intel_dp->sink_rates[i] = dp_rates[i];
144 intel_dp->num_sink_rates = i;
147 /* Get length of rates array potentially limited by max_rate. */
148 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
152 /* Limit results by potentially reduced max rate */
153 for (i = 0; i < len; i++) {
154 if (rates[len - i - 1] <= max_rate)
161 /* Get length of common rates array potentially limited by max_rate. */
162 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
165 return intel_dp_rate_limit_len(intel_dp->common_rates,
166 intel_dp->num_common_rates, max_rate);
169 /* Theoretical max between source and sink */
170 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
172 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
175 /* Theoretical max between source and sink */
176 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
178 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
179 int source_max = dig_port->max_lanes;
180 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
181 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
182 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
185 sink_max = min(sink_max, lttpr_max);
187 return min3(source_max, sink_max, fia_max);
190 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
192 return intel_dp->max_link_lane_count;
196 intel_dp_link_required(int pixel_clock, int bpp)
198 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
199 return DIV_ROUND_UP(pixel_clock * bpp, 8);
203 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
205 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
206 * link rate that is generally expressed in Gbps. Since, 8 bits of data
207 * is transmitted every LS_Clk per lane, there is no need to account for
208 * the channel encoding that is done in the PHY layer here.
211 return max_link_clock * max_lanes;
214 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
217 struct intel_encoder *encoder = &intel_dig_port->base;
218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
220 return DISPLAY_VER(dev_priv) >= 12 ||
221 (DISPLAY_VER(dev_priv) == 11 &&
222 encoder->port != PORT_A);
225 static int icl_max_source_rate(struct intel_dp *intel_dp)
227 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
228 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
229 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
231 if (intel_phy_is_combo(dev_priv, phy) &&
232 !intel_dp_is_edp(intel_dp))
238 static int ehl_max_source_rate(struct intel_dp *intel_dp)
240 if (intel_dp_is_edp(intel_dp))
247 intel_dp_set_source_rates(struct intel_dp *intel_dp)
249 /* The values must be in increasing order */
250 static const int icl_rates[] = {
251 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
253 static const int bxt_rates[] = {
254 162000, 216000, 243000, 270000, 324000, 432000, 540000
256 static const int skl_rates[] = {
257 162000, 216000, 270000, 324000, 432000, 540000
259 static const int hsw_rates[] = {
260 162000, 270000, 540000
262 static const int g4x_rates[] = {
265 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
266 struct intel_encoder *encoder = &dig_port->base;
267 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
268 const int *source_rates;
269 int size, max_rate = 0, vbt_max_rate;
271 /* This should only be done once */
272 drm_WARN_ON(&dev_priv->drm,
273 intel_dp->source_rates || intel_dp->num_source_rates);
275 if (DISPLAY_VER(dev_priv) >= 11) {
276 source_rates = icl_rates;
277 size = ARRAY_SIZE(icl_rates);
278 if (IS_JSL_EHL(dev_priv))
279 max_rate = ehl_max_source_rate(intel_dp);
281 max_rate = icl_max_source_rate(intel_dp);
282 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
283 source_rates = bxt_rates;
284 size = ARRAY_SIZE(bxt_rates);
285 } else if (DISPLAY_VER(dev_priv) == 9) {
286 source_rates = skl_rates;
287 size = ARRAY_SIZE(skl_rates);
288 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
289 IS_BROADWELL(dev_priv)) {
290 source_rates = hsw_rates;
291 size = ARRAY_SIZE(hsw_rates);
293 source_rates = g4x_rates;
294 size = ARRAY_SIZE(g4x_rates);
297 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
298 if (max_rate && vbt_max_rate)
299 max_rate = min(max_rate, vbt_max_rate);
300 else if (vbt_max_rate)
301 max_rate = vbt_max_rate;
304 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
306 intel_dp->source_rates = source_rates;
307 intel_dp->num_source_rates = size;
310 static int intersect_rates(const int *source_rates, int source_len,
311 const int *sink_rates, int sink_len,
314 int i = 0, j = 0, k = 0;
316 while (i < source_len && j < sink_len) {
317 if (source_rates[i] == sink_rates[j]) {
318 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
320 common_rates[k] = source_rates[i];
324 } else if (source_rates[i] < sink_rates[j]) {
333 /* return index of rate in rates array, or -1 if not found */
334 static int intel_dp_rate_index(const int *rates, int len, int rate)
338 for (i = 0; i < len; i++)
339 if (rate == rates[i])
345 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
347 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
349 drm_WARN_ON(&i915->drm,
350 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
352 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
353 intel_dp->num_source_rates,
354 intel_dp->sink_rates,
355 intel_dp->num_sink_rates,
356 intel_dp->common_rates);
358 /* Paranoia, there should always be something in common. */
359 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
360 intel_dp->common_rates[0] = 162000;
361 intel_dp->num_common_rates = 1;
365 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
369 * FIXME: we need to synchronize the current link parameters with
370 * hardware readout. Currently fast link training doesn't work on
373 if (link_rate == 0 ||
374 link_rate > intel_dp->max_link_rate)
377 if (lane_count == 0 ||
378 lane_count > intel_dp_max_lane_count(intel_dp))
384 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
388 const struct drm_display_mode *fixed_mode =
389 intel_dp->attached_connector->panel.fixed_mode;
390 int mode_rate, max_rate;
392 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
393 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
394 if (mode_rate > max_rate)
400 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
401 int link_rate, u8 lane_count)
403 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
407 * TODO: Enable fallback on MST links once MST link compute can handle
408 * the fallback params.
410 if (intel_dp->is_mst) {
411 drm_err(&i915->drm, "Link Training Unsuccessful\n");
415 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
416 drm_dbg_kms(&i915->drm,
417 "Retrying Link training for eDP with max parameters\n");
418 intel_dp->use_max_params = true;
422 index = intel_dp_rate_index(intel_dp->common_rates,
423 intel_dp->num_common_rates,
426 if (intel_dp_is_edp(intel_dp) &&
427 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
428 intel_dp->common_rates[index - 1],
430 drm_dbg_kms(&i915->drm,
431 "Retrying Link training for eDP with same parameters\n");
434 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
435 intel_dp->max_link_lane_count = lane_count;
436 } else if (lane_count > 1) {
437 if (intel_dp_is_edp(intel_dp) &&
438 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
439 intel_dp_max_common_rate(intel_dp),
441 drm_dbg_kms(&i915->drm,
442 "Retrying Link training for eDP with same parameters\n");
445 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
446 intel_dp->max_link_lane_count = lane_count >> 1;
448 drm_err(&i915->drm, "Link Training Unsuccessful\n");
455 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
457 return div_u64(mul_u32_u32(mode_clock, 1000000U),
458 DP_DSC_FEC_OVERHEAD_FACTOR);
462 small_joiner_ram_size_bits(struct drm_i915_private *i915)
464 if (DISPLAY_VER(i915) >= 11)
470 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
471 u32 link_clock, u32 lane_count,
472 u32 mode_clock, u32 mode_hdisplay,
476 u32 bits_per_pixel, max_bpp_small_joiner_ram;
480 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
481 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
482 * for SST -> TimeSlotsPerMTP is 1,
483 * for MST -> TimeSlotsPerMTP has to be calculated
485 bits_per_pixel = (link_clock * lane_count * 8) /
486 intel_dp_mode_to_fec_clock(mode_clock);
487 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
489 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
490 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
494 max_bpp_small_joiner_ram *= 2;
496 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
497 max_bpp_small_joiner_ram);
500 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
501 * check, output bpp from small joiner RAM check)
503 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
506 u32 max_bpp_bigjoiner =
507 i915->max_cdclk_freq * 48 /
508 intel_dp_mode_to_fec_clock(mode_clock);
510 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
511 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
514 /* Error out if the max bpp is less than smallest allowed valid bpp */
515 if (bits_per_pixel < valid_dsc_bpp[0]) {
516 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
517 bits_per_pixel, valid_dsc_bpp[0]);
521 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
522 if (DISPLAY_VER(i915) >= 13) {
523 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
525 /* Find the nearest match in the array of known BPPs from VESA */
526 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
527 if (bits_per_pixel < valid_dsc_bpp[i + 1])
530 bits_per_pixel = valid_dsc_bpp[i];
534 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
535 * fractional part is 0
537 return bits_per_pixel << 4;
540 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
541 int mode_clock, int mode_hdisplay,
544 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
545 u8 min_slice_count, i;
548 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
549 min_slice_count = DIV_ROUND_UP(mode_clock,
550 DP_DSC_MAX_ENC_THROUGHPUT_0);
552 min_slice_count = DIV_ROUND_UP(mode_clock,
553 DP_DSC_MAX_ENC_THROUGHPUT_1);
555 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
556 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
557 drm_dbg_kms(&i915->drm,
558 "Unsupported slice width %d by DP DSC Sink device\n",
562 /* Also take into account max slice width */
563 min_slice_count = max_t(u8, min_slice_count,
564 DIV_ROUND_UP(mode_hdisplay,
567 /* Find the closest match to the valid slice count values */
568 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
569 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
571 if (test_slice_count >
572 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
575 /* big joiner needs small joiner to be enabled */
576 if (bigjoiner && test_slice_count < 4)
579 if (min_slice_count <= test_slice_count)
580 return test_slice_count;
583 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
588 static enum intel_output_format
589 intel_dp_output_format(struct drm_connector *connector,
590 const struct drm_display_mode *mode)
592 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
593 const struct drm_display_info *info = &connector->display_info;
595 if (!connector->ycbcr_420_allowed ||
596 !drm_mode_is_420_only(info, mode))
597 return INTEL_OUTPUT_FORMAT_RGB;
599 if (intel_dp->dfp.rgb_to_ycbcr &&
600 intel_dp->dfp.ycbcr_444_to_420)
601 return INTEL_OUTPUT_FORMAT_RGB;
603 if (intel_dp->dfp.ycbcr_444_to_420)
604 return INTEL_OUTPUT_FORMAT_YCBCR444;
606 return INTEL_OUTPUT_FORMAT_YCBCR420;
609 int intel_dp_min_bpp(enum intel_output_format output_format)
611 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
617 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
620 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
621 * format of the number of bytes per pixel will be half the number
622 * of bytes of RGB pixel.
624 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
631 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
632 const struct drm_display_mode *mode)
634 enum intel_output_format output_format =
635 intel_dp_output_format(connector, mode);
637 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
640 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
644 * Older platforms don't like hdisplay==4096 with DP.
646 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
647 * and frame counter increment), but we don't get vblank interrupts,
648 * and the pipe underruns immediately. The link also doesn't seem
649 * to get trained properly.
651 * On CHV the vblank interrupts don't seem to disappear but
652 * otherwise the symptoms are similar.
654 * TODO: confirm the behaviour on HSW+
656 return hdisplay == 4096 && !HAS_DDI(dev_priv);
659 static enum drm_mode_status
660 intel_dp_mode_valid_downstream(struct intel_connector *connector,
661 const struct drm_display_mode *mode,
664 struct intel_dp *intel_dp = intel_attached_dp(connector);
665 const struct drm_display_info *info = &connector->base.display_info;
668 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
669 if (intel_dp->dfp.pcon_max_frl_bw) {
672 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
674 target_bw = bpp * target_clock;
676 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
678 /* converting bw from Gbps to Kbps*/
679 max_frl_bw = max_frl_bw * 1000000;
681 if (target_bw > max_frl_bw)
682 return MODE_CLOCK_HIGH;
687 if (intel_dp->dfp.max_dotclock &&
688 target_clock > intel_dp->dfp.max_dotclock)
689 return MODE_CLOCK_HIGH;
691 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
692 tmds_clock = target_clock;
693 if (drm_mode_is_420_only(info, mode))
696 if (intel_dp->dfp.min_tmds_clock &&
697 tmds_clock < intel_dp->dfp.min_tmds_clock)
698 return MODE_CLOCK_LOW;
699 if (intel_dp->dfp.max_tmds_clock &&
700 tmds_clock > intel_dp->dfp.max_tmds_clock)
701 return MODE_CLOCK_HIGH;
706 static enum drm_mode_status
707 intel_dp_mode_valid(struct drm_connector *connector,
708 struct drm_display_mode *mode)
710 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
711 struct intel_connector *intel_connector = to_intel_connector(connector);
712 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
713 struct drm_i915_private *dev_priv = to_i915(connector->dev);
714 int target_clock = mode->clock;
715 int max_rate, mode_rate, max_lanes, max_link_clock;
716 int max_dotclk = dev_priv->max_dotclk_freq;
717 u16 dsc_max_output_bpp = 0;
718 u8 dsc_slice_count = 0;
719 enum drm_mode_status status;
720 bool dsc = false, bigjoiner = false;
722 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
723 return MODE_NO_DBLESCAN;
725 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
726 return MODE_H_ILLEGAL;
728 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
729 if (mode->hdisplay != fixed_mode->hdisplay)
732 if (mode->vdisplay != fixed_mode->vdisplay)
735 target_clock = fixed_mode->clock;
738 if (mode->clock < 10000)
739 return MODE_CLOCK_LOW;
741 if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
742 intel_dp_can_bigjoiner(intel_dp)) {
746 if (target_clock > max_dotclk)
747 return MODE_CLOCK_HIGH;
749 max_link_clock = intel_dp_max_link_rate(intel_dp);
750 max_lanes = intel_dp_max_lane_count(intel_dp);
752 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
753 mode_rate = intel_dp_link_required(target_clock,
754 intel_dp_mode_min_output_bpp(connector, mode));
756 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
757 return MODE_H_ILLEGAL;
760 * Output bpp is stored in 6.4 format so right shift by 4 to get the
761 * integer value since we support only integer values of bpp.
763 if (DISPLAY_VER(dev_priv) >= 10 &&
764 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
766 * TBD pass the connector BPC,
767 * for now U8_MAX so that max BPC on that platform would be picked
769 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
771 if (intel_dp_is_edp(intel_dp)) {
773 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
775 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
777 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
779 intel_dp_dsc_get_output_bpp(dev_priv,
787 intel_dp_dsc_get_slice_count(intel_dp,
793 dsc = dsc_max_output_bpp && dsc_slice_count;
797 * Big joiner configuration needs DSC for TGL which is not true for
798 * XE_LPD where uncompressed joiner is supported.
800 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
801 return MODE_CLOCK_HIGH;
803 if (mode_rate > max_rate && !dsc)
804 return MODE_CLOCK_HIGH;
806 status = intel_dp_mode_valid_downstream(intel_connector,
808 if (status != MODE_OK)
811 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
814 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
816 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
818 return max_rate >= 540000;
821 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
823 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
825 return max_rate >= 810000;
828 static void snprintf_int_array(char *str, size_t len,
829 const int *array, int nelem)
835 for (i = 0; i < nelem; i++) {
836 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
844 static void intel_dp_print_rates(struct intel_dp *intel_dp)
846 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
847 char str[128]; /* FIXME: too big for stack? */
849 if (!drm_debug_enabled(DRM_UT_KMS))
852 snprintf_int_array(str, sizeof(str),
853 intel_dp->source_rates, intel_dp->num_source_rates);
854 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
856 snprintf_int_array(str, sizeof(str),
857 intel_dp->sink_rates, intel_dp->num_sink_rates);
858 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
860 snprintf_int_array(str, sizeof(str),
861 intel_dp->common_rates, intel_dp->num_common_rates);
862 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
866 intel_dp_max_link_rate(struct intel_dp *intel_dp)
868 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
871 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
872 if (drm_WARN_ON(&i915->drm, len <= 0))
875 return intel_dp->common_rates[len - 1];
878 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
880 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
881 int i = intel_dp_rate_index(intel_dp->sink_rates,
882 intel_dp->num_sink_rates, rate);
884 if (drm_WARN_ON(&i915->drm, i < 0))
890 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
891 u8 *link_bw, u8 *rate_select)
893 /* eDP 1.4 rate select method. */
894 if (intel_dp->use_rate_select) {
897 intel_dp_rate_select(intel_dp, port_clock);
899 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
904 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
905 const struct intel_crtc_state *pipe_config)
907 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
909 /* On TGL, FEC is supported on all Pipes */
910 if (DISPLAY_VER(dev_priv) >= 12)
913 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
919 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
920 const struct intel_crtc_state *pipe_config)
922 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
923 drm_dp_sink_supports_fec(intel_dp->fec_capable);
926 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
927 const struct intel_crtc_state *crtc_state)
929 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
932 return intel_dsc_source_support(crtc_state) &&
933 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
936 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
937 const struct intel_crtc_state *crtc_state)
939 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
940 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
941 intel_dp->dfp.ycbcr_444_to_420);
944 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
945 const struct intel_crtc_state *crtc_state, int bpc)
947 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
949 if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
955 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
956 const struct intel_crtc_state *crtc_state, int bpc)
958 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
960 if (intel_dp->dfp.min_tmds_clock &&
961 tmds_clock < intel_dp->dfp.min_tmds_clock)
964 if (intel_dp->dfp.max_tmds_clock &&
965 tmds_clock > intel_dp->dfp.max_tmds_clock)
971 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
972 const struct intel_crtc_state *crtc_state,
976 return intel_hdmi_deep_color_possible(crtc_state, bpc,
977 intel_dp->has_hdmi_sink,
978 intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
979 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
982 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
983 const struct intel_crtc_state *crtc_state)
985 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
986 struct intel_connector *intel_connector = intel_dp->attached_connector;
989 bpc = crtc_state->pipe_bpp / 3;
991 if (intel_dp->dfp.max_bpc)
992 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
994 if (intel_dp->dfp.min_tmds_clock) {
995 for (; bpc >= 10; bpc -= 2) {
996 if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1002 if (intel_dp_is_edp(intel_dp)) {
1003 /* Get bpp from vbt only for panels that dont have bpp in edid */
1004 if (intel_connector->base.display_info.bpc == 0 &&
1005 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1006 drm_dbg_kms(&dev_priv->drm,
1007 "clamping bpp for eDP panel to BIOS-provided %i\n",
1008 dev_priv->vbt.edp.bpp);
1009 bpp = dev_priv->vbt.edp.bpp;
1016 /* Adjust link config limits based on compliance test requests. */
1018 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1019 struct intel_crtc_state *pipe_config,
1020 struct link_config_limits *limits)
1022 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1024 /* For DP Compliance we override the computed bpp for the pipe */
1025 if (intel_dp->compliance.test_data.bpc != 0) {
1026 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1028 limits->min_bpp = limits->max_bpp = bpp;
1029 pipe_config->dither_force_disable = bpp == 6 * 3;
1031 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1034 /* Use values requested by Compliance Test Request */
1035 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1038 /* Validate the compliance test data since max values
1039 * might have changed due to link train fallback.
1041 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1042 intel_dp->compliance.test_lane_count)) {
1043 index = intel_dp_rate_index(intel_dp->common_rates,
1044 intel_dp->num_common_rates,
1045 intel_dp->compliance.test_link_rate);
1047 limits->min_clock = limits->max_clock = index;
1048 limits->min_lane_count = limits->max_lane_count =
1049 intel_dp->compliance.test_lane_count;
1054 /* Optimize link config in order: max bpp, min clock, min lanes */
1056 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1057 struct intel_crtc_state *pipe_config,
1058 const struct link_config_limits *limits)
1060 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1061 int bpp, clock, lane_count;
1062 int mode_rate, link_clock, link_avail;
1064 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1065 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1067 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1070 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1071 for (lane_count = limits->min_lane_count;
1072 lane_count <= limits->max_lane_count;
1074 link_clock = intel_dp->common_rates[clock];
1075 link_avail = intel_dp_max_data_rate(link_clock,
1078 if (mode_rate <= link_avail) {
1079 pipe_config->lane_count = lane_count;
1080 pipe_config->pipe_bpp = bpp;
1081 pipe_config->port_clock = link_clock;
1092 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1094 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1096 u8 dsc_bpc[3] = {0};
1099 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1100 if (DISPLAY_VER(i915) >= 12)
1101 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1103 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1105 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1107 for (i = 0; i < num_bpc; i++) {
1108 if (dsc_max_bpc >= dsc_bpc[i])
1109 return dsc_bpc[i] * 3;
1115 #define DSC_SUPPORTED_VERSION_MIN 1
1117 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1118 struct intel_crtc_state *crtc_state)
1120 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1122 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1127 * RC_MODEL_SIZE is currently a constant across all configurations.
1129 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1130 * DP_DSC_RC_BUF_SIZE for this.
1132 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1135 * Slice Height of 8 works for all currently available panels. So start
1136 * with that if pic_height is an integral multiple of 8. Eventually add
1137 * logic to try multiple slice heights.
1139 if (vdsc_cfg->pic_height % 8 == 0)
1140 vdsc_cfg->slice_height = 8;
1141 else if (vdsc_cfg->pic_height % 4 == 0)
1142 vdsc_cfg->slice_height = 4;
1144 vdsc_cfg->slice_height = 2;
1146 ret = intel_dsc_compute_params(encoder, crtc_state);
1150 vdsc_cfg->dsc_version_major =
1151 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1152 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1153 vdsc_cfg->dsc_version_minor =
1154 min(DSC_SUPPORTED_VERSION_MIN,
1155 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1156 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1158 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1161 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1162 if (!line_buf_depth) {
1163 drm_dbg_kms(&i915->drm,
1164 "DSC Sink Line Buffer Depth invalid\n");
1168 if (vdsc_cfg->dsc_version_minor == 2)
1169 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1170 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1172 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1173 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1175 vdsc_cfg->block_pred_enable =
1176 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1177 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1179 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1182 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1183 struct intel_crtc_state *pipe_config,
1184 struct drm_connector_state *conn_state,
1185 struct link_config_limits *limits)
1187 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1188 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1189 const struct drm_display_mode *adjusted_mode =
1190 &pipe_config->hw.adjusted_mode;
1194 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1195 intel_dp_supports_fec(intel_dp, pipe_config);
1197 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1200 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1202 /* Min Input BPC for ICL+ is 8 */
1203 if (pipe_bpp < 8 * 3) {
1204 drm_dbg_kms(&dev_priv->drm,
1205 "No DSC support for less than 8bpc\n");
1210 * For now enable DSC for max bpp, max link rate, max lane count.
1211 * Optimize this later for the minimum possible link rate/lane count
1212 * with DSC enabled for the requested mode.
1214 pipe_config->pipe_bpp = pipe_bpp;
1215 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1216 pipe_config->lane_count = limits->max_lane_count;
1218 if (intel_dp_is_edp(intel_dp)) {
1219 pipe_config->dsc.compressed_bpp =
1220 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1221 pipe_config->pipe_bpp);
1222 pipe_config->dsc.slice_count =
1223 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1226 u16 dsc_max_output_bpp;
1227 u8 dsc_dp_slice_count;
1229 dsc_max_output_bpp =
1230 intel_dp_dsc_get_output_bpp(dev_priv,
1231 pipe_config->port_clock,
1232 pipe_config->lane_count,
1233 adjusted_mode->crtc_clock,
1234 adjusted_mode->crtc_hdisplay,
1235 pipe_config->bigjoiner,
1237 dsc_dp_slice_count =
1238 intel_dp_dsc_get_slice_count(intel_dp,
1239 adjusted_mode->crtc_clock,
1240 adjusted_mode->crtc_hdisplay,
1241 pipe_config->bigjoiner);
1242 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1243 drm_dbg_kms(&dev_priv->drm,
1244 "Compressed BPP/Slice Count not supported\n");
1247 pipe_config->dsc.compressed_bpp = min_t(u16,
1248 dsc_max_output_bpp >> 4,
1249 pipe_config->pipe_bpp);
1250 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1253 /* As of today we support DSC for only RGB */
1254 if (intel_dp->force_dsc_bpp) {
1255 if (intel_dp->force_dsc_bpp >= 8 &&
1256 intel_dp->force_dsc_bpp < pipe_bpp) {
1257 drm_dbg_kms(&dev_priv->drm,
1258 "DSC BPP forced to %d",
1259 intel_dp->force_dsc_bpp);
1260 pipe_config->dsc.compressed_bpp =
1261 intel_dp->force_dsc_bpp;
1263 drm_dbg_kms(&dev_priv->drm,
1264 "Invalid DSC BPP %d",
1265 intel_dp->force_dsc_bpp);
1270 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1271 * is greater than the maximum Cdclock and if slice count is even
1272 * then we need to use 2 VDSC instances.
1274 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1275 pipe_config->bigjoiner) {
1276 if (pipe_config->dsc.slice_count < 2) {
1277 drm_dbg_kms(&dev_priv->drm,
1278 "Cannot split stream to use 2 VDSC instances\n");
1282 pipe_config->dsc.dsc_split = true;
1285 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1287 drm_dbg_kms(&dev_priv->drm,
1288 "Cannot compute valid DSC parameters for Input Bpp = %d "
1289 "Compressed BPP = %d\n",
1290 pipe_config->pipe_bpp,
1291 pipe_config->dsc.compressed_bpp);
1295 pipe_config->dsc.compression_enable = true;
1296 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1297 "Compressed Bpp = %d Slice Count = %d\n",
1298 pipe_config->pipe_bpp,
1299 pipe_config->dsc.compressed_bpp,
1300 pipe_config->dsc.slice_count);
1306 intel_dp_compute_link_config(struct intel_encoder *encoder,
1307 struct intel_crtc_state *pipe_config,
1308 struct drm_connector_state *conn_state)
1310 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1311 const struct drm_display_mode *adjusted_mode =
1312 &pipe_config->hw.adjusted_mode;
1313 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1314 struct link_config_limits limits;
1318 common_len = intel_dp_common_len_rate_limit(intel_dp,
1319 intel_dp->max_link_rate);
1321 /* No common link rates between source and sink */
1322 drm_WARN_ON(encoder->base.dev, common_len <= 0);
1324 limits.min_clock = 0;
1325 limits.max_clock = common_len - 1;
1327 limits.min_lane_count = 1;
1328 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1330 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1331 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1333 if (intel_dp->use_max_params) {
1335 * Use the maximum clock and number of lanes the eDP panel
1336 * advertizes being capable of in case the initial fast
1337 * optimal params failed us. The panels are generally
1338 * designed to support only a single clock and lane
1339 * configuration, and typically on older panels these
1340 * values correspond to the native resolution of the panel.
1342 limits.min_lane_count = limits.max_lane_count;
1343 limits.min_clock = limits.max_clock;
1346 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1348 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1349 "max rate %d max bpp %d pixel clock %iKHz\n",
1350 limits.max_lane_count,
1351 intel_dp->common_rates[limits.max_clock],
1352 limits.max_bpp, adjusted_mode->crtc_clock);
1354 if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1355 adjusted_mode->crtc_hdisplay > 5120) &&
1356 intel_dp_can_bigjoiner(intel_dp))
1357 pipe_config->bigjoiner = true;
1360 * Optimize for slow and wide for everything, because there are some
1361 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1363 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1366 * Pipe joiner needs compression upto display12 due to BW limitation. DG2
1367 * onwards pipe joiner can be enabled without compression.
1369 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1370 if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 &&
1371 pipe_config->bigjoiner)) {
1372 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1373 conn_state, &limits);
1378 if (pipe_config->dsc.compression_enable) {
1379 drm_dbg_kms(&i915->drm,
1380 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1381 pipe_config->lane_count, pipe_config->port_clock,
1382 pipe_config->pipe_bpp,
1383 pipe_config->dsc.compressed_bpp);
1385 drm_dbg_kms(&i915->drm,
1386 "DP link rate required %i available %i\n",
1387 intel_dp_link_required(adjusted_mode->crtc_clock,
1388 pipe_config->dsc.compressed_bpp),
1389 intel_dp_max_data_rate(pipe_config->port_clock,
1390 pipe_config->lane_count));
1392 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1393 pipe_config->lane_count, pipe_config->port_clock,
1394 pipe_config->pipe_bpp);
1396 drm_dbg_kms(&i915->drm,
1397 "DP link rate required %i available %i\n",
1398 intel_dp_link_required(adjusted_mode->crtc_clock,
1399 pipe_config->pipe_bpp),
1400 intel_dp_max_data_rate(pipe_config->port_clock,
1401 pipe_config->lane_count));
1406 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1407 const struct drm_connector_state *conn_state)
1409 const struct intel_digital_connector_state *intel_conn_state =
1410 to_intel_digital_connector_state(conn_state);
1411 const struct drm_display_mode *adjusted_mode =
1412 &crtc_state->hw.adjusted_mode;
1415 * Our YCbCr output is always limited range.
1416 * crtc_state->limited_color_range only applies to RGB,
1417 * and it must never be set for YCbCr or we risk setting
1418 * some conflicting bits in PIPECONF which will mess up
1419 * the colors on the monitor.
1421 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1424 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1427 * CEA-861-E - 5.1 Default Encoding Parameters
1428 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1430 return crtc_state->pipe_bpp != 18 &&
1431 drm_default_rgb_quant_range(adjusted_mode) ==
1432 HDMI_QUANTIZATION_RANGE_LIMITED;
1434 return intel_conn_state->broadcast_rgb ==
1435 INTEL_BROADCAST_RGB_LIMITED;
1439 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1442 if (IS_G4X(dev_priv))
1444 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1450 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1451 const struct drm_connector_state *conn_state,
1452 struct drm_dp_vsc_sdp *vsc)
1454 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1458 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1459 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1460 * Colorimetry Format indication.
1462 vsc->revision = 0x5;
1465 /* DP 1.4a spec, Table 2-120 */
1466 switch (crtc_state->output_format) {
1467 case INTEL_OUTPUT_FORMAT_YCBCR444:
1468 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1470 case INTEL_OUTPUT_FORMAT_YCBCR420:
1471 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1473 case INTEL_OUTPUT_FORMAT_RGB:
1475 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1478 switch (conn_state->colorspace) {
1479 case DRM_MODE_COLORIMETRY_BT709_YCC:
1480 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1482 case DRM_MODE_COLORIMETRY_XVYCC_601:
1483 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1485 case DRM_MODE_COLORIMETRY_XVYCC_709:
1486 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1488 case DRM_MODE_COLORIMETRY_SYCC_601:
1489 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1491 case DRM_MODE_COLORIMETRY_OPYCC_601:
1492 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1494 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1495 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1497 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1498 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1500 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1501 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1503 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1504 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1505 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1509 * RGB->YCBCR color conversion uses the BT.709
1512 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1513 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1515 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1519 vsc->bpc = crtc_state->pipe_bpp / 3;
1521 /* only RGB pixelformat supports 6 bpc */
1522 drm_WARN_ON(&dev_priv->drm,
1523 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1525 /* all YCbCr are always limited range */
1526 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1527 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1530 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1531 struct intel_crtc_state *crtc_state,
1532 const struct drm_connector_state *conn_state)
1534 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1536 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1537 if (crtc_state->has_psr)
1540 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1543 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1544 vsc->sdp_type = DP_SDP_VSC;
1545 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1546 &crtc_state->infoframes.vsc);
1549 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1550 const struct intel_crtc_state *crtc_state,
1551 const struct drm_connector_state *conn_state,
1552 struct drm_dp_vsc_sdp *vsc)
1554 vsc->sdp_type = DP_SDP_VSC;
1556 if (intel_dp->psr.psr2_enabled) {
1557 if (intel_dp->psr.colorimetry_support &&
1558 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1559 /* [PSR2, +Colorimetry] */
1560 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1564 * [PSR2, -Colorimetry]
1565 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1566 * 3D stereo + PSR/PSR2 + Y-coordinate.
1568 vsc->revision = 0x4;
1574 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1575 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1578 vsc->revision = 0x2;
1584 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1585 struct intel_crtc_state *crtc_state,
1586 const struct drm_connector_state *conn_state)
1589 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1590 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1592 if (!conn_state->hdr_output_metadata)
1595 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1598 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1602 crtc_state->infoframes.enable |=
1603 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1607 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1608 struct intel_crtc_state *pipe_config,
1609 int output_bpp, bool constant_n)
1611 struct intel_connector *intel_connector = intel_dp->attached_connector;
1612 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1615 if (pipe_config->vrr.enable)
1619 * DRRS and PSR can't be enable together, so giving preference to PSR
1620 * as it allows more power-savings by complete shutting down display,
1621 * so to guarantee this, intel_dp_drrs_compute_config() must be called
1622 * after intel_psr_compute_config().
1624 if (pipe_config->has_psr)
1627 if (!intel_connector->panel.downclock_mode ||
1628 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1631 pipe_config->has_drrs = true;
1633 pixel_clock = intel_connector->panel.downclock_mode->clock;
1634 if (pipe_config->splitter.enable)
1635 pixel_clock /= pipe_config->splitter.link_count;
1637 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1638 pipe_config->port_clock, &pipe_config->dp_m2_n2,
1639 constant_n, pipe_config->fec_enable);
1641 /* FIXME: abstract this better */
1642 if (pipe_config->splitter.enable)
1643 pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
1647 intel_dp_compute_config(struct intel_encoder *encoder,
1648 struct intel_crtc_state *pipe_config,
1649 struct drm_connector_state *conn_state)
1651 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1652 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1653 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1654 enum port port = encoder->port;
1655 struct intel_connector *intel_connector = intel_dp->attached_connector;
1656 struct intel_digital_connector_state *intel_conn_state =
1657 to_intel_digital_connector_state(conn_state);
1658 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1659 int ret = 0, output_bpp;
1661 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1662 pipe_config->has_pch_encoder = true;
1664 pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1667 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1668 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1673 if (!intel_dp_port_has_audio(dev_priv, port))
1674 pipe_config->has_audio = false;
1675 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1676 pipe_config->has_audio = intel_dp->has_audio;
1678 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1680 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1681 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1684 if (HAS_GMCH(dev_priv))
1685 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1687 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1695 if (HAS_GMCH(dev_priv) &&
1696 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1699 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1702 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1705 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1709 pipe_config->limited_color_range =
1710 intel_dp_limited_color_range(pipe_config, conn_state);
1712 if (pipe_config->dsc.compression_enable)
1713 output_bpp = pipe_config->dsc.compressed_bpp;
1715 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1716 pipe_config->pipe_bpp);
1718 if (intel_dp->mso_link_count) {
1719 int n = intel_dp->mso_link_count;
1720 int overlap = intel_dp->mso_pixel_overlap;
1722 pipe_config->splitter.enable = true;
1723 pipe_config->splitter.link_count = n;
1724 pipe_config->splitter.pixel_overlap = overlap;
1726 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1729 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1730 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1731 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1732 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1733 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1734 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1735 adjusted_mode->crtc_clock /= n;
1738 intel_link_compute_m_n(output_bpp,
1739 pipe_config->lane_count,
1740 adjusted_mode->crtc_clock,
1741 pipe_config->port_clock,
1742 &pipe_config->dp_m_n,
1743 constant_n, pipe_config->fec_enable);
1745 /* FIXME: abstract this better */
1746 if (pipe_config->splitter.enable)
1747 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1749 if (!HAS_DDI(dev_priv))
1750 g4x_dp_set_clock(encoder, pipe_config);
1752 intel_vrr_compute_config(pipe_config, conn_state);
1753 intel_psr_compute_config(intel_dp, pipe_config);
1754 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1756 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1757 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1762 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1763 int link_rate, int lane_count)
1765 intel_dp->link_trained = false;
1766 intel_dp->link_rate = link_rate;
1767 intel_dp->lane_count = lane_count;
1770 /* Enable backlight PWM and backlight PP control. */
1771 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1772 const struct drm_connector_state *conn_state)
1774 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1775 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1777 if (!intel_dp_is_edp(intel_dp))
1780 drm_dbg_kms(&i915->drm, "\n");
1782 intel_panel_enable_backlight(crtc_state, conn_state);
1783 intel_pps_backlight_on(intel_dp);
1786 /* Disable backlight PP control and backlight PWM. */
1787 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1789 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1790 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1792 if (!intel_dp_is_edp(intel_dp))
1795 drm_dbg_kms(&i915->drm, "\n");
1797 intel_pps_backlight_off(intel_dp);
1798 intel_panel_disable_backlight(old_conn_state);
1801 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1804 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1805 * be capable of signalling downstream hpd with a long pulse.
1806 * Whether or not that means D3 is safe to use is not clear,
1807 * but let's assume so until proven otherwise.
1809 * FIXME should really check all downstream ports...
1811 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1812 drm_dp_is_branch(intel_dp->dpcd) &&
1813 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1816 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1817 const struct intel_crtc_state *crtc_state,
1820 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1823 if (!crtc_state->dsc.compression_enable)
1826 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1827 enable ? DP_DECOMPRESSION_EN : 0);
1829 drm_dbg_kms(&i915->drm,
1830 "Failed to %s sink decompression state\n",
1831 enabledisable(enable));
1835 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1837 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1838 u8 oui[] = { 0x00, 0xaa, 0x01 };
1842 * During driver init, we want to be careful and avoid changing the source OUI if it's
1843 * already set to what we want, so as to avoid clearing any state by accident
1846 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1847 drm_err(&i915->drm, "Failed to read source OUI\n");
1849 if (memcmp(oui, buf, sizeof(oui)) == 0)
1853 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
1854 drm_err(&i915->drm, "Failed to write source OUI\n");
1857 /* If the device supports it, try to set the power state appropriately */
1858 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
1860 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1861 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1864 /* Should have a valid DPCD by this point */
1865 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1868 if (mode != DP_SET_POWER_D0) {
1869 if (downstream_hpd_needs_d0(intel_dp))
1872 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1874 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
1876 lspcon_resume(dp_to_dig_port(intel_dp));
1878 /* Write the source OUI as early as possible */
1879 if (intel_dp_is_edp(intel_dp))
1880 intel_edp_init_source_oui(intel_dp, false);
1883 * When turning on, we need to retry for 1ms to give the sink
1886 for (i = 0; i < 3; i++) {
1887 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1893 if (ret == 1 && lspcon->active)
1894 lspcon_wait_pcon_mode(lspcon);
1898 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
1899 encoder->base.base.id, encoder->base.name,
1900 mode == DP_SET_POWER_D0 ? "D0" : "D3");
1904 intel_dp_get_dpcd(struct intel_dp *intel_dp);
1907 * intel_dp_sync_state - sync the encoder state during init/resume
1908 * @encoder: intel encoder to sync
1909 * @crtc_state: state for the CRTC connected to the encoder
1911 * Sync any state stored in the encoder wrt. HW state during driver init
1912 * and system resume.
1914 void intel_dp_sync_state(struct intel_encoder *encoder,
1915 const struct intel_crtc_state *crtc_state)
1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1920 * Don't clobber DPCD if it's been already read out during output
1921 * setup (eDP) or detect.
1923 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1924 intel_dp_get_dpcd(intel_dp);
1926 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1927 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1930 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
1931 struct intel_crtc_state *crtc_state)
1933 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1934 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1937 * If BIOS has set an unsupported or non-standard link rate for some
1938 * reason force an encoder recompute and full modeset.
1940 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
1941 crtc_state->port_clock) < 0) {
1942 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
1943 crtc_state->uapi.connectors_changed = true;
1948 * FIXME hack to force full modeset when DSC is being used.
1950 * As long as we do not have full state readout and config comparison
1951 * of crtc_state->dsc, we have no way to ensure reliable fastset.
1952 * Remove once we have readout for DSC.
1954 if (crtc_state->dsc.compression_enable) {
1955 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
1956 crtc_state->uapi.mode_changed = true;
1960 if (CAN_PSR(intel_dp)) {
1961 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
1962 crtc_state->uapi.mode_changed = true;
1969 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
1971 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1973 /* Clear the cached register set to avoid using stale values */
1975 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
1977 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
1978 intel_dp->pcon_dsc_dpcd,
1979 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
1980 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
1981 DP_PCON_DSC_ENCODER);
1983 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
1984 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
1987 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
1989 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
1992 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
1993 if (frl_bw_mask & (1 << i))
1999 static int intel_dp_pcon_set_frl_mask(int max_frl)
2003 return DP_PCON_FRL_BW_MASK_48GBPS;
2005 return DP_PCON_FRL_BW_MASK_40GBPS;
2007 return DP_PCON_FRL_BW_MASK_32GBPS;
2009 return DP_PCON_FRL_BW_MASK_24GBPS;
2011 return DP_PCON_FRL_BW_MASK_18GBPS;
2013 return DP_PCON_FRL_BW_MASK_9GBPS;
2019 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2021 struct intel_connector *intel_connector = intel_dp->attached_connector;
2022 struct drm_connector *connector = &intel_connector->base;
2024 int max_lanes, rate_per_lane;
2025 int max_dsc_lanes, dsc_rate_per_lane;
2027 max_lanes = connector->display_info.hdmi.max_lanes;
2028 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2029 max_frl_rate = max_lanes * rate_per_lane;
2031 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2032 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2033 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2034 if (max_dsc_lanes && dsc_rate_per_lane)
2035 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2038 return max_frl_rate;
2041 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2043 #define TIMEOUT_FRL_READY_MS 500
2044 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2046 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2047 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2048 u8 max_frl_bw_mask = 0, frl_trained_mask;
2051 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2055 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2056 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2058 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2059 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2061 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2063 if (max_frl_bw <= 0)
2066 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2069 /* Wait for PCON to be FRL Ready */
2070 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2075 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2076 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2077 DP_PCON_ENABLE_SEQUENTIAL_LINK);
2080 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2081 DP_PCON_FRL_LINK_TRAIN_NORMAL);
2084 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2088 * Wait for FRL to be completed
2089 * Check if the HDMI Link is up and active.
2091 wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2096 /* Verify HDMI Link configuration shows FRL Mode */
2097 if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2098 DP_PCON_HDMI_MODE_FRL) {
2099 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2102 drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2104 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2105 intel_dp->frl.is_trained = true;
2106 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2111 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2113 if (drm_dp_is_branch(intel_dp->dpcd) &&
2114 intel_dp->has_hdmi_sink &&
2115 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2121 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2123 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2126 * Always go for FRL training if:
2127 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2130 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2131 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2132 intel_dp->frl.is_trained)
2135 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2138 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2139 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2140 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2142 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2143 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2145 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2150 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2152 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2154 return intel_hdmi_dsc_get_slice_height(vactive);
2158 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2159 const struct intel_crtc_state *crtc_state)
2161 struct intel_connector *intel_connector = intel_dp->attached_connector;
2162 struct drm_connector *connector = &intel_connector->base;
2163 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2164 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2165 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2166 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2168 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2169 pcon_max_slice_width,
2170 hdmi_max_slices, hdmi_throughput);
2174 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2175 const struct intel_crtc_state *crtc_state,
2176 int num_slices, int slice_width)
2178 struct intel_connector *intel_connector = intel_dp->attached_connector;
2179 struct drm_connector *connector = &intel_connector->base;
2180 int output_format = crtc_state->output_format;
2181 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2182 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2183 int hdmi_max_chunk_bytes =
2184 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2186 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2187 num_slices, output_format, hdmi_all_bpp,
2188 hdmi_max_chunk_bytes);
2192 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2193 const struct intel_crtc_state *crtc_state)
2201 struct intel_connector *intel_connector = intel_dp->attached_connector;
2202 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2203 struct drm_connector *connector;
2204 bool hdmi_is_dsc_1_2;
2206 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2209 if (!intel_connector)
2211 connector = &intel_connector->base;
2212 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2214 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2218 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2222 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2226 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2229 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2230 num_slices, slice_width);
2231 if (!bits_per_pixel)
2234 pps_param[0] = slice_height & 0xFF;
2235 pps_param[1] = slice_height >> 8;
2236 pps_param[2] = slice_width & 0xFF;
2237 pps_param[3] = slice_width >> 8;
2238 pps_param[4] = bits_per_pixel & 0xFF;
2239 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2241 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2243 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2246 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2247 const struct intel_crtc_state *crtc_state)
2249 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2252 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2255 if (!drm_dp_is_branch(intel_dp->dpcd))
2258 tmp = intel_dp->has_hdmi_sink ?
2259 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2261 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2262 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2263 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2264 enabledisable(intel_dp->has_hdmi_sink));
2266 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2267 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2269 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2270 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2271 drm_dbg_kms(&i915->drm,
2272 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2273 enabledisable(intel_dp->dfp.ycbcr_444_to_420));
2276 if (intel_dp->dfp.rgb_to_ycbcr) {
2280 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2281 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2284 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2286 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2287 intel_dp->downstream_ports,
2288 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2289 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2290 intel_dp->downstream_ports,
2291 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2292 switch (crtc_state->infoframes.vsc.colorimetry) {
2293 case DP_COLORIMETRY_BT2020_RGB:
2294 case DP_COLORIMETRY_BT2020_YCC:
2296 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2298 case DP_COLORIMETRY_BT709_YCC:
2299 case DP_COLORIMETRY_XVYCC_709:
2301 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2308 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2309 drm_dbg_kms(&i915->drm,
2310 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2311 enabledisable(tmp));
2315 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2319 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2322 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2325 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2327 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2330 * Clear the cached register set to avoid using stale values
2331 * for the sinks that do not support DSC.
2333 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2335 /* Clear fec_capable to avoid using stale values */
2336 intel_dp->fec_capable = 0;
2338 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2339 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2340 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2341 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2343 sizeof(intel_dp->dsc_dpcd)) < 0)
2345 "Failed to read DPCD register 0x%x\n",
2348 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2349 (int)sizeof(intel_dp->dsc_dpcd),
2350 intel_dp->dsc_dpcd);
2352 /* FEC is supported only on DP 1.4 */
2353 if (!intel_dp_is_edp(intel_dp) &&
2354 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2355 &intel_dp->fec_capable) < 0)
2357 "Failed to read FEC DPCD register\n");
2359 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2360 intel_dp->fec_capable);
2364 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2365 struct drm_display_mode *mode)
2367 struct intel_dp *intel_dp = intel_attached_dp(connector);
2368 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2369 int n = intel_dp->mso_link_count;
2370 int overlap = intel_dp->mso_pixel_overlap;
2375 mode->hdisplay = (mode->hdisplay - overlap) * n;
2376 mode->hsync_start = (mode->hsync_start - overlap) * n;
2377 mode->hsync_end = (mode->hsync_end - overlap) * n;
2378 mode->htotal = (mode->htotal - overlap) * n;
2381 drm_mode_set_name(mode);
2383 drm_dbg_kms(&i915->drm,
2384 "[CONNECTOR:%d:%s] using generated MSO mode: ",
2385 connector->base.base.id, connector->base.name);
2386 drm_mode_debug_printmodeline(mode);
2389 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2391 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2394 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2397 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2398 drm_err(&i915->drm, "Failed to read MSO cap\n");
2402 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2403 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2404 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2405 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2410 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
2411 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
2412 if (!HAS_MSO(i915)) {
2413 drm_err(&i915->drm, "No source MSO support, disabling\n");
2418 intel_dp->mso_link_count = mso;
2419 intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
2423 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2425 struct drm_i915_private *dev_priv =
2426 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2428 /* this function is meant to be called only once */
2429 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2431 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2434 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2435 drm_dp_is_branch(intel_dp->dpcd));
2438 * Read the eDP display control registers.
2440 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2441 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2442 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2443 * method). The display control registers should read zero if they're
2444 * not supported anyway.
2446 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2447 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2448 sizeof(intel_dp->edp_dpcd))
2449 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2450 (int)sizeof(intel_dp->edp_dpcd),
2451 intel_dp->edp_dpcd);
2454 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2455 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2457 intel_psr_init_dpcd(intel_dp);
2459 /* Read the eDP 1.4+ supported link rates. */
2460 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2461 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2464 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2465 sink_rates, sizeof(sink_rates));
2467 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2468 int val = le16_to_cpu(sink_rates[i]);
2473 /* Value read multiplied by 200kHz gives the per-lane
2474 * link rate in kHz. The source rates are, however,
2475 * stored in terms of LS_Clk kHz. The full conversion
2476 * back to symbols is
2477 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2479 intel_dp->sink_rates[i] = (val * 200) / 10;
2481 intel_dp->num_sink_rates = i;
2485 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2486 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2488 if (intel_dp->num_sink_rates)
2489 intel_dp->use_rate_select = true;
2491 intel_dp_set_sink_rates(intel_dp);
2493 intel_dp_set_common_rates(intel_dp);
2495 /* Read the eDP DSC DPCD registers */
2496 if (DISPLAY_VER(dev_priv) >= 10)
2497 intel_dp_get_dsc_sink_cap(intel_dp);
2500 * If needed, program our source OUI so we can make various Intel-specific AUX services
2501 * available (such as HDR backlight controls)
2503 intel_edp_init_source_oui(intel_dp, true);
2505 intel_edp_mso_init(intel_dp);
2511 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2513 if (!intel_dp->attached_connector)
2516 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2522 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2526 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2530 * Don't clobber cached eDP rates. Also skip re-reading
2531 * the OUI/ID since we know it won't change.
2533 if (!intel_dp_is_edp(intel_dp)) {
2534 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2535 drm_dp_is_branch(intel_dp->dpcd));
2537 intel_dp_set_sink_rates(intel_dp);
2538 intel_dp_set_common_rates(intel_dp);
2541 if (intel_dp_has_sink_count(intel_dp)) {
2542 ret = drm_dp_read_sink_count(&intel_dp->aux);
2547 * Sink count can change between short pulse hpd hence
2548 * a member variable in intel_dp will track any changes
2549 * between short pulse interrupts.
2551 intel_dp->sink_count = ret;
2554 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2555 * a dongle is present but no display. Unless we require to know
2556 * if a dongle is present or not, we don't need to update
2557 * downstream port information. So, an early return here saves
2558 * time from performing other operations which are not required.
2560 if (!intel_dp->sink_count)
2564 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2565 intel_dp->downstream_ports) == 0;
2569 intel_dp_can_mst(struct intel_dp *intel_dp)
2571 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2573 return i915->params.enable_dp_mst &&
2574 intel_dp->can_mst &&
2575 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2579 intel_dp_configure_mst(struct intel_dp *intel_dp)
2581 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2582 struct intel_encoder *encoder =
2583 &dp_to_dig_port(intel_dp)->base;
2584 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2586 drm_dbg_kms(&i915->drm,
2587 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2588 encoder->base.base.id, encoder->base.name,
2589 yesno(intel_dp->can_mst), yesno(sink_can_mst),
2590 yesno(i915->params.enable_dp_mst));
2592 if (!intel_dp->can_mst)
2595 intel_dp->is_mst = sink_can_mst &&
2596 i915->params.enable_dp_mst;
2598 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2603 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2605 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2606 sink_irq_vector, DP_DPRX_ESI_LEN) ==
2611 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2612 const struct drm_connector_state *conn_state)
2615 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2616 * of Color Encoding Format and Content Color Gamut], in order to
2617 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2619 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2622 switch (conn_state->colorspace) {
2623 case DRM_MODE_COLORIMETRY_SYCC_601:
2624 case DRM_MODE_COLORIMETRY_OPYCC_601:
2625 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2626 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2627 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2636 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2637 struct dp_sdp *sdp, size_t size)
2639 size_t length = sizeof(struct dp_sdp);
2644 memset(sdp, 0, size);
2647 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2648 * VSC SDP Header Bytes
2650 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2651 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2652 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2653 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2656 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2659 if (vsc->revision != 0x5)
2662 /* VSC SDP Payload for DB16 through DB18 */
2663 /* Pixel Encoding and Colorimetry Formats */
2664 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2665 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2672 sdp->db[17] = 0x1; /* DB17[3:0] */
2684 MISSING_CASE(vsc->bpc);
2687 /* Dynamic Range and Component Bit Depth */
2688 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2689 sdp->db[17] |= 0x80; /* DB17[7] */
2692 sdp->db[18] = vsc->content_type & 0x7;
2699 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2703 size_t length = sizeof(struct dp_sdp);
2704 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2705 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2711 memset(sdp, 0, size);
2713 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2715 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2719 if (len != infoframe_size) {
2720 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2725 * Set up the infoframe sdp packet for HDR static metadata.
2726 * Prepare VSC Header for SU as per DP 1.4a spec,
2727 * Table 2-100 and Table 2-101
2730 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2731 sdp->sdp_header.HB0 = 0;
2733 * Packet Type 80h + Non-audio INFOFRAME Type value
2734 * HDMI_INFOFRAME_TYPE_DRM: 0x87
2735 * - 80h + Non-audio INFOFRAME Type value
2736 * - InfoFrame Type: 0x07
2737 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2739 sdp->sdp_header.HB1 = drm_infoframe->type;
2741 * Least Significant Eight Bits of (Data Byte Count – 1)
2742 * infoframe_size - 1
2744 sdp->sdp_header.HB2 = 0x1D;
2745 /* INFOFRAME SDP Version Number */
2746 sdp->sdp_header.HB3 = (0x13 << 2);
2747 /* CTA Header Byte 2 (INFOFRAME Version Number) */
2748 sdp->db[0] = drm_infoframe->version;
2749 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2750 sdp->db[1] = drm_infoframe->length;
2752 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2753 * HDMI_INFOFRAME_HEADER_SIZE
2755 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2756 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2757 HDMI_DRM_INFOFRAME_SIZE);
2760 * Size of DP infoframe sdp packet for HDR static metadata consists of
2761 * - DP SDP Header(struct dp_sdp_header): 4 bytes
2762 * - Two Data Blocks: 2 bytes
2763 * CTA Header Byte2 (INFOFRAME Version Number)
2764 * CTA Header Byte3 (Length of INFOFRAME)
2765 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2767 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2768 * infoframe size. But GEN11+ has larger than that size, write_infoframe
2769 * will pad rest of the size.
2771 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2774 static void intel_write_dp_sdp(struct intel_encoder *encoder,
2775 const struct intel_crtc_state *crtc_state,
2778 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2780 struct dp_sdp sdp = {};
2783 if ((crtc_state->infoframes.enable &
2784 intel_hdmi_infoframe_enable(type)) == 0)
2789 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
2792 case HDMI_PACKET_TYPE_GAMUT_METADATA:
2793 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
2801 if (drm_WARN_ON(&dev_priv->drm, len < 0))
2804 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
2807 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
2808 const struct intel_crtc_state *crtc_state,
2809 struct drm_dp_vsc_sdp *vsc)
2811 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2812 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2813 struct dp_sdp sdp = {};
2816 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
2818 if (drm_WARN_ON(&dev_priv->drm, len < 0))
2821 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
2825 void intel_dp_set_infoframes(struct intel_encoder *encoder,
2827 const struct intel_crtc_state *crtc_state,
2828 const struct drm_connector_state *conn_state)
2830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2831 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
2832 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
2833 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
2834 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
2835 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
2837 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
2838 /* When PSR is enabled, this routine doesn't disable VSC DIP */
2839 if (!crtc_state->has_psr)
2840 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
2842 intel_de_write(dev_priv, reg, val);
2843 intel_de_posting_read(dev_priv, reg);
2848 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2849 if (!crtc_state->has_psr)
2850 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
2852 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
2855 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
2856 const void *buffer, size_t size)
2858 const struct dp_sdp *sdp = buffer;
2860 if (size < sizeof(struct dp_sdp))
2863 memset(vsc, 0, sizeof(*vsc));
2865 if (sdp->sdp_header.HB0 != 0)
2868 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
2871 vsc->sdp_type = sdp->sdp_header.HB1;
2872 vsc->revision = sdp->sdp_header.HB2;
2873 vsc->length = sdp->sdp_header.HB3;
2875 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
2876 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
2878 * - HB2 = 0x2, HB3 = 0x8
2879 * VSC SDP supporting 3D stereo + PSR
2880 * - HB2 = 0x4, HB3 = 0xe
2881 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
2882 * first scan line of the SU region (applies to eDP v1.4b
2886 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
2888 * - HB2 = 0x5, HB3 = 0x13
2889 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
2892 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
2893 vsc->colorimetry = sdp->db[16] & 0xf;
2894 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
2896 switch (sdp->db[17] & 0x7) {
2913 MISSING_CASE(sdp->db[17] & 0x7);
2917 vsc->content_type = sdp->db[18] & 0x7;
2926 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
2927 const void *buffer, size_t size)
2931 const struct dp_sdp *sdp = buffer;
2933 if (size < sizeof(struct dp_sdp))
2936 if (sdp->sdp_header.HB0 != 0)
2939 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
2943 * Least Significant Eight Bits of (Data Byte Count – 1)
2944 * 1Dh (i.e., Data Byte Count = 30 bytes).
2946 if (sdp->sdp_header.HB2 != 0x1D)
2949 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
2950 if ((sdp->sdp_header.HB3 & 0x3) != 0)
2953 /* INFOFRAME SDP Version Number */
2954 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
2957 /* CTA Header Byte 2 (INFOFRAME Version Number) */
2958 if (sdp->db[0] != 1)
2961 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2962 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
2965 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
2966 HDMI_DRM_INFOFRAME_SIZE);
2971 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
2972 struct intel_crtc_state *crtc_state,
2973 struct drm_dp_vsc_sdp *vsc)
2975 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2977 unsigned int type = DP_SDP_VSC;
2978 struct dp_sdp sdp = {};
2981 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2982 if (crtc_state->has_psr)
2985 if ((crtc_state->infoframes.enable &
2986 intel_hdmi_infoframe_enable(type)) == 0)
2989 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
2991 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
2994 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
2997 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
2998 struct intel_crtc_state *crtc_state,
2999 struct hdmi_drm_infoframe *drm_infoframe)
3001 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3003 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3004 struct dp_sdp sdp = {};
3007 if ((crtc_state->infoframes.enable &
3008 intel_hdmi_infoframe_enable(type)) == 0)
3011 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3014 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3018 drm_dbg_kms(&dev_priv->drm,
3019 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3022 void intel_read_dp_sdp(struct intel_encoder *encoder,
3023 struct intel_crtc_state *crtc_state,
3028 intel_read_dp_vsc_sdp(encoder, crtc_state,
3029 &crtc_state->infoframes.vsc);
3031 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3032 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3033 &crtc_state->infoframes.drm.drm);
3041 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3043 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3046 u8 test_lane_count, test_link_bw;
3050 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3051 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3055 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3058 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3060 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3063 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3066 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3068 /* Validate the requested link rate and lane count */
3069 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3073 intel_dp->compliance.test_lane_count = test_lane_count;
3074 intel_dp->compliance.test_link_rate = test_link_rate;
3079 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3081 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3084 __be16 h_width, v_height;
3087 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3088 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3091 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3094 if (test_pattern != DP_COLOR_RAMP)
3097 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3100 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3104 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3107 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3111 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3114 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3117 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3119 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3121 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3122 case DP_TEST_BIT_DEPTH_6:
3123 intel_dp->compliance.test_data.bpc = 6;
3125 case DP_TEST_BIT_DEPTH_8:
3126 intel_dp->compliance.test_data.bpc = 8;
3132 intel_dp->compliance.test_data.video_pattern = test_pattern;
3133 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3134 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3135 /* Set test active flag here so userspace doesn't interrupt things */
3136 intel_dp->compliance.test_active = true;
3141 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3143 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3144 u8 test_result = DP_TEST_ACK;
3145 struct intel_connector *intel_connector = intel_dp->attached_connector;
3146 struct drm_connector *connector = &intel_connector->base;
3148 if (intel_connector->detect_edid == NULL ||
3149 connector->edid_corrupt ||
3150 intel_dp->aux.i2c_defer_count > 6) {
3151 /* Check EDID read for NACKs, DEFERs and corruption
3152 * (DP CTS 1.2 Core r1.1)
3153 * 4.2.2.4 : Failed EDID read, I2C_NAK
3154 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3155 * 4.2.2.6 : EDID corruption detected
3156 * Use failsafe mode for all cases
3158 if (intel_dp->aux.i2c_nack_count > 0 ||
3159 intel_dp->aux.i2c_defer_count > 0)
3160 drm_dbg_kms(&i915->drm,
3161 "EDID read had %d NACKs, %d DEFERs\n",
3162 intel_dp->aux.i2c_nack_count,
3163 intel_dp->aux.i2c_defer_count);
3164 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3166 struct edid *block = intel_connector->detect_edid;
3168 /* We have to write the checksum
3169 * of the last block read
3171 block += intel_connector->detect_edid->extensions;
3173 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3174 block->checksum) <= 0)
3175 drm_dbg_kms(&i915->drm,
3176 "Failed to write EDID checksum\n");
3178 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3179 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3182 /* Set test active flag here so userspace doesn't interrupt things */
3183 intel_dp->compliance.test_active = true;
3188 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3189 const struct intel_crtc_state *crtc_state)
3191 struct drm_i915_private *dev_priv =
3192 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3193 struct drm_dp_phy_test_params *data =
3194 &intel_dp->compliance.test_data.phytest;
3195 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3196 enum pipe pipe = crtc->pipe;
3199 switch (data->phy_pattern) {
3200 case DP_PHY_TEST_PATTERN_NONE:
3201 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3202 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3204 case DP_PHY_TEST_PATTERN_D10_2:
3205 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3206 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3207 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3209 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3210 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3211 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3212 DDI_DP_COMP_CTL_ENABLE |
3213 DDI_DP_COMP_CTL_SCRAMBLED_0);
3215 case DP_PHY_TEST_PATTERN_PRBS7:
3216 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3217 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3218 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3220 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3222 * FIXME: Ideally pattern should come from DPCD 0x250. As
3223 * current firmware of DPR-100 could not set it, so hardcoding
3224 * now for complaince test.
3226 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3227 pattern_val = 0x3e0f83e0;
3228 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3229 pattern_val = 0x0f83e0f8;
3230 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3231 pattern_val = 0x0000f83e;
3232 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3233 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3234 DDI_DP_COMP_CTL_ENABLE |
3235 DDI_DP_COMP_CTL_CUSTOM80);
3237 case DP_PHY_TEST_PATTERN_CP2520:
3239 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3240 * current firmware of DPR-100 could not set it, so hardcoding
3241 * now for complaince test.
3243 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3245 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3246 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3250 WARN(1, "Invalid Phy Test Pattern\n");
3255 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3256 const struct intel_crtc_state *crtc_state)
3258 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3259 struct drm_device *dev = dig_port->base.base.dev;
3260 struct drm_i915_private *dev_priv = to_i915(dev);
3261 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3262 enum pipe pipe = crtc->pipe;
3263 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3265 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3266 TRANS_DDI_FUNC_CTL(pipe));
3267 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3268 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3270 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3271 TGL_TRANS_DDI_PORT_MASK);
3272 trans_conf_value &= ~PIPECONF_ENABLE;
3273 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3275 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3276 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3277 trans_ddi_func_ctl_value);
3278 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3282 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3283 const struct intel_crtc_state *crtc_state)
3285 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3286 struct drm_device *dev = dig_port->base.base.dev;
3287 struct drm_i915_private *dev_priv = to_i915(dev);
3288 enum port port = dig_port->base.port;
3289 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3290 enum pipe pipe = crtc->pipe;
3291 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3293 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3294 TRANS_DDI_FUNC_CTL(pipe));
3295 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3296 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3298 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3299 TGL_TRANS_DDI_SELECT_PORT(port);
3300 trans_conf_value |= PIPECONF_ENABLE;
3301 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3303 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3304 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3305 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3306 trans_ddi_func_ctl_value);
3309 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3310 const struct intel_crtc_state *crtc_state)
3312 struct drm_dp_phy_test_params *data =
3313 &intel_dp->compliance.test_data.phytest;
3314 u8 link_status[DP_LINK_STATUS_SIZE];
3316 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3318 DRM_DEBUG_KMS("failed to get link status\n");
3322 /* retrieve vswing & pre-emphasis setting */
3323 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3326 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3328 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3330 intel_dp_phy_pattern_update(intel_dp, crtc_state);
3332 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3334 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3335 intel_dp->train_set, crtc_state->lane_count);
3337 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3338 link_status[DP_DPCD_REV]);
3341 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3343 struct drm_dp_phy_test_params *data =
3344 &intel_dp->compliance.test_data.phytest;
3346 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3347 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3351 /* Set test active flag here so userspace doesn't interrupt things */
3352 intel_dp->compliance.test_active = true;
3357 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3359 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3360 u8 response = DP_TEST_NAK;
3364 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3366 drm_dbg_kms(&i915->drm,
3367 "Could not read test request from sink\n");
3372 case DP_TEST_LINK_TRAINING:
3373 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3374 response = intel_dp_autotest_link_training(intel_dp);
3376 case DP_TEST_LINK_VIDEO_PATTERN:
3377 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3378 response = intel_dp_autotest_video_pattern(intel_dp);
3380 case DP_TEST_LINK_EDID_READ:
3381 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3382 response = intel_dp_autotest_edid(intel_dp);
3384 case DP_TEST_LINK_PHY_TEST_PATTERN:
3385 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3386 response = intel_dp_autotest_phy_pattern(intel_dp);
3389 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3394 if (response & DP_TEST_ACK)
3395 intel_dp->compliance.test_type = request;
3398 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3400 drm_dbg_kms(&i915->drm,
3401 "Could not write test response to sink\n");
3405 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3407 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3409 if (esi[1] & DP_CP_IRQ) {
3410 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3416 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3417 * @intel_dp: Intel DP struct
3419 * Read any pending MST interrupts, call MST core to handle these and ack the
3420 * interrupts. Check if the main and AUX link state is ok.
3423 * - %true if pending interrupts were serviced (or no interrupts were
3424 * pending) w/o detecting an error condition.
3425 * - %false if an error condition - like AUX failure or a loss of link - is
3426 * detected, which needs servicing from the hotplug work.
3429 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3431 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3432 bool link_ok = true;
3434 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3438 * The +2 is because DP_DPRX_ESI_LEN is 14, but we then
3439 * pass in "esi+10" to drm_dp_channel_eq_ok(), which
3440 * takes a 6-byte array. So we actually need 16 bytes
3443 * Somebody who knows what the limits actually are
3444 * should check this, but for now this is at least
3445 * harmless and avoids a valid compiler warning about
3446 * using more of the array than we have allocated.
3448 u8 esi[DP_DPRX_ESI_LEN+2] = {};
3452 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3453 drm_dbg_kms(&i915->drm,
3454 "failed to get ESI - device may have failed\n");
3460 /* check link status - esi[10] = 0x200c */
3461 if (intel_dp->active_mst_links > 0 && link_ok &&
3462 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3463 drm_dbg_kms(&i915->drm,
3464 "channel EQ not ok, retraining\n");
3468 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3470 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3475 for (retry = 0; retry < 3; retry++) {
3478 wret = drm_dp_dpcd_write(&intel_dp->aux,
3479 DP_SINK_COUNT_ESI+1,
3490 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3495 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3496 if (intel_dp->frl.is_trained && !is_active) {
3497 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3500 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
3501 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3504 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3506 /* Restart FRL training or fall back to TMDS mode */
3507 intel_dp_check_frl_training(intel_dp);
3512 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3514 u8 link_status[DP_LINK_STATUS_SIZE];
3516 if (!intel_dp->link_trained)
3520 * While PSR source HW is enabled, it will control main-link sending
3521 * frames, enabling and disabling it so trying to do a retrain will fail
3522 * as the link would or not be on or it could mix training patterns
3523 * and frame data at the same time causing retrain to fail.
3524 * Also when exiting PSR, HW will retrain the link anyways fixing
3525 * any link status error.
3527 if (intel_psr_enabled(intel_dp))
3530 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3535 * Validate the cached values of intel_dp->link_rate and
3536 * intel_dp->lane_count before attempting to retrain.
3538 * FIXME would be nice to user the crtc state here, but since
3539 * we need to call this from the short HPD handler that seems
3542 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3543 intel_dp->lane_count))
3546 /* Retrain if Channel EQ or CR not ok */
3547 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3550 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3551 const struct drm_connector_state *conn_state)
3553 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3554 struct intel_encoder *encoder;
3557 if (!conn_state->best_encoder)
3561 encoder = &dp_to_dig_port(intel_dp)->base;
3562 if (conn_state->best_encoder == &encoder->base)
3566 for_each_pipe(i915, pipe) {
3567 encoder = &intel_dp->mst_encoders[pipe]->base;
3568 if (conn_state->best_encoder == &encoder->base)
3575 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3576 struct drm_modeset_acquire_ctx *ctx,
3579 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3580 struct drm_connector_list_iter conn_iter;
3581 struct intel_connector *connector;
3586 if (!intel_dp_needs_link_retrain(intel_dp))
3589 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3590 for_each_intel_connector_iter(connector, &conn_iter) {
3591 struct drm_connector_state *conn_state =
3592 connector->base.state;
3593 struct intel_crtc_state *crtc_state;
3594 struct intel_crtc *crtc;
3596 if (!intel_dp_has_connector(intel_dp, conn_state))
3599 crtc = to_intel_crtc(conn_state->crtc);
3603 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3607 crtc_state = to_intel_crtc_state(crtc->base.state);
3609 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3611 if (!crtc_state->hw.active)
3614 if (conn_state->commit &&
3615 !try_wait_for_completion(&conn_state->commit->hw_done))
3618 *crtc_mask |= drm_crtc_mask(&crtc->base);
3620 drm_connector_list_iter_end(&conn_iter);
3622 if (!intel_dp_needs_link_retrain(intel_dp))
3628 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3630 struct intel_connector *connector = intel_dp->attached_connector;
3632 return connector->base.status == connector_status_connected ||
3636 int intel_dp_retrain_link(struct intel_encoder *encoder,
3637 struct drm_modeset_acquire_ctx *ctx)
3639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3640 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3641 struct intel_crtc *crtc;
3645 if (!intel_dp_is_connected(intel_dp))
3648 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3653 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
3660 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3661 encoder->base.base.id, encoder->base.name);
3663 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3664 const struct intel_crtc_state *crtc_state =
3665 to_intel_crtc_state(crtc->base.state);
3667 /* Suppress underruns caused by re-training */
3668 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3669 if (crtc_state->has_pch_encoder)
3670 intel_set_pch_fifo_underrun_reporting(dev_priv,
3671 intel_crtc_pch_transcoder(crtc), false);
3674 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3675 const struct intel_crtc_state *crtc_state =
3676 to_intel_crtc_state(crtc->base.state);
3678 /* retrain on the MST master transcoder */
3679 if (DISPLAY_VER(dev_priv) >= 12 &&
3680 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3681 !intel_dp_mst_is_master_trans(crtc_state))
3684 intel_dp_check_frl_training(intel_dp);
3685 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3686 intel_dp_start_link_train(intel_dp, crtc_state);
3687 intel_dp_stop_link_train(intel_dp, crtc_state);
3691 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3692 const struct intel_crtc_state *crtc_state =
3693 to_intel_crtc_state(crtc->base.state);
3695 /* Keep underrun reporting disabled until things are stable */
3696 intel_wait_for_vblank(dev_priv, crtc->pipe);
3698 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3699 if (crtc_state->has_pch_encoder)
3700 intel_set_pch_fifo_underrun_reporting(dev_priv,
3701 intel_crtc_pch_transcoder(crtc), true);
3707 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3708 struct drm_modeset_acquire_ctx *ctx,
3711 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3712 struct drm_connector_list_iter conn_iter;
3713 struct intel_connector *connector;
3718 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3719 for_each_intel_connector_iter(connector, &conn_iter) {
3720 struct drm_connector_state *conn_state =
3721 connector->base.state;
3722 struct intel_crtc_state *crtc_state;
3723 struct intel_crtc *crtc;
3725 if (!intel_dp_has_connector(intel_dp, conn_state))
3728 crtc = to_intel_crtc(conn_state->crtc);
3732 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3736 crtc_state = to_intel_crtc_state(crtc->base.state);
3738 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3740 if (!crtc_state->hw.active)
3743 if (conn_state->commit &&
3744 !try_wait_for_completion(&conn_state->commit->hw_done))
3747 *crtc_mask |= drm_crtc_mask(&crtc->base);
3749 drm_connector_list_iter_end(&conn_iter);
3754 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
3755 struct drm_modeset_acquire_ctx *ctx)
3757 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3758 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3759 struct intel_crtc *crtc;
3763 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3768 ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
3775 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
3776 encoder->base.base.id, encoder->base.name);
3778 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3779 const struct intel_crtc_state *crtc_state =
3780 to_intel_crtc_state(crtc->base.state);
3782 /* test on the MST master transcoder */
3783 if (DISPLAY_VER(dev_priv) >= 12 &&
3784 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3785 !intel_dp_mst_is_master_trans(crtc_state))
3788 intel_dp_process_phy_request(intel_dp, crtc_state);
3795 void intel_dp_phy_test(struct intel_encoder *encoder)
3797 struct drm_modeset_acquire_ctx ctx;
3800 drm_modeset_acquire_init(&ctx, 0);
3803 ret = intel_dp_do_phy_test(encoder, &ctx);
3805 if (ret == -EDEADLK) {
3806 drm_modeset_backoff(&ctx);
3813 drm_modeset_drop_locks(&ctx);
3814 drm_modeset_acquire_fini(&ctx);
3815 drm_WARN(encoder->base.dev, ret,
3816 "Acquiring modeset locks failed with %i\n", ret);
3819 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
3821 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3824 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3827 if (drm_dp_dpcd_readb(&intel_dp->aux,
3828 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
3831 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
3833 if (val & DP_AUTOMATED_TEST_REQUEST)
3834 intel_dp_handle_test_request(intel_dp);
3836 if (val & DP_CP_IRQ)
3837 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3839 if (val & DP_SINK_SPECIFIC_IRQ)
3840 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
3843 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
3845 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3848 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3851 if (drm_dp_dpcd_readb(&intel_dp->aux,
3852 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
3853 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
3857 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3858 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
3859 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
3863 if (val & HDMI_LINK_STATUS_CHANGED)
3864 intel_dp_handle_hdmi_link_status_change(intel_dp);
3868 * According to DP spec
3871 * 2. Configure link according to Receiver Capabilities
3872 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3873 * 4. Check link status on receipt of hot-plug interrupt
3875 * intel_dp_short_pulse - handles short pulse interrupts
3876 * when full detection is not required.
3877 * Returns %true if short pulse is handled and full detection
3878 * is NOT required and %false otherwise.
3881 intel_dp_short_pulse(struct intel_dp *intel_dp)
3883 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3884 u8 old_sink_count = intel_dp->sink_count;
3888 * Clearing compliance test variables to allow capturing
3889 * of values for next automated test request.
3891 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
3894 * Now read the DPCD to see if it's actually running
3895 * If the current value of sink count doesn't match with
3896 * the value that was stored earlier or dpcd read failed
3897 * we need to do full detection
3899 ret = intel_dp_get_dpcd(intel_dp);
3901 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3902 /* No need to proceed if we are going to do full detect */
3906 intel_dp_check_device_service_irq(intel_dp);
3907 intel_dp_check_link_service_irq(intel_dp);
3909 /* Handle CEC interrupts, if any */
3910 drm_dp_cec_irq(&intel_dp->aux);
3912 /* defer to the hotplug work for link retraining if needed */
3913 if (intel_dp_needs_link_retrain(intel_dp))
3916 intel_psr_short_pulse(intel_dp);
3918 switch (intel_dp->compliance.test_type) {
3919 case DP_TEST_LINK_TRAINING:
3920 drm_dbg_kms(&dev_priv->drm,
3921 "Link Training Compliance Test requested\n");
3922 /* Send a Hotplug Uevent to userspace to start modeset */
3923 drm_kms_helper_hotplug_event(&dev_priv->drm);
3925 case DP_TEST_LINK_PHY_TEST_PATTERN:
3926 drm_dbg_kms(&dev_priv->drm,
3927 "PHY test pattern Compliance Test requested\n");
3929 * Schedule long hpd to do the test
3931 * FIXME get rid of the ad-hoc phy test modeset code
3932 * and properly incorporate it into the normal modeset.
3940 /* XXX this is probably wrong for multiple downstream ports */
3941 static enum drm_connector_status
3942 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3944 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3945 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3946 u8 *dpcd = intel_dp->dpcd;
3949 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
3950 return connector_status_connected;
3952 lspcon_resume(dig_port);
3954 if (!intel_dp_get_dpcd(intel_dp))
3955 return connector_status_disconnected;
3957 /* if there's no downstream port, we're done */
3958 if (!drm_dp_is_branch(dpcd))
3959 return connector_status_connected;
3961 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3962 if (intel_dp_has_sink_count(intel_dp) &&
3963 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3964 return intel_dp->sink_count ?
3965 connector_status_connected : connector_status_disconnected;
3968 if (intel_dp_can_mst(intel_dp))
3969 return connector_status_connected;
3971 /* If no HPD, poke DDC gently */
3972 if (drm_probe_ddc(&intel_dp->aux.ddc))
3973 return connector_status_connected;
3975 /* Well we tried, say unknown for unreliable port types */
3976 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3977 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3978 if (type == DP_DS_PORT_TYPE_VGA ||
3979 type == DP_DS_PORT_TYPE_NON_EDID)
3980 return connector_status_unknown;
3982 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3983 DP_DWN_STRM_PORT_TYPE_MASK;
3984 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3985 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3986 return connector_status_unknown;
3989 /* Anything else is out of spec, warn and ignore */
3990 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
3991 return connector_status_disconnected;
3994 static enum drm_connector_status
3995 edp_detect(struct intel_dp *intel_dp)
3997 return connector_status_connected;
4001 * intel_digital_port_connected - is the specified port connected?
4002 * @encoder: intel_encoder
4004 * In cases where there's a connector physically connected but it can't be used
4005 * by our hardware we also return false, since the rest of the driver should
4006 * pretty much treat the port as disconnected. This is relevant for type-C
4007 * (starting on ICL) where there's ownership involved.
4009 * Return %true if port is connected, %false otherwise.
4011 bool intel_digital_port_connected(struct intel_encoder *encoder)
4013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4014 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4015 bool is_connected = false;
4016 intel_wakeref_t wakeref;
4018 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4019 is_connected = dig_port->connected(encoder);
4021 return is_connected;
4024 static struct edid *
4025 intel_dp_get_edid(struct intel_dp *intel_dp)
4027 struct intel_connector *intel_connector = intel_dp->attached_connector;
4029 /* use cached edid if we have one */
4030 if (intel_connector->edid) {
4032 if (IS_ERR(intel_connector->edid))
4035 return drm_edid_duplicate(intel_connector->edid);
4037 return drm_get_edid(&intel_connector->base,
4038 &intel_dp->aux.ddc);
4042 intel_dp_update_dfp(struct intel_dp *intel_dp,
4043 const struct edid *edid)
4045 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4046 struct intel_connector *connector = intel_dp->attached_connector;
4048 intel_dp->dfp.max_bpc =
4049 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4050 intel_dp->downstream_ports, edid);
4052 intel_dp->dfp.max_dotclock =
4053 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4054 intel_dp->downstream_ports);
4056 intel_dp->dfp.min_tmds_clock =
4057 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4058 intel_dp->downstream_ports,
4060 intel_dp->dfp.max_tmds_clock =
4061 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4062 intel_dp->downstream_ports,
4065 intel_dp->dfp.pcon_max_frl_bw =
4066 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4067 intel_dp->downstream_ports);
4069 drm_dbg_kms(&i915->drm,
4070 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4071 connector->base.base.id, connector->base.name,
4072 intel_dp->dfp.max_bpc,
4073 intel_dp->dfp.max_dotclock,
4074 intel_dp->dfp.min_tmds_clock,
4075 intel_dp->dfp.max_tmds_clock,
4076 intel_dp->dfp.pcon_max_frl_bw);
4078 intel_dp_get_pcon_dsc_cap(intel_dp);
4082 intel_dp_update_420(struct intel_dp *intel_dp)
4084 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4085 struct intel_connector *connector = intel_dp->attached_connector;
4086 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4088 /* No YCbCr output support on gmch platforms */
4093 * ILK doesn't seem capable of DP YCbCr output. The
4094 * displayed image is severly corrupted. SNB+ is fine.
4096 if (IS_IRONLAKE(i915))
4099 is_branch = drm_dp_is_branch(intel_dp->dpcd);
4100 ycbcr_420_passthrough =
4101 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4102 intel_dp->downstream_ports);
4103 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4105 dp_to_dig_port(intel_dp)->lspcon.active ||
4106 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4107 intel_dp->downstream_ports);
4108 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4109 intel_dp->downstream_ports,
4110 DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4111 DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4112 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4114 if (DISPLAY_VER(i915) >= 11) {
4115 /* Let PCON convert from RGB->YCbCr if possible */
4116 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4117 intel_dp->dfp.rgb_to_ycbcr = true;
4118 intel_dp->dfp.ycbcr_444_to_420 = true;
4119 connector->base.ycbcr_420_allowed = true;
4121 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4122 intel_dp->dfp.ycbcr_444_to_420 =
4123 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4125 connector->base.ycbcr_420_allowed =
4126 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4129 /* 4:4:4->4:2:0 conversion is the only way */
4130 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4132 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4135 drm_dbg_kms(&i915->drm,
4136 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4137 connector->base.base.id, connector->base.name,
4138 yesno(intel_dp->dfp.rgb_to_ycbcr),
4139 yesno(connector->base.ycbcr_420_allowed),
4140 yesno(intel_dp->dfp.ycbcr_444_to_420));
4144 intel_dp_set_edid(struct intel_dp *intel_dp)
4146 struct intel_connector *connector = intel_dp->attached_connector;
4149 intel_dp_unset_edid(intel_dp);
4150 edid = intel_dp_get_edid(intel_dp);
4151 connector->detect_edid = edid;
4153 intel_dp_update_dfp(intel_dp, edid);
4154 intel_dp_update_420(intel_dp);
4156 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4157 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4158 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4161 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4165 intel_dp_unset_edid(struct intel_dp *intel_dp)
4167 struct intel_connector *connector = intel_dp->attached_connector;
4169 drm_dp_cec_unset_edid(&intel_dp->aux);
4170 kfree(connector->detect_edid);
4171 connector->detect_edid = NULL;
4173 intel_dp->has_hdmi_sink = false;
4174 intel_dp->has_audio = false;
4176 intel_dp->dfp.max_bpc = 0;
4177 intel_dp->dfp.max_dotclock = 0;
4178 intel_dp->dfp.min_tmds_clock = 0;
4179 intel_dp->dfp.max_tmds_clock = 0;
4181 intel_dp->dfp.pcon_max_frl_bw = 0;
4183 intel_dp->dfp.ycbcr_444_to_420 = false;
4184 connector->base.ycbcr_420_allowed = false;
4188 intel_dp_detect(struct drm_connector *connector,
4189 struct drm_modeset_acquire_ctx *ctx,
4192 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4193 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4194 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4195 struct intel_encoder *encoder = &dig_port->base;
4196 enum drm_connector_status status;
4198 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4199 connector->base.id, connector->name);
4200 drm_WARN_ON(&dev_priv->drm,
4201 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4203 if (!INTEL_DISPLAY_ENABLED(dev_priv))
4204 return connector_status_disconnected;
4206 /* Can't disconnect eDP */
4207 if (intel_dp_is_edp(intel_dp))
4208 status = edp_detect(intel_dp);
4209 else if (intel_digital_port_connected(encoder))
4210 status = intel_dp_detect_dpcd(intel_dp);
4212 status = connector_status_disconnected;
4214 if (status == connector_status_disconnected) {
4215 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4216 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4218 if (intel_dp->is_mst) {
4219 drm_dbg_kms(&dev_priv->drm,
4220 "MST device may have disappeared %d vs %d\n",
4222 intel_dp->mst_mgr.mst_state);
4223 intel_dp->is_mst = false;
4224 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4231 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4232 if (DISPLAY_VER(dev_priv) >= 11)
4233 intel_dp_get_dsc_sink_cap(intel_dp);
4235 intel_dp_configure_mst(intel_dp);
4238 * TODO: Reset link params when switching to MST mode, until MST
4239 * supports link training fallback params.
4241 if (intel_dp->reset_link_params || intel_dp->is_mst) {
4242 /* Initial max link lane count */
4243 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4245 /* Initial max link rate */
4246 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4248 intel_dp->reset_link_params = false;
4251 intel_dp_print_rates(intel_dp);
4253 if (intel_dp->is_mst) {
4255 * If we are in MST mode then this connector
4256 * won't appear connected or have anything
4259 status = connector_status_disconnected;
4264 * Some external monitors do not signal loss of link synchronization
4265 * with an IRQ_HPD, so force a link status check.
4267 if (!intel_dp_is_edp(intel_dp)) {
4270 ret = intel_dp_retrain_link(encoder, ctx);
4276 * Clearing NACK and defer counts to get their exact values
4277 * while reading EDID which are required by Compliance tests
4278 * 4.2.2.4 and 4.2.2.5
4280 intel_dp->aux.i2c_nack_count = 0;
4281 intel_dp->aux.i2c_defer_count = 0;
4283 intel_dp_set_edid(intel_dp);
4284 if (intel_dp_is_edp(intel_dp) ||
4285 to_intel_connector(connector)->detect_edid)
4286 status = connector_status_connected;
4288 intel_dp_check_device_service_irq(intel_dp);
4291 if (status != connector_status_connected && !intel_dp->is_mst)
4292 intel_dp_unset_edid(intel_dp);
4295 * Make sure the refs for power wells enabled during detect are
4296 * dropped to avoid a new detect cycle triggered by HPD polling.
4298 intel_display_power_flush_work(dev_priv);
4300 if (!intel_dp_is_edp(intel_dp))
4301 drm_dp_set_subconnector_property(connector,
4304 intel_dp->downstream_ports);
4309 intel_dp_force(struct drm_connector *connector)
4311 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4312 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4313 struct intel_encoder *intel_encoder = &dig_port->base;
4314 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4315 enum intel_display_power_domain aux_domain =
4316 intel_aux_power_domain(dig_port);
4317 intel_wakeref_t wakeref;
4319 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4320 connector->base.id, connector->name);
4321 intel_dp_unset_edid(intel_dp);
4323 if (connector->status != connector_status_connected)
4326 wakeref = intel_display_power_get(dev_priv, aux_domain);
4328 intel_dp_set_edid(intel_dp);
4330 intel_display_power_put(dev_priv, aux_domain, wakeref);
4333 static int intel_dp_get_modes(struct drm_connector *connector)
4335 struct intel_connector *intel_connector = to_intel_connector(connector);
4339 edid = intel_connector->detect_edid;
4341 num_modes = intel_connector_update_modes(connector, edid);
4343 if (intel_vrr_is_capable(connector))
4344 drm_connector_set_vrr_capable_property(connector,
4348 /* Also add fixed mode, which may or may not be present in EDID */
4349 if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4350 intel_connector->panel.fixed_mode) {
4351 struct drm_display_mode *mode;
4353 mode = drm_mode_duplicate(connector->dev,
4354 intel_connector->panel.fixed_mode);
4356 drm_mode_probed_add(connector, mode);
4365 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4366 struct drm_display_mode *mode;
4368 mode = drm_dp_downstream_mode(connector->dev,
4370 intel_dp->downstream_ports);
4372 drm_mode_probed_add(connector, mode);
4381 intel_dp_connector_register(struct drm_connector *connector)
4383 struct drm_i915_private *i915 = to_i915(connector->dev);
4384 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4385 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4386 struct intel_lspcon *lspcon = &dig_port->lspcon;
4389 ret = intel_connector_register(connector);
4393 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4394 intel_dp->aux.name, connector->kdev->kobj.name);
4396 intel_dp->aux.dev = connector->kdev;
4397 ret = drm_dp_aux_register(&intel_dp->aux);
4399 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4401 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4405 * ToDo: Clean this up to handle lspcon init and resume more
4406 * efficiently and streamlined.
4408 if (lspcon_init(dig_port)) {
4409 lspcon_detect_hdr_capability(lspcon);
4410 if (lspcon->hdr_supported)
4411 drm_object_attach_property(&connector->base,
4412 connector->dev->mode_config.hdr_output_metadata_property,
4420 intel_dp_connector_unregister(struct drm_connector *connector)
4422 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4424 drm_dp_cec_unregister_connector(&intel_dp->aux);
4425 drm_dp_aux_unregister(&intel_dp->aux);
4426 intel_connector_unregister(connector);
4429 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4431 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4432 struct intel_dp *intel_dp = &dig_port->dp;
4434 intel_dp_mst_encoder_cleanup(dig_port);
4436 intel_pps_vdd_off_sync(intel_dp);
4438 intel_dp_aux_fini(intel_dp);
4441 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4443 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4445 intel_pps_vdd_off_sync(intel_dp);
4448 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4450 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4452 intel_pps_wait_power_cycle(intel_dp);
4455 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4458 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4459 struct drm_connector_list_iter conn_iter;
4460 struct drm_connector *connector;
4463 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4464 drm_for_each_connector_iter(connector, &conn_iter) {
4465 struct drm_connector_state *conn_state;
4466 struct intel_crtc_state *crtc_state;
4467 struct intel_crtc *crtc;
4469 if (!connector->has_tile ||
4470 connector->tile_group->id != tile_group_id)
4473 conn_state = drm_atomic_get_connector_state(&state->base,
4475 if (IS_ERR(conn_state)) {
4476 ret = PTR_ERR(conn_state);
4480 crtc = to_intel_crtc(conn_state->crtc);
4485 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4486 crtc_state->uapi.mode_changed = true;
4488 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4492 drm_connector_list_iter_end(&conn_iter);
4497 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4499 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4500 struct intel_crtc *crtc;
4502 if (transcoders == 0)
4505 for_each_intel_crtc(&dev_priv->drm, crtc) {
4506 struct intel_crtc_state *crtc_state;
4509 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4510 if (IS_ERR(crtc_state))
4511 return PTR_ERR(crtc_state);
4513 if (!crtc_state->hw.enable)
4516 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4519 crtc_state->uapi.mode_changed = true;
4521 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4525 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4529 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4532 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4537 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4538 struct drm_connector *connector)
4540 const struct drm_connector_state *old_conn_state =
4541 drm_atomic_get_old_connector_state(&state->base, connector);
4542 const struct intel_crtc_state *old_crtc_state;
4543 struct intel_crtc *crtc;
4546 crtc = to_intel_crtc(old_conn_state->crtc);
4550 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4552 if (!old_crtc_state->hw.active)
4555 transcoders = old_crtc_state->sync_mode_slaves_mask;
4556 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4557 transcoders |= BIT(old_crtc_state->master_transcoder);
4559 return intel_modeset_affected_transcoders(state,
4563 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4564 struct drm_atomic_state *_state)
4566 struct drm_i915_private *dev_priv = to_i915(conn->dev);
4567 struct intel_atomic_state *state = to_intel_atomic_state(_state);
4570 ret = intel_digital_connector_atomic_check(conn, &state->base);
4575 * We don't enable port sync on BDW due to missing w/as and
4576 * due to not having adjusted the modeset sequence appropriately.
4578 if (DISPLAY_VER(dev_priv) < 9)
4581 if (!intel_connector_needs_modeset(state, conn))
4584 if (conn->has_tile) {
4585 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4590 return intel_modeset_synced_crtcs(state, conn);
4593 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4594 .force = intel_dp_force,
4595 .fill_modes = drm_helper_probe_single_connector_modes,
4596 .atomic_get_property = intel_digital_connector_atomic_get_property,
4597 .atomic_set_property = intel_digital_connector_atomic_set_property,
4598 .late_register = intel_dp_connector_register,
4599 .early_unregister = intel_dp_connector_unregister,
4600 .destroy = intel_connector_destroy,
4601 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4602 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4605 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4606 .detect_ctx = intel_dp_detect,
4607 .get_modes = intel_dp_get_modes,
4608 .mode_valid = intel_dp_mode_valid,
4609 .atomic_check = intel_dp_connector_atomic_check,
4613 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4615 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4616 struct intel_dp *intel_dp = &dig_port->dp;
4618 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4619 (long_hpd || !intel_pps_have_power(intel_dp))) {
4621 * vdd off can generate a long/short pulse on eDP which
4622 * would require vdd on to handle it, and thus we
4623 * would end up in an endless cycle of
4624 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4626 drm_dbg_kms(&i915->drm,
4627 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4628 long_hpd ? "long" : "short",
4629 dig_port->base.base.base.id,
4630 dig_port->base.base.name);
4634 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4635 dig_port->base.base.base.id,
4636 dig_port->base.base.name,
4637 long_hpd ? "long" : "short");
4640 intel_dp->reset_link_params = true;
4644 if (intel_dp->is_mst) {
4645 if (!intel_dp_check_mst_status(intel_dp))
4647 } else if (!intel_dp_short_pulse(intel_dp)) {
4654 /* check the VBT to see whether the eDP is on another port */
4655 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4658 * eDP not supported on g4x. so bail out early just
4659 * for a bit extra safety in case the VBT is bonkers.
4661 if (DISPLAY_VER(dev_priv) < 5)
4664 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
4667 return intel_bios_is_port_edp(dev_priv, port);
4671 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4673 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4674 enum port port = dp_to_dig_port(intel_dp)->base.port;
4676 if (!intel_dp_is_edp(intel_dp))
4677 drm_connector_attach_dp_subconnector_property(connector);
4679 if (!IS_G4X(dev_priv) && port != PORT_A)
4680 intel_attach_force_audio_property(connector);
4682 intel_attach_broadcast_rgb_property(connector);
4683 if (HAS_GMCH(dev_priv))
4684 drm_connector_attach_max_bpc_property(connector, 6, 10);
4685 else if (DISPLAY_VER(dev_priv) >= 5)
4686 drm_connector_attach_max_bpc_property(connector, 6, 12);
4688 /* Register HDMI colorspace for case of lspcon */
4689 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4690 drm_connector_attach_content_type_property(connector);
4691 intel_attach_hdmi_colorspace_property(connector);
4693 intel_attach_dp_colorspace_property(connector);
4696 if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
4697 drm_object_attach_property(&connector->base,
4698 connector->dev->mode_config.hdr_output_metadata_property,
4701 if (intel_dp_is_edp(intel_dp)) {
4702 u32 allowed_scalers;
4704 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4705 if (!HAS_GMCH(dev_priv))
4706 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4708 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4710 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4714 if (HAS_VRR(dev_priv))
4715 drm_connector_attach_vrr_capable_property(connector);
4719 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4720 * @dev_priv: i915 device
4721 * @crtc_state: a pointer to the active intel_crtc_state
4722 * @refresh_rate: RR to be programmed
4724 * This function gets called when refresh rate (RR) has to be changed from
4725 * one frequency to another. Switches can be between high and low RR
4726 * supported by the panel or to any other RR based on media playback (in
4727 * this case, RR value needs to be passed from user space).
4729 * The caller of this function needs to take a lock on dev_priv->drrs.
4731 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
4732 const struct intel_crtc_state *crtc_state,
4735 struct intel_dp *intel_dp = dev_priv->drrs.dp;
4736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4737 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4739 if (refresh_rate <= 0) {
4740 drm_dbg_kms(&dev_priv->drm,
4741 "Refresh rate should be positive non-zero.\n");
4745 if (intel_dp == NULL) {
4746 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
4751 drm_dbg_kms(&dev_priv->drm,
4752 "DRRS: intel_crtc not initialized\n");
4756 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4757 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
4761 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
4763 index = DRRS_LOW_RR;
4765 if (index == dev_priv->drrs.refresh_rate_type) {
4766 drm_dbg_kms(&dev_priv->drm,
4767 "DRRS requested for previously set RR...ignoring\n");
4771 if (!crtc_state->hw.active) {
4772 drm_dbg_kms(&dev_priv->drm,
4773 "eDP encoder disabled. CRTC not Active\n");
4777 if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
4780 intel_dp_set_m_n(crtc_state, M1_N1);
4783 intel_dp_set_m_n(crtc_state, M2_N2);
4787 drm_err(&dev_priv->drm,
4788 "Unsupported refreshrate type\n");
4790 } else if (DISPLAY_VER(dev_priv) > 6) {
4791 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
4794 val = intel_de_read(dev_priv, reg);
4795 if (index > DRRS_HIGH_RR) {
4796 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4797 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4799 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4801 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4802 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4804 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4806 intel_de_write(dev_priv, reg, val);
4809 dev_priv->drrs.refresh_rate_type = index;
4811 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
4816 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
4818 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4820 dev_priv->drrs.busy_frontbuffer_bits = 0;
4821 dev_priv->drrs.dp = intel_dp;
4825 * intel_edp_drrs_enable - init drrs struct if supported
4826 * @intel_dp: DP struct
4827 * @crtc_state: A pointer to the active crtc state.
4829 * Initializes frontbuffer_bits and drrs.dp
4831 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
4832 const struct intel_crtc_state *crtc_state)
4834 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4836 if (!crtc_state->has_drrs)
4839 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
4841 mutex_lock(&dev_priv->drrs.mutex);
4843 if (dev_priv->drrs.dp) {
4844 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
4848 intel_edp_drrs_enable_locked(intel_dp);
4851 mutex_unlock(&dev_priv->drrs.mutex);
4855 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
4856 const struct intel_crtc_state *crtc_state)
4858 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4860 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4863 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
4864 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
4867 dev_priv->drrs.dp = NULL;
4871 * intel_edp_drrs_disable - Disable DRRS
4872 * @intel_dp: DP struct
4873 * @old_crtc_state: Pointer to old crtc_state.
4876 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
4877 const struct intel_crtc_state *old_crtc_state)
4879 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4881 if (!old_crtc_state->has_drrs)
4884 mutex_lock(&dev_priv->drrs.mutex);
4885 if (!dev_priv->drrs.dp) {
4886 mutex_unlock(&dev_priv->drrs.mutex);
4890 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
4891 mutex_unlock(&dev_priv->drrs.mutex);
4893 cancel_delayed_work_sync(&dev_priv->drrs.work);
4897 * intel_edp_drrs_update - Update DRRS state
4898 * @intel_dp: Intel DP
4899 * @crtc_state: new CRTC state
4901 * This function will update DRRS states, disabling or enabling DRRS when
4902 * executing fastsets. For full modeset, intel_edp_drrs_disable() and
4903 * intel_edp_drrs_enable() should be called instead.
4906 intel_edp_drrs_update(struct intel_dp *intel_dp,
4907 const struct intel_crtc_state *crtc_state)
4909 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4911 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
4914 mutex_lock(&dev_priv->drrs.mutex);
4916 /* New state matches current one? */
4917 if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
4920 if (crtc_state->has_drrs)
4921 intel_edp_drrs_enable_locked(intel_dp);
4923 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
4926 mutex_unlock(&dev_priv->drrs.mutex);
4929 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4931 struct drm_i915_private *dev_priv =
4932 container_of(work, typeof(*dev_priv), drrs.work.work);
4933 struct intel_dp *intel_dp;
4935 mutex_lock(&dev_priv->drrs.mutex);
4937 intel_dp = dev_priv->drrs.dp;
4943 * The delayed work can race with an invalidate hence we need to
4947 if (dev_priv->drrs.busy_frontbuffer_bits)
4950 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
4951 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4953 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4954 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
4958 mutex_unlock(&dev_priv->drrs.mutex);
4962 * intel_edp_drrs_invalidate - Disable Idleness DRRS
4963 * @dev_priv: i915 device
4964 * @frontbuffer_bits: frontbuffer plane tracking bits
4966 * This function gets called everytime rendering on the given planes start.
4967 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
4969 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4971 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
4972 unsigned int frontbuffer_bits)
4974 struct intel_dp *intel_dp;
4975 struct drm_crtc *crtc;
4978 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
4981 cancel_delayed_work(&dev_priv->drrs.work);
4983 mutex_lock(&dev_priv->drrs.mutex);
4985 intel_dp = dev_priv->drrs.dp;
4987 mutex_unlock(&dev_priv->drrs.mutex);
4991 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4992 pipe = to_intel_crtc(crtc)->pipe;
4994 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
4995 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
4997 /* invalidate means busy screen hence upclock */
4998 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4999 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5000 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5002 mutex_unlock(&dev_priv->drrs.mutex);
5006 * intel_edp_drrs_flush - Restart Idleness DRRS
5007 * @dev_priv: i915 device
5008 * @frontbuffer_bits: frontbuffer plane tracking bits
5010 * This function gets called every time rendering on the given planes has
5011 * completed or flip on a crtc is completed. So DRRS should be upclocked
5012 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5013 * if no other planes are dirty.
5015 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5017 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5018 unsigned int frontbuffer_bits)
5020 struct intel_dp *intel_dp;
5021 struct drm_crtc *crtc;
5024 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5027 cancel_delayed_work(&dev_priv->drrs.work);
5029 mutex_lock(&dev_priv->drrs.mutex);
5031 intel_dp = dev_priv->drrs.dp;
5033 mutex_unlock(&dev_priv->drrs.mutex);
5037 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5038 pipe = to_intel_crtc(crtc)->pipe;
5040 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5041 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5043 /* flush means busy screen hence upclock */
5044 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5045 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5046 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5049 * flush also means no more activity hence schedule downclock, if all
5050 * other fbs are quiescent too
5052 if (!dev_priv->drrs.busy_frontbuffer_bits)
5053 schedule_delayed_work(&dev_priv->drrs.work,
5054 msecs_to_jiffies(1000));
5055 mutex_unlock(&dev_priv->drrs.mutex);
5059 * DOC: Display Refresh Rate Switching (DRRS)
5061 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5062 * which enables swtching between low and high refresh rates,
5063 * dynamically, based on the usage scenario. This feature is applicable
5064 * for internal panels.
5066 * Indication that the panel supports DRRS is given by the panel EDID, which
5067 * would list multiple refresh rates for one resolution.
5069 * DRRS is of 2 types - static and seamless.
5070 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5071 * (may appear as a blink on screen) and is used in dock-undock scenario.
5072 * Seamless DRRS involves changing RR without any visual effect to the user
5073 * and can be used during normal system usage. This is done by programming
5074 * certain registers.
5076 * Support for static/seamless DRRS may be indicated in the VBT based on
5077 * inputs from the panel spec.
5079 * DRRS saves power by switching to low RR based on usage scenarios.
5081 * The implementation is based on frontbuffer tracking implementation. When
5082 * there is a disturbance on the screen triggered by user activity or a periodic
5083 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5084 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5087 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5088 * and intel_edp_drrs_flush() are called.
5090 * DRRS can be further extended to support other internal panels and also
5091 * the scenario of video playback wherein RR is set based on the rate
5092 * requested by userspace.
5096 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5097 * @connector: eDP connector
5098 * @fixed_mode: preferred mode of panel
5100 * This function is called only once at driver load to initialize basic
5104 * Downclock mode if panel supports it, else return NULL.
5105 * DRRS support is determined by the presence of downclock mode (apart
5106 * from VBT setting).
5108 static struct drm_display_mode *
5109 intel_dp_drrs_init(struct intel_connector *connector,
5110 struct drm_display_mode *fixed_mode)
5112 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5113 struct drm_display_mode *downclock_mode = NULL;
5115 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5116 mutex_init(&dev_priv->drrs.mutex);
5118 if (DISPLAY_VER(dev_priv) <= 6) {
5119 drm_dbg_kms(&dev_priv->drm,
5120 "DRRS supported for Gen7 and above\n");
5124 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5125 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
5129 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
5130 if (!downclock_mode) {
5131 drm_dbg_kms(&dev_priv->drm,
5132 "Downclock mode is not found. DRRS not supported\n");
5136 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5138 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5139 drm_dbg_kms(&dev_priv->drm,
5140 "seamless DRRS supported for eDP panel.\n");
5141 return downclock_mode;
5144 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5145 struct intel_connector *intel_connector)
5147 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5148 struct drm_device *dev = &dev_priv->drm;
5149 struct drm_connector *connector = &intel_connector->base;
5150 struct drm_display_mode *fixed_mode = NULL;
5151 struct drm_display_mode *downclock_mode = NULL;
5153 enum pipe pipe = INVALID_PIPE;
5156 if (!intel_dp_is_edp(intel_dp))
5160 * On IBX/CPT we may get here with LVDS already registered. Since the
5161 * driver uses the only internal power sequencer available for both
5162 * eDP and LVDS bail out early in this case to prevent interfering
5163 * with an already powered-on LVDS power sequencer.
5165 if (intel_get_lvds_encoder(dev_priv)) {
5167 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5168 drm_info(&dev_priv->drm,
5169 "LVDS was detected, not registering eDP\n");
5174 intel_pps_init(intel_dp);
5176 /* Cache DPCD and EDID for edp. */
5177 has_dpcd = intel_edp_init_dpcd(intel_dp);
5180 /* if this fails, presume the device is a ghost */
5181 drm_info(&dev_priv->drm,
5182 "failed to retrieve link info, disabling eDP\n");
5186 mutex_lock(&dev->mode_config.mutex);
5187 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5189 if (drm_add_edid_modes(connector, edid)) {
5190 drm_connector_update_edid_property(connector, edid);
5193 edid = ERR_PTR(-EINVAL);
5196 edid = ERR_PTR(-ENOENT);
5198 intel_connector->edid = edid;
5200 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5202 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
5204 /* multiply the mode clock and horizontal timings for MSO */
5205 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5206 intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5208 /* fallback to VBT if available for eDP */
5210 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5211 mutex_unlock(&dev->mode_config.mutex);
5213 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5215 * Figure out the current pipe for the initial backlight setup.
5216 * If the current pipe isn't valid, try the PPS pipe, and if that
5217 * fails just assume pipe A.
5219 pipe = vlv_active_pipe(intel_dp);
5221 if (pipe != PIPE_A && pipe != PIPE_B)
5222 pipe = intel_dp->pps.pps_pipe;
5224 if (pipe != PIPE_A && pipe != PIPE_B)
5227 drm_dbg_kms(&dev_priv->drm,
5228 "using pipe %c for initial backlight setup\n",
5232 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5233 if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
5234 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5235 intel_panel_setup_backlight(connector, pipe);
5238 drm_connector_set_panel_orientation_with_quirk(connector,
5239 dev_priv->vbt.orientation,
5240 fixed_mode->hdisplay, fixed_mode->vdisplay);
5246 intel_pps_vdd_off_sync(intel_dp);
5251 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5253 struct intel_connector *intel_connector;
5254 struct drm_connector *connector;
5256 intel_connector = container_of(work, typeof(*intel_connector),
5257 modeset_retry_work);
5258 connector = &intel_connector->base;
5259 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5262 /* Grab the locks before changing connector property*/
5263 mutex_lock(&connector->dev->mode_config.mutex);
5264 /* Set connector link status to BAD and send a Uevent to notify
5265 * userspace to do a modeset.
5267 drm_connector_set_link_status_property(connector,
5268 DRM_MODE_LINK_STATUS_BAD);
5269 mutex_unlock(&connector->dev->mode_config.mutex);
5270 /* Send Hotplug uevent so userspace can reprobe */
5271 drm_kms_helper_hotplug_event(connector->dev);
5275 intel_dp_init_connector(struct intel_digital_port *dig_port,
5276 struct intel_connector *intel_connector)
5278 struct drm_connector *connector = &intel_connector->base;
5279 struct intel_dp *intel_dp = &dig_port->dp;
5280 struct intel_encoder *intel_encoder = &dig_port->base;
5281 struct drm_device *dev = intel_encoder->base.dev;
5282 struct drm_i915_private *dev_priv = to_i915(dev);
5283 enum port port = intel_encoder->port;
5284 enum phy phy = intel_port_to_phy(dev_priv, port);
5287 /* Initialize the work for modeset in case of link train failure */
5288 INIT_WORK(&intel_connector->modeset_retry_work,
5289 intel_dp_modeset_retry_work_fn);
5291 if (drm_WARN(dev, dig_port->max_lanes < 1,
5292 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5293 dig_port->max_lanes, intel_encoder->base.base.id,
5294 intel_encoder->base.name))
5297 intel_dp_set_source_rates(intel_dp);
5299 intel_dp->reset_link_params = true;
5300 intel_dp->pps.pps_pipe = INVALID_PIPE;
5301 intel_dp->pps.active_pipe = INVALID_PIPE;
5303 /* Preserve the current hw state. */
5304 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5305 intel_dp->attached_connector = intel_connector;
5307 if (intel_dp_is_port_edp(dev_priv, port)) {
5309 * Currently we don't support eDP on TypeC ports, although in
5310 * theory it could work on TypeC legacy ports.
5312 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5313 type = DRM_MODE_CONNECTOR_eDP;
5315 type = DRM_MODE_CONNECTOR_DisplayPort;
5318 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5319 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5322 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5323 * for DP the encoder type can be set by the caller to
5324 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5326 if (type == DRM_MODE_CONNECTOR_eDP)
5327 intel_encoder->type = INTEL_OUTPUT_EDP;
5329 /* eDP only on port B and/or C on vlv/chv */
5330 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5331 IS_CHERRYVIEW(dev_priv)) &&
5332 intel_dp_is_edp(intel_dp) &&
5333 port != PORT_B && port != PORT_C))
5336 drm_dbg_kms(&dev_priv->drm,
5337 "Adding %s connector on [ENCODER:%d:%s]\n",
5338 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5339 intel_encoder->base.base.id, intel_encoder->base.name);
5341 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5342 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5344 if (!HAS_GMCH(dev_priv))
5345 connector->interlace_allowed = true;
5346 connector->doublescan_allowed = 0;
5348 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5350 intel_dp_aux_init(intel_dp);
5352 intel_connector_attach_encoder(intel_connector, intel_encoder);
5354 if (HAS_DDI(dev_priv))
5355 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5357 intel_connector->get_hw_state = intel_connector_get_hw_state;
5359 /* init MST on ports that can support it */
5360 intel_dp_mst_encoder_init(dig_port,
5361 intel_connector->base.base.id);
5363 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5364 intel_dp_aux_fini(intel_dp);
5365 intel_dp_mst_encoder_cleanup(dig_port);
5369 intel_dp_add_properties(intel_dp, connector);
5371 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5372 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5374 drm_dbg_kms(&dev_priv->drm,
5375 "HDCP init failed, skipping.\n");
5378 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5379 * 0xd. Failure to do so will result in spurious interrupts being
5380 * generated on the port when a cable is not attached.
5382 if (IS_G45(dev_priv)) {
5383 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5384 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5385 (temp & ~0xf) | 0xd);
5388 intel_dp->frl.is_trained = false;
5389 intel_dp->frl.trained_rate_gbps = 0;
5391 intel_psr_init(intel_dp);
5396 drm_connector_cleanup(connector);
5401 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5403 struct intel_encoder *encoder;
5405 if (!HAS_DISPLAY(dev_priv))
5408 for_each_intel_encoder(&dev_priv->drm, encoder) {
5409 struct intel_dp *intel_dp;
5411 if (encoder->type != INTEL_OUTPUT_DDI)
5414 intel_dp = enc_to_intel_dp(encoder);
5416 if (!intel_dp->can_mst)
5419 if (intel_dp->is_mst)
5420 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5424 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5426 struct intel_encoder *encoder;
5428 if (!HAS_DISPLAY(dev_priv))
5431 for_each_intel_encoder(&dev_priv->drm, encoder) {
5432 struct intel_dp *intel_dp;
5435 if (encoder->type != INTEL_OUTPUT_DDI)
5438 intel_dp = enc_to_intel_dp(encoder);
5440 if (!intel_dp->can_mst)
5443 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5446 intel_dp->is_mst = false;
5447 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,