drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_drv.h"
  48 #include "i915_irq.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_cx0_phy.h"
  57 #include "intel_ddi.h"
  58 #include "intel_de.h"
  59 #include "intel_display_driver.h"
  60 #include "intel_display_types.h"
  61 #include "intel_dp.h"
  62 #include "intel_dp_aux.h"
  63 #include "intel_dp_hdcp.h"
  64 #include "intel_dp_link_training.h"
  65 #include "intel_dp_mst.h"
  66 #include "intel_dpio_phy.h"
  67 #include "intel_dpll.h"
  68 #include "intel_fifo_underrun.h"
  69 #include "intel_hdcp.h"
  70 #include "intel_hdmi.h"
  71 #include "intel_hotplug.h"
  72 #include "intel_hotplug_irq.h"
  73 #include "intel_lspcon.h"
  74 #include "intel_lvds.h"
  75 #include "intel_panel.h"
  76 #include "intel_pch_display.h"
  77 #include "intel_pps.h"
  78 #include "intel_psr.h"
  79 #include "intel_tc.h"
  80 #include "intel_vdsc.h"
  81 #include "intel_vrr.h"
  82 #include "intel_crtc_state_dump.h"
  83
  84 /* DP DSC throughput values used for slice count calculations KPixels/s */
  85 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  86 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  87 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  88
  89 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
  90 #define DP_DSC_FEC_OVERHEAD_FACTOR              1028530
  91
  92 /* Compliance test status bits  */
  93 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  94 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  95 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  96 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  97
  98
  99 /* Constants for DP DSC configurations */
 100 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 101
 102 /* With Single pipe configuration, HW is capable of supporting maximum
 103  * of 4 slices per line.
 104  */
 105 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 106
 107 /**
 108  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 109  * @intel_dp: DP struct
 110  *
 111  * If a CPU or PCH DP output is attached to an eDP panel, this function
 112  * will return true, and false otherwise.
 113  *
 114  * This function is not safe to use prior to encoder type being set.
 115  */
 116 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 117 {
 118         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 119
 120         return dig_port->base.type == INTEL_OUTPUT_EDP;
 121 }
 122
 123 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 124
 125 /* Is link rate UHBR and thus 128b/132b? */
 126 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 127 {
 128         return drm_dp_is_uhbr_rate(crtc_state->port_clock);
 129 }
 130
 131 /**
 132  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
 133  * @rate: link rate in 10kbit/s units
 134  *
 135  * Returns the link symbol size in bits/symbol units depending on the link
 136  * rate -> channel coding.
 137  */
 138 int intel_dp_link_symbol_size(int rate)
 139 {
 140         return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
 141 }
 142
 143 /**
 144  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
 145  * @rate: link rate in 10kbit/s units
 146  *
 147  * Returns the link symbol clock frequency in kHz units depending on the
 148  * link rate and channel coding.
 149  */
 150 int intel_dp_link_symbol_clock(int rate)
 151 {
 152         return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 153 }
 154
 155 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 156 {
 157         intel_dp->sink_rates[0] = 162000;
 158         intel_dp->num_sink_rates = 1;
 159 }
 160
 161 /* update sink rates from dpcd */
 162 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 163 {
 164         static const int dp_rates[] = {
 165                 162000, 270000, 540000, 810000
 166         };
 167         int i, max_rate;
 168         int max_lttpr_rate;
 169
 170         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 171                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 172                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 173
 174                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 175                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 176
 177                 return;
 178         }
 179
 180         /*
 181          * Sink rates for 8b/10b.
 182          */
 183         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 184         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 185         if (max_lttpr_rate)
 186                 max_rate = min(max_rate, max_lttpr_rate);
 187
 188         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 189                 if (dp_rates[i] > max_rate)
 190                         break;
 191                 intel_dp->sink_rates[i] = dp_rates[i];
 192         }
 193
 194         /*
 195          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 196          * rates and 10 Gbps.
 197          */
 198         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 199                 u8 uhbr_rates = 0;
 200
 201                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 202
 203                 drm_dp_dpcd_readb(&intel_dp->aux,
 204                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 205
 206                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 207                         /* We have a repeater */
 208                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 209                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 210                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 211                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 212                                 /* Repeater supports 128b/132b, valid UHBR rates */
 213                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 214                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 215                         } else {
 216                                 /* Does not support 128b/132b */
 217                                 uhbr_rates = 0;
 218                         }
 219                 }
 220
 221                 if (uhbr_rates & DP_UHBR10)
 222                         intel_dp->sink_rates[i++] = 1000000;
 223                 if (uhbr_rates & DP_UHBR13_5)
 224                         intel_dp->sink_rates[i++] = 1350000;
 225                 if (uhbr_rates & DP_UHBR20)
 226                         intel_dp->sink_rates[i++] = 2000000;
 227         }
 228
 229         intel_dp->num_sink_rates = i;
 230 }
 231
 232 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 233 {
 234         struct intel_connector *connector = intel_dp->attached_connector;
 235         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 236         struct intel_encoder *encoder = &intel_dig_port->base;
 237
 238         intel_dp_set_dpcd_sink_rates(intel_dp);
 239
 240         if (intel_dp->num_sink_rates)
 241                 return;
 242
 243         drm_err(&dp_to_i915(intel_dp)->drm,
 244                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 245                 connector->base.base.id, connector->base.name,
 246                 encoder->base.base.id, encoder->base.name);
 247
 248         intel_dp_set_default_sink_rates(intel_dp);
 249 }
 250
 251 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 252 {
 253         intel_dp->max_sink_lane_count = 1;
 254 }
 255
 256 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 257 {
 258         struct intel_connector *connector = intel_dp->attached_connector;
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261
 262         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 263
 264         switch (intel_dp->max_sink_lane_count) {
 265         case 1:
 266         case 2:
 267         case 4:
 268                 return;
 269         }
 270
 271         drm_err(&dp_to_i915(intel_dp)->drm,
 272                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 273                 connector->base.base.id, connector->base.name,
 274                 encoder->base.base.id, encoder->base.name,
 275                 intel_dp->max_sink_lane_count);
 276
 277         intel_dp_set_default_max_sink_lane_count(intel_dp);
 278 }
 279
 280 /* Get length of rates array potentially limited by max_rate. */
 281 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 282 {
 283         int i;
 284
 285         /* Limit results by potentially reduced max rate */
 286         for (i = 0; i < len; i++) {
 287                 if (rates[len - i - 1] <= max_rate)
 288                         return len - i;
 289         }
 290
 291         return 0;
 292 }
 293
 294 /* Get length of common rates array potentially limited by max_rate. */
 295 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 296                                           int max_rate)
 297 {
 298         return intel_dp_rate_limit_len(intel_dp->common_rates,
 299                                        intel_dp->num_common_rates, max_rate);
 300 }
 301
 302 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 303 {
 304         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 305                         index < 0 || index >= intel_dp->num_common_rates))
 306                 return 162000;
 307
 308         return intel_dp->common_rates[index];
 309 }
 310
 311 /* Theoretical max between source and sink */
 312 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 313 {
 314         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 315 }
 316
 317 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 318 {
 319         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 320         int max_lanes = dig_port->max_lanes;
 321
 322         if (vbt_max_lanes)
 323                 max_lanes = min(max_lanes, vbt_max_lanes);
 324
 325         return max_lanes;
 326 }
 327
 328 /* Theoretical max between source and sink */
 329 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 330 {
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         int source_max = intel_dp_max_source_lane_count(dig_port);
 333         int sink_max = intel_dp->max_sink_lane_count;
 334         int lane_max = intel_tc_port_max_lane_count(dig_port);
 335         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 336
 337         if (lttpr_max)
 338                 sink_max = min(sink_max, lttpr_max);
 339
 340         return min3(source_max, sink_max, lane_max);
 341 }
 342
 343 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 344 {
 345         switch (intel_dp->max_link_lane_count) {
 346         case 1:
 347         case 2:
 348         case 4:
 349                 return intel_dp->max_link_lane_count;
 350         default:
 351                 MISSING_CASE(intel_dp->max_link_lane_count);
 352                 return 1;
 353         }
 354 }
 355
 356 /*
 357  * The required data bandwidth for a mode with given pixel clock and bpp. This
 358  * is the required net bandwidth independent of the data bandwidth efficiency.
 359  *
 360  * TODO: check if callers of this functions should use
 361  * intel_dp_effective_data_rate() instead.
 362  */
 363 int
 364 intel_dp_link_required(int pixel_clock, int bpp)
 365 {
 366         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 367         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 368 }
 369
 370 /**
 371  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
 372  * @pixel_clock: pixel clock in kHz
 373  * @bpp_x16: bits per pixel .4 fixed point format
 374  * @bw_overhead: BW allocation overhead in 1ppm units
 375  *
 376  * Return the effective pixel data rate in kB/sec units taking into account
 377  * the provided SSC, FEC, DSC BW allocation overhead.
 378  */
 379 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 380                                  int bw_overhead)
 381 {
 382         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
 383                                 1000000 * 16 * 8);
 384 }
 385
 386 /*
 387  * Given a link rate and lanes, get the data bandwidth.
 388  *
 389  * Data bandwidth is the actual payload rate, which depends on the data
 390  * bandwidth efficiency and the link rate.
 391  *
 392  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 393  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 394  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 395  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 396  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 397  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 398  *
 399  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 400  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 401  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 402  * does not match the symbol clock, the port clock (not even if you think in
 403  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 404  * rate in units of 10000 bps.
 405  */
 406 int
 407 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 408 {
 409         int ch_coding_efficiency =
 410                 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
 411         int max_link_rate_kbps = max_link_rate * 10;
 412
 413         /*
 414          * UHBR rates always use 128b/132b channel encoding, and have
 415          * 97.71% data bandwidth efficiency. Consider max_link_rate the
 416          * link bit rate in units of 10000 bps.
 417          */
 418         /*
 419          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 420          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 421          * out to be a nop by coincidence:
 422          *
 423          *      int max_link_rate_kbps = max_link_rate * 10;
 424          *      max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10);
 425          *      max_link_rate = max_link_rate_kbps / 8;
 426          */
 427         return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
 428                                               ch_coding_efficiency),
 429                                   1000000 * 8);
 430 }
 431
 432 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 433 {
 434         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 435         struct intel_encoder *encoder = &intel_dig_port->base;
 436         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 437
 438         return DISPLAY_VER(dev_priv) >= 12 ||
 439                 (DISPLAY_VER(dev_priv) == 11 &&
 440                  encoder->port != PORT_A);
 441 }
 442
 443 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 444 {
 445         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 446 }
 447
 448 static int icl_max_source_rate(struct intel_dp *intel_dp)
 449 {
 450         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 451         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 452         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 453
 454         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 455                 return 540000;
 456
 457         return 810000;
 458 }
 459
 460 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 461 {
 462         if (intel_dp_is_edp(intel_dp))
 463                 return 540000;
 464
 465         return 810000;
 466 }
 467
 468 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 469 {
 470         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 471         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 472         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 473
 474         if (intel_is_c10phy(i915, phy))
 475                 return 810000;
 476
 477         return 2000000;
 478 }
 479
 480 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 481 {
 482         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 483         int max_rate;
 484
 485         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 486
 487         if (intel_dp_is_edp(intel_dp)) {
 488                 struct intel_connector *connector = intel_dp->attached_connector;
 489                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 490
 491                 if (max_rate && edp_max_rate)
 492                         max_rate = min(max_rate, edp_max_rate);
 493                 else if (edp_max_rate)
 494                         max_rate = edp_max_rate;
 495         }
 496
 497         return max_rate;
 498 }
 499
 500 static void
 501 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 502 {
 503         /* The values must be in increasing order */
 504         static const int mtl_rates[] = {
 505                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 506                 810000, 1000000, 1350000, 2000000,
 507         };
 508         static const int icl_rates[] = {
 509                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 510                 1000000, 1350000,
 511         };
 512         static const int bxt_rates[] = {
 513                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 514         };
 515         static const int skl_rates[] = {
 516                 162000, 216000, 270000, 324000, 432000, 540000
 517         };
 518         static const int hsw_rates[] = {
 519                 162000, 270000, 540000
 520         };
 521         static const int g4x_rates[] = {
 522                 162000, 270000
 523         };
 524         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 525         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 526         const int *source_rates;
 527         int size, max_rate = 0, vbt_max_rate;
 528
 529         /* This should only be done once */
 530         drm_WARN_ON(&dev_priv->drm,
 531                     intel_dp->source_rates || intel_dp->num_source_rates);
 532
 533         if (DISPLAY_VER(dev_priv) >= 14) {
 534                 source_rates = mtl_rates;
 535                 size = ARRAY_SIZE(mtl_rates);
 536                 max_rate = mtl_max_source_rate(intel_dp);
 537         } else if (DISPLAY_VER(dev_priv) >= 11) {
 538                 source_rates = icl_rates;
 539                 size = ARRAY_SIZE(icl_rates);
 540                 if (IS_DG2(dev_priv))
 541                         max_rate = dg2_max_source_rate(intel_dp);
 542                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 543                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 544                         max_rate = 810000;
 545                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 546                         max_rate = ehl_max_source_rate(intel_dp);
 547                 else
 548                         max_rate = icl_max_source_rate(intel_dp);
 549         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 550                 source_rates = bxt_rates;
 551                 size = ARRAY_SIZE(bxt_rates);
 552         } else if (DISPLAY_VER(dev_priv) == 9) {
 553                 source_rates = skl_rates;
 554                 size = ARRAY_SIZE(skl_rates);
 555         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 556                    IS_BROADWELL(dev_priv)) {
 557                 source_rates = hsw_rates;
 558                 size = ARRAY_SIZE(hsw_rates);
 559         } else {
 560                 source_rates = g4x_rates;
 561                 size = ARRAY_SIZE(g4x_rates);
 562         }
 563
 564         vbt_max_rate = vbt_max_link_rate(intel_dp);
 565         if (max_rate && vbt_max_rate)
 566                 max_rate = min(max_rate, vbt_max_rate);
 567         else if (vbt_max_rate)
 568                 max_rate = vbt_max_rate;
 569
 570         if (max_rate)
 571                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 572
 573         intel_dp->source_rates = source_rates;
 574         intel_dp->num_source_rates = size;
 575 }
 576
 577 static int intersect_rates(const int *source_rates, int source_len,
 578                            const int *sink_rates, int sink_len,
 579                            int *common_rates)
 580 {
 581         int i = 0, j = 0, k = 0;
 582
 583         while (i < source_len && j < sink_len) {
 584                 if (source_rates[i] == sink_rates[j]) {
 585                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 586                                 return k;
 587                         common_rates[k] = source_rates[i];
 588                         ++k;
 589                         ++i;
 590                         ++j;
 591                 } else if (source_rates[i] < sink_rates[j]) {
 592                         ++i;
 593                 } else {
 594                         ++j;
 595                 }
 596         }
 597         return k;
 598 }
 599
 600 /* return index of rate in rates array, or -1 if not found */
 601 static int intel_dp_rate_index(const int *rates, int len, int rate)
 602 {
 603         int i;
 604
 605         for (i = 0; i < len; i++)
 606                 if (rate == rates[i])
 607                         return i;
 608
 609         return -1;
 610 }
 611
 612 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 613 {
 614         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 615
 616         drm_WARN_ON(&i915->drm,
 617                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 618
 619         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 620                                                      intel_dp->num_source_rates,
 621                                                      intel_dp->sink_rates,
 622                                                      intel_dp->num_sink_rates,
 623                                                      intel_dp->common_rates);
 624
 625         /* Paranoia, there should always be something in common. */
 626         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 627                 intel_dp->common_rates[0] = 162000;
 628                 intel_dp->num_common_rates = 1;
 629         }
 630 }
 631
 632 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 633                                        u8 lane_count)
 634 {
 635         /*
 636          * FIXME: we need to synchronize the current link parameters with
 637          * hardware readout. Currently fast link training doesn't work on
 638          * boot-up.
 639          */
 640         if (link_rate == 0 ||
 641             link_rate > intel_dp->max_link_rate)
 642                 return false;
 643
 644         if (lane_count == 0 ||
 645             lane_count > intel_dp_max_lane_count(intel_dp))
 646                 return false;
 647
 648         return true;
 649 }
 650
 651 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 652                                                      int link_rate,
 653                                                      u8 lane_count)
 654 {
 655         /* FIXME figure out what we actually want here */
 656         const struct drm_display_mode *fixed_mode =
 657                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 658         int mode_rate, max_rate;
 659
 660         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 661         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 662         if (mode_rate > max_rate)
 663                 return false;
 664
 665         return true;
 666 }
 667
 668 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 669                                             int link_rate, u8 lane_count)
 670 {
 671         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 672         int index;
 673
 674         /*
 675          * TODO: Enable fallback on MST links once MST link compute can handle
 676          * the fallback params.
 677          */
 678         if (intel_dp->is_mst) {
 679                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 680                 return -1;
 681         }
 682
 683         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 684                 drm_dbg_kms(&i915->drm,
 685                             "Retrying Link training for eDP with max parameters\n");
 686                 intel_dp->use_max_params = true;
 687                 return 0;
 688         }
 689
 690         index = intel_dp_rate_index(intel_dp->common_rates,
 691                                     intel_dp->num_common_rates,
 692                                     link_rate);
 693         if (index > 0) {
 694                 if (intel_dp_is_edp(intel_dp) &&
 695                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 696                                                               intel_dp_common_rate(intel_dp, index - 1),
 697                                                               lane_count)) {
 698                         drm_dbg_kms(&i915->drm,
 699                                     "Retrying Link training for eDP with same parameters\n");
 700                         return 0;
 701                 }
 702                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 703                 intel_dp->max_link_lane_count = lane_count;
 704         } else if (lane_count > 1) {
 705                 if (intel_dp_is_edp(intel_dp) &&
 706                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 707                                                               intel_dp_max_common_rate(intel_dp),
 708                                                               lane_count >> 1)) {
 709                         drm_dbg_kms(&i915->drm,
 710                                     "Retrying Link training for eDP with same parameters\n");
 711                         return 0;
 712                 }
 713                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 714                 intel_dp->max_link_lane_count = lane_count >> 1;
 715         } else {
 716                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 717                 return -1;
 718         }
 719
 720         return 0;
 721 }
 722
 723 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 724 {
 725         return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
 726                        1000000U);
 727 }
 728
 729 int intel_dp_bw_fec_overhead(bool fec_enabled)
 730 {
 731         /*
 732          * TODO: Calculate the actual overhead for a given mode.
 733          * The hard-coded 1/0.972261=2.853% overhead factor
 734          * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
 735          * 0.453% DSC overhead. This is enough for a 3840 width mode,
 736          * which has a DSC overhead of up to ~0.2%, but may not be
 737          * enough for a 1024 width mode where this is ~0.8% (on a 4
 738          * lane DP link, with 2 DSC slices and 8 bpp color depth).
 739          */
 740         return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
 741 }
 742
 743 static int
 744 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 745 {
 746         if (DISPLAY_VER(i915) >= 13)
 747                 return 17280 * 8;
 748         else if (DISPLAY_VER(i915) >= 11)
 749                 return 7680 * 8;
 750         else
 751                 return 6144 * 8;
 752 }
 753
 754 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 755 {
 756         u32 bits_per_pixel = bpp;
 757         int i;
 758
 759         /* Error out if the max bpp is less than smallest allowed valid bpp */
 760         if (bits_per_pixel < valid_dsc_bpp[0]) {
 761                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 762                             bits_per_pixel, valid_dsc_bpp[0]);
 763                 return 0;
 764         }
 765
 766         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 767         if (DISPLAY_VER(i915) >= 13) {
 768                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 769
 770                 /*
 771                  * According to BSpec, 27 is the max DSC output bpp,
 772                  * 8 is the min DSC output bpp.
 773                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 774                  * if it is required to oompress up to bpp < 8, means we can't do
 775                  * that and probably means we can't fit the required mode, even with
 776                  * DSC enabled.
 777                  */
 778                 if (bits_per_pixel < 8) {
 779                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 780                                     bits_per_pixel);
 781                         return 0;
 782                 }
 783                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 784         } else {
 785                 /* Find the nearest match in the array of known BPPs from VESA */
 786                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 787                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 788                                 break;
 789                 }
 790                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 791                             bits_per_pixel, valid_dsc_bpp[i]);
 792
 793                 bits_per_pixel = valid_dsc_bpp[i];
 794         }
 795
 796         return bits_per_pixel;
 797 }
 798
 799 static
 800 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 801                                        u32 mode_clock, u32 mode_hdisplay,
 802                                        bool bigjoiner)
 803 {
 804         u32 max_bpp_small_joiner_ram;
 805
 806         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 807         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 808
 809         if (bigjoiner) {
 810                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
 811                 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 812                 int ppc = 2;
 813                 u32 max_bpp_bigjoiner =
 814                         i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
 815                         intel_dp_mode_to_fec_clock(mode_clock);
 816
 817                 max_bpp_small_joiner_ram *= 2;
 818
 819                 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
 820         }
 821
 822         return max_bpp_small_joiner_ram;
 823 }
 824
 825 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 826                                         u32 link_clock, u32 lane_count,
 827                                         u32 mode_clock, u32 mode_hdisplay,
 828                                         bool bigjoiner,
 829                                         enum intel_output_format output_format,
 830                                         u32 pipe_bpp,
 831                                         u32 timeslots)
 832 {
 833         u32 bits_per_pixel, joiner_max_bpp;
 834
 835         /*
 836          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 837          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 838          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 839          * for MST -> TimeSlots has to be calculated, based on mode requirements
 840          *
 841          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 842          * To support the given mode:
 843          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 844          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 845          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 846          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 847          *                     (ModeClock / FEC Overhead)
 848          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 849          *                     (ModeClock / FEC Overhead * 8)
 850          */
 851         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 852                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 853
 854         /* Bandwidth required for 420 is half, that of 444 format */
 855         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 856                 bits_per_pixel *= 2;
 857
 858         /*
 859          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 860          * supported PPS value can be 63.9375 and with the further
 861          * mention that for 420, 422 formats, bpp should be programmed double
 862          * the target bpp restricting our target bpp to be 31.9375 at max.
 863          */
 864         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 865                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 866
 867         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 868                                 "total bw %u pixel clock %u\n",
 869                                 bits_per_pixel, timeslots,
 870                                 (link_clock * lane_count * 8),
 871                                 intel_dp_mode_to_fec_clock(mode_clock));
 872
 873         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 874                                                             mode_hdisplay, bigjoiner);
 875         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 876
 877         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 878
 879         return bits_per_pixel;
 880 }
 881
 882 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 883                                 int mode_clock, int mode_hdisplay,
 884                                 bool bigjoiner)
 885 {
 886         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 887         u8 min_slice_count, i;
 888         int max_slice_width;
 889
 890         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 891                 min_slice_count = DIV_ROUND_UP(mode_clock,
 892                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 893         else
 894                 min_slice_count = DIV_ROUND_UP(mode_clock,
 895                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 896
 897         /*
 898          * Due to some DSC engine BW limitations, we need to enable second
 899          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 900          */
 901         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 902                 min_slice_count = max_t(u8, min_slice_count, 2);
 903
 904         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
 905         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 906                 drm_dbg_kms(&i915->drm,
 907                             "Unsupported slice width %d by DP DSC Sink device\n",
 908                             max_slice_width);
 909                 return 0;
 910         }
 911         /* Also take into account max slice width */
 912         min_slice_count = max_t(u8, min_slice_count,
 913                                 DIV_ROUND_UP(mode_hdisplay,
 914                                              max_slice_width));
 915
 916         /* Find the closest match to the valid slice count values */
 917         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 918                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 919
 920                 if (test_slice_count >
 921                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 922                         break;
 923
 924                 /* big joiner needs small joiner to be enabled */
 925                 if (bigjoiner && test_slice_count < 4)
 926                         continue;
 927
 928                 if (min_slice_count <= test_slice_count)
 929                         return test_slice_count;
 930         }
 931
 932         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 933                     min_slice_count);
 934         return 0;
 935 }
 936
 937 static bool source_can_output(struct intel_dp *intel_dp,
 938                               enum intel_output_format format)
 939 {
 940         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 941
 942         switch (format) {
 943         case INTEL_OUTPUT_FORMAT_RGB:
 944                 return true;
 945
 946         case INTEL_OUTPUT_FORMAT_YCBCR444:
 947                 /*
 948                  * No YCbCr output support on gmch platforms.
 949                  * Also, ILK doesn't seem capable of DP YCbCr output.
 950                  * The displayed image is severly corrupted. SNB+ is fine.
 951                  */
 952                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 953
 954         case INTEL_OUTPUT_FORMAT_YCBCR420:
 955                 /* Platform < Gen 11 cannot output YCbCr420 format */
 956                 return DISPLAY_VER(i915) >= 11;
 957
 958         default:
 959                 MISSING_CASE(format);
 960                 return false;
 961         }
 962 }
 963
 964 static bool
 965 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 966                          enum intel_output_format sink_format)
 967 {
 968         if (!drm_dp_is_branch(intel_dp->dpcd))
 969                 return false;
 970
 971         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 972                 return intel_dp->dfp.rgb_to_ycbcr;
 973
 974         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 975                 return intel_dp->dfp.rgb_to_ycbcr &&
 976                         intel_dp->dfp.ycbcr_444_to_420;
 977
 978         return false;
 979 }
 980
 981 static bool
 982 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 983                               enum intel_output_format sink_format)
 984 {
 985         if (!drm_dp_is_branch(intel_dp->dpcd))
 986                 return false;
 987
 988         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 989                 return intel_dp->dfp.ycbcr_444_to_420;
 990
 991         return false;
 992 }
 993
 994 static bool
 995 dfp_can_convert(struct intel_dp *intel_dp,
 996                 enum intel_output_format output_format,
 997                 enum intel_output_format sink_format)
 998 {
 999         switch (output_format) {
1000         case INTEL_OUTPUT_FORMAT_RGB:
1001                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1002         case INTEL_OUTPUT_FORMAT_YCBCR444:
1003                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1004         default:
1005                 MISSING_CASE(output_format);
1006                 return false;
1007         }
1008
1009         return false;
1010 }
1011
1012 static enum intel_output_format
1013 intel_dp_output_format(struct intel_connector *connector,
1014                        enum intel_output_format sink_format)
1015 {
1016         struct intel_dp *intel_dp = intel_attached_dp(connector);
1017         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1018         enum intel_output_format force_dsc_output_format =
1019                 intel_dp->force_dsc_output_format;
1020         enum intel_output_format output_format;
1021         if (force_dsc_output_format) {
1022                 if (source_can_output(intel_dp, force_dsc_output_format) &&
1023                     (!drm_dp_is_branch(intel_dp->dpcd) ||
1024                      sink_format != force_dsc_output_format ||
1025                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1026                         return force_dsc_output_format;
1027
1028                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1029         }
1030
1031         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1032             dfp_can_convert_from_rgb(intel_dp, sink_format))
1033                 output_format = INTEL_OUTPUT_FORMAT_RGB;
1034
1035         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1036                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1037                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1038
1039         else
1040                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1041
1042         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1043
1044         return output_format;
1045 }
1046
1047 int intel_dp_min_bpp(enum intel_output_format output_format)
1048 {
1049         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1050                 return 6 * 3;
1051         else
1052                 return 8 * 3;
1053 }
1054
1055 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1056 {
1057         /*
1058          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1059          * format of the number of bytes per pixel will be half the number
1060          * of bytes of RGB pixel.
1061          */
1062         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1063                 bpp /= 2;
1064
1065         return bpp;
1066 }
1067
1068 static enum intel_output_format
1069 intel_dp_sink_format(struct intel_connector *connector,
1070                      const struct drm_display_mode *mode)
1071 {
1072         const struct drm_display_info *info = &connector->base.display_info;
1073
1074         if (drm_mode_is_420_only(info, mode))
1075                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1076
1077         return INTEL_OUTPUT_FORMAT_RGB;
1078 }
1079
1080 static int
1081 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1082                              const struct drm_display_mode *mode)
1083 {
1084         enum intel_output_format output_format, sink_format;
1085
1086         sink_format = intel_dp_sink_format(connector, mode);
1087
1088         output_format = intel_dp_output_format(connector, sink_format);
1089
1090         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1091 }
1092
1093 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1094                                   int hdisplay)
1095 {
1096         /*
1097          * Older platforms don't like hdisplay==4096 with DP.
1098          *
1099          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1100          * and frame counter increment), but we don't get vblank interrupts,
1101          * and the pipe underruns immediately. The link also doesn't seem
1102          * to get trained properly.
1103          *
1104          * On CHV the vblank interrupts don't seem to disappear but
1105          * otherwise the symptoms are similar.
1106          *
1107          * TODO: confirm the behaviour on HSW+
1108          */
1109         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1110 }
1111
1112 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1113 {
1114         struct intel_connector *connector = intel_dp->attached_connector;
1115         const struct drm_display_info *info = &connector->base.display_info;
1116         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1117
1118         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1119         if (max_tmds_clock && info->max_tmds_clock)
1120                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1121
1122         return max_tmds_clock;
1123 }
1124
1125 static enum drm_mode_status
1126 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1127                           int clock, int bpc,
1128                           enum intel_output_format sink_format,
1129                           bool respect_downstream_limits)
1130 {
1131         int tmds_clock, min_tmds_clock, max_tmds_clock;
1132
1133         if (!respect_downstream_limits)
1134                 return MODE_OK;
1135
1136         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1137
1138         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1139         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1140
1141         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1142                 return MODE_CLOCK_LOW;
1143
1144         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1145                 return MODE_CLOCK_HIGH;
1146
1147         return MODE_OK;
1148 }
1149
1150 static enum drm_mode_status
1151 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1152                                const struct drm_display_mode *mode,
1153                                int target_clock)
1154 {
1155         struct intel_dp *intel_dp = intel_attached_dp(connector);
1156         const struct drm_display_info *info = &connector->base.display_info;
1157         enum drm_mode_status status;
1158         enum intel_output_format sink_format;
1159
1160         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1161         if (intel_dp->dfp.pcon_max_frl_bw) {
1162                 int target_bw;
1163                 int max_frl_bw;
1164                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1165
1166                 target_bw = bpp * target_clock;
1167
1168                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1169
1170                 /* converting bw from Gbps to Kbps*/
1171                 max_frl_bw = max_frl_bw * 1000000;
1172
1173                 if (target_bw > max_frl_bw)
1174                         return MODE_CLOCK_HIGH;
1175
1176                 return MODE_OK;
1177         }
1178
1179         if (intel_dp->dfp.max_dotclock &&
1180             target_clock > intel_dp->dfp.max_dotclock)
1181                 return MODE_CLOCK_HIGH;
1182
1183         sink_format = intel_dp_sink_format(connector, mode);
1184
1185         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1186         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1187                                            8, sink_format, true);
1188
1189         if (status != MODE_OK) {
1190                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1191                     !connector->base.ycbcr_420_allowed ||
1192                     !drm_mode_is_420_also(info, mode))
1193                         return status;
1194                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1195                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1196                                                    8, sink_format, true);
1197                 if (status != MODE_OK)
1198                         return status;
1199         }
1200
1201         return MODE_OK;
1202 }
1203
1204 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1205                              int hdisplay, int clock)
1206 {
1207         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1208
1209         if (!intel_dp_can_bigjoiner(intel_dp))
1210                 return false;
1211
1212         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1213 }
1214
1215 static enum drm_mode_status
1216 intel_dp_mode_valid(struct drm_connector *_connector,
1217                     struct drm_display_mode *mode)
1218 {
1219         struct intel_connector *connector = to_intel_connector(_connector);
1220         struct intel_dp *intel_dp = intel_attached_dp(connector);
1221         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1222         const struct drm_display_mode *fixed_mode;
1223         int target_clock = mode->clock;
1224         int max_rate, mode_rate, max_lanes, max_link_clock;
1225         int max_dotclk = dev_priv->max_dotclk_freq;
1226         u16 dsc_max_compressed_bpp = 0;
1227         u8 dsc_slice_count = 0;
1228         enum drm_mode_status status;
1229         bool dsc = false, bigjoiner = false;
1230
1231         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1232         if (status != MODE_OK)
1233                 return status;
1234
1235         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1236                 return MODE_H_ILLEGAL;
1237
1238         fixed_mode = intel_panel_fixed_mode(connector, mode);
1239         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1240                 status = intel_panel_mode_valid(connector, mode);
1241                 if (status != MODE_OK)
1242                         return status;
1243
1244                 target_clock = fixed_mode->clock;
1245         }
1246
1247         if (mode->clock < 10000)
1248                 return MODE_CLOCK_LOW;
1249
1250         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1251                 bigjoiner = true;
1252                 max_dotclk *= 2;
1253         }
1254         if (target_clock > max_dotclk)
1255                 return MODE_CLOCK_HIGH;
1256
1257         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1258                 return MODE_H_ILLEGAL;
1259
1260         max_link_clock = intel_dp_max_link_rate(intel_dp);
1261         max_lanes = intel_dp_max_lane_count(intel_dp);
1262
1263         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1264         mode_rate = intel_dp_link_required(target_clock,
1265                                            intel_dp_mode_min_output_bpp(connector, mode));
1266
1267         if (HAS_DSC(dev_priv) &&
1268             drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1269                 enum intel_output_format sink_format, output_format;
1270                 int pipe_bpp;
1271
1272                 sink_format = intel_dp_sink_format(connector, mode);
1273                 output_format = intel_dp_output_format(connector, sink_format);
1274                 /*
1275                  * TBD pass the connector BPC,
1276                  * for now U8_MAX so that max BPC on that platform would be picked
1277                  */
1278                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1279
1280                 /*
1281                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1282                  * integer value since we support only integer values of bpp.
1283                  */
1284                 if (intel_dp_is_edp(intel_dp)) {
1285                         dsc_max_compressed_bpp =
1286                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1287                         dsc_slice_count =
1288                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1289                                                                 true);
1290                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1291                         dsc_max_compressed_bpp =
1292                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1293                                                                     max_link_clock,
1294                                                                     max_lanes,
1295                                                                     target_clock,
1296                                                                     mode->hdisplay,
1297                                                                     bigjoiner,
1298                                                                     output_format,
1299                                                                     pipe_bpp, 64);
1300                         dsc_slice_count =
1301                                 intel_dp_dsc_get_slice_count(connector,
1302                                                              target_clock,
1303                                                              mode->hdisplay,
1304                                                              bigjoiner);
1305                 }
1306
1307                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1308         }
1309
1310         /*
1311          * Big joiner configuration needs DSC for TGL which is not true for
1312          * XE_LPD where uncompressed joiner is supported.
1313          */
1314         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1315                 return MODE_CLOCK_HIGH;
1316
1317         if (mode_rate > max_rate && !dsc)
1318                 return MODE_CLOCK_HIGH;
1319
1320         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1321         if (status != MODE_OK)
1322                 return status;
1323
1324         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1325 }
1326
1327 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1328 {
1329         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1330 }
1331
1332 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1333 {
1334         return DISPLAY_VER(i915) >= 10;
1335 }
1336
1337 static void snprintf_int_array(char *str, size_t len,
1338                                const int *array, int nelem)
1339 {
1340         int i;
1341
1342         str[0] = '\0';
1343
1344         for (i = 0; i < nelem; i++) {
1345                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1346                 if (r >= len)
1347                         return;
1348                 str += r;
1349                 len -= r;
1350         }
1351 }
1352
1353 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1354 {
1355         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1356         char str[128]; /* FIXME: too big for stack? */
1357
1358         if (!drm_debug_enabled(DRM_UT_KMS))
1359                 return;
1360
1361         snprintf_int_array(str, sizeof(str),
1362                            intel_dp->source_rates, intel_dp->num_source_rates);
1363         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1364
1365         snprintf_int_array(str, sizeof(str),
1366                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1367         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1368
1369         snprintf_int_array(str, sizeof(str),
1370                            intel_dp->common_rates, intel_dp->num_common_rates);
1371         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1372 }
1373
1374 int
1375 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1376 {
1377         int len;
1378
1379         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1380
1381         return intel_dp_common_rate(intel_dp, len - 1);
1382 }
1383
1384 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1385 {
1386         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1387         int i = intel_dp_rate_index(intel_dp->sink_rates,
1388                                     intel_dp->num_sink_rates, rate);
1389
1390         if (drm_WARN_ON(&i915->drm, i < 0))
1391                 i = 0;
1392
1393         return i;
1394 }
1395
1396 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1397                            u8 *link_bw, u8 *rate_select)
1398 {
1399         /* eDP 1.4 rate select method. */
1400         if (intel_dp->use_rate_select) {
1401                 *link_bw = 0;
1402                 *rate_select =
1403                         intel_dp_rate_select(intel_dp, port_clock);
1404         } else {
1405                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1406                 *rate_select = 0;
1407         }
1408 }
1409
1410 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1411 {
1412         struct intel_connector *connector = intel_dp->attached_connector;
1413
1414         return connector->base.display_info.is_hdmi;
1415 }
1416
1417 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1418                                          const struct intel_crtc_state *pipe_config)
1419 {
1420         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1421         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1422
1423         if (DISPLAY_VER(dev_priv) >= 12)
1424                 return true;
1425
1426         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1427                 return true;
1428
1429         return false;
1430 }
1431
1432 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1433                            const struct intel_connector *connector,
1434                            const struct intel_crtc_state *pipe_config)
1435 {
1436         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1437                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1438 }
1439
1440 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1441                                   const struct intel_crtc_state *crtc_state)
1442 {
1443         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1444                 return false;
1445
1446         return intel_dsc_source_support(crtc_state) &&
1447                 connector->dp.dsc_decompression_aux &&
1448                 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1449 }
1450
1451 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1452                                      const struct intel_crtc_state *crtc_state,
1453                                      int bpc, bool respect_downstream_limits)
1454 {
1455         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1456
1457         /*
1458          * Current bpc could already be below 8bpc due to
1459          * FDI bandwidth constraints or other limits.
1460          * HDMI minimum is 8bpc however.
1461          */
1462         bpc = max(bpc, 8);
1463
1464         /*
1465          * We will never exceed downstream TMDS clock limits while
1466          * attempting deep color. If the user insists on forcing an
1467          * out of spec mode they will have to be satisfied with 8bpc.
1468          */
1469         if (!respect_downstream_limits)
1470                 bpc = 8;
1471
1472         for (; bpc >= 8; bpc -= 2) {
1473                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1474                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1475                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1476                                               respect_downstream_limits) == MODE_OK)
1477                         return bpc;
1478         }
1479
1480         return -EINVAL;
1481 }
1482
1483 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1484                             const struct intel_crtc_state *crtc_state,
1485                             bool respect_downstream_limits)
1486 {
1487         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1488         struct intel_connector *intel_connector = intel_dp->attached_connector;
1489         int bpp, bpc;
1490
1491         bpc = crtc_state->pipe_bpp / 3;
1492
1493         if (intel_dp->dfp.max_bpc)
1494                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1495
1496         if (intel_dp->dfp.min_tmds_clock) {
1497                 int max_hdmi_bpc;
1498
1499                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1500                                                          respect_downstream_limits);
1501                 if (max_hdmi_bpc < 0)
1502                         return 0;
1503
1504                 bpc = min(bpc, max_hdmi_bpc);
1505         }
1506
1507         bpp = bpc * 3;
1508         if (intel_dp_is_edp(intel_dp)) {
1509                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1510                 if (intel_connector->base.display_info.bpc == 0 &&
1511                     intel_connector->panel.vbt.edp.bpp &&
1512                     intel_connector->panel.vbt.edp.bpp < bpp) {
1513                         drm_dbg_kms(&dev_priv->drm,
1514                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1515                                     intel_connector->panel.vbt.edp.bpp);
1516                         bpp = intel_connector->panel.vbt.edp.bpp;
1517                 }
1518         }
1519
1520         return bpp;
1521 }
1522
1523 /* Adjust link config limits based on compliance test requests. */
1524 void
1525 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1526                                   struct intel_crtc_state *pipe_config,
1527                                   struct link_config_limits *limits)
1528 {
1529         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1530
1531         /* For DP Compliance we override the computed bpp for the pipe */
1532         if (intel_dp->compliance.test_data.bpc != 0) {
1533                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1534
1535                 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1536                 pipe_config->dither_force_disable = bpp == 6 * 3;
1537
1538                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1539         }
1540
1541         /* Use values requested by Compliance Test Request */
1542         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1543                 int index;
1544
1545                 /* Validate the compliance test data since max values
1546                  * might have changed due to link train fallback.
1547                  */
1548                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1549                                                intel_dp->compliance.test_lane_count)) {
1550                         index = intel_dp_rate_index(intel_dp->common_rates,
1551                                                     intel_dp->num_common_rates,
1552                                                     intel_dp->compliance.test_link_rate);
1553                         if (index >= 0)
1554                                 limits->min_rate = limits->max_rate =
1555                                         intel_dp->compliance.test_link_rate;
1556                         limits->min_lane_count = limits->max_lane_count =
1557                                 intel_dp->compliance.test_lane_count;
1558                 }
1559         }
1560 }
1561
1562 static bool has_seamless_m_n(struct intel_connector *connector)
1563 {
1564         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1565
1566         /*
1567          * Seamless M/N reprogramming only implemented
1568          * for BDW+ double buffered M/N registers so far.
1569          */
1570         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1571                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1572 }
1573
1574 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1575                                const struct drm_connector_state *conn_state)
1576 {
1577         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1578         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1579
1580         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1581         if (has_seamless_m_n(connector))
1582                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1583         else
1584                 return adjusted_mode->crtc_clock;
1585 }
1586
1587 /* Optimize link config in order: max bpp, min clock, min lanes */
1588 static int
1589 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1590                                   struct intel_crtc_state *pipe_config,
1591                                   const struct drm_connector_state *conn_state,
1592                                   const struct link_config_limits *limits)
1593 {
1594         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1595         int mode_rate, link_rate, link_avail;
1596
1597         for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1598              bpp >= to_bpp_int(limits->link.min_bpp_x16);
1599              bpp -= 2 * 3) {
1600                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1601
1602                 mode_rate = intel_dp_link_required(clock, link_bpp);
1603
1604                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1605                         link_rate = intel_dp_common_rate(intel_dp, i);
1606                         if (link_rate < limits->min_rate ||
1607                             link_rate > limits->max_rate)
1608                                 continue;
1609
1610                         for (lane_count = limits->min_lane_count;
1611                              lane_count <= limits->max_lane_count;
1612                              lane_count <<= 1) {
1613                                 link_avail = intel_dp_max_data_rate(link_rate,
1614                                                                     lane_count);
1615
1616                                 if (mode_rate <= link_avail) {
1617                                         pipe_config->lane_count = lane_count;
1618                                         pipe_config->pipe_bpp = bpp;
1619                                         pipe_config->port_clock = link_rate;
1620
1621                                         return 0;
1622                                 }
1623                         }
1624                 }
1625         }
1626
1627         return -EINVAL;
1628 }
1629
1630 static
1631 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1632 {
1633         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1634         if (DISPLAY_VER(i915) >= 12)
1635                 return 12;
1636         if (DISPLAY_VER(i915) == 11)
1637                 return 10;
1638
1639         return 0;
1640 }
1641
1642 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1643                                  u8 max_req_bpc)
1644 {
1645         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1646         int i, num_bpc;
1647         u8 dsc_bpc[3] = {};
1648         u8 dsc_max_bpc;
1649
1650         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1651
1652         if (!dsc_max_bpc)
1653                 return dsc_max_bpc;
1654
1655         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1656
1657         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1658                                                        dsc_bpc);
1659         for (i = 0; i < num_bpc; i++) {
1660                 if (dsc_max_bpc >= dsc_bpc[i])
1661                         return dsc_bpc[i] * 3;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1668 {
1669         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1670 }
1671
1672 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1673 {
1674         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1675                 DP_DSC_MINOR_SHIFT;
1676 }
1677
1678 static int intel_dp_get_slice_height(int vactive)
1679 {
1680         int slice_height;
1681
1682         /*
1683          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1684          * lines is an optimal slice height, but any size can be used as long as
1685          * vertical active integer multiple and maximum vertical slice count
1686          * requirements are met.
1687          */
1688         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1689                 if (vactive % slice_height == 0)
1690                         return slice_height;
1691
1692         /*
1693          * Highly unlikely we reach here as most of the resolutions will end up
1694          * finding appropriate slice_height in above loop but returning
1695          * slice_height as 2 here as it should work with all resolutions.
1696          */
1697         return 2;
1698 }
1699
1700 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1701                                        struct intel_crtc_state *crtc_state)
1702 {
1703         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1704         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1705         u8 line_buf_depth;
1706         int ret;
1707
1708         /*
1709          * RC_MODEL_SIZE is currently a constant across all configurations.
1710          *
1711          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1712          * DP_DSC_RC_BUF_SIZE for this.
1713          */
1714         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1715         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1716
1717         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1718
1719         ret = intel_dsc_compute_params(crtc_state);
1720         if (ret)
1721                 return ret;
1722
1723         vdsc_cfg->dsc_version_major =
1724                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1725                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1726         vdsc_cfg->dsc_version_minor =
1727                 min(intel_dp_source_dsc_version_minor(i915),
1728                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1729         if (vdsc_cfg->convert_rgb)
1730                 vdsc_cfg->convert_rgb =
1731                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1732                         DP_DSC_RGB;
1733
1734         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1735         if (!line_buf_depth) {
1736                 drm_dbg_kms(&i915->drm,
1737                             "DSC Sink Line Buffer Depth invalid\n");
1738                 return -EINVAL;
1739         }
1740
1741         if (vdsc_cfg->dsc_version_minor == 2)
1742                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1743                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1744         else
1745                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1746                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1747
1748         vdsc_cfg->block_pred_enable =
1749                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1750                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1751
1752         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1753 }
1754
1755 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1756                                          enum intel_output_format output_format)
1757 {
1758         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1759         u8 sink_dsc_format;
1760
1761         switch (output_format) {
1762         case INTEL_OUTPUT_FORMAT_RGB:
1763                 sink_dsc_format = DP_DSC_RGB;
1764                 break;
1765         case INTEL_OUTPUT_FORMAT_YCBCR444:
1766                 sink_dsc_format = DP_DSC_YCbCr444;
1767                 break;
1768         case INTEL_OUTPUT_FORMAT_YCBCR420:
1769                 if (min(intel_dp_source_dsc_version_minor(i915),
1770                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1771                         return false;
1772                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1773                 break;
1774         default:
1775                 return false;
1776         }
1777
1778         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1779 }
1780
1781 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1782                                             u32 lane_count, u32 mode_clock,
1783                                             enum intel_output_format output_format,
1784                                             int timeslots)
1785 {
1786         u32 available_bw, required_bw;
1787
1788         available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
1789         required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1790
1791         return available_bw > required_bw;
1792 }
1793
1794 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1795                                    struct intel_crtc_state *pipe_config,
1796                                    struct link_config_limits *limits,
1797                                    u16 compressed_bppx16,
1798                                    int timeslots)
1799 {
1800         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1801         int link_rate, lane_count;
1802         int i;
1803
1804         for (i = 0; i < intel_dp->num_common_rates; i++) {
1805                 link_rate = intel_dp_common_rate(intel_dp, i);
1806                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1807                         continue;
1808
1809                 for (lane_count = limits->min_lane_count;
1810                      lane_count <= limits->max_lane_count;
1811                      lane_count <<= 1) {
1812                         if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1813                                                              lane_count, adjusted_mode->clock,
1814                                                              pipe_config->output_format,
1815                                                              timeslots))
1816                                 continue;
1817
1818                         pipe_config->lane_count = lane_count;
1819                         pipe_config->port_clock = link_rate;
1820
1821                         return 0;
1822                 }
1823         }
1824
1825         return -EINVAL;
1826 }
1827
1828 static
1829 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1830                                             struct intel_crtc_state *pipe_config,
1831                                             int bpc)
1832 {
1833         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1834
1835         if (max_bppx16)
1836                 return max_bppx16;
1837         /*
1838          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1839          * values as given in spec Table 2-157 DP v2.0
1840          */
1841         switch (pipe_config->output_format) {
1842         case INTEL_OUTPUT_FORMAT_RGB:
1843         case INTEL_OUTPUT_FORMAT_YCBCR444:
1844                 return (3 * bpc) << 4;
1845         case INTEL_OUTPUT_FORMAT_YCBCR420:
1846                 return (3 * (bpc / 2)) << 4;
1847         default:
1848                 MISSING_CASE(pipe_config->output_format);
1849                 break;
1850         }
1851
1852         return 0;
1853 }
1854
1855 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1856 {
1857         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1858         switch (pipe_config->output_format) {
1859         case INTEL_OUTPUT_FORMAT_RGB:
1860         case INTEL_OUTPUT_FORMAT_YCBCR444:
1861                 return 8;
1862         case INTEL_OUTPUT_FORMAT_YCBCR420:
1863                 return 6;
1864         default:
1865                 MISSING_CASE(pipe_config->output_format);
1866                 break;
1867         }
1868
1869         return 0;
1870 }
1871
1872 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1873                                          struct intel_crtc_state *pipe_config,
1874                                          int bpc)
1875 {
1876         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1877                                                        pipe_config, bpc) >> 4;
1878 }
1879
1880 static int dsc_src_min_compressed_bpp(void)
1881 {
1882         /* Min Compressed bpp supported by source is 8 */
1883         return 8;
1884 }
1885
1886 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1887 {
1888         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1889
1890         /*
1891          * Max Compressed bpp for Gen 13+ is 27bpp.
1892          * For earlier platform is 23bpp. (Bspec:49259).
1893          */
1894         if (DISPLAY_VER(i915) < 13)
1895                 return 23;
1896         else
1897                 return 27;
1898 }
1899
1900 /*
1901  * From a list of valid compressed bpps try different compressed bpp and find a
1902  * suitable link configuration that can support it.
1903  */
1904 static int
1905 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1906                             struct intel_crtc_state *pipe_config,
1907                             struct link_config_limits *limits,
1908                             int dsc_max_bpp,
1909                             int dsc_min_bpp,
1910                             int pipe_bpp,
1911                             int timeslots)
1912 {
1913         int i, ret;
1914
1915         /* Compressed BPP should be less than the Input DSC bpp */
1916         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1917
1918         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1919                 if (valid_dsc_bpp[i] < dsc_min_bpp ||
1920                     valid_dsc_bpp[i] > dsc_max_bpp)
1921                         break;
1922
1923                 ret = dsc_compute_link_config(intel_dp,
1924                                               pipe_config,
1925                                               limits,
1926                                               valid_dsc_bpp[i] << 4,
1927                                               timeslots);
1928                 if (ret == 0) {
1929                         pipe_config->dsc.compressed_bpp_x16 =
1930                                 to_bpp_x16(valid_dsc_bpp[i]);
1931                         return 0;
1932                 }
1933         }
1934
1935         return -EINVAL;
1936 }
1937
1938 /*
1939  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1940  * uncompressed bpp-1. So we start from max compressed bpp and see if any
1941  * link configuration is able to support that compressed bpp, if not we
1942  * step down and check for lower compressed bpp.
1943  */
1944 static int
1945 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1946                               const struct intel_connector *connector,
1947                               struct intel_crtc_state *pipe_config,
1948                               struct link_config_limits *limits,
1949                               int dsc_max_bpp,
1950                               int dsc_min_bpp,
1951                               int pipe_bpp,
1952                               int timeslots)
1953 {
1954         u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1955         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1956         u16 compressed_bppx16;
1957         u8 bppx16_step;
1958         int ret;
1959
1960         if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1961                 bppx16_step = 16;
1962         else
1963                 bppx16_step = 16 / bppx16_incr;
1964
1965         /* Compressed BPP should be less than the Input DSC bpp */
1966         dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1967         dsc_min_bpp = dsc_min_bpp << 4;
1968
1969         for (compressed_bppx16 = dsc_max_bpp;
1970              compressed_bppx16 >= dsc_min_bpp;
1971              compressed_bppx16 -= bppx16_step) {
1972                 if (intel_dp->force_dsc_fractional_bpp_en &&
1973                     !to_bpp_frac(compressed_bppx16))
1974                         continue;
1975                 ret = dsc_compute_link_config(intel_dp,
1976                                               pipe_config,
1977                                               limits,
1978                                               compressed_bppx16,
1979                                               timeslots);
1980                 if (ret == 0) {
1981                         pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1982                         if (intel_dp->force_dsc_fractional_bpp_en &&
1983                             to_bpp_frac(compressed_bppx16))
1984                                 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1985
1986                         return 0;
1987                 }
1988         }
1989         return -EINVAL;
1990 }
1991
1992 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1993                                       const struct intel_connector *connector,
1994                                       struct intel_crtc_state *pipe_config,
1995                                       struct link_config_limits *limits,
1996                                       int pipe_bpp,
1997                                       int timeslots)
1998 {
1999         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2000         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2001         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2002         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2003         int dsc_joiner_max_bpp;
2004
2005         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2006         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2007         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2008         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2009
2010         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2011         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2012                                                                 pipe_config,
2013                                                                 pipe_bpp / 3);
2014         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2015
2016         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2017                                                                 adjusted_mode->hdisplay,
2018                                                                 pipe_config->bigjoiner_pipes);
2019         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2020         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2021
2022         if (DISPLAY_VER(i915) >= 13)
2023                 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2024                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2025         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2026                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2027 }
2028
2029 static
2030 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2031 {
2032         /* Min DSC Input BPC for ICL+ is 8 */
2033         return HAS_DSC(i915) ? 8 : 0;
2034 }
2035
2036 static
2037 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2038                                 struct drm_connector_state *conn_state,
2039                                 struct link_config_limits *limits,
2040                                 int pipe_bpp)
2041 {
2042         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2043
2044         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2045         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2046
2047         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2048         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2049
2050         return pipe_bpp >= dsc_min_pipe_bpp &&
2051                pipe_bpp <= dsc_max_pipe_bpp;
2052 }
2053
2054 static
2055 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2056                                 struct drm_connector_state *conn_state,
2057                                 struct link_config_limits *limits)
2058 {
2059         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2060         int forced_bpp;
2061
2062         if (!intel_dp->force_dsc_bpc)
2063                 return 0;
2064
2065         forced_bpp = intel_dp->force_dsc_bpc * 3;
2066
2067         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2068                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2069                 return forced_bpp;
2070         }
2071
2072         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2073                     intel_dp->force_dsc_bpc);
2074
2075         return 0;
2076 }
2077
2078 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2079                                          struct intel_crtc_state *pipe_config,
2080                                          struct drm_connector_state *conn_state,
2081                                          struct link_config_limits *limits,
2082                                          int timeslots)
2083 {
2084         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2085         const struct intel_connector *connector =
2086                 to_intel_connector(conn_state->connector);
2087         u8 max_req_bpc = conn_state->max_requested_bpc;
2088         u8 dsc_max_bpc, dsc_max_bpp;
2089         u8 dsc_min_bpc, dsc_min_bpp;
2090         u8 dsc_bpc[3] = {};
2091         int forced_bpp, pipe_bpp;
2092         int num_bpc, i, ret;
2093
2094         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2095
2096         if (forced_bpp) {
2097                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2098                                                  limits, forced_bpp, timeslots);
2099                 if (ret == 0) {
2100                         pipe_config->pipe_bpp = forced_bpp;
2101                         return 0;
2102                 }
2103         }
2104
2105         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2106         if (!dsc_max_bpc)
2107                 return -EINVAL;
2108
2109         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2110         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2111
2112         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2113         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2114
2115         /*
2116          * Get the maximum DSC bpc that will be supported by any valid
2117          * link configuration and compressed bpp.
2118          */
2119         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2120         for (i = 0; i < num_bpc; i++) {
2121                 pipe_bpp = dsc_bpc[i] * 3;
2122                 if (pipe_bpp < dsc_min_bpp)
2123                         break;
2124                 if (pipe_bpp > dsc_max_bpp)
2125                         continue;
2126                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2127                                                  limits, pipe_bpp, timeslots);
2128                 if (ret == 0) {
2129                         pipe_config->pipe_bpp = pipe_bpp;
2130                         return 0;
2131                 }
2132         }
2133
2134         return -EINVAL;
2135 }
2136
2137 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2138                                           struct intel_crtc_state *pipe_config,
2139                                           struct drm_connector_state *conn_state,
2140                                           struct link_config_limits *limits)
2141 {
2142         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2143         struct intel_connector *connector =
2144                 to_intel_connector(conn_state->connector);
2145         int pipe_bpp, forced_bpp;
2146         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2147         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2148
2149         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2150
2151         if (forced_bpp) {
2152                 pipe_bpp = forced_bpp;
2153         } else {
2154                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2155
2156                 /* For eDP use max bpp that can be supported with DSC. */
2157                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2158                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2159                         drm_dbg_kms(&i915->drm,
2160                                     "Computed BPC is not in DSC BPC limits\n");
2161                         return -EINVAL;
2162                 }
2163         }
2164         pipe_config->port_clock = limits->max_rate;
2165         pipe_config->lane_count = limits->max_lane_count;
2166
2167         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2168         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2169         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2170         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2171
2172         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2173         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2174                                                                 pipe_config,
2175                                                                 pipe_bpp / 3);
2176         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2177         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2178
2179         /* Compressed BPP should be less than the Input DSC bpp */
2180         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2181
2182         pipe_config->dsc.compressed_bpp_x16 =
2183                 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2184
2185         pipe_config->pipe_bpp = pipe_bpp;
2186
2187         return 0;
2188 }
2189
2190 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2191                                 struct intel_crtc_state *pipe_config,
2192                                 struct drm_connector_state *conn_state,
2193                                 struct link_config_limits *limits,
2194                                 int timeslots,
2195                                 bool compute_pipe_bpp)
2196 {
2197         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2198         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2199         const struct intel_connector *connector =
2200                 to_intel_connector(conn_state->connector);
2201         const struct drm_display_mode *adjusted_mode =
2202                 &pipe_config->hw.adjusted_mode;
2203         int ret;
2204
2205         pipe_config->fec_enable = pipe_config->fec_enable ||
2206                 (!intel_dp_is_edp(intel_dp) &&
2207                  intel_dp_supports_fec(intel_dp, connector, pipe_config));
2208
2209         if (!intel_dp_supports_dsc(connector, pipe_config))
2210                 return -EINVAL;
2211
2212         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2213                 return -EINVAL;
2214
2215         /*
2216          * compute pipe bpp is set to false for DP MST DSC case
2217          * and compressed_bpp is calculated same time once
2218          * vpci timeslots are allocated, because overall bpp
2219          * calculation procedure is bit different for MST case.
2220          */
2221         if (compute_pipe_bpp) {
2222                 if (intel_dp_is_edp(intel_dp))
2223                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2224                                                              conn_state, limits);
2225                 else
2226                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2227                                                             conn_state, limits, timeslots);
2228                 if (ret) {
2229                         drm_dbg_kms(&dev_priv->drm,
2230                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2231                         return ret;
2232                 }
2233         }
2234
2235         /* Calculate Slice count */
2236         if (intel_dp_is_edp(intel_dp)) {
2237                 pipe_config->dsc.slice_count =
2238                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2239                                                         true);
2240                 if (!pipe_config->dsc.slice_count) {
2241                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2242                                     pipe_config->dsc.slice_count);
2243                         return -EINVAL;
2244                 }
2245         } else {
2246                 u8 dsc_dp_slice_count;
2247
2248                 dsc_dp_slice_count =
2249                         intel_dp_dsc_get_slice_count(connector,
2250                                                      adjusted_mode->crtc_clock,
2251                                                      adjusted_mode->crtc_hdisplay,
2252                                                      pipe_config->bigjoiner_pipes);
2253                 if (!dsc_dp_slice_count) {
2254                         drm_dbg_kms(&dev_priv->drm,
2255                                     "Compressed Slice Count not supported\n");
2256                         return -EINVAL;
2257                 }
2258
2259                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2260         }
2261         /*
2262          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2263          * is greater than the maximum Cdclock and if slice count is even
2264          * then we need to use 2 VDSC instances.
2265          */
2266         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2267                 pipe_config->dsc.dsc_split = true;
2268
2269         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2270         if (ret < 0) {
2271                 drm_dbg_kms(&dev_priv->drm,
2272                             "Cannot compute valid DSC parameters for Input Bpp = %d"
2273                             "Compressed BPP = " BPP_X16_FMT "\n",
2274                             pipe_config->pipe_bpp,
2275                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2276                 return ret;
2277         }
2278
2279         pipe_config->dsc.compression_enable = true;
2280         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2281                     "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2282                     pipe_config->pipe_bpp,
2283                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2284                     pipe_config->dsc.slice_count);
2285
2286         return 0;
2287 }
2288
2289 /**
2290  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2291  * @intel_dp: intel DP
2292  * @crtc_state: crtc state
2293  * @dsc: DSC compression mode
2294  * @limits: link configuration limits
2295  *
2296  * Calculates the output link min, max bpp values in @limits based on the
2297  * pipe bpp range, @crtc_state and @dsc mode.
2298  *
2299  * Returns %true in case of success.
2300  */
2301 bool
2302 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2303                                         const struct intel_crtc_state *crtc_state,
2304                                         bool dsc,
2305                                         struct link_config_limits *limits)
2306 {
2307         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2308         const struct drm_display_mode *adjusted_mode =
2309                 &crtc_state->hw.adjusted_mode;
2310         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2311         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2312         int max_link_bpp_x16;
2313
2314         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2315                                to_bpp_x16(limits->pipe.max_bpp));
2316
2317         if (!dsc) {
2318                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2319
2320                 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2321                         return false;
2322
2323                 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2324         } else {
2325                 /*
2326                  * TODO: set the DSC link limits already here, atm these are
2327                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2328                  * intel_dp_dsc_compute_pipe_bpp()
2329                  */
2330                 limits->link.min_bpp_x16 = 0;
2331         }
2332
2333         limits->link.max_bpp_x16 = max_link_bpp_x16;
2334
2335         drm_dbg_kms(&i915->drm,
2336                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2337                     encoder->base.base.id, encoder->base.name,
2338                     crtc->base.base.id, crtc->base.name,
2339                     adjusted_mode->crtc_clock,
2340                     dsc ? "on" : "off",
2341                     limits->max_lane_count,
2342                     limits->max_rate,
2343                     limits->pipe.max_bpp,
2344                     BPP_X16_ARGS(limits->link.max_bpp_x16));
2345
2346         return true;
2347 }
2348
2349 static bool
2350 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2351                                struct intel_crtc_state *crtc_state,
2352                                bool respect_downstream_limits,
2353                                bool dsc,
2354                                struct link_config_limits *limits)
2355 {
2356         limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2357         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2358
2359         /* FIXME 128b/132b SST support missing */
2360         limits->max_rate = min(limits->max_rate, 810000);
2361
2362         limits->min_lane_count = 1;
2363         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2364
2365         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2366         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2367                                                      respect_downstream_limits);
2368
2369         if (intel_dp->use_max_params) {
2370                 /*
2371                  * Use the maximum clock and number of lanes the eDP panel
2372                  * advertizes being capable of in case the initial fast
2373                  * optimal params failed us. The panels are generally
2374                  * designed to support only a single clock and lane
2375                  * configuration, and typically on older panels these
2376                  * values correspond to the native resolution of the panel.
2377                  */
2378                 limits->min_lane_count = limits->max_lane_count;
2379                 limits->min_rate = limits->max_rate;
2380         }
2381
2382         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2383
2384         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2385                                                        crtc_state,
2386                                                        dsc,
2387                                                        limits);
2388 }
2389
2390 static int
2391 intel_dp_compute_link_config(struct intel_encoder *encoder,
2392                              struct intel_crtc_state *pipe_config,
2393                              struct drm_connector_state *conn_state,
2394                              bool respect_downstream_limits)
2395 {
2396         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2397         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2398         const struct intel_connector *connector =
2399                 to_intel_connector(conn_state->connector);
2400         const struct drm_display_mode *adjusted_mode =
2401                 &pipe_config->hw.adjusted_mode;
2402         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2403         struct link_config_limits limits;
2404         bool joiner_needs_dsc = false;
2405         bool dsc_needed;
2406         int ret = 0;
2407
2408         if (pipe_config->fec_enable &&
2409             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2410                 return -EINVAL;
2411
2412         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2413                                     adjusted_mode->crtc_clock))
2414                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2415
2416         /*
2417          * Pipe joiner needs compression up to display 12 due to bandwidth
2418          * limitation. DG2 onwards pipe joiner can be enabled without
2419          * compression.
2420          */
2421         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2422
2423         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2424                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2425                                                      respect_downstream_limits,
2426                                                      false,
2427                                                      &limits);
2428
2429         if (!dsc_needed) {
2430                 /*
2431                  * Optimize for slow and wide for everything, because there are some
2432                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2433                  */
2434                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2435                                                         conn_state, &limits);
2436                 if (ret)
2437                         dsc_needed = true;
2438         }
2439
2440         if (dsc_needed) {
2441                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2442                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2443                             str_yes_no(intel_dp->force_dsc_en));
2444
2445                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2446                                                     respect_downstream_limits,
2447                                                     true,
2448                                                     &limits))
2449                         return -EINVAL;
2450
2451                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2452                                                   conn_state, &limits, 64, true);
2453                 if (ret < 0)
2454                         return ret;
2455         }
2456
2457         if (pipe_config->dsc.compression_enable) {
2458                 drm_dbg_kms(&i915->drm,
2459                             "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
2460                             pipe_config->lane_count, pipe_config->port_clock,
2461                             pipe_config->pipe_bpp,
2462                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2463
2464                 drm_dbg_kms(&i915->drm,
2465                             "DP link rate required %i available %i\n",
2466                             intel_dp_link_required(adjusted_mode->crtc_clock,
2467                                                    to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
2468                             intel_dp_max_data_rate(pipe_config->port_clock,
2469                                                    pipe_config->lane_count));
2470         } else {
2471                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2472                             pipe_config->lane_count, pipe_config->port_clock,
2473                             pipe_config->pipe_bpp);
2474
2475                 drm_dbg_kms(&i915->drm,
2476                             "DP link rate required %i available %i\n",
2477                             intel_dp_link_required(adjusted_mode->crtc_clock,
2478                                                    pipe_config->pipe_bpp),
2479                             intel_dp_max_data_rate(pipe_config->port_clock,
2480                                                    pipe_config->lane_count));
2481         }
2482         return 0;
2483 }
2484
2485 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2486                                   const struct drm_connector_state *conn_state)
2487 {
2488         const struct intel_digital_connector_state *intel_conn_state =
2489                 to_intel_digital_connector_state(conn_state);
2490         const struct drm_display_mode *adjusted_mode =
2491                 &crtc_state->hw.adjusted_mode;
2492
2493         /*
2494          * Our YCbCr output is always limited range.
2495          * crtc_state->limited_color_range only applies to RGB,
2496          * and it must never be set for YCbCr or we risk setting
2497          * some conflicting bits in TRANSCONF which will mess up
2498          * the colors on the monitor.
2499          */
2500         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2501                 return false;
2502
2503         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2504                 /*
2505                  * See:
2506                  * CEA-861-E - 5.1 Default Encoding Parameters
2507                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2508                  */
2509                 return crtc_state->pipe_bpp != 18 &&
2510                         drm_default_rgb_quant_range(adjusted_mode) ==
2511                         HDMI_QUANTIZATION_RANGE_LIMITED;
2512         } else {
2513                 return intel_conn_state->broadcast_rgb ==
2514                         INTEL_BROADCAST_RGB_LIMITED;
2515         }
2516 }
2517
2518 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2519                                     enum port port)
2520 {
2521         if (IS_G4X(dev_priv))
2522                 return false;
2523         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2524                 return false;
2525
2526         return true;
2527 }
2528
2529 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2530                                              const struct drm_connector_state *conn_state,
2531                                              struct drm_dp_vsc_sdp *vsc)
2532 {
2533         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2534         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2535
2536         if (crtc_state->has_panel_replay) {
2537                 /*
2538                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2539                  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2540                  * Encoding/Colorimetry Format indication.
2541                  */
2542                 vsc->revision = 0x7;
2543         } else {
2544                 /*
2545                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2546                  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2547                  * Colorimetry Format indication.
2548                  */
2549                 vsc->revision = 0x5;
2550         }
2551
2552         vsc->length = 0x13;
2553
2554         /* DP 1.4a spec, Table 2-120 */
2555         switch (crtc_state->output_format) {
2556         case INTEL_OUTPUT_FORMAT_YCBCR444:
2557                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2558                 break;
2559         case INTEL_OUTPUT_FORMAT_YCBCR420:
2560                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2561                 break;
2562         case INTEL_OUTPUT_FORMAT_RGB:
2563         default:
2564                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2565         }
2566
2567         switch (conn_state->colorspace) {
2568         case DRM_MODE_COLORIMETRY_BT709_YCC:
2569                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2570                 break;
2571         case DRM_MODE_COLORIMETRY_XVYCC_601:
2572                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2573                 break;
2574         case DRM_MODE_COLORIMETRY_XVYCC_709:
2575                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2576                 break;
2577         case DRM_MODE_COLORIMETRY_SYCC_601:
2578                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2579                 break;
2580         case DRM_MODE_COLORIMETRY_OPYCC_601:
2581                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2582                 break;
2583         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2584                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2585                 break;
2586         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2587                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2588                 break;
2589         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2590                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2591                 break;
2592         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2593         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2594                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2595                 break;
2596         default:
2597                 /*
2598                  * RGB->YCBCR color conversion uses the BT.709
2599                  * color space.
2600                  */
2601                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2602                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2603                 else
2604                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2605                 break;
2606         }
2607
2608         vsc->bpc = crtc_state->pipe_bpp / 3;
2609
2610         /* only RGB pixelformat supports 6 bpc */
2611         drm_WARN_ON(&dev_priv->drm,
2612                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2613
2614         /* all YCbCr are always limited range */
2615         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2616         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2617 }
2618
2619 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2620                                      struct intel_crtc_state *crtc_state,
2621                                      const struct drm_connector_state *conn_state)
2622 {
2623         struct drm_dp_vsc_sdp *vsc;
2624
2625         if ((!intel_dp->colorimetry_support ||
2626              !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2627             !crtc_state->has_psr)
2628                 return;
2629
2630         vsc = &crtc_state->infoframes.vsc;
2631
2632         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2633         vsc->sdp_type = DP_SDP_VSC;
2634
2635         /* Needs colorimetry */
2636         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2637                 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2638                                                  vsc);
2639         } else if (crtc_state->has_psr2) {
2640                 /*
2641                  * [PSR2 without colorimetry]
2642                  * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2643                  * 3D stereo + PSR/PSR2 + Y-coordinate.
2644                  */
2645                 vsc->revision = 0x4;
2646                 vsc->length = 0xe;
2647         } else if (crtc_state->has_panel_replay) {
2648                 /*
2649                  * [Panel Replay without colorimetry info]
2650                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2651                  * VSC SDP supporting 3D stereo + Panel Replay.
2652                  */
2653                 vsc->revision = 0x6;
2654                 vsc->length = 0x10;
2655         } else {
2656                 /*
2657                  * [PSR1]
2658                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2659                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2660                  * higher).
2661                  */
2662                 vsc->revision = 0x2;
2663                 vsc->length = 0x8;
2664         }
2665 }
2666
2667 static void
2668 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2669                                             struct intel_crtc_state *crtc_state,
2670                                             const struct drm_connector_state *conn_state)
2671 {
2672         int ret;
2673         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2674         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2675
2676         if (!conn_state->hdr_output_metadata)
2677                 return;
2678
2679         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2680
2681         if (ret) {
2682                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2683                 return;
2684         }
2685
2686         crtc_state->infoframes.enable |=
2687                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2688 }
2689
2690 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2691                                     enum transcoder cpu_transcoder)
2692 {
2693         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2694                 return true;
2695
2696         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2697 }
2698
2699 static bool can_enable_drrs(struct intel_connector *connector,
2700                             const struct intel_crtc_state *pipe_config,
2701                             const struct drm_display_mode *downclock_mode)
2702 {
2703         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2704
2705         if (pipe_config->vrr.enable)
2706                 return false;
2707
2708         /*
2709          * DRRS and PSR can't be enable together, so giving preference to PSR
2710          * as it allows more power-savings by complete shutting down display,
2711          * so to guarantee this, intel_drrs_compute_config() must be called
2712          * after intel_psr_compute_config().
2713          */
2714         if (pipe_config->has_psr)
2715                 return false;
2716
2717         /* FIXME missing FDI M2/N2 etc. */
2718         if (pipe_config->has_pch_encoder)
2719                 return false;
2720
2721         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2722                 return false;
2723
2724         return downclock_mode &&
2725                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2726 }
2727
2728 static void
2729 intel_dp_drrs_compute_config(struct intel_connector *connector,
2730                              struct intel_crtc_state *pipe_config,
2731                              int link_bpp_x16)
2732 {
2733         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2734         const struct drm_display_mode *downclock_mode =
2735                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2736         int pixel_clock;
2737
2738         if (has_seamless_m_n(connector))
2739                 pipe_config->update_m_n = true;
2740
2741         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2742                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2743                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2744                 return;
2745         }
2746
2747         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2748                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2749
2750         pipe_config->has_drrs = true;
2751
2752         pixel_clock = downclock_mode->clock;
2753         if (pipe_config->splitter.enable)
2754                 pixel_clock /= pipe_config->splitter.link_count;
2755
2756         intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2757                                pipe_config->port_clock,
2758                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2759                                &pipe_config->dp_m2_n2);
2760
2761         /* FIXME: abstract this better */
2762         if (pipe_config->splitter.enable)
2763                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2764 }
2765
2766 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2767                                struct intel_crtc_state *crtc_state,
2768                                const struct drm_connector_state *conn_state)
2769 {
2770         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2771         const struct intel_digital_connector_state *intel_conn_state =
2772                 to_intel_digital_connector_state(conn_state);
2773         struct intel_connector *connector =
2774                 to_intel_connector(conn_state->connector);
2775
2776         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2777             !intel_dp_port_has_audio(i915, encoder->port))
2778                 return false;
2779
2780         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2781                 return connector->base.display_info.has_audio;
2782         else
2783                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2784 }
2785
2786 static int
2787 intel_dp_compute_output_format(struct intel_encoder *encoder,
2788                                struct intel_crtc_state *crtc_state,
2789                                struct drm_connector_state *conn_state,
2790                                bool respect_downstream_limits)
2791 {
2792         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2793         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2794         struct intel_connector *connector = intel_dp->attached_connector;
2795         const struct drm_display_info *info = &connector->base.display_info;
2796         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2797         bool ycbcr_420_only;
2798         int ret;
2799
2800         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2801
2802         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2803                 drm_dbg_kms(&i915->drm,
2804                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2805                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2806         } else {
2807                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2808         }
2809
2810         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2811
2812         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2813                                            respect_downstream_limits);
2814         if (ret) {
2815                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2816                     !connector->base.ycbcr_420_allowed ||
2817                     !drm_mode_is_420_also(info, adjusted_mode))
2818                         return ret;
2819
2820                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2821                 crtc_state->output_format = intel_dp_output_format(connector,
2822                                                                    crtc_state->sink_format);
2823                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2824                                                    respect_downstream_limits);
2825         }
2826
2827         return ret;
2828 }
2829
2830 void
2831 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2832                               struct intel_crtc_state *pipe_config,
2833                               struct drm_connector_state *conn_state)
2834 {
2835         pipe_config->has_audio =
2836                 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2837                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2838
2839         pipe_config->sdp_split_enable = pipe_config->has_audio &&
2840                                         intel_dp_is_uhbr(pipe_config);
2841 }
2842
2843 int
2844 intel_dp_compute_config(struct intel_encoder *encoder,
2845                         struct intel_crtc_state *pipe_config,
2846                         struct drm_connector_state *conn_state)
2847 {
2848         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2849         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2850         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2851         const struct drm_display_mode *fixed_mode;
2852         struct intel_connector *connector = intel_dp->attached_connector;
2853         int ret = 0, link_bpp_x16;
2854
2855         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2856                 pipe_config->has_pch_encoder = true;
2857
2858         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2859         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2860                 ret = intel_panel_compute_config(connector, adjusted_mode);
2861                 if (ret)
2862                         return ret;
2863         }
2864
2865         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2866                 return -EINVAL;
2867
2868         if (!connector->base.interlace_allowed &&
2869             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2870                 return -EINVAL;
2871
2872         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2873                 return -EINVAL;
2874
2875         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2876                 return -EINVAL;
2877
2878         /*
2879          * Try to respect downstream TMDS clock limits first, if
2880          * that fails assume the user might know something we don't.
2881          */
2882         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2883         if (ret)
2884                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2885         if (ret)
2886                 return ret;
2887
2888         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2889             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2890                 ret = intel_panel_fitting(pipe_config, conn_state);
2891                 if (ret)
2892                         return ret;
2893         }
2894
2895         pipe_config->limited_color_range =
2896                 intel_dp_limited_color_range(pipe_config, conn_state);
2897
2898         pipe_config->enhanced_framing =
2899                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2900
2901         if (pipe_config->dsc.compression_enable)
2902                 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2903         else
2904                 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2905                                                               pipe_config->pipe_bpp));
2906
2907         if (intel_dp->mso_link_count) {
2908                 int n = intel_dp->mso_link_count;
2909                 int overlap = intel_dp->mso_pixel_overlap;
2910
2911                 pipe_config->splitter.enable = true;
2912                 pipe_config->splitter.link_count = n;
2913                 pipe_config->splitter.pixel_overlap = overlap;
2914
2915                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2916                             n, overlap);
2917
2918                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2919                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2920                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2921                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2922                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2923                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2924                 adjusted_mode->crtc_clock /= n;
2925         }
2926
2927         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2928
2929         intel_link_compute_m_n(link_bpp_x16,
2930                                pipe_config->lane_count,
2931                                adjusted_mode->crtc_clock,
2932                                pipe_config->port_clock,
2933                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2934                                &pipe_config->dp_m_n);
2935
2936         /* FIXME: abstract this better */
2937         if (pipe_config->splitter.enable)
2938                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2939
2940         if (!HAS_DDI(dev_priv))
2941                 g4x_dp_set_clock(encoder, pipe_config);
2942
2943         intel_vrr_compute_config(pipe_config, conn_state);
2944         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2945         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
2946         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2947         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2948
2949         return 0;
2950 }
2951
2952 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2953                               int link_rate, int lane_count)
2954 {
2955         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2956         intel_dp->link_trained = false;
2957         intel_dp->link_rate = link_rate;
2958         intel_dp->lane_count = lane_count;
2959 }
2960
2961 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2962 {
2963         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2964         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2965 }
2966
2967 /* Enable backlight PWM and backlight PP control. */
2968 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2969                             const struct drm_connector_state *conn_state)
2970 {
2971         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2972         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2973
2974         if (!intel_dp_is_edp(intel_dp))
2975                 return;
2976
2977         drm_dbg_kms(&i915->drm, "\n");
2978
2979         intel_backlight_enable(crtc_state, conn_state);
2980         intel_pps_backlight_on(intel_dp);
2981 }
2982
2983 /* Disable backlight PP control and backlight PWM. */
2984 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2985 {
2986         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2987         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2988
2989         if (!intel_dp_is_edp(intel_dp))
2990                 return;
2991
2992         drm_dbg_kms(&i915->drm, "\n");
2993
2994         intel_pps_backlight_off(intel_dp);
2995         intel_backlight_disable(old_conn_state);
2996 }
2997
2998 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2999 {
3000         /*
3001          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3002          * be capable of signalling downstream hpd with a long pulse.
3003          * Whether or not that means D3 is safe to use is not clear,
3004          * but let's assume so until proven otherwise.
3005          *
3006          * FIXME should really check all downstream ports...
3007          */
3008         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3009                 drm_dp_is_branch(intel_dp->dpcd) &&
3010                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3011 }
3012
3013 static int
3014 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3015 {
3016         int err;
3017         u8 val;
3018
3019         err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3020         if (err < 0)
3021                 return err;
3022
3023         if (set)
3024                 val |= flag;
3025         else
3026                 val &= ~flag;
3027
3028         return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3029 }
3030
3031 static void
3032 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3033                                     bool enable)
3034 {
3035         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3036
3037         if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3038                                          DP_DECOMPRESSION_EN, enable) < 0)
3039                 drm_dbg_kms(&i915->drm,
3040                             "Failed to %s sink decompression state\n",
3041                             str_enable_disable(enable));
3042 }
3043
3044 static void
3045 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3046                                   bool enable)
3047 {
3048         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3049         struct drm_dp_aux *aux = connector->port ?
3050                                  connector->port->passthrough_aux : NULL;
3051
3052         if (!aux)
3053                 return;
3054
3055         if (write_dsc_decompression_flag(aux,
3056                                          DP_DSC_PASSTHROUGH_EN, enable) < 0)
3057                 drm_dbg_kms(&i915->drm,
3058                             "Failed to %s sink compression passthrough state\n",
3059                             str_enable_disable(enable));
3060 }
3061
3062 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3063                                       const struct intel_connector *connector,
3064                                       bool for_get_ref)
3065 {
3066         struct drm_i915_private *i915 = to_i915(state->base.dev);
3067         struct drm_connector *_connector_iter;
3068         struct drm_connector_state *old_conn_state;
3069         struct drm_connector_state *new_conn_state;
3070         int ref_count = 0;
3071         int i;
3072
3073         /*
3074          * On SST the decompression AUX device won't be shared, each connector
3075          * uses for this its own AUX targeting the sink device.
3076          */
3077         if (!connector->mst_port)
3078                 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3079
3080         for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3081                                            old_conn_state, new_conn_state, i) {
3082                 const struct intel_connector *
3083                         connector_iter = to_intel_connector(_connector_iter);
3084
3085                 if (connector_iter->mst_port != connector->mst_port)
3086                         continue;
3087
3088                 if (!connector_iter->dp.dsc_decompression_enabled)
3089                         continue;
3090
3091                 drm_WARN_ON(&i915->drm,
3092                             (for_get_ref && !new_conn_state->crtc) ||
3093                             (!for_get_ref && !old_conn_state->crtc));
3094
3095                 if (connector_iter->dp.dsc_decompression_aux ==
3096                     connector->dp.dsc_decompression_aux)
3097                         ref_count++;
3098         }
3099
3100         return ref_count;
3101 }
3102
3103 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3104                                      struct intel_connector *connector)
3105 {
3106         bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3107
3108         connector->dp.dsc_decompression_enabled = true;
3109
3110         return ret;
3111 }
3112
3113 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3114                                      struct intel_connector *connector)
3115 {
3116         connector->dp.dsc_decompression_enabled = false;
3117
3118         return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3119 }
3120
3121 /**
3122  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3123  * @state: atomic state
3124  * @connector: connector to enable the decompression for
3125  * @new_crtc_state: new state for the CRTC driving @connector
3126  *
3127  * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3128  * register of the appropriate sink/branch device. On SST this is always the
3129  * sink device, whereas on MST based on each device's DSC capabilities it's
3130  * either the last branch device (enabling decompression in it) or both the
3131  * last branch device (enabling passthrough in it) and the sink device
3132  * (enabling decompression in it).
3133  */
3134 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3135                                         struct intel_connector *connector,
3136                                         const struct intel_crtc_state *new_crtc_state)
3137 {
3138         struct drm_i915_private *i915 = to_i915(state->base.dev);
3139
3140         if (!new_crtc_state->dsc.compression_enable)
3141                 return;
3142
3143         if (drm_WARN_ON(&i915->drm,
3144                         !connector->dp.dsc_decompression_aux ||
3145                         connector->dp.dsc_decompression_enabled))
3146                 return;
3147
3148         if (!intel_dp_dsc_aux_get_ref(state, connector))
3149                 return;
3150
3151         intel_dp_sink_set_dsc_passthrough(connector, true);
3152         intel_dp_sink_set_dsc_decompression(connector, true);
3153 }
3154
3155 /**
3156  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3157  * @state: atomic state
3158  * @connector: connector to disable the decompression for
3159  * @old_crtc_state: old state for the CRTC driving @connector
3160  *
3161  * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3162  * register of the appropriate sink/branch device, corresponding to the
3163  * sequence in intel_dp_sink_enable_decompression().
3164  */
3165 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3166                                          struct intel_connector *connector,
3167                                          const struct intel_crtc_state *old_crtc_state)
3168 {
3169         struct drm_i915_private *i915 = to_i915(state->base.dev);
3170
3171         if (!old_crtc_state->dsc.compression_enable)
3172                 return;
3173
3174         if (drm_WARN_ON(&i915->drm,
3175                         !connector->dp.dsc_decompression_aux ||
3176                         !connector->dp.dsc_decompression_enabled))
3177                 return;
3178
3179         if (!intel_dp_dsc_aux_put_ref(state, connector))
3180                 return;
3181
3182         intel_dp_sink_set_dsc_decompression(connector, false);
3183         intel_dp_sink_set_dsc_passthrough(connector, false);
3184 }
3185
3186 static void
3187 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3188 {
3189         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3190         u8 oui[] = { 0x00, 0xaa, 0x01 };
3191         u8 buf[3] = {};
3192
3193         /*
3194          * During driver init, we want to be careful and avoid changing the source OUI if it's
3195          * already set to what we want, so as to avoid clearing any state by accident
3196          */
3197         if (careful) {
3198                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3199                         drm_err(&i915->drm, "Failed to read source OUI\n");
3200
3201                 if (memcmp(oui, buf, sizeof(oui)) == 0)
3202                         return;
3203         }
3204
3205         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3206                 drm_err(&i915->drm, "Failed to write source OUI\n");
3207
3208         intel_dp->last_oui_write = jiffies;
3209 }
3210
3211 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3212 {
3213         struct intel_connector *connector = intel_dp->attached_connector;
3214         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3215
3216         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3217                     connector->base.base.id, connector->base.name,
3218                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3219
3220         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3221                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3222 }
3223
3224 /* If the device supports it, try to set the power state appropriately */
3225 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3226 {
3227         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3228         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3229         int ret, i;
3230
3231         /* Should have a valid DPCD by this point */
3232         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3233                 return;
3234
3235         if (mode != DP_SET_POWER_D0) {
3236                 if (downstream_hpd_needs_d0(intel_dp))
3237                         return;
3238
3239                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3240         } else {
3241                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3242
3243                 lspcon_resume(dp_to_dig_port(intel_dp));
3244
3245                 /* Write the source OUI as early as possible */
3246                 if (intel_dp_is_edp(intel_dp))
3247                         intel_edp_init_source_oui(intel_dp, false);
3248
3249                 /*
3250                  * When turning on, we need to retry for 1ms to give the sink
3251                  * time to wake up.
3252                  */
3253                 for (i = 0; i < 3; i++) {
3254                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3255                         if (ret == 1)
3256                                 break;
3257                         msleep(1);
3258                 }
3259
3260                 if (ret == 1 && lspcon->active)
3261                         lspcon_wait_pcon_mode(lspcon);
3262         }
3263
3264         if (ret != 1)
3265                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3266                             encoder->base.base.id, encoder->base.name,
3267                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3268 }
3269
3270 static bool
3271 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3272
3273 /**
3274  * intel_dp_sync_state - sync the encoder state during init/resume
3275  * @encoder: intel encoder to sync
3276  * @crtc_state: state for the CRTC connected to the encoder
3277  *
3278  * Sync any state stored in the encoder wrt. HW state during driver init
3279  * and system resume.
3280  */
3281 void intel_dp_sync_state(struct intel_encoder *encoder,
3282                          const struct intel_crtc_state *crtc_state)
3283 {
3284         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3285
3286         if (!crtc_state)
3287                 return;
3288
3289         /*
3290          * Don't clobber DPCD if it's been already read out during output
3291          * setup (eDP) or detect.
3292          */
3293         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3294                 intel_dp_get_dpcd(intel_dp);
3295
3296         intel_dp_reset_max_link_params(intel_dp);
3297 }
3298
3299 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3300                                     struct intel_crtc_state *crtc_state)
3301 {
3302         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3303         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3304         bool fastset = true;
3305
3306         /*
3307          * If BIOS has set an unsupported or non-standard link rate for some
3308          * reason force an encoder recompute and full modeset.
3309          */
3310         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3311                                 crtc_state->port_clock) < 0) {
3312                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3313                             encoder->base.base.id, encoder->base.name);
3314                 crtc_state->uapi.connectors_changed = true;
3315                 fastset = false;
3316         }
3317
3318         /*
3319          * FIXME hack to force full modeset when DSC is being used.
3320          *
3321          * As long as we do not have full state readout and config comparison
3322          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3323          * Remove once we have readout for DSC.
3324          */
3325         if (crtc_state->dsc.compression_enable) {
3326                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3327                             encoder->base.base.id, encoder->base.name);
3328                 crtc_state->uapi.mode_changed = true;
3329                 fastset = false;
3330         }
3331
3332         return fastset;
3333 }
3334
3335 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3336 {
3337         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3338
3339         /* Clear the cached register set to avoid using stale values */
3340
3341         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3342
3343         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3344                              intel_dp->pcon_dsc_dpcd,
3345                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3346                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3347                         DP_PCON_DSC_ENCODER);
3348
3349         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3350                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3351 }
3352
3353 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3354 {
3355         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3356         int i;
3357
3358         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3359                 if (frl_bw_mask & (1 << i))
3360                         return bw_gbps[i];
3361         }
3362         return 0;
3363 }
3364
3365 static int intel_dp_pcon_set_frl_mask(int max_frl)
3366 {
3367         switch (max_frl) {
3368         case 48:
3369                 return DP_PCON_FRL_BW_MASK_48GBPS;
3370         case 40:
3371                 return DP_PCON_FRL_BW_MASK_40GBPS;
3372         case 32:
3373                 return DP_PCON_FRL_BW_MASK_32GBPS;
3374         case 24:
3375                 return DP_PCON_FRL_BW_MASK_24GBPS;
3376         case 18:
3377                 return DP_PCON_FRL_BW_MASK_18GBPS;
3378         case 9:
3379                 return DP_PCON_FRL_BW_MASK_9GBPS;
3380         }
3381
3382         return 0;
3383 }
3384
3385 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3386 {
3387         struct intel_connector *intel_connector = intel_dp->attached_connector;
3388         struct drm_connector *connector = &intel_connector->base;
3389         int max_frl_rate;
3390         int max_lanes, rate_per_lane;
3391         int max_dsc_lanes, dsc_rate_per_lane;
3392
3393         max_lanes = connector->display_info.hdmi.max_lanes;
3394         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3395         max_frl_rate = max_lanes * rate_per_lane;
3396
3397         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3398                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3399                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3400                 if (max_dsc_lanes && dsc_rate_per_lane)
3401                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3402         }
3403
3404         return max_frl_rate;
3405 }
3406
3407 static bool
3408 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3409                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3410 {
3411         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3412             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3413             *frl_trained_mask >= max_frl_bw_mask)
3414                 return true;
3415
3416         return false;
3417 }
3418
3419 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3420 {
3421 #define TIMEOUT_FRL_READY_MS 500
3422 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3423
3424         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3425         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3426         u8 max_frl_bw_mask = 0, frl_trained_mask;
3427         bool is_active;
3428
3429         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3430         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3431
3432         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3433         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3434
3435         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3436
3437         if (max_frl_bw <= 0)
3438                 return -EINVAL;
3439
3440         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3441         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3442
3443         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3444                 goto frl_trained;
3445
3446         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3447         if (ret < 0)
3448                 return ret;
3449         /* Wait for PCON to be FRL Ready */
3450         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3451
3452         if (!is_active)
3453                 return -ETIMEDOUT;
3454
3455         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3456                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3457         if (ret < 0)
3458                 return ret;
3459         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3460                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3461         if (ret < 0)
3462                 return ret;
3463         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3464         if (ret < 0)
3465                 return ret;
3466         /*
3467          * Wait for FRL to be completed
3468          * Check if the HDMI Link is up and active.
3469          */
3470         wait_for(is_active =
3471                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3472                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3473
3474         if (!is_active)
3475                 return -ETIMEDOUT;
3476
3477 frl_trained:
3478         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3479         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3480         intel_dp->frl.is_trained = true;
3481         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3482
3483         return 0;
3484 }
3485
3486 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3487 {
3488         if (drm_dp_is_branch(intel_dp->dpcd) &&
3489             intel_dp_has_hdmi_sink(intel_dp) &&
3490             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3491                 return true;
3492
3493         return false;
3494 }
3495
3496 static
3497 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3498 {
3499         int ret;
3500         u8 buf = 0;
3501
3502         /* Set PCON source control mode */
3503         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3504
3505         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3506         if (ret < 0)
3507                 return ret;
3508
3509         /* Set HDMI LINK ENABLE */
3510         buf |= DP_PCON_ENABLE_HDMI_LINK;
3511         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3512         if (ret < 0)
3513                 return ret;
3514
3515         return 0;
3516 }
3517
3518 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3519 {
3520         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3521
3522         /*
3523          * Always go for FRL training if:
3524          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3525          * -sink is HDMI2.1
3526          */
3527         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3528             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3529             intel_dp->frl.is_trained)
3530                 return;
3531
3532         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3533                 int ret, mode;
3534
3535                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3536                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3537                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3538
3539                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3540                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3541         } else {
3542                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3543         }
3544 }
3545
3546 static int
3547 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3548 {
3549         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3550
3551         return intel_hdmi_dsc_get_slice_height(vactive);
3552 }
3553
3554 static int
3555 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3556                              const struct intel_crtc_state *crtc_state)
3557 {
3558         struct intel_connector *intel_connector = intel_dp->attached_connector;
3559         struct drm_connector *connector = &intel_connector->base;
3560         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3561         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3562         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3563         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3564
3565         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3566                                              pcon_max_slice_width,
3567                                              hdmi_max_slices, hdmi_throughput);
3568 }
3569
3570 static int
3571 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3572                           const struct intel_crtc_state *crtc_state,
3573                           int num_slices, int slice_width)
3574 {
3575         struct intel_connector *intel_connector = intel_dp->attached_connector;
3576         struct drm_connector *connector = &intel_connector->base;
3577         int output_format = crtc_state->output_format;
3578         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3579         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3580         int hdmi_max_chunk_bytes =
3581                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3582
3583         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3584                                       num_slices, output_format, hdmi_all_bpp,
3585                                       hdmi_max_chunk_bytes);
3586 }
3587
3588 void
3589 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3590                             const struct intel_crtc_state *crtc_state)
3591 {
3592         u8 pps_param[6];
3593         int slice_height;
3594         int slice_width;
3595         int num_slices;
3596         int bits_per_pixel;
3597         int ret;
3598         struct intel_connector *intel_connector = intel_dp->attached_connector;
3599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3600         struct drm_connector *connector;
3601         bool hdmi_is_dsc_1_2;
3602
3603         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3604                 return;
3605
3606         if (!intel_connector)
3607                 return;
3608         connector = &intel_connector->base;
3609         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3610
3611         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3612             !hdmi_is_dsc_1_2)
3613                 return;
3614
3615         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3616         if (!slice_height)
3617                 return;
3618
3619         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3620         if (!num_slices)
3621                 return;
3622
3623         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3624                                    num_slices);
3625
3626         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3627                                                    num_slices, slice_width);
3628         if (!bits_per_pixel)
3629                 return;
3630
3631         pps_param[0] = slice_height & 0xFF;
3632         pps_param[1] = slice_height >> 8;
3633         pps_param[2] = slice_width & 0xFF;
3634         pps_param[3] = slice_width >> 8;
3635         pps_param[4] = bits_per_pixel & 0xFF;
3636         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3637
3638         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3639         if (ret < 0)
3640                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3641 }
3642
3643 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3644                                            const struct intel_crtc_state *crtc_state)
3645 {
3646         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3647         bool ycbcr444_to_420 = false;
3648         bool rgb_to_ycbcr = false;
3649         u8 tmp;
3650
3651         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3652                 return;
3653
3654         if (!drm_dp_is_branch(intel_dp->dpcd))
3655                 return;
3656
3657         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3658
3659         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3660                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3661                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3662                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3663
3664         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3665                 switch (crtc_state->output_format) {
3666                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3667                         break;
3668                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3669                         ycbcr444_to_420 = true;
3670                         break;
3671                 case INTEL_OUTPUT_FORMAT_RGB:
3672                         rgb_to_ycbcr = true;
3673                         ycbcr444_to_420 = true;
3674                         break;
3675                 default:
3676                         MISSING_CASE(crtc_state->output_format);
3677                         break;
3678                 }
3679         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3680                 switch (crtc_state->output_format) {
3681                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3682                         break;
3683                 case INTEL_OUTPUT_FORMAT_RGB:
3684                         rgb_to_ycbcr = true;
3685                         break;
3686                 default:
3687                         MISSING_CASE(crtc_state->output_format);
3688                         break;
3689                 }
3690         }
3691
3692         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3693
3694         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3695                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3696                 drm_dbg_kms(&i915->drm,
3697                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3698                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3699
3700         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3701
3702         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3703                 drm_dbg_kms(&i915->drm,
3704                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3705                             str_enable_disable(tmp));
3706 }
3707
3708 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3709 {
3710         u8 dprx = 0;
3711
3712         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3713                               &dprx) != 1)
3714                 return false;
3715         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3716 }
3717
3718 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3719                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3720 {
3721         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3722                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3723                 drm_err(aux->drm_dev,
3724                         "Failed to read DPCD register 0x%x\n",
3725                         DP_DSC_SUPPORT);
3726                 return;
3727         }
3728
3729         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3730                     DP_DSC_RECEIVER_CAP_SIZE,
3731                     dsc_dpcd);
3732 }
3733
3734 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3735 {
3736         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3737
3738         /*
3739          * Clear the cached register set to avoid using stale values
3740          * for the sinks that do not support DSC.
3741          */
3742         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3743
3744         /* Clear fec_capable to avoid using stale values */
3745         connector->dp.fec_capability = 0;
3746
3747         if (dpcd_rev < DP_DPCD_REV_14)
3748                 return;
3749
3750         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3751                                connector->dp.dsc_dpcd);
3752
3753         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3754                               &connector->dp.fec_capability) < 0) {
3755                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3756                 return;
3757         }
3758
3759         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3760                     connector->dp.fec_capability);
3761 }
3762
3763 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3764 {
3765         if (edp_dpcd_rev < DP_EDP_14)
3766                 return;
3767
3768         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3769 }
3770
3771 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3772                                      struct drm_display_mode *mode)
3773 {
3774         struct intel_dp *intel_dp = intel_attached_dp(connector);
3775         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3776         int n = intel_dp->mso_link_count;
3777         int overlap = intel_dp->mso_pixel_overlap;
3778
3779         if (!mode || !n)
3780                 return;
3781
3782         mode->hdisplay = (mode->hdisplay - overlap) * n;
3783         mode->hsync_start = (mode->hsync_start - overlap) * n;
3784         mode->hsync_end = (mode->hsync_end - overlap) * n;
3785         mode->htotal = (mode->htotal - overlap) * n;
3786         mode->clock *= n;
3787
3788         drm_mode_set_name(mode);
3789
3790         drm_dbg_kms(&i915->drm,
3791                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3792                     connector->base.base.id, connector->base.name,
3793                     DRM_MODE_ARG(mode));
3794 }
3795
3796 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3797 {
3798         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3799         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3800         struct intel_connector *connector = intel_dp->attached_connector;
3801
3802         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3803                 /*
3804                  * This is a big fat ugly hack.
3805                  *
3806                  * Some machines in UEFI boot mode provide us a VBT that has 18
3807                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3808                  * unknown we fail to light up. Yet the same BIOS boots up with
3809                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3810                  * max, not what it tells us to use.
3811                  *
3812                  * Note: This will still be broken if the eDP panel is not lit
3813                  * up by the BIOS, and thus we can't get the mode at module
3814                  * load.
3815                  */
3816                 drm_dbg_kms(&dev_priv->drm,
3817                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3818                             pipe_bpp, connector->panel.vbt.edp.bpp);
3819                 connector->panel.vbt.edp.bpp = pipe_bpp;
3820         }
3821 }
3822
3823 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3824 {
3825         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3826         struct intel_connector *connector = intel_dp->attached_connector;
3827         struct drm_display_info *info = &connector->base.display_info;
3828         u8 mso;
3829
3830         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3831                 return;
3832
3833         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3834                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3835                 return;
3836         }
3837
3838         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3839         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3840         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3841                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3842                 mso = 0;
3843         }
3844
3845         if (mso) {
3846                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3847                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3848                             info->mso_pixel_overlap);
3849                 if (!HAS_MSO(i915)) {
3850                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3851                         mso = 0;
3852                 }
3853         }
3854
3855         intel_dp->mso_link_count = mso;
3856         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3857 }
3858
3859 static bool
3860 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3861 {
3862         struct drm_i915_private *dev_priv =
3863                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3864
3865         /* this function is meant to be called only once */
3866         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3867
3868         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3869                 return false;
3870
3871         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3872                          drm_dp_is_branch(intel_dp->dpcd));
3873
3874         /*
3875          * Read the eDP display control registers.
3876          *
3877          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3878          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3879          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3880          * method). The display control registers should read zero if they're
3881          * not supported anyway.
3882          */
3883         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3884                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3885                              sizeof(intel_dp->edp_dpcd)) {
3886                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3887                             (int)sizeof(intel_dp->edp_dpcd),
3888                             intel_dp->edp_dpcd);
3889
3890                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3891         }
3892
3893         /*
3894          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3895          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3896          */
3897         intel_psr_init_dpcd(intel_dp);
3898
3899         /* Clear the default sink rates */
3900         intel_dp->num_sink_rates = 0;
3901
3902         /* Read the eDP 1.4+ supported link rates. */
3903         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3904                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3905                 int i;
3906
3907                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3908                                 sink_rates, sizeof(sink_rates));
3909
3910                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3911                         int val = le16_to_cpu(sink_rates[i]);
3912
3913                         if (val == 0)
3914                                 break;
3915
3916                         /* Value read multiplied by 200kHz gives the per-lane
3917                          * link rate in kHz. The source rates are, however,
3918                          * stored in terms of LS_Clk kHz. The full conversion
3919                          * back to symbols is
3920                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3921                          */
3922                         intel_dp->sink_rates[i] = (val * 200) / 10;
3923                 }
3924                 intel_dp->num_sink_rates = i;
3925         }
3926
3927         /*
3928          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3929          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3930          */
3931         if (intel_dp->num_sink_rates)
3932                 intel_dp->use_rate_select = true;
3933         else
3934                 intel_dp_set_sink_rates(intel_dp);
3935         intel_dp_set_max_sink_lane_count(intel_dp);
3936
3937         /* Read the eDP DSC DPCD registers */
3938         if (HAS_DSC(dev_priv))
3939                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3940                                            connector);
3941
3942         /*
3943          * If needed, program our source OUI so we can make various Intel-specific AUX services
3944          * available (such as HDR backlight controls)
3945          */
3946         intel_edp_init_source_oui(intel_dp, true);
3947
3948         return true;
3949 }
3950
3951 static bool
3952 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3953 {
3954         if (!intel_dp->attached_connector)
3955                 return false;
3956
3957         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3958                                           intel_dp->dpcd,
3959                                           &intel_dp->desc);
3960 }
3961
3962 static bool
3963 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3964 {
3965         int ret;
3966
3967         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3968                 return false;
3969
3970         /*
3971          * Don't clobber cached eDP rates. Also skip re-reading
3972          * the OUI/ID since we know it won't change.
3973          */
3974         if (!intel_dp_is_edp(intel_dp)) {
3975                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3976                                  drm_dp_is_branch(intel_dp->dpcd));
3977
3978                 intel_dp_set_sink_rates(intel_dp);
3979                 intel_dp_set_max_sink_lane_count(intel_dp);
3980                 intel_dp_set_common_rates(intel_dp);
3981         }
3982
3983         if (intel_dp_has_sink_count(intel_dp)) {
3984                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3985                 if (ret < 0)
3986                         return false;
3987
3988                 /*
3989                  * Sink count can change between short pulse hpd hence
3990                  * a member variable in intel_dp will track any changes
3991                  * between short pulse interrupts.
3992                  */
3993                 intel_dp->sink_count = ret;
3994
3995                 /*
3996                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3997                  * a dongle is present but no display. Unless we require to know
3998                  * if a dongle is present or not, we don't need to update
3999                  * downstream port information. So, an early return here saves
4000                  * time from performing other operations which are not required.
4001                  */
4002                 if (!intel_dp->sink_count)
4003                         return false;
4004         }
4005
4006         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4007                                            intel_dp->downstream_ports) == 0;
4008 }
4009
4010 static bool
4011 intel_dp_can_mst(struct intel_dp *intel_dp)
4012 {
4013         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4014
4015         return i915->display.params.enable_dp_mst &&
4016                 intel_dp_mst_source_support(intel_dp) &&
4017                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4018 }
4019
4020 static void
4021 intel_dp_configure_mst(struct intel_dp *intel_dp)
4022 {
4023         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4024         struct intel_encoder *encoder =
4025                 &dp_to_dig_port(intel_dp)->base;
4026         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4027
4028         drm_dbg_kms(&i915->drm,
4029                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4030                     encoder->base.base.id, encoder->base.name,
4031                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
4032                     str_yes_no(sink_can_mst),
4033                     str_yes_no(i915->display.params.enable_dp_mst));
4034
4035         if (!intel_dp_mst_source_support(intel_dp))
4036                 return;
4037
4038         intel_dp->is_mst = sink_can_mst &&
4039                 i915->display.params.enable_dp_mst;
4040
4041         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4042                                         intel_dp->is_mst);
4043 }
4044
4045 static bool
4046 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4047 {
4048         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4049 }
4050
4051 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4052 {
4053         int retry;
4054
4055         for (retry = 0; retry < 3; retry++) {
4056                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4057                                       &esi[1], 3) == 3)
4058                         return true;
4059         }
4060
4061         return false;
4062 }
4063
4064 bool
4065 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4066                        const struct drm_connector_state *conn_state)
4067 {
4068         /*
4069          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4070          * of Color Encoding Format and Content Color Gamut], in order to
4071          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4072          */
4073         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4074                 return true;
4075
4076         switch (conn_state->colorspace) {
4077         case DRM_MODE_COLORIMETRY_SYCC_601:
4078         case DRM_MODE_COLORIMETRY_OPYCC_601:
4079         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4080         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4081         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4082                 return true;
4083         default:
4084                 break;
4085         }
4086
4087         return false;
4088 }
4089
4090 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4091                                      struct dp_sdp *sdp, size_t size)
4092 {
4093         size_t length = sizeof(struct dp_sdp);
4094
4095         if (size < length)
4096                 return -ENOSPC;
4097
4098         memset(sdp, 0, size);
4099
4100         /*
4101          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4102          * VSC SDP Header Bytes
4103          */
4104         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4105         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4106         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4107         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4108
4109         if (vsc->revision == 0x6) {
4110                 sdp->db[0] = 1;
4111                 sdp->db[3] = 1;
4112         }
4113
4114         /*
4115          * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
4116          * Format as per DP 1.4a spec and DP 2.0 respectively.
4117          */
4118         if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
4119                 goto out;
4120
4121         /* VSC SDP Payload for DB16 through DB18 */
4122         /* Pixel Encoding and Colorimetry Formats  */
4123         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4124         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4125
4126         switch (vsc->bpc) {
4127         case 6:
4128                 /* 6bpc: 0x0 */
4129                 break;
4130         case 8:
4131                 sdp->db[17] = 0x1; /* DB17[3:0] */
4132                 break;
4133         case 10:
4134                 sdp->db[17] = 0x2;
4135                 break;
4136         case 12:
4137                 sdp->db[17] = 0x3;
4138                 break;
4139         case 16:
4140                 sdp->db[17] = 0x4;
4141                 break;
4142         default:
4143                 MISSING_CASE(vsc->bpc);
4144                 break;
4145         }
4146         /* Dynamic Range and Component Bit Depth */
4147         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4148                 sdp->db[17] |= 0x80;  /* DB17[7] */
4149
4150         /* Content Type */
4151         sdp->db[18] = vsc->content_type & 0x7;
4152
4153 out:
4154         return length;
4155 }
4156
4157 static ssize_t
4158 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4159                                          const struct hdmi_drm_infoframe *drm_infoframe,
4160                                          struct dp_sdp *sdp,
4161                                          size_t size)
4162 {
4163         size_t length = sizeof(struct dp_sdp);
4164         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4165         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4166         ssize_t len;
4167
4168         if (size < length)
4169                 return -ENOSPC;
4170
4171         memset(sdp, 0, size);
4172
4173         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4174         if (len < 0) {
4175                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4176                 return -ENOSPC;
4177         }
4178
4179         if (len != infoframe_size) {
4180                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4181                 return -ENOSPC;
4182         }
4183
4184         /*
4185          * Set up the infoframe sdp packet for HDR static metadata.
4186          * Prepare VSC Header for SU as per DP 1.4a spec,
4187          * Table 2-100 and Table 2-101
4188          */
4189
4190         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4191         sdp->sdp_header.HB0 = 0;
4192         /*
4193          * Packet Type 80h + Non-audio INFOFRAME Type value
4194          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4195          * - 80h + Non-audio INFOFRAME Type value
4196          * - InfoFrame Type: 0x07
4197          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4198          */
4199         sdp->sdp_header.HB1 = drm_infoframe->type;
4200         /*
4201          * Least Significant Eight Bits of (Data Byte Count – 1)
4202          * infoframe_size - 1
4203          */
4204         sdp->sdp_header.HB2 = 0x1D;
4205         /* INFOFRAME SDP Version Number */
4206         sdp->sdp_header.HB3 = (0x13 << 2);
4207         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4208         sdp->db[0] = drm_infoframe->version;
4209         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4210         sdp->db[1] = drm_infoframe->length;
4211         /*
4212          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4213          * HDMI_INFOFRAME_HEADER_SIZE
4214          */
4215         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4216         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4217                HDMI_DRM_INFOFRAME_SIZE);
4218
4219         /*
4220          * Size of DP infoframe sdp packet for HDR static metadata consists of
4221          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4222          * - Two Data Blocks: 2 bytes
4223          *    CTA Header Byte2 (INFOFRAME Version Number)
4224          *    CTA Header Byte3 (Length of INFOFRAME)
4225          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4226          *
4227          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4228          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4229          * will pad rest of the size.
4230          */
4231         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4232 }
4233
4234 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4235                                const struct intel_crtc_state *crtc_state,
4236                                unsigned int type)
4237 {
4238         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4239         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4240         struct dp_sdp sdp = {};
4241         ssize_t len;
4242
4243         if ((crtc_state->infoframes.enable &
4244              intel_hdmi_infoframe_enable(type)) == 0)
4245                 return;
4246
4247         switch (type) {
4248         case DP_SDP_VSC:
4249                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4250                                             sizeof(sdp));
4251                 break;
4252         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4253                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4254                                                                &crtc_state->infoframes.drm.drm,
4255                                                                &sdp, sizeof(sdp));
4256                 break;
4257         default:
4258                 MISSING_CASE(type);
4259                 return;
4260         }
4261
4262         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4263                 return;
4264
4265         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4266 }
4267
4268 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4269                              bool enable,
4270                              const struct intel_crtc_state *crtc_state,
4271                              const struct drm_connector_state *conn_state)
4272 {
4273         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4274         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4275         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4276                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4277                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4278         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4279
4280         /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4281         if (!enable && HAS_DSC(dev_priv))
4282                 val &= ~VDIP_ENABLE_PPS;
4283
4284         /* When PSR is enabled, this routine doesn't disable VSC DIP */
4285         if (!crtc_state->has_psr)
4286                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4287
4288         intel_de_write(dev_priv, reg, val);
4289         intel_de_posting_read(dev_priv, reg);
4290
4291         if (!enable)
4292                 return;
4293
4294         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4295
4296         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4297 }
4298
4299 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4300                                    const void *buffer, size_t size)
4301 {
4302         const struct dp_sdp *sdp = buffer;
4303
4304         if (size < sizeof(struct dp_sdp))
4305                 return -EINVAL;
4306
4307         memset(vsc, 0, sizeof(*vsc));
4308
4309         if (sdp->sdp_header.HB0 != 0)
4310                 return -EINVAL;
4311
4312         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4313                 return -EINVAL;
4314
4315         vsc->sdp_type = sdp->sdp_header.HB1;
4316         vsc->revision = sdp->sdp_header.HB2;
4317         vsc->length = sdp->sdp_header.HB3;
4318
4319         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4320             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4321                 /*
4322                  * - HB2 = 0x2, HB3 = 0x8
4323                  *   VSC SDP supporting 3D stereo + PSR
4324                  * - HB2 = 0x4, HB3 = 0xe
4325                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4326                  *   first scan line of the SU region (applies to eDP v1.4b
4327                  *   and higher).
4328                  */
4329                 return 0;
4330         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4331                 /*
4332                  * - HB2 = 0x5, HB3 = 0x13
4333                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4334                  *   Format.
4335                  */
4336                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4337                 vsc->colorimetry = sdp->db[16] & 0xf;
4338                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4339
4340                 switch (sdp->db[17] & 0x7) {
4341                 case 0x0:
4342                         vsc->bpc = 6;
4343                         break;
4344                 case 0x1:
4345                         vsc->bpc = 8;
4346                         break;
4347                 case 0x2:
4348                         vsc->bpc = 10;
4349                         break;
4350                 case 0x3:
4351                         vsc->bpc = 12;
4352                         break;
4353                 case 0x4:
4354                         vsc->bpc = 16;
4355                         break;
4356                 default:
4357                         MISSING_CASE(sdp->db[17] & 0x7);
4358                         return -EINVAL;
4359                 }
4360
4361                 vsc->content_type = sdp->db[18] & 0x7;
4362         } else {
4363                 return -EINVAL;
4364         }
4365
4366         return 0;
4367 }
4368
4369 static int
4370 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4371                                            const void *buffer, size_t size)
4372 {
4373         int ret;
4374
4375         const struct dp_sdp *sdp = buffer;
4376
4377         if (size < sizeof(struct dp_sdp))
4378                 return -EINVAL;
4379
4380         if (sdp->sdp_header.HB0 != 0)
4381                 return -EINVAL;
4382
4383         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4384                 return -EINVAL;
4385
4386         /*
4387          * Least Significant Eight Bits of (Data Byte Count – 1)
4388          * 1Dh (i.e., Data Byte Count = 30 bytes).
4389          */
4390         if (sdp->sdp_header.HB2 != 0x1D)
4391                 return -EINVAL;
4392
4393         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4394         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4395                 return -EINVAL;
4396
4397         /* INFOFRAME SDP Version Number */
4398         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4399                 return -EINVAL;
4400
4401         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4402         if (sdp->db[0] != 1)
4403                 return -EINVAL;
4404
4405         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4406         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4407                 return -EINVAL;
4408
4409         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4410                                              HDMI_DRM_INFOFRAME_SIZE);
4411
4412         return ret;
4413 }
4414
4415 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4416                                   struct intel_crtc_state *crtc_state,
4417                                   struct drm_dp_vsc_sdp *vsc)
4418 {
4419         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4420         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4421         unsigned int type = DP_SDP_VSC;
4422         struct dp_sdp sdp = {};
4423         int ret;
4424
4425         if ((crtc_state->infoframes.enable &
4426              intel_hdmi_infoframe_enable(type)) == 0)
4427                 return;
4428
4429         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4430
4431         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4432
4433         if (ret)
4434                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4435 }
4436
4437 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4438                                                      struct intel_crtc_state *crtc_state,
4439                                                      struct hdmi_drm_infoframe *drm_infoframe)
4440 {
4441         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4442         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4443         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4444         struct dp_sdp sdp = {};
4445         int ret;
4446
4447         if ((crtc_state->infoframes.enable &
4448             intel_hdmi_infoframe_enable(type)) == 0)
4449                 return;
4450
4451         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4452                                  sizeof(sdp));
4453
4454         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4455                                                          sizeof(sdp));
4456
4457         if (ret)
4458                 drm_dbg_kms(&dev_priv->drm,
4459                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4460 }
4461
4462 void intel_read_dp_sdp(struct intel_encoder *encoder,
4463                        struct intel_crtc_state *crtc_state,
4464                        unsigned int type)
4465 {
4466         switch (type) {
4467         case DP_SDP_VSC:
4468                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4469                                       &crtc_state->infoframes.vsc);
4470                 break;
4471         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4472                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4473                                                          &crtc_state->infoframes.drm.drm);
4474                 break;
4475         default:
4476                 MISSING_CASE(type);
4477                 break;
4478         }
4479 }
4480
4481 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4482 {
4483         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4484         int status = 0;
4485         int test_link_rate;
4486         u8 test_lane_count, test_link_bw;
4487         /* (DP CTS 1.2)
4488          * 4.3.1.11
4489          */
4490         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4491         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4492                                    &test_lane_count);
4493
4494         if (status <= 0) {
4495                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4496                 return DP_TEST_NAK;
4497         }
4498         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4499
4500         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4501                                    &test_link_bw);
4502         if (status <= 0) {
4503                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4504                 return DP_TEST_NAK;
4505         }
4506         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4507
4508         /* Validate the requested link rate and lane count */
4509         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4510                                         test_lane_count))
4511                 return DP_TEST_NAK;
4512
4513         intel_dp->compliance.test_lane_count = test_lane_count;
4514         intel_dp->compliance.test_link_rate = test_link_rate;
4515
4516         return DP_TEST_ACK;
4517 }
4518
4519 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4520 {
4521         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4522         u8 test_pattern;
4523         u8 test_misc;
4524         __be16 h_width, v_height;
4525         int status = 0;
4526
4527         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4528         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4529                                    &test_pattern);
4530         if (status <= 0) {
4531                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4532                 return DP_TEST_NAK;
4533         }
4534         if (test_pattern != DP_COLOR_RAMP)
4535                 return DP_TEST_NAK;
4536
4537         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4538                                   &h_width, 2);
4539         if (status <= 0) {
4540                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4541                 return DP_TEST_NAK;
4542         }
4543
4544         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4545                                   &v_height, 2);
4546         if (status <= 0) {
4547                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4548                 return DP_TEST_NAK;
4549         }
4550
4551         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4552                                    &test_misc);
4553         if (status <= 0) {
4554                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4555                 return DP_TEST_NAK;
4556         }
4557         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4558                 return DP_TEST_NAK;
4559         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4560                 return DP_TEST_NAK;
4561         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4562         case DP_TEST_BIT_DEPTH_6:
4563                 intel_dp->compliance.test_data.bpc = 6;
4564                 break;
4565         case DP_TEST_BIT_DEPTH_8:
4566                 intel_dp->compliance.test_data.bpc = 8;
4567                 break;
4568         default:
4569                 return DP_TEST_NAK;
4570         }
4571
4572         intel_dp->compliance.test_data.video_pattern = test_pattern;
4573         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4574         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4575         /* Set test active flag here so userspace doesn't interrupt things */
4576         intel_dp->compliance.test_active = true;
4577
4578         return DP_TEST_ACK;
4579 }
4580
4581 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4582 {
4583         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4584         u8 test_result = DP_TEST_ACK;
4585         struct intel_connector *intel_connector = intel_dp->attached_connector;
4586         struct drm_connector *connector = &intel_connector->base;
4587
4588         if (intel_connector->detect_edid == NULL ||
4589             connector->edid_corrupt ||
4590             intel_dp->aux.i2c_defer_count > 6) {
4591                 /* Check EDID read for NACKs, DEFERs and corruption
4592                  * (DP CTS 1.2 Core r1.1)
4593                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4594                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4595                  *    4.2.2.6 : EDID corruption detected
4596                  * Use failsafe mode for all cases
4597                  */
4598                 if (intel_dp->aux.i2c_nack_count > 0 ||
4599                         intel_dp->aux.i2c_defer_count > 0)
4600                         drm_dbg_kms(&i915->drm,
4601                                     "EDID read had %d NACKs, %d DEFERs\n",
4602                                     intel_dp->aux.i2c_nack_count,
4603                                     intel_dp->aux.i2c_defer_count);
4604                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4605         } else {
4606                 /* FIXME: Get rid of drm_edid_raw() */
4607                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4608
4609                 /* We have to write the checksum of the last block read */
4610                 block += block->extensions;
4611
4612                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4613                                        block->checksum) <= 0)
4614                         drm_dbg_kms(&i915->drm,
4615                                     "Failed to write EDID checksum\n");
4616
4617                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4618                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4619         }
4620
4621         /* Set test active flag here so userspace doesn't interrupt things */
4622         intel_dp->compliance.test_active = true;
4623
4624         return test_result;
4625 }
4626
4627 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4628                                         const struct intel_crtc_state *crtc_state)
4629 {
4630         struct drm_i915_private *dev_priv =
4631                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4632         struct drm_dp_phy_test_params *data =
4633                         &intel_dp->compliance.test_data.phytest;
4634         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4635         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4636         enum pipe pipe = crtc->pipe;
4637         u32 pattern_val;
4638
4639         switch (data->phy_pattern) {
4640         case DP_LINK_QUAL_PATTERN_DISABLE:
4641                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4642                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4643                 if (DISPLAY_VER(dev_priv) >= 10)
4644                         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4645                                      DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4646                                      DP_TP_CTL_LINK_TRAIN_NORMAL);
4647                 break;
4648         case DP_LINK_QUAL_PATTERN_D10_2:
4649                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4650                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4651                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4652                 break;
4653         case DP_LINK_QUAL_PATTERN_ERROR_RATE:
4654                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4655                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4656                                DDI_DP_COMP_CTL_ENABLE |
4657                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4658                 break;
4659         case DP_LINK_QUAL_PATTERN_PRBS7:
4660                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4661                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4662                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4663                 break;
4664         case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:
4665                 /*
4666                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4667                  * current firmware of DPR-100 could not set it, so hardcoding
4668                  * now for complaince test.
4669                  */
4670                 drm_dbg_kms(&dev_priv->drm,
4671                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4672                 pattern_val = 0x3e0f83e0;
4673                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4674                 pattern_val = 0x0f83e0f8;
4675                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4676                 pattern_val = 0x0000f83e;
4677                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4678                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4679                                DDI_DP_COMP_CTL_ENABLE |
4680                                DDI_DP_COMP_CTL_CUSTOM80);
4681                 break;
4682         case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:
4683                 /*
4684                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4685                  * current firmware of DPR-100 could not set it, so hardcoding
4686                  * now for complaince test.
4687                  */
4688                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4689                 pattern_val = 0xFB;
4690                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4691                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4692                                pattern_val);
4693                 break;
4694         case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:
4695                 if (DISPLAY_VER(dev_priv) < 10)  {
4696                         drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");
4697                         break;
4698                 }
4699                 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");
4700                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4701                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4702                              DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4703                              DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);
4704                 break;
4705         default:
4706                 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");
4707         }
4708 }
4709
4710 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4711                                          const struct intel_crtc_state *crtc_state)
4712 {
4713         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4714         struct drm_dp_phy_test_params *data =
4715                 &intel_dp->compliance.test_data.phytest;
4716         u8 link_status[DP_LINK_STATUS_SIZE];
4717
4718         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4719                                              link_status) < 0) {
4720                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4721                 return;
4722         }
4723
4724         /* retrieve vswing & pre-emphasis setting */
4725         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4726                                   link_status);
4727
4728         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4729
4730         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4731
4732         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4733                           intel_dp->train_set, crtc_state->lane_count);
4734
4735         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4736                                     intel_dp->dpcd[DP_DPCD_REV]);
4737 }
4738
4739 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4740 {
4741         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4742         struct drm_dp_phy_test_params *data =
4743                 &intel_dp->compliance.test_data.phytest;
4744
4745         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4746                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4747                 return DP_TEST_NAK;
4748         }
4749
4750         /* Set test active flag here so userspace doesn't interrupt things */
4751         intel_dp->compliance.test_active = true;
4752
4753         return DP_TEST_ACK;
4754 }
4755
4756 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4757 {
4758         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4759         u8 response = DP_TEST_NAK;
4760         u8 request = 0;
4761         int status;
4762
4763         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4764         if (status <= 0) {
4765                 drm_dbg_kms(&i915->drm,
4766                             "Could not read test request from sink\n");
4767                 goto update_status;
4768         }
4769
4770         switch (request) {
4771         case DP_TEST_LINK_TRAINING:
4772                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4773                 response = intel_dp_autotest_link_training(intel_dp);
4774                 break;
4775         case DP_TEST_LINK_VIDEO_PATTERN:
4776                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4777                 response = intel_dp_autotest_video_pattern(intel_dp);
4778                 break;
4779         case DP_TEST_LINK_EDID_READ:
4780                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4781                 response = intel_dp_autotest_edid(intel_dp);
4782                 break;
4783         case DP_TEST_LINK_PHY_TEST_PATTERN:
4784                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4785                 response = intel_dp_autotest_phy_pattern(intel_dp);
4786                 break;
4787         default:
4788                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4789                             request);
4790                 break;
4791         }
4792
4793         if (response & DP_TEST_ACK)
4794                 intel_dp->compliance.test_type = request;
4795
4796 update_status:
4797         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4798         if (status <= 0)
4799                 drm_dbg_kms(&i915->drm,
4800                             "Could not write test response to sink\n");
4801 }
4802
4803 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4804                              u8 link_status[DP_LINK_STATUS_SIZE])
4805 {
4806         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4807         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4808         bool uhbr = intel_dp->link_rate >= 1000000;
4809         bool ok;
4810
4811         if (uhbr)
4812                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4813                                                           intel_dp->lane_count);
4814         else
4815                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4816
4817         if (ok)
4818                 return true;
4819
4820         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4821         drm_dbg_kms(&i915->drm,
4822                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4823                     encoder->base.base.id, encoder->base.name,
4824                     uhbr ? "128b/132b" : "8b/10b");
4825
4826         return false;
4827 }
4828
4829 static void
4830 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4831 {
4832         bool handled = false;
4833
4834         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4835
4836         if (esi[1] & DP_CP_IRQ) {
4837                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4838                 ack[1] |= DP_CP_IRQ;
4839         }
4840 }
4841
4842 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4843 {
4844         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4845         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4846         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4847         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4848
4849         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4850                              esi_link_status_size) != esi_link_status_size) {
4851                 drm_err(&i915->drm,
4852                         "[ENCODER:%d:%s] Failed to read link status\n",
4853                         encoder->base.base.id, encoder->base.name);
4854                 return false;
4855         }
4856
4857         return intel_dp_link_ok(intel_dp, link_status);
4858 }
4859
4860 /**
4861  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4862  * @intel_dp: Intel DP struct
4863  *
4864  * Read any pending MST interrupts, call MST core to handle these and ack the
4865  * interrupts. Check if the main and AUX link state is ok.
4866  *
4867  * Returns:
4868  * - %true if pending interrupts were serviced (or no interrupts were
4869  *   pending) w/o detecting an error condition.
4870  * - %false if an error condition - like AUX failure or a loss of link - is
4871  *   detected, which needs servicing from the hotplug work.
4872  */
4873 static bool
4874 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4875 {
4876         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4877         bool link_ok = true;
4878
4879         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4880
4881         for (;;) {
4882                 u8 esi[4] = {};
4883                 u8 ack[4] = {};
4884
4885                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4886                         drm_dbg_kms(&i915->drm,
4887                                     "failed to get ESI - device may have failed\n");
4888                         link_ok = false;
4889
4890                         break;
4891                 }
4892
4893                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4894
4895                 if (intel_dp->active_mst_links > 0 && link_ok &&
4896                     esi[3] & LINK_STATUS_CHANGED) {
4897                         if (!intel_dp_mst_link_status(intel_dp))
4898                                 link_ok = false;
4899                         ack[3] |= LINK_STATUS_CHANGED;
4900                 }
4901
4902                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4903
4904                 if (!memchr_inv(ack, 0, sizeof(ack)))
4905                         break;
4906
4907                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4908                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4909
4910                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4911                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4912         }
4913
4914         return link_ok;
4915 }
4916
4917 static void
4918 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4919 {
4920         bool is_active;
4921         u8 buf = 0;
4922
4923         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4924         if (intel_dp->frl.is_trained && !is_active) {
4925                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4926                         return;
4927
4928                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4929                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4930                         return;
4931
4932                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4933
4934                 intel_dp->frl.is_trained = false;
4935
4936                 /* Restart FRL training or fall back to TMDS mode */
4937                 intel_dp_check_frl_training(intel_dp);
4938         }
4939 }
4940
4941 static bool
4942 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4943 {
4944         u8 link_status[DP_LINK_STATUS_SIZE];
4945
4946         if (!intel_dp->link_trained)
4947                 return false;
4948
4949         /*
4950          * While PSR source HW is enabled, it will control main-link sending
4951          * frames, enabling and disabling it so trying to do a retrain will fail
4952          * as the link would or not be on or it could mix training patterns
4953          * and frame data at the same time causing retrain to fail.
4954          * Also when exiting PSR, HW will retrain the link anyways fixing
4955          * any link status error.
4956          */
4957         if (intel_psr_enabled(intel_dp))
4958                 return false;
4959
4960         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4961                                              link_status) < 0)
4962                 return false;
4963
4964         /*
4965          * Validate the cached values of intel_dp->link_rate and
4966          * intel_dp->lane_count before attempting to retrain.
4967          *
4968          * FIXME would be nice to user the crtc state here, but since
4969          * we need to call this from the short HPD handler that seems
4970          * a bit hard.
4971          */
4972         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4973                                         intel_dp->lane_count))
4974                 return false;
4975
4976         /* Retrain if link not ok */
4977         return !intel_dp_link_ok(intel_dp, link_status);
4978 }
4979
4980 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4981                                    const struct drm_connector_state *conn_state)
4982 {
4983         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4984         struct intel_encoder *encoder;
4985         enum pipe pipe;
4986
4987         if (!conn_state->best_encoder)
4988                 return false;
4989
4990         /* SST */
4991         encoder = &dp_to_dig_port(intel_dp)->base;
4992         if (conn_state->best_encoder == &encoder->base)
4993                 return true;
4994
4995         /* MST */
4996         for_each_pipe(i915, pipe) {
4997                 encoder = &intel_dp->mst_encoders[pipe]->base;
4998                 if (conn_state->best_encoder == &encoder->base)
4999                         return true;
5000         }
5001
5002         return false;
5003 }
5004
5005 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5006                               struct drm_modeset_acquire_ctx *ctx,
5007                               u8 *pipe_mask)
5008 {
5009         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5010         struct drm_connector_list_iter conn_iter;
5011         struct intel_connector *connector;
5012         int ret = 0;
5013
5014         *pipe_mask = 0;
5015
5016         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5017         for_each_intel_connector_iter(connector, &conn_iter) {
5018                 struct drm_connector_state *conn_state =
5019                         connector->base.state;
5020                 struct intel_crtc_state *crtc_state;
5021                 struct intel_crtc *crtc;
5022
5023                 if (!intel_dp_has_connector(intel_dp, conn_state))
5024                         continue;
5025
5026                 crtc = to_intel_crtc(conn_state->crtc);
5027                 if (!crtc)
5028                         continue;
5029
5030                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5031                 if (ret)
5032                         break;
5033
5034                 crtc_state = to_intel_crtc_state(crtc->base.state);
5035
5036                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5037
5038                 if (!crtc_state->hw.active)
5039                         continue;
5040
5041                 if (conn_state->commit &&
5042                     !try_wait_for_completion(&conn_state->commit->hw_done))
5043                         continue;
5044
5045                 *pipe_mask |= BIT(crtc->pipe);
5046         }
5047         drm_connector_list_iter_end(&conn_iter);
5048
5049         return ret;
5050 }
5051
5052 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5053 {
5054         struct intel_connector *connector = intel_dp->attached_connector;
5055
5056         return connector->base.status == connector_status_connected ||
5057                 intel_dp->is_mst;
5058 }
5059
5060 int intel_dp_retrain_link(struct intel_encoder *encoder,
5061                           struct drm_modeset_acquire_ctx *ctx)
5062 {
5063         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5064         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5065         struct intel_crtc *crtc;
5066         u8 pipe_mask;
5067         int ret;
5068
5069         if (!intel_dp_is_connected(intel_dp))
5070                 return 0;
5071
5072         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5073                                ctx);
5074         if (ret)
5075                 return ret;
5076
5077         if (!intel_dp_needs_link_retrain(intel_dp))
5078                 return 0;
5079
5080         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5081         if (ret)
5082                 return ret;
5083
5084         if (pipe_mask == 0)
5085                 return 0;
5086
5087         if (!intel_dp_needs_link_retrain(intel_dp))
5088                 return 0;
5089
5090         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5091                     encoder->base.base.id, encoder->base.name);
5092
5093         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5094                 const struct intel_crtc_state *crtc_state =
5095                         to_intel_crtc_state(crtc->base.state);
5096
5097                 /* Suppress underruns caused by re-training */
5098                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5099                 if (crtc_state->has_pch_encoder)
5100                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5101                                                               intel_crtc_pch_transcoder(crtc), false);
5102         }
5103
5104         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5105                 const struct intel_crtc_state *crtc_state =
5106                         to_intel_crtc_state(crtc->base.state);
5107
5108                 /* retrain on the MST master transcoder */
5109                 if (DISPLAY_VER(dev_priv) >= 12 &&
5110                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5111                     !intel_dp_mst_is_master_trans(crtc_state))
5112                         continue;
5113
5114                 intel_dp_check_frl_training(intel_dp);
5115                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5116                 intel_dp_start_link_train(intel_dp, crtc_state);
5117                 intel_dp_stop_link_train(intel_dp, crtc_state);
5118                 break;
5119         }
5120
5121         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5122                 const struct intel_crtc_state *crtc_state =
5123                         to_intel_crtc_state(crtc->base.state);
5124
5125                 /* Keep underrun reporting disabled until things are stable */
5126                 intel_crtc_wait_for_next_vblank(crtc);
5127
5128                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5129                 if (crtc_state->has_pch_encoder)
5130                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5131                                                               intel_crtc_pch_transcoder(crtc), true);
5132         }
5133
5134         return 0;
5135 }
5136
5137 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5138                                   struct drm_modeset_acquire_ctx *ctx,
5139                                   u8 *pipe_mask)
5140 {
5141         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5142         struct drm_connector_list_iter conn_iter;
5143         struct intel_connector *connector;
5144         int ret = 0;
5145
5146         *pipe_mask = 0;
5147
5148         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5149         for_each_intel_connector_iter(connector, &conn_iter) {
5150                 struct drm_connector_state *conn_state =
5151                         connector->base.state;
5152                 struct intel_crtc_state *crtc_state;
5153                 struct intel_crtc *crtc;
5154
5155                 if (!intel_dp_has_connector(intel_dp, conn_state))
5156                         continue;
5157
5158                 crtc = to_intel_crtc(conn_state->crtc);
5159                 if (!crtc)
5160                         continue;
5161
5162                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5163                 if (ret)
5164                         break;
5165
5166                 crtc_state = to_intel_crtc_state(crtc->base.state);
5167
5168                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5169
5170                 if (!crtc_state->hw.active)
5171                         continue;
5172
5173                 if (conn_state->commit &&
5174                     !try_wait_for_completion(&conn_state->commit->hw_done))
5175                         continue;
5176
5177                 *pipe_mask |= BIT(crtc->pipe);
5178         }
5179         drm_connector_list_iter_end(&conn_iter);
5180
5181         return ret;
5182 }
5183
5184 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5185                                 struct drm_modeset_acquire_ctx *ctx)
5186 {
5187         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5188         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5189         struct intel_crtc *crtc;
5190         u8 pipe_mask;
5191         int ret;
5192
5193         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5194                                ctx);
5195         if (ret)
5196                 return ret;
5197
5198         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5199         if (ret)
5200                 return ret;
5201
5202         if (pipe_mask == 0)
5203                 return 0;
5204
5205         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5206                     encoder->base.base.id, encoder->base.name);
5207
5208         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5209                 const struct intel_crtc_state *crtc_state =
5210                         to_intel_crtc_state(crtc->base.state);
5211
5212                 /* test on the MST master transcoder */
5213                 if (DISPLAY_VER(dev_priv) >= 12 &&
5214                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5215                     !intel_dp_mst_is_master_trans(crtc_state))
5216                         continue;
5217
5218                 intel_dp_process_phy_request(intel_dp, crtc_state);
5219                 break;
5220         }
5221
5222         return 0;
5223 }
5224
5225 void intel_dp_phy_test(struct intel_encoder *encoder)
5226 {
5227         struct drm_modeset_acquire_ctx ctx;
5228         int ret;
5229
5230         drm_modeset_acquire_init(&ctx, 0);
5231
5232         for (;;) {
5233                 ret = intel_dp_do_phy_test(encoder, &ctx);
5234
5235                 if (ret == -EDEADLK) {
5236                         drm_modeset_backoff(&ctx);
5237                         continue;
5238                 }
5239
5240                 break;
5241         }
5242
5243         drm_modeset_drop_locks(&ctx);
5244         drm_modeset_acquire_fini(&ctx);
5245         drm_WARN(encoder->base.dev, ret,
5246                  "Acquiring modeset locks failed with %i\n", ret);
5247 }
5248
5249 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5250 {
5251         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5252         u8 val;
5253
5254         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5255                 return;
5256
5257         if (drm_dp_dpcd_readb(&intel_dp->aux,
5258                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5259                 return;
5260
5261         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5262
5263         if (val & DP_AUTOMATED_TEST_REQUEST)
5264                 intel_dp_handle_test_request(intel_dp);
5265
5266         if (val & DP_CP_IRQ)
5267                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5268
5269         if (val & DP_SINK_SPECIFIC_IRQ)
5270                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5271 }
5272
5273 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5274 {
5275         u8 val;
5276
5277         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5278                 return;
5279
5280         if (drm_dp_dpcd_readb(&intel_dp->aux,
5281                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5282                 return;
5283
5284         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5285                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5286                 return;
5287
5288         if (val & HDMI_LINK_STATUS_CHANGED)
5289                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5290 }
5291
5292 /*
5293  * According to DP spec
5294  * 5.1.2:
5295  *  1. Read DPCD
5296  *  2. Configure link according to Receiver Capabilities
5297  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5298  *  4. Check link status on receipt of hot-plug interrupt
5299  *
5300  * intel_dp_short_pulse -  handles short pulse interrupts
5301  * when full detection is not required.
5302  * Returns %true if short pulse is handled and full detection
5303  * is NOT required and %false otherwise.
5304  */
5305 static bool
5306 intel_dp_short_pulse(struct intel_dp *intel_dp)
5307 {
5308         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5309         u8 old_sink_count = intel_dp->sink_count;
5310         bool ret;
5311
5312         /*
5313          * Clearing compliance test variables to allow capturing
5314          * of values for next automated test request.
5315          */
5316         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5317
5318         /*
5319          * Now read the DPCD to see if it's actually running
5320          * If the current value of sink count doesn't match with
5321          * the value that was stored earlier or dpcd read failed
5322          * we need to do full detection
5323          */
5324         ret = intel_dp_get_dpcd(intel_dp);
5325
5326         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5327                 /* No need to proceed if we are going to do full detect */
5328                 return false;
5329         }
5330
5331         intel_dp_check_device_service_irq(intel_dp);
5332         intel_dp_check_link_service_irq(intel_dp);
5333
5334         /* Handle CEC interrupts, if any */
5335         drm_dp_cec_irq(&intel_dp->aux);
5336
5337         /* defer to the hotplug work for link retraining if needed */
5338         if (intel_dp_needs_link_retrain(intel_dp))
5339                 return false;
5340
5341         intel_psr_short_pulse(intel_dp);
5342
5343         switch (intel_dp->compliance.test_type) {
5344         case DP_TEST_LINK_TRAINING:
5345                 drm_dbg_kms(&dev_priv->drm,
5346                             "Link Training Compliance Test requested\n");
5347                 /* Send a Hotplug Uevent to userspace to start modeset */
5348                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5349                 break;
5350         case DP_TEST_LINK_PHY_TEST_PATTERN:
5351                 drm_dbg_kms(&dev_priv->drm,
5352                             "PHY test pattern Compliance Test requested\n");
5353                 /*
5354                  * Schedule long hpd to do the test
5355                  *
5356                  * FIXME get rid of the ad-hoc phy test modeset code
5357                  * and properly incorporate it into the normal modeset.
5358                  */
5359                 return false;
5360         }
5361
5362         return true;
5363 }
5364
5365 /* XXX this is probably wrong for multiple downstream ports */
5366 static enum drm_connector_status
5367 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5368 {
5369         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5370         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5371         u8 *dpcd = intel_dp->dpcd;
5372         u8 type;
5373
5374         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5375                 return connector_status_connected;
5376
5377         lspcon_resume(dig_port);
5378
5379         if (!intel_dp_get_dpcd(intel_dp))
5380                 return connector_status_disconnected;
5381
5382         /* if there's no downstream port, we're done */
5383         if (!drm_dp_is_branch(dpcd))
5384                 return connector_status_connected;
5385
5386         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5387         if (intel_dp_has_sink_count(intel_dp) &&
5388             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5389                 return intel_dp->sink_count ?
5390                 connector_status_connected : connector_status_disconnected;
5391         }
5392
5393         if (intel_dp_can_mst(intel_dp))
5394                 return connector_status_connected;
5395
5396         /* If no HPD, poke DDC gently */
5397         if (drm_probe_ddc(&intel_dp->aux.ddc))
5398                 return connector_status_connected;
5399
5400         /* Well we tried, say unknown for unreliable port types */
5401         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5402                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5403                 if (type == DP_DS_PORT_TYPE_VGA ||
5404                     type == DP_DS_PORT_TYPE_NON_EDID)
5405                         return connector_status_unknown;
5406         } else {
5407                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5408                         DP_DWN_STRM_PORT_TYPE_MASK;
5409                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5410                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5411                         return connector_status_unknown;
5412         }
5413
5414         /* Anything else is out of spec, warn and ignore */
5415         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5416         return connector_status_disconnected;
5417 }
5418
5419 static enum drm_connector_status
5420 edp_detect(struct intel_dp *intel_dp)
5421 {
5422         return connector_status_connected;
5423 }
5424
5425 void intel_digital_port_lock(struct intel_encoder *encoder)
5426 {
5427         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5428
5429         if (dig_port->lock)
5430                 dig_port->lock(dig_port);
5431 }
5432
5433 void intel_digital_port_unlock(struct intel_encoder *encoder)
5434 {
5435         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5436
5437         if (dig_port->unlock)
5438                 dig_port->unlock(dig_port);
5439 }
5440
5441 /*
5442  * intel_digital_port_connected_locked - is the specified port connected?
5443  * @encoder: intel_encoder
5444  *
5445  * In cases where there's a connector physically connected but it can't be used
5446  * by our hardware we also return false, since the rest of the driver should
5447  * pretty much treat the port as disconnected. This is relevant for type-C
5448  * (starting on ICL) where there's ownership involved.
5449  *
5450  * The caller must hold the lock acquired by calling intel_digital_port_lock()
5451  * when calling this function.
5452  *
5453  * Return %true if port is connected, %false otherwise.
5454  */
5455 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5456 {
5457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5458         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5459         bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5460         bool is_connected = false;
5461         intel_wakeref_t wakeref;
5462
5463         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5464                 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5465
5466                 do {
5467                         is_connected = dig_port->connected(encoder);
5468                         if (is_connected || is_glitch_free)
5469                                 break;
5470                         usleep_range(10, 30);
5471                 } while (time_before(jiffies, wait_expires));
5472         }
5473
5474         return is_connected;
5475 }
5476
5477 bool intel_digital_port_connected(struct intel_encoder *encoder)
5478 {
5479         bool ret;
5480
5481         intel_digital_port_lock(encoder);
5482         ret = intel_digital_port_connected_locked(encoder);
5483         intel_digital_port_unlock(encoder);
5484
5485         return ret;
5486 }
5487
5488 static const struct drm_edid *
5489 intel_dp_get_edid(struct intel_dp *intel_dp)
5490 {
5491         struct intel_connector *connector = intel_dp->attached_connector;
5492         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5493
5494         /* Use panel fixed edid if we have one */
5495         if (fixed_edid) {
5496                 /* invalid edid */
5497                 if (IS_ERR(fixed_edid))
5498                         return NULL;
5499
5500                 return drm_edid_dup(fixed_edid);
5501         }
5502
5503         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5504 }
5505
5506 static void
5507 intel_dp_update_dfp(struct intel_dp *intel_dp,
5508                     const struct drm_edid *drm_edid)
5509 {
5510         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5511         struct intel_connector *connector = intel_dp->attached_connector;
5512
5513         intel_dp->dfp.max_bpc =
5514                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5515                                           intel_dp->downstream_ports, drm_edid);
5516
5517         intel_dp->dfp.max_dotclock =
5518                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5519                                                intel_dp->downstream_ports);
5520
5521         intel_dp->dfp.min_tmds_clock =
5522                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5523                                                  intel_dp->downstream_ports,
5524                                                  drm_edid);
5525         intel_dp->dfp.max_tmds_clock =
5526                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5527                                                  intel_dp->downstream_ports,
5528                                                  drm_edid);
5529
5530         intel_dp->dfp.pcon_max_frl_bw =
5531                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5532                                            intel_dp->downstream_ports);
5533
5534         drm_dbg_kms(&i915->drm,
5535                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5536                     connector->base.base.id, connector->base.name,
5537                     intel_dp->dfp.max_bpc,
5538                     intel_dp->dfp.max_dotclock,
5539                     intel_dp->dfp.min_tmds_clock,
5540                     intel_dp->dfp.max_tmds_clock,
5541                     intel_dp->dfp.pcon_max_frl_bw);
5542
5543         intel_dp_get_pcon_dsc_cap(intel_dp);
5544 }
5545
5546 static bool
5547 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5548 {
5549         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5550             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5551                 return true;
5552
5553         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5554             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5555                 return true;
5556
5557         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5558             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5559                 return true;
5560
5561         return false;
5562 }
5563
5564 static void
5565 intel_dp_update_420(struct intel_dp *intel_dp)
5566 {
5567         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5568         struct intel_connector *connector = intel_dp->attached_connector;
5569
5570         intel_dp->dfp.ycbcr420_passthrough =
5571                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5572                                                   intel_dp->downstream_ports);
5573         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5574         intel_dp->dfp.ycbcr_444_to_420 =
5575                 dp_to_dig_port(intel_dp)->lspcon.active ||
5576                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5577                                                         intel_dp->downstream_ports);
5578         intel_dp->dfp.rgb_to_ycbcr =
5579                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5580                                                           intel_dp->downstream_ports,
5581                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5582
5583         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5584
5585         drm_dbg_kms(&i915->drm,
5586                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5587                     connector->base.base.id, connector->base.name,
5588                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5589                     str_yes_no(connector->base.ycbcr_420_allowed),
5590                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5591 }
5592
5593 static void
5594 intel_dp_set_edid(struct intel_dp *intel_dp)
5595 {
5596         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5597         struct intel_connector *connector = intel_dp->attached_connector;
5598         const struct drm_edid *drm_edid;
5599         bool vrr_capable;
5600
5601         intel_dp_unset_edid(intel_dp);
5602         drm_edid = intel_dp_get_edid(intel_dp);
5603         connector->detect_edid = drm_edid;
5604
5605         /* Below we depend on display info having been updated */
5606         drm_edid_connector_update(&connector->base, drm_edid);
5607
5608         vrr_capable = intel_vrr_is_capable(connector);
5609         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5610                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5611         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5612
5613         intel_dp_update_dfp(intel_dp, drm_edid);
5614         intel_dp_update_420(intel_dp);
5615
5616         drm_dp_cec_attach(&intel_dp->aux,
5617                           connector->base.display_info.source_physical_address);
5618 }
5619
5620 static void
5621 intel_dp_unset_edid(struct intel_dp *intel_dp)
5622 {
5623         struct intel_connector *connector = intel_dp->attached_connector;
5624
5625         drm_dp_cec_unset_edid(&intel_dp->aux);
5626         drm_edid_free(connector->detect_edid);
5627         connector->detect_edid = NULL;
5628
5629         intel_dp->dfp.max_bpc = 0;
5630         intel_dp->dfp.max_dotclock = 0;
5631         intel_dp->dfp.min_tmds_clock = 0;
5632         intel_dp->dfp.max_tmds_clock = 0;
5633
5634         intel_dp->dfp.pcon_max_frl_bw = 0;
5635
5636         intel_dp->dfp.ycbcr_444_to_420 = false;
5637         connector->base.ycbcr_420_allowed = false;
5638
5639         drm_connector_set_vrr_capable_property(&connector->base,
5640                                                false);
5641 }
5642
5643 static void
5644 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5645 {
5646         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5647
5648         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5649         if (!HAS_DSC(i915))
5650                 return;
5651
5652         if (intel_dp_is_edp(intel_dp))
5653                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5654                                            connector);
5655         else
5656                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5657                                           connector);
5658 }
5659
5660 static int
5661 intel_dp_detect(struct drm_connector *connector,
5662                 struct drm_modeset_acquire_ctx *ctx,
5663                 bool force)
5664 {
5665         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5666         struct intel_connector *intel_connector =
5667                 to_intel_connector(connector);
5668         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5669         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5670         struct intel_encoder *encoder = &dig_port->base;
5671         enum drm_connector_status status;
5672
5673         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5674                     connector->base.id, connector->name);
5675         drm_WARN_ON(&dev_priv->drm,
5676                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5677
5678         if (!intel_display_device_enabled(dev_priv))
5679                 return connector_status_disconnected;
5680
5681         if (!intel_display_driver_check_access(dev_priv))
5682                 return connector->status;
5683
5684         /* Can't disconnect eDP */
5685         if (intel_dp_is_edp(intel_dp))
5686                 status = edp_detect(intel_dp);
5687         else if (intel_digital_port_connected(encoder))
5688                 status = intel_dp_detect_dpcd(intel_dp);
5689         else
5690                 status = connector_status_disconnected;
5691
5692         if (status == connector_status_disconnected) {
5693                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5694                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5695                 intel_dp->psr.sink_panel_replay_support = false;
5696
5697                 if (intel_dp->is_mst) {
5698                         drm_dbg_kms(&dev_priv->drm,
5699                                     "MST device may have disappeared %d vs %d\n",
5700                                     intel_dp->is_mst,
5701                                     intel_dp->mst_mgr.mst_state);
5702                         intel_dp->is_mst = false;
5703                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5704                                                         intel_dp->is_mst);
5705                 }
5706
5707                 goto out;
5708         }
5709
5710         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5711
5712         intel_dp_configure_mst(intel_dp);
5713
5714         /*
5715          * TODO: Reset link params when switching to MST mode, until MST
5716          * supports link training fallback params.
5717          */
5718         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5719                 intel_dp_reset_max_link_params(intel_dp);
5720                 intel_dp->reset_link_params = false;
5721         }
5722
5723         intel_dp_print_rates(intel_dp);
5724
5725         if (intel_dp->is_mst) {
5726                 /*
5727                  * If we are in MST mode then this connector
5728                  * won't appear connected or have anything
5729                  * with EDID on it
5730                  */
5731                 status = connector_status_disconnected;
5732                 goto out;
5733         }
5734
5735         /*
5736          * Some external monitors do not signal loss of link synchronization
5737          * with an IRQ_HPD, so force a link status check.
5738          */
5739         if (!intel_dp_is_edp(intel_dp)) {
5740                 int ret;
5741
5742                 ret = intel_dp_retrain_link(encoder, ctx);
5743                 if (ret)
5744                         return ret;
5745         }
5746
5747         /*
5748          * Clearing NACK and defer counts to get their exact values
5749          * while reading EDID which are required by Compliance tests
5750          * 4.2.2.4 and 4.2.2.5
5751          */
5752         intel_dp->aux.i2c_nack_count = 0;
5753         intel_dp->aux.i2c_defer_count = 0;
5754
5755         intel_dp_set_edid(intel_dp);
5756         if (intel_dp_is_edp(intel_dp) ||
5757             to_intel_connector(connector)->detect_edid)
5758                 status = connector_status_connected;
5759
5760         intel_dp_check_device_service_irq(intel_dp);
5761
5762 out:
5763         if (status != connector_status_connected && !intel_dp->is_mst)
5764                 intel_dp_unset_edid(intel_dp);
5765
5766         if (!intel_dp_is_edp(intel_dp))
5767                 drm_dp_set_subconnector_property(connector,
5768                                                  status,
5769                                                  intel_dp->dpcd,
5770                                                  intel_dp->downstream_ports);
5771         return status;
5772 }
5773
5774 static void
5775 intel_dp_force(struct drm_connector *connector)
5776 {
5777         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5778         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5779         struct intel_encoder *intel_encoder = &dig_port->base;
5780         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5781
5782         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5783                     connector->base.id, connector->name);
5784
5785         if (!intel_display_driver_check_access(dev_priv))
5786                 return;
5787
5788         intel_dp_unset_edid(intel_dp);
5789
5790         if (connector->status != connector_status_connected)
5791                 return;
5792
5793         intel_dp_set_edid(intel_dp);
5794 }
5795
5796 static int intel_dp_get_modes(struct drm_connector *connector)
5797 {
5798         struct intel_connector *intel_connector = to_intel_connector(connector);
5799         int num_modes;
5800
5801         /* drm_edid_connector_update() done in ->detect() or ->force() */
5802         num_modes = drm_edid_connector_add_modes(connector);
5803
5804         /* Also add fixed mode, which may or may not be present in EDID */
5805         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5806                 num_modes += intel_panel_get_modes(intel_connector);
5807
5808         if (num_modes)
5809                 return num_modes;
5810
5811         if (!intel_connector->detect_edid) {
5812                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5813                 struct drm_display_mode *mode;
5814
5815                 mode = drm_dp_downstream_mode(connector->dev,
5816                                               intel_dp->dpcd,
5817                                               intel_dp->downstream_ports);
5818                 if (mode) {
5819                         drm_mode_probed_add(connector, mode);
5820                         num_modes++;
5821                 }
5822         }
5823
5824         return num_modes;
5825 }
5826
5827 static int
5828 intel_dp_connector_register(struct drm_connector *connector)
5829 {
5830         struct drm_i915_private *i915 = to_i915(connector->dev);
5831         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5832         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5833         struct intel_lspcon *lspcon = &dig_port->lspcon;
5834         int ret;
5835
5836         ret = intel_connector_register(connector);
5837         if (ret)
5838                 return ret;
5839
5840         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5841                     intel_dp->aux.name, connector->kdev->kobj.name);
5842
5843         intel_dp->aux.dev = connector->kdev;
5844         ret = drm_dp_aux_register(&intel_dp->aux);
5845         if (!ret)
5846                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5847
5848         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5849                 return ret;
5850
5851         /*
5852          * ToDo: Clean this up to handle lspcon init and resume more
5853          * efficiently and streamlined.
5854          */
5855         if (lspcon_init(dig_port)) {
5856                 lspcon_detect_hdr_capability(lspcon);
5857                 if (lspcon->hdr_supported)
5858                         drm_connector_attach_hdr_output_metadata_property(connector);
5859         }
5860
5861         return ret;
5862 }
5863
5864 static void
5865 intel_dp_connector_unregister(struct drm_connector *connector)
5866 {
5867         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5868
5869         drm_dp_cec_unregister_connector(&intel_dp->aux);
5870         drm_dp_aux_unregister(&intel_dp->aux);
5871         intel_connector_unregister(connector);
5872 }
5873
5874 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5875 {
5876         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5877         struct intel_dp *intel_dp = &dig_port->dp;
5878
5879         intel_dp_mst_encoder_cleanup(dig_port);
5880
5881         intel_pps_vdd_off_sync(intel_dp);
5882
5883         /*
5884          * Ensure power off delay is respected on module remove, so that we can
5885          * reduce delays at driver probe. See pps_init_timestamps().
5886          */
5887         intel_pps_wait_power_cycle(intel_dp);
5888
5889         intel_dp_aux_fini(intel_dp);
5890 }
5891
5892 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5893 {
5894         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5895
5896         intel_pps_vdd_off_sync(intel_dp);
5897 }
5898
5899 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5900 {
5901         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5902
5903         intel_pps_wait_power_cycle(intel_dp);
5904 }
5905
5906 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5907                                     int tile_group_id)
5908 {
5909         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5910         struct drm_connector_list_iter conn_iter;
5911         struct drm_connector *connector;
5912         int ret = 0;
5913
5914         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5915         drm_for_each_connector_iter(connector, &conn_iter) {
5916                 struct drm_connector_state *conn_state;
5917                 struct intel_crtc_state *crtc_state;
5918                 struct intel_crtc *crtc;
5919
5920                 if (!connector->has_tile ||
5921                     connector->tile_group->id != tile_group_id)
5922                         continue;
5923
5924                 conn_state = drm_atomic_get_connector_state(&state->base,
5925                                                             connector);
5926                 if (IS_ERR(conn_state)) {
5927                         ret = PTR_ERR(conn_state);
5928                         break;
5929                 }
5930
5931                 crtc = to_intel_crtc(conn_state->crtc);
5932
5933                 if (!crtc)
5934                         continue;
5935
5936                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5937                 crtc_state->uapi.mode_changed = true;
5938
5939                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5940                 if (ret)
5941                         break;
5942         }
5943         drm_connector_list_iter_end(&conn_iter);
5944
5945         return ret;
5946 }
5947
5948 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5949 {
5950         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5951         struct intel_crtc *crtc;
5952
5953         if (transcoders == 0)
5954                 return 0;
5955
5956         for_each_intel_crtc(&dev_priv->drm, crtc) {
5957                 struct intel_crtc_state *crtc_state;
5958                 int ret;
5959
5960                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5961                 if (IS_ERR(crtc_state))
5962                         return PTR_ERR(crtc_state);
5963
5964                 if (!crtc_state->hw.enable)
5965                         continue;
5966
5967                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5968                         continue;
5969
5970                 crtc_state->uapi.mode_changed = true;
5971
5972                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5973                 if (ret)
5974                         return ret;
5975
5976                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5977                 if (ret)
5978                         return ret;
5979
5980                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5981         }
5982
5983         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5984
5985         return 0;
5986 }
5987
5988 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5989                                       struct drm_connector *connector)
5990 {
5991         const struct drm_connector_state *old_conn_state =
5992                 drm_atomic_get_old_connector_state(&state->base, connector);
5993         const struct intel_crtc_state *old_crtc_state;
5994         struct intel_crtc *crtc;
5995         u8 transcoders;
5996
5997         crtc = to_intel_crtc(old_conn_state->crtc);
5998         if (!crtc)
5999                 return 0;
6000
6001         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6002
6003         if (!old_crtc_state->hw.active)
6004                 return 0;
6005
6006         transcoders = old_crtc_state->sync_mode_slaves_mask;
6007         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6008                 transcoders |= BIT(old_crtc_state->master_transcoder);
6009
6010         return intel_modeset_affected_transcoders(state,
6011                                                   transcoders);
6012 }
6013
6014 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6015                                            struct drm_atomic_state *_state)
6016 {
6017         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6018         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6019         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6020         struct intel_connector *intel_conn = to_intel_connector(conn);
6021         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6022         int ret;
6023
6024         ret = intel_digital_connector_atomic_check(conn, &state->base);
6025         if (ret)
6026                 return ret;
6027
6028         if (intel_dp_mst_source_support(intel_dp)) {
6029                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6030                 if (ret)
6031                         return ret;
6032         }
6033
6034         /*
6035          * We don't enable port sync on BDW due to missing w/as and
6036          * due to not having adjusted the modeset sequence appropriately.
6037          */
6038         if (DISPLAY_VER(dev_priv) < 9)
6039                 return 0;
6040
6041         if (!intel_connector_needs_modeset(state, conn))
6042                 return 0;
6043
6044         if (conn->has_tile) {
6045                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6046                 if (ret)
6047                         return ret;
6048         }
6049
6050         return intel_modeset_synced_crtcs(state, conn);
6051 }
6052
6053 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6054                                        enum drm_connector_status hpd_state)
6055 {
6056         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6057         struct drm_i915_private *i915 = to_i915(connector->dev);
6058         bool hpd_high = hpd_state == connector_status_connected;
6059         unsigned int hpd_pin = encoder->hpd_pin;
6060         bool need_work = false;
6061
6062         spin_lock_irq(&i915->irq_lock);
6063         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6064                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6065
6066                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6067                 need_work = true;
6068         }
6069         spin_unlock_irq(&i915->irq_lock);
6070
6071         if (need_work)
6072                 intel_hpd_schedule_detection(i915);
6073 }
6074
6075 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6076         .force = intel_dp_force,
6077         .fill_modes = drm_helper_probe_single_connector_modes,
6078         .atomic_get_property = intel_digital_connector_atomic_get_property,
6079         .atomic_set_property = intel_digital_connector_atomic_set_property,
6080         .late_register = intel_dp_connector_register,
6081         .early_unregister = intel_dp_connector_unregister,
6082         .destroy = intel_connector_destroy,
6083         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6084         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6085         .oob_hotplug_event = intel_dp_oob_hotplug_event,
6086 };
6087
6088 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6089         .detect_ctx = intel_dp_detect,
6090         .get_modes = intel_dp_get_modes,
6091         .mode_valid = intel_dp_mode_valid,
6092         .atomic_check = intel_dp_connector_atomic_check,
6093 };
6094
6095 enum irqreturn
6096 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6097 {
6098         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6099         struct intel_dp *intel_dp = &dig_port->dp;
6100
6101         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6102             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6103                 /*
6104                  * vdd off can generate a long/short pulse on eDP which
6105                  * would require vdd on to handle it, and thus we
6106                  * would end up in an endless cycle of
6107                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6108                  */
6109                 drm_dbg_kms(&i915->drm,
6110                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6111                             long_hpd ? "long" : "short",
6112                             dig_port->base.base.base.id,
6113                             dig_port->base.base.name);
6114                 return IRQ_HANDLED;
6115         }
6116
6117         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6118                     dig_port->base.base.base.id,
6119                     dig_port->base.base.name,
6120                     long_hpd ? "long" : "short");
6121
6122         if (long_hpd) {
6123                 intel_dp->reset_link_params = true;
6124                 return IRQ_NONE;
6125         }
6126
6127         if (intel_dp->is_mst) {
6128                 if (!intel_dp_check_mst_status(intel_dp))
6129                         return IRQ_NONE;
6130         } else if (!intel_dp_short_pulse(intel_dp)) {
6131                 return IRQ_NONE;
6132         }
6133
6134         return IRQ_HANDLED;
6135 }
6136
6137 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6138                                   const struct intel_bios_encoder_data *devdata,
6139                                   enum port port)
6140 {
6141         /*
6142          * eDP not supported on g4x. so bail out early just
6143          * for a bit extra safety in case the VBT is bonkers.
6144          */
6145         if (DISPLAY_VER(dev_priv) < 5)
6146                 return false;
6147
6148         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6149                 return true;
6150
6151         return devdata && intel_bios_encoder_supports_edp(devdata);
6152 }
6153
6154 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6155 {
6156         const struct intel_bios_encoder_data *devdata =
6157                 intel_bios_encoder_data_lookup(i915, port);
6158
6159         return _intel_dp_is_port_edp(i915, devdata, port);
6160 }
6161
6162 static bool
6163 has_gamut_metadata_dip(struct intel_encoder *encoder)
6164 {
6165         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6166         enum port port = encoder->port;
6167
6168         if (intel_bios_encoder_is_lspcon(encoder->devdata))
6169                 return false;
6170
6171         if (DISPLAY_VER(i915) >= 11)
6172                 return true;
6173
6174         if (port == PORT_A)
6175                 return false;
6176
6177         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6178             DISPLAY_VER(i915) >= 9)
6179                 return true;
6180
6181         return false;
6182 }
6183
6184 static void
6185 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6186 {
6187         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6188         enum port port = dp_to_dig_port(intel_dp)->base.port;
6189
6190         if (!intel_dp_is_edp(intel_dp))
6191                 drm_connector_attach_dp_subconnector_property(connector);
6192
6193         if (!IS_G4X(dev_priv) && port != PORT_A)
6194                 intel_attach_force_audio_property(connector);
6195
6196         intel_attach_broadcast_rgb_property(connector);
6197         if (HAS_GMCH(dev_priv))
6198                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6199         else if (DISPLAY_VER(dev_priv) >= 5)
6200                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6201
6202         /* Register HDMI colorspace for case of lspcon */
6203         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6204                 drm_connector_attach_content_type_property(connector);
6205                 intel_attach_hdmi_colorspace_property(connector);
6206         } else {
6207                 intel_attach_dp_colorspace_property(connector);
6208         }
6209
6210         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6211                 drm_connector_attach_hdr_output_metadata_property(connector);
6212
6213         if (HAS_VRR(dev_priv))
6214                 drm_connector_attach_vrr_capable_property(connector);
6215 }
6216
6217 static void
6218 intel_edp_add_properties(struct intel_dp *intel_dp)
6219 {
6220         struct intel_connector *connector = intel_dp->attached_connector;
6221         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6222         const struct drm_display_mode *fixed_mode =
6223                 intel_panel_preferred_fixed_mode(connector);
6224
6225         intel_attach_scaling_mode_property(&connector->base);
6226
6227         drm_connector_set_panel_orientation_with_quirk(&connector->base,
6228                                                        i915->display.vbt.orientation,
6229                                                        fixed_mode->hdisplay,
6230                                                        fixed_mode->vdisplay);
6231 }
6232
6233 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6234                                       struct intel_connector *connector)
6235 {
6236         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6237         enum pipe pipe = INVALID_PIPE;
6238
6239         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6240                 /*
6241                  * Figure out the current pipe for the initial backlight setup.
6242                  * If the current pipe isn't valid, try the PPS pipe, and if that
6243                  * fails just assume pipe A.
6244                  */
6245                 pipe = vlv_active_pipe(intel_dp);
6246
6247                 if (pipe != PIPE_A && pipe != PIPE_B)
6248                         pipe = intel_dp->pps.pps_pipe;
6249
6250                 if (pipe != PIPE_A && pipe != PIPE_B)
6251                         pipe = PIPE_A;
6252         }
6253
6254         intel_backlight_setup(connector, pipe);
6255 }
6256
6257 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6258                                      struct intel_connector *intel_connector)
6259 {
6260         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6261         struct drm_connector *connector = &intel_connector->base;
6262         struct drm_display_mode *fixed_mode;
6263         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6264         bool has_dpcd;
6265         const struct drm_edid *drm_edid;
6266
6267         if (!intel_dp_is_edp(intel_dp))
6268                 return true;
6269
6270         /*
6271          * On IBX/CPT we may get here with LVDS already registered. Since the
6272          * driver uses the only internal power sequencer available for both
6273          * eDP and LVDS bail out early in this case to prevent interfering
6274          * with an already powered-on LVDS power sequencer.
6275          */
6276         if (intel_get_lvds_encoder(dev_priv)) {
6277                 drm_WARN_ON(&dev_priv->drm,
6278                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6279                 drm_info(&dev_priv->drm,
6280                          "LVDS was detected, not registering eDP\n");
6281
6282                 return false;
6283         }
6284
6285         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6286                                     encoder->devdata);
6287
6288         if (!intel_pps_init(intel_dp)) {
6289                 drm_info(&dev_priv->drm,
6290                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6291                          encoder->base.base.id, encoder->base.name);
6292                 /*
6293                  * The BIOS may have still enabled VDD on the PPS even
6294                  * though it's unusable. Make sure we turn it back off
6295                  * and to release the power domain references/etc.
6296                  */
6297                 goto out_vdd_off;
6298         }
6299
6300         /*
6301          * Enable HPD sense for live status check.
6302          * intel_hpd_irq_setup() will turn it off again
6303          * if it's no longer needed later.
6304          *
6305          * The DPCD probe below will make sure VDD is on.
6306          */
6307         intel_hpd_enable_detection(encoder);
6308
6309         /* Cache DPCD and EDID for edp. */
6310         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6311
6312         if (!has_dpcd) {
6313                 /* if this fails, presume the device is a ghost */
6314                 drm_info(&dev_priv->drm,
6315                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6316                          encoder->base.base.id, encoder->base.name);
6317                 goto out_vdd_off;
6318         }
6319
6320         /*
6321          * VBT and straps are liars. Also check HPD as that seems
6322          * to be the most reliable piece of information available.
6323          *
6324          * ... expect on devices that forgot to hook HPD up for eDP
6325          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6326          * ports are attempting to use the same AUX CH, according to VBT.
6327          */
6328         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6329                 /*
6330                  * If this fails, presume the DPCD answer came
6331                  * from some other port using the same AUX CH.
6332                  *
6333                  * FIXME maybe cleaner to check this before the
6334                  * DPCD read? Would need sort out the VDD handling...
6335                  */
6336                 if (!intel_digital_port_connected(encoder)) {
6337                         drm_info(&dev_priv->drm,
6338                                  "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6339                                  encoder->base.base.id, encoder->base.name);
6340                         goto out_vdd_off;
6341                 }
6342
6343                 /*
6344                  * Unfortunately even the HPD based detection fails on
6345                  * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6346                  * back to checking for a VGA branch device. Only do this
6347                  * on known affected platforms to minimize false positives.
6348                  */
6349                 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6350                     (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6351                     DP_DWN_STRM_PORT_TYPE_ANALOG) {
6352                         drm_info(&dev_priv->drm,
6353                                  "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6354                                  encoder->base.base.id, encoder->base.name);
6355                         goto out_vdd_off;
6356                 }
6357         }
6358
6359         mutex_lock(&dev_priv->drm.mode_config.mutex);
6360         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6361         if (!drm_edid) {
6362                 /* Fallback to EDID from ACPI OpRegion, if any */
6363                 drm_edid = intel_opregion_get_edid(intel_connector);
6364                 if (drm_edid)
6365                         drm_dbg_kms(&dev_priv->drm,
6366                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6367                                     connector->base.id, connector->name);
6368         }
6369         if (drm_edid) {
6370                 if (drm_edid_connector_update(connector, drm_edid) ||
6371                     !drm_edid_connector_add_modes(connector)) {
6372                         drm_edid_connector_update(connector, NULL);
6373                         drm_edid_free(drm_edid);
6374                         drm_edid = ERR_PTR(-EINVAL);
6375                 }
6376         } else {
6377                 drm_edid = ERR_PTR(-ENOENT);
6378         }
6379
6380         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6381                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6382
6383         intel_panel_add_edid_fixed_modes(intel_connector, true);
6384
6385         /* MSO requires information from the EDID */
6386         intel_edp_mso_init(intel_dp);
6387
6388         /* multiply the mode clock and horizontal timings for MSO */
6389         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6390                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6391
6392         /* fallback to VBT if available for eDP */
6393         if (!intel_panel_preferred_fixed_mode(intel_connector))
6394                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6395
6396         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6397
6398         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6399                 drm_info(&dev_priv->drm,
6400                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6401                          encoder->base.base.id, encoder->base.name);
6402                 goto out_vdd_off;
6403         }
6404
6405         intel_panel_init(intel_connector, drm_edid);
6406
6407         intel_edp_backlight_setup(intel_dp, intel_connector);
6408
6409         intel_edp_add_properties(intel_dp);
6410
6411         intel_pps_init_late(intel_dp);
6412
6413         return true;
6414
6415 out_vdd_off:
6416         intel_pps_vdd_off_sync(intel_dp);
6417
6418         return false;
6419 }
6420
6421 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6422 {
6423         struct intel_connector *intel_connector;
6424         struct drm_connector *connector;
6425
6426         intel_connector = container_of(work, typeof(*intel_connector),
6427                                        modeset_retry_work);
6428         connector = &intel_connector->base;
6429         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6430                     connector->name);
6431
6432         /* Grab the locks before changing connector property*/
6433         mutex_lock(&connector->dev->mode_config.mutex);
6434         /* Set connector link status to BAD and send a Uevent to notify
6435          * userspace to do a modeset.
6436          */
6437         drm_connector_set_link_status_property(connector,
6438                                                DRM_MODE_LINK_STATUS_BAD);
6439         mutex_unlock(&connector->dev->mode_config.mutex);
6440         /* Send Hotplug uevent so userspace can reprobe */
6441         drm_kms_helper_connector_hotplug_event(connector);
6442 }
6443
6444 bool
6445 intel_dp_init_connector(struct intel_digital_port *dig_port,
6446                         struct intel_connector *intel_connector)
6447 {
6448         struct drm_connector *connector = &intel_connector->base;
6449         struct intel_dp *intel_dp = &dig_port->dp;
6450         struct intel_encoder *intel_encoder = &dig_port->base;
6451         struct drm_device *dev = intel_encoder->base.dev;
6452         struct drm_i915_private *dev_priv = to_i915(dev);
6453         enum port port = intel_encoder->port;
6454         enum phy phy = intel_port_to_phy(dev_priv, port);
6455         int type;
6456
6457         /* Initialize the work for modeset in case of link train failure */
6458         INIT_WORK(&intel_connector->modeset_retry_work,
6459                   intel_dp_modeset_retry_work_fn);
6460
6461         if (drm_WARN(dev, dig_port->max_lanes < 1,
6462                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6463                      dig_port->max_lanes, intel_encoder->base.base.id,
6464                      intel_encoder->base.name))
6465                 return false;
6466
6467         intel_dp->reset_link_params = true;
6468         intel_dp->pps.pps_pipe = INVALID_PIPE;
6469         intel_dp->pps.active_pipe = INVALID_PIPE;
6470
6471         /* Preserve the current hw state. */
6472         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6473         intel_dp->attached_connector = intel_connector;
6474
6475         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6476                 /*
6477                  * Currently we don't support eDP on TypeC ports, although in
6478                  * theory it could work on TypeC legacy ports.
6479                  */
6480                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6481                 type = DRM_MODE_CONNECTOR_eDP;
6482                 intel_encoder->type = INTEL_OUTPUT_EDP;
6483
6484                 /* eDP only on port B and/or C on vlv/chv */
6485                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6486                                       IS_CHERRYVIEW(dev_priv)) &&
6487                                 port != PORT_B && port != PORT_C))
6488                         return false;
6489         } else {
6490                 type = DRM_MODE_CONNECTOR_DisplayPort;
6491         }
6492
6493         intel_dp_set_default_sink_rates(intel_dp);
6494         intel_dp_set_default_max_sink_lane_count(intel_dp);
6495
6496         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6497                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6498
6499         intel_dp_aux_init(intel_dp);
6500         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6501
6502         drm_dbg_kms(&dev_priv->drm,
6503                     "Adding %s connector on [ENCODER:%d:%s]\n",
6504                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6505                     intel_encoder->base.base.id, intel_encoder->base.name);
6506
6507         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6508                                     type, &intel_dp->aux.ddc);
6509         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6510
6511         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6512                 connector->interlace_allowed = true;
6513
6514         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6515         intel_connector->base.polled = intel_connector->polled;
6516
6517         intel_connector_attach_encoder(intel_connector, intel_encoder);
6518
6519         if (HAS_DDI(dev_priv))
6520                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6521         else
6522                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6523
6524         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6525                 intel_dp_aux_fini(intel_dp);
6526                 goto fail;
6527         }
6528
6529         intel_dp_set_source_rates(intel_dp);
6530         intel_dp_set_common_rates(intel_dp);
6531         intel_dp_reset_max_link_params(intel_dp);
6532
6533         /* init MST on ports that can support it */
6534         intel_dp_mst_encoder_init(dig_port,
6535                                   intel_connector->base.base.id);
6536
6537         intel_dp_add_properties(intel_dp, connector);
6538
6539         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6540                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6541                 if (ret)
6542                         drm_dbg_kms(&dev_priv->drm,
6543                                     "HDCP init failed, skipping.\n");
6544         }
6545
6546         intel_dp->colorimetry_support =
6547                 intel_dp_get_colorimetry_status(intel_dp);
6548
6549         intel_dp->frl.is_trained = false;
6550         intel_dp->frl.trained_rate_gbps = 0;
6551
6552         intel_psr_init(intel_dp);
6553
6554         return true;
6555
6556 fail:
6557         intel_display_power_flush_work(dev_priv);
6558         drm_connector_cleanup(connector);
6559
6560         return false;
6561 }
6562
6563 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6564 {
6565         struct intel_encoder *encoder;
6566
6567         if (!HAS_DISPLAY(dev_priv))
6568                 return;
6569
6570         for_each_intel_encoder(&dev_priv->drm, encoder) {
6571                 struct intel_dp *intel_dp;
6572
6573                 if (encoder->type != INTEL_OUTPUT_DDI)
6574                         continue;
6575
6576                 intel_dp = enc_to_intel_dp(encoder);
6577
6578                 if (!intel_dp_mst_source_support(intel_dp))
6579                         continue;
6580
6581                 if (intel_dp->is_mst)
6582                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6583         }
6584 }
6585
6586 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6587 {
6588         struct intel_encoder *encoder;
6589
6590         if (!HAS_DISPLAY(dev_priv))
6591                 return;
6592
6593         for_each_intel_encoder(&dev_priv->drm, encoder) {
6594                 struct intel_dp *intel_dp;
6595                 int ret;
6596
6597                 if (encoder->type != INTEL_OUTPUT_DDI)
6598                         continue;
6599
6600                 intel_dp = enc_to_intel_dp(encoder);
6601
6602                 if (!intel_dp_mst_source_support(intel_dp))
6603                         continue;
6604
6605                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6606                                                      true);
6607                 if (ret) {
6608                         intel_dp->is_mst = false;
6609                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6610                                                         false);
6611                 }
6612         }
6613 }