2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/string_helpers.h>
33 #include <linux/timekeeping.h>
34 #include <linux/types.h>
36 #include <asm/byteorder.h>
38 #include <drm/display/drm_dp_helper.h>
39 #include <drm/display/drm_dsc_helper.h>
40 #include <drm/display/drm_hdmi_helper.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_probe_helper.h>
47 #include "i915_debugfs.h"
49 #include "intel_atomic.h"
50 #include "intel_audio.h"
51 #include "intel_backlight.h"
52 #include "intel_combo_phy_regs.h"
53 #include "intel_connector.h"
54 #include "intel_crtc.h"
55 #include "intel_ddi.h"
57 #include "intel_display_types.h"
59 #include "intel_dp_aux.h"
60 #include "intel_dp_hdcp.h"
61 #include "intel_dp_link_training.h"
62 #include "intel_dp_mst.h"
63 #include "intel_dpio_phy.h"
64 #include "intel_dpll.h"
65 #include "intel_fifo_underrun.h"
66 #include "intel_hdcp.h"
67 #include "intel_hdmi.h"
68 #include "intel_hotplug.h"
69 #include "intel_lspcon.h"
70 #include "intel_lvds.h"
71 #include "intel_panel.h"
72 #include "intel_pch_display.h"
73 #include "intel_pps.h"
74 #include "intel_psr.h"
76 #include "intel_vdsc.h"
77 #include "intel_vrr.h"
79 /* DP DSC throughput values used for slice count calculations KPixels/s */
80 #define DP_DSC_PEAK_PIXEL_RATE 2720000
81 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
82 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
84 /* DP DSC FEC Overhead factor = 1/(0.972261) */
85 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
87 /* Compliance test status bits */
88 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
89 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
90 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
91 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
94 /* Constants for DP DSC configurations */
95 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
97 /* With Single pipe configuration, HW is capable of supporting maximum
98 * of 4 slices per line.
100 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
103 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104 * @intel_dp: DP struct
106 * If a CPU or PCH DP output is attached to an eDP panel, this function
107 * will return true, and false otherwise.
109 * This function is not safe to use prior to encoder type being set.
111 bool intel_dp_is_edp(struct intel_dp *intel_dp)
113 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
115 return dig_port->base.type == INTEL_OUTPUT_EDP;
118 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
119 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
121 /* Is link rate UHBR and thus 128b/132b? */
122 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
124 return crtc_state->port_clock >= 1000000;
127 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
129 intel_dp->sink_rates[0] = 162000;
130 intel_dp->num_sink_rates = 1;
133 /* update sink rates from dpcd */
134 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
136 static const int dp_rates[] = {
137 162000, 270000, 540000, 810000
142 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
143 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
144 static const int quirk_rates[] = { 162000, 270000, 324000 };
146 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
147 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
153 * Sink rates for 8b/10b.
155 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
156 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
158 max_rate = min(max_rate, max_lttpr_rate);
160 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
161 if (dp_rates[i] > max_rate)
163 intel_dp->sink_rates[i] = dp_rates[i];
167 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
170 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
173 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
175 drm_dp_dpcd_readb(&intel_dp->aux,
176 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
178 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
179 /* We have a repeater */
180 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
181 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
182 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
183 DP_PHY_REPEATER_128B132B_SUPPORTED) {
184 /* Repeater supports 128b/132b, valid UHBR rates */
185 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
186 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
188 /* Does not support 128b/132b */
193 if (uhbr_rates & DP_UHBR10)
194 intel_dp->sink_rates[i++] = 1000000;
195 if (uhbr_rates & DP_UHBR13_5)
196 intel_dp->sink_rates[i++] = 1350000;
197 if (uhbr_rates & DP_UHBR20)
198 intel_dp->sink_rates[i++] = 2000000;
201 intel_dp->num_sink_rates = i;
204 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
206 struct intel_connector *connector = intel_dp->attached_connector;
207 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
208 struct intel_encoder *encoder = &intel_dig_port->base;
210 intel_dp_set_dpcd_sink_rates(intel_dp);
212 if (intel_dp->num_sink_rates)
215 drm_err(&dp_to_i915(intel_dp)->drm,
216 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
217 connector->base.base.id, connector->base.name,
218 encoder->base.base.id, encoder->base.name);
220 intel_dp_set_default_sink_rates(intel_dp);
223 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
225 intel_dp->max_sink_lane_count = 1;
228 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
230 struct intel_connector *connector = intel_dp->attached_connector;
231 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
232 struct intel_encoder *encoder = &intel_dig_port->base;
234 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
236 switch (intel_dp->max_sink_lane_count) {
243 drm_err(&dp_to_i915(intel_dp)->drm,
244 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
245 connector->base.base.id, connector->base.name,
246 encoder->base.base.id, encoder->base.name,
247 intel_dp->max_sink_lane_count);
249 intel_dp_set_default_max_sink_lane_count(intel_dp);
252 /* Get length of rates array potentially limited by max_rate. */
253 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
257 /* Limit results by potentially reduced max rate */
258 for (i = 0; i < len; i++) {
259 if (rates[len - i - 1] <= max_rate)
266 /* Get length of common rates array potentially limited by max_rate. */
267 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
270 return intel_dp_rate_limit_len(intel_dp->common_rates,
271 intel_dp->num_common_rates, max_rate);
274 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
276 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
277 index < 0 || index >= intel_dp->num_common_rates))
280 return intel_dp->common_rates[index];
283 /* Theoretical max between source and sink */
284 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
286 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
289 /* Theoretical max between source and sink */
290 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
292 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
293 int source_max = dig_port->max_lanes;
294 int sink_max = intel_dp->max_sink_lane_count;
295 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
296 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
299 sink_max = min(sink_max, lttpr_max);
301 return min3(source_max, sink_max, fia_max);
304 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
306 switch (intel_dp->max_link_lane_count) {
310 return intel_dp->max_link_lane_count;
312 MISSING_CASE(intel_dp->max_link_lane_count);
318 * The required data bandwidth for a mode with given pixel clock and bpp. This
319 * is the required net bandwidth independent of the data bandwidth efficiency.
322 intel_dp_link_required(int pixel_clock, int bpp)
324 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
325 return DIV_ROUND_UP(pixel_clock * bpp, 8);
329 * Given a link rate and lanes, get the data bandwidth.
331 * Data bandwidth is the actual payload rate, which depends on the data
332 * bandwidth efficiency and the link rate.
334 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
335 * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
336 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
337 * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
338 * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
339 * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
341 * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
342 * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
343 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
344 * does not match the symbol clock, the port clock (not even if you think in
345 * terms of a byte clock), nor the data bandwidth. It only matches the link bit
346 * rate in units of 10000 bps.
349 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
351 if (max_link_rate >= 1000000) {
353 * UHBR rates always use 128b/132b channel encoding, and have
354 * 97.71% data bandwidth efficiency. Consider max_link_rate the
355 * link bit rate in units of 10000 bps.
357 int max_link_rate_kbps = max_link_rate * 10;
359 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
360 max_link_rate = max_link_rate_kbps / 8;
364 * Lower than UHBR rates always use 8b/10b channel encoding, and have
365 * 80% data bandwidth efficiency for SST non-FEC. However, this turns
366 * out to be a nop by coincidence, and can be skipped:
368 * int max_link_rate_kbps = max_link_rate * 10;
369 * max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
370 * max_link_rate = max_link_rate_kbps / 8;
373 return max_link_rate * max_lanes;
376 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
378 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
379 struct intel_encoder *encoder = &intel_dig_port->base;
380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
382 return DISPLAY_VER(dev_priv) >= 12 ||
383 (DISPLAY_VER(dev_priv) == 11 &&
384 encoder->port != PORT_A);
387 static int dg2_max_source_rate(struct intel_dp *intel_dp)
389 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
392 static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
396 voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
398 return voltage == VOLTAGE_INFO_0_85V;
401 static int icl_max_source_rate(struct intel_dp *intel_dp)
403 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
404 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
405 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
407 if (intel_phy_is_combo(dev_priv, phy) &&
408 (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
414 static int ehl_max_source_rate(struct intel_dp *intel_dp)
416 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
417 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
418 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
420 if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
426 static int dg1_max_source_rate(struct intel_dp *intel_dp)
428 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
429 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
430 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
432 if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
438 static int vbt_max_link_rate(struct intel_dp *intel_dp)
440 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
443 max_rate = intel_bios_dp_max_link_rate(encoder);
445 if (intel_dp_is_edp(intel_dp)) {
446 struct intel_connector *connector = intel_dp->attached_connector;
447 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
449 if (max_rate && edp_max_rate)
450 max_rate = min(max_rate, edp_max_rate);
451 else if (edp_max_rate)
452 max_rate = edp_max_rate;
459 intel_dp_set_source_rates(struct intel_dp *intel_dp)
461 /* The values must be in increasing order */
462 static const int icl_rates[] = {
463 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
466 static const int bxt_rates[] = {
467 162000, 216000, 243000, 270000, 324000, 432000, 540000
469 static const int skl_rates[] = {
470 162000, 216000, 270000, 324000, 432000, 540000
472 static const int hsw_rates[] = {
473 162000, 270000, 540000
475 static const int g4x_rates[] = {
478 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
479 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
480 const int *source_rates;
481 int size, max_rate = 0, vbt_max_rate;
483 /* This should only be done once */
484 drm_WARN_ON(&dev_priv->drm,
485 intel_dp->source_rates || intel_dp->num_source_rates);
487 if (DISPLAY_VER(dev_priv) >= 11) {
488 source_rates = icl_rates;
489 size = ARRAY_SIZE(icl_rates);
490 if (IS_DG2(dev_priv))
491 max_rate = dg2_max_source_rate(intel_dp);
492 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
493 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
494 max_rate = dg1_max_source_rate(intel_dp);
495 else if (IS_JSL_EHL(dev_priv))
496 max_rate = ehl_max_source_rate(intel_dp);
498 max_rate = icl_max_source_rate(intel_dp);
499 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
500 source_rates = bxt_rates;
501 size = ARRAY_SIZE(bxt_rates);
502 } else if (DISPLAY_VER(dev_priv) == 9) {
503 source_rates = skl_rates;
504 size = ARRAY_SIZE(skl_rates);
505 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
506 IS_BROADWELL(dev_priv)) {
507 source_rates = hsw_rates;
508 size = ARRAY_SIZE(hsw_rates);
510 source_rates = g4x_rates;
511 size = ARRAY_SIZE(g4x_rates);
514 vbt_max_rate = vbt_max_link_rate(intel_dp);
515 if (max_rate && vbt_max_rate)
516 max_rate = min(max_rate, vbt_max_rate);
517 else if (vbt_max_rate)
518 max_rate = vbt_max_rate;
521 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
523 intel_dp->source_rates = source_rates;
524 intel_dp->num_source_rates = size;
527 static int intersect_rates(const int *source_rates, int source_len,
528 const int *sink_rates, int sink_len,
531 int i = 0, j = 0, k = 0;
533 while (i < source_len && j < sink_len) {
534 if (source_rates[i] == sink_rates[j]) {
535 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
537 common_rates[k] = source_rates[i];
541 } else if (source_rates[i] < sink_rates[j]) {
550 /* return index of rate in rates array, or -1 if not found */
551 static int intel_dp_rate_index(const int *rates, int len, int rate)
555 for (i = 0; i < len; i++)
556 if (rate == rates[i])
562 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
564 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
566 drm_WARN_ON(&i915->drm,
567 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
569 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
570 intel_dp->num_source_rates,
571 intel_dp->sink_rates,
572 intel_dp->num_sink_rates,
573 intel_dp->common_rates);
575 /* Paranoia, there should always be something in common. */
576 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
577 intel_dp->common_rates[0] = 162000;
578 intel_dp->num_common_rates = 1;
582 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
586 * FIXME: we need to synchronize the current link parameters with
587 * hardware readout. Currently fast link training doesn't work on
590 if (link_rate == 0 ||
591 link_rate > intel_dp->max_link_rate)
594 if (lane_count == 0 ||
595 lane_count > intel_dp_max_lane_count(intel_dp))
601 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
605 /* FIXME figure out what we actually want here */
606 const struct drm_display_mode *fixed_mode =
607 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
608 int mode_rate, max_rate;
610 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
611 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
612 if (mode_rate > max_rate)
618 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
619 int link_rate, u8 lane_count)
621 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
625 * TODO: Enable fallback on MST links once MST link compute can handle
626 * the fallback params.
628 if (intel_dp->is_mst) {
629 drm_err(&i915->drm, "Link Training Unsuccessful\n");
633 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
634 drm_dbg_kms(&i915->drm,
635 "Retrying Link training for eDP with max parameters\n");
636 intel_dp->use_max_params = true;
640 index = intel_dp_rate_index(intel_dp->common_rates,
641 intel_dp->num_common_rates,
644 if (intel_dp_is_edp(intel_dp) &&
645 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
646 intel_dp_common_rate(intel_dp, index - 1),
648 drm_dbg_kms(&i915->drm,
649 "Retrying Link training for eDP with same parameters\n");
652 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
653 intel_dp->max_link_lane_count = lane_count;
654 } else if (lane_count > 1) {
655 if (intel_dp_is_edp(intel_dp) &&
656 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
657 intel_dp_max_common_rate(intel_dp),
659 drm_dbg_kms(&i915->drm,
660 "Retrying Link training for eDP with same parameters\n");
663 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
664 intel_dp->max_link_lane_count = lane_count >> 1;
666 drm_err(&i915->drm, "Link Training Unsuccessful\n");
673 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
675 return div_u64(mul_u32_u32(mode_clock, 1000000U),
676 DP_DSC_FEC_OVERHEAD_FACTOR);
680 small_joiner_ram_size_bits(struct drm_i915_private *i915)
682 if (DISPLAY_VER(i915) >= 13)
684 else if (DISPLAY_VER(i915) >= 11)
690 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
691 u32 link_clock, u32 lane_count,
692 u32 mode_clock, u32 mode_hdisplay,
696 u32 bits_per_pixel, max_bpp_small_joiner_ram;
700 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
701 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
702 * for SST -> TimeSlotsPerMTP is 1,
703 * for MST -> TimeSlotsPerMTP has to be calculated
705 bits_per_pixel = (link_clock * lane_count * 8) /
706 intel_dp_mode_to_fec_clock(mode_clock);
708 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
709 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
713 max_bpp_small_joiner_ram *= 2;
716 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
717 * check, output bpp from small joiner RAM check)
719 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
722 u32 max_bpp_bigjoiner =
723 i915->max_cdclk_freq * 48 /
724 intel_dp_mode_to_fec_clock(mode_clock);
726 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
729 /* Error out if the max bpp is less than smallest allowed valid bpp */
730 if (bits_per_pixel < valid_dsc_bpp[0]) {
731 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
732 bits_per_pixel, valid_dsc_bpp[0]);
736 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
737 if (DISPLAY_VER(i915) >= 13) {
738 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
740 /* Find the nearest match in the array of known BPPs from VESA */
741 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
742 if (bits_per_pixel < valid_dsc_bpp[i + 1])
745 bits_per_pixel = valid_dsc_bpp[i];
749 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
750 * fractional part is 0
752 return bits_per_pixel << 4;
755 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
756 int mode_clock, int mode_hdisplay,
759 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
760 u8 min_slice_count, i;
763 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
764 min_slice_count = DIV_ROUND_UP(mode_clock,
765 DP_DSC_MAX_ENC_THROUGHPUT_0);
767 min_slice_count = DIV_ROUND_UP(mode_clock,
768 DP_DSC_MAX_ENC_THROUGHPUT_1);
770 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
771 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
772 drm_dbg_kms(&i915->drm,
773 "Unsupported slice width %d by DP DSC Sink device\n",
777 /* Also take into account max slice width */
778 min_slice_count = max_t(u8, min_slice_count,
779 DIV_ROUND_UP(mode_hdisplay,
782 /* Find the closest match to the valid slice count values */
783 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
784 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
786 if (test_slice_count >
787 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
790 /* big joiner needs small joiner to be enabled */
791 if (bigjoiner && test_slice_count < 4)
794 if (min_slice_count <= test_slice_count)
795 return test_slice_count;
798 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
803 static enum intel_output_format
804 intel_dp_output_format(struct intel_connector *connector,
805 bool ycbcr_420_output)
807 struct intel_dp *intel_dp = intel_attached_dp(connector);
809 if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
810 return INTEL_OUTPUT_FORMAT_RGB;
812 if (intel_dp->dfp.rgb_to_ycbcr &&
813 intel_dp->dfp.ycbcr_444_to_420)
814 return INTEL_OUTPUT_FORMAT_RGB;
816 if (intel_dp->dfp.ycbcr_444_to_420)
817 return INTEL_OUTPUT_FORMAT_YCBCR444;
819 return INTEL_OUTPUT_FORMAT_YCBCR420;
822 int intel_dp_min_bpp(enum intel_output_format output_format)
824 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
830 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
833 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
834 * format of the number of bytes per pixel will be half the number
835 * of bytes of RGB pixel.
837 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
844 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
845 const struct drm_display_mode *mode)
847 const struct drm_display_info *info = &connector->base.display_info;
848 enum intel_output_format output_format =
849 intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
851 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
854 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
858 * Older platforms don't like hdisplay==4096 with DP.
860 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
861 * and frame counter increment), but we don't get vblank interrupts,
862 * and the pipe underruns immediately. The link also doesn't seem
863 * to get trained properly.
865 * On CHV the vblank interrupts don't seem to disappear but
866 * otherwise the symptoms are similar.
868 * TODO: confirm the behaviour on HSW+
870 return hdisplay == 4096 && !HAS_DDI(dev_priv);
873 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
875 struct intel_connector *connector = intel_dp->attached_connector;
876 const struct drm_display_info *info = &connector->base.display_info;
877 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
879 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
880 if (max_tmds_clock && info->max_tmds_clock)
881 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
883 return max_tmds_clock;
886 static enum drm_mode_status
887 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
888 int clock, int bpc, bool ycbcr420_output,
889 bool respect_downstream_limits)
891 int tmds_clock, min_tmds_clock, max_tmds_clock;
893 if (!respect_downstream_limits)
896 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
898 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
899 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
901 if (min_tmds_clock && tmds_clock < min_tmds_clock)
902 return MODE_CLOCK_LOW;
904 if (max_tmds_clock && tmds_clock > max_tmds_clock)
905 return MODE_CLOCK_HIGH;
910 static enum drm_mode_status
911 intel_dp_mode_valid_downstream(struct intel_connector *connector,
912 const struct drm_display_mode *mode,
915 struct intel_dp *intel_dp = intel_attached_dp(connector);
916 const struct drm_display_info *info = &connector->base.display_info;
917 enum drm_mode_status status;
920 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
921 if (intel_dp->dfp.pcon_max_frl_bw) {
924 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
926 target_bw = bpp * target_clock;
928 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
930 /* converting bw from Gbps to Kbps*/
931 max_frl_bw = max_frl_bw * 1000000;
933 if (target_bw > max_frl_bw)
934 return MODE_CLOCK_HIGH;
939 if (intel_dp->dfp.max_dotclock &&
940 target_clock > intel_dp->dfp.max_dotclock)
941 return MODE_CLOCK_HIGH;
943 ycbcr_420_only = drm_mode_is_420_only(info, mode);
945 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
946 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
947 8, ycbcr_420_only, true);
949 if (status != MODE_OK) {
950 if (ycbcr_420_only ||
951 !connector->base.ycbcr_420_allowed ||
952 !drm_mode_is_420_also(info, mode))
955 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
957 if (status != MODE_OK)
964 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
965 int hdisplay, int clock)
967 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
969 if (!intel_dp_can_bigjoiner(intel_dp))
972 return clock > i915->max_dotclk_freq || hdisplay > 5120;
975 static enum drm_mode_status
976 intel_dp_mode_valid(struct drm_connector *_connector,
977 struct drm_display_mode *mode)
979 struct intel_connector *connector = to_intel_connector(_connector);
980 struct intel_dp *intel_dp = intel_attached_dp(connector);
981 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
982 const struct drm_display_mode *fixed_mode;
983 int target_clock = mode->clock;
984 int max_rate, mode_rate, max_lanes, max_link_clock;
985 int max_dotclk = dev_priv->max_dotclk_freq;
986 u16 dsc_max_output_bpp = 0;
987 u8 dsc_slice_count = 0;
988 enum drm_mode_status status;
989 bool dsc = false, bigjoiner = false;
991 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
992 return MODE_NO_DBLESCAN;
994 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
995 return MODE_H_ILLEGAL;
997 fixed_mode = intel_panel_fixed_mode(connector, mode);
998 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
999 status = intel_panel_mode_valid(connector, mode);
1000 if (status != MODE_OK)
1003 target_clock = fixed_mode->clock;
1006 if (mode->clock < 10000)
1007 return MODE_CLOCK_LOW;
1009 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1013 if (target_clock > max_dotclk)
1014 return MODE_CLOCK_HIGH;
1016 max_link_clock = intel_dp_max_link_rate(intel_dp);
1017 max_lanes = intel_dp_max_lane_count(intel_dp);
1019 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1020 mode_rate = intel_dp_link_required(target_clock,
1021 intel_dp_mode_min_output_bpp(connector, mode));
1023 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1024 return MODE_H_ILLEGAL;
1027 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1028 * integer value since we support only integer values of bpp.
1030 if (DISPLAY_VER(dev_priv) >= 10 &&
1031 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1033 * TBD pass the connector BPC,
1034 * for now U8_MAX so that max BPC on that platform would be picked
1036 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1038 if (intel_dp_is_edp(intel_dp)) {
1039 dsc_max_output_bpp =
1040 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1042 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1044 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1045 dsc_max_output_bpp =
1046 intel_dp_dsc_get_output_bpp(dev_priv,
1054 intel_dp_dsc_get_slice_count(intel_dp,
1060 dsc = dsc_max_output_bpp && dsc_slice_count;
1064 * Big joiner configuration needs DSC for TGL which is not true for
1065 * XE_LPD where uncompressed joiner is supported.
1067 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1068 return MODE_CLOCK_HIGH;
1070 if (mode_rate > max_rate && !dsc)
1071 return MODE_CLOCK_HIGH;
1073 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1074 if (status != MODE_OK)
1077 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1080 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1082 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1085 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1087 return DISPLAY_VER(i915) >= 10;
1090 static void snprintf_int_array(char *str, size_t len,
1091 const int *array, int nelem)
1097 for (i = 0; i < nelem; i++) {
1098 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1106 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1108 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1109 char str[128]; /* FIXME: too big for stack? */
1111 if (!drm_debug_enabled(DRM_UT_KMS))
1114 snprintf_int_array(str, sizeof(str),
1115 intel_dp->source_rates, intel_dp->num_source_rates);
1116 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1118 snprintf_int_array(str, sizeof(str),
1119 intel_dp->sink_rates, intel_dp->num_sink_rates);
1120 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1122 snprintf_int_array(str, sizeof(str),
1123 intel_dp->common_rates, intel_dp->num_common_rates);
1124 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1128 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1132 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1134 return intel_dp_common_rate(intel_dp, len - 1);
1137 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1139 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1140 int i = intel_dp_rate_index(intel_dp->sink_rates,
1141 intel_dp->num_sink_rates, rate);
1143 if (drm_WARN_ON(&i915->drm, i < 0))
1149 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1150 u8 *link_bw, u8 *rate_select)
1152 /* eDP 1.4 rate select method. */
1153 if (intel_dp->use_rate_select) {
1156 intel_dp_rate_select(intel_dp, port_clock);
1158 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1163 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1164 const struct intel_crtc_state *pipe_config)
1166 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1168 /* On TGL, FEC is supported on all Pipes */
1169 if (DISPLAY_VER(dev_priv) >= 12)
1172 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1178 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1179 const struct intel_crtc_state *pipe_config)
1181 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1182 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1185 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1186 const struct intel_crtc_state *crtc_state)
1188 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1191 return intel_dsc_source_support(crtc_state) &&
1192 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1195 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1196 const struct intel_crtc_state *crtc_state)
1198 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1199 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1200 intel_dp->dfp.ycbcr_444_to_420);
1203 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1204 const struct intel_crtc_state *crtc_state,
1205 int bpc, bool respect_downstream_limits)
1207 bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1208 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1211 * Current bpc could already be below 8bpc due to
1212 * FDI bandwidth constraints or other limits.
1213 * HDMI minimum is 8bpc however.
1218 * We will never exceed downstream TMDS clock limits while
1219 * attempting deep color. If the user insists on forcing an
1220 * out of spec mode they will have to be satisfied with 8bpc.
1222 if (!respect_downstream_limits)
1225 for (; bpc >= 8; bpc -= 2) {
1226 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1227 intel_dp->has_hdmi_sink, ycbcr420_output) &&
1228 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1229 respect_downstream_limits) == MODE_OK)
1236 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1237 const struct intel_crtc_state *crtc_state,
1238 bool respect_downstream_limits)
1240 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1241 struct intel_connector *intel_connector = intel_dp->attached_connector;
1244 bpc = crtc_state->pipe_bpp / 3;
1246 if (intel_dp->dfp.max_bpc)
1247 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1249 if (intel_dp->dfp.min_tmds_clock) {
1252 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1253 respect_downstream_limits);
1254 if (max_hdmi_bpc < 0)
1257 bpc = min(bpc, max_hdmi_bpc);
1261 if (intel_dp_is_edp(intel_dp)) {
1262 /* Get bpp from vbt only for panels that dont have bpp in edid */
1263 if (intel_connector->base.display_info.bpc == 0 &&
1264 intel_connector->panel.vbt.edp.bpp &&
1265 intel_connector->panel.vbt.edp.bpp < bpp) {
1266 drm_dbg_kms(&dev_priv->drm,
1267 "clamping bpp for eDP panel to BIOS-provided %i\n",
1268 intel_connector->panel.vbt.edp.bpp);
1269 bpp = intel_connector->panel.vbt.edp.bpp;
1276 /* Adjust link config limits based on compliance test requests. */
1278 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1279 struct intel_crtc_state *pipe_config,
1280 struct link_config_limits *limits)
1282 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1284 /* For DP Compliance we override the computed bpp for the pipe */
1285 if (intel_dp->compliance.test_data.bpc != 0) {
1286 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1288 limits->min_bpp = limits->max_bpp = bpp;
1289 pipe_config->dither_force_disable = bpp == 6 * 3;
1291 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1294 /* Use values requested by Compliance Test Request */
1295 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1298 /* Validate the compliance test data since max values
1299 * might have changed due to link train fallback.
1301 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1302 intel_dp->compliance.test_lane_count)) {
1303 index = intel_dp_rate_index(intel_dp->common_rates,
1304 intel_dp->num_common_rates,
1305 intel_dp->compliance.test_link_rate);
1307 limits->min_rate = limits->max_rate =
1308 intel_dp->compliance.test_link_rate;
1309 limits->min_lane_count = limits->max_lane_count =
1310 intel_dp->compliance.test_lane_count;
1315 /* Optimize link config in order: max bpp, min clock, min lanes */
1317 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1318 struct intel_crtc_state *pipe_config,
1319 const struct link_config_limits *limits)
1321 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1322 int bpp, i, lane_count;
1323 int mode_rate, link_rate, link_avail;
1325 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1326 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1328 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1331 for (i = 0; i < intel_dp->num_common_rates; i++) {
1332 link_rate = intel_dp_common_rate(intel_dp, i);
1333 if (link_rate < limits->min_rate ||
1334 link_rate > limits->max_rate)
1337 for (lane_count = limits->min_lane_count;
1338 lane_count <= limits->max_lane_count;
1340 link_avail = intel_dp_max_data_rate(link_rate,
1343 if (mode_rate <= link_avail) {
1344 pipe_config->lane_count = lane_count;
1345 pipe_config->pipe_bpp = bpp;
1346 pipe_config->port_clock = link_rate;
1357 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1359 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1361 u8 dsc_bpc[3] = {0};
1364 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1365 if (DISPLAY_VER(i915) >= 12)
1366 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1368 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1370 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1372 for (i = 0; i < num_bpc; i++) {
1373 if (dsc_max_bpc >= dsc_bpc[i])
1374 return dsc_bpc[i] * 3;
1380 #define DSC_SUPPORTED_VERSION_MIN 1
1382 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1383 struct intel_crtc_state *crtc_state)
1385 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1386 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1387 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1392 * RC_MODEL_SIZE is currently a constant across all configurations.
1394 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1395 * DP_DSC_RC_BUF_SIZE for this.
1397 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1400 * Slice Height of 8 works for all currently available panels. So start
1401 * with that if pic_height is an integral multiple of 8. Eventually add
1402 * logic to try multiple slice heights.
1404 if (vdsc_cfg->pic_height % 8 == 0)
1405 vdsc_cfg->slice_height = 8;
1406 else if (vdsc_cfg->pic_height % 4 == 0)
1407 vdsc_cfg->slice_height = 4;
1409 vdsc_cfg->slice_height = 2;
1411 ret = intel_dsc_compute_params(crtc_state);
1415 vdsc_cfg->dsc_version_major =
1416 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1417 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1418 vdsc_cfg->dsc_version_minor =
1419 min(DSC_SUPPORTED_VERSION_MIN,
1420 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1421 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1423 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1426 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1427 if (!line_buf_depth) {
1428 drm_dbg_kms(&i915->drm,
1429 "DSC Sink Line Buffer Depth invalid\n");
1433 if (vdsc_cfg->dsc_version_minor == 2)
1434 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1435 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1437 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1438 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1440 vdsc_cfg->block_pred_enable =
1441 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1442 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1444 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1447 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1448 struct intel_crtc_state *pipe_config,
1449 struct drm_connector_state *conn_state,
1450 struct link_config_limits *limits)
1452 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1453 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1454 const struct drm_display_mode *adjusted_mode =
1455 &pipe_config->hw.adjusted_mode;
1459 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1460 intel_dp_supports_fec(intel_dp, pipe_config);
1462 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1465 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1467 /* Min Input BPC for ICL+ is 8 */
1468 if (pipe_bpp < 8 * 3) {
1469 drm_dbg_kms(&dev_priv->drm,
1470 "No DSC support for less than 8bpc\n");
1475 * For now enable DSC for max bpp, max link rate, max lane count.
1476 * Optimize this later for the minimum possible link rate/lane count
1477 * with DSC enabled for the requested mode.
1479 pipe_config->pipe_bpp = pipe_bpp;
1480 pipe_config->port_clock = limits->max_rate;
1481 pipe_config->lane_count = limits->max_lane_count;
1483 if (intel_dp_is_edp(intel_dp)) {
1484 pipe_config->dsc.compressed_bpp =
1485 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1486 pipe_config->pipe_bpp);
1487 pipe_config->dsc.slice_count =
1488 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1491 u16 dsc_max_output_bpp;
1492 u8 dsc_dp_slice_count;
1494 dsc_max_output_bpp =
1495 intel_dp_dsc_get_output_bpp(dev_priv,
1496 pipe_config->port_clock,
1497 pipe_config->lane_count,
1498 adjusted_mode->crtc_clock,
1499 adjusted_mode->crtc_hdisplay,
1500 pipe_config->bigjoiner_pipes,
1502 dsc_dp_slice_count =
1503 intel_dp_dsc_get_slice_count(intel_dp,
1504 adjusted_mode->crtc_clock,
1505 adjusted_mode->crtc_hdisplay,
1506 pipe_config->bigjoiner_pipes);
1507 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1508 drm_dbg_kms(&dev_priv->drm,
1509 "Compressed BPP/Slice Count not supported\n");
1512 pipe_config->dsc.compressed_bpp = min_t(u16,
1513 dsc_max_output_bpp >> 4,
1514 pipe_config->pipe_bpp);
1515 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1518 /* As of today we support DSC for only RGB */
1519 if (intel_dp->force_dsc_bpp) {
1520 if (intel_dp->force_dsc_bpp >= 8 &&
1521 intel_dp->force_dsc_bpp < pipe_bpp) {
1522 drm_dbg_kms(&dev_priv->drm,
1523 "DSC BPP forced to %d",
1524 intel_dp->force_dsc_bpp);
1525 pipe_config->dsc.compressed_bpp =
1526 intel_dp->force_dsc_bpp;
1528 drm_dbg_kms(&dev_priv->drm,
1529 "Invalid DSC BPP %d",
1530 intel_dp->force_dsc_bpp);
1535 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1536 * is greater than the maximum Cdclock and if slice count is even
1537 * then we need to use 2 VDSC instances.
1539 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1540 pipe_config->bigjoiner_pipes) {
1541 if (pipe_config->dsc.slice_count < 2) {
1542 drm_dbg_kms(&dev_priv->drm,
1543 "Cannot split stream to use 2 VDSC instances\n");
1547 pipe_config->dsc.dsc_split = true;
1550 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1552 drm_dbg_kms(&dev_priv->drm,
1553 "Cannot compute valid DSC parameters for Input Bpp = %d "
1554 "Compressed BPP = %d\n",
1555 pipe_config->pipe_bpp,
1556 pipe_config->dsc.compressed_bpp);
1560 pipe_config->dsc.compression_enable = true;
1561 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1562 "Compressed Bpp = %d Slice Count = %d\n",
1563 pipe_config->pipe_bpp,
1564 pipe_config->dsc.compressed_bpp,
1565 pipe_config->dsc.slice_count);
1571 intel_dp_compute_link_config(struct intel_encoder *encoder,
1572 struct intel_crtc_state *pipe_config,
1573 struct drm_connector_state *conn_state,
1574 bool respect_downstream_limits)
1576 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1577 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1578 const struct drm_display_mode *adjusted_mode =
1579 &pipe_config->hw.adjusted_mode;
1580 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1581 struct link_config_limits limits;
1582 bool joiner_needs_dsc = false;
1585 limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1586 limits.max_rate = intel_dp_max_link_rate(intel_dp);
1588 limits.min_lane_count = 1;
1589 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1591 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1592 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1594 if (intel_dp->use_max_params) {
1596 * Use the maximum clock and number of lanes the eDP panel
1597 * advertizes being capable of in case the initial fast
1598 * optimal params failed us. The panels are generally
1599 * designed to support only a single clock and lane
1600 * configuration, and typically on older panels these
1601 * values correspond to the native resolution of the panel.
1603 limits.min_lane_count = limits.max_lane_count;
1604 limits.min_rate = limits.max_rate;
1607 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1609 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1610 "max rate %d max bpp %d pixel clock %iKHz\n",
1611 limits.max_lane_count, limits.max_rate,
1612 limits.max_bpp, adjusted_mode->crtc_clock);
1614 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1615 adjusted_mode->crtc_clock))
1616 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1619 * Pipe joiner needs compression up to display 12 due to bandwidth
1620 * limitation. DG2 onwards pipe joiner can be enabled without
1623 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1626 * Optimize for slow and wide for everything, because there are some
1627 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1629 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1631 if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1632 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1633 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1634 str_yes_no(intel_dp->force_dsc_en));
1635 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1636 conn_state, &limits);
1641 if (pipe_config->dsc.compression_enable) {
1642 drm_dbg_kms(&i915->drm,
1643 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1644 pipe_config->lane_count, pipe_config->port_clock,
1645 pipe_config->pipe_bpp,
1646 pipe_config->dsc.compressed_bpp);
1648 drm_dbg_kms(&i915->drm,
1649 "DP link rate required %i available %i\n",
1650 intel_dp_link_required(adjusted_mode->crtc_clock,
1651 pipe_config->dsc.compressed_bpp),
1652 intel_dp_max_data_rate(pipe_config->port_clock,
1653 pipe_config->lane_count));
1655 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1656 pipe_config->lane_count, pipe_config->port_clock,
1657 pipe_config->pipe_bpp);
1659 drm_dbg_kms(&i915->drm,
1660 "DP link rate required %i available %i\n",
1661 intel_dp_link_required(adjusted_mode->crtc_clock,
1662 pipe_config->pipe_bpp),
1663 intel_dp_max_data_rate(pipe_config->port_clock,
1664 pipe_config->lane_count));
1669 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1670 const struct drm_connector_state *conn_state)
1672 const struct intel_digital_connector_state *intel_conn_state =
1673 to_intel_digital_connector_state(conn_state);
1674 const struct drm_display_mode *adjusted_mode =
1675 &crtc_state->hw.adjusted_mode;
1678 * Our YCbCr output is always limited range.
1679 * crtc_state->limited_color_range only applies to RGB,
1680 * and it must never be set for YCbCr or we risk setting
1681 * some conflicting bits in PIPECONF which will mess up
1682 * the colors on the monitor.
1684 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1687 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1690 * CEA-861-E - 5.1 Default Encoding Parameters
1691 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1693 return crtc_state->pipe_bpp != 18 &&
1694 drm_default_rgb_quant_range(adjusted_mode) ==
1695 HDMI_QUANTIZATION_RANGE_LIMITED;
1697 return intel_conn_state->broadcast_rgb ==
1698 INTEL_BROADCAST_RGB_LIMITED;
1702 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1705 if (IS_G4X(dev_priv))
1707 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1713 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1714 const struct drm_connector_state *conn_state,
1715 struct drm_dp_vsc_sdp *vsc)
1717 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1718 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1721 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1722 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1723 * Colorimetry Format indication.
1725 vsc->revision = 0x5;
1728 /* DP 1.4a spec, Table 2-120 */
1729 switch (crtc_state->output_format) {
1730 case INTEL_OUTPUT_FORMAT_YCBCR444:
1731 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1733 case INTEL_OUTPUT_FORMAT_YCBCR420:
1734 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1736 case INTEL_OUTPUT_FORMAT_RGB:
1738 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1741 switch (conn_state->colorspace) {
1742 case DRM_MODE_COLORIMETRY_BT709_YCC:
1743 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1745 case DRM_MODE_COLORIMETRY_XVYCC_601:
1746 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1748 case DRM_MODE_COLORIMETRY_XVYCC_709:
1749 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1751 case DRM_MODE_COLORIMETRY_SYCC_601:
1752 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1754 case DRM_MODE_COLORIMETRY_OPYCC_601:
1755 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1757 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1758 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1760 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1761 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1763 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1764 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1766 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1767 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1768 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1772 * RGB->YCBCR color conversion uses the BT.709
1775 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1776 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1778 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1782 vsc->bpc = crtc_state->pipe_bpp / 3;
1784 /* only RGB pixelformat supports 6 bpc */
1785 drm_WARN_ON(&dev_priv->drm,
1786 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1788 /* all YCbCr are always limited range */
1789 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1790 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1793 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1794 struct intel_crtc_state *crtc_state,
1795 const struct drm_connector_state *conn_state)
1797 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1799 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1800 if (crtc_state->has_psr)
1803 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1806 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1807 vsc->sdp_type = DP_SDP_VSC;
1808 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1809 &crtc_state->infoframes.vsc);
1812 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1813 const struct intel_crtc_state *crtc_state,
1814 const struct drm_connector_state *conn_state,
1815 struct drm_dp_vsc_sdp *vsc)
1817 vsc->sdp_type = DP_SDP_VSC;
1819 if (crtc_state->has_psr2) {
1820 if (intel_dp->psr.colorimetry_support &&
1821 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1822 /* [PSR2, +Colorimetry] */
1823 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1827 * [PSR2, -Colorimetry]
1828 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1829 * 3D stereo + PSR/PSR2 + Y-coordinate.
1831 vsc->revision = 0x4;
1837 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1838 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1841 vsc->revision = 0x2;
1847 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1848 struct intel_crtc_state *crtc_state,
1849 const struct drm_connector_state *conn_state)
1852 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1853 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1855 if (!conn_state->hdr_output_metadata)
1858 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1861 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1865 crtc_state->infoframes.enable |=
1866 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1869 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1870 enum transcoder cpu_transcoder)
1872 /* M1/N1 is double buffered */
1873 if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
1876 return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1879 static bool can_enable_drrs(struct intel_connector *connector,
1880 const struct intel_crtc_state *pipe_config,
1881 const struct drm_display_mode *downclock_mode)
1883 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1885 if (pipe_config->vrr.enable)
1889 * DRRS and PSR can't be enable together, so giving preference to PSR
1890 * as it allows more power-savings by complete shutting down display,
1891 * so to guarantee this, intel_drrs_compute_config() must be called
1892 * after intel_psr_compute_config().
1894 if (pipe_config->has_psr)
1897 /* FIXME missing FDI M2/N2 etc. */
1898 if (pipe_config->has_pch_encoder)
1901 if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
1904 return downclock_mode &&
1905 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1909 intel_dp_drrs_compute_config(struct intel_connector *connector,
1910 struct intel_crtc_state *pipe_config,
1911 int output_bpp, bool constant_n)
1913 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1914 const struct drm_display_mode *downclock_mode =
1915 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
1918 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
1919 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
1920 intel_zero_m_n(&pipe_config->dp_m2_n2);
1924 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
1925 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
1927 pipe_config->has_drrs = true;
1929 pixel_clock = downclock_mode->clock;
1930 if (pipe_config->splitter.enable)
1931 pixel_clock /= pipe_config->splitter.link_count;
1933 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1934 pipe_config->port_clock, &pipe_config->dp_m2_n2,
1935 constant_n, pipe_config->fec_enable);
1937 /* FIXME: abstract this better */
1938 if (pipe_config->splitter.enable)
1939 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
1942 static bool intel_dp_has_audio(struct intel_encoder *encoder,
1943 const struct intel_crtc_state *crtc_state,
1944 const struct drm_connector_state *conn_state)
1946 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1947 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1948 const struct intel_digital_connector_state *intel_conn_state =
1949 to_intel_digital_connector_state(conn_state);
1951 if (!intel_dp_port_has_audio(i915, encoder->port))
1954 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1955 return intel_dp->has_audio;
1957 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1961 intel_dp_compute_output_format(struct intel_encoder *encoder,
1962 struct intel_crtc_state *crtc_state,
1963 struct drm_connector_state *conn_state,
1964 bool respect_downstream_limits)
1966 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1967 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1968 struct intel_connector *connector = intel_dp->attached_connector;
1969 const struct drm_display_info *info = &connector->base.display_info;
1970 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1971 bool ycbcr_420_only;
1974 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
1976 crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
1978 if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
1979 drm_dbg_kms(&i915->drm,
1980 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
1981 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
1984 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1985 respect_downstream_limits);
1987 if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
1988 !connector->base.ycbcr_420_allowed ||
1989 !drm_mode_is_420_also(info, adjusted_mode))
1992 crtc_state->output_format = intel_dp_output_format(connector, true);
1993 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1994 respect_downstream_limits);
2001 intel_dp_compute_config(struct intel_encoder *encoder,
2002 struct intel_crtc_state *pipe_config,
2003 struct drm_connector_state *conn_state)
2005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2006 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2007 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2008 const struct drm_display_mode *fixed_mode;
2009 struct intel_connector *connector = intel_dp->attached_connector;
2010 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
2011 int ret = 0, output_bpp;
2013 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2014 pipe_config->has_pch_encoder = true;
2016 pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
2018 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2019 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2020 ret = intel_panel_compute_config(connector, adjusted_mode);
2025 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2028 if (HAS_GMCH(dev_priv) &&
2029 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2032 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2035 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2039 * Try to respect downstream TMDS clock limits first, if
2040 * that fails assume the user might know something we don't.
2042 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2044 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2048 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2049 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2050 ret = intel_panel_fitting(pipe_config, conn_state);
2055 pipe_config->limited_color_range =
2056 intel_dp_limited_color_range(pipe_config, conn_state);
2058 if (pipe_config->dsc.compression_enable)
2059 output_bpp = pipe_config->dsc.compressed_bpp;
2061 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2062 pipe_config->pipe_bpp);
2064 if (intel_dp->mso_link_count) {
2065 int n = intel_dp->mso_link_count;
2066 int overlap = intel_dp->mso_pixel_overlap;
2068 pipe_config->splitter.enable = true;
2069 pipe_config->splitter.link_count = n;
2070 pipe_config->splitter.pixel_overlap = overlap;
2072 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2075 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2076 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2077 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2078 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2079 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2080 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2081 adjusted_mode->crtc_clock /= n;
2084 intel_link_compute_m_n(output_bpp,
2085 pipe_config->lane_count,
2086 adjusted_mode->crtc_clock,
2087 pipe_config->port_clock,
2088 &pipe_config->dp_m_n,
2089 constant_n, pipe_config->fec_enable);
2091 /* FIXME: abstract this better */
2092 if (pipe_config->splitter.enable)
2093 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2095 if (!HAS_DDI(dev_priv))
2096 g4x_dp_set_clock(encoder, pipe_config);
2098 intel_vrr_compute_config(pipe_config, conn_state);
2099 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2100 intel_dp_drrs_compute_config(connector, pipe_config,
2101 output_bpp, constant_n);
2102 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2103 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2108 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2109 int link_rate, int lane_count)
2111 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2112 intel_dp->link_trained = false;
2113 intel_dp->link_rate = link_rate;
2114 intel_dp->lane_count = lane_count;
2117 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2119 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2120 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2123 /* Enable backlight PWM and backlight PP control. */
2124 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2125 const struct drm_connector_state *conn_state)
2127 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2128 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2130 if (!intel_dp_is_edp(intel_dp))
2133 drm_dbg_kms(&i915->drm, "\n");
2135 intel_backlight_enable(crtc_state, conn_state);
2136 intel_pps_backlight_on(intel_dp);
2139 /* Disable backlight PP control and backlight PWM. */
2140 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2142 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2143 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2145 if (!intel_dp_is_edp(intel_dp))
2148 drm_dbg_kms(&i915->drm, "\n");
2150 intel_pps_backlight_off(intel_dp);
2151 intel_backlight_disable(old_conn_state);
2154 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2157 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2158 * be capable of signalling downstream hpd with a long pulse.
2159 * Whether or not that means D3 is safe to use is not clear,
2160 * but let's assume so until proven otherwise.
2162 * FIXME should really check all downstream ports...
2164 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2165 drm_dp_is_branch(intel_dp->dpcd) &&
2166 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2169 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2170 const struct intel_crtc_state *crtc_state,
2173 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2176 if (!crtc_state->dsc.compression_enable)
2179 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2180 enable ? DP_DECOMPRESSION_EN : 0);
2182 drm_dbg_kms(&i915->drm,
2183 "Failed to %s sink decompression state\n",
2184 str_enable_disable(enable));
2188 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2190 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2191 u8 oui[] = { 0x00, 0xaa, 0x01 };
2195 * During driver init, we want to be careful and avoid changing the source OUI if it's
2196 * already set to what we want, so as to avoid clearing any state by accident
2199 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2200 drm_err(&i915->drm, "Failed to read source OUI\n");
2202 if (memcmp(oui, buf, sizeof(oui)) == 0)
2206 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2207 drm_err(&i915->drm, "Failed to write source OUI\n");
2209 intel_dp->last_oui_write = jiffies;
2212 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2214 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2216 drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2217 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2220 /* If the device supports it, try to set the power state appropriately */
2221 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2223 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2224 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2227 /* Should have a valid DPCD by this point */
2228 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2231 if (mode != DP_SET_POWER_D0) {
2232 if (downstream_hpd_needs_d0(intel_dp))
2235 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2237 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2239 lspcon_resume(dp_to_dig_port(intel_dp));
2241 /* Write the source OUI as early as possible */
2242 if (intel_dp_is_edp(intel_dp))
2243 intel_edp_init_source_oui(intel_dp, false);
2246 * When turning on, we need to retry for 1ms to give the sink
2249 for (i = 0; i < 3; i++) {
2250 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2256 if (ret == 1 && lspcon->active)
2257 lspcon_wait_pcon_mode(lspcon);
2261 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2262 encoder->base.base.id, encoder->base.name,
2263 mode == DP_SET_POWER_D0 ? "D0" : "D3");
2267 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2270 * intel_dp_sync_state - sync the encoder state during init/resume
2271 * @encoder: intel encoder to sync
2272 * @crtc_state: state for the CRTC connected to the encoder
2274 * Sync any state stored in the encoder wrt. HW state during driver init
2275 * and system resume.
2277 void intel_dp_sync_state(struct intel_encoder *encoder,
2278 const struct intel_crtc_state *crtc_state)
2280 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2286 * Don't clobber DPCD if it's been already read out during output
2287 * setup (eDP) or detect.
2289 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2290 intel_dp_get_dpcd(intel_dp);
2292 intel_dp_reset_max_link_params(intel_dp);
2295 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2296 struct intel_crtc_state *crtc_state)
2298 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2299 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2302 * If BIOS has set an unsupported or non-standard link rate for some
2303 * reason force an encoder recompute and full modeset.
2305 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2306 crtc_state->port_clock) < 0) {
2307 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2308 crtc_state->uapi.connectors_changed = true;
2313 * FIXME hack to force full modeset when DSC is being used.
2315 * As long as we do not have full state readout and config comparison
2316 * of crtc_state->dsc, we have no way to ensure reliable fastset.
2317 * Remove once we have readout for DSC.
2319 if (crtc_state->dsc.compression_enable) {
2320 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2321 crtc_state->uapi.mode_changed = true;
2325 if (CAN_PSR(intel_dp)) {
2326 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2327 crtc_state->uapi.mode_changed = true;
2334 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2336 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2338 /* Clear the cached register set to avoid using stale values */
2340 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2342 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2343 intel_dp->pcon_dsc_dpcd,
2344 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2345 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2346 DP_PCON_DSC_ENCODER);
2348 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2349 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2352 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2354 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2357 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2358 if (frl_bw_mask & (1 << i))
2364 static int intel_dp_pcon_set_frl_mask(int max_frl)
2368 return DP_PCON_FRL_BW_MASK_48GBPS;
2370 return DP_PCON_FRL_BW_MASK_40GBPS;
2372 return DP_PCON_FRL_BW_MASK_32GBPS;
2374 return DP_PCON_FRL_BW_MASK_24GBPS;
2376 return DP_PCON_FRL_BW_MASK_18GBPS;
2378 return DP_PCON_FRL_BW_MASK_9GBPS;
2384 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2386 struct intel_connector *intel_connector = intel_dp->attached_connector;
2387 struct drm_connector *connector = &intel_connector->base;
2389 int max_lanes, rate_per_lane;
2390 int max_dsc_lanes, dsc_rate_per_lane;
2392 max_lanes = connector->display_info.hdmi.max_lanes;
2393 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2394 max_frl_rate = max_lanes * rate_per_lane;
2396 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2397 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2398 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2399 if (max_dsc_lanes && dsc_rate_per_lane)
2400 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2403 return max_frl_rate;
2407 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2408 u8 max_frl_bw_mask, u8 *frl_trained_mask)
2410 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2411 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2412 *frl_trained_mask >= max_frl_bw_mask)
2418 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2420 #define TIMEOUT_FRL_READY_MS 500
2421 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2423 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2424 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2425 u8 max_frl_bw_mask = 0, frl_trained_mask;
2428 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2429 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2431 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2432 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2434 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2436 if (max_frl_bw <= 0)
2439 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2440 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2442 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2445 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2448 /* Wait for PCON to be FRL Ready */
2449 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2454 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2455 DP_PCON_ENABLE_SEQUENTIAL_LINK);
2458 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2459 DP_PCON_FRL_LINK_TRAIN_NORMAL);
2462 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2466 * Wait for FRL to be completed
2467 * Check if the HDMI Link is up and active.
2469 wait_for(is_active =
2470 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2471 TIMEOUT_HDMI_LINK_ACTIVE_MS);
2477 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2478 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2479 intel_dp->frl.is_trained = true;
2480 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2485 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2487 if (drm_dp_is_branch(intel_dp->dpcd) &&
2488 intel_dp->has_hdmi_sink &&
2489 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2496 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2501 /* Set PCON source control mode */
2502 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2504 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2508 /* Set HDMI LINK ENABLE */
2509 buf |= DP_PCON_ENABLE_HDMI_LINK;
2510 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2517 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2519 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2522 * Always go for FRL training if:
2523 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2526 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2527 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2528 intel_dp->frl.is_trained)
2531 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2534 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2535 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2536 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2538 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2539 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2541 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2546 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2548 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2550 return intel_hdmi_dsc_get_slice_height(vactive);
2554 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2555 const struct intel_crtc_state *crtc_state)
2557 struct intel_connector *intel_connector = intel_dp->attached_connector;
2558 struct drm_connector *connector = &intel_connector->base;
2559 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2560 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2561 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2562 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2564 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2565 pcon_max_slice_width,
2566 hdmi_max_slices, hdmi_throughput);
2570 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2571 const struct intel_crtc_state *crtc_state,
2572 int num_slices, int slice_width)
2574 struct intel_connector *intel_connector = intel_dp->attached_connector;
2575 struct drm_connector *connector = &intel_connector->base;
2576 int output_format = crtc_state->output_format;
2577 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2578 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2579 int hdmi_max_chunk_bytes =
2580 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2582 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2583 num_slices, output_format, hdmi_all_bpp,
2584 hdmi_max_chunk_bytes);
2588 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2589 const struct intel_crtc_state *crtc_state)
2597 struct intel_connector *intel_connector = intel_dp->attached_connector;
2598 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2599 struct drm_connector *connector;
2600 bool hdmi_is_dsc_1_2;
2602 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2605 if (!intel_connector)
2607 connector = &intel_connector->base;
2608 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2610 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2614 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2618 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2622 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2625 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2626 num_slices, slice_width);
2627 if (!bits_per_pixel)
2630 pps_param[0] = slice_height & 0xFF;
2631 pps_param[1] = slice_height >> 8;
2632 pps_param[2] = slice_width & 0xFF;
2633 pps_param[3] = slice_width >> 8;
2634 pps_param[4] = bits_per_pixel & 0xFF;
2635 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2637 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2639 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2642 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2643 const struct intel_crtc_state *crtc_state)
2645 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2648 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2651 if (!drm_dp_is_branch(intel_dp->dpcd))
2654 tmp = intel_dp->has_hdmi_sink ?
2655 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2657 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2658 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2659 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2660 str_enable_disable(intel_dp->has_hdmi_sink));
2662 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2663 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2665 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2666 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2667 drm_dbg_kms(&i915->drm,
2668 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2669 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2671 tmp = intel_dp->dfp.rgb_to_ycbcr ?
2672 DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2674 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2675 drm_dbg_kms(&i915->drm,
2676 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2677 str_enable_disable(tmp));
2681 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2685 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2688 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2691 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2693 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2696 * Clear the cached register set to avoid using stale values
2697 * for the sinks that do not support DSC.
2699 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2701 /* Clear fec_capable to avoid using stale values */
2702 intel_dp->fec_capable = 0;
2704 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2705 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2706 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2707 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2709 sizeof(intel_dp->dsc_dpcd)) < 0)
2711 "Failed to read DPCD register 0x%x\n",
2714 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2715 (int)sizeof(intel_dp->dsc_dpcd),
2716 intel_dp->dsc_dpcd);
2718 /* FEC is supported only on DP 1.4 */
2719 if (!intel_dp_is_edp(intel_dp) &&
2720 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2721 &intel_dp->fec_capable) < 0)
2723 "Failed to read FEC DPCD register\n");
2725 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2726 intel_dp->fec_capable);
2730 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2731 struct drm_display_mode *mode)
2733 struct intel_dp *intel_dp = intel_attached_dp(connector);
2734 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2735 int n = intel_dp->mso_link_count;
2736 int overlap = intel_dp->mso_pixel_overlap;
2741 mode->hdisplay = (mode->hdisplay - overlap) * n;
2742 mode->hsync_start = (mode->hsync_start - overlap) * n;
2743 mode->hsync_end = (mode->hsync_end - overlap) * n;
2744 mode->htotal = (mode->htotal - overlap) * n;
2747 drm_mode_set_name(mode);
2749 drm_dbg_kms(&i915->drm,
2750 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2751 connector->base.base.id, connector->base.name,
2752 DRM_MODE_ARG(mode));
2755 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
2757 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2758 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2759 struct intel_connector *connector = intel_dp->attached_connector;
2761 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
2763 * This is a big fat ugly hack.
2765 * Some machines in UEFI boot mode provide us a VBT that has 18
2766 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2767 * unknown we fail to light up. Yet the same BIOS boots up with
2768 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2769 * max, not what it tells us to use.
2771 * Note: This will still be broken if the eDP panel is not lit
2772 * up by the BIOS, and thus we can't get the mode at module
2775 drm_dbg_kms(&dev_priv->drm,
2776 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2777 pipe_bpp, connector->panel.vbt.edp.bpp);
2778 connector->panel.vbt.edp.bpp = pipe_bpp;
2782 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2784 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2785 struct intel_connector *connector = intel_dp->attached_connector;
2786 struct drm_display_info *info = &connector->base.display_info;
2789 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2792 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2793 drm_err(&i915->drm, "Failed to read MSO cap\n");
2797 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2798 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2799 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2800 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2805 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2806 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2807 info->mso_pixel_overlap);
2808 if (!HAS_MSO(i915)) {
2809 drm_err(&i915->drm, "No source MSO support, disabling\n");
2814 intel_dp->mso_link_count = mso;
2815 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2819 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2821 struct drm_i915_private *dev_priv =
2822 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2824 /* this function is meant to be called only once */
2825 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2827 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2830 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2831 drm_dp_is_branch(intel_dp->dpcd));
2834 * Read the eDP display control registers.
2836 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2837 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2838 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2839 * method). The display control registers should read zero if they're
2840 * not supported anyway.
2842 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2843 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2844 sizeof(intel_dp->edp_dpcd)) {
2845 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2846 (int)sizeof(intel_dp->edp_dpcd),
2847 intel_dp->edp_dpcd);
2849 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2853 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2854 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2856 intel_psr_init_dpcd(intel_dp);
2858 /* Clear the default sink rates */
2859 intel_dp->num_sink_rates = 0;
2861 /* Read the eDP 1.4+ supported link rates. */
2862 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2863 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2866 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2867 sink_rates, sizeof(sink_rates));
2869 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2870 int val = le16_to_cpu(sink_rates[i]);
2875 /* Value read multiplied by 200kHz gives the per-lane
2876 * link rate in kHz. The source rates are, however,
2877 * stored in terms of LS_Clk kHz. The full conversion
2878 * back to symbols is
2879 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2881 intel_dp->sink_rates[i] = (val * 200) / 10;
2883 intel_dp->num_sink_rates = i;
2887 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2888 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2890 if (intel_dp->num_sink_rates)
2891 intel_dp->use_rate_select = true;
2893 intel_dp_set_sink_rates(intel_dp);
2894 intel_dp_set_max_sink_lane_count(intel_dp);
2896 /* Read the eDP DSC DPCD registers */
2897 if (DISPLAY_VER(dev_priv) >= 10)
2898 intel_dp_get_dsc_sink_cap(intel_dp);
2901 * If needed, program our source OUI so we can make various Intel-specific AUX services
2902 * available (such as HDR backlight controls)
2904 intel_edp_init_source_oui(intel_dp, true);
2910 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2912 if (!intel_dp->attached_connector)
2915 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2921 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2925 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2929 * Don't clobber cached eDP rates. Also skip re-reading
2930 * the OUI/ID since we know it won't change.
2932 if (!intel_dp_is_edp(intel_dp)) {
2933 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2934 drm_dp_is_branch(intel_dp->dpcd));
2936 intel_dp_set_sink_rates(intel_dp);
2937 intel_dp_set_max_sink_lane_count(intel_dp);
2938 intel_dp_set_common_rates(intel_dp);
2941 if (intel_dp_has_sink_count(intel_dp)) {
2942 ret = drm_dp_read_sink_count(&intel_dp->aux);
2947 * Sink count can change between short pulse hpd hence
2948 * a member variable in intel_dp will track any changes
2949 * between short pulse interrupts.
2951 intel_dp->sink_count = ret;
2954 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2955 * a dongle is present but no display. Unless we require to know
2956 * if a dongle is present or not, we don't need to update
2957 * downstream port information. So, an early return here saves
2958 * time from performing other operations which are not required.
2960 if (!intel_dp->sink_count)
2964 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2965 intel_dp->downstream_ports) == 0;
2969 intel_dp_can_mst(struct intel_dp *intel_dp)
2971 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2973 return i915->params.enable_dp_mst &&
2974 intel_dp_mst_source_support(intel_dp) &&
2975 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2979 intel_dp_configure_mst(struct intel_dp *intel_dp)
2981 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2982 struct intel_encoder *encoder =
2983 &dp_to_dig_port(intel_dp)->base;
2984 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2986 drm_dbg_kms(&i915->drm,
2987 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2988 encoder->base.base.id, encoder->base.name,
2989 str_yes_no(intel_dp_mst_source_support(intel_dp)),
2990 str_yes_no(sink_can_mst),
2991 str_yes_no(i915->params.enable_dp_mst));
2993 if (!intel_dp_mst_source_support(intel_dp))
2996 intel_dp->is_mst = sink_can_mst &&
2997 i915->params.enable_dp_mst;
2999 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3004 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3006 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3009 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3013 for (retry = 0; retry < 3; retry++) {
3014 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3023 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3024 const struct drm_connector_state *conn_state)
3027 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3028 * of Color Encoding Format and Content Color Gamut], in order to
3029 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3031 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3034 switch (conn_state->colorspace) {
3035 case DRM_MODE_COLORIMETRY_SYCC_601:
3036 case DRM_MODE_COLORIMETRY_OPYCC_601:
3037 case DRM_MODE_COLORIMETRY_BT2020_YCC:
3038 case DRM_MODE_COLORIMETRY_BT2020_RGB:
3039 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3048 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3049 struct dp_sdp *sdp, size_t size)
3051 size_t length = sizeof(struct dp_sdp);
3056 memset(sdp, 0, size);
3059 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3060 * VSC SDP Header Bytes
3062 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3063 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3064 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3065 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3068 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3071 if (vsc->revision != 0x5)
3074 /* VSC SDP Payload for DB16 through DB18 */
3075 /* Pixel Encoding and Colorimetry Formats */
3076 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3077 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3084 sdp->db[17] = 0x1; /* DB17[3:0] */
3096 MISSING_CASE(vsc->bpc);
3099 /* Dynamic Range and Component Bit Depth */
3100 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3101 sdp->db[17] |= 0x80; /* DB17[7] */
3104 sdp->db[18] = vsc->content_type & 0x7;
3111 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3112 const struct hdmi_drm_infoframe *drm_infoframe,
3116 size_t length = sizeof(struct dp_sdp);
3117 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3118 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3124 memset(sdp, 0, size);
3126 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3128 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3132 if (len != infoframe_size) {
3133 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3138 * Set up the infoframe sdp packet for HDR static metadata.
3139 * Prepare VSC Header for SU as per DP 1.4a spec,
3140 * Table 2-100 and Table 2-101
3143 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3144 sdp->sdp_header.HB0 = 0;
3146 * Packet Type 80h + Non-audio INFOFRAME Type value
3147 * HDMI_INFOFRAME_TYPE_DRM: 0x87
3148 * - 80h + Non-audio INFOFRAME Type value
3149 * - InfoFrame Type: 0x07
3150 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3152 sdp->sdp_header.HB1 = drm_infoframe->type;
3154 * Least Significant Eight Bits of (Data Byte Count – 1)
3155 * infoframe_size - 1
3157 sdp->sdp_header.HB2 = 0x1D;
3158 /* INFOFRAME SDP Version Number */
3159 sdp->sdp_header.HB3 = (0x13 << 2);
3160 /* CTA Header Byte 2 (INFOFRAME Version Number) */
3161 sdp->db[0] = drm_infoframe->version;
3162 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3163 sdp->db[1] = drm_infoframe->length;
3165 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3166 * HDMI_INFOFRAME_HEADER_SIZE
3168 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3169 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3170 HDMI_DRM_INFOFRAME_SIZE);
3173 * Size of DP infoframe sdp packet for HDR static metadata consists of
3174 * - DP SDP Header(struct dp_sdp_header): 4 bytes
3175 * - Two Data Blocks: 2 bytes
3176 * CTA Header Byte2 (INFOFRAME Version Number)
3177 * CTA Header Byte3 (Length of INFOFRAME)
3178 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3180 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3181 * infoframe size. But GEN11+ has larger than that size, write_infoframe
3182 * will pad rest of the size.
3184 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3187 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3188 const struct intel_crtc_state *crtc_state,
3191 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3193 struct dp_sdp sdp = {};
3196 if ((crtc_state->infoframes.enable &
3197 intel_hdmi_infoframe_enable(type)) == 0)
3202 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3205 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3206 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3207 &crtc_state->infoframes.drm.drm,
3215 if (drm_WARN_ON(&dev_priv->drm, len < 0))
3218 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3221 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3222 const struct intel_crtc_state *crtc_state,
3223 const struct drm_dp_vsc_sdp *vsc)
3225 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3227 struct dp_sdp sdp = {};
3230 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3232 if (drm_WARN_ON(&dev_priv->drm, len < 0))
3235 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3239 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3241 const struct intel_crtc_state *crtc_state,
3242 const struct drm_connector_state *conn_state)
3244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3245 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3246 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3247 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3248 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3249 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3251 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3252 /* When PSR is enabled, this routine doesn't disable VSC DIP */
3253 if (!crtc_state->has_psr)
3254 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3256 intel_de_write(dev_priv, reg, val);
3257 intel_de_posting_read(dev_priv, reg);
3262 /* When PSR is enabled, VSC SDP is handled by PSR routine */
3263 if (!crtc_state->has_psr)
3264 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3266 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3269 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3270 const void *buffer, size_t size)
3272 const struct dp_sdp *sdp = buffer;
3274 if (size < sizeof(struct dp_sdp))
3277 memset(vsc, 0, sizeof(*vsc));
3279 if (sdp->sdp_header.HB0 != 0)
3282 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3285 vsc->sdp_type = sdp->sdp_header.HB1;
3286 vsc->revision = sdp->sdp_header.HB2;
3287 vsc->length = sdp->sdp_header.HB3;
3289 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3290 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3292 * - HB2 = 0x2, HB3 = 0x8
3293 * VSC SDP supporting 3D stereo + PSR
3294 * - HB2 = 0x4, HB3 = 0xe
3295 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3296 * first scan line of the SU region (applies to eDP v1.4b
3300 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3302 * - HB2 = 0x5, HB3 = 0x13
3303 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3306 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3307 vsc->colorimetry = sdp->db[16] & 0xf;
3308 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3310 switch (sdp->db[17] & 0x7) {
3327 MISSING_CASE(sdp->db[17] & 0x7);
3331 vsc->content_type = sdp->db[18] & 0x7;
3340 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3341 const void *buffer, size_t size)
3345 const struct dp_sdp *sdp = buffer;
3347 if (size < sizeof(struct dp_sdp))
3350 if (sdp->sdp_header.HB0 != 0)
3353 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3357 * Least Significant Eight Bits of (Data Byte Count – 1)
3358 * 1Dh (i.e., Data Byte Count = 30 bytes).
3360 if (sdp->sdp_header.HB2 != 0x1D)
3363 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3364 if ((sdp->sdp_header.HB3 & 0x3) != 0)
3367 /* INFOFRAME SDP Version Number */
3368 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3371 /* CTA Header Byte 2 (INFOFRAME Version Number) */
3372 if (sdp->db[0] != 1)
3375 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3376 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3379 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3380 HDMI_DRM_INFOFRAME_SIZE);
3385 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3386 struct intel_crtc_state *crtc_state,
3387 struct drm_dp_vsc_sdp *vsc)
3389 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3391 unsigned int type = DP_SDP_VSC;
3392 struct dp_sdp sdp = {};
3395 /* When PSR is enabled, VSC SDP is handled by PSR routine */
3396 if (crtc_state->has_psr)
3399 if ((crtc_state->infoframes.enable &
3400 intel_hdmi_infoframe_enable(type)) == 0)
3403 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3405 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3408 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3411 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3412 struct intel_crtc_state *crtc_state,
3413 struct hdmi_drm_infoframe *drm_infoframe)
3415 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3417 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3418 struct dp_sdp sdp = {};
3421 if ((crtc_state->infoframes.enable &
3422 intel_hdmi_infoframe_enable(type)) == 0)
3425 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3428 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3432 drm_dbg_kms(&dev_priv->drm,
3433 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3436 void intel_read_dp_sdp(struct intel_encoder *encoder,
3437 struct intel_crtc_state *crtc_state,
3442 intel_read_dp_vsc_sdp(encoder, crtc_state,
3443 &crtc_state->infoframes.vsc);
3445 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3446 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3447 &crtc_state->infoframes.drm.drm);
3455 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3457 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3460 u8 test_lane_count, test_link_bw;
3464 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3465 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3469 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3472 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3474 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3477 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3480 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3482 /* Validate the requested link rate and lane count */
3483 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3487 intel_dp->compliance.test_lane_count = test_lane_count;
3488 intel_dp->compliance.test_link_rate = test_link_rate;
3493 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3495 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3498 __be16 h_width, v_height;
3501 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3502 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3505 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3508 if (test_pattern != DP_COLOR_RAMP)
3511 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3514 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3518 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3521 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3525 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3528 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3531 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3533 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3535 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3536 case DP_TEST_BIT_DEPTH_6:
3537 intel_dp->compliance.test_data.bpc = 6;
3539 case DP_TEST_BIT_DEPTH_8:
3540 intel_dp->compliance.test_data.bpc = 8;
3546 intel_dp->compliance.test_data.video_pattern = test_pattern;
3547 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3548 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3549 /* Set test active flag here so userspace doesn't interrupt things */
3550 intel_dp->compliance.test_active = true;
3555 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3557 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3558 u8 test_result = DP_TEST_ACK;
3559 struct intel_connector *intel_connector = intel_dp->attached_connector;
3560 struct drm_connector *connector = &intel_connector->base;
3562 if (intel_connector->detect_edid == NULL ||
3563 connector->edid_corrupt ||
3564 intel_dp->aux.i2c_defer_count > 6) {
3565 /* Check EDID read for NACKs, DEFERs and corruption
3566 * (DP CTS 1.2 Core r1.1)
3567 * 4.2.2.4 : Failed EDID read, I2C_NAK
3568 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3569 * 4.2.2.6 : EDID corruption detected
3570 * Use failsafe mode for all cases
3572 if (intel_dp->aux.i2c_nack_count > 0 ||
3573 intel_dp->aux.i2c_defer_count > 0)
3574 drm_dbg_kms(&i915->drm,
3575 "EDID read had %d NACKs, %d DEFERs\n",
3576 intel_dp->aux.i2c_nack_count,
3577 intel_dp->aux.i2c_defer_count);
3578 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3580 struct edid *block = intel_connector->detect_edid;
3582 /* We have to write the checksum
3583 * of the last block read
3585 block += intel_connector->detect_edid->extensions;
3587 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3588 block->checksum) <= 0)
3589 drm_dbg_kms(&i915->drm,
3590 "Failed to write EDID checksum\n");
3592 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3593 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3596 /* Set test active flag here so userspace doesn't interrupt things */
3597 intel_dp->compliance.test_active = true;
3602 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3603 const struct intel_crtc_state *crtc_state)
3605 struct drm_i915_private *dev_priv =
3606 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3607 struct drm_dp_phy_test_params *data =
3608 &intel_dp->compliance.test_data.phytest;
3609 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3610 enum pipe pipe = crtc->pipe;
3613 switch (data->phy_pattern) {
3614 case DP_PHY_TEST_PATTERN_NONE:
3615 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3616 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3618 case DP_PHY_TEST_PATTERN_D10_2:
3619 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3620 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3621 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3623 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3624 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3625 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3626 DDI_DP_COMP_CTL_ENABLE |
3627 DDI_DP_COMP_CTL_SCRAMBLED_0);
3629 case DP_PHY_TEST_PATTERN_PRBS7:
3630 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3631 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3632 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3634 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3636 * FIXME: Ideally pattern should come from DPCD 0x250. As
3637 * current firmware of DPR-100 could not set it, so hardcoding
3638 * now for complaince test.
3640 drm_dbg_kms(&dev_priv->drm,
3641 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3642 pattern_val = 0x3e0f83e0;
3643 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3644 pattern_val = 0x0f83e0f8;
3645 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3646 pattern_val = 0x0000f83e;
3647 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3648 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3649 DDI_DP_COMP_CTL_ENABLE |
3650 DDI_DP_COMP_CTL_CUSTOM80);
3652 case DP_PHY_TEST_PATTERN_CP2520:
3654 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3655 * current firmware of DPR-100 could not set it, so hardcoding
3656 * now for complaince test.
3658 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3660 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3661 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3665 WARN(1, "Invalid Phy Test Pattern\n");
3670 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3671 const struct intel_crtc_state *crtc_state)
3673 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3674 struct drm_device *dev = dig_port->base.base.dev;
3675 struct drm_i915_private *dev_priv = to_i915(dev);
3676 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3677 enum pipe pipe = crtc->pipe;
3678 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3680 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3681 TRANS_DDI_FUNC_CTL(pipe));
3682 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3683 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3685 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3686 TGL_TRANS_DDI_PORT_MASK);
3687 trans_conf_value &= ~PIPECONF_ENABLE;
3688 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3690 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3691 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3692 trans_ddi_func_ctl_value);
3693 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3697 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3698 const struct intel_crtc_state *crtc_state)
3700 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3701 struct drm_device *dev = dig_port->base.base.dev;
3702 struct drm_i915_private *dev_priv = to_i915(dev);
3703 enum port port = dig_port->base.port;
3704 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3705 enum pipe pipe = crtc->pipe;
3706 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3708 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3709 TRANS_DDI_FUNC_CTL(pipe));
3710 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3711 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3713 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3714 TGL_TRANS_DDI_SELECT_PORT(port);
3715 trans_conf_value |= PIPECONF_ENABLE;
3716 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3718 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3719 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3720 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3721 trans_ddi_func_ctl_value);
3724 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3725 const struct intel_crtc_state *crtc_state)
3727 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3728 struct drm_dp_phy_test_params *data =
3729 &intel_dp->compliance.test_data.phytest;
3730 u8 link_status[DP_LINK_STATUS_SIZE];
3732 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3734 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3738 /* retrieve vswing & pre-emphasis setting */
3739 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3742 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3744 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3746 intel_dp_phy_pattern_update(intel_dp, crtc_state);
3748 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3750 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3751 intel_dp->train_set, crtc_state->lane_count);
3753 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3754 link_status[DP_DPCD_REV]);
3757 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3759 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3760 struct drm_dp_phy_test_params *data =
3761 &intel_dp->compliance.test_data.phytest;
3763 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3764 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3768 /* Set test active flag here so userspace doesn't interrupt things */
3769 intel_dp->compliance.test_active = true;
3774 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3776 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3777 u8 response = DP_TEST_NAK;
3781 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3783 drm_dbg_kms(&i915->drm,
3784 "Could not read test request from sink\n");
3789 case DP_TEST_LINK_TRAINING:
3790 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3791 response = intel_dp_autotest_link_training(intel_dp);
3793 case DP_TEST_LINK_VIDEO_PATTERN:
3794 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3795 response = intel_dp_autotest_video_pattern(intel_dp);
3797 case DP_TEST_LINK_EDID_READ:
3798 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3799 response = intel_dp_autotest_edid(intel_dp);
3801 case DP_TEST_LINK_PHY_TEST_PATTERN:
3802 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3803 response = intel_dp_autotest_phy_pattern(intel_dp);
3806 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3811 if (response & DP_TEST_ACK)
3812 intel_dp->compliance.test_type = request;
3815 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3817 drm_dbg_kms(&i915->drm,
3818 "Could not write test response to sink\n");
3821 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3822 u8 link_status[DP_LINK_STATUS_SIZE])
3824 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3825 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3826 bool uhbr = intel_dp->link_rate >= 1000000;
3830 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3831 intel_dp->lane_count);
3833 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3838 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3839 drm_dbg_kms(&i915->drm,
3840 "[ENCODER:%d:%s] %s link not ok, retraining\n",
3841 encoder->base.base.id, encoder->base.name,
3842 uhbr ? "128b/132b" : "8b/10b");
3848 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3850 bool handled = false;
3852 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3854 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3856 if (esi[1] & DP_CP_IRQ) {
3857 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3858 ack[1] |= DP_CP_IRQ;
3862 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3864 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3865 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3866 u8 link_status[DP_LINK_STATUS_SIZE] = {};
3867 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3869 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3870 esi_link_status_size) != esi_link_status_size) {
3872 "[ENCODER:%d:%s] Failed to read link status\n",
3873 encoder->base.base.id, encoder->base.name);
3877 return intel_dp_link_ok(intel_dp, link_status);
3881 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3882 * @intel_dp: Intel DP struct
3884 * Read any pending MST interrupts, call MST core to handle these and ack the
3885 * interrupts. Check if the main and AUX link state is ok.
3888 * - %true if pending interrupts were serviced (or no interrupts were
3889 * pending) w/o detecting an error condition.
3890 * - %false if an error condition - like AUX failure or a loss of link - is
3891 * detected, which needs servicing from the hotplug work.
3894 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3896 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3897 bool link_ok = true;
3899 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3905 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3906 drm_dbg_kms(&i915->drm,
3907 "failed to get ESI - device may have failed\n");
3913 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3915 if (intel_dp->active_mst_links > 0 && link_ok &&
3916 esi[3] & LINK_STATUS_CHANGED) {
3917 if (!intel_dp_mst_link_status(intel_dp))
3919 ack[3] |= LINK_STATUS_CHANGED;
3922 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3924 if (!memchr_inv(ack, 0, sizeof(ack)))
3927 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3928 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3935 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3940 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3941 if (intel_dp->frl.is_trained && !is_active) {
3942 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3945 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
3946 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3949 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3951 /* Restart FRL training or fall back to TMDS mode */
3952 intel_dp_check_frl_training(intel_dp);
3957 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3959 u8 link_status[DP_LINK_STATUS_SIZE];
3961 if (!intel_dp->link_trained)
3965 * While PSR source HW is enabled, it will control main-link sending
3966 * frames, enabling and disabling it so trying to do a retrain will fail
3967 * as the link would or not be on or it could mix training patterns
3968 * and frame data at the same time causing retrain to fail.
3969 * Also when exiting PSR, HW will retrain the link anyways fixing
3970 * any link status error.
3972 if (intel_psr_enabled(intel_dp))
3975 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3980 * Validate the cached values of intel_dp->link_rate and
3981 * intel_dp->lane_count before attempting to retrain.
3983 * FIXME would be nice to user the crtc state here, but since
3984 * we need to call this from the short HPD handler that seems
3987 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3988 intel_dp->lane_count))
3991 /* Retrain if link not ok */
3992 return !intel_dp_link_ok(intel_dp, link_status);
3995 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3996 const struct drm_connector_state *conn_state)
3998 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3999 struct intel_encoder *encoder;
4002 if (!conn_state->best_encoder)
4006 encoder = &dp_to_dig_port(intel_dp)->base;
4007 if (conn_state->best_encoder == &encoder->base)
4011 for_each_pipe(i915, pipe) {
4012 encoder = &intel_dp->mst_encoders[pipe]->base;
4013 if (conn_state->best_encoder == &encoder->base)
4020 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
4021 struct drm_modeset_acquire_ctx *ctx,
4024 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4025 struct drm_connector_list_iter conn_iter;
4026 struct intel_connector *connector;
4031 if (!intel_dp_needs_link_retrain(intel_dp))
4034 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4035 for_each_intel_connector_iter(connector, &conn_iter) {
4036 struct drm_connector_state *conn_state =
4037 connector->base.state;
4038 struct intel_crtc_state *crtc_state;
4039 struct intel_crtc *crtc;
4041 if (!intel_dp_has_connector(intel_dp, conn_state))
4044 crtc = to_intel_crtc(conn_state->crtc);
4048 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4052 crtc_state = to_intel_crtc_state(crtc->base.state);
4054 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4056 if (!crtc_state->hw.active)
4059 if (conn_state->commit &&
4060 !try_wait_for_completion(&conn_state->commit->hw_done))
4063 *pipe_mask |= BIT(crtc->pipe);
4065 drm_connector_list_iter_end(&conn_iter);
4067 if (!intel_dp_needs_link_retrain(intel_dp))
4073 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4075 struct intel_connector *connector = intel_dp->attached_connector;
4077 return connector->base.status == connector_status_connected ||
4081 int intel_dp_retrain_link(struct intel_encoder *encoder,
4082 struct drm_modeset_acquire_ctx *ctx)
4084 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4086 struct intel_crtc *crtc;
4090 if (!intel_dp_is_connected(intel_dp))
4093 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4098 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4105 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4106 encoder->base.base.id, encoder->base.name);
4108 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4109 const struct intel_crtc_state *crtc_state =
4110 to_intel_crtc_state(crtc->base.state);
4112 /* Suppress underruns caused by re-training */
4113 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4114 if (crtc_state->has_pch_encoder)
4115 intel_set_pch_fifo_underrun_reporting(dev_priv,
4116 intel_crtc_pch_transcoder(crtc), false);
4119 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4120 const struct intel_crtc_state *crtc_state =
4121 to_intel_crtc_state(crtc->base.state);
4123 /* retrain on the MST master transcoder */
4124 if (DISPLAY_VER(dev_priv) >= 12 &&
4125 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4126 !intel_dp_mst_is_master_trans(crtc_state))
4129 intel_dp_check_frl_training(intel_dp);
4130 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4131 intel_dp_start_link_train(intel_dp, crtc_state);
4132 intel_dp_stop_link_train(intel_dp, crtc_state);
4136 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4137 const struct intel_crtc_state *crtc_state =
4138 to_intel_crtc_state(crtc->base.state);
4140 /* Keep underrun reporting disabled until things are stable */
4141 intel_crtc_wait_for_next_vblank(crtc);
4143 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4144 if (crtc_state->has_pch_encoder)
4145 intel_set_pch_fifo_underrun_reporting(dev_priv,
4146 intel_crtc_pch_transcoder(crtc), true);
4152 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4153 struct drm_modeset_acquire_ctx *ctx,
4156 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4157 struct drm_connector_list_iter conn_iter;
4158 struct intel_connector *connector;
4163 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4164 for_each_intel_connector_iter(connector, &conn_iter) {
4165 struct drm_connector_state *conn_state =
4166 connector->base.state;
4167 struct intel_crtc_state *crtc_state;
4168 struct intel_crtc *crtc;
4170 if (!intel_dp_has_connector(intel_dp, conn_state))
4173 crtc = to_intel_crtc(conn_state->crtc);
4177 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4181 crtc_state = to_intel_crtc_state(crtc->base.state);
4183 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4185 if (!crtc_state->hw.active)
4188 if (conn_state->commit &&
4189 !try_wait_for_completion(&conn_state->commit->hw_done))
4192 *pipe_mask |= BIT(crtc->pipe);
4194 drm_connector_list_iter_end(&conn_iter);
4199 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4200 struct drm_modeset_acquire_ctx *ctx)
4202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4203 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4204 struct intel_crtc *crtc;
4208 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4213 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4220 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4221 encoder->base.base.id, encoder->base.name);
4223 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4224 const struct intel_crtc_state *crtc_state =
4225 to_intel_crtc_state(crtc->base.state);
4227 /* test on the MST master transcoder */
4228 if (DISPLAY_VER(dev_priv) >= 12 &&
4229 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4230 !intel_dp_mst_is_master_trans(crtc_state))
4233 intel_dp_process_phy_request(intel_dp, crtc_state);
4240 void intel_dp_phy_test(struct intel_encoder *encoder)
4242 struct drm_modeset_acquire_ctx ctx;
4245 drm_modeset_acquire_init(&ctx, 0);
4248 ret = intel_dp_do_phy_test(encoder, &ctx);
4250 if (ret == -EDEADLK) {
4251 drm_modeset_backoff(&ctx);
4258 drm_modeset_drop_locks(&ctx);
4259 drm_modeset_acquire_fini(&ctx);
4260 drm_WARN(encoder->base.dev, ret,
4261 "Acquiring modeset locks failed with %i\n", ret);
4264 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4266 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4269 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4272 if (drm_dp_dpcd_readb(&intel_dp->aux,
4273 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4276 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4278 if (val & DP_AUTOMATED_TEST_REQUEST)
4279 intel_dp_handle_test_request(intel_dp);
4281 if (val & DP_CP_IRQ)
4282 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4284 if (val & DP_SINK_SPECIFIC_IRQ)
4285 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4288 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4292 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4295 if (drm_dp_dpcd_readb(&intel_dp->aux,
4296 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4299 if (drm_dp_dpcd_writeb(&intel_dp->aux,
4300 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4303 if (val & HDMI_LINK_STATUS_CHANGED)
4304 intel_dp_handle_hdmi_link_status_change(intel_dp);
4308 * According to DP spec
4311 * 2. Configure link according to Receiver Capabilities
4312 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4313 * 4. Check link status on receipt of hot-plug interrupt
4315 * intel_dp_short_pulse - handles short pulse interrupts
4316 * when full detection is not required.
4317 * Returns %true if short pulse is handled and full detection
4318 * is NOT required and %false otherwise.
4321 intel_dp_short_pulse(struct intel_dp *intel_dp)
4323 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4324 u8 old_sink_count = intel_dp->sink_count;
4328 * Clearing compliance test variables to allow capturing
4329 * of values for next automated test request.
4331 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4334 * Now read the DPCD to see if it's actually running
4335 * If the current value of sink count doesn't match with
4336 * the value that was stored earlier or dpcd read failed
4337 * we need to do full detection
4339 ret = intel_dp_get_dpcd(intel_dp);
4341 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4342 /* No need to proceed if we are going to do full detect */
4346 intel_dp_check_device_service_irq(intel_dp);
4347 intel_dp_check_link_service_irq(intel_dp);
4349 /* Handle CEC interrupts, if any */
4350 drm_dp_cec_irq(&intel_dp->aux);
4352 /* defer to the hotplug work for link retraining if needed */
4353 if (intel_dp_needs_link_retrain(intel_dp))
4356 intel_psr_short_pulse(intel_dp);
4358 switch (intel_dp->compliance.test_type) {
4359 case DP_TEST_LINK_TRAINING:
4360 drm_dbg_kms(&dev_priv->drm,
4361 "Link Training Compliance Test requested\n");
4362 /* Send a Hotplug Uevent to userspace to start modeset */
4363 drm_kms_helper_hotplug_event(&dev_priv->drm);
4365 case DP_TEST_LINK_PHY_TEST_PATTERN:
4366 drm_dbg_kms(&dev_priv->drm,
4367 "PHY test pattern Compliance Test requested\n");
4369 * Schedule long hpd to do the test
4371 * FIXME get rid of the ad-hoc phy test modeset code
4372 * and properly incorporate it into the normal modeset.
4380 /* XXX this is probably wrong for multiple downstream ports */
4381 static enum drm_connector_status
4382 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4384 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4385 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4386 u8 *dpcd = intel_dp->dpcd;
4389 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4390 return connector_status_connected;
4392 lspcon_resume(dig_port);
4394 if (!intel_dp_get_dpcd(intel_dp))
4395 return connector_status_disconnected;
4397 /* if there's no downstream port, we're done */
4398 if (!drm_dp_is_branch(dpcd))
4399 return connector_status_connected;
4401 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4402 if (intel_dp_has_sink_count(intel_dp) &&
4403 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4404 return intel_dp->sink_count ?
4405 connector_status_connected : connector_status_disconnected;
4408 if (intel_dp_can_mst(intel_dp))
4409 return connector_status_connected;
4411 /* If no HPD, poke DDC gently */
4412 if (drm_probe_ddc(&intel_dp->aux.ddc))
4413 return connector_status_connected;
4415 /* Well we tried, say unknown for unreliable port types */
4416 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4417 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4418 if (type == DP_DS_PORT_TYPE_VGA ||
4419 type == DP_DS_PORT_TYPE_NON_EDID)
4420 return connector_status_unknown;
4422 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4423 DP_DWN_STRM_PORT_TYPE_MASK;
4424 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4425 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4426 return connector_status_unknown;
4429 /* Anything else is out of spec, warn and ignore */
4430 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4431 return connector_status_disconnected;
4434 static enum drm_connector_status
4435 edp_detect(struct intel_dp *intel_dp)
4437 return connector_status_connected;
4441 * intel_digital_port_connected - is the specified port connected?
4442 * @encoder: intel_encoder
4444 * In cases where there's a connector physically connected but it can't be used
4445 * by our hardware we also return false, since the rest of the driver should
4446 * pretty much treat the port as disconnected. This is relevant for type-C
4447 * (starting on ICL) where there's ownership involved.
4449 * Return %true if port is connected, %false otherwise.
4451 bool intel_digital_port_connected(struct intel_encoder *encoder)
4453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4454 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4455 bool is_connected = false;
4456 intel_wakeref_t wakeref;
4458 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4459 is_connected = dig_port->connected(encoder);
4461 return is_connected;
4464 static struct edid *
4465 intel_dp_get_edid(struct intel_dp *intel_dp)
4467 struct intel_connector *intel_connector = intel_dp->attached_connector;
4469 /* use cached edid if we have one */
4470 if (intel_connector->edid) {
4472 if (IS_ERR(intel_connector->edid))
4475 return drm_edid_duplicate(intel_connector->edid);
4477 return drm_get_edid(&intel_connector->base,
4478 &intel_dp->aux.ddc);
4482 intel_dp_update_dfp(struct intel_dp *intel_dp,
4483 const struct edid *edid)
4485 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4486 struct intel_connector *connector = intel_dp->attached_connector;
4488 intel_dp->dfp.max_bpc =
4489 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4490 intel_dp->downstream_ports, edid);
4492 intel_dp->dfp.max_dotclock =
4493 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4494 intel_dp->downstream_ports);
4496 intel_dp->dfp.min_tmds_clock =
4497 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4498 intel_dp->downstream_ports,
4500 intel_dp->dfp.max_tmds_clock =
4501 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4502 intel_dp->downstream_ports,
4505 intel_dp->dfp.pcon_max_frl_bw =
4506 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4507 intel_dp->downstream_ports);
4509 drm_dbg_kms(&i915->drm,
4510 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4511 connector->base.base.id, connector->base.name,
4512 intel_dp->dfp.max_bpc,
4513 intel_dp->dfp.max_dotclock,
4514 intel_dp->dfp.min_tmds_clock,
4515 intel_dp->dfp.max_tmds_clock,
4516 intel_dp->dfp.pcon_max_frl_bw);
4518 intel_dp_get_pcon_dsc_cap(intel_dp);
4522 intel_dp_update_420(struct intel_dp *intel_dp)
4524 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4525 struct intel_connector *connector = intel_dp->attached_connector;
4526 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4528 /* No YCbCr output support on gmch platforms */
4533 * ILK doesn't seem capable of DP YCbCr output. The
4534 * displayed image is severly corrupted. SNB+ is fine.
4536 if (IS_IRONLAKE(i915))
4539 is_branch = drm_dp_is_branch(intel_dp->dpcd);
4540 ycbcr_420_passthrough =
4541 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4542 intel_dp->downstream_ports);
4543 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4545 dp_to_dig_port(intel_dp)->lspcon.active ||
4546 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4547 intel_dp->downstream_ports);
4548 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4549 intel_dp->downstream_ports,
4550 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4552 if (DISPLAY_VER(i915) >= 11) {
4553 /* Let PCON convert from RGB->YCbCr if possible */
4554 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4555 intel_dp->dfp.rgb_to_ycbcr = true;
4556 intel_dp->dfp.ycbcr_444_to_420 = true;
4557 connector->base.ycbcr_420_allowed = true;
4559 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4560 intel_dp->dfp.ycbcr_444_to_420 =
4561 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4563 connector->base.ycbcr_420_allowed =
4564 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4567 /* 4:4:4->4:2:0 conversion is the only way */
4568 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4570 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4573 drm_dbg_kms(&i915->drm,
4574 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4575 connector->base.base.id, connector->base.name,
4576 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4577 str_yes_no(connector->base.ycbcr_420_allowed),
4578 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4582 intel_dp_set_edid(struct intel_dp *intel_dp)
4584 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4585 struct intel_connector *connector = intel_dp->attached_connector;
4589 intel_dp_unset_edid(intel_dp);
4590 edid = intel_dp_get_edid(intel_dp);
4591 connector->detect_edid = edid;
4593 vrr_capable = intel_vrr_is_capable(connector);
4594 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4595 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4596 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4598 intel_dp_update_dfp(intel_dp, edid);
4599 intel_dp_update_420(intel_dp);
4601 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4602 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4603 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4606 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4610 intel_dp_unset_edid(struct intel_dp *intel_dp)
4612 struct intel_connector *connector = intel_dp->attached_connector;
4614 drm_dp_cec_unset_edid(&intel_dp->aux);
4615 kfree(connector->detect_edid);
4616 connector->detect_edid = NULL;
4618 intel_dp->has_hdmi_sink = false;
4619 intel_dp->has_audio = false;
4621 intel_dp->dfp.max_bpc = 0;
4622 intel_dp->dfp.max_dotclock = 0;
4623 intel_dp->dfp.min_tmds_clock = 0;
4624 intel_dp->dfp.max_tmds_clock = 0;
4626 intel_dp->dfp.pcon_max_frl_bw = 0;
4628 intel_dp->dfp.ycbcr_444_to_420 = false;
4629 connector->base.ycbcr_420_allowed = false;
4631 drm_connector_set_vrr_capable_property(&connector->base,
4636 intel_dp_detect(struct drm_connector *connector,
4637 struct drm_modeset_acquire_ctx *ctx,
4640 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4641 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4642 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4643 struct intel_encoder *encoder = &dig_port->base;
4644 enum drm_connector_status status;
4646 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4647 connector->base.id, connector->name);
4648 drm_WARN_ON(&dev_priv->drm,
4649 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4651 if (!INTEL_DISPLAY_ENABLED(dev_priv))
4652 return connector_status_disconnected;
4654 /* Can't disconnect eDP */
4655 if (intel_dp_is_edp(intel_dp))
4656 status = edp_detect(intel_dp);
4657 else if (intel_digital_port_connected(encoder))
4658 status = intel_dp_detect_dpcd(intel_dp);
4660 status = connector_status_disconnected;
4662 if (status == connector_status_disconnected) {
4663 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4664 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4666 if (intel_dp->is_mst) {
4667 drm_dbg_kms(&dev_priv->drm,
4668 "MST device may have disappeared %d vs %d\n",
4670 intel_dp->mst_mgr.mst_state);
4671 intel_dp->is_mst = false;
4672 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4679 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4680 if (DISPLAY_VER(dev_priv) >= 11)
4681 intel_dp_get_dsc_sink_cap(intel_dp);
4683 intel_dp_configure_mst(intel_dp);
4686 * TODO: Reset link params when switching to MST mode, until MST
4687 * supports link training fallback params.
4689 if (intel_dp->reset_link_params || intel_dp->is_mst) {
4690 intel_dp_reset_max_link_params(intel_dp);
4691 intel_dp->reset_link_params = false;
4694 intel_dp_print_rates(intel_dp);
4696 if (intel_dp->is_mst) {
4698 * If we are in MST mode then this connector
4699 * won't appear connected or have anything
4702 status = connector_status_disconnected;
4707 * Some external monitors do not signal loss of link synchronization
4708 * with an IRQ_HPD, so force a link status check.
4710 if (!intel_dp_is_edp(intel_dp)) {
4713 ret = intel_dp_retrain_link(encoder, ctx);
4719 * Clearing NACK and defer counts to get their exact values
4720 * while reading EDID which are required by Compliance tests
4721 * 4.2.2.4 and 4.2.2.5
4723 intel_dp->aux.i2c_nack_count = 0;
4724 intel_dp->aux.i2c_defer_count = 0;
4726 intel_dp_set_edid(intel_dp);
4727 if (intel_dp_is_edp(intel_dp) ||
4728 to_intel_connector(connector)->detect_edid)
4729 status = connector_status_connected;
4731 intel_dp_check_device_service_irq(intel_dp);
4734 if (status != connector_status_connected && !intel_dp->is_mst)
4735 intel_dp_unset_edid(intel_dp);
4738 * Make sure the refs for power wells enabled during detect are
4739 * dropped to avoid a new detect cycle triggered by HPD polling.
4741 intel_display_power_flush_work(dev_priv);
4743 if (!intel_dp_is_edp(intel_dp))
4744 drm_dp_set_subconnector_property(connector,
4747 intel_dp->downstream_ports);
4752 intel_dp_force(struct drm_connector *connector)
4754 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4755 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4756 struct intel_encoder *intel_encoder = &dig_port->base;
4757 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4758 enum intel_display_power_domain aux_domain =
4759 intel_aux_power_domain(dig_port);
4760 intel_wakeref_t wakeref;
4762 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4763 connector->base.id, connector->name);
4764 intel_dp_unset_edid(intel_dp);
4766 if (connector->status != connector_status_connected)
4769 wakeref = intel_display_power_get(dev_priv, aux_domain);
4771 intel_dp_set_edid(intel_dp);
4773 intel_display_power_put(dev_priv, aux_domain, wakeref);
4776 static int intel_dp_get_modes(struct drm_connector *connector)
4778 struct intel_connector *intel_connector = to_intel_connector(connector);
4782 edid = intel_connector->detect_edid;
4784 num_modes = intel_connector_update_modes(connector, edid);
4786 /* Also add fixed mode, which may or may not be present in EDID */
4787 if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4788 num_modes += intel_panel_get_modes(intel_connector);
4794 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4795 struct drm_display_mode *mode;
4797 mode = drm_dp_downstream_mode(connector->dev,
4799 intel_dp->downstream_ports);
4801 drm_mode_probed_add(connector, mode);
4810 intel_dp_connector_register(struct drm_connector *connector)
4812 struct drm_i915_private *i915 = to_i915(connector->dev);
4813 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4814 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4815 struct intel_lspcon *lspcon = &dig_port->lspcon;
4818 ret = intel_connector_register(connector);
4822 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4823 intel_dp->aux.name, connector->kdev->kobj.name);
4825 intel_dp->aux.dev = connector->kdev;
4826 ret = drm_dp_aux_register(&intel_dp->aux);
4828 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4830 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4834 * ToDo: Clean this up to handle lspcon init and resume more
4835 * efficiently and streamlined.
4837 if (lspcon_init(dig_port)) {
4838 lspcon_detect_hdr_capability(lspcon);
4839 if (lspcon->hdr_supported)
4840 drm_connector_attach_hdr_output_metadata_property(connector);
4847 intel_dp_connector_unregister(struct drm_connector *connector)
4849 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4851 drm_dp_cec_unregister_connector(&intel_dp->aux);
4852 drm_dp_aux_unregister(&intel_dp->aux);
4853 intel_connector_unregister(connector);
4856 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4858 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4859 struct intel_dp *intel_dp = &dig_port->dp;
4861 intel_dp_mst_encoder_cleanup(dig_port);
4863 intel_pps_vdd_off_sync(intel_dp);
4865 intel_dp_aux_fini(intel_dp);
4868 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4870 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4872 intel_pps_vdd_off_sync(intel_dp);
4875 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4877 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4879 intel_pps_wait_power_cycle(intel_dp);
4882 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4885 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4886 struct drm_connector_list_iter conn_iter;
4887 struct drm_connector *connector;
4890 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4891 drm_for_each_connector_iter(connector, &conn_iter) {
4892 struct drm_connector_state *conn_state;
4893 struct intel_crtc_state *crtc_state;
4894 struct intel_crtc *crtc;
4896 if (!connector->has_tile ||
4897 connector->tile_group->id != tile_group_id)
4900 conn_state = drm_atomic_get_connector_state(&state->base,
4902 if (IS_ERR(conn_state)) {
4903 ret = PTR_ERR(conn_state);
4907 crtc = to_intel_crtc(conn_state->crtc);
4912 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4913 crtc_state->uapi.mode_changed = true;
4915 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4919 drm_connector_list_iter_end(&conn_iter);
4924 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4926 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4927 struct intel_crtc *crtc;
4929 if (transcoders == 0)
4932 for_each_intel_crtc(&dev_priv->drm, crtc) {
4933 struct intel_crtc_state *crtc_state;
4936 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4937 if (IS_ERR(crtc_state))
4938 return PTR_ERR(crtc_state);
4940 if (!crtc_state->hw.enable)
4943 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4946 crtc_state->uapi.mode_changed = true;
4948 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4952 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4956 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4959 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4964 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4965 struct drm_connector *connector)
4967 const struct drm_connector_state *old_conn_state =
4968 drm_atomic_get_old_connector_state(&state->base, connector);
4969 const struct intel_crtc_state *old_crtc_state;
4970 struct intel_crtc *crtc;
4973 crtc = to_intel_crtc(old_conn_state->crtc);
4977 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4979 if (!old_crtc_state->hw.active)
4982 transcoders = old_crtc_state->sync_mode_slaves_mask;
4983 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4984 transcoders |= BIT(old_crtc_state->master_transcoder);
4986 return intel_modeset_affected_transcoders(state,
4990 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4991 struct drm_atomic_state *_state)
4993 struct drm_i915_private *dev_priv = to_i915(conn->dev);
4994 struct intel_atomic_state *state = to_intel_atomic_state(_state);
4997 ret = intel_digital_connector_atomic_check(conn, &state->base);
5002 * We don't enable port sync on BDW due to missing w/as and
5003 * due to not having adjusted the modeset sequence appropriately.
5005 if (DISPLAY_VER(dev_priv) < 9)
5008 if (!intel_connector_needs_modeset(state, conn))
5011 if (conn->has_tile) {
5012 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5017 return intel_modeset_synced_crtcs(state, conn);
5020 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5022 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5023 struct drm_i915_private *i915 = to_i915(connector->dev);
5025 spin_lock_irq(&i915->irq_lock);
5026 i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
5027 spin_unlock_irq(&i915->irq_lock);
5028 queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
5031 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5032 .force = intel_dp_force,
5033 .fill_modes = drm_helper_probe_single_connector_modes,
5034 .atomic_get_property = intel_digital_connector_atomic_get_property,
5035 .atomic_set_property = intel_digital_connector_atomic_set_property,
5036 .late_register = intel_dp_connector_register,
5037 .early_unregister = intel_dp_connector_unregister,
5038 .destroy = intel_connector_destroy,
5039 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5040 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5041 .oob_hotplug_event = intel_dp_oob_hotplug_event,
5044 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5045 .detect_ctx = intel_dp_detect,
5046 .get_modes = intel_dp_get_modes,
5047 .mode_valid = intel_dp_mode_valid,
5048 .atomic_check = intel_dp_connector_atomic_check,
5052 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5054 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5055 struct intel_dp *intel_dp = &dig_port->dp;
5057 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5058 (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5060 * vdd off can generate a long/short pulse on eDP which
5061 * would require vdd on to handle it, and thus we
5062 * would end up in an endless cycle of
5063 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5065 drm_dbg_kms(&i915->drm,
5066 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5067 long_hpd ? "long" : "short",
5068 dig_port->base.base.base.id,
5069 dig_port->base.base.name);
5073 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5074 dig_port->base.base.base.id,
5075 dig_port->base.base.name,
5076 long_hpd ? "long" : "short");
5079 intel_dp->reset_link_params = true;
5083 if (intel_dp->is_mst) {
5084 if (!intel_dp_check_mst_status(intel_dp))
5086 } else if (!intel_dp_short_pulse(intel_dp)) {
5093 /* check the VBT to see whether the eDP is on another port */
5094 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5097 * eDP not supported on g4x. so bail out early just
5098 * for a bit extra safety in case the VBT is bonkers.
5100 if (DISPLAY_VER(dev_priv) < 5)
5103 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5106 return intel_bios_is_port_edp(dev_priv, port);
5110 has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
5112 if (intel_bios_is_lspcon_present(i915, port))
5115 if (DISPLAY_VER(i915) >= 11)
5121 if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5122 DISPLAY_VER(i915) >= 9)
5129 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5131 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5132 enum port port = dp_to_dig_port(intel_dp)->base.port;
5134 if (!intel_dp_is_edp(intel_dp))
5135 drm_connector_attach_dp_subconnector_property(connector);
5137 if (!IS_G4X(dev_priv) && port != PORT_A)
5138 intel_attach_force_audio_property(connector);
5140 intel_attach_broadcast_rgb_property(connector);
5141 if (HAS_GMCH(dev_priv))
5142 drm_connector_attach_max_bpc_property(connector, 6, 10);
5143 else if (DISPLAY_VER(dev_priv) >= 5)
5144 drm_connector_attach_max_bpc_property(connector, 6, 12);
5146 /* Register HDMI colorspace for case of lspcon */
5147 if (intel_bios_is_lspcon_present(dev_priv, port)) {
5148 drm_connector_attach_content_type_property(connector);
5149 intel_attach_hdmi_colorspace_property(connector);
5151 intel_attach_dp_colorspace_property(connector);
5154 if (has_gamut_metadata_dip(dev_priv, port))
5155 drm_connector_attach_hdr_output_metadata_property(connector);
5157 if (intel_dp_is_edp(intel_dp)) {
5158 u32 allowed_scalers;
5160 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5161 if (!HAS_GMCH(dev_priv))
5162 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5164 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5166 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5170 if (HAS_VRR(dev_priv))
5171 drm_connector_attach_vrr_capable_property(connector);
5175 intel_edp_add_properties(struct intel_dp *intel_dp)
5177 struct intel_connector *connector = intel_dp->attached_connector;
5178 struct drm_i915_private *i915 = to_i915(connector->base.dev);
5179 const struct drm_display_mode *fixed_mode =
5180 intel_panel_preferred_fixed_mode(connector);
5185 drm_connector_set_panel_orientation_with_quirk(&connector->base,
5186 i915->vbt.orientation,
5187 fixed_mode->hdisplay,
5188 fixed_mode->vdisplay);
5191 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5192 struct intel_connector *intel_connector)
5194 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5195 struct drm_device *dev = &dev_priv->drm;
5196 struct drm_connector *connector = &intel_connector->base;
5197 struct drm_display_mode *fixed_mode;
5198 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5200 enum pipe pipe = INVALID_PIPE;
5203 if (!intel_dp_is_edp(intel_dp))
5207 * On IBX/CPT we may get here with LVDS already registered. Since the
5208 * driver uses the only internal power sequencer available for both
5209 * eDP and LVDS bail out early in this case to prevent interfering
5210 * with an already powered-on LVDS power sequencer.
5212 if (intel_get_lvds_encoder(dev_priv)) {
5214 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5215 drm_info(&dev_priv->drm,
5216 "LVDS was detected, not registering eDP\n");
5221 intel_pps_init(intel_dp);
5223 /* Cache DPCD and EDID for edp. */
5224 has_dpcd = intel_edp_init_dpcd(intel_dp);
5227 /* if this fails, presume the device is a ghost */
5228 drm_info(&dev_priv->drm,
5229 "failed to retrieve link info, disabling eDP\n");
5233 mutex_lock(&dev->mode_config.mutex);
5234 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5236 /* Fallback to EDID from ACPI OpRegion, if any */
5237 edid = intel_opregion_get_edid(intel_connector);
5239 drm_dbg_kms(&dev_priv->drm,
5240 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5241 connector->base.id, connector->name);
5244 if (drm_add_edid_modes(connector, edid)) {
5245 drm_connector_update_edid_property(connector, edid);
5248 edid = ERR_PTR(-EINVAL);
5251 edid = ERR_PTR(-ENOENT);
5253 intel_connector->edid = edid;
5255 intel_bios_init_panel(dev_priv, &intel_connector->panel,
5256 encoder->devdata, IS_ERR(edid) ? NULL : edid);
5258 intel_panel_add_edid_fixed_modes(intel_connector,
5259 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
5260 intel_vrr_is_capable(intel_connector));
5262 /* MSO requires information from the EDID */
5263 intel_edp_mso_init(intel_dp);
5265 /* multiply the mode clock and horizontal timings for MSO */
5266 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5267 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5269 /* fallback to VBT if available for eDP */
5270 if (!intel_panel_preferred_fixed_mode(intel_connector))
5271 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5273 mutex_unlock(&dev->mode_config.mutex);
5275 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5277 * Figure out the current pipe for the initial backlight setup.
5278 * If the current pipe isn't valid, try the PPS pipe, and if that
5279 * fails just assume pipe A.
5281 pipe = vlv_active_pipe(intel_dp);
5283 if (pipe != PIPE_A && pipe != PIPE_B)
5284 pipe = intel_dp->pps.pps_pipe;
5286 if (pipe != PIPE_A && pipe != PIPE_B)
5289 drm_dbg_kms(&dev_priv->drm,
5290 "using pipe %c for initial backlight setup\n",
5294 intel_panel_init(intel_connector);
5296 if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
5297 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5298 intel_backlight_setup(intel_connector, pipe);
5300 intel_edp_add_properties(intel_dp);
5302 intel_pps_init_late(intel_dp);
5307 intel_pps_vdd_off_sync(intel_dp);
5312 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5314 struct intel_connector *intel_connector;
5315 struct drm_connector *connector;
5317 intel_connector = container_of(work, typeof(*intel_connector),
5318 modeset_retry_work);
5319 connector = &intel_connector->base;
5320 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5323 /* Grab the locks before changing connector property*/
5324 mutex_lock(&connector->dev->mode_config.mutex);
5325 /* Set connector link status to BAD and send a Uevent to notify
5326 * userspace to do a modeset.
5328 drm_connector_set_link_status_property(connector,
5329 DRM_MODE_LINK_STATUS_BAD);
5330 mutex_unlock(&connector->dev->mode_config.mutex);
5331 /* Send Hotplug uevent so userspace can reprobe */
5332 drm_kms_helper_connector_hotplug_event(connector);
5336 intel_dp_init_connector(struct intel_digital_port *dig_port,
5337 struct intel_connector *intel_connector)
5339 struct drm_connector *connector = &intel_connector->base;
5340 struct intel_dp *intel_dp = &dig_port->dp;
5341 struct intel_encoder *intel_encoder = &dig_port->base;
5342 struct drm_device *dev = intel_encoder->base.dev;
5343 struct drm_i915_private *dev_priv = to_i915(dev);
5344 enum port port = intel_encoder->port;
5345 enum phy phy = intel_port_to_phy(dev_priv, port);
5348 /* Initialize the work for modeset in case of link train failure */
5349 INIT_WORK(&intel_connector->modeset_retry_work,
5350 intel_dp_modeset_retry_work_fn);
5352 if (drm_WARN(dev, dig_port->max_lanes < 1,
5353 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5354 dig_port->max_lanes, intel_encoder->base.base.id,
5355 intel_encoder->base.name))
5358 intel_dp->reset_link_params = true;
5359 intel_dp->pps.pps_pipe = INVALID_PIPE;
5360 intel_dp->pps.active_pipe = INVALID_PIPE;
5362 /* Preserve the current hw state. */
5363 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5364 intel_dp->attached_connector = intel_connector;
5366 if (intel_dp_is_port_edp(dev_priv, port)) {
5368 * Currently we don't support eDP on TypeC ports, although in
5369 * theory it could work on TypeC legacy ports.
5371 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5372 type = DRM_MODE_CONNECTOR_eDP;
5373 intel_encoder->type = INTEL_OUTPUT_EDP;
5375 /* eDP only on port B and/or C on vlv/chv */
5376 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5377 IS_CHERRYVIEW(dev_priv)) &&
5378 port != PORT_B && port != PORT_C))
5381 type = DRM_MODE_CONNECTOR_DisplayPort;
5384 intel_dp_set_default_sink_rates(intel_dp);
5385 intel_dp_set_default_max_sink_lane_count(intel_dp);
5387 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5388 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5390 drm_dbg_kms(&dev_priv->drm,
5391 "Adding %s connector on [ENCODER:%d:%s]\n",
5392 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5393 intel_encoder->base.base.id, intel_encoder->base.name);
5395 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5396 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5398 if (!HAS_GMCH(dev_priv))
5399 connector->interlace_allowed = true;
5400 connector->doublescan_allowed = 0;
5402 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5404 intel_dp_aux_init(intel_dp);
5406 intel_connector_attach_encoder(intel_connector, intel_encoder);
5408 if (HAS_DDI(dev_priv))
5409 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5411 intel_connector->get_hw_state = intel_connector_get_hw_state;
5413 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5414 intel_dp_aux_fini(intel_dp);
5418 intel_dp_set_source_rates(intel_dp);
5419 intel_dp_set_common_rates(intel_dp);
5420 intel_dp_reset_max_link_params(intel_dp);
5422 /* init MST on ports that can support it */
5423 intel_dp_mst_encoder_init(dig_port,
5424 intel_connector->base.base.id);
5426 intel_dp_add_properties(intel_dp, connector);
5428 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5429 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5431 drm_dbg_kms(&dev_priv->drm,
5432 "HDCP init failed, skipping.\n");
5435 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5436 * 0xd. Failure to do so will result in spurious interrupts being
5437 * generated on the port when a cable is not attached.
5439 if (IS_G45(dev_priv)) {
5440 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5441 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5442 (temp & ~0xf) | 0xd);
5445 intel_dp->frl.is_trained = false;
5446 intel_dp->frl.trained_rate_gbps = 0;
5448 intel_psr_init(intel_dp);
5453 drm_connector_cleanup(connector);
5458 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5460 struct intel_encoder *encoder;
5462 if (!HAS_DISPLAY(dev_priv))
5465 for_each_intel_encoder(&dev_priv->drm, encoder) {
5466 struct intel_dp *intel_dp;
5468 if (encoder->type != INTEL_OUTPUT_DDI)
5471 intel_dp = enc_to_intel_dp(encoder);
5473 if (!intel_dp_mst_source_support(intel_dp))
5476 if (intel_dp->is_mst)
5477 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5481 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5483 struct intel_encoder *encoder;
5485 if (!HAS_DISPLAY(dev_priv))
5488 for_each_intel_encoder(&dev_priv->drm, encoder) {
5489 struct intel_dp *intel_dp;
5492 if (encoder->type != INTEL_OUTPUT_DDI)
5495 intel_dp = enc_to_intel_dp(encoder);
5497 if (!intel_dp_mst_source_support(intel_dp))
5500 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5503 intel_dp->is_mst = false;
5504 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,