drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_debugfs.h"
  48 #include "i915_drv.h"
  49 #include "intel_atomic.h"
  50 #include "intel_audio.h"
  51 #include "intel_backlight.h"
  52 #include "intel_combo_phy_regs.h"
  53 #include "intel_connector.h"
  54 #include "intel_crtc.h"
  55 #include "intel_ddi.h"
  56 #include "intel_de.h"
  57 #include "intel_display_types.h"
  58 #include "intel_dp.h"
  59 #include "intel_dp_aux.h"
  60 #include "intel_dp_hdcp.h"
  61 #include "intel_dp_link_training.h"
  62 #include "intel_dp_mst.h"
  63 #include "intel_dpio_phy.h"
  64 #include "intel_dpll.h"
  65 #include "intel_fifo_underrun.h"
  66 #include "intel_hdcp.h"
  67 #include "intel_hdmi.h"
  68 #include "intel_hotplug.h"
  69 #include "intel_lspcon.h"
  70 #include "intel_lvds.h"
  71 #include "intel_panel.h"
  72 #include "intel_pch_display.h"
  73 #include "intel_pps.h"
  74 #include "intel_psr.h"
  75 #include "intel_tc.h"
  76 #include "intel_vdsc.h"
  77 #include "intel_vrr.h"
  78
  79 /* DP DSC throughput values used for slice count calculations KPixels/s */
  80 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  81 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  82 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  83
  84 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  85 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  86
  87 /* Compliance test status bits  */
  88 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  89 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  90 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  91 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  92
  93
  94 /* Constants for DP DSC configurations */
  95 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  96
  97 /* With Single pipe configuration, HW is capable of supporting maximum
  98  * of 4 slices per line.
  99  */
 100 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 101
 102 /**
 103  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 104  * @intel_dp: DP struct
 105  *
 106  * If a CPU or PCH DP output is attached to an eDP panel, this function
 107  * will return true, and false otherwise.
 108  *
 109  * This function is not safe to use prior to encoder type being set.
 110  */
 111 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 112 {
 113         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 114
 115         return dig_port->base.type == INTEL_OUTPUT_EDP;
 116 }
 117
 118 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 119 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 120
 121 /* Is link rate UHBR and thus 128b/132b? */
 122 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 123 {
 124         return crtc_state->port_clock >= 1000000;
 125 }
 126
 127 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 128 {
 129         intel_dp->sink_rates[0] = 162000;
 130         intel_dp->num_sink_rates = 1;
 131 }
 132
 133 /* update sink rates from dpcd */
 134 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 135 {
 136         static const int dp_rates[] = {
 137                 162000, 270000, 540000, 810000
 138         };
 139         int i, max_rate;
 140         int max_lttpr_rate;
 141
 142         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 143                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 144                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 145
 146                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 147                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 148
 149                 return;
 150         }
 151
 152         /*
 153          * Sink rates for 8b/10b.
 154          */
 155         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 156         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 157         if (max_lttpr_rate)
 158                 max_rate = min(max_rate, max_lttpr_rate);
 159
 160         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 161                 if (dp_rates[i] > max_rate)
 162                         break;
 163                 intel_dp->sink_rates[i] = dp_rates[i];
 164         }
 165
 166         /*
 167          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 168          * rates and 10 Gbps.
 169          */
 170         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 171                 u8 uhbr_rates = 0;
 172
 173                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 174
 175                 drm_dp_dpcd_readb(&intel_dp->aux,
 176                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 177
 178                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 179                         /* We have a repeater */
 180                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 181                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 182                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 183                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 184                                 /* Repeater supports 128b/132b, valid UHBR rates */
 185                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 186                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 187                         } else {
 188                                 /* Does not support 128b/132b */
 189                                 uhbr_rates = 0;
 190                         }
 191                 }
 192
 193                 if (uhbr_rates & DP_UHBR10)
 194                         intel_dp->sink_rates[i++] = 1000000;
 195                 if (uhbr_rates & DP_UHBR13_5)
 196                         intel_dp->sink_rates[i++] = 1350000;
 197                 if (uhbr_rates & DP_UHBR20)
 198                         intel_dp->sink_rates[i++] = 2000000;
 199         }
 200
 201         intel_dp->num_sink_rates = i;
 202 }
 203
 204 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 205 {
 206         struct intel_connector *connector = intel_dp->attached_connector;
 207         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 208         struct intel_encoder *encoder = &intel_dig_port->base;
 209
 210         intel_dp_set_dpcd_sink_rates(intel_dp);
 211
 212         if (intel_dp->num_sink_rates)
 213                 return;
 214
 215         drm_err(&dp_to_i915(intel_dp)->drm,
 216                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 217                 connector->base.base.id, connector->base.name,
 218                 encoder->base.base.id, encoder->base.name);
 219
 220         intel_dp_set_default_sink_rates(intel_dp);
 221 }
 222
 223 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 224 {
 225         intel_dp->max_sink_lane_count = 1;
 226 }
 227
 228 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 229 {
 230         struct intel_connector *connector = intel_dp->attached_connector;
 231         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 232         struct intel_encoder *encoder = &intel_dig_port->base;
 233
 234         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 235
 236         switch (intel_dp->max_sink_lane_count) {
 237         case 1:
 238         case 2:
 239         case 4:
 240                 return;
 241         }
 242
 243         drm_err(&dp_to_i915(intel_dp)->drm,
 244                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 245                 connector->base.base.id, connector->base.name,
 246                 encoder->base.base.id, encoder->base.name,
 247                 intel_dp->max_sink_lane_count);
 248
 249         intel_dp_set_default_max_sink_lane_count(intel_dp);
 250 }
 251
 252 /* Get length of rates array potentially limited by max_rate. */
 253 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 254 {
 255         int i;
 256
 257         /* Limit results by potentially reduced max rate */
 258         for (i = 0; i < len; i++) {
 259                 if (rates[len - i - 1] <= max_rate)
 260                         return len - i;
 261         }
 262
 263         return 0;
 264 }
 265
 266 /* Get length of common rates array potentially limited by max_rate. */
 267 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 268                                           int max_rate)
 269 {
 270         return intel_dp_rate_limit_len(intel_dp->common_rates,
 271                                        intel_dp->num_common_rates, max_rate);
 272 }
 273
 274 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 275 {
 276         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 277                         index < 0 || index >= intel_dp->num_common_rates))
 278                 return 162000;
 279
 280         return intel_dp->common_rates[index];
 281 }
 282
 283 /* Theoretical max between source and sink */
 284 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 285 {
 286         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 287 }
 288
 289 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 290 {
 291         int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
 292         int max_lanes = dig_port->max_lanes;
 293
 294         if (vbt_max_lanes)
 295                 max_lanes = min(max_lanes, vbt_max_lanes);
 296
 297         return max_lanes;
 298 }
 299
 300 /* Theoretical max between source and sink */
 301 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 302 {
 303         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 304         int source_max = intel_dp_max_source_lane_count(dig_port);
 305         int sink_max = intel_dp->max_sink_lane_count;
 306         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 307         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 308
 309         if (lttpr_max)
 310                 sink_max = min(sink_max, lttpr_max);
 311
 312         return min3(source_max, sink_max, fia_max);
 313 }
 314
 315 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 316 {
 317         switch (intel_dp->max_link_lane_count) {
 318         case 1:
 319         case 2:
 320         case 4:
 321                 return intel_dp->max_link_lane_count;
 322         default:
 323                 MISSING_CASE(intel_dp->max_link_lane_count);
 324                 return 1;
 325         }
 326 }
 327
 328 /*
 329  * The required data bandwidth for a mode with given pixel clock and bpp. This
 330  * is the required net bandwidth independent of the data bandwidth efficiency.
 331  */
 332 int
 333 intel_dp_link_required(int pixel_clock, int bpp)
 334 {
 335         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 336         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 337 }
 338
 339 /*
 340  * Given a link rate and lanes, get the data bandwidth.
 341  *
 342  * Data bandwidth is the actual payload rate, which depends on the data
 343  * bandwidth efficiency and the link rate.
 344  *
 345  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 346  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 347  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 348  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 349  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 350  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 351  *
 352  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 353  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 354  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 355  * does not match the symbol clock, the port clock (not even if you think in
 356  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 357  * rate in units of 10000 bps.
 358  */
 359 int
 360 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 361 {
 362         if (max_link_rate >= 1000000) {
 363                 /*
 364                  * UHBR rates always use 128b/132b channel encoding, and have
 365                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 366                  * link bit rate in units of 10000 bps.
 367                  */
 368                 int max_link_rate_kbps = max_link_rate * 10;
 369
 370                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 371                 max_link_rate = max_link_rate_kbps / 8;
 372         }
 373
 374         /*
 375          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 376          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 377          * out to be a nop by coincidence, and can be skipped:
 378          *
 379          *      int max_link_rate_kbps = max_link_rate * 10;
 380          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 381          *      max_link_rate = max_link_rate_kbps / 8;
 382          */
 383
 384         return max_link_rate * max_lanes;
 385 }
 386
 387 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 388 {
 389         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 390         struct intel_encoder *encoder = &intel_dig_port->base;
 391         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 392
 393         return DISPLAY_VER(dev_priv) >= 12 ||
 394                 (DISPLAY_VER(dev_priv) == 11 &&
 395                  encoder->port != PORT_A);
 396 }
 397
 398 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 399 {
 400         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 401 }
 402
 403 static int icl_max_source_rate(struct intel_dp *intel_dp)
 404 {
 405         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 406         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 407         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 408
 409         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 410                 return 540000;
 411
 412         return 810000;
 413 }
 414
 415 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 416 {
 417         if (intel_dp_is_edp(intel_dp))
 418                 return 540000;
 419
 420         return 810000;
 421 }
 422
 423 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 424 {
 425         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 426         int max_rate;
 427
 428         max_rate = intel_bios_dp_max_link_rate(encoder);
 429
 430         if (intel_dp_is_edp(intel_dp)) {
 431                 struct intel_connector *connector = intel_dp->attached_connector;
 432                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 433
 434                 if (max_rate && edp_max_rate)
 435                         max_rate = min(max_rate, edp_max_rate);
 436                 else if (edp_max_rate)
 437                         max_rate = edp_max_rate;
 438         }
 439
 440         return max_rate;
 441 }
 442
 443 static void
 444 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 445 {
 446         /* The values must be in increasing order */
 447         static const int icl_rates[] = {
 448                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 449                 1000000, 1350000,
 450         };
 451         static const int bxt_rates[] = {
 452                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 453         };
 454         static const int skl_rates[] = {
 455                 162000, 216000, 270000, 324000, 432000, 540000
 456         };
 457         static const int hsw_rates[] = {
 458                 162000, 270000, 540000
 459         };
 460         static const int g4x_rates[] = {
 461                 162000, 270000
 462         };
 463         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 464         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 465         const int *source_rates;
 466         int size, max_rate = 0, vbt_max_rate;
 467
 468         /* This should only be done once */
 469         drm_WARN_ON(&dev_priv->drm,
 470                     intel_dp->source_rates || intel_dp->num_source_rates);
 471
 472         if (DISPLAY_VER(dev_priv) >= 11) {
 473                 source_rates = icl_rates;
 474                 size = ARRAY_SIZE(icl_rates);
 475                 if (IS_DG2(dev_priv))
 476                         max_rate = dg2_max_source_rate(intel_dp);
 477                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 478                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 479                         max_rate = 810000;
 480                 else if (IS_JSL_EHL(dev_priv))
 481                         max_rate = ehl_max_source_rate(intel_dp);
 482                 else
 483                         max_rate = icl_max_source_rate(intel_dp);
 484         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 485                 source_rates = bxt_rates;
 486                 size = ARRAY_SIZE(bxt_rates);
 487         } else if (DISPLAY_VER(dev_priv) == 9) {
 488                 source_rates = skl_rates;
 489                 size = ARRAY_SIZE(skl_rates);
 490         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 491                    IS_BROADWELL(dev_priv)) {
 492                 source_rates = hsw_rates;
 493                 size = ARRAY_SIZE(hsw_rates);
 494         } else {
 495                 source_rates = g4x_rates;
 496                 size = ARRAY_SIZE(g4x_rates);
 497         }
 498
 499         vbt_max_rate = vbt_max_link_rate(intel_dp);
 500         if (max_rate && vbt_max_rate)
 501                 max_rate = min(max_rate, vbt_max_rate);
 502         else if (vbt_max_rate)
 503                 max_rate = vbt_max_rate;
 504
 505         if (max_rate)
 506                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 507
 508         intel_dp->source_rates = source_rates;
 509         intel_dp->num_source_rates = size;
 510 }
 511
 512 static int intersect_rates(const int *source_rates, int source_len,
 513                            const int *sink_rates, int sink_len,
 514                            int *common_rates)
 515 {
 516         int i = 0, j = 0, k = 0;
 517
 518         while (i < source_len && j < sink_len) {
 519                 if (source_rates[i] == sink_rates[j]) {
 520                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 521                                 return k;
 522                         common_rates[k] = source_rates[i];
 523                         ++k;
 524                         ++i;
 525                         ++j;
 526                 } else if (source_rates[i] < sink_rates[j]) {
 527                         ++i;
 528                 } else {
 529                         ++j;
 530                 }
 531         }
 532         return k;
 533 }
 534
 535 /* return index of rate in rates array, or -1 if not found */
 536 static int intel_dp_rate_index(const int *rates, int len, int rate)
 537 {
 538         int i;
 539
 540         for (i = 0; i < len; i++)
 541                 if (rate == rates[i])
 542                         return i;
 543
 544         return -1;
 545 }
 546
 547 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 548 {
 549         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 550
 551         drm_WARN_ON(&i915->drm,
 552                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 553
 554         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 555                                                      intel_dp->num_source_rates,
 556                                                      intel_dp->sink_rates,
 557                                                      intel_dp->num_sink_rates,
 558                                                      intel_dp->common_rates);
 559
 560         /* Paranoia, there should always be something in common. */
 561         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 562                 intel_dp->common_rates[0] = 162000;
 563                 intel_dp->num_common_rates = 1;
 564         }
 565 }
 566
 567 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 568                                        u8 lane_count)
 569 {
 570         /*
 571          * FIXME: we need to synchronize the current link parameters with
 572          * hardware readout. Currently fast link training doesn't work on
 573          * boot-up.
 574          */
 575         if (link_rate == 0 ||
 576             link_rate > intel_dp->max_link_rate)
 577                 return false;
 578
 579         if (lane_count == 0 ||
 580             lane_count > intel_dp_max_lane_count(intel_dp))
 581                 return false;
 582
 583         return true;
 584 }
 585
 586 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 587                                                      int link_rate,
 588                                                      u8 lane_count)
 589 {
 590         /* FIXME figure out what we actually want here */
 591         const struct drm_display_mode *fixed_mode =
 592                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 593         int mode_rate, max_rate;
 594
 595         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 596         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 597         if (mode_rate > max_rate)
 598                 return false;
 599
 600         return true;
 601 }
 602
 603 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 604                                             int link_rate, u8 lane_count)
 605 {
 606         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 607         int index;
 608
 609         /*
 610          * TODO: Enable fallback on MST links once MST link compute can handle
 611          * the fallback params.
 612          */
 613         if (intel_dp->is_mst) {
 614                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 615                 return -1;
 616         }
 617
 618         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 619                 drm_dbg_kms(&i915->drm,
 620                             "Retrying Link training for eDP with max parameters\n");
 621                 intel_dp->use_max_params = true;
 622                 return 0;
 623         }
 624
 625         index = intel_dp_rate_index(intel_dp->common_rates,
 626                                     intel_dp->num_common_rates,
 627                                     link_rate);
 628         if (index > 0) {
 629                 if (intel_dp_is_edp(intel_dp) &&
 630                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 631                                                               intel_dp_common_rate(intel_dp, index - 1),
 632                                                               lane_count)) {
 633                         drm_dbg_kms(&i915->drm,
 634                                     "Retrying Link training for eDP with same parameters\n");
 635                         return 0;
 636                 }
 637                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 638                 intel_dp->max_link_lane_count = lane_count;
 639         } else if (lane_count > 1) {
 640                 if (intel_dp_is_edp(intel_dp) &&
 641                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 642                                                               intel_dp_max_common_rate(intel_dp),
 643                                                               lane_count >> 1)) {
 644                         drm_dbg_kms(&i915->drm,
 645                                     "Retrying Link training for eDP with same parameters\n");
 646                         return 0;
 647                 }
 648                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 649                 intel_dp->max_link_lane_count = lane_count >> 1;
 650         } else {
 651                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 652                 return -1;
 653         }
 654
 655         return 0;
 656 }
 657
 658 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 659 {
 660         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 661                        DP_DSC_FEC_OVERHEAD_FACTOR);
 662 }
 663
 664 static int
 665 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 666 {
 667         if (DISPLAY_VER(i915) >= 13)
 668                 return 17280 * 8;
 669         else if (DISPLAY_VER(i915) >= 11)
 670                 return 7680 * 8;
 671         else
 672                 return 6144 * 8;
 673 }
 674
 675 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 676                                        u32 link_clock, u32 lane_count,
 677                                        u32 mode_clock, u32 mode_hdisplay,
 678                                        bool bigjoiner,
 679                                        u32 pipe_bpp)
 680 {
 681         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 682         int i;
 683
 684         /*
 685          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 686          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 687          * for SST -> TimeSlotsPerMTP is 1,
 688          * for MST -> TimeSlotsPerMTP has to be calculated
 689          */
 690         bits_per_pixel = (link_clock * lane_count * 8) /
 691                          intel_dp_mode_to_fec_clock(mode_clock);
 692
 693         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 694         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 695                 mode_hdisplay;
 696
 697         if (bigjoiner)
 698                 max_bpp_small_joiner_ram *= 2;
 699
 700         /*
 701          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 702          * check, output bpp from small joiner RAM check)
 703          */
 704         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 705
 706         if (bigjoiner) {
 707                 u32 max_bpp_bigjoiner =
 708                         i915->display.cdclk.max_cdclk_freq * 48 /
 709                         intel_dp_mode_to_fec_clock(mode_clock);
 710
 711                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 712         }
 713
 714         /* Error out if the max bpp is less than smallest allowed valid bpp */
 715         if (bits_per_pixel < valid_dsc_bpp[0]) {
 716                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 717                             bits_per_pixel, valid_dsc_bpp[0]);
 718                 return 0;
 719         }
 720
 721         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 722         if (DISPLAY_VER(i915) >= 13) {
 723                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 724         } else {
 725                 /* Find the nearest match in the array of known BPPs from VESA */
 726                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 727                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 728                                 break;
 729                 }
 730                 bits_per_pixel = valid_dsc_bpp[i];
 731         }
 732
 733         /*
 734          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 735          * fractional part is 0
 736          */
 737         return bits_per_pixel << 4;
 738 }
 739
 740 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 741                                        int mode_clock, int mode_hdisplay,
 742                                        bool bigjoiner)
 743 {
 744         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 745         u8 min_slice_count, i;
 746         int max_slice_width;
 747
 748         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 749                 min_slice_count = DIV_ROUND_UP(mode_clock,
 750                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 751         else
 752                 min_slice_count = DIV_ROUND_UP(mode_clock,
 753                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 754
 755         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 756         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 757                 drm_dbg_kms(&i915->drm,
 758                             "Unsupported slice width %d by DP DSC Sink device\n",
 759                             max_slice_width);
 760                 return 0;
 761         }
 762         /* Also take into account max slice width */
 763         min_slice_count = max_t(u8, min_slice_count,
 764                                 DIV_ROUND_UP(mode_hdisplay,
 765                                              max_slice_width));
 766
 767         /* Find the closest match to the valid slice count values */
 768         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 769                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 770
 771                 if (test_slice_count >
 772                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 773                         break;
 774
 775                 /* big joiner needs small joiner to be enabled */
 776                 if (bigjoiner && test_slice_count < 4)
 777                         continue;
 778
 779                 if (min_slice_count <= test_slice_count)
 780                         return test_slice_count;
 781         }
 782
 783         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 784                     min_slice_count);
 785         return 0;
 786 }
 787
 788 static enum intel_output_format
 789 intel_dp_output_format(struct intel_connector *connector,
 790                        bool ycbcr_420_output)
 791 {
 792         struct intel_dp *intel_dp = intel_attached_dp(connector);
 793
 794         if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 795                 return INTEL_OUTPUT_FORMAT_RGB;
 796
 797         if (intel_dp->dfp.rgb_to_ycbcr &&
 798             intel_dp->dfp.ycbcr_444_to_420)
 799                 return INTEL_OUTPUT_FORMAT_RGB;
 800
 801         if (intel_dp->dfp.ycbcr_444_to_420)
 802                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 803         else
 804                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 805 }
 806
 807 int intel_dp_min_bpp(enum intel_output_format output_format)
 808 {
 809         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 810                 return 6 * 3;
 811         else
 812                 return 8 * 3;
 813 }
 814
 815 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 816 {
 817         /*
 818          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 819          * format of the number of bytes per pixel will be half the number
 820          * of bytes of RGB pixel.
 821          */
 822         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 823                 bpp /= 2;
 824
 825         return bpp;
 826 }
 827
 828 static int
 829 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 830                              const struct drm_display_mode *mode)
 831 {
 832         const struct drm_display_info *info = &connector->base.display_info;
 833         enum intel_output_format output_format =
 834                 intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
 835
 836         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 837 }
 838
 839 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 840                                   int hdisplay)
 841 {
 842         /*
 843          * Older platforms don't like hdisplay==4096 with DP.
 844          *
 845          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 846          * and frame counter increment), but we don't get vblank interrupts,
 847          * and the pipe underruns immediately. The link also doesn't seem
 848          * to get trained properly.
 849          *
 850          * On CHV the vblank interrupts don't seem to disappear but
 851          * otherwise the symptoms are similar.
 852          *
 853          * TODO: confirm the behaviour on HSW+
 854          */
 855         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 856 }
 857
 858 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
 859 {
 860         struct intel_connector *connector = intel_dp->attached_connector;
 861         const struct drm_display_info *info = &connector->base.display_info;
 862         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
 863
 864         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
 865         if (max_tmds_clock && info->max_tmds_clock)
 866                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
 867
 868         return max_tmds_clock;
 869 }
 870
 871 static enum drm_mode_status
 872 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
 873                           int clock, int bpc, bool ycbcr420_output,
 874                           bool respect_downstream_limits)
 875 {
 876         int tmds_clock, min_tmds_clock, max_tmds_clock;
 877
 878         if (!respect_downstream_limits)
 879                 return MODE_OK;
 880
 881         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 882
 883         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
 884         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
 885
 886         if (min_tmds_clock && tmds_clock < min_tmds_clock)
 887                 return MODE_CLOCK_LOW;
 888
 889         if (max_tmds_clock && tmds_clock > max_tmds_clock)
 890                 return MODE_CLOCK_HIGH;
 891
 892         return MODE_OK;
 893 }
 894
 895 static enum drm_mode_status
 896 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 897                                const struct drm_display_mode *mode,
 898                                int target_clock)
 899 {
 900         struct intel_dp *intel_dp = intel_attached_dp(connector);
 901         const struct drm_display_info *info = &connector->base.display_info;
 902         enum drm_mode_status status;
 903         bool ycbcr_420_only;
 904
 905         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 906         if (intel_dp->dfp.pcon_max_frl_bw) {
 907                 int target_bw;
 908                 int max_frl_bw;
 909                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
 910
 911                 target_bw = bpp * target_clock;
 912
 913                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 914
 915                 /* converting bw from Gbps to Kbps*/
 916                 max_frl_bw = max_frl_bw * 1000000;
 917
 918                 if (target_bw > max_frl_bw)
 919                         return MODE_CLOCK_HIGH;
 920
 921                 return MODE_OK;
 922         }
 923
 924         if (intel_dp->dfp.max_dotclock &&
 925             target_clock > intel_dp->dfp.max_dotclock)
 926                 return MODE_CLOCK_HIGH;
 927
 928         ycbcr_420_only = drm_mode_is_420_only(info, mode);
 929
 930         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 931         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 932                                            8, ycbcr_420_only, true);
 933
 934         if (status != MODE_OK) {
 935                 if (ycbcr_420_only ||
 936                     !connector->base.ycbcr_420_allowed ||
 937                     !drm_mode_is_420_also(info, mode))
 938                         return status;
 939
 940                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 941                                                    8, true, true);
 942                 if (status != MODE_OK)
 943                         return status;
 944         }
 945
 946         return MODE_OK;
 947 }
 948
 949 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 950                                     int hdisplay, int clock)
 951 {
 952         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 953
 954         if (!intel_dp_can_bigjoiner(intel_dp))
 955                 return false;
 956
 957         return clock > i915->max_dotclk_freq || hdisplay > 5120;
 958 }
 959
 960 static enum drm_mode_status
 961 intel_dp_mode_valid(struct drm_connector *_connector,
 962                     struct drm_display_mode *mode)
 963 {
 964         struct intel_connector *connector = to_intel_connector(_connector);
 965         struct intel_dp *intel_dp = intel_attached_dp(connector);
 966         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 967         const struct drm_display_mode *fixed_mode;
 968         int target_clock = mode->clock;
 969         int max_rate, mode_rate, max_lanes, max_link_clock;
 970         int max_dotclk = dev_priv->max_dotclk_freq;
 971         u16 dsc_max_output_bpp = 0;
 972         u8 dsc_slice_count = 0;
 973         enum drm_mode_status status;
 974         bool dsc = false, bigjoiner = false;
 975
 976         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 977                 return MODE_NO_DBLESCAN;
 978
 979         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 980                 return MODE_H_ILLEGAL;
 981
 982         fixed_mode = intel_panel_fixed_mode(connector, mode);
 983         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 984                 status = intel_panel_mode_valid(connector, mode);
 985                 if (status != MODE_OK)
 986                         return status;
 987
 988                 target_clock = fixed_mode->clock;
 989         }
 990
 991         if (mode->clock < 10000)
 992                 return MODE_CLOCK_LOW;
 993
 994         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 995                 bigjoiner = true;
 996                 max_dotclk *= 2;
 997         }
 998         if (target_clock > max_dotclk)
 999                 return MODE_CLOCK_HIGH;
1000
1001         max_link_clock = intel_dp_max_link_rate(intel_dp);
1002         max_lanes = intel_dp_max_lane_count(intel_dp);
1003
1004         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1005         mode_rate = intel_dp_link_required(target_clock,
1006                                            intel_dp_mode_min_output_bpp(connector, mode));
1007
1008         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1009                 return MODE_H_ILLEGAL;
1010
1011         /*
1012          * Output bpp is stored in 6.4 format so right shift by 4 to get the
1013          * integer value since we support only integer values of bpp.
1014          */
1015         if (DISPLAY_VER(dev_priv) >= 10 &&
1016             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1017                 /*
1018                  * TBD pass the connector BPC,
1019                  * for now U8_MAX so that max BPC on that platform would be picked
1020                  */
1021                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1022
1023                 if (intel_dp_is_edp(intel_dp)) {
1024                         dsc_max_output_bpp =
1025                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1026                         dsc_slice_count =
1027                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1028                                                                 true);
1029                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1030                         dsc_max_output_bpp =
1031                                 intel_dp_dsc_get_output_bpp(dev_priv,
1032                                                             max_link_clock,
1033                                                             max_lanes,
1034                                                             target_clock,
1035                                                             mode->hdisplay,
1036                                                             bigjoiner,
1037                                                             pipe_bpp) >> 4;
1038                         dsc_slice_count =
1039                                 intel_dp_dsc_get_slice_count(intel_dp,
1040                                                              target_clock,
1041                                                              mode->hdisplay,
1042                                                              bigjoiner);
1043                 }
1044
1045                 dsc = dsc_max_output_bpp && dsc_slice_count;
1046         }
1047
1048         /*
1049          * Big joiner configuration needs DSC for TGL which is not true for
1050          * XE_LPD where uncompressed joiner is supported.
1051          */
1052         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1053                 return MODE_CLOCK_HIGH;
1054
1055         if (mode_rate > max_rate && !dsc)
1056                 return MODE_CLOCK_HIGH;
1057
1058         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1059         if (status != MODE_OK)
1060                 return status;
1061
1062         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1063 }
1064
1065 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1066 {
1067         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1068 }
1069
1070 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1071 {
1072         return DISPLAY_VER(i915) >= 10;
1073 }
1074
1075 static void snprintf_int_array(char *str, size_t len,
1076                                const int *array, int nelem)
1077 {
1078         int i;
1079
1080         str[0] = '\0';
1081
1082         for (i = 0; i < nelem; i++) {
1083                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1084                 if (r >= len)
1085                         return;
1086                 str += r;
1087                 len -= r;
1088         }
1089 }
1090
1091 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1092 {
1093         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1094         char str[128]; /* FIXME: too big for stack? */
1095
1096         if (!drm_debug_enabled(DRM_UT_KMS))
1097                 return;
1098
1099         snprintf_int_array(str, sizeof(str),
1100                            intel_dp->source_rates, intel_dp->num_source_rates);
1101         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1102
1103         snprintf_int_array(str, sizeof(str),
1104                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1105         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1106
1107         snprintf_int_array(str, sizeof(str),
1108                            intel_dp->common_rates, intel_dp->num_common_rates);
1109         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1110 }
1111
1112 int
1113 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1114 {
1115         int len;
1116
1117         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1118
1119         return intel_dp_common_rate(intel_dp, len - 1);
1120 }
1121
1122 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1123 {
1124         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1125         int i = intel_dp_rate_index(intel_dp->sink_rates,
1126                                     intel_dp->num_sink_rates, rate);
1127
1128         if (drm_WARN_ON(&i915->drm, i < 0))
1129                 i = 0;
1130
1131         return i;
1132 }
1133
1134 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1135                            u8 *link_bw, u8 *rate_select)
1136 {
1137         /* eDP 1.4 rate select method. */
1138         if (intel_dp->use_rate_select) {
1139                 *link_bw = 0;
1140                 *rate_select =
1141                         intel_dp_rate_select(intel_dp, port_clock);
1142         } else {
1143                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1144                 *rate_select = 0;
1145         }
1146 }
1147
1148 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1149                                          const struct intel_crtc_state *pipe_config)
1150 {
1151         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1152
1153         /* On TGL, FEC is supported on all Pipes */
1154         if (DISPLAY_VER(dev_priv) >= 12)
1155                 return true;
1156
1157         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1158                 return true;
1159
1160         return false;
1161 }
1162
1163 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1164                                   const struct intel_crtc_state *pipe_config)
1165 {
1166         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1167                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1168 }
1169
1170 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1171                                   const struct intel_crtc_state *crtc_state)
1172 {
1173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1174                 return false;
1175
1176         return intel_dsc_source_support(crtc_state) &&
1177                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1178 }
1179
1180 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1181                                  const struct intel_crtc_state *crtc_state)
1182 {
1183         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1184                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1185                  intel_dp->dfp.ycbcr_444_to_420);
1186 }
1187
1188 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1189                                      const struct intel_crtc_state *crtc_state,
1190                                      int bpc, bool respect_downstream_limits)
1191 {
1192         bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1193         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1194
1195         /*
1196          * Current bpc could already be below 8bpc due to
1197          * FDI bandwidth constraints or other limits.
1198          * HDMI minimum is 8bpc however.
1199          */
1200         bpc = max(bpc, 8);
1201
1202         /*
1203          * We will never exceed downstream TMDS clock limits while
1204          * attempting deep color. If the user insists on forcing an
1205          * out of spec mode they will have to be satisfied with 8bpc.
1206          */
1207         if (!respect_downstream_limits)
1208                 bpc = 8;
1209
1210         for (; bpc >= 8; bpc -= 2) {
1211                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1212                                             intel_dp->has_hdmi_sink, ycbcr420_output) &&
1213                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1214                                               respect_downstream_limits) == MODE_OK)
1215                         return bpc;
1216         }
1217
1218         return -EINVAL;
1219 }
1220
1221 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1222                             const struct intel_crtc_state *crtc_state,
1223                             bool respect_downstream_limits)
1224 {
1225         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1226         struct intel_connector *intel_connector = intel_dp->attached_connector;
1227         int bpp, bpc;
1228
1229         bpc = crtc_state->pipe_bpp / 3;
1230
1231         if (intel_dp->dfp.max_bpc)
1232                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1233
1234         if (intel_dp->dfp.min_tmds_clock) {
1235                 int max_hdmi_bpc;
1236
1237                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1238                                                          respect_downstream_limits);
1239                 if (max_hdmi_bpc < 0)
1240                         return 0;
1241
1242                 bpc = min(bpc, max_hdmi_bpc);
1243         }
1244
1245         bpp = bpc * 3;
1246         if (intel_dp_is_edp(intel_dp)) {
1247                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1248                 if (intel_connector->base.display_info.bpc == 0 &&
1249                     intel_connector->panel.vbt.edp.bpp &&
1250                     intel_connector->panel.vbt.edp.bpp < bpp) {
1251                         drm_dbg_kms(&dev_priv->drm,
1252                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1253                                     intel_connector->panel.vbt.edp.bpp);
1254                         bpp = intel_connector->panel.vbt.edp.bpp;
1255                 }
1256         }
1257
1258         return bpp;
1259 }
1260
1261 /* Adjust link config limits based on compliance test requests. */
1262 void
1263 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1264                                   struct intel_crtc_state *pipe_config,
1265                                   struct link_config_limits *limits)
1266 {
1267         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1268
1269         /* For DP Compliance we override the computed bpp for the pipe */
1270         if (intel_dp->compliance.test_data.bpc != 0) {
1271                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1272
1273                 limits->min_bpp = limits->max_bpp = bpp;
1274                 pipe_config->dither_force_disable = bpp == 6 * 3;
1275
1276                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1277         }
1278
1279         /* Use values requested by Compliance Test Request */
1280         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1281                 int index;
1282
1283                 /* Validate the compliance test data since max values
1284                  * might have changed due to link train fallback.
1285                  */
1286                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1287                                                intel_dp->compliance.test_lane_count)) {
1288                         index = intel_dp_rate_index(intel_dp->common_rates,
1289                                                     intel_dp->num_common_rates,
1290                                                     intel_dp->compliance.test_link_rate);
1291                         if (index >= 0)
1292                                 limits->min_rate = limits->max_rate =
1293                                         intel_dp->compliance.test_link_rate;
1294                         limits->min_lane_count = limits->max_lane_count =
1295                                 intel_dp->compliance.test_lane_count;
1296                 }
1297         }
1298 }
1299
1300 static bool has_seamless_m_n(struct intel_connector *connector)
1301 {
1302         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1303
1304         /*
1305          * Seamless M/N reprogramming only implemented
1306          * for BDW+ double buffered M/N registers so far.
1307          */
1308         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1309                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1310 }
1311
1312 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1313                                const struct drm_connector_state *conn_state)
1314 {
1315         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1316         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1317
1318         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1319         if (has_seamless_m_n(connector))
1320                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1321         else
1322                 return adjusted_mode->crtc_clock;
1323 }
1324
1325 /* Optimize link config in order: max bpp, min clock, min lanes */
1326 static int
1327 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1328                                   struct intel_crtc_state *pipe_config,
1329                                   const struct drm_connector_state *conn_state,
1330                                   const struct link_config_limits *limits)
1331 {
1332         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1333         int mode_rate, link_rate, link_avail;
1334
1335         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1336                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1337
1338                 mode_rate = intel_dp_link_required(clock, output_bpp);
1339
1340                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1341                         link_rate = intel_dp_common_rate(intel_dp, i);
1342                         if (link_rate < limits->min_rate ||
1343                             link_rate > limits->max_rate)
1344                                 continue;
1345
1346                         for (lane_count = limits->min_lane_count;
1347                              lane_count <= limits->max_lane_count;
1348                              lane_count <<= 1) {
1349                                 link_avail = intel_dp_max_data_rate(link_rate,
1350                                                                     lane_count);
1351
1352                                 if (mode_rate <= link_avail) {
1353                                         pipe_config->lane_count = lane_count;
1354                                         pipe_config->pipe_bpp = bpp;
1355                                         pipe_config->port_clock = link_rate;
1356
1357                                         return 0;
1358                                 }
1359                         }
1360                 }
1361         }
1362
1363         return -EINVAL;
1364 }
1365
1366 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1367 {
1368         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1369         int i, num_bpc;
1370         u8 dsc_bpc[3] = {0};
1371         u8 dsc_max_bpc;
1372
1373         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1374         if (DISPLAY_VER(i915) >= 12)
1375                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1376         else
1377                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1378
1379         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1380                                                        dsc_bpc);
1381         for (i = 0; i < num_bpc; i++) {
1382                 if (dsc_max_bpc >= dsc_bpc[i])
1383                         return dsc_bpc[i] * 3;
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1390 {
1391         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1392
1393         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1394 }
1395
1396 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1397 {
1398         return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1399                 DP_DSC_MINOR_SHIFT;
1400 }
1401
1402 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1403                                        struct intel_crtc_state *crtc_state)
1404 {
1405         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1406         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1407         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1408         u8 line_buf_depth;
1409         int ret;
1410
1411         /*
1412          * RC_MODEL_SIZE is currently a constant across all configurations.
1413          *
1414          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1415          * DP_DSC_RC_BUF_SIZE for this.
1416          */
1417         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1418         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1419
1420         /*
1421          * Slice Height of 8 works for all currently available panels. So start
1422          * with that if pic_height is an integral multiple of 8. Eventually add
1423          * logic to try multiple slice heights.
1424          */
1425         if (vdsc_cfg->pic_height % 8 == 0)
1426                 vdsc_cfg->slice_height = 8;
1427         else if (vdsc_cfg->pic_height % 4 == 0)
1428                 vdsc_cfg->slice_height = 4;
1429         else
1430                 vdsc_cfg->slice_height = 2;
1431
1432         ret = intel_dsc_compute_params(crtc_state);
1433         if (ret)
1434                 return ret;
1435
1436         vdsc_cfg->dsc_version_major =
1437                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1438                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1439         vdsc_cfg->dsc_version_minor =
1440                 min(intel_dp_source_dsc_version_minor(intel_dp),
1441                     intel_dp_sink_dsc_version_minor(intel_dp));
1442
1443         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1444                 DP_DSC_RGB;
1445
1446         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1447         if (!line_buf_depth) {
1448                 drm_dbg_kms(&i915->drm,
1449                             "DSC Sink Line Buffer Depth invalid\n");
1450                 return -EINVAL;
1451         }
1452
1453         if (vdsc_cfg->dsc_version_minor == 2)
1454                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1455                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1456         else
1457                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1458                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1459
1460         vdsc_cfg->block_pred_enable =
1461                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1462                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1463
1464         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1465 }
1466
1467 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1468                                        struct intel_crtc_state *pipe_config,
1469                                        struct drm_connector_state *conn_state,
1470                                        struct link_config_limits *limits)
1471 {
1472         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1473         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1474         const struct drm_display_mode *adjusted_mode =
1475                 &pipe_config->hw.adjusted_mode;
1476         int pipe_bpp;
1477         int ret;
1478
1479         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1480                 intel_dp_supports_fec(intel_dp, pipe_config);
1481
1482         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1483                 return -EINVAL;
1484
1485         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1486
1487         /* Min Input BPC for ICL+ is 8 */
1488         if (pipe_bpp < 8 * 3) {
1489                 drm_dbg_kms(&dev_priv->drm,
1490                             "No DSC support for less than 8bpc\n");
1491                 return -EINVAL;
1492         }
1493
1494         /*
1495          * For now enable DSC for max bpp, max link rate, max lane count.
1496          * Optimize this later for the minimum possible link rate/lane count
1497          * with DSC enabled for the requested mode.
1498          */
1499         pipe_config->pipe_bpp = pipe_bpp;
1500         pipe_config->port_clock = limits->max_rate;
1501         pipe_config->lane_count = limits->max_lane_count;
1502
1503         if (intel_dp_is_edp(intel_dp)) {
1504                 pipe_config->dsc.compressed_bpp =
1505                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1506                               pipe_config->pipe_bpp);
1507                 pipe_config->dsc.slice_count =
1508                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1509                                                         true);
1510         } else {
1511                 u16 dsc_max_output_bpp;
1512                 u8 dsc_dp_slice_count;
1513
1514                 dsc_max_output_bpp =
1515                         intel_dp_dsc_get_output_bpp(dev_priv,
1516                                                     pipe_config->port_clock,
1517                                                     pipe_config->lane_count,
1518                                                     adjusted_mode->crtc_clock,
1519                                                     adjusted_mode->crtc_hdisplay,
1520                                                     pipe_config->bigjoiner_pipes,
1521                                                     pipe_bpp);
1522                 dsc_dp_slice_count =
1523                         intel_dp_dsc_get_slice_count(intel_dp,
1524                                                      adjusted_mode->crtc_clock,
1525                                                      adjusted_mode->crtc_hdisplay,
1526                                                      pipe_config->bigjoiner_pipes);
1527                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1528                         drm_dbg_kms(&dev_priv->drm,
1529                                     "Compressed BPP/Slice Count not supported\n");
1530                         return -EINVAL;
1531                 }
1532                 pipe_config->dsc.compressed_bpp = min_t(u16,
1533                                                                dsc_max_output_bpp >> 4,
1534                                                                pipe_config->pipe_bpp);
1535                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1536         }
1537
1538         /* As of today we support DSC for only RGB */
1539         if (intel_dp->force_dsc_bpp) {
1540                 if (intel_dp->force_dsc_bpp >= 8 &&
1541                     intel_dp->force_dsc_bpp < pipe_bpp) {
1542                         drm_dbg_kms(&dev_priv->drm,
1543                                     "DSC BPP forced to %d",
1544                                     intel_dp->force_dsc_bpp);
1545                         pipe_config->dsc.compressed_bpp =
1546                                                 intel_dp->force_dsc_bpp;
1547                 } else {
1548                         drm_dbg_kms(&dev_priv->drm,
1549                                     "Invalid DSC BPP %d",
1550                                     intel_dp->force_dsc_bpp);
1551                 }
1552         }
1553
1554         /*
1555          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1556          * is greater than the maximum Cdclock and if slice count is even
1557          * then we need to use 2 VDSC instances.
1558          */
1559         if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq ||
1560             pipe_config->bigjoiner_pipes) {
1561                 if (pipe_config->dsc.slice_count < 2) {
1562                         drm_dbg_kms(&dev_priv->drm,
1563                                     "Cannot split stream to use 2 VDSC instances\n");
1564                         return -EINVAL;
1565                 }
1566
1567                 pipe_config->dsc.dsc_split = true;
1568         }
1569
1570         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1571         if (ret < 0) {
1572                 drm_dbg_kms(&dev_priv->drm,
1573                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1574                             "Compressed BPP = %d\n",
1575                             pipe_config->pipe_bpp,
1576                             pipe_config->dsc.compressed_bpp);
1577                 return ret;
1578         }
1579
1580         pipe_config->dsc.compression_enable = true;
1581         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1582                     "Compressed Bpp = %d Slice Count = %d\n",
1583                     pipe_config->pipe_bpp,
1584                     pipe_config->dsc.compressed_bpp,
1585                     pipe_config->dsc.slice_count);
1586
1587         return 0;
1588 }
1589
1590 static int
1591 intel_dp_compute_link_config(struct intel_encoder *encoder,
1592                              struct intel_crtc_state *pipe_config,
1593                              struct drm_connector_state *conn_state,
1594                              bool respect_downstream_limits)
1595 {
1596         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1597         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1598         const struct drm_display_mode *adjusted_mode =
1599                 &pipe_config->hw.adjusted_mode;
1600         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1601         struct link_config_limits limits;
1602         bool joiner_needs_dsc = false;
1603         int ret;
1604
1605         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1606         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1607
1608         limits.min_lane_count = 1;
1609         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1610
1611         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1612         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1613
1614         if (intel_dp->use_max_params) {
1615                 /*
1616                  * Use the maximum clock and number of lanes the eDP panel
1617                  * advertizes being capable of in case the initial fast
1618                  * optimal params failed us. The panels are generally
1619                  * designed to support only a single clock and lane
1620                  * configuration, and typically on older panels these
1621                  * values correspond to the native resolution of the panel.
1622                  */
1623                 limits.min_lane_count = limits.max_lane_count;
1624                 limits.min_rate = limits.max_rate;
1625         }
1626
1627         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1628
1629         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1630                     "max rate %d max bpp %d pixel clock %iKHz\n",
1631                     limits.max_lane_count, limits.max_rate,
1632                     limits.max_bpp, adjusted_mode->crtc_clock);
1633
1634         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1635                                     adjusted_mode->crtc_clock))
1636                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1637
1638         /*
1639          * Pipe joiner needs compression up to display 12 due to bandwidth
1640          * limitation. DG2 onwards pipe joiner can be enabled without
1641          * compression.
1642          */
1643         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1644
1645         /*
1646          * Optimize for slow and wide for everything, because there are some
1647          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1648          */
1649         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1650
1651         if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1652                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1653                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1654                             str_yes_no(intel_dp->force_dsc_en));
1655                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1656                                                   conn_state, &limits);
1657                 if (ret < 0)
1658                         return ret;
1659         }
1660
1661         if (pipe_config->dsc.compression_enable) {
1662                 drm_dbg_kms(&i915->drm,
1663                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1664                             pipe_config->lane_count, pipe_config->port_clock,
1665                             pipe_config->pipe_bpp,
1666                             pipe_config->dsc.compressed_bpp);
1667
1668                 drm_dbg_kms(&i915->drm,
1669                             "DP link rate required %i available %i\n",
1670                             intel_dp_link_required(adjusted_mode->crtc_clock,
1671                                                    pipe_config->dsc.compressed_bpp),
1672                             intel_dp_max_data_rate(pipe_config->port_clock,
1673                                                    pipe_config->lane_count));
1674         } else {
1675                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1676                             pipe_config->lane_count, pipe_config->port_clock,
1677                             pipe_config->pipe_bpp);
1678
1679                 drm_dbg_kms(&i915->drm,
1680                             "DP link rate required %i available %i\n",
1681                             intel_dp_link_required(adjusted_mode->crtc_clock,
1682                                                    pipe_config->pipe_bpp),
1683                             intel_dp_max_data_rate(pipe_config->port_clock,
1684                                                    pipe_config->lane_count));
1685         }
1686         return 0;
1687 }
1688
1689 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1690                                   const struct drm_connector_state *conn_state)
1691 {
1692         const struct intel_digital_connector_state *intel_conn_state =
1693                 to_intel_digital_connector_state(conn_state);
1694         const struct drm_display_mode *adjusted_mode =
1695                 &crtc_state->hw.adjusted_mode;
1696
1697         /*
1698          * Our YCbCr output is always limited range.
1699          * crtc_state->limited_color_range only applies to RGB,
1700          * and it must never be set for YCbCr or we risk setting
1701          * some conflicting bits in PIPECONF which will mess up
1702          * the colors on the monitor.
1703          */
1704         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1705                 return false;
1706
1707         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1708                 /*
1709                  * See:
1710                  * CEA-861-E - 5.1 Default Encoding Parameters
1711                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1712                  */
1713                 return crtc_state->pipe_bpp != 18 &&
1714                         drm_default_rgb_quant_range(adjusted_mode) ==
1715                         HDMI_QUANTIZATION_RANGE_LIMITED;
1716         } else {
1717                 return intel_conn_state->broadcast_rgb ==
1718                         INTEL_BROADCAST_RGB_LIMITED;
1719         }
1720 }
1721
1722 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1723                                     enum port port)
1724 {
1725         if (IS_G4X(dev_priv))
1726                 return false;
1727         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1728                 return false;
1729
1730         return true;
1731 }
1732
1733 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1734                                              const struct drm_connector_state *conn_state,
1735                                              struct drm_dp_vsc_sdp *vsc)
1736 {
1737         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1738         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1739
1740         /*
1741          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1742          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1743          * Colorimetry Format indication.
1744          */
1745         vsc->revision = 0x5;
1746         vsc->length = 0x13;
1747
1748         /* DP 1.4a spec, Table 2-120 */
1749         switch (crtc_state->output_format) {
1750         case INTEL_OUTPUT_FORMAT_YCBCR444:
1751                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1752                 break;
1753         case INTEL_OUTPUT_FORMAT_YCBCR420:
1754                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1755                 break;
1756         case INTEL_OUTPUT_FORMAT_RGB:
1757         default:
1758                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1759         }
1760
1761         switch (conn_state->colorspace) {
1762         case DRM_MODE_COLORIMETRY_BT709_YCC:
1763                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1764                 break;
1765         case DRM_MODE_COLORIMETRY_XVYCC_601:
1766                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1767                 break;
1768         case DRM_MODE_COLORIMETRY_XVYCC_709:
1769                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1770                 break;
1771         case DRM_MODE_COLORIMETRY_SYCC_601:
1772                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1773                 break;
1774         case DRM_MODE_COLORIMETRY_OPYCC_601:
1775                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1776                 break;
1777         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1778                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1779                 break;
1780         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1781                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1782                 break;
1783         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1784                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1785                 break;
1786         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1787         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1788                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1789                 break;
1790         default:
1791                 /*
1792                  * RGB->YCBCR color conversion uses the BT.709
1793                  * color space.
1794                  */
1795                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1796                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1797                 else
1798                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1799                 break;
1800         }
1801
1802         vsc->bpc = crtc_state->pipe_bpp / 3;
1803
1804         /* only RGB pixelformat supports 6 bpc */
1805         drm_WARN_ON(&dev_priv->drm,
1806                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1807
1808         /* all YCbCr are always limited range */
1809         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1810         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1811 }
1812
1813 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1814                                      struct intel_crtc_state *crtc_state,
1815                                      const struct drm_connector_state *conn_state)
1816 {
1817         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1818
1819         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1820         if (crtc_state->has_psr)
1821                 return;
1822
1823         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1824                 return;
1825
1826         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1827         vsc->sdp_type = DP_SDP_VSC;
1828         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1829                                          &crtc_state->infoframes.vsc);
1830 }
1831
1832 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1833                                   const struct intel_crtc_state *crtc_state,
1834                                   const struct drm_connector_state *conn_state,
1835                                   struct drm_dp_vsc_sdp *vsc)
1836 {
1837         vsc->sdp_type = DP_SDP_VSC;
1838
1839         if (crtc_state->has_psr2) {
1840                 if (intel_dp->psr.colorimetry_support &&
1841                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1842                         /* [PSR2, +Colorimetry] */
1843                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1844                                                          vsc);
1845                 } else {
1846                         /*
1847                          * [PSR2, -Colorimetry]
1848                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1849                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1850                          */
1851                         vsc->revision = 0x4;
1852                         vsc->length = 0xe;
1853                 }
1854         } else {
1855                 /*
1856                  * [PSR1]
1857                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1858                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1859                  * higher).
1860                  */
1861                 vsc->revision = 0x2;
1862                 vsc->length = 0x8;
1863         }
1864 }
1865
1866 static void
1867 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1868                                             struct intel_crtc_state *crtc_state,
1869                                             const struct drm_connector_state *conn_state)
1870 {
1871         int ret;
1872         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1873         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1874
1875         if (!conn_state->hdr_output_metadata)
1876                 return;
1877
1878         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1879
1880         if (ret) {
1881                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1882                 return;
1883         }
1884
1885         crtc_state->infoframes.enable |=
1886                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1887 }
1888
1889 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1890                                     enum transcoder cpu_transcoder)
1891 {
1892         if (HAS_DOUBLE_BUFFERED_M_N(i915))
1893                 return true;
1894
1895         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1896 }
1897
1898 static bool can_enable_drrs(struct intel_connector *connector,
1899                             const struct intel_crtc_state *pipe_config,
1900                             const struct drm_display_mode *downclock_mode)
1901 {
1902         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1903
1904         if (pipe_config->vrr.enable)
1905                 return false;
1906
1907         /*
1908          * DRRS and PSR can't be enable together, so giving preference to PSR
1909          * as it allows more power-savings by complete shutting down display,
1910          * so to guarantee this, intel_drrs_compute_config() must be called
1911          * after intel_psr_compute_config().
1912          */
1913         if (pipe_config->has_psr)
1914                 return false;
1915
1916         /* FIXME missing FDI M2/N2 etc. */
1917         if (pipe_config->has_pch_encoder)
1918                 return false;
1919
1920         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
1921                 return false;
1922
1923         return downclock_mode &&
1924                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1925 }
1926
1927 static void
1928 intel_dp_drrs_compute_config(struct intel_connector *connector,
1929                              struct intel_crtc_state *pipe_config,
1930                              int output_bpp)
1931 {
1932         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1933         const struct drm_display_mode *downclock_mode =
1934                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
1935         int pixel_clock;
1936
1937         if (has_seamless_m_n(connector))
1938                 pipe_config->seamless_m_n = true;
1939
1940         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
1941                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
1942                         intel_zero_m_n(&pipe_config->dp_m2_n2);
1943                 return;
1944         }
1945
1946         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
1947                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
1948
1949         pipe_config->has_drrs = true;
1950
1951         pixel_clock = downclock_mode->clock;
1952         if (pipe_config->splitter.enable)
1953                 pixel_clock /= pipe_config->splitter.link_count;
1954
1955         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1956                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
1957                                pipe_config->fec_enable);
1958
1959         /* FIXME: abstract this better */
1960         if (pipe_config->splitter.enable)
1961                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
1962 }
1963
1964 static bool intel_dp_has_audio(struct intel_encoder *encoder,
1965                                const struct intel_crtc_state *crtc_state,
1966                                const struct drm_connector_state *conn_state)
1967 {
1968         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1969         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1970         const struct intel_digital_connector_state *intel_conn_state =
1971                 to_intel_digital_connector_state(conn_state);
1972
1973         if (!intel_dp_port_has_audio(i915, encoder->port))
1974                 return false;
1975
1976         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1977                 return intel_dp->has_audio;
1978         else
1979                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1980 }
1981
1982 static int
1983 intel_dp_compute_output_format(struct intel_encoder *encoder,
1984                                struct intel_crtc_state *crtc_state,
1985                                struct drm_connector_state *conn_state,
1986                                bool respect_downstream_limits)
1987 {
1988         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1989         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1990         struct intel_connector *connector = intel_dp->attached_connector;
1991         const struct drm_display_info *info = &connector->base.display_info;
1992         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1993         bool ycbcr_420_only;
1994         int ret;
1995
1996         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
1997
1998         crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
1999
2000         if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
2001                 drm_dbg_kms(&i915->drm,
2002                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2003                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2004         }
2005
2006         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2007                                            respect_downstream_limits);
2008         if (ret) {
2009                 if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
2010                     !connector->base.ycbcr_420_allowed ||
2011                     !drm_mode_is_420_also(info, adjusted_mode))
2012                         return ret;
2013
2014                 crtc_state->output_format = intel_dp_output_format(connector, true);
2015                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2016                                                    respect_downstream_limits);
2017         }
2018
2019         return ret;
2020 }
2021
2022 int
2023 intel_dp_compute_config(struct intel_encoder *encoder,
2024                         struct intel_crtc_state *pipe_config,
2025                         struct drm_connector_state *conn_state)
2026 {
2027         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2028         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2029         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2030         const struct drm_display_mode *fixed_mode;
2031         struct intel_connector *connector = intel_dp->attached_connector;
2032         int ret = 0, output_bpp;
2033
2034         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2035                 pipe_config->has_pch_encoder = true;
2036
2037         pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
2038
2039         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2040         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2041                 ret = intel_panel_compute_config(connector, adjusted_mode);
2042                 if (ret)
2043                         return ret;
2044         }
2045
2046         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2047                 return -EINVAL;
2048
2049         if (HAS_GMCH(dev_priv) &&
2050             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2051                 return -EINVAL;
2052
2053         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2054                 return -EINVAL;
2055
2056         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2057                 return -EINVAL;
2058
2059         /*
2060          * Try to respect downstream TMDS clock limits first, if
2061          * that fails assume the user might know something we don't.
2062          */
2063         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2064         if (ret)
2065                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2066         if (ret)
2067                 return ret;
2068
2069         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2070             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2071                 ret = intel_panel_fitting(pipe_config, conn_state);
2072                 if (ret)
2073                         return ret;
2074         }
2075
2076         pipe_config->limited_color_range =
2077                 intel_dp_limited_color_range(pipe_config, conn_state);
2078
2079         if (pipe_config->dsc.compression_enable)
2080                 output_bpp = pipe_config->dsc.compressed_bpp;
2081         else
2082                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2083                                                  pipe_config->pipe_bpp);
2084
2085         if (intel_dp->mso_link_count) {
2086                 int n = intel_dp->mso_link_count;
2087                 int overlap = intel_dp->mso_pixel_overlap;
2088
2089                 pipe_config->splitter.enable = true;
2090                 pipe_config->splitter.link_count = n;
2091                 pipe_config->splitter.pixel_overlap = overlap;
2092
2093                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2094                             n, overlap);
2095
2096                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2097                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2098                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2099                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2100                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2101                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2102                 adjusted_mode->crtc_clock /= n;
2103         }
2104
2105         intel_link_compute_m_n(output_bpp,
2106                                pipe_config->lane_count,
2107                                adjusted_mode->crtc_clock,
2108                                pipe_config->port_clock,
2109                                &pipe_config->dp_m_n,
2110                                pipe_config->fec_enable);
2111
2112         /* FIXME: abstract this better */
2113         if (pipe_config->splitter.enable)
2114                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2115
2116         if (!HAS_DDI(dev_priv))
2117                 g4x_dp_set_clock(encoder, pipe_config);
2118
2119         intel_vrr_compute_config(pipe_config, conn_state);
2120         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2121         intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2122         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2123         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2124
2125         return 0;
2126 }
2127
2128 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2129                               int link_rate, int lane_count)
2130 {
2131         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2132         intel_dp->link_trained = false;
2133         intel_dp->link_rate = link_rate;
2134         intel_dp->lane_count = lane_count;
2135 }
2136
2137 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2138 {
2139         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2140         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2141 }
2142
2143 /* Enable backlight PWM and backlight PP control. */
2144 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2145                             const struct drm_connector_state *conn_state)
2146 {
2147         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2148         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2149
2150         if (!intel_dp_is_edp(intel_dp))
2151                 return;
2152
2153         drm_dbg_kms(&i915->drm, "\n");
2154
2155         intel_backlight_enable(crtc_state, conn_state);
2156         intel_pps_backlight_on(intel_dp);
2157 }
2158
2159 /* Disable backlight PP control and backlight PWM. */
2160 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2161 {
2162         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2163         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2164
2165         if (!intel_dp_is_edp(intel_dp))
2166                 return;
2167
2168         drm_dbg_kms(&i915->drm, "\n");
2169
2170         intel_pps_backlight_off(intel_dp);
2171         intel_backlight_disable(old_conn_state);
2172 }
2173
2174 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2175 {
2176         /*
2177          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2178          * be capable of signalling downstream hpd with a long pulse.
2179          * Whether or not that means D3 is safe to use is not clear,
2180          * but let's assume so until proven otherwise.
2181          *
2182          * FIXME should really check all downstream ports...
2183          */
2184         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2185                 drm_dp_is_branch(intel_dp->dpcd) &&
2186                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2187 }
2188
2189 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2190                                            const struct intel_crtc_state *crtc_state,
2191                                            bool enable)
2192 {
2193         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2194         int ret;
2195
2196         if (!crtc_state->dsc.compression_enable)
2197                 return;
2198
2199         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2200                                  enable ? DP_DECOMPRESSION_EN : 0);
2201         if (ret < 0)
2202                 drm_dbg_kms(&i915->drm,
2203                             "Failed to %s sink decompression state\n",
2204                             str_enable_disable(enable));
2205 }
2206
2207 static void
2208 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2209 {
2210         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2211         u8 oui[] = { 0x00, 0xaa, 0x01 };
2212         u8 buf[3] = { 0 };
2213
2214         /*
2215          * During driver init, we want to be careful and avoid changing the source OUI if it's
2216          * already set to what we want, so as to avoid clearing any state by accident
2217          */
2218         if (careful) {
2219                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2220                         drm_err(&i915->drm, "Failed to read source OUI\n");
2221
2222                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2223                         return;
2224         }
2225
2226         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2227                 drm_err(&i915->drm, "Failed to write source OUI\n");
2228
2229         intel_dp->last_oui_write = jiffies;
2230 }
2231
2232 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2233 {
2234         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2235
2236         drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2237         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2238 }
2239
2240 /* If the device supports it, try to set the power state appropriately */
2241 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2242 {
2243         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2244         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2245         int ret, i;
2246
2247         /* Should have a valid DPCD by this point */
2248         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2249                 return;
2250
2251         if (mode != DP_SET_POWER_D0) {
2252                 if (downstream_hpd_needs_d0(intel_dp))
2253                         return;
2254
2255                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2256         } else {
2257                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2258
2259                 lspcon_resume(dp_to_dig_port(intel_dp));
2260
2261                 /* Write the source OUI as early as possible */
2262                 if (intel_dp_is_edp(intel_dp))
2263                         intel_edp_init_source_oui(intel_dp, false);
2264
2265                 /*
2266                  * When turning on, we need to retry for 1ms to give the sink
2267                  * time to wake up.
2268                  */
2269                 for (i = 0; i < 3; i++) {
2270                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2271                         if (ret == 1)
2272                                 break;
2273                         msleep(1);
2274                 }
2275
2276                 if (ret == 1 && lspcon->active)
2277                         lspcon_wait_pcon_mode(lspcon);
2278         }
2279
2280         if (ret != 1)
2281                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2282                             encoder->base.base.id, encoder->base.name,
2283                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2284 }
2285
2286 static bool
2287 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2288
2289 /**
2290  * intel_dp_sync_state - sync the encoder state during init/resume
2291  * @encoder: intel encoder to sync
2292  * @crtc_state: state for the CRTC connected to the encoder
2293  *
2294  * Sync any state stored in the encoder wrt. HW state during driver init
2295  * and system resume.
2296  */
2297 void intel_dp_sync_state(struct intel_encoder *encoder,
2298                          const struct intel_crtc_state *crtc_state)
2299 {
2300         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2301
2302         if (!crtc_state)
2303                 return;
2304
2305         /*
2306          * Don't clobber DPCD if it's been already read out during output
2307          * setup (eDP) or detect.
2308          */
2309         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2310                 intel_dp_get_dpcd(intel_dp);
2311
2312         intel_dp_reset_max_link_params(intel_dp);
2313 }
2314
2315 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2316                                     struct intel_crtc_state *crtc_state)
2317 {
2318         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2319         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2320
2321         /*
2322          * If BIOS has set an unsupported or non-standard link rate for some
2323          * reason force an encoder recompute and full modeset.
2324          */
2325         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2326                                 crtc_state->port_clock) < 0) {
2327                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2328                 crtc_state->uapi.connectors_changed = true;
2329                 return false;
2330         }
2331
2332         /*
2333          * FIXME hack to force full modeset when DSC is being used.
2334          *
2335          * As long as we do not have full state readout and config comparison
2336          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2337          * Remove once we have readout for DSC.
2338          */
2339         if (crtc_state->dsc.compression_enable) {
2340                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2341                 crtc_state->uapi.mode_changed = true;
2342                 return false;
2343         }
2344
2345         if (CAN_PSR(intel_dp)) {
2346                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2347                 crtc_state->uapi.mode_changed = true;
2348                 return false;
2349         }
2350
2351         return true;
2352 }
2353
2354 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2355 {
2356         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2357
2358         /* Clear the cached register set to avoid using stale values */
2359
2360         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2361
2362         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2363                              intel_dp->pcon_dsc_dpcd,
2364                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2365                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2366                         DP_PCON_DSC_ENCODER);
2367
2368         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2369                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2370 }
2371
2372 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2373 {
2374         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2375         int i;
2376
2377         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2378                 if (frl_bw_mask & (1 << i))
2379                         return bw_gbps[i];
2380         }
2381         return 0;
2382 }
2383
2384 static int intel_dp_pcon_set_frl_mask(int max_frl)
2385 {
2386         switch (max_frl) {
2387         case 48:
2388                 return DP_PCON_FRL_BW_MASK_48GBPS;
2389         case 40:
2390                 return DP_PCON_FRL_BW_MASK_40GBPS;
2391         case 32:
2392                 return DP_PCON_FRL_BW_MASK_32GBPS;
2393         case 24:
2394                 return DP_PCON_FRL_BW_MASK_24GBPS;
2395         case 18:
2396                 return DP_PCON_FRL_BW_MASK_18GBPS;
2397         case 9:
2398                 return DP_PCON_FRL_BW_MASK_9GBPS;
2399         }
2400
2401         return 0;
2402 }
2403
2404 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2405 {
2406         struct intel_connector *intel_connector = intel_dp->attached_connector;
2407         struct drm_connector *connector = &intel_connector->base;
2408         int max_frl_rate;
2409         int max_lanes, rate_per_lane;
2410         int max_dsc_lanes, dsc_rate_per_lane;
2411
2412         max_lanes = connector->display_info.hdmi.max_lanes;
2413         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2414         max_frl_rate = max_lanes * rate_per_lane;
2415
2416         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2417                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2418                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2419                 if (max_dsc_lanes && dsc_rate_per_lane)
2420                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2421         }
2422
2423         return max_frl_rate;
2424 }
2425
2426 static bool
2427 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2428                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2429 {
2430         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2431             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2432             *frl_trained_mask >= max_frl_bw_mask)
2433                 return true;
2434
2435         return false;
2436 }
2437
2438 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2439 {
2440 #define TIMEOUT_FRL_READY_MS 500
2441 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2442
2443         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2444         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2445         u8 max_frl_bw_mask = 0, frl_trained_mask;
2446         bool is_active;
2447
2448         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2449         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2450
2451         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2452         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2453
2454         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2455
2456         if (max_frl_bw <= 0)
2457                 return -EINVAL;
2458
2459         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2460         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2461
2462         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2463                 goto frl_trained;
2464
2465         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2466         if (ret < 0)
2467                 return ret;
2468         /* Wait for PCON to be FRL Ready */
2469         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2470
2471         if (!is_active)
2472                 return -ETIMEDOUT;
2473
2474         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2475                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2476         if (ret < 0)
2477                 return ret;
2478         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2479                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2480         if (ret < 0)
2481                 return ret;
2482         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2483         if (ret < 0)
2484                 return ret;
2485         /*
2486          * Wait for FRL to be completed
2487          * Check if the HDMI Link is up and active.
2488          */
2489         wait_for(is_active =
2490                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2491                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2492
2493         if (!is_active)
2494                 return -ETIMEDOUT;
2495
2496 frl_trained:
2497         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2498         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2499         intel_dp->frl.is_trained = true;
2500         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2501
2502         return 0;
2503 }
2504
2505 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2506 {
2507         if (drm_dp_is_branch(intel_dp->dpcd) &&
2508             intel_dp->has_hdmi_sink &&
2509             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2510                 return true;
2511
2512         return false;
2513 }
2514
2515 static
2516 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2517 {
2518         int ret;
2519         u8 buf = 0;
2520
2521         /* Set PCON source control mode */
2522         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2523
2524         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2525         if (ret < 0)
2526                 return ret;
2527
2528         /* Set HDMI LINK ENABLE */
2529         buf |= DP_PCON_ENABLE_HDMI_LINK;
2530         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2531         if (ret < 0)
2532                 return ret;
2533
2534         return 0;
2535 }
2536
2537 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2538 {
2539         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2540
2541         /*
2542          * Always go for FRL training if:
2543          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2544          * -sink is HDMI2.1
2545          */
2546         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2547             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2548             intel_dp->frl.is_trained)
2549                 return;
2550
2551         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2552                 int ret, mode;
2553
2554                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2555                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2556                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2557
2558                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2559                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2560         } else {
2561                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2562         }
2563 }
2564
2565 static int
2566 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2567 {
2568         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2569
2570         return intel_hdmi_dsc_get_slice_height(vactive);
2571 }
2572
2573 static int
2574 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2575                              const struct intel_crtc_state *crtc_state)
2576 {
2577         struct intel_connector *intel_connector = intel_dp->attached_connector;
2578         struct drm_connector *connector = &intel_connector->base;
2579         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2580         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2581         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2582         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2583
2584         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2585                                              pcon_max_slice_width,
2586                                              hdmi_max_slices, hdmi_throughput);
2587 }
2588
2589 static int
2590 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2591                           const struct intel_crtc_state *crtc_state,
2592                           int num_slices, int slice_width)
2593 {
2594         struct intel_connector *intel_connector = intel_dp->attached_connector;
2595         struct drm_connector *connector = &intel_connector->base;
2596         int output_format = crtc_state->output_format;
2597         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2598         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2599         int hdmi_max_chunk_bytes =
2600                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2601
2602         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2603                                       num_slices, output_format, hdmi_all_bpp,
2604                                       hdmi_max_chunk_bytes);
2605 }
2606
2607 void
2608 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2609                             const struct intel_crtc_state *crtc_state)
2610 {
2611         u8 pps_param[6];
2612         int slice_height;
2613         int slice_width;
2614         int num_slices;
2615         int bits_per_pixel;
2616         int ret;
2617         struct intel_connector *intel_connector = intel_dp->attached_connector;
2618         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2619         struct drm_connector *connector;
2620         bool hdmi_is_dsc_1_2;
2621
2622         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2623                 return;
2624
2625         if (!intel_connector)
2626                 return;
2627         connector = &intel_connector->base;
2628         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2629
2630         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2631             !hdmi_is_dsc_1_2)
2632                 return;
2633
2634         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2635         if (!slice_height)
2636                 return;
2637
2638         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2639         if (!num_slices)
2640                 return;
2641
2642         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2643                                    num_slices);
2644
2645         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2646                                                    num_slices, slice_width);
2647         if (!bits_per_pixel)
2648                 return;
2649
2650         pps_param[0] = slice_height & 0xFF;
2651         pps_param[1] = slice_height >> 8;
2652         pps_param[2] = slice_width & 0xFF;
2653         pps_param[3] = slice_width >> 8;
2654         pps_param[4] = bits_per_pixel & 0xFF;
2655         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2656
2657         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2658         if (ret < 0)
2659                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2660 }
2661
2662 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2663                                            const struct intel_crtc_state *crtc_state)
2664 {
2665         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2666         u8 tmp;
2667
2668         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2669                 return;
2670
2671         if (!drm_dp_is_branch(intel_dp->dpcd))
2672                 return;
2673
2674         tmp = intel_dp->has_hdmi_sink ?
2675                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2676
2677         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2678                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2679                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2680                             str_enable_disable(intel_dp->has_hdmi_sink));
2681
2682         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2683                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2684
2685         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2686                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2687                 drm_dbg_kms(&i915->drm,
2688                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2689                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2690
2691         tmp = intel_dp->dfp.rgb_to_ycbcr ?
2692                 DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2693
2694         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2695                 drm_dbg_kms(&i915->drm,
2696                            "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2697                            str_enable_disable(tmp));
2698 }
2699
2700
2701 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2702 {
2703         u8 dprx = 0;
2704
2705         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2706                               &dprx) != 1)
2707                 return false;
2708         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2709 }
2710
2711 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2712 {
2713         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2714
2715         /*
2716          * Clear the cached register set to avoid using stale values
2717          * for the sinks that do not support DSC.
2718          */
2719         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2720
2721         /* Clear fec_capable to avoid using stale values */
2722         intel_dp->fec_capable = 0;
2723
2724         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2725         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2726             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2727                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2728                                      intel_dp->dsc_dpcd,
2729                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2730                         drm_err(&i915->drm,
2731                                 "Failed to read DPCD register 0x%x\n",
2732                                 DP_DSC_SUPPORT);
2733
2734                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2735                             (int)sizeof(intel_dp->dsc_dpcd),
2736                             intel_dp->dsc_dpcd);
2737
2738                 /* FEC is supported only on DP 1.4 */
2739                 if (!intel_dp_is_edp(intel_dp) &&
2740                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2741                                       &intel_dp->fec_capable) < 0)
2742                         drm_err(&i915->drm,
2743                                 "Failed to read FEC DPCD register\n");
2744
2745                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2746                             intel_dp->fec_capable);
2747         }
2748 }
2749
2750 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2751                                      struct drm_display_mode *mode)
2752 {
2753         struct intel_dp *intel_dp = intel_attached_dp(connector);
2754         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2755         int n = intel_dp->mso_link_count;
2756         int overlap = intel_dp->mso_pixel_overlap;
2757
2758         if (!mode || !n)
2759                 return;
2760
2761         mode->hdisplay = (mode->hdisplay - overlap) * n;
2762         mode->hsync_start = (mode->hsync_start - overlap) * n;
2763         mode->hsync_end = (mode->hsync_end - overlap) * n;
2764         mode->htotal = (mode->htotal - overlap) * n;
2765         mode->clock *= n;
2766
2767         drm_mode_set_name(mode);
2768
2769         drm_dbg_kms(&i915->drm,
2770                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2771                     connector->base.base.id, connector->base.name,
2772                     DRM_MODE_ARG(mode));
2773 }
2774
2775 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
2776 {
2777         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2778         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2779         struct intel_connector *connector = intel_dp->attached_connector;
2780
2781         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
2782                 /*
2783                  * This is a big fat ugly hack.
2784                  *
2785                  * Some machines in UEFI boot mode provide us a VBT that has 18
2786                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2787                  * unknown we fail to light up. Yet the same BIOS boots up with
2788                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2789                  * max, not what it tells us to use.
2790                  *
2791                  * Note: This will still be broken if the eDP panel is not lit
2792                  * up by the BIOS, and thus we can't get the mode at module
2793                  * load.
2794                  */
2795                 drm_dbg_kms(&dev_priv->drm,
2796                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2797                             pipe_bpp, connector->panel.vbt.edp.bpp);
2798                 connector->panel.vbt.edp.bpp = pipe_bpp;
2799         }
2800 }
2801
2802 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2803 {
2804         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2805         struct intel_connector *connector = intel_dp->attached_connector;
2806         struct drm_display_info *info = &connector->base.display_info;
2807         u8 mso;
2808
2809         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2810                 return;
2811
2812         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2813                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2814                 return;
2815         }
2816
2817         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2818         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2819         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2820                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2821                 mso = 0;
2822         }
2823
2824         if (mso) {
2825                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2826                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2827                             info->mso_pixel_overlap);
2828                 if (!HAS_MSO(i915)) {
2829                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2830                         mso = 0;
2831                 }
2832         }
2833
2834         intel_dp->mso_link_count = mso;
2835         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2836 }
2837
2838 static bool
2839 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2840 {
2841         struct drm_i915_private *dev_priv =
2842                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2843
2844         /* this function is meant to be called only once */
2845         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2846
2847         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2848                 return false;
2849
2850         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2851                          drm_dp_is_branch(intel_dp->dpcd));
2852
2853         /*
2854          * Read the eDP display control registers.
2855          *
2856          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2857          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2858          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2859          * method). The display control registers should read zero if they're
2860          * not supported anyway.
2861          */
2862         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2863                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2864                              sizeof(intel_dp->edp_dpcd)) {
2865                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2866                             (int)sizeof(intel_dp->edp_dpcd),
2867                             intel_dp->edp_dpcd);
2868
2869                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2870         }
2871
2872         /*
2873          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2874          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2875          */
2876         intel_psr_init_dpcd(intel_dp);
2877
2878         /* Clear the default sink rates */
2879         intel_dp->num_sink_rates = 0;
2880
2881         /* Read the eDP 1.4+ supported link rates. */
2882         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2883                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2884                 int i;
2885
2886                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2887                                 sink_rates, sizeof(sink_rates));
2888
2889                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2890                         int val = le16_to_cpu(sink_rates[i]);
2891
2892                         if (val == 0)
2893                                 break;
2894
2895                         /* Value read multiplied by 200kHz gives the per-lane
2896                          * link rate in kHz. The source rates are, however,
2897                          * stored in terms of LS_Clk kHz. The full conversion
2898                          * back to symbols is
2899                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2900                          */
2901                         intel_dp->sink_rates[i] = (val * 200) / 10;
2902                 }
2903                 intel_dp->num_sink_rates = i;
2904         }
2905
2906         /*
2907          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2908          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2909          */
2910         if (intel_dp->num_sink_rates)
2911                 intel_dp->use_rate_select = true;
2912         else
2913                 intel_dp_set_sink_rates(intel_dp);
2914         intel_dp_set_max_sink_lane_count(intel_dp);
2915
2916         /* Read the eDP DSC DPCD registers */
2917         if (DISPLAY_VER(dev_priv) >= 10)
2918                 intel_dp_get_dsc_sink_cap(intel_dp);
2919
2920         /*
2921          * If needed, program our source OUI so we can make various Intel-specific AUX services
2922          * available (such as HDR backlight controls)
2923          */
2924         intel_edp_init_source_oui(intel_dp, true);
2925
2926         return true;
2927 }
2928
2929 static bool
2930 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2931 {
2932         if (!intel_dp->attached_connector)
2933                 return false;
2934
2935         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2936                                           intel_dp->dpcd,
2937                                           &intel_dp->desc);
2938 }
2939
2940 static bool
2941 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2942 {
2943         int ret;
2944
2945         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2946                 return false;
2947
2948         /*
2949          * Don't clobber cached eDP rates. Also skip re-reading
2950          * the OUI/ID since we know it won't change.
2951          */
2952         if (!intel_dp_is_edp(intel_dp)) {
2953                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2954                                  drm_dp_is_branch(intel_dp->dpcd));
2955
2956                 intel_dp_set_sink_rates(intel_dp);
2957                 intel_dp_set_max_sink_lane_count(intel_dp);
2958                 intel_dp_set_common_rates(intel_dp);
2959         }
2960
2961         if (intel_dp_has_sink_count(intel_dp)) {
2962                 ret = drm_dp_read_sink_count(&intel_dp->aux);
2963                 if (ret < 0)
2964                         return false;
2965
2966                 /*
2967                  * Sink count can change between short pulse hpd hence
2968                  * a member variable in intel_dp will track any changes
2969                  * between short pulse interrupts.
2970                  */
2971                 intel_dp->sink_count = ret;
2972
2973                 /*
2974                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2975                  * a dongle is present but no display. Unless we require to know
2976                  * if a dongle is present or not, we don't need to update
2977                  * downstream port information. So, an early return here saves
2978                  * time from performing other operations which are not required.
2979                  */
2980                 if (!intel_dp->sink_count)
2981                         return false;
2982         }
2983
2984         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2985                                            intel_dp->downstream_ports) == 0;
2986 }
2987
2988 static bool
2989 intel_dp_can_mst(struct intel_dp *intel_dp)
2990 {
2991         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2992
2993         return i915->params.enable_dp_mst &&
2994                 intel_dp_mst_source_support(intel_dp) &&
2995                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2996 }
2997
2998 static void
2999 intel_dp_configure_mst(struct intel_dp *intel_dp)
3000 {
3001         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3002         struct intel_encoder *encoder =
3003                 &dp_to_dig_port(intel_dp)->base;
3004         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3005
3006         drm_dbg_kms(&i915->drm,
3007                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3008                     encoder->base.base.id, encoder->base.name,
3009                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
3010                     str_yes_no(sink_can_mst),
3011                     str_yes_no(i915->params.enable_dp_mst));
3012
3013         if (!intel_dp_mst_source_support(intel_dp))
3014                 return;
3015
3016         intel_dp->is_mst = sink_can_mst &&
3017                 i915->params.enable_dp_mst;
3018
3019         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3020                                         intel_dp->is_mst);
3021 }
3022
3023 static bool
3024 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3025 {
3026         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3027 }
3028
3029 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3030 {
3031         int retry;
3032
3033         for (retry = 0; retry < 3; retry++) {
3034                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3035                                       &esi[1], 3) == 3)
3036                         return true;
3037         }
3038
3039         return false;
3040 }
3041
3042 bool
3043 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3044                        const struct drm_connector_state *conn_state)
3045 {
3046         /*
3047          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3048          * of Color Encoding Format and Content Color Gamut], in order to
3049          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3050          */
3051         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3052                 return true;
3053
3054         switch (conn_state->colorspace) {
3055         case DRM_MODE_COLORIMETRY_SYCC_601:
3056         case DRM_MODE_COLORIMETRY_OPYCC_601:
3057         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3058         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3059         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3060                 return true;
3061         default:
3062                 break;
3063         }
3064
3065         return false;
3066 }
3067
3068 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3069                                      struct dp_sdp *sdp, size_t size)
3070 {
3071         size_t length = sizeof(struct dp_sdp);
3072
3073         if (size < length)
3074                 return -ENOSPC;
3075
3076         memset(sdp, 0, size);
3077
3078         /*
3079          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3080          * VSC SDP Header Bytes
3081          */
3082         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3083         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3084         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3085         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3086
3087         /*
3088          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3089          * per DP 1.4a spec.
3090          */
3091         if (vsc->revision != 0x5)
3092                 goto out;
3093
3094         /* VSC SDP Payload for DB16 through DB18 */
3095         /* Pixel Encoding and Colorimetry Formats  */
3096         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3097         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3098
3099         switch (vsc->bpc) {
3100         case 6:
3101                 /* 6bpc: 0x0 */
3102                 break;
3103         case 8:
3104                 sdp->db[17] = 0x1; /* DB17[3:0] */
3105                 break;
3106         case 10:
3107                 sdp->db[17] = 0x2;
3108                 break;
3109         case 12:
3110                 sdp->db[17] = 0x3;
3111                 break;
3112         case 16:
3113                 sdp->db[17] = 0x4;
3114                 break;
3115         default:
3116                 MISSING_CASE(vsc->bpc);
3117                 break;
3118         }
3119         /* Dynamic Range and Component Bit Depth */
3120         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3121                 sdp->db[17] |= 0x80;  /* DB17[7] */
3122
3123         /* Content Type */
3124         sdp->db[18] = vsc->content_type & 0x7;
3125
3126 out:
3127         return length;
3128 }
3129
3130 static ssize_t
3131 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3132                                          const struct hdmi_drm_infoframe *drm_infoframe,
3133                                          struct dp_sdp *sdp,
3134                                          size_t size)
3135 {
3136         size_t length = sizeof(struct dp_sdp);
3137         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3138         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3139         ssize_t len;
3140
3141         if (size < length)
3142                 return -ENOSPC;
3143
3144         memset(sdp, 0, size);
3145
3146         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3147         if (len < 0) {
3148                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3149                 return -ENOSPC;
3150         }
3151
3152         if (len != infoframe_size) {
3153                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3154                 return -ENOSPC;
3155         }
3156
3157         /*
3158          * Set up the infoframe sdp packet for HDR static metadata.
3159          * Prepare VSC Header for SU as per DP 1.4a spec,
3160          * Table 2-100 and Table 2-101
3161          */
3162
3163         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3164         sdp->sdp_header.HB0 = 0;
3165         /*
3166          * Packet Type 80h + Non-audio INFOFRAME Type value
3167          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3168          * - 80h + Non-audio INFOFRAME Type value
3169          * - InfoFrame Type: 0x07
3170          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3171          */
3172         sdp->sdp_header.HB1 = drm_infoframe->type;
3173         /*
3174          * Least Significant Eight Bits of (Data Byte Count – 1)
3175          * infoframe_size - 1
3176          */
3177         sdp->sdp_header.HB2 = 0x1D;
3178         /* INFOFRAME SDP Version Number */
3179         sdp->sdp_header.HB3 = (0x13 << 2);
3180         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3181         sdp->db[0] = drm_infoframe->version;
3182         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3183         sdp->db[1] = drm_infoframe->length;
3184         /*
3185          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3186          * HDMI_INFOFRAME_HEADER_SIZE
3187          */
3188         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3189         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3190                HDMI_DRM_INFOFRAME_SIZE);
3191
3192         /*
3193          * Size of DP infoframe sdp packet for HDR static metadata consists of
3194          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3195          * - Two Data Blocks: 2 bytes
3196          *    CTA Header Byte2 (INFOFRAME Version Number)
3197          *    CTA Header Byte3 (Length of INFOFRAME)
3198          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3199          *
3200          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3201          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3202          * will pad rest of the size.
3203          */
3204         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3205 }
3206
3207 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3208                                const struct intel_crtc_state *crtc_state,
3209                                unsigned int type)
3210 {
3211         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3213         struct dp_sdp sdp = {};
3214         ssize_t len;
3215
3216         if ((crtc_state->infoframes.enable &
3217              intel_hdmi_infoframe_enable(type)) == 0)
3218                 return;
3219
3220         switch (type) {
3221         case DP_SDP_VSC:
3222                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3223                                             sizeof(sdp));
3224                 break;
3225         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3226                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3227                                                                &crtc_state->infoframes.drm.drm,
3228                                                                &sdp, sizeof(sdp));
3229                 break;
3230         default:
3231                 MISSING_CASE(type);
3232                 return;
3233         }
3234
3235         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3236                 return;
3237
3238         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3239 }
3240
3241 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3242                             const struct intel_crtc_state *crtc_state,
3243                             const struct drm_dp_vsc_sdp *vsc)
3244 {
3245         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3246         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3247         struct dp_sdp sdp = {};
3248         ssize_t len;
3249
3250         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3251
3252         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3253                 return;
3254
3255         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3256                                         &sdp, len);
3257 }
3258
3259 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3260                              bool enable,
3261                              const struct intel_crtc_state *crtc_state,
3262                              const struct drm_connector_state *conn_state)
3263 {
3264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3265         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3266         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3267                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3268                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3269         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3270
3271         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3272         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3273         if (!crtc_state->has_psr)
3274                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3275
3276         intel_de_write(dev_priv, reg, val);
3277         intel_de_posting_read(dev_priv, reg);
3278
3279         if (!enable)
3280                 return;
3281
3282         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3283         if (!crtc_state->has_psr)
3284                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3285
3286         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3287 }
3288
3289 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3290                                    const void *buffer, size_t size)
3291 {
3292         const struct dp_sdp *sdp = buffer;
3293
3294         if (size < sizeof(struct dp_sdp))
3295                 return -EINVAL;
3296
3297         memset(vsc, 0, sizeof(*vsc));
3298
3299         if (sdp->sdp_header.HB0 != 0)
3300                 return -EINVAL;
3301
3302         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3303                 return -EINVAL;
3304
3305         vsc->sdp_type = sdp->sdp_header.HB1;
3306         vsc->revision = sdp->sdp_header.HB2;
3307         vsc->length = sdp->sdp_header.HB3;
3308
3309         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3310             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3311                 /*
3312                  * - HB2 = 0x2, HB3 = 0x8
3313                  *   VSC SDP supporting 3D stereo + PSR
3314                  * - HB2 = 0x4, HB3 = 0xe
3315                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3316                  *   first scan line of the SU region (applies to eDP v1.4b
3317                  *   and higher).
3318                  */
3319                 return 0;
3320         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3321                 /*
3322                  * - HB2 = 0x5, HB3 = 0x13
3323                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3324                  *   Format.
3325                  */
3326                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3327                 vsc->colorimetry = sdp->db[16] & 0xf;
3328                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3329
3330                 switch (sdp->db[17] & 0x7) {
3331                 case 0x0:
3332                         vsc->bpc = 6;
3333                         break;
3334                 case 0x1:
3335                         vsc->bpc = 8;
3336                         break;
3337                 case 0x2:
3338                         vsc->bpc = 10;
3339                         break;
3340                 case 0x3:
3341                         vsc->bpc = 12;
3342                         break;
3343                 case 0x4:
3344                         vsc->bpc = 16;
3345                         break;
3346                 default:
3347                         MISSING_CASE(sdp->db[17] & 0x7);
3348                         return -EINVAL;
3349                 }
3350
3351                 vsc->content_type = sdp->db[18] & 0x7;
3352         } else {
3353                 return -EINVAL;
3354         }
3355
3356         return 0;
3357 }
3358
3359 static int
3360 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3361                                            const void *buffer, size_t size)
3362 {
3363         int ret;
3364
3365         const struct dp_sdp *sdp = buffer;
3366
3367         if (size < sizeof(struct dp_sdp))
3368                 return -EINVAL;
3369
3370         if (sdp->sdp_header.HB0 != 0)
3371                 return -EINVAL;
3372
3373         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3374                 return -EINVAL;
3375
3376         /*
3377          * Least Significant Eight Bits of (Data Byte Count – 1)
3378          * 1Dh (i.e., Data Byte Count = 30 bytes).
3379          */
3380         if (sdp->sdp_header.HB2 != 0x1D)
3381                 return -EINVAL;
3382
3383         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3384         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3385                 return -EINVAL;
3386
3387         /* INFOFRAME SDP Version Number */
3388         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3389                 return -EINVAL;
3390
3391         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3392         if (sdp->db[0] != 1)
3393                 return -EINVAL;
3394
3395         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3396         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3397                 return -EINVAL;
3398
3399         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3400                                              HDMI_DRM_INFOFRAME_SIZE);
3401
3402         return ret;
3403 }
3404
3405 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3406                                   struct intel_crtc_state *crtc_state,
3407                                   struct drm_dp_vsc_sdp *vsc)
3408 {
3409         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3410         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3411         unsigned int type = DP_SDP_VSC;
3412         struct dp_sdp sdp = {};
3413         int ret;
3414
3415         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3416         if (crtc_state->has_psr)
3417                 return;
3418
3419         if ((crtc_state->infoframes.enable &
3420              intel_hdmi_infoframe_enable(type)) == 0)
3421                 return;
3422
3423         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3424
3425         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3426
3427         if (ret)
3428                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3429 }
3430
3431 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3432                                                      struct intel_crtc_state *crtc_state,
3433                                                      struct hdmi_drm_infoframe *drm_infoframe)
3434 {
3435         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3436         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3437         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3438         struct dp_sdp sdp = {};
3439         int ret;
3440
3441         if ((crtc_state->infoframes.enable &
3442             intel_hdmi_infoframe_enable(type)) == 0)
3443                 return;
3444
3445         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3446                                  sizeof(sdp));
3447
3448         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3449                                                          sizeof(sdp));
3450
3451         if (ret)
3452                 drm_dbg_kms(&dev_priv->drm,
3453                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3454 }
3455
3456 void intel_read_dp_sdp(struct intel_encoder *encoder,
3457                        struct intel_crtc_state *crtc_state,
3458                        unsigned int type)
3459 {
3460         switch (type) {
3461         case DP_SDP_VSC:
3462                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3463                                       &crtc_state->infoframes.vsc);
3464                 break;
3465         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3466                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3467                                                          &crtc_state->infoframes.drm.drm);
3468                 break;
3469         default:
3470                 MISSING_CASE(type);
3471                 break;
3472         }
3473 }
3474
3475 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3476 {
3477         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3478         int status = 0;
3479         int test_link_rate;
3480         u8 test_lane_count, test_link_bw;
3481         /* (DP CTS 1.2)
3482          * 4.3.1.11
3483          */
3484         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3485         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3486                                    &test_lane_count);
3487
3488         if (status <= 0) {
3489                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3490                 return DP_TEST_NAK;
3491         }
3492         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3493
3494         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3495                                    &test_link_bw);
3496         if (status <= 0) {
3497                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3498                 return DP_TEST_NAK;
3499         }
3500         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3501
3502         /* Validate the requested link rate and lane count */
3503         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3504                                         test_lane_count))
3505                 return DP_TEST_NAK;
3506
3507         intel_dp->compliance.test_lane_count = test_lane_count;
3508         intel_dp->compliance.test_link_rate = test_link_rate;
3509
3510         return DP_TEST_ACK;
3511 }
3512
3513 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3514 {
3515         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3516         u8 test_pattern;
3517         u8 test_misc;
3518         __be16 h_width, v_height;
3519         int status = 0;
3520
3521         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3522         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3523                                    &test_pattern);
3524         if (status <= 0) {
3525                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3526                 return DP_TEST_NAK;
3527         }
3528         if (test_pattern != DP_COLOR_RAMP)
3529                 return DP_TEST_NAK;
3530
3531         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3532                                   &h_width, 2);
3533         if (status <= 0) {
3534                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3535                 return DP_TEST_NAK;
3536         }
3537
3538         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3539                                   &v_height, 2);
3540         if (status <= 0) {
3541                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3542                 return DP_TEST_NAK;
3543         }
3544
3545         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3546                                    &test_misc);
3547         if (status <= 0) {
3548                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3549                 return DP_TEST_NAK;
3550         }
3551         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3552                 return DP_TEST_NAK;
3553         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3554                 return DP_TEST_NAK;
3555         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3556         case DP_TEST_BIT_DEPTH_6:
3557                 intel_dp->compliance.test_data.bpc = 6;
3558                 break;
3559         case DP_TEST_BIT_DEPTH_8:
3560                 intel_dp->compliance.test_data.bpc = 8;
3561                 break;
3562         default:
3563                 return DP_TEST_NAK;
3564         }
3565
3566         intel_dp->compliance.test_data.video_pattern = test_pattern;
3567         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3568         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3569         /* Set test active flag here so userspace doesn't interrupt things */
3570         intel_dp->compliance.test_active = true;
3571
3572         return DP_TEST_ACK;
3573 }
3574
3575 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3576 {
3577         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3578         u8 test_result = DP_TEST_ACK;
3579         struct intel_connector *intel_connector = intel_dp->attached_connector;
3580         struct drm_connector *connector = &intel_connector->base;
3581
3582         if (intel_connector->detect_edid == NULL ||
3583             connector->edid_corrupt ||
3584             intel_dp->aux.i2c_defer_count > 6) {
3585                 /* Check EDID read for NACKs, DEFERs and corruption
3586                  * (DP CTS 1.2 Core r1.1)
3587                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3588                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3589                  *    4.2.2.6 : EDID corruption detected
3590                  * Use failsafe mode for all cases
3591                  */
3592                 if (intel_dp->aux.i2c_nack_count > 0 ||
3593                         intel_dp->aux.i2c_defer_count > 0)
3594                         drm_dbg_kms(&i915->drm,
3595                                     "EDID read had %d NACKs, %d DEFERs\n",
3596                                     intel_dp->aux.i2c_nack_count,
3597                                     intel_dp->aux.i2c_defer_count);
3598                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3599         } else {
3600                 struct edid *block = intel_connector->detect_edid;
3601
3602                 /* We have to write the checksum
3603                  * of the last block read
3604                  */
3605                 block += intel_connector->detect_edid->extensions;
3606
3607                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3608                                        block->checksum) <= 0)
3609                         drm_dbg_kms(&i915->drm,
3610                                     "Failed to write EDID checksum\n");
3611
3612                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3613                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3614         }
3615
3616         /* Set test active flag here so userspace doesn't interrupt things */
3617         intel_dp->compliance.test_active = true;
3618
3619         return test_result;
3620 }
3621
3622 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3623                                         const struct intel_crtc_state *crtc_state)
3624 {
3625         struct drm_i915_private *dev_priv =
3626                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3627         struct drm_dp_phy_test_params *data =
3628                         &intel_dp->compliance.test_data.phytest;
3629         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3630         enum pipe pipe = crtc->pipe;
3631         u32 pattern_val;
3632
3633         switch (data->phy_pattern) {
3634         case DP_PHY_TEST_PATTERN_NONE:
3635                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3636                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3637                 break;
3638         case DP_PHY_TEST_PATTERN_D10_2:
3639                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3640                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3641                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3642                 break;
3643         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3644                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3645                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3646                                DDI_DP_COMP_CTL_ENABLE |
3647                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3648                 break;
3649         case DP_PHY_TEST_PATTERN_PRBS7:
3650                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3651                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3652                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3653                 break;
3654         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3655                 /*
3656                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3657                  * current firmware of DPR-100 could not set it, so hardcoding
3658                  * now for complaince test.
3659                  */
3660                 drm_dbg_kms(&dev_priv->drm,
3661                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3662                 pattern_val = 0x3e0f83e0;
3663                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3664                 pattern_val = 0x0f83e0f8;
3665                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3666                 pattern_val = 0x0000f83e;
3667                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3668                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3669                                DDI_DP_COMP_CTL_ENABLE |
3670                                DDI_DP_COMP_CTL_CUSTOM80);
3671                 break;
3672         case DP_PHY_TEST_PATTERN_CP2520:
3673                 /*
3674                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3675                  * current firmware of DPR-100 could not set it, so hardcoding
3676                  * now for complaince test.
3677                  */
3678                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3679                 pattern_val = 0xFB;
3680                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3681                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3682                                pattern_val);
3683                 break;
3684         default:
3685                 WARN(1, "Invalid Phy Test Pattern\n");
3686         }
3687 }
3688
3689 static void
3690 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3691                                   const struct intel_crtc_state *crtc_state)
3692 {
3693         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3694         struct drm_device *dev = dig_port->base.base.dev;
3695         struct drm_i915_private *dev_priv = to_i915(dev);
3696         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3697         enum pipe pipe = crtc->pipe;
3698         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3699
3700         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3701                                                  TRANS_DDI_FUNC_CTL(pipe));
3702         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3703         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3704
3705         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3706                                       TGL_TRANS_DDI_PORT_MASK);
3707         trans_conf_value &= ~PIPECONF_ENABLE;
3708         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3709
3710         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3711         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3712                        trans_ddi_func_ctl_value);
3713         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3714 }
3715
3716 static void
3717 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3718                                  const struct intel_crtc_state *crtc_state)
3719 {
3720         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3721         struct drm_device *dev = dig_port->base.base.dev;
3722         struct drm_i915_private *dev_priv = to_i915(dev);
3723         enum port port = dig_port->base.port;
3724         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3725         enum pipe pipe = crtc->pipe;
3726         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3727
3728         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3729                                                  TRANS_DDI_FUNC_CTL(pipe));
3730         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3731         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3732
3733         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3734                                     TGL_TRANS_DDI_SELECT_PORT(port);
3735         trans_conf_value |= PIPECONF_ENABLE;
3736         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3737
3738         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3739         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3740         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3741                        trans_ddi_func_ctl_value);
3742 }
3743
3744 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3745                                          const struct intel_crtc_state *crtc_state)
3746 {
3747         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3748         struct drm_dp_phy_test_params *data =
3749                 &intel_dp->compliance.test_data.phytest;
3750         u8 link_status[DP_LINK_STATUS_SIZE];
3751
3752         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3753                                              link_status) < 0) {
3754                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3755                 return;
3756         }
3757
3758         /* retrieve vswing & pre-emphasis setting */
3759         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3760                                   link_status);
3761
3762         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3763
3764         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3765
3766         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3767
3768         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3769
3770         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3771                           intel_dp->train_set, crtc_state->lane_count);
3772
3773         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3774                                     link_status[DP_DPCD_REV]);
3775 }
3776
3777 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3778 {
3779         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3780         struct drm_dp_phy_test_params *data =
3781                 &intel_dp->compliance.test_data.phytest;
3782
3783         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3784                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3785                 return DP_TEST_NAK;
3786         }
3787
3788         /* Set test active flag here so userspace doesn't interrupt things */
3789         intel_dp->compliance.test_active = true;
3790
3791         return DP_TEST_ACK;
3792 }
3793
3794 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3795 {
3796         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3797         u8 response = DP_TEST_NAK;
3798         u8 request = 0;
3799         int status;
3800
3801         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3802         if (status <= 0) {
3803                 drm_dbg_kms(&i915->drm,
3804                             "Could not read test request from sink\n");
3805                 goto update_status;
3806         }
3807
3808         switch (request) {
3809         case DP_TEST_LINK_TRAINING:
3810                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3811                 response = intel_dp_autotest_link_training(intel_dp);
3812                 break;
3813         case DP_TEST_LINK_VIDEO_PATTERN:
3814                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3815                 response = intel_dp_autotest_video_pattern(intel_dp);
3816                 break;
3817         case DP_TEST_LINK_EDID_READ:
3818                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3819                 response = intel_dp_autotest_edid(intel_dp);
3820                 break;
3821         case DP_TEST_LINK_PHY_TEST_PATTERN:
3822                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3823                 response = intel_dp_autotest_phy_pattern(intel_dp);
3824                 break;
3825         default:
3826                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3827                             request);
3828                 break;
3829         }
3830
3831         if (response & DP_TEST_ACK)
3832                 intel_dp->compliance.test_type = request;
3833
3834 update_status:
3835         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3836         if (status <= 0)
3837                 drm_dbg_kms(&i915->drm,
3838                             "Could not write test response to sink\n");
3839 }
3840
3841 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3842                              u8 link_status[DP_LINK_STATUS_SIZE])
3843 {
3844         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3845         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3846         bool uhbr = intel_dp->link_rate >= 1000000;
3847         bool ok;
3848
3849         if (uhbr)
3850                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3851                                                           intel_dp->lane_count);
3852         else
3853                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3854
3855         if (ok)
3856                 return true;
3857
3858         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3859         drm_dbg_kms(&i915->drm,
3860                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
3861                     encoder->base.base.id, encoder->base.name,
3862                     uhbr ? "128b/132b" : "8b/10b");
3863
3864         return false;
3865 }
3866
3867 static void
3868 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3869 {
3870         bool handled = false;
3871
3872         drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3873         if (handled)
3874                 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3875
3876         if (esi[1] & DP_CP_IRQ) {
3877                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3878                 ack[1] |= DP_CP_IRQ;
3879         }
3880 }
3881
3882 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3883 {
3884         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3885         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3886         u8 link_status[DP_LINK_STATUS_SIZE] = {};
3887         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3888
3889         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3890                              esi_link_status_size) != esi_link_status_size) {
3891                 drm_err(&i915->drm,
3892                         "[ENCODER:%d:%s] Failed to read link status\n",
3893                         encoder->base.base.id, encoder->base.name);
3894                 return false;
3895         }
3896
3897         return intel_dp_link_ok(intel_dp, link_status);
3898 }
3899
3900 /**
3901  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3902  * @intel_dp: Intel DP struct
3903  *
3904  * Read any pending MST interrupts, call MST core to handle these and ack the
3905  * interrupts. Check if the main and AUX link state is ok.
3906  *
3907  * Returns:
3908  * - %true if pending interrupts were serviced (or no interrupts were
3909  *   pending) w/o detecting an error condition.
3910  * - %false if an error condition - like AUX failure or a loss of link - is
3911  *   detected, which needs servicing from the hotplug work.
3912  */
3913 static bool
3914 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3915 {
3916         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3917         bool link_ok = true;
3918
3919         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3920
3921         for (;;) {
3922                 u8 esi[4] = {};
3923                 u8 ack[4] = {};
3924
3925                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3926                         drm_dbg_kms(&i915->drm,
3927                                     "failed to get ESI - device may have failed\n");
3928                         link_ok = false;
3929
3930                         break;
3931                 }
3932
3933                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3934
3935                 if (intel_dp->active_mst_links > 0 && link_ok &&
3936                     esi[3] & LINK_STATUS_CHANGED) {
3937                         if (!intel_dp_mst_link_status(intel_dp))
3938                                 link_ok = false;
3939                         ack[3] |= LINK_STATUS_CHANGED;
3940                 }
3941
3942                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3943
3944                 if (!memchr_inv(ack, 0, sizeof(ack)))
3945                         break;
3946
3947                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3948                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3949         }
3950
3951         return link_ok;
3952 }
3953
3954 static void
3955 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3956 {
3957         bool is_active;
3958         u8 buf = 0;
3959
3960         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3961         if (intel_dp->frl.is_trained && !is_active) {
3962                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3963                         return;
3964
3965                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3966                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3967                         return;
3968
3969                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3970
3971                 /* Restart FRL training or fall back to TMDS mode */
3972                 intel_dp_check_frl_training(intel_dp);
3973         }
3974 }
3975
3976 static bool
3977 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3978 {
3979         u8 link_status[DP_LINK_STATUS_SIZE];
3980
3981         if (!intel_dp->link_trained)
3982                 return false;
3983
3984         /*
3985          * While PSR source HW is enabled, it will control main-link sending
3986          * frames, enabling and disabling it so trying to do a retrain will fail
3987          * as the link would or not be on or it could mix training patterns
3988          * and frame data at the same time causing retrain to fail.
3989          * Also when exiting PSR, HW will retrain the link anyways fixing
3990          * any link status error.
3991          */
3992         if (intel_psr_enabled(intel_dp))
3993                 return false;
3994
3995         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3996                                              link_status) < 0)
3997                 return false;
3998
3999         /*
4000          * Validate the cached values of intel_dp->link_rate and
4001          * intel_dp->lane_count before attempting to retrain.
4002          *
4003          * FIXME would be nice to user the crtc state here, but since
4004          * we need to call this from the short HPD handler that seems
4005          * a bit hard.
4006          */
4007         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4008                                         intel_dp->lane_count))
4009                 return false;
4010
4011         /* Retrain if link not ok */
4012         return !intel_dp_link_ok(intel_dp, link_status);
4013 }
4014
4015 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4016                                    const struct drm_connector_state *conn_state)
4017 {
4018         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4019         struct intel_encoder *encoder;
4020         enum pipe pipe;
4021
4022         if (!conn_state->best_encoder)
4023                 return false;
4024
4025         /* SST */
4026         encoder = &dp_to_dig_port(intel_dp)->base;
4027         if (conn_state->best_encoder == &encoder->base)
4028                 return true;
4029
4030         /* MST */
4031         for_each_pipe(i915, pipe) {
4032                 encoder = &intel_dp->mst_encoders[pipe]->base;
4033                 if (conn_state->best_encoder == &encoder->base)
4034                         return true;
4035         }
4036
4037         return false;
4038 }
4039
4040 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
4041                                       struct drm_modeset_acquire_ctx *ctx,
4042                                       u8 *pipe_mask)
4043 {
4044         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4045         struct drm_connector_list_iter conn_iter;
4046         struct intel_connector *connector;
4047         int ret = 0;
4048
4049         *pipe_mask = 0;
4050
4051         if (!intel_dp_needs_link_retrain(intel_dp))
4052                 return 0;
4053
4054         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4055         for_each_intel_connector_iter(connector, &conn_iter) {
4056                 struct drm_connector_state *conn_state =
4057                         connector->base.state;
4058                 struct intel_crtc_state *crtc_state;
4059                 struct intel_crtc *crtc;
4060
4061                 if (!intel_dp_has_connector(intel_dp, conn_state))
4062                         continue;
4063
4064                 crtc = to_intel_crtc(conn_state->crtc);
4065                 if (!crtc)
4066                         continue;
4067
4068                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4069                 if (ret)
4070                         break;
4071
4072                 crtc_state = to_intel_crtc_state(crtc->base.state);
4073
4074                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4075
4076                 if (!crtc_state->hw.active)
4077                         continue;
4078
4079                 if (conn_state->commit &&
4080                     !try_wait_for_completion(&conn_state->commit->hw_done))
4081                         continue;
4082
4083                 *pipe_mask |= BIT(crtc->pipe);
4084         }
4085         drm_connector_list_iter_end(&conn_iter);
4086
4087         if (!intel_dp_needs_link_retrain(intel_dp))
4088                 *pipe_mask = 0;
4089
4090         return ret;
4091 }
4092
4093 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4094 {
4095         struct intel_connector *connector = intel_dp->attached_connector;
4096
4097         return connector->base.status == connector_status_connected ||
4098                 intel_dp->is_mst;
4099 }
4100
4101 int intel_dp_retrain_link(struct intel_encoder *encoder,
4102                           struct drm_modeset_acquire_ctx *ctx)
4103 {
4104         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4105         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4106         struct intel_crtc *crtc;
4107         u8 pipe_mask;
4108         int ret;
4109
4110         if (!intel_dp_is_connected(intel_dp))
4111                 return 0;
4112
4113         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4114                                ctx);
4115         if (ret)
4116                 return ret;
4117
4118         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4119         if (ret)
4120                 return ret;
4121
4122         if (pipe_mask == 0)
4123                 return 0;
4124
4125         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4126                     encoder->base.base.id, encoder->base.name);
4127
4128         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4129                 const struct intel_crtc_state *crtc_state =
4130                         to_intel_crtc_state(crtc->base.state);
4131
4132                 /* Suppress underruns caused by re-training */
4133                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4134                 if (crtc_state->has_pch_encoder)
4135                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4136                                                               intel_crtc_pch_transcoder(crtc), false);
4137         }
4138
4139         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4140                 const struct intel_crtc_state *crtc_state =
4141                         to_intel_crtc_state(crtc->base.state);
4142
4143                 /* retrain on the MST master transcoder */
4144                 if (DISPLAY_VER(dev_priv) >= 12 &&
4145                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4146                     !intel_dp_mst_is_master_trans(crtc_state))
4147                         continue;
4148
4149                 intel_dp_check_frl_training(intel_dp);
4150                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4151                 intel_dp_start_link_train(intel_dp, crtc_state);
4152                 intel_dp_stop_link_train(intel_dp, crtc_state);
4153                 break;
4154         }
4155
4156         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4157                 const struct intel_crtc_state *crtc_state =
4158                         to_intel_crtc_state(crtc->base.state);
4159
4160                 /* Keep underrun reporting disabled until things are stable */
4161                 intel_crtc_wait_for_next_vblank(crtc);
4162
4163                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4164                 if (crtc_state->has_pch_encoder)
4165                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4166                                                               intel_crtc_pch_transcoder(crtc), true);
4167         }
4168
4169         return 0;
4170 }
4171
4172 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4173                                   struct drm_modeset_acquire_ctx *ctx,
4174                                   u8 *pipe_mask)
4175 {
4176         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4177         struct drm_connector_list_iter conn_iter;
4178         struct intel_connector *connector;
4179         int ret = 0;
4180
4181         *pipe_mask = 0;
4182
4183         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4184         for_each_intel_connector_iter(connector, &conn_iter) {
4185                 struct drm_connector_state *conn_state =
4186                         connector->base.state;
4187                 struct intel_crtc_state *crtc_state;
4188                 struct intel_crtc *crtc;
4189
4190                 if (!intel_dp_has_connector(intel_dp, conn_state))
4191                         continue;
4192
4193                 crtc = to_intel_crtc(conn_state->crtc);
4194                 if (!crtc)
4195                         continue;
4196
4197                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4198                 if (ret)
4199                         break;
4200
4201                 crtc_state = to_intel_crtc_state(crtc->base.state);
4202
4203                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4204
4205                 if (!crtc_state->hw.active)
4206                         continue;
4207
4208                 if (conn_state->commit &&
4209                     !try_wait_for_completion(&conn_state->commit->hw_done))
4210                         continue;
4211
4212                 *pipe_mask |= BIT(crtc->pipe);
4213         }
4214         drm_connector_list_iter_end(&conn_iter);
4215
4216         return ret;
4217 }
4218
4219 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4220                                 struct drm_modeset_acquire_ctx *ctx)
4221 {
4222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4223         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4224         struct intel_crtc *crtc;
4225         u8 pipe_mask;
4226         int ret;
4227
4228         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4229                                ctx);
4230         if (ret)
4231                 return ret;
4232
4233         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4234         if (ret)
4235                 return ret;
4236
4237         if (pipe_mask == 0)
4238                 return 0;
4239
4240         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4241                     encoder->base.base.id, encoder->base.name);
4242
4243         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4244                 const struct intel_crtc_state *crtc_state =
4245                         to_intel_crtc_state(crtc->base.state);
4246
4247                 /* test on the MST master transcoder */
4248                 if (DISPLAY_VER(dev_priv) >= 12 &&
4249                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4250                     !intel_dp_mst_is_master_trans(crtc_state))
4251                         continue;
4252
4253                 intel_dp_process_phy_request(intel_dp, crtc_state);
4254                 break;
4255         }
4256
4257         return 0;
4258 }
4259
4260 void intel_dp_phy_test(struct intel_encoder *encoder)
4261 {
4262         struct drm_modeset_acquire_ctx ctx;
4263         int ret;
4264
4265         drm_modeset_acquire_init(&ctx, 0);
4266
4267         for (;;) {
4268                 ret = intel_dp_do_phy_test(encoder, &ctx);
4269
4270                 if (ret == -EDEADLK) {
4271                         drm_modeset_backoff(&ctx);
4272                         continue;
4273                 }
4274
4275                 break;
4276         }
4277
4278         drm_modeset_drop_locks(&ctx);
4279         drm_modeset_acquire_fini(&ctx);
4280         drm_WARN(encoder->base.dev, ret,
4281                  "Acquiring modeset locks failed with %i\n", ret);
4282 }
4283
4284 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4285 {
4286         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4287         u8 val;
4288
4289         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4290                 return;
4291
4292         if (drm_dp_dpcd_readb(&intel_dp->aux,
4293                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4294                 return;
4295
4296         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4297
4298         if (val & DP_AUTOMATED_TEST_REQUEST)
4299                 intel_dp_handle_test_request(intel_dp);
4300
4301         if (val & DP_CP_IRQ)
4302                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4303
4304         if (val & DP_SINK_SPECIFIC_IRQ)
4305                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4306 }
4307
4308 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4309 {
4310         u8 val;
4311
4312         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4313                 return;
4314
4315         if (drm_dp_dpcd_readb(&intel_dp->aux,
4316                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4317                 return;
4318
4319         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4320                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4321                 return;
4322
4323         if (val & HDMI_LINK_STATUS_CHANGED)
4324                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4325 }
4326
4327 /*
4328  * According to DP spec
4329  * 5.1.2:
4330  *  1. Read DPCD
4331  *  2. Configure link according to Receiver Capabilities
4332  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4333  *  4. Check link status on receipt of hot-plug interrupt
4334  *
4335  * intel_dp_short_pulse -  handles short pulse interrupts
4336  * when full detection is not required.
4337  * Returns %true if short pulse is handled and full detection
4338  * is NOT required and %false otherwise.
4339  */
4340 static bool
4341 intel_dp_short_pulse(struct intel_dp *intel_dp)
4342 {
4343         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4344         u8 old_sink_count = intel_dp->sink_count;
4345         bool ret;
4346
4347         /*
4348          * Clearing compliance test variables to allow capturing
4349          * of values for next automated test request.
4350          */
4351         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4352
4353         /*
4354          * Now read the DPCD to see if it's actually running
4355          * If the current value of sink count doesn't match with
4356          * the value that was stored earlier or dpcd read failed
4357          * we need to do full detection
4358          */
4359         ret = intel_dp_get_dpcd(intel_dp);
4360
4361         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4362                 /* No need to proceed if we are going to do full detect */
4363                 return false;
4364         }
4365
4366         intel_dp_check_device_service_irq(intel_dp);
4367         intel_dp_check_link_service_irq(intel_dp);
4368
4369         /* Handle CEC interrupts, if any */
4370         drm_dp_cec_irq(&intel_dp->aux);
4371
4372         /* defer to the hotplug work for link retraining if needed */
4373         if (intel_dp_needs_link_retrain(intel_dp))
4374                 return false;
4375
4376         intel_psr_short_pulse(intel_dp);
4377
4378         switch (intel_dp->compliance.test_type) {
4379         case DP_TEST_LINK_TRAINING:
4380                 drm_dbg_kms(&dev_priv->drm,
4381                             "Link Training Compliance Test requested\n");
4382                 /* Send a Hotplug Uevent to userspace to start modeset */
4383                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4384                 break;
4385         case DP_TEST_LINK_PHY_TEST_PATTERN:
4386                 drm_dbg_kms(&dev_priv->drm,
4387                             "PHY test pattern Compliance Test requested\n");
4388                 /*
4389                  * Schedule long hpd to do the test
4390                  *
4391                  * FIXME get rid of the ad-hoc phy test modeset code
4392                  * and properly incorporate it into the normal modeset.
4393                  */
4394                 return false;
4395         }
4396
4397         return true;
4398 }
4399
4400 /* XXX this is probably wrong for multiple downstream ports */
4401 static enum drm_connector_status
4402 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4403 {
4404         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4405         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4406         u8 *dpcd = intel_dp->dpcd;
4407         u8 type;
4408
4409         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4410                 return connector_status_connected;
4411
4412         lspcon_resume(dig_port);
4413
4414         if (!intel_dp_get_dpcd(intel_dp))
4415                 return connector_status_disconnected;
4416
4417         /* if there's no downstream port, we're done */
4418         if (!drm_dp_is_branch(dpcd))
4419                 return connector_status_connected;
4420
4421         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4422         if (intel_dp_has_sink_count(intel_dp) &&
4423             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4424                 return intel_dp->sink_count ?
4425                 connector_status_connected : connector_status_disconnected;
4426         }
4427
4428         if (intel_dp_can_mst(intel_dp))
4429                 return connector_status_connected;
4430
4431         /* If no HPD, poke DDC gently */
4432         if (drm_probe_ddc(&intel_dp->aux.ddc))
4433                 return connector_status_connected;
4434
4435         /* Well we tried, say unknown for unreliable port types */
4436         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4437                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4438                 if (type == DP_DS_PORT_TYPE_VGA ||
4439                     type == DP_DS_PORT_TYPE_NON_EDID)
4440                         return connector_status_unknown;
4441         } else {
4442                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4443                         DP_DWN_STRM_PORT_TYPE_MASK;
4444                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4445                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4446                         return connector_status_unknown;
4447         }
4448
4449         /* Anything else is out of spec, warn and ignore */
4450         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4451         return connector_status_disconnected;
4452 }
4453
4454 static enum drm_connector_status
4455 edp_detect(struct intel_dp *intel_dp)
4456 {
4457         return connector_status_connected;
4458 }
4459
4460 /*
4461  * intel_digital_port_connected - is the specified port connected?
4462  * @encoder: intel_encoder
4463  *
4464  * In cases where there's a connector physically connected but it can't be used
4465  * by our hardware we also return false, since the rest of the driver should
4466  * pretty much treat the port as disconnected. This is relevant for type-C
4467  * (starting on ICL) where there's ownership involved.
4468  *
4469  * Return %true if port is connected, %false otherwise.
4470  */
4471 bool intel_digital_port_connected(struct intel_encoder *encoder)
4472 {
4473         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4474         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4475         bool is_connected = false;
4476         intel_wakeref_t wakeref;
4477
4478         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4479                 is_connected = dig_port->connected(encoder);
4480
4481         return is_connected;
4482 }
4483
4484 static struct edid *
4485 intel_dp_get_edid(struct intel_dp *intel_dp)
4486 {
4487         struct intel_connector *intel_connector = intel_dp->attached_connector;
4488
4489         /* use cached edid if we have one */
4490         if (intel_connector->edid) {
4491                 /* invalid edid */
4492                 if (IS_ERR(intel_connector->edid))
4493                         return NULL;
4494
4495                 return drm_edid_duplicate(intel_connector->edid);
4496         } else
4497                 return drm_get_edid(&intel_connector->base,
4498                                     &intel_dp->aux.ddc);
4499 }
4500
4501 static void
4502 intel_dp_update_dfp(struct intel_dp *intel_dp,
4503                     const struct edid *edid)
4504 {
4505         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4506         struct intel_connector *connector = intel_dp->attached_connector;
4507
4508         intel_dp->dfp.max_bpc =
4509                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4510                                           intel_dp->downstream_ports, edid);
4511
4512         intel_dp->dfp.max_dotclock =
4513                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4514                                                intel_dp->downstream_ports);
4515
4516         intel_dp->dfp.min_tmds_clock =
4517                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4518                                                  intel_dp->downstream_ports,
4519                                                  edid);
4520         intel_dp->dfp.max_tmds_clock =
4521                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4522                                                  intel_dp->downstream_ports,
4523                                                  edid);
4524
4525         intel_dp->dfp.pcon_max_frl_bw =
4526                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4527                                            intel_dp->downstream_ports);
4528
4529         drm_dbg_kms(&i915->drm,
4530                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4531                     connector->base.base.id, connector->base.name,
4532                     intel_dp->dfp.max_bpc,
4533                     intel_dp->dfp.max_dotclock,
4534                     intel_dp->dfp.min_tmds_clock,
4535                     intel_dp->dfp.max_tmds_clock,
4536                     intel_dp->dfp.pcon_max_frl_bw);
4537
4538         intel_dp_get_pcon_dsc_cap(intel_dp);
4539 }
4540
4541 static void
4542 intel_dp_update_420(struct intel_dp *intel_dp)
4543 {
4544         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4545         struct intel_connector *connector = intel_dp->attached_connector;
4546         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4547
4548         /* No YCbCr output support on gmch platforms */
4549         if (HAS_GMCH(i915))
4550                 return;
4551
4552         /*
4553          * ILK doesn't seem capable of DP YCbCr output. The
4554          * displayed image is severly corrupted. SNB+ is fine.
4555          */
4556         if (IS_IRONLAKE(i915))
4557                 return;
4558
4559         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4560         ycbcr_420_passthrough =
4561                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4562                                                   intel_dp->downstream_ports);
4563         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4564         ycbcr_444_to_420 =
4565                 dp_to_dig_port(intel_dp)->lspcon.active ||
4566                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4567                                                         intel_dp->downstream_ports);
4568         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4569                                                                  intel_dp->downstream_ports,
4570                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4571
4572         if (DISPLAY_VER(i915) >= 11) {
4573                 /* Let PCON convert from RGB->YCbCr if possible */
4574                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4575                         intel_dp->dfp.rgb_to_ycbcr = true;
4576                         intel_dp->dfp.ycbcr_444_to_420 = true;
4577                         connector->base.ycbcr_420_allowed = true;
4578                 } else {
4579                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4580                         intel_dp->dfp.ycbcr_444_to_420 =
4581                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4582
4583                         connector->base.ycbcr_420_allowed =
4584                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4585                 }
4586         } else {
4587                 /* 4:4:4->4:2:0 conversion is the only way */
4588                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4589
4590                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4591         }
4592
4593         drm_dbg_kms(&i915->drm,
4594                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4595                     connector->base.base.id, connector->base.name,
4596                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4597                     str_yes_no(connector->base.ycbcr_420_allowed),
4598                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4599 }
4600
4601 static void
4602 intel_dp_set_edid(struct intel_dp *intel_dp)
4603 {
4604         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4605         struct intel_connector *connector = intel_dp->attached_connector;
4606         struct edid *edid;
4607         bool vrr_capable;
4608
4609         intel_dp_unset_edid(intel_dp);
4610         edid = intel_dp_get_edid(intel_dp);
4611         connector->detect_edid = edid;
4612
4613         vrr_capable = intel_vrr_is_capable(connector);
4614         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4615                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4616         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4617
4618         intel_dp_update_dfp(intel_dp, edid);
4619         intel_dp_update_420(intel_dp);
4620
4621         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4622                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4623                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4624         }
4625
4626         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4627 }
4628
4629 static void
4630 intel_dp_unset_edid(struct intel_dp *intel_dp)
4631 {
4632         struct intel_connector *connector = intel_dp->attached_connector;
4633
4634         drm_dp_cec_unset_edid(&intel_dp->aux);
4635         kfree(connector->detect_edid);
4636         connector->detect_edid = NULL;
4637
4638         intel_dp->has_hdmi_sink = false;
4639         intel_dp->has_audio = false;
4640
4641         intel_dp->dfp.max_bpc = 0;
4642         intel_dp->dfp.max_dotclock = 0;
4643         intel_dp->dfp.min_tmds_clock = 0;
4644         intel_dp->dfp.max_tmds_clock = 0;
4645
4646         intel_dp->dfp.pcon_max_frl_bw = 0;
4647
4648         intel_dp->dfp.ycbcr_444_to_420 = false;
4649         connector->base.ycbcr_420_allowed = false;
4650
4651         drm_connector_set_vrr_capable_property(&connector->base,
4652                                                false);
4653 }
4654
4655 static int
4656 intel_dp_detect(struct drm_connector *connector,
4657                 struct drm_modeset_acquire_ctx *ctx,
4658                 bool force)
4659 {
4660         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4661         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4662         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4663         struct intel_encoder *encoder = &dig_port->base;
4664         enum drm_connector_status status;
4665
4666         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4667                     connector->base.id, connector->name);
4668         drm_WARN_ON(&dev_priv->drm,
4669                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4670
4671         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4672                 return connector_status_disconnected;
4673
4674         /* Can't disconnect eDP */
4675         if (intel_dp_is_edp(intel_dp))
4676                 status = edp_detect(intel_dp);
4677         else if (intel_digital_port_connected(encoder))
4678                 status = intel_dp_detect_dpcd(intel_dp);
4679         else
4680                 status = connector_status_disconnected;
4681
4682         if (status == connector_status_disconnected) {
4683                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4684                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4685
4686                 if (intel_dp->is_mst) {
4687                         drm_dbg_kms(&dev_priv->drm,
4688                                     "MST device may have disappeared %d vs %d\n",
4689                                     intel_dp->is_mst,
4690                                     intel_dp->mst_mgr.mst_state);
4691                         intel_dp->is_mst = false;
4692                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4693                                                         intel_dp->is_mst);
4694                 }
4695
4696                 goto out;
4697         }
4698
4699         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4700         if (DISPLAY_VER(dev_priv) >= 11)
4701                 intel_dp_get_dsc_sink_cap(intel_dp);
4702
4703         intel_dp_configure_mst(intel_dp);
4704
4705         /*
4706          * TODO: Reset link params when switching to MST mode, until MST
4707          * supports link training fallback params.
4708          */
4709         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4710                 intel_dp_reset_max_link_params(intel_dp);
4711                 intel_dp->reset_link_params = false;
4712         }
4713
4714         intel_dp_print_rates(intel_dp);
4715
4716         if (intel_dp->is_mst) {
4717                 /*
4718                  * If we are in MST mode then this connector
4719                  * won't appear connected or have anything
4720                  * with EDID on it
4721                  */
4722                 status = connector_status_disconnected;
4723                 goto out;
4724         }
4725
4726         /*
4727          * Some external monitors do not signal loss of link synchronization
4728          * with an IRQ_HPD, so force a link status check.
4729          */
4730         if (!intel_dp_is_edp(intel_dp)) {
4731                 int ret;
4732
4733                 ret = intel_dp_retrain_link(encoder, ctx);
4734                 if (ret)
4735                         return ret;
4736         }
4737
4738         /*
4739          * Clearing NACK and defer counts to get their exact values
4740          * while reading EDID which are required by Compliance tests
4741          * 4.2.2.4 and 4.2.2.5
4742          */
4743         intel_dp->aux.i2c_nack_count = 0;
4744         intel_dp->aux.i2c_defer_count = 0;
4745
4746         intel_dp_set_edid(intel_dp);
4747         if (intel_dp_is_edp(intel_dp) ||
4748             to_intel_connector(connector)->detect_edid)
4749                 status = connector_status_connected;
4750
4751         intel_dp_check_device_service_irq(intel_dp);
4752
4753 out:
4754         if (status != connector_status_connected && !intel_dp->is_mst)
4755                 intel_dp_unset_edid(intel_dp);
4756
4757         /*
4758          * Make sure the refs for power wells enabled during detect are
4759          * dropped to avoid a new detect cycle triggered by HPD polling.
4760          */
4761         intel_display_power_flush_work(dev_priv);
4762
4763         if (!intel_dp_is_edp(intel_dp))
4764                 drm_dp_set_subconnector_property(connector,
4765                                                  status,
4766                                                  intel_dp->dpcd,
4767                                                  intel_dp->downstream_ports);
4768         return status;
4769 }
4770
4771 static void
4772 intel_dp_force(struct drm_connector *connector)
4773 {
4774         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4775         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4776         struct intel_encoder *intel_encoder = &dig_port->base;
4777         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4778         enum intel_display_power_domain aux_domain =
4779                 intel_aux_power_domain(dig_port);
4780         intel_wakeref_t wakeref;
4781
4782         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4783                     connector->base.id, connector->name);
4784         intel_dp_unset_edid(intel_dp);
4785
4786         if (connector->status != connector_status_connected)
4787                 return;
4788
4789         wakeref = intel_display_power_get(dev_priv, aux_domain);
4790
4791         intel_dp_set_edid(intel_dp);
4792
4793         intel_display_power_put(dev_priv, aux_domain, wakeref);
4794 }
4795
4796 static int intel_dp_get_modes(struct drm_connector *connector)
4797 {
4798         struct intel_connector *intel_connector = to_intel_connector(connector);
4799         struct edid *edid;
4800         int num_modes = 0;
4801
4802         edid = intel_connector->detect_edid;
4803         if (edid)
4804                 num_modes = intel_connector_update_modes(connector, edid);
4805
4806         /* Also add fixed mode, which may or may not be present in EDID */
4807         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4808                 num_modes += intel_panel_get_modes(intel_connector);
4809
4810         if (num_modes)
4811                 return num_modes;
4812
4813         if (!edid) {
4814                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4815                 struct drm_display_mode *mode;
4816
4817                 mode = drm_dp_downstream_mode(connector->dev,
4818                                               intel_dp->dpcd,
4819                                               intel_dp->downstream_ports);
4820                 if (mode) {
4821                         drm_mode_probed_add(connector, mode);
4822                         num_modes++;
4823                 }
4824         }
4825
4826         return num_modes;
4827 }
4828
4829 static int
4830 intel_dp_connector_register(struct drm_connector *connector)
4831 {
4832         struct drm_i915_private *i915 = to_i915(connector->dev);
4833         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4834         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4835         struct intel_lspcon *lspcon = &dig_port->lspcon;
4836         int ret;
4837
4838         ret = intel_connector_register(connector);
4839         if (ret)
4840                 return ret;
4841
4842         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4843                     intel_dp->aux.name, connector->kdev->kobj.name);
4844
4845         intel_dp->aux.dev = connector->kdev;
4846         ret = drm_dp_aux_register(&intel_dp->aux);
4847         if (!ret)
4848                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4849
4850         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4851                 return ret;
4852
4853         /*
4854          * ToDo: Clean this up to handle lspcon init and resume more
4855          * efficiently and streamlined.
4856          */
4857         if (lspcon_init(dig_port)) {
4858                 lspcon_detect_hdr_capability(lspcon);
4859                 if (lspcon->hdr_supported)
4860                         drm_connector_attach_hdr_output_metadata_property(connector);
4861         }
4862
4863         return ret;
4864 }
4865
4866 static void
4867 intel_dp_connector_unregister(struct drm_connector *connector)
4868 {
4869         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4870
4871         drm_dp_cec_unregister_connector(&intel_dp->aux);
4872         drm_dp_aux_unregister(&intel_dp->aux);
4873         intel_connector_unregister(connector);
4874 }
4875
4876 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4877 {
4878         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4879         struct intel_dp *intel_dp = &dig_port->dp;
4880
4881         intel_dp_mst_encoder_cleanup(dig_port);
4882
4883         intel_pps_vdd_off_sync(intel_dp);
4884
4885         intel_dp_aux_fini(intel_dp);
4886 }
4887
4888 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4889 {
4890         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4891
4892         intel_pps_vdd_off_sync(intel_dp);
4893 }
4894
4895 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4896 {
4897         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4898
4899         intel_pps_wait_power_cycle(intel_dp);
4900 }
4901
4902 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4903                                     int tile_group_id)
4904 {
4905         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4906         struct drm_connector_list_iter conn_iter;
4907         struct drm_connector *connector;
4908         int ret = 0;
4909
4910         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4911         drm_for_each_connector_iter(connector, &conn_iter) {
4912                 struct drm_connector_state *conn_state;
4913                 struct intel_crtc_state *crtc_state;
4914                 struct intel_crtc *crtc;
4915
4916                 if (!connector->has_tile ||
4917                     connector->tile_group->id != tile_group_id)
4918                         continue;
4919
4920                 conn_state = drm_atomic_get_connector_state(&state->base,
4921                                                             connector);
4922                 if (IS_ERR(conn_state)) {
4923                         ret = PTR_ERR(conn_state);
4924                         break;
4925                 }
4926
4927                 crtc = to_intel_crtc(conn_state->crtc);
4928
4929                 if (!crtc)
4930                         continue;
4931
4932                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4933                 crtc_state->uapi.mode_changed = true;
4934
4935                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4936                 if (ret)
4937                         break;
4938         }
4939         drm_connector_list_iter_end(&conn_iter);
4940
4941         return ret;
4942 }
4943
4944 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4945 {
4946         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4947         struct intel_crtc *crtc;
4948
4949         if (transcoders == 0)
4950                 return 0;
4951
4952         for_each_intel_crtc(&dev_priv->drm, crtc) {
4953                 struct intel_crtc_state *crtc_state;
4954                 int ret;
4955
4956                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4957                 if (IS_ERR(crtc_state))
4958                         return PTR_ERR(crtc_state);
4959
4960                 if (!crtc_state->hw.enable)
4961                         continue;
4962
4963                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4964                         continue;
4965
4966                 crtc_state->uapi.mode_changed = true;
4967
4968                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4969                 if (ret)
4970                         return ret;
4971
4972                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4973                 if (ret)
4974                         return ret;
4975
4976                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4977         }
4978
4979         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4980
4981         return 0;
4982 }
4983
4984 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4985                                       struct drm_connector *connector)
4986 {
4987         const struct drm_connector_state *old_conn_state =
4988                 drm_atomic_get_old_connector_state(&state->base, connector);
4989         const struct intel_crtc_state *old_crtc_state;
4990         struct intel_crtc *crtc;
4991         u8 transcoders;
4992
4993         crtc = to_intel_crtc(old_conn_state->crtc);
4994         if (!crtc)
4995                 return 0;
4996
4997         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4998
4999         if (!old_crtc_state->hw.active)
5000                 return 0;
5001
5002         transcoders = old_crtc_state->sync_mode_slaves_mask;
5003         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5004                 transcoders |= BIT(old_crtc_state->master_transcoder);
5005
5006         return intel_modeset_affected_transcoders(state,
5007                                                   transcoders);
5008 }
5009
5010 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5011                                            struct drm_atomic_state *_state)
5012 {
5013         struct drm_i915_private *dev_priv = to_i915(conn->dev);
5014         struct intel_atomic_state *state = to_intel_atomic_state(_state);
5015         int ret;
5016
5017         ret = intel_digital_connector_atomic_check(conn, &state->base);
5018         if (ret)
5019                 return ret;
5020
5021         /*
5022          * We don't enable port sync on BDW due to missing w/as and
5023          * due to not having adjusted the modeset sequence appropriately.
5024          */
5025         if (DISPLAY_VER(dev_priv) < 9)
5026                 return 0;
5027
5028         if (!intel_connector_needs_modeset(state, conn))
5029                 return 0;
5030
5031         if (conn->has_tile) {
5032                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5033                 if (ret)
5034                         return ret;
5035         }
5036
5037         return intel_modeset_synced_crtcs(state, conn);
5038 }
5039
5040 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5041 {
5042         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5043         struct drm_i915_private *i915 = to_i915(connector->dev);
5044
5045         spin_lock_irq(&i915->irq_lock);
5046         i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
5047         spin_unlock_irq(&i915->irq_lock);
5048         queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
5049 }
5050
5051 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5052         .force = intel_dp_force,
5053         .fill_modes = drm_helper_probe_single_connector_modes,
5054         .atomic_get_property = intel_digital_connector_atomic_get_property,
5055         .atomic_set_property = intel_digital_connector_atomic_set_property,
5056         .late_register = intel_dp_connector_register,
5057         .early_unregister = intel_dp_connector_unregister,
5058         .destroy = intel_connector_destroy,
5059         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5060         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5061         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5062 };
5063
5064 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5065         .detect_ctx = intel_dp_detect,
5066         .get_modes = intel_dp_get_modes,
5067         .mode_valid = intel_dp_mode_valid,
5068         .atomic_check = intel_dp_connector_atomic_check,
5069 };
5070
5071 enum irqreturn
5072 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5073 {
5074         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5075         struct intel_dp *intel_dp = &dig_port->dp;
5076
5077         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5078             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5079                 /*
5080                  * vdd off can generate a long/short pulse on eDP which
5081                  * would require vdd on to handle it, and thus we
5082                  * would end up in an endless cycle of
5083                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5084                  */
5085                 drm_dbg_kms(&i915->drm,
5086                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5087                             long_hpd ? "long" : "short",
5088                             dig_port->base.base.base.id,
5089                             dig_port->base.base.name);
5090                 return IRQ_HANDLED;
5091         }
5092
5093         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5094                     dig_port->base.base.base.id,
5095                     dig_port->base.base.name,
5096                     long_hpd ? "long" : "short");
5097
5098         if (long_hpd) {
5099                 intel_dp->reset_link_params = true;
5100                 return IRQ_NONE;
5101         }
5102
5103         if (intel_dp->is_mst) {
5104                 if (!intel_dp_check_mst_status(intel_dp))
5105                         return IRQ_NONE;
5106         } else if (!intel_dp_short_pulse(intel_dp)) {
5107                 return IRQ_NONE;
5108         }
5109
5110         return IRQ_HANDLED;
5111 }
5112
5113 /* check the VBT to see whether the eDP is on another port */
5114 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5115 {
5116         /*
5117          * eDP not supported on g4x. so bail out early just
5118          * for a bit extra safety in case the VBT is bonkers.
5119          */
5120         if (DISPLAY_VER(dev_priv) < 5)
5121                 return false;
5122
5123         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5124                 return true;
5125
5126         return intel_bios_is_port_edp(dev_priv, port);
5127 }
5128
5129 static bool
5130 has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
5131 {
5132         if (intel_bios_is_lspcon_present(i915, port))
5133                 return false;
5134
5135         if (DISPLAY_VER(i915) >= 11)
5136                 return true;
5137
5138         if (port == PORT_A)
5139                 return false;
5140
5141         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5142             DISPLAY_VER(i915) >= 9)
5143                 return true;
5144
5145         return false;
5146 }
5147
5148 static void
5149 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5150 {
5151         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5152         enum port port = dp_to_dig_port(intel_dp)->base.port;
5153
5154         if (!intel_dp_is_edp(intel_dp))
5155                 drm_connector_attach_dp_subconnector_property(connector);
5156
5157         if (!IS_G4X(dev_priv) && port != PORT_A)
5158                 intel_attach_force_audio_property(connector);
5159
5160         intel_attach_broadcast_rgb_property(connector);
5161         if (HAS_GMCH(dev_priv))
5162                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5163         else if (DISPLAY_VER(dev_priv) >= 5)
5164                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5165
5166         /* Register HDMI colorspace for case of lspcon */
5167         if (intel_bios_is_lspcon_present(dev_priv, port)) {
5168                 drm_connector_attach_content_type_property(connector);
5169                 intel_attach_hdmi_colorspace_property(connector);
5170         } else {
5171                 intel_attach_dp_colorspace_property(connector);
5172         }
5173
5174         if (has_gamut_metadata_dip(dev_priv, port))
5175                 drm_connector_attach_hdr_output_metadata_property(connector);
5176
5177         if (intel_dp_is_edp(intel_dp)) {
5178                 u32 allowed_scalers;
5179
5180                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5181                 if (!HAS_GMCH(dev_priv))
5182                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5183
5184                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5185
5186                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5187
5188         }
5189
5190         if (HAS_VRR(dev_priv))
5191                 drm_connector_attach_vrr_capable_property(connector);
5192 }
5193
5194 static void
5195 intel_edp_add_properties(struct intel_dp *intel_dp)
5196 {
5197         struct intel_connector *connector = intel_dp->attached_connector;
5198         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5199         const struct drm_display_mode *fixed_mode =
5200                 intel_panel_preferred_fixed_mode(connector);
5201
5202         if (!fixed_mode)
5203                 return;
5204
5205         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5206                                                        i915->display.vbt.orientation,
5207                                                        fixed_mode->hdisplay,
5208                                                        fixed_mode->vdisplay);
5209 }
5210
5211 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5212                                      struct intel_connector *intel_connector)
5213 {
5214         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5215         struct drm_device *dev = &dev_priv->drm;
5216         struct drm_connector *connector = &intel_connector->base;
5217         struct drm_display_mode *fixed_mode;
5218         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5219         bool has_dpcd;
5220         enum pipe pipe = INVALID_PIPE;
5221         struct edid *edid;
5222
5223         if (!intel_dp_is_edp(intel_dp))
5224                 return true;
5225
5226         /*
5227          * On IBX/CPT we may get here with LVDS already registered. Since the
5228          * driver uses the only internal power sequencer available for both
5229          * eDP and LVDS bail out early in this case to prevent interfering
5230          * with an already powered-on LVDS power sequencer.
5231          */
5232         if (intel_get_lvds_encoder(dev_priv)) {
5233                 drm_WARN_ON(dev,
5234                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5235                 drm_info(&dev_priv->drm,
5236                          "LVDS was detected, not registering eDP\n");
5237
5238                 return false;
5239         }
5240
5241         intel_pps_init(intel_dp);
5242
5243         /* Cache DPCD and EDID for edp. */
5244         has_dpcd = intel_edp_init_dpcd(intel_dp);
5245
5246         if (!has_dpcd) {
5247                 /* if this fails, presume the device is a ghost */
5248                 drm_info(&dev_priv->drm,
5249                          "failed to retrieve link info, disabling eDP\n");
5250                 goto out_vdd_off;
5251         }
5252
5253         mutex_lock(&dev->mode_config.mutex);
5254         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5255         if (!edid) {
5256                 /* Fallback to EDID from ACPI OpRegion, if any */
5257                 edid = intel_opregion_get_edid(intel_connector);
5258                 if (edid)
5259                         drm_dbg_kms(&dev_priv->drm,
5260                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5261                                     connector->base.id, connector->name);
5262         }
5263         if (edid) {
5264                 if (drm_add_edid_modes(connector, edid)) {
5265                         drm_connector_update_edid_property(connector, edid);
5266                 } else {
5267                         kfree(edid);
5268                         edid = ERR_PTR(-EINVAL);
5269                 }
5270         } else {
5271                 edid = ERR_PTR(-ENOENT);
5272         }
5273         intel_connector->edid = edid;
5274
5275         intel_bios_init_panel(dev_priv, &intel_connector->panel,
5276                               encoder->devdata, IS_ERR(edid) ? NULL : edid);
5277
5278         intel_panel_add_edid_fixed_modes(intel_connector,
5279                                          intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
5280                                          intel_vrr_is_capable(intel_connector));
5281
5282         /* MSO requires information from the EDID */
5283         intel_edp_mso_init(intel_dp);
5284
5285         /* multiply the mode clock and horizontal timings for MSO */
5286         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5287                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5288
5289         /* fallback to VBT if available for eDP */
5290         if (!intel_panel_preferred_fixed_mode(intel_connector))
5291                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5292
5293         mutex_unlock(&dev->mode_config.mutex);
5294
5295         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5296                 /*
5297                  * Figure out the current pipe for the initial backlight setup.
5298                  * If the current pipe isn't valid, try the PPS pipe, and if that
5299                  * fails just assume pipe A.
5300                  */
5301                 pipe = vlv_active_pipe(intel_dp);
5302
5303                 if (pipe != PIPE_A && pipe != PIPE_B)
5304                         pipe = intel_dp->pps.pps_pipe;
5305
5306                 if (pipe != PIPE_A && pipe != PIPE_B)
5307                         pipe = PIPE_A;
5308
5309                 drm_dbg_kms(&dev_priv->drm,
5310                             "using pipe %c for initial backlight setup\n",
5311                             pipe_name(pipe));
5312         }
5313
5314         intel_panel_init(intel_connector);
5315
5316         intel_backlight_setup(intel_connector, pipe);
5317
5318         intel_edp_add_properties(intel_dp);
5319
5320         intel_pps_init_late(intel_dp);
5321
5322         return true;
5323
5324 out_vdd_off:
5325         intel_pps_vdd_off_sync(intel_dp);
5326
5327         return false;
5328 }
5329
5330 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5331 {
5332         struct intel_connector *intel_connector;
5333         struct drm_connector *connector;
5334
5335         intel_connector = container_of(work, typeof(*intel_connector),
5336                                        modeset_retry_work);
5337         connector = &intel_connector->base;
5338         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5339                     connector->name);
5340
5341         /* Grab the locks before changing connector property*/
5342         mutex_lock(&connector->dev->mode_config.mutex);
5343         /* Set connector link status to BAD and send a Uevent to notify
5344          * userspace to do a modeset.
5345          */
5346         drm_connector_set_link_status_property(connector,
5347                                                DRM_MODE_LINK_STATUS_BAD);
5348         mutex_unlock(&connector->dev->mode_config.mutex);
5349         /* Send Hotplug uevent so userspace can reprobe */
5350         drm_kms_helper_connector_hotplug_event(connector);
5351 }
5352
5353 bool
5354 intel_dp_init_connector(struct intel_digital_port *dig_port,
5355                         struct intel_connector *intel_connector)
5356 {
5357         struct drm_connector *connector = &intel_connector->base;
5358         struct intel_dp *intel_dp = &dig_port->dp;
5359         struct intel_encoder *intel_encoder = &dig_port->base;
5360         struct drm_device *dev = intel_encoder->base.dev;
5361         struct drm_i915_private *dev_priv = to_i915(dev);
5362         enum port port = intel_encoder->port;
5363         enum phy phy = intel_port_to_phy(dev_priv, port);
5364         int type;
5365
5366         /* Initialize the work for modeset in case of link train failure */
5367         INIT_WORK(&intel_connector->modeset_retry_work,
5368                   intel_dp_modeset_retry_work_fn);
5369
5370         if (drm_WARN(dev, dig_port->max_lanes < 1,
5371                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5372                      dig_port->max_lanes, intel_encoder->base.base.id,
5373                      intel_encoder->base.name))
5374                 return false;
5375
5376         intel_dp->reset_link_params = true;
5377         intel_dp->pps.pps_pipe = INVALID_PIPE;
5378         intel_dp->pps.active_pipe = INVALID_PIPE;
5379
5380         /* Preserve the current hw state. */
5381         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5382         intel_dp->attached_connector = intel_connector;
5383
5384         if (intel_dp_is_port_edp(dev_priv, port)) {
5385                 /*
5386                  * Currently we don't support eDP on TypeC ports, although in
5387                  * theory it could work on TypeC legacy ports.
5388                  */
5389                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5390                 type = DRM_MODE_CONNECTOR_eDP;
5391                 intel_encoder->type = INTEL_OUTPUT_EDP;
5392
5393                 /* eDP only on port B and/or C on vlv/chv */
5394                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5395                                       IS_CHERRYVIEW(dev_priv)) &&
5396                                 port != PORT_B && port != PORT_C))
5397                         return false;
5398         } else {
5399                 type = DRM_MODE_CONNECTOR_DisplayPort;
5400         }
5401
5402         intel_dp_set_default_sink_rates(intel_dp);
5403         intel_dp_set_default_max_sink_lane_count(intel_dp);
5404
5405         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5406                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5407
5408         drm_dbg_kms(&dev_priv->drm,
5409                     "Adding %s connector on [ENCODER:%d:%s]\n",
5410                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5411                     intel_encoder->base.base.id, intel_encoder->base.name);
5412
5413         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5414         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5415
5416         if (!HAS_GMCH(dev_priv))
5417                 connector->interlace_allowed = true;
5418         connector->doublescan_allowed = 0;
5419
5420         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5421
5422         intel_dp_aux_init(intel_dp);
5423
5424         intel_connector_attach_encoder(intel_connector, intel_encoder);
5425
5426         if (HAS_DDI(dev_priv))
5427                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5428         else
5429                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5430
5431         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5432                 intel_dp_aux_fini(intel_dp);
5433                 goto fail;
5434         }
5435
5436         intel_dp_set_source_rates(intel_dp);
5437         intel_dp_set_common_rates(intel_dp);
5438         intel_dp_reset_max_link_params(intel_dp);
5439
5440         /* init MST on ports that can support it */
5441         intel_dp_mst_encoder_init(dig_port,
5442                                   intel_connector->base.base.id);
5443
5444         intel_dp_add_properties(intel_dp, connector);
5445
5446         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5447                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5448                 if (ret)
5449                         drm_dbg_kms(&dev_priv->drm,
5450                                     "HDCP init failed, skipping.\n");
5451         }
5452
5453         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5454          * 0xd.  Failure to do so will result in spurious interrupts being
5455          * generated on the port when a cable is not attached.
5456          */
5457         if (IS_G45(dev_priv)) {
5458                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5459                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5460                                (temp & ~0xf) | 0xd);
5461         }
5462
5463         intel_dp->frl.is_trained = false;
5464         intel_dp->frl.trained_rate_gbps = 0;
5465
5466         intel_psr_init(intel_dp);
5467
5468         return true;
5469
5470 fail:
5471         drm_connector_cleanup(connector);
5472
5473         return false;
5474 }
5475
5476 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5477 {
5478         struct intel_encoder *encoder;
5479
5480         if (!HAS_DISPLAY(dev_priv))
5481                 return;
5482
5483         for_each_intel_encoder(&dev_priv->drm, encoder) {
5484                 struct intel_dp *intel_dp;
5485
5486                 if (encoder->type != INTEL_OUTPUT_DDI)
5487                         continue;
5488
5489                 intel_dp = enc_to_intel_dp(encoder);
5490
5491                 if (!intel_dp_mst_source_support(intel_dp))
5492                         continue;
5493
5494                 if (intel_dp->is_mst)
5495                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5496         }
5497 }
5498
5499 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5500 {
5501         struct intel_encoder *encoder;
5502
5503         if (!HAS_DISPLAY(dev_priv))
5504                 return;
5505
5506         for_each_intel_encoder(&dev_priv->drm, encoder) {
5507                 struct intel_dp *intel_dp;
5508                 int ret;
5509
5510                 if (encoder->type != INTEL_OUTPUT_DDI)
5511                         continue;
5512
5513                 intel_dp = enc_to_intel_dp(encoder);
5514
5515                 if (!intel_dp_mst_source_support(intel_dp))
5516                         continue;
5517
5518                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5519                                                      true);
5520                 if (ret) {
5521                         intel_dp->is_mst = false;
5522                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5523                                                         false);
5524                 }
5525         }
5526 }