2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
35 #include <asm/byteorder.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include <drm/drm_probe_helper.h>
44 #include "i915_debugfs.h"
46 #include "i915_trace.h"
47 #include "intel_atomic.h"
48 #include "intel_audio.h"
49 #include "intel_connector.h"
50 #include "intel_ddi.h"
51 #include "intel_display_debugfs.h"
52 #include "intel_display_types.h"
54 #include "intel_dp_link_training.h"
55 #include "intel_dp_mst.h"
56 #include "intel_dpio_phy.h"
57 #include "intel_fifo_underrun.h"
58 #include "intel_hdcp.h"
59 #include "intel_hdmi.h"
60 #include "intel_hotplug.h"
61 #include "intel_lspcon.h"
62 #include "intel_lvds.h"
63 #include "intel_panel.h"
64 #include "intel_psr.h"
65 #include "intel_sideband.h"
67 #include "intel_vdsc.h"
69 #define DP_DPRX_ESI_LEN 14
71 /* DP DSC throughput values used for slice count calculations KPixels/s */
72 #define DP_DSC_PEAK_PIXEL_RATE 2720000
73 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
74 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
77 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
79 /* Compliance test status bits */
80 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
81 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
82 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
83 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
90 static const struct dp_link_dpll g4x_dpll[] = {
92 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
94 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
97 static const struct dp_link_dpll pch_dpll[] = {
99 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
101 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
104 static const struct dp_link_dpll vlv_dpll[] = {
106 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
108 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
112 * CHV supports eDP 1.4 that have more link rates.
113 * Below only provides the fixed rate but exclude variable rate.
115 static const struct dp_link_dpll chv_dpll[] = {
117 * CHV requires to program fractional division for m2.
118 * m2 is stored in fixed point format using formula below
119 * (m2_int << 22) | m2_fraction
121 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
122 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
123 { 270000, /* m2_int = 27, m2_fraction = 0 */
124 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
127 /* Constants for DP DSC configurations */
128 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
130 /* With Single pipe configuration, HW is capable of supporting maximum
131 * of 4 slices per line.
133 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
136 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
137 * @intel_dp: DP struct
139 * If a CPU or PCH DP output is attached to an eDP panel, this function
140 * will return true, and false otherwise.
142 bool intel_dp_is_edp(struct intel_dp *intel_dp)
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
146 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
149 static void intel_dp_link_down(struct intel_encoder *encoder,
150 const struct intel_crtc_state *old_crtc_state);
151 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
152 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
153 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
154 const struct intel_crtc_state *crtc_state);
155 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
157 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
159 /* update sink rates from dpcd */
160 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
162 static const int dp_rates[] = {
163 162000, 270000, 540000, 810000
167 if (drm_dp_has_quirk(&intel_dp->desc, 0,
168 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
169 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
170 static const int quirk_rates[] = { 162000, 270000, 324000 };
172 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
173 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
178 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
180 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
181 if (dp_rates[i] > max_rate)
183 intel_dp->sink_rates[i] = dp_rates[i];
186 intel_dp->num_sink_rates = i;
189 /* Get length of rates array potentially limited by max_rate. */
190 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
194 /* Limit results by potentially reduced max rate */
195 for (i = 0; i < len; i++) {
196 if (rates[len - i - 1] <= max_rate)
203 /* Get length of common rates array potentially limited by max_rate. */
204 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
207 return intel_dp_rate_limit_len(intel_dp->common_rates,
208 intel_dp->num_common_rates, max_rate);
211 /* Theoretical max between source and sink */
212 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
214 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
217 /* Theoretical max between source and sink */
218 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
221 int source_max = intel_dig_port->max_lanes;
222 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
223 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
225 return min3(source_max, sink_max, fia_max);
228 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
230 return intel_dp->max_link_lane_count;
234 intel_dp_link_required(int pixel_clock, int bpp)
236 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
237 return DIV_ROUND_UP(pixel_clock * bpp, 8);
241 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
243 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
244 * link rate that is generally expressed in Gbps. Since, 8 bits of data
245 * is transmitted every LS_Clk per lane, there is no need to account for
246 * the channel encoding that is done in the PHY layer here.
249 return max_link_clock * max_lanes;
253 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
256 struct intel_encoder *encoder = &intel_dig_port->base;
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
258 int max_dotclk = dev_priv->max_dotclk_freq;
261 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
263 if (type != DP_DS_PORT_TYPE_VGA)
266 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
267 intel_dp->downstream_ports);
269 if (ds_max_dotclk != 0)
270 max_dotclk = min(max_dotclk, ds_max_dotclk);
275 static int cnl_max_source_rate(struct intel_dp *intel_dp)
277 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
278 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
279 enum port port = dig_port->base.port;
281 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
283 /* Low voltage SKUs are limited to max of 5.4G */
284 if (voltage == VOLTAGE_INFO_0_85V)
287 /* For this SKU 8.1G is supported in all ports */
288 if (IS_CNL_WITH_PORT_F(dev_priv))
291 /* For other SKUs, max rate on ports A and D is 5.4G */
292 if (port == PORT_A || port == PORT_D)
298 static int icl_max_source_rate(struct intel_dp *intel_dp)
300 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
301 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
302 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
304 if (intel_phy_is_combo(dev_priv, phy) &&
305 !IS_ELKHARTLAKE(dev_priv) &&
306 !intel_dp_is_edp(intel_dp))
313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
315 /* The values must be in increasing order */
316 static const int cnl_rates[] = {
317 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
319 static const int bxt_rates[] = {
320 162000, 216000, 243000, 270000, 324000, 432000, 540000
322 static const int skl_rates[] = {
323 162000, 216000, 270000, 324000, 432000, 540000
325 static const int hsw_rates[] = {
326 162000, 270000, 540000
328 static const int g4x_rates[] = {
331 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
332 struct intel_encoder *encoder = &dig_port->base;
333 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
334 const int *source_rates;
335 int size, max_rate = 0, vbt_max_rate;
337 /* This should only be done once */
338 drm_WARN_ON(&dev_priv->drm,
339 intel_dp->source_rates || intel_dp->num_source_rates);
341 if (INTEL_GEN(dev_priv) >= 10) {
342 source_rates = cnl_rates;
343 size = ARRAY_SIZE(cnl_rates);
344 if (IS_GEN(dev_priv, 10))
345 max_rate = cnl_max_source_rate(intel_dp);
347 max_rate = icl_max_source_rate(intel_dp);
348 } else if (IS_GEN9_LP(dev_priv)) {
349 source_rates = bxt_rates;
350 size = ARRAY_SIZE(bxt_rates);
351 } else if (IS_GEN9_BC(dev_priv)) {
352 source_rates = skl_rates;
353 size = ARRAY_SIZE(skl_rates);
354 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
355 IS_BROADWELL(dev_priv)) {
356 source_rates = hsw_rates;
357 size = ARRAY_SIZE(hsw_rates);
359 source_rates = g4x_rates;
360 size = ARRAY_SIZE(g4x_rates);
363 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
364 if (max_rate && vbt_max_rate)
365 max_rate = min(max_rate, vbt_max_rate);
366 else if (vbt_max_rate)
367 max_rate = vbt_max_rate;
370 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
372 intel_dp->source_rates = source_rates;
373 intel_dp->num_source_rates = size;
376 static int intersect_rates(const int *source_rates, int source_len,
377 const int *sink_rates, int sink_len,
380 int i = 0, j = 0, k = 0;
382 while (i < source_len && j < sink_len) {
383 if (source_rates[i] == sink_rates[j]) {
384 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
386 common_rates[k] = source_rates[i];
390 } else if (source_rates[i] < sink_rates[j]) {
399 /* return index of rate in rates array, or -1 if not found */
400 static int intel_dp_rate_index(const int *rates, int len, int rate)
404 for (i = 0; i < len; i++)
405 if (rate == rates[i])
411 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
413 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
415 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
416 intel_dp->num_source_rates,
417 intel_dp->sink_rates,
418 intel_dp->num_sink_rates,
419 intel_dp->common_rates);
421 /* Paranoia, there should always be something in common. */
422 if (WARN_ON(intel_dp->num_common_rates == 0)) {
423 intel_dp->common_rates[0] = 162000;
424 intel_dp->num_common_rates = 1;
428 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
432 * FIXME: we need to synchronize the current link parameters with
433 * hardware readout. Currently fast link training doesn't work on
436 if (link_rate == 0 ||
437 link_rate > intel_dp->max_link_rate)
440 if (lane_count == 0 ||
441 lane_count > intel_dp_max_lane_count(intel_dp))
447 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
451 const struct drm_display_mode *fixed_mode =
452 intel_dp->attached_connector->panel.fixed_mode;
453 int mode_rate, max_rate;
455 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
456 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
457 if (mode_rate > max_rate)
463 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
464 int link_rate, u8 lane_count)
466 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
469 index = intel_dp_rate_index(intel_dp->common_rates,
470 intel_dp->num_common_rates,
473 if (intel_dp_is_edp(intel_dp) &&
474 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
475 intel_dp->common_rates[index - 1],
477 drm_dbg_kms(&i915->drm,
478 "Retrying Link training for eDP with same parameters\n");
481 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
482 intel_dp->max_link_lane_count = lane_count;
483 } else if (lane_count > 1) {
484 if (intel_dp_is_edp(intel_dp) &&
485 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
486 intel_dp_max_common_rate(intel_dp),
488 drm_dbg_kms(&i915->drm,
489 "Retrying Link training for eDP with same parameters\n");
492 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
493 intel_dp->max_link_lane_count = lane_count >> 1;
495 drm_err(&i915->drm, "Link Training Unsuccessful\n");
502 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
504 return div_u64(mul_u32_u32(mode_clock, 1000000U),
505 DP_DSC_FEC_OVERHEAD_FACTOR);
509 small_joiner_ram_size_bits(struct drm_i915_private *i915)
511 if (INTEL_GEN(i915) >= 11)
517 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
518 u32 link_clock, u32 lane_count,
519 u32 mode_clock, u32 mode_hdisplay)
521 u32 bits_per_pixel, max_bpp_small_joiner_ram;
525 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
526 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
527 * for SST -> TimeSlotsPerMTP is 1,
528 * for MST -> TimeSlotsPerMTP has to be calculated
530 bits_per_pixel = (link_clock * lane_count * 8) /
531 intel_dp_mode_to_fec_clock(mode_clock);
532 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
534 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
535 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
537 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
538 max_bpp_small_joiner_ram);
541 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
542 * check, output bpp from small joiner RAM check)
544 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
546 /* Error out if the max bpp is less than smallest allowed valid bpp */
547 if (bits_per_pixel < valid_dsc_bpp[0]) {
548 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
549 bits_per_pixel, valid_dsc_bpp[0]);
553 /* Find the nearest match in the array of known BPPs from VESA */
554 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
555 if (bits_per_pixel < valid_dsc_bpp[i + 1])
558 bits_per_pixel = valid_dsc_bpp[i];
561 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
562 * fractional part is 0
564 return bits_per_pixel << 4;
567 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
568 int mode_clock, int mode_hdisplay)
570 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
571 u8 min_slice_count, i;
574 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
575 min_slice_count = DIV_ROUND_UP(mode_clock,
576 DP_DSC_MAX_ENC_THROUGHPUT_0);
578 min_slice_count = DIV_ROUND_UP(mode_clock,
579 DP_DSC_MAX_ENC_THROUGHPUT_1);
581 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
582 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
583 drm_dbg_kms(&i915->drm,
584 "Unsupported slice width %d by DP DSC Sink device\n",
588 /* Also take into account max slice width */
589 min_slice_count = min_t(u8, min_slice_count,
590 DIV_ROUND_UP(mode_hdisplay,
593 /* Find the closest match to the valid slice count values */
594 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
595 if (valid_dsc_slicecount[i] >
596 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
599 if (min_slice_count <= valid_dsc_slicecount[i])
600 return valid_dsc_slicecount[i];
603 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
608 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
612 * Older platforms don't like hdisplay==4096 with DP.
614 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
615 * and frame counter increment), but we don't get vblank interrupts,
616 * and the pipe underruns immediately. The link also doesn't seem
617 * to get trained properly.
619 * On CHV the vblank interrupts don't seem to disappear but
620 * otherwise the symptoms are similar.
622 * TODO: confirm the behaviour on HSW+
624 return hdisplay == 4096 && !HAS_DDI(dev_priv);
627 static enum drm_mode_status
628 intel_dp_mode_valid(struct drm_connector *connector,
629 struct drm_display_mode *mode)
631 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
632 struct intel_connector *intel_connector = to_intel_connector(connector);
633 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
634 struct drm_i915_private *dev_priv = to_i915(connector->dev);
635 int target_clock = mode->clock;
636 int max_rate, mode_rate, max_lanes, max_link_clock;
638 u16 dsc_max_output_bpp = 0;
639 u8 dsc_slice_count = 0;
641 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
642 return MODE_NO_DBLESCAN;
644 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
646 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
647 if (mode->hdisplay > fixed_mode->hdisplay)
650 if (mode->vdisplay > fixed_mode->vdisplay)
653 target_clock = fixed_mode->clock;
656 max_link_clock = intel_dp_max_link_rate(intel_dp);
657 max_lanes = intel_dp_max_lane_count(intel_dp);
659 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
660 mode_rate = intel_dp_link_required(target_clock, 18);
662 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
663 return MODE_H_ILLEGAL;
666 * Output bpp is stored in 6.4 format so right shift by 4 to get the
667 * integer value since we support only integer values of bpp.
669 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
670 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
671 if (intel_dp_is_edp(intel_dp)) {
673 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
675 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
677 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
679 intel_dp_dsc_get_output_bpp(dev_priv,
683 mode->hdisplay) >> 4;
685 intel_dp_dsc_get_slice_count(intel_dp,
691 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
692 target_clock > max_dotclk)
693 return MODE_CLOCK_HIGH;
695 if (mode->clock < 10000)
696 return MODE_CLOCK_LOW;
698 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
699 return MODE_H_ILLEGAL;
701 return intel_mode_valid_max_plane_size(dev_priv, mode);
704 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
711 for (i = 0; i < src_bytes; i++)
712 v |= ((u32)src[i]) << ((3 - i) * 8);
716 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
721 for (i = 0; i < dst_bytes; i++)
722 dst[i] = src >> ((3-i) * 8);
726 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
728 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
729 bool force_disable_vdd);
731 intel_dp_pps_init(struct intel_dp *intel_dp);
733 static intel_wakeref_t
734 pps_lock(struct intel_dp *intel_dp)
736 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
737 intel_wakeref_t wakeref;
740 * See intel_power_sequencer_reset() why we need
741 * a power domain reference here.
743 wakeref = intel_display_power_get(dev_priv,
744 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
746 mutex_lock(&dev_priv->pps_mutex);
751 static intel_wakeref_t
752 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
754 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
756 mutex_unlock(&dev_priv->pps_mutex);
757 intel_display_power_put(dev_priv,
758 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
763 #define with_pps_lock(dp, wf) \
764 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
767 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
769 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
770 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
771 enum pipe pipe = intel_dp->pps_pipe;
772 bool pll_enabled, release_cl_override = false;
773 enum dpio_phy phy = DPIO_PHY(pipe);
774 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
777 if (drm_WARN(&dev_priv->drm,
778 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
779 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
780 pipe_name(pipe), intel_dig_port->base.base.base.id,
781 intel_dig_port->base.base.name))
784 drm_dbg_kms(&dev_priv->drm,
785 "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
786 pipe_name(pipe), intel_dig_port->base.base.base.id,
787 intel_dig_port->base.base.name);
789 /* Preserve the BIOS-computed detected bit. This is
790 * supposed to be read-only.
792 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
793 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
794 DP |= DP_PORT_WIDTH(1);
795 DP |= DP_LINK_TRAIN_PAT_1;
797 if (IS_CHERRYVIEW(dev_priv))
798 DP |= DP_PIPE_SEL_CHV(pipe);
800 DP |= DP_PIPE_SEL(pipe);
802 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
805 * The DPLL for the pipe must be enabled for this to work.
806 * So enable temporarily it if it's not already enabled.
809 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
810 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
812 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
813 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
814 drm_err(&dev_priv->drm,
815 "Failed to force on pll for pipe %c!\n",
822 * Similar magic as in intel_dp_enable_port().
823 * We _must_ do this port enable + disable trick
824 * to make this power sequencer lock onto the port.
825 * Otherwise even VDD force bit won't work.
827 intel_de_write(dev_priv, intel_dp->output_reg, DP);
828 intel_de_posting_read(dev_priv, intel_dp->output_reg);
830 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
831 intel_de_posting_read(dev_priv, intel_dp->output_reg);
833 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
834 intel_de_posting_read(dev_priv, intel_dp->output_reg);
837 vlv_force_pll_off(dev_priv, pipe);
839 if (release_cl_override)
840 chv_phy_powergate_ch(dev_priv, phy, ch, false);
844 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
846 struct intel_encoder *encoder;
847 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
850 * We don't have power sequencer currently.
851 * Pick one that's not used by other ports.
853 for_each_intel_dp(&dev_priv->drm, encoder) {
854 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
856 if (encoder->type == INTEL_OUTPUT_EDP) {
857 drm_WARN_ON(&dev_priv->drm,
858 intel_dp->active_pipe != INVALID_PIPE &&
859 intel_dp->active_pipe !=
862 if (intel_dp->pps_pipe != INVALID_PIPE)
863 pipes &= ~(1 << intel_dp->pps_pipe);
865 drm_WARN_ON(&dev_priv->drm,
866 intel_dp->pps_pipe != INVALID_PIPE);
868 if (intel_dp->active_pipe != INVALID_PIPE)
869 pipes &= ~(1 << intel_dp->active_pipe);
876 return ffs(pipes) - 1;
880 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
882 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
886 lockdep_assert_held(&dev_priv->pps_mutex);
888 /* We should never land here with regular DP ports */
889 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
891 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
892 intel_dp->active_pipe != intel_dp->pps_pipe);
894 if (intel_dp->pps_pipe != INVALID_PIPE)
895 return intel_dp->pps_pipe;
897 pipe = vlv_find_free_pps(dev_priv);
900 * Didn't find one. This should not happen since there
901 * are two power sequencers and up to two eDP ports.
903 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
906 vlv_steal_power_sequencer(dev_priv, pipe);
907 intel_dp->pps_pipe = pipe;
909 drm_dbg_kms(&dev_priv->drm,
910 "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
911 pipe_name(intel_dp->pps_pipe),
912 intel_dig_port->base.base.base.id,
913 intel_dig_port->base.base.name);
915 /* init power sequencer on this pipe and port */
916 intel_dp_init_panel_power_sequencer(intel_dp);
917 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
920 * Even vdd force doesn't work until we've made
921 * the power sequencer lock in on the port.
923 vlv_power_sequencer_kick(intel_dp);
925 return intel_dp->pps_pipe;
929 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
931 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
932 int backlight_controller = dev_priv->vbt.backlight.controller;
934 lockdep_assert_held(&dev_priv->pps_mutex);
936 /* We should never land here with regular DP ports */
937 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
939 if (!intel_dp->pps_reset)
940 return backlight_controller;
942 intel_dp->pps_reset = false;
945 * Only the HW needs to be reprogrammed, the SW state is fixed and
946 * has been setup during connector init.
948 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
950 return backlight_controller;
953 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
956 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
959 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
962 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
965 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
968 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
975 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
977 vlv_pipe_check pipe_check)
981 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
982 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
983 PANEL_PORT_SELECT_MASK;
985 if (port_sel != PANEL_PORT_SELECT_VLV(port))
988 if (!pipe_check(dev_priv, pipe))
998 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1000 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1001 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1002 enum port port = intel_dig_port->base.port;
1004 lockdep_assert_held(&dev_priv->pps_mutex);
1006 /* try to find a pipe with this port selected */
1007 /* first pick one where the panel is on */
1008 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1009 vlv_pipe_has_pp_on);
1010 /* didn't find one? pick one where vdd is on */
1011 if (intel_dp->pps_pipe == INVALID_PIPE)
1012 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1013 vlv_pipe_has_vdd_on);
1014 /* didn't find one? pick one with just the correct port */
1015 if (intel_dp->pps_pipe == INVALID_PIPE)
1016 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1019 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1020 if (intel_dp->pps_pipe == INVALID_PIPE) {
1021 drm_dbg_kms(&dev_priv->drm,
1022 "no initial power sequencer for [ENCODER:%d:%s]\n",
1023 intel_dig_port->base.base.base.id,
1024 intel_dig_port->base.base.name);
1028 drm_dbg_kms(&dev_priv->drm,
1029 "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1030 intel_dig_port->base.base.base.id,
1031 intel_dig_port->base.base.name,
1032 pipe_name(intel_dp->pps_pipe));
1034 intel_dp_init_panel_power_sequencer(intel_dp);
1035 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1038 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1040 struct intel_encoder *encoder;
1042 if (drm_WARN_ON(&dev_priv->drm,
1043 !(IS_VALLEYVIEW(dev_priv) ||
1044 IS_CHERRYVIEW(dev_priv) ||
1045 IS_GEN9_LP(dev_priv))))
1049 * We can't grab pps_mutex here due to deadlock with power_domain
1050 * mutex when power_domain functions are called while holding pps_mutex.
1051 * That also means that in order to use pps_pipe the code needs to
1052 * hold both a power domain reference and pps_mutex, and the power domain
1053 * reference get/put must be done while _not_ holding pps_mutex.
1054 * pps_{lock,unlock}() do these steps in the correct order, so one
1055 * should use them always.
1058 for_each_intel_dp(&dev_priv->drm, encoder) {
1059 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1061 drm_WARN_ON(&dev_priv->drm,
1062 intel_dp->active_pipe != INVALID_PIPE);
1064 if (encoder->type != INTEL_OUTPUT_EDP)
1067 if (IS_GEN9_LP(dev_priv))
1068 intel_dp->pps_reset = true;
1070 intel_dp->pps_pipe = INVALID_PIPE;
1074 struct pps_registers {
1082 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1083 struct pps_registers *regs)
1085 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1088 memset(regs, 0, sizeof(*regs));
1090 if (IS_GEN9_LP(dev_priv))
1091 pps_idx = bxt_power_sequencer_idx(intel_dp);
1092 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1093 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1095 regs->pp_ctrl = PP_CONTROL(pps_idx);
1096 regs->pp_stat = PP_STATUS(pps_idx);
1097 regs->pp_on = PP_ON_DELAYS(pps_idx);
1098 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1100 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1101 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1102 regs->pp_div = INVALID_MMIO_REG;
1104 regs->pp_div = PP_DIVISOR(pps_idx);
1108 _pp_ctrl_reg(struct intel_dp *intel_dp)
1110 struct pps_registers regs;
1112 intel_pps_get_registers(intel_dp, ®s);
1114 return regs.pp_ctrl;
1118 _pp_stat_reg(struct intel_dp *intel_dp)
1120 struct pps_registers regs;
1122 intel_pps_get_registers(intel_dp, ®s);
1124 return regs.pp_stat;
1127 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1128 This function only applicable when panel PM state is not to be tracked */
1129 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1132 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1134 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1135 intel_wakeref_t wakeref;
1137 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1140 with_pps_lock(intel_dp, wakeref) {
1141 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1142 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1143 i915_reg_t pp_ctrl_reg, pp_div_reg;
1146 pp_ctrl_reg = PP_CONTROL(pipe);
1147 pp_div_reg = PP_DIVISOR(pipe);
1148 pp_div = intel_de_read(dev_priv, pp_div_reg);
1149 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1151 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1152 intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1153 intel_de_write(dev_priv, pp_ctrl_reg,
1155 msleep(intel_dp->panel_power_cycle_delay);
1162 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1164 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1166 lockdep_assert_held(&dev_priv->pps_mutex);
1168 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1169 intel_dp->pps_pipe == INVALID_PIPE)
1172 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1175 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1177 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1179 lockdep_assert_held(&dev_priv->pps_mutex);
1181 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1182 intel_dp->pps_pipe == INVALID_PIPE)
1185 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1189 intel_dp_check_edp(struct intel_dp *intel_dp)
1191 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1193 if (!intel_dp_is_edp(intel_dp))
1196 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1197 drm_WARN(&dev_priv->drm, 1,
1198 "eDP powered off while attempting aux channel communication.\n");
1199 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1200 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1201 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1206 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1208 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1209 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1210 const unsigned int timeout_ms = 10;
1214 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1215 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1216 msecs_to_jiffies_timeout(timeout_ms));
1218 /* just trace the final value */
1219 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1223 "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1224 intel_dp->aux.name, timeout_ms, status);
1230 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1232 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1238 * The clock divider is based off the hrawclk, and would like to run at
1239 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1241 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1244 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1246 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1247 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1254 * The clock divider is based off the cdclk or PCH rawclk, and would
1255 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1256 * divide by 2000 and use that
1258 if (dig_port->aux_ch == AUX_CH_A)
1259 freq = dev_priv->cdclk.hw.cdclk;
1261 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1262 return DIV_ROUND_CLOSEST(freq, 2000);
1265 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1267 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1268 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1270 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1271 /* Workaround for non-ULT HSW */
1279 return ilk_get_aux_clock_divider(intel_dp, index);
1282 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1285 * SKL doesn't need us to program the AUX clock divider (Hardware will
1286 * derive the clock from CDCLK automatically). We still implement the
1287 * get_aux_clock_divider vfunc to plug-in into the existing code.
1289 return index ? 0 : 1;
1292 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1294 u32 aux_clock_divider)
1296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1297 struct drm_i915_private *dev_priv =
1298 to_i915(intel_dig_port->base.base.dev);
1299 u32 precharge, timeout;
1301 if (IS_GEN(dev_priv, 6))
1306 if (IS_BROADWELL(dev_priv))
1307 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1309 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1311 return DP_AUX_CH_CTL_SEND_BUSY |
1312 DP_AUX_CH_CTL_DONE |
1313 DP_AUX_CH_CTL_INTERRUPT |
1314 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1316 DP_AUX_CH_CTL_RECEIVE_ERROR |
1317 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1318 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1319 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1322 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1327 struct drm_i915_private *i915 =
1328 to_i915(intel_dig_port->base.base.dev);
1329 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1332 ret = DP_AUX_CH_CTL_SEND_BUSY |
1333 DP_AUX_CH_CTL_DONE |
1334 DP_AUX_CH_CTL_INTERRUPT |
1335 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1336 DP_AUX_CH_CTL_TIME_OUT_MAX |
1337 DP_AUX_CH_CTL_RECEIVE_ERROR |
1338 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1339 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1340 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1342 if (intel_phy_is_tc(i915, phy) &&
1343 intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1344 ret |= DP_AUX_CH_CTL_TBT_IO;
1350 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1351 const u8 *send, int send_bytes,
1352 u8 *recv, int recv_size,
1353 u32 aux_send_ctl_flags)
1355 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1356 struct drm_i915_private *i915 =
1357 to_i915(intel_dig_port->base.base.dev);
1358 struct intel_uncore *uncore = &i915->uncore;
1359 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1360 bool is_tc_port = intel_phy_is_tc(i915, phy);
1361 i915_reg_t ch_ctl, ch_data[5];
1362 u32 aux_clock_divider;
1363 enum intel_display_power_domain aux_domain =
1364 intel_aux_power_domain(intel_dig_port);
1365 intel_wakeref_t aux_wakeref;
1366 intel_wakeref_t pps_wakeref;
1367 int i, ret, recv_bytes;
1372 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1373 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1374 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1377 intel_tc_port_lock(intel_dig_port);
1379 aux_wakeref = intel_display_power_get(i915, aux_domain);
1380 pps_wakeref = pps_lock(intel_dp);
1383 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1384 * In such cases we want to leave VDD enabled and it's up to upper layers
1385 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1388 vdd = edp_panel_vdd_on(intel_dp);
1390 /* dp aux is extremely sensitive to irq latency, hence request the
1391 * lowest possible wakeup latency and so prevent the cpu from going into
1392 * deep sleep states.
1394 cpu_latency_qos_update_request(&i915->pm_qos, 0);
1396 intel_dp_check_edp(intel_dp);
1398 /* Try to wait for any previous AUX channel activity */
1399 for (try = 0; try < 3; try++) {
1400 status = intel_uncore_read_notrace(uncore, ch_ctl);
1401 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1405 /* just trace the final value */
1406 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1409 const u32 status = intel_uncore_read(uncore, ch_ctl);
1411 if (status != intel_dp->aux_busy_last_status) {
1412 drm_WARN(&i915->drm, 1,
1413 "%s: not started (status 0x%08x)\n",
1414 intel_dp->aux.name, status);
1415 intel_dp->aux_busy_last_status = status;
1422 /* Only 5 data registers! */
1423 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1428 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1429 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1433 send_ctl |= aux_send_ctl_flags;
1435 /* Must try at least 3 times according to DP spec */
1436 for (try = 0; try < 5; try++) {
1437 /* Load the send data into the aux channel data registers */
1438 for (i = 0; i < send_bytes; i += 4)
1439 intel_uncore_write(uncore,
1441 intel_dp_pack_aux(send + i,
1444 /* Send the command and wait for it to complete */
1445 intel_uncore_write(uncore, ch_ctl, send_ctl);
1447 status = intel_dp_aux_wait_done(intel_dp);
1449 /* Clear done status and any errors */
1450 intel_uncore_write(uncore,
1453 DP_AUX_CH_CTL_DONE |
1454 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1455 DP_AUX_CH_CTL_RECEIVE_ERROR);
1457 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1458 * 400us delay required for errors and timeouts
1459 * Timeout errors from the HW already meet this
1460 * requirement so skip to next iteration
1462 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1465 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1466 usleep_range(400, 500);
1469 if (status & DP_AUX_CH_CTL_DONE)
1474 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1475 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1476 intel_dp->aux.name, status);
1482 /* Check for timeout or receive error.
1483 * Timeouts occur when the sink is not connected
1485 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1486 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1487 intel_dp->aux.name, status);
1492 /* Timeouts occur when the device isn't connected, so they're
1493 * "normal" -- don't fill the kernel log with these */
1494 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1495 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1496 intel_dp->aux.name, status);
1501 /* Unload any bytes sent back from the other side */
1502 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1503 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1506 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1507 * We have no idea of what happened so we return -EBUSY so
1508 * drm layer takes care for the necessary retries.
1510 if (recv_bytes == 0 || recv_bytes > 20) {
1511 drm_dbg_kms(&i915->drm,
1512 "%s: Forbidden recv_bytes = %d on aux transaction\n",
1513 intel_dp->aux.name, recv_bytes);
1518 if (recv_bytes > recv_size)
1519 recv_bytes = recv_size;
1521 for (i = 0; i < recv_bytes; i += 4)
1522 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1523 recv + i, recv_bytes - i);
1527 cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1530 edp_panel_vdd_off(intel_dp, false);
1532 pps_unlock(intel_dp, pps_wakeref);
1533 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1536 intel_tc_port_unlock(intel_dig_port);
1541 #define BARE_ADDRESS_SIZE 3
1542 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1545 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1546 const struct drm_dp_aux_msg *msg)
1548 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1549 txbuf[1] = (msg->address >> 8) & 0xff;
1550 txbuf[2] = msg->address & 0xff;
1551 txbuf[3] = msg->size - 1;
1555 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1557 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1558 u8 txbuf[20], rxbuf[20];
1559 size_t txsize, rxsize;
1562 intel_dp_aux_header(txbuf, msg);
1564 switch (msg->request & ~DP_AUX_I2C_MOT) {
1565 case DP_AUX_NATIVE_WRITE:
1566 case DP_AUX_I2C_WRITE:
1567 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1568 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1569 rxsize = 2; /* 0 or 1 data bytes */
1571 if (WARN_ON(txsize > 20))
1574 WARN_ON(!msg->buffer != !msg->size);
1577 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1579 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1582 msg->reply = rxbuf[0] >> 4;
1585 /* Number of bytes written in a short write. */
1586 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1588 /* Return payload size. */
1594 case DP_AUX_NATIVE_READ:
1595 case DP_AUX_I2C_READ:
1596 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1597 rxsize = msg->size + 1;
1599 if (WARN_ON(rxsize > 20))
1602 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1605 msg->reply = rxbuf[0] >> 4;
1607 * Assume happy day, and copy the data. The caller is
1608 * expected to check msg->reply before touching it.
1610 * Return payload size.
1613 memcpy(msg->buffer, rxbuf + 1, ret);
1626 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1628 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1629 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1630 enum aux_ch aux_ch = dig_port->aux_ch;
1636 return DP_AUX_CH_CTL(aux_ch);
1638 MISSING_CASE(aux_ch);
1639 return DP_AUX_CH_CTL(AUX_CH_B);
1643 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1645 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1646 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1647 enum aux_ch aux_ch = dig_port->aux_ch;
1653 return DP_AUX_CH_DATA(aux_ch, index);
1655 MISSING_CASE(aux_ch);
1656 return DP_AUX_CH_DATA(AUX_CH_B, index);
1660 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1662 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1663 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1664 enum aux_ch aux_ch = dig_port->aux_ch;
1668 return DP_AUX_CH_CTL(aux_ch);
1672 return PCH_DP_AUX_CH_CTL(aux_ch);
1674 MISSING_CASE(aux_ch);
1675 return DP_AUX_CH_CTL(AUX_CH_A);
1679 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1681 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1682 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1683 enum aux_ch aux_ch = dig_port->aux_ch;
1687 return DP_AUX_CH_DATA(aux_ch, index);
1691 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1693 MISSING_CASE(aux_ch);
1694 return DP_AUX_CH_DATA(AUX_CH_A, index);
1698 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1700 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1701 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1702 enum aux_ch aux_ch = dig_port->aux_ch;
1712 return DP_AUX_CH_CTL(aux_ch);
1714 MISSING_CASE(aux_ch);
1715 return DP_AUX_CH_CTL(AUX_CH_A);
1719 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1721 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1722 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1723 enum aux_ch aux_ch = dig_port->aux_ch;
1733 return DP_AUX_CH_DATA(aux_ch, index);
1735 MISSING_CASE(aux_ch);
1736 return DP_AUX_CH_DATA(AUX_CH_A, index);
1741 intel_dp_aux_fini(struct intel_dp *intel_dp)
1743 kfree(intel_dp->aux.name);
1747 intel_dp_aux_init(struct intel_dp *intel_dp)
1749 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1750 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1751 struct intel_encoder *encoder = &dig_port->base;
1753 if (INTEL_GEN(dev_priv) >= 9) {
1754 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1755 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1756 } else if (HAS_PCH_SPLIT(dev_priv)) {
1757 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1758 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1760 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1761 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1764 if (INTEL_GEN(dev_priv) >= 9)
1765 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1766 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1767 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1768 else if (HAS_PCH_SPLIT(dev_priv))
1769 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1771 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1773 if (INTEL_GEN(dev_priv) >= 9)
1774 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1776 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1778 drm_dp_aux_init(&intel_dp->aux);
1780 /* Failure to allocate our preferred name is not critical */
1781 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1782 aux_ch_name(dig_port->aux_ch),
1783 port_name(encoder->port));
1784 intel_dp->aux.transfer = intel_dp_aux_transfer;
1787 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1789 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1791 return max_rate >= 540000;
1794 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1796 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1798 return max_rate >= 810000;
1802 intel_dp_set_clock(struct intel_encoder *encoder,
1803 struct intel_crtc_state *pipe_config)
1805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1806 const struct dp_link_dpll *divisor = NULL;
1809 if (IS_G4X(dev_priv)) {
1811 count = ARRAY_SIZE(g4x_dpll);
1812 } else if (HAS_PCH_SPLIT(dev_priv)) {
1814 count = ARRAY_SIZE(pch_dpll);
1815 } else if (IS_CHERRYVIEW(dev_priv)) {
1817 count = ARRAY_SIZE(chv_dpll);
1818 } else if (IS_VALLEYVIEW(dev_priv)) {
1820 count = ARRAY_SIZE(vlv_dpll);
1823 if (divisor && count) {
1824 for (i = 0; i < count; i++) {
1825 if (pipe_config->port_clock == divisor[i].clock) {
1826 pipe_config->dpll = divisor[i].dpll;
1827 pipe_config->clock_set = true;
1834 static void snprintf_int_array(char *str, size_t len,
1835 const int *array, int nelem)
1841 for (i = 0; i < nelem; i++) {
1842 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1850 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1852 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1853 char str[128]; /* FIXME: too big for stack? */
1855 if (!drm_debug_enabled(DRM_UT_KMS))
1858 snprintf_int_array(str, sizeof(str),
1859 intel_dp->source_rates, intel_dp->num_source_rates);
1860 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1862 snprintf_int_array(str, sizeof(str),
1863 intel_dp->sink_rates, intel_dp->num_sink_rates);
1864 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1866 snprintf_int_array(str, sizeof(str),
1867 intel_dp->common_rates, intel_dp->num_common_rates);
1868 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1872 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1876 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1877 if (WARN_ON(len <= 0))
1880 return intel_dp->common_rates[len - 1];
1883 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1885 int i = intel_dp_rate_index(intel_dp->sink_rates,
1886 intel_dp->num_sink_rates, rate);
1894 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1895 u8 *link_bw, u8 *rate_select)
1897 /* eDP 1.4 rate select method. */
1898 if (intel_dp->use_rate_select) {
1901 intel_dp_rate_select(intel_dp, port_clock);
1903 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1908 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1909 const struct intel_crtc_state *pipe_config)
1911 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1913 /* On TGL, FEC is supported on all Pipes */
1914 if (INTEL_GEN(dev_priv) >= 12)
1917 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1923 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1924 const struct intel_crtc_state *pipe_config)
1926 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1927 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1930 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1931 const struct intel_crtc_state *crtc_state)
1933 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1935 if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1938 return intel_dsc_source_support(encoder, crtc_state) &&
1939 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1942 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1943 struct intel_crtc_state *pipe_config)
1945 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1946 struct intel_connector *intel_connector = intel_dp->attached_connector;
1949 bpp = pipe_config->pipe_bpp;
1950 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1953 bpp = min(bpp, 3*bpc);
1955 if (intel_dp_is_edp(intel_dp)) {
1956 /* Get bpp from vbt only for panels that dont have bpp in edid */
1957 if (intel_connector->base.display_info.bpc == 0 &&
1958 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1959 drm_dbg_kms(&dev_priv->drm,
1960 "clamping bpp for eDP panel to BIOS-provided %i\n",
1961 dev_priv->vbt.edp.bpp);
1962 bpp = dev_priv->vbt.edp.bpp;
1969 /* Adjust link config limits based on compliance test requests. */
1971 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1972 struct intel_crtc_state *pipe_config,
1973 struct link_config_limits *limits)
1975 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1977 /* For DP Compliance we override the computed bpp for the pipe */
1978 if (intel_dp->compliance.test_data.bpc != 0) {
1979 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1981 limits->min_bpp = limits->max_bpp = bpp;
1982 pipe_config->dither_force_disable = bpp == 6 * 3;
1984 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1987 /* Use values requested by Compliance Test Request */
1988 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1991 /* Validate the compliance test data since max values
1992 * might have changed due to link train fallback.
1994 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1995 intel_dp->compliance.test_lane_count)) {
1996 index = intel_dp_rate_index(intel_dp->common_rates,
1997 intel_dp->num_common_rates,
1998 intel_dp->compliance.test_link_rate);
2000 limits->min_clock = limits->max_clock = index;
2001 limits->min_lane_count = limits->max_lane_count =
2002 intel_dp->compliance.test_lane_count;
2007 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2010 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2011 * format of the number of bytes per pixel will be half the number
2012 * of bytes of RGB pixel.
2014 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2020 /* Optimize link config in order: max bpp, min clock, min lanes */
2022 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2023 struct intel_crtc_state *pipe_config,
2024 const struct link_config_limits *limits)
2026 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2027 int bpp, clock, lane_count;
2028 int mode_rate, link_clock, link_avail;
2030 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2031 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2033 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2036 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2037 for (lane_count = limits->min_lane_count;
2038 lane_count <= limits->max_lane_count;
2040 link_clock = intel_dp->common_rates[clock];
2041 link_avail = intel_dp_max_data_rate(link_clock,
2044 if (mode_rate <= link_avail) {
2045 pipe_config->lane_count = lane_count;
2046 pipe_config->pipe_bpp = bpp;
2047 pipe_config->port_clock = link_clock;
2058 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2061 u8 dsc_bpc[3] = {0};
2063 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2065 for (i = 0; i < num_bpc; i++) {
2066 if (dsc_max_bpc >= dsc_bpc[i])
2067 return dsc_bpc[i] * 3;
2073 #define DSC_SUPPORTED_VERSION_MIN 1
2075 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2076 struct intel_crtc_state *crtc_state)
2078 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2079 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2080 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2084 ret = intel_dsc_compute_params(encoder, crtc_state);
2089 * Slice Height of 8 works for all currently available panels. So start
2090 * with that if pic_height is an integral multiple of 8. Eventually add
2091 * logic to try multiple slice heights.
2093 if (vdsc_cfg->pic_height % 8 == 0)
2094 vdsc_cfg->slice_height = 8;
2095 else if (vdsc_cfg->pic_height % 4 == 0)
2096 vdsc_cfg->slice_height = 4;
2098 vdsc_cfg->slice_height = 2;
2100 vdsc_cfg->dsc_version_major =
2101 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2102 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2103 vdsc_cfg->dsc_version_minor =
2104 min(DSC_SUPPORTED_VERSION_MIN,
2105 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2106 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2108 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2111 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2112 if (!line_buf_depth) {
2113 drm_dbg_kms(&i915->drm,
2114 "DSC Sink Line Buffer Depth invalid\n");
2118 if (vdsc_cfg->dsc_version_minor == 2)
2119 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2120 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2122 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2123 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2125 vdsc_cfg->block_pred_enable =
2126 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2127 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2129 return drm_dsc_compute_rc_parameters(vdsc_cfg);
2132 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2133 struct intel_crtc_state *pipe_config,
2134 struct drm_connector_state *conn_state,
2135 struct link_config_limits *limits)
2137 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2138 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2139 const struct drm_display_mode *adjusted_mode =
2140 &pipe_config->hw.adjusted_mode;
2145 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2146 intel_dp_supports_fec(intel_dp, pipe_config);
2148 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2151 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2152 if (INTEL_GEN(dev_priv) >= 12)
2153 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2155 dsc_max_bpc = min_t(u8, 10,
2156 conn_state->max_requested_bpc);
2158 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2160 /* Min Input BPC for ICL+ is 8 */
2161 if (pipe_bpp < 8 * 3) {
2162 drm_dbg_kms(&dev_priv->drm,
2163 "No DSC support for less than 8bpc\n");
2168 * For now enable DSC for max bpp, max link rate, max lane count.
2169 * Optimize this later for the minimum possible link rate/lane count
2170 * with DSC enabled for the requested mode.
2172 pipe_config->pipe_bpp = pipe_bpp;
2173 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2174 pipe_config->lane_count = limits->max_lane_count;
2176 if (intel_dp_is_edp(intel_dp)) {
2177 pipe_config->dsc.compressed_bpp =
2178 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2179 pipe_config->pipe_bpp);
2180 pipe_config->dsc.slice_count =
2181 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2184 u16 dsc_max_output_bpp;
2185 u8 dsc_dp_slice_count;
2187 dsc_max_output_bpp =
2188 intel_dp_dsc_get_output_bpp(dev_priv,
2189 pipe_config->port_clock,
2190 pipe_config->lane_count,
2191 adjusted_mode->crtc_clock,
2192 adjusted_mode->crtc_hdisplay);
2193 dsc_dp_slice_count =
2194 intel_dp_dsc_get_slice_count(intel_dp,
2195 adjusted_mode->crtc_clock,
2196 adjusted_mode->crtc_hdisplay);
2197 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2198 drm_dbg_kms(&dev_priv->drm,
2199 "Compressed BPP/Slice Count not supported\n");
2202 pipe_config->dsc.compressed_bpp = min_t(u16,
2203 dsc_max_output_bpp >> 4,
2204 pipe_config->pipe_bpp);
2205 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2208 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2209 * is greater than the maximum Cdclock and if slice count is even
2210 * then we need to use 2 VDSC instances.
2212 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2213 if (pipe_config->dsc.slice_count > 1) {
2214 pipe_config->dsc.dsc_split = true;
2216 drm_dbg_kms(&dev_priv->drm,
2217 "Cannot split stream to use 2 VDSC instances\n");
2222 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2224 drm_dbg_kms(&dev_priv->drm,
2225 "Cannot compute valid DSC parameters for Input Bpp = %d "
2226 "Compressed BPP = %d\n",
2227 pipe_config->pipe_bpp,
2228 pipe_config->dsc.compressed_bpp);
2232 pipe_config->dsc.compression_enable = true;
2233 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2234 "Compressed Bpp = %d Slice Count = %d\n",
2235 pipe_config->pipe_bpp,
2236 pipe_config->dsc.compressed_bpp,
2237 pipe_config->dsc.slice_count);
2242 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2244 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2251 intel_dp_compute_link_config(struct intel_encoder *encoder,
2252 struct intel_crtc_state *pipe_config,
2253 struct drm_connector_state *conn_state)
2255 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2256 const struct drm_display_mode *adjusted_mode =
2257 &pipe_config->hw.adjusted_mode;
2258 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2259 struct link_config_limits limits;
2263 common_len = intel_dp_common_len_rate_limit(intel_dp,
2264 intel_dp->max_link_rate);
2266 /* No common link rates between source and sink */
2267 drm_WARN_ON(encoder->base.dev, common_len <= 0);
2269 limits.min_clock = 0;
2270 limits.max_clock = common_len - 1;
2272 limits.min_lane_count = 1;
2273 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2275 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2276 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2278 if (intel_dp_is_edp(intel_dp)) {
2280 * Use the maximum clock and number of lanes the eDP panel
2281 * advertizes being capable of. The panels are generally
2282 * designed to support only a single clock and lane
2283 * configuration, and typically these values correspond to the
2284 * native resolution of the panel.
2286 limits.min_lane_count = limits.max_lane_count;
2287 limits.min_clock = limits.max_clock;
2290 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2292 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2293 "max rate %d max bpp %d pixel clock %iKHz\n",
2294 limits.max_lane_count,
2295 intel_dp->common_rates[limits.max_clock],
2296 limits.max_bpp, adjusted_mode->crtc_clock);
2299 * Optimize for slow and wide. This is the place to add alternative
2300 * optimization policy.
2302 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2304 /* enable compression if the mode doesn't fit available BW */
2305 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2306 if (ret || intel_dp->force_dsc_en) {
2307 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2308 conn_state, &limits);
2313 if (pipe_config->dsc.compression_enable) {
2314 drm_dbg_kms(&i915->drm,
2315 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2316 pipe_config->lane_count, pipe_config->port_clock,
2317 pipe_config->pipe_bpp,
2318 pipe_config->dsc.compressed_bpp);
2320 drm_dbg_kms(&i915->drm,
2321 "DP link rate required %i available %i\n",
2322 intel_dp_link_required(adjusted_mode->crtc_clock,
2323 pipe_config->dsc.compressed_bpp),
2324 intel_dp_max_data_rate(pipe_config->port_clock,
2325 pipe_config->lane_count));
2327 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2328 pipe_config->lane_count, pipe_config->port_clock,
2329 pipe_config->pipe_bpp);
2331 drm_dbg_kms(&i915->drm,
2332 "DP link rate required %i available %i\n",
2333 intel_dp_link_required(adjusted_mode->crtc_clock,
2334 pipe_config->pipe_bpp),
2335 intel_dp_max_data_rate(pipe_config->port_clock,
2336 pipe_config->lane_count));
2342 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2343 struct drm_connector *connector,
2344 struct intel_crtc_state *crtc_state)
2346 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2347 const struct drm_display_info *info = &connector->display_info;
2348 const struct drm_display_mode *adjusted_mode =
2349 &crtc_state->hw.adjusted_mode;
2350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2353 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2354 !intel_dp_get_colorimetry_status(intel_dp) ||
2355 !connector->ycbcr_420_allowed)
2358 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2360 /* YCBCR 420 output conversion needs a scaler */
2361 ret = skl_update_scaler_crtc(crtc_state);
2363 drm_dbg_kms(&i915->drm,
2364 "Scaler allocation for output failed\n");
2368 intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2373 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2374 const struct drm_connector_state *conn_state)
2376 const struct intel_digital_connector_state *intel_conn_state =
2377 to_intel_digital_connector_state(conn_state);
2378 const struct drm_display_mode *adjusted_mode =
2379 &crtc_state->hw.adjusted_mode;
2382 * Our YCbCr output is always limited range.
2383 * crtc_state->limited_color_range only applies to RGB,
2384 * and it must never be set for YCbCr or we risk setting
2385 * some conflicting bits in PIPECONF which will mess up
2386 * the colors on the monitor.
2388 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2391 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2394 * CEA-861-E - 5.1 Default Encoding Parameters
2395 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2397 return crtc_state->pipe_bpp != 18 &&
2398 drm_default_rgb_quant_range(adjusted_mode) ==
2399 HDMI_QUANTIZATION_RANGE_LIMITED;
2401 return intel_conn_state->broadcast_rgb ==
2402 INTEL_BROADCAST_RGB_LIMITED;
2406 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2409 if (IS_G4X(dev_priv))
2411 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2417 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2418 const struct drm_connector_state *conn_state,
2419 struct drm_dp_vsc_sdp *vsc)
2421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2425 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2426 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2427 * Colorimetry Format indication.
2429 vsc->revision = 0x5;
2432 /* DP 1.4a spec, Table 2-120 */
2433 switch (crtc_state->output_format) {
2434 case INTEL_OUTPUT_FORMAT_YCBCR444:
2435 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2437 case INTEL_OUTPUT_FORMAT_YCBCR420:
2438 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2440 case INTEL_OUTPUT_FORMAT_RGB:
2442 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2445 switch (conn_state->colorspace) {
2446 case DRM_MODE_COLORIMETRY_BT709_YCC:
2447 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2449 case DRM_MODE_COLORIMETRY_XVYCC_601:
2450 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2452 case DRM_MODE_COLORIMETRY_XVYCC_709:
2453 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2455 case DRM_MODE_COLORIMETRY_SYCC_601:
2456 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2458 case DRM_MODE_COLORIMETRY_OPYCC_601:
2459 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2461 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2462 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2464 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2465 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2467 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2468 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2470 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2471 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2472 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2476 * RGB->YCBCR color conversion uses the BT.709
2479 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2480 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2482 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2486 vsc->bpc = crtc_state->pipe_bpp / 3;
2488 /* only RGB pixelformat supports 6 bpc */
2489 drm_WARN_ON(&dev_priv->drm,
2490 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2492 /* all YCbCr are always limited range */
2493 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2494 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2497 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2498 struct intel_crtc_state *crtc_state,
2499 const struct drm_connector_state *conn_state)
2501 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2503 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2504 if (intel_psr_enabled(intel_dp))
2507 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2510 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2511 vsc->sdp_type = DP_SDP_VSC;
2512 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2513 &crtc_state->infoframes.vsc);
2517 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2518 struct intel_crtc_state *crtc_state,
2519 const struct drm_connector_state *conn_state)
2522 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2523 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2525 if (!conn_state->hdr_output_metadata)
2528 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2531 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2535 crtc_state->infoframes.enable |=
2536 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2540 intel_dp_compute_config(struct intel_encoder *encoder,
2541 struct intel_crtc_state *pipe_config,
2542 struct drm_connector_state *conn_state)
2544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2545 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2546 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2547 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2548 enum port port = encoder->port;
2549 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
2550 struct intel_connector *intel_connector = intel_dp->attached_connector;
2551 struct intel_digital_connector_state *intel_conn_state =
2552 to_intel_digital_connector_state(conn_state);
2553 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2554 DP_DPCD_QUIRK_CONSTANT_N);
2555 int ret = 0, output_bpp;
2557 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2558 pipe_config->has_pch_encoder = true;
2560 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2563 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2565 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2571 pipe_config->has_drrs = false;
2572 if (!intel_dp_port_has_audio(dev_priv, port))
2573 pipe_config->has_audio = false;
2574 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2575 pipe_config->has_audio = intel_dp->has_audio;
2577 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2579 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2580 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2583 if (INTEL_GEN(dev_priv) >= 9) {
2584 ret = skl_update_scaler_crtc(pipe_config);
2589 if (HAS_GMCH(dev_priv))
2590 intel_gmch_panel_fitting(intel_crtc, pipe_config,
2591 conn_state->scaling_mode);
2593 intel_pch_panel_fitting(intel_crtc, pipe_config,
2594 conn_state->scaling_mode);
2597 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2600 if (HAS_GMCH(dev_priv) &&
2601 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2604 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2607 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2610 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2614 pipe_config->limited_color_range =
2615 intel_dp_limited_color_range(pipe_config, conn_state);
2617 if (pipe_config->dsc.compression_enable)
2618 output_bpp = pipe_config->dsc.compressed_bpp;
2620 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2622 intel_link_compute_m_n(output_bpp,
2623 pipe_config->lane_count,
2624 adjusted_mode->crtc_clock,
2625 pipe_config->port_clock,
2626 &pipe_config->dp_m_n,
2627 constant_n, pipe_config->fec_enable);
2629 if (intel_connector->panel.downclock_mode != NULL &&
2630 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2631 pipe_config->has_drrs = true;
2632 intel_link_compute_m_n(output_bpp,
2633 pipe_config->lane_count,
2634 intel_connector->panel.downclock_mode->clock,
2635 pipe_config->port_clock,
2636 &pipe_config->dp_m2_n2,
2637 constant_n, pipe_config->fec_enable);
2640 if (!HAS_DDI(dev_priv))
2641 intel_dp_set_clock(encoder, pipe_config);
2643 intel_psr_compute_config(intel_dp, pipe_config);
2644 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2645 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2650 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2651 int link_rate, u8 lane_count,
2654 intel_dp->link_trained = false;
2655 intel_dp->link_rate = link_rate;
2656 intel_dp->lane_count = lane_count;
2657 intel_dp->link_mst = link_mst;
2660 static void intel_dp_prepare(struct intel_encoder *encoder,
2661 const struct intel_crtc_state *pipe_config)
2663 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2664 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2665 enum port port = encoder->port;
2666 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2667 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2669 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2670 pipe_config->lane_count,
2671 intel_crtc_has_type(pipe_config,
2672 INTEL_OUTPUT_DP_MST));
2674 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2675 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2678 * There are four kinds of DP registers:
2685 * IBX PCH and CPU are the same for almost everything,
2686 * except that the CPU DP PLL is configured in this
2689 * CPT PCH is quite different, having many bits moved
2690 * to the TRANS_DP_CTL register instead. That
2691 * configuration happens (oddly) in ilk_pch_enable
2694 /* Preserve the BIOS-computed detected bit. This is
2695 * supposed to be read-only.
2697 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2699 /* Handle DP bits in common between all three register formats */
2700 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2701 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2703 /* Split out the IBX/CPU vs CPT settings */
2705 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2706 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2707 intel_dp->DP |= DP_SYNC_HS_HIGH;
2708 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2709 intel_dp->DP |= DP_SYNC_VS_HIGH;
2710 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2712 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2713 intel_dp->DP |= DP_ENHANCED_FRAMING;
2715 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2716 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2719 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2721 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2722 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2723 trans_dp |= TRANS_DP_ENH_FRAMING;
2725 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2726 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2728 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2729 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2731 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2732 intel_dp->DP |= DP_SYNC_HS_HIGH;
2733 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2734 intel_dp->DP |= DP_SYNC_VS_HIGH;
2735 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2737 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2738 intel_dp->DP |= DP_ENHANCED_FRAMING;
2740 if (IS_CHERRYVIEW(dev_priv))
2741 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2743 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2747 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2748 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2750 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2751 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2753 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2754 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2756 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2758 static void wait_panel_status(struct intel_dp *intel_dp,
2762 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2763 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2765 lockdep_assert_held(&dev_priv->pps_mutex);
2767 intel_pps_verify_state(intel_dp);
2769 pp_stat_reg = _pp_stat_reg(intel_dp);
2770 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2772 drm_dbg_kms(&dev_priv->drm,
2773 "mask %08x value %08x status %08x control %08x\n",
2775 intel_de_read(dev_priv, pp_stat_reg),
2776 intel_de_read(dev_priv, pp_ctrl_reg));
2778 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2780 drm_err(&dev_priv->drm,
2781 "Panel status timeout: status %08x control %08x\n",
2782 intel_de_read(dev_priv, pp_stat_reg),
2783 intel_de_read(dev_priv, pp_ctrl_reg));
2785 drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2788 static void wait_panel_on(struct intel_dp *intel_dp)
2790 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2792 drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2793 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2796 static void wait_panel_off(struct intel_dp *intel_dp)
2798 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2800 drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2801 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2804 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2806 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2807 ktime_t panel_power_on_time;
2808 s64 panel_power_off_duration;
2810 drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2812 /* take the difference of currrent time and panel power off time
2813 * and then make panel wait for t11_t12 if needed. */
2814 panel_power_on_time = ktime_get_boottime();
2815 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2817 /* When we disable the VDD override bit last we have to do the manual
2819 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2820 wait_remaining_ms_from_jiffies(jiffies,
2821 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2823 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2826 static void wait_backlight_on(struct intel_dp *intel_dp)
2828 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2829 intel_dp->backlight_on_delay);
2832 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2834 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2835 intel_dp->backlight_off_delay);
2838 /* Read the current pp_control value, unlocking the register if it
2842 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2844 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2847 lockdep_assert_held(&dev_priv->pps_mutex);
2849 control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2850 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2851 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2852 control &= ~PANEL_UNLOCK_MASK;
2853 control |= PANEL_UNLOCK_REGS;
2859 * Must be paired with edp_panel_vdd_off().
2860 * Must hold pps_mutex around the whole on/off sequence.
2861 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2863 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2865 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2866 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2868 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2869 bool need_to_disable = !intel_dp->want_panel_vdd;
2871 lockdep_assert_held(&dev_priv->pps_mutex);
2873 if (!intel_dp_is_edp(intel_dp))
2876 cancel_delayed_work(&intel_dp->panel_vdd_work);
2877 intel_dp->want_panel_vdd = true;
2879 if (edp_have_panel_vdd(intel_dp))
2880 return need_to_disable;
2882 intel_display_power_get(dev_priv,
2883 intel_aux_power_domain(intel_dig_port));
2885 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2886 intel_dig_port->base.base.base.id,
2887 intel_dig_port->base.base.name);
2889 if (!edp_have_panel_power(intel_dp))
2890 wait_panel_power_cycle(intel_dp);
2892 pp = ilk_get_pp_control(intel_dp);
2893 pp |= EDP_FORCE_VDD;
2895 pp_stat_reg = _pp_stat_reg(intel_dp);
2896 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2898 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2899 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2900 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2901 intel_de_read(dev_priv, pp_stat_reg),
2902 intel_de_read(dev_priv, pp_ctrl_reg));
2904 * If the panel wasn't on, delay before accessing aux channel
2906 if (!edp_have_panel_power(intel_dp)) {
2907 drm_dbg_kms(&dev_priv->drm,
2908 "[ENCODER:%d:%s] panel power wasn't enabled\n",
2909 intel_dig_port->base.base.base.id,
2910 intel_dig_port->base.base.name);
2911 msleep(intel_dp->panel_power_up_delay);
2914 return need_to_disable;
2918 * Must be paired with intel_edp_panel_vdd_off() or
2919 * intel_edp_panel_off().
2920 * Nested calls to these functions are not allowed since
2921 * we drop the lock. Caller must use some higher level
2922 * locking to prevent nested calls from other threads.
2924 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2926 intel_wakeref_t wakeref;
2929 if (!intel_dp_is_edp(intel_dp))
2933 with_pps_lock(intel_dp, wakeref)
2934 vdd = edp_panel_vdd_on(intel_dp);
2935 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2936 dp_to_dig_port(intel_dp)->base.base.base.id,
2937 dp_to_dig_port(intel_dp)->base.base.name);
2940 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2942 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2943 struct intel_digital_port *intel_dig_port =
2944 dp_to_dig_port(intel_dp);
2946 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2948 lockdep_assert_held(&dev_priv->pps_mutex);
2950 drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
2952 if (!edp_have_panel_vdd(intel_dp))
2955 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2956 intel_dig_port->base.base.base.id,
2957 intel_dig_port->base.base.name);
2959 pp = ilk_get_pp_control(intel_dp);
2960 pp &= ~EDP_FORCE_VDD;
2962 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2963 pp_stat_reg = _pp_stat_reg(intel_dp);
2965 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2966 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2968 /* Make sure sequencer is idle before allowing subsequent activity */
2969 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2970 intel_de_read(dev_priv, pp_stat_reg),
2971 intel_de_read(dev_priv, pp_ctrl_reg));
2973 if ((pp & PANEL_POWER_ON) == 0)
2974 intel_dp->panel_power_off_time = ktime_get_boottime();
2976 intel_display_power_put_unchecked(dev_priv,
2977 intel_aux_power_domain(intel_dig_port));
2980 static void edp_panel_vdd_work(struct work_struct *__work)
2982 struct intel_dp *intel_dp =
2983 container_of(to_delayed_work(__work),
2984 struct intel_dp, panel_vdd_work);
2985 intel_wakeref_t wakeref;
2987 with_pps_lock(intel_dp, wakeref) {
2988 if (!intel_dp->want_panel_vdd)
2989 edp_panel_vdd_off_sync(intel_dp);
2993 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2995 unsigned long delay;
2998 * Queue the timer to fire a long time from now (relative to the power
2999 * down delay) to keep the panel power up across a sequence of
3002 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3003 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3007 * Must be paired with edp_panel_vdd_on().
3008 * Must hold pps_mutex around the whole on/off sequence.
3009 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3011 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3013 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3015 lockdep_assert_held(&dev_priv->pps_mutex);
3017 if (!intel_dp_is_edp(intel_dp))
3020 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3021 dp_to_dig_port(intel_dp)->base.base.base.id,
3022 dp_to_dig_port(intel_dp)->base.base.name);
3024 intel_dp->want_panel_vdd = false;
3027 edp_panel_vdd_off_sync(intel_dp);
3029 edp_panel_vdd_schedule_off(intel_dp);
3032 static void edp_panel_on(struct intel_dp *intel_dp)
3034 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3036 i915_reg_t pp_ctrl_reg;
3038 lockdep_assert_held(&dev_priv->pps_mutex);
3040 if (!intel_dp_is_edp(intel_dp))
3043 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3044 dp_to_dig_port(intel_dp)->base.base.base.id,
3045 dp_to_dig_port(intel_dp)->base.base.name);
3047 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3048 "[ENCODER:%d:%s] panel power already on\n",
3049 dp_to_dig_port(intel_dp)->base.base.base.id,
3050 dp_to_dig_port(intel_dp)->base.base.name))
3053 wait_panel_power_cycle(intel_dp);
3055 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3056 pp = ilk_get_pp_control(intel_dp);
3057 if (IS_GEN(dev_priv, 5)) {
3058 /* ILK workaround: disable reset around power sequence */
3059 pp &= ~PANEL_POWER_RESET;
3060 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3061 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3064 pp |= PANEL_POWER_ON;
3065 if (!IS_GEN(dev_priv, 5))
3066 pp |= PANEL_POWER_RESET;
3068 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3069 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3071 wait_panel_on(intel_dp);
3072 intel_dp->last_power_on = jiffies;
3074 if (IS_GEN(dev_priv, 5)) {
3075 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3076 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3077 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3081 void intel_edp_panel_on(struct intel_dp *intel_dp)
3083 intel_wakeref_t wakeref;
3085 if (!intel_dp_is_edp(intel_dp))
3088 with_pps_lock(intel_dp, wakeref)
3089 edp_panel_on(intel_dp);
3093 static void edp_panel_off(struct intel_dp *intel_dp)
3095 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3096 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3098 i915_reg_t pp_ctrl_reg;
3100 lockdep_assert_held(&dev_priv->pps_mutex);
3102 if (!intel_dp_is_edp(intel_dp))
3105 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3106 dig_port->base.base.base.id, dig_port->base.base.name);
3108 drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3109 "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3110 dig_port->base.base.base.id, dig_port->base.base.name);
3112 pp = ilk_get_pp_control(intel_dp);
3113 /* We need to switch off panel power _and_ force vdd, for otherwise some
3114 * panels get very unhappy and cease to work. */
3115 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3118 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3120 intel_dp->want_panel_vdd = false;
3122 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3123 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3125 wait_panel_off(intel_dp);
3126 intel_dp->panel_power_off_time = ktime_get_boottime();
3128 /* We got a reference when we enabled the VDD. */
3129 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3132 void intel_edp_panel_off(struct intel_dp *intel_dp)
3134 intel_wakeref_t wakeref;
3136 if (!intel_dp_is_edp(intel_dp))
3139 with_pps_lock(intel_dp, wakeref)
3140 edp_panel_off(intel_dp);
3143 /* Enable backlight in the panel power control. */
3144 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3146 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3147 intel_wakeref_t wakeref;
3150 * If we enable the backlight right away following a panel power
3151 * on, we may see slight flicker as the panel syncs with the eDP
3152 * link. So delay a bit to make sure the image is solid before
3153 * allowing it to appear.
3155 wait_backlight_on(intel_dp);
3157 with_pps_lock(intel_dp, wakeref) {
3158 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3161 pp = ilk_get_pp_control(intel_dp);
3162 pp |= EDP_BLC_ENABLE;
3164 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3165 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3169 /* Enable backlight PWM and backlight PP control. */
3170 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3171 const struct drm_connector_state *conn_state)
3173 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3174 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3176 if (!intel_dp_is_edp(intel_dp))
3179 drm_dbg_kms(&i915->drm, "\n");
3181 intel_panel_enable_backlight(crtc_state, conn_state);
3182 _intel_edp_backlight_on(intel_dp);
3185 /* Disable backlight in the panel power control. */
3186 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3188 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3189 intel_wakeref_t wakeref;
3191 if (!intel_dp_is_edp(intel_dp))
3194 with_pps_lock(intel_dp, wakeref) {
3195 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3198 pp = ilk_get_pp_control(intel_dp);
3199 pp &= ~EDP_BLC_ENABLE;
3201 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3202 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3205 intel_dp->last_backlight_off = jiffies;
3206 edp_wait_backlight_off(intel_dp);
3209 /* Disable backlight PP control and backlight PWM. */
3210 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3212 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3213 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3215 if (!intel_dp_is_edp(intel_dp))
3218 drm_dbg_kms(&i915->drm, "\n");
3220 _intel_edp_backlight_off(intel_dp);
3221 intel_panel_disable_backlight(old_conn_state);
3225 * Hook for controlling the panel power control backlight through the bl_power
3226 * sysfs attribute. Take care to handle multiple calls.
3228 static void intel_edp_backlight_power(struct intel_connector *connector,
3231 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3232 struct intel_dp *intel_dp = intel_attached_dp(connector);
3233 intel_wakeref_t wakeref;
3237 with_pps_lock(intel_dp, wakeref)
3238 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3239 if (is_enabled == enable)
3242 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3243 enable ? "enable" : "disable");
3246 _intel_edp_backlight_on(intel_dp);
3248 _intel_edp_backlight_off(intel_dp);
3251 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3253 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3254 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3255 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3257 I915_STATE_WARN(cur_state != state,
3258 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3259 dig_port->base.base.base.id, dig_port->base.base.name,
3260 onoff(state), onoff(cur_state));
3262 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3264 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3266 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3268 I915_STATE_WARN(cur_state != state,
3269 "eDP PLL state assertion failure (expected %s, current %s)\n",
3270 onoff(state), onoff(cur_state));
3272 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3273 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3275 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3276 const struct intel_crtc_state *pipe_config)
3278 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3279 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3281 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3282 assert_dp_port_disabled(intel_dp);
3283 assert_edp_pll_disabled(dev_priv);
3285 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3286 pipe_config->port_clock);
3288 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3290 if (pipe_config->port_clock == 162000)
3291 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3293 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3295 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3296 intel_de_posting_read(dev_priv, DP_A);
3300 * [DevILK] Work around required when enabling DP PLL
3301 * while a pipe is enabled going to FDI:
3302 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3303 * 2. Program DP PLL enable
3305 if (IS_GEN(dev_priv, 5))
3306 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3308 intel_dp->DP |= DP_PLL_ENABLE;
3310 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3311 intel_de_posting_read(dev_priv, DP_A);
3315 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3316 const struct intel_crtc_state *old_crtc_state)
3318 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3319 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3321 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3322 assert_dp_port_disabled(intel_dp);
3323 assert_edp_pll_enabled(dev_priv);
3325 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3327 intel_dp->DP &= ~DP_PLL_ENABLE;
3329 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3330 intel_de_posting_read(dev_priv, DP_A);
3334 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3337 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3338 * be capable of signalling downstream hpd with a long pulse.
3339 * Whether or not that means D3 is safe to use is not clear,
3340 * but let's assume so until proven otherwise.
3342 * FIXME should really check all downstream ports...
3344 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3345 drm_dp_is_branch(intel_dp->dpcd) &&
3346 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3349 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3350 const struct intel_crtc_state *crtc_state,
3353 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3356 if (!crtc_state->dsc.compression_enable)
3359 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3360 enable ? DP_DECOMPRESSION_EN : 0);
3362 drm_dbg_kms(&i915->drm,
3363 "Failed to %s sink decompression state\n",
3364 enable ? "enable" : "disable");
3367 /* If the sink supports it, try to set the power state appropriately */
3368 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3370 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3373 /* Should have a valid DPCD by this point */
3374 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3377 if (mode != DRM_MODE_DPMS_ON) {
3378 if (downstream_hpd_needs_d0(intel_dp))
3381 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3384 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3387 * When turning on, we need to retry for 1ms to give the sink
3390 for (i = 0; i < 3; i++) {
3391 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3398 if (ret == 1 && lspcon->active)
3399 lspcon_wait_pcon_mode(lspcon);
3403 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3404 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3407 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3408 enum port port, enum pipe *pipe)
3412 for_each_pipe(dev_priv, p) {
3413 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3415 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3421 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3424 /* must initialize pipe to something for the asserts */
3430 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3431 i915_reg_t dp_reg, enum port port,
3437 val = intel_de_read(dev_priv, dp_reg);
3439 ret = val & DP_PORT_EN;
3441 /* asserts want to know the pipe even if the port is disabled */
3442 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3443 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3444 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3445 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3446 else if (IS_CHERRYVIEW(dev_priv))
3447 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3449 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3454 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3457 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3458 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3459 intel_wakeref_t wakeref;
3462 wakeref = intel_display_power_get_if_enabled(dev_priv,
3463 encoder->power_domain);
3467 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3468 encoder->port, pipe);
3470 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3475 static void intel_dp_get_config(struct intel_encoder *encoder,
3476 struct intel_crtc_state *pipe_config)
3478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3479 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3481 enum port port = encoder->port;
3482 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3484 if (encoder->type == INTEL_OUTPUT_EDP)
3485 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3487 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3489 tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3491 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3493 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3494 u32 trans_dp = intel_de_read(dev_priv,
3495 TRANS_DP_CTL(crtc->pipe));
3497 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3498 flags |= DRM_MODE_FLAG_PHSYNC;
3500 flags |= DRM_MODE_FLAG_NHSYNC;
3502 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3503 flags |= DRM_MODE_FLAG_PVSYNC;
3505 flags |= DRM_MODE_FLAG_NVSYNC;
3507 if (tmp & DP_SYNC_HS_HIGH)
3508 flags |= DRM_MODE_FLAG_PHSYNC;
3510 flags |= DRM_MODE_FLAG_NHSYNC;
3512 if (tmp & DP_SYNC_VS_HIGH)
3513 flags |= DRM_MODE_FLAG_PVSYNC;
3515 flags |= DRM_MODE_FLAG_NVSYNC;
3518 pipe_config->hw.adjusted_mode.flags |= flags;
3520 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3521 pipe_config->limited_color_range = true;
3523 pipe_config->lane_count =
3524 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3526 intel_dp_get_m_n(crtc, pipe_config);
3528 if (port == PORT_A) {
3529 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3530 pipe_config->port_clock = 162000;
3532 pipe_config->port_clock = 270000;
3535 pipe_config->hw.adjusted_mode.crtc_clock =
3536 intel_dotclock_calculate(pipe_config->port_clock,
3537 &pipe_config->dp_m_n);
3539 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3540 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3542 * This is a big fat ugly hack.
3544 * Some machines in UEFI boot mode provide us a VBT that has 18
3545 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3546 * unknown we fail to light up. Yet the same BIOS boots up with
3547 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3548 * max, not what it tells us to use.
3550 * Note: This will still be broken if the eDP panel is not lit
3551 * up by the BIOS, and thus we can't get the mode at module
3554 drm_dbg_kms(&dev_priv->drm,
3555 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3556 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3557 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3561 static void intel_disable_dp(struct intel_atomic_state *state,
3562 struct intel_encoder *encoder,
3563 const struct intel_crtc_state *old_crtc_state,
3564 const struct drm_connector_state *old_conn_state)
3566 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3568 intel_dp->link_trained = false;
3570 if (old_crtc_state->has_audio)
3571 intel_audio_codec_disable(encoder,
3572 old_crtc_state, old_conn_state);
3574 /* Make sure the panel is off before trying to change the mode. But also
3575 * ensure that we have vdd while we switch off the panel. */
3576 intel_edp_panel_vdd_on(intel_dp);
3577 intel_edp_backlight_off(old_conn_state);
3578 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3579 intel_edp_panel_off(intel_dp);
3582 static void g4x_disable_dp(struct intel_atomic_state *state,
3583 struct intel_encoder *encoder,
3584 const struct intel_crtc_state *old_crtc_state,
3585 const struct drm_connector_state *old_conn_state)
3587 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3590 static void vlv_disable_dp(struct intel_atomic_state *state,
3591 struct intel_encoder *encoder,
3592 const struct intel_crtc_state *old_crtc_state,
3593 const struct drm_connector_state *old_conn_state)
3595 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3598 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3599 struct intel_encoder *encoder,
3600 const struct intel_crtc_state *old_crtc_state,
3601 const struct drm_connector_state *old_conn_state)
3603 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3604 enum port port = encoder->port;
3607 * Bspec does not list a specific disable sequence for g4x DP.
3608 * Follow the ilk+ sequence (disable pipe before the port) for
3609 * g4x DP as it does not suffer from underruns like the normal
3610 * g4x modeset sequence (disable pipe after the port).
3612 intel_dp_link_down(encoder, old_crtc_state);
3614 /* Only ilk+ has port A */
3616 ilk_edp_pll_off(intel_dp, old_crtc_state);
3619 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3620 struct intel_encoder *encoder,
3621 const struct intel_crtc_state *old_crtc_state,
3622 const struct drm_connector_state *old_conn_state)
3624 intel_dp_link_down(encoder, old_crtc_state);
3627 static void chv_post_disable_dp(struct intel_atomic_state *state,
3628 struct intel_encoder *encoder,
3629 const struct intel_crtc_state *old_crtc_state,
3630 const struct drm_connector_state *old_conn_state)
3632 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3634 intel_dp_link_down(encoder, old_crtc_state);
3636 vlv_dpio_get(dev_priv);
3638 /* Assert data lane reset */
3639 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3641 vlv_dpio_put(dev_priv);
3645 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3649 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3650 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3651 enum port port = intel_dig_port->base.port;
3652 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3654 if (dp_train_pat & train_pat_mask)
3655 drm_dbg_kms(&dev_priv->drm,
3656 "Using DP training pattern TPS%d\n",
3657 dp_train_pat & train_pat_mask);
3659 if (HAS_DDI(dev_priv)) {
3660 u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3662 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3663 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3665 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3667 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3668 switch (dp_train_pat & train_pat_mask) {
3669 case DP_TRAINING_PATTERN_DISABLE:
3670 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3673 case DP_TRAINING_PATTERN_1:
3674 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3676 case DP_TRAINING_PATTERN_2:
3677 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3679 case DP_TRAINING_PATTERN_3:
3680 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3682 case DP_TRAINING_PATTERN_4:
3683 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3686 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
3688 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3689 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3690 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3692 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3693 case DP_TRAINING_PATTERN_DISABLE:
3694 *DP |= DP_LINK_TRAIN_OFF_CPT;
3696 case DP_TRAINING_PATTERN_1:
3697 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3699 case DP_TRAINING_PATTERN_2:
3700 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3702 case DP_TRAINING_PATTERN_3:
3703 drm_dbg_kms(&dev_priv->drm,
3704 "TPS3 not supported, using TPS2 instead\n");
3705 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3710 *DP &= ~DP_LINK_TRAIN_MASK;
3712 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3713 case DP_TRAINING_PATTERN_DISABLE:
3714 *DP |= DP_LINK_TRAIN_OFF;
3716 case DP_TRAINING_PATTERN_1:
3717 *DP |= DP_LINK_TRAIN_PAT_1;
3719 case DP_TRAINING_PATTERN_2:
3720 *DP |= DP_LINK_TRAIN_PAT_2;
3722 case DP_TRAINING_PATTERN_3:
3723 drm_dbg_kms(&dev_priv->drm,
3724 "TPS3 not supported, using TPS2 instead\n");
3725 *DP |= DP_LINK_TRAIN_PAT_2;
3731 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3732 const struct intel_crtc_state *old_crtc_state)
3734 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3736 /* enable with pattern 1 (as per spec) */
3738 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3741 * Magic for VLV/CHV. We _must_ first set up the register
3742 * without actually enabling the port, and then do another
3743 * write to enable the port. Otherwise link training will
3744 * fail when the power sequencer is freshly used for this port.
3746 intel_dp->DP |= DP_PORT_EN;
3747 if (old_crtc_state->has_audio)
3748 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3750 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3751 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3754 static void intel_enable_dp(struct intel_atomic_state *state,
3755 struct intel_encoder *encoder,
3756 const struct intel_crtc_state *pipe_config,
3757 const struct drm_connector_state *conn_state)
3759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3760 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3761 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3762 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3763 enum pipe pipe = crtc->pipe;
3764 intel_wakeref_t wakeref;
3766 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3769 with_pps_lock(intel_dp, wakeref) {
3770 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3771 vlv_init_panel_power_sequencer(encoder, pipe_config);
3773 intel_dp_enable_port(intel_dp, pipe_config);
3775 edp_panel_vdd_on(intel_dp);
3776 edp_panel_on(intel_dp);
3777 edp_panel_vdd_off(intel_dp, true);
3780 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3781 unsigned int lane_mask = 0x0;
3783 if (IS_CHERRYVIEW(dev_priv))
3784 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3786 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3790 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3791 intel_dp_start_link_train(intel_dp);
3792 intel_dp_stop_link_train(intel_dp);
3794 if (pipe_config->has_audio) {
3795 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3797 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3801 static void g4x_enable_dp(struct intel_atomic_state *state,
3802 struct intel_encoder *encoder,
3803 const struct intel_crtc_state *pipe_config,
3804 const struct drm_connector_state *conn_state)
3806 intel_enable_dp(state, encoder, pipe_config, conn_state);
3807 intel_edp_backlight_on(pipe_config, conn_state);
3810 static void vlv_enable_dp(struct intel_atomic_state *state,
3811 struct intel_encoder *encoder,
3812 const struct intel_crtc_state *pipe_config,
3813 const struct drm_connector_state *conn_state)
3815 intel_edp_backlight_on(pipe_config, conn_state);
3818 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3819 struct intel_encoder *encoder,
3820 const struct intel_crtc_state *pipe_config,
3821 const struct drm_connector_state *conn_state)
3823 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3824 enum port port = encoder->port;
3826 intel_dp_prepare(encoder, pipe_config);
3828 /* Only ilk+ has port A */
3830 ilk_edp_pll_on(intel_dp, pipe_config);
3833 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3835 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3836 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3837 enum pipe pipe = intel_dp->pps_pipe;
3838 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3840 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3842 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3845 edp_panel_vdd_off_sync(intel_dp);
3848 * VLV seems to get confused when multiple power sequencers
3849 * have the same port selected (even if only one has power/vdd
3850 * enabled). The failure manifests as vlv_wait_port_ready() failing
3851 * CHV on the other hand doesn't seem to mind having the same port
3852 * selected in multiple power sequencers, but let's clear the
3853 * port select always when logically disconnecting a power sequencer
3856 drm_dbg_kms(&dev_priv->drm,
3857 "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3858 pipe_name(pipe), intel_dig_port->base.base.base.id,
3859 intel_dig_port->base.base.name);
3860 intel_de_write(dev_priv, pp_on_reg, 0);
3861 intel_de_posting_read(dev_priv, pp_on_reg);
3863 intel_dp->pps_pipe = INVALID_PIPE;
3866 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3869 struct intel_encoder *encoder;
3871 lockdep_assert_held(&dev_priv->pps_mutex);
3873 for_each_intel_dp(&dev_priv->drm, encoder) {
3874 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3876 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3877 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3878 pipe_name(pipe), encoder->base.base.id,
3879 encoder->base.name);
3881 if (intel_dp->pps_pipe != pipe)
3884 drm_dbg_kms(&dev_priv->drm,
3885 "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3886 pipe_name(pipe), encoder->base.base.id,
3887 encoder->base.name);
3889 /* make sure vdd is off before we steal it */
3890 vlv_detach_power_sequencer(intel_dp);
3894 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3895 const struct intel_crtc_state *crtc_state)
3897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3898 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3899 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3901 lockdep_assert_held(&dev_priv->pps_mutex);
3903 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3905 if (intel_dp->pps_pipe != INVALID_PIPE &&
3906 intel_dp->pps_pipe != crtc->pipe) {
3908 * If another power sequencer was being used on this
3909 * port previously make sure to turn off vdd there while
3910 * we still have control of it.
3912 vlv_detach_power_sequencer(intel_dp);
3916 * We may be stealing the power
3917 * sequencer from another port.
3919 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3921 intel_dp->active_pipe = crtc->pipe;
3923 if (!intel_dp_is_edp(intel_dp))
3926 /* now it's all ours */
3927 intel_dp->pps_pipe = crtc->pipe;
3929 drm_dbg_kms(&dev_priv->drm,
3930 "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3931 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3932 encoder->base.name);
3934 /* init power sequencer on this pipe and port */
3935 intel_dp_init_panel_power_sequencer(intel_dp);
3936 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3939 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3940 struct intel_encoder *encoder,
3941 const struct intel_crtc_state *pipe_config,
3942 const struct drm_connector_state *conn_state)
3944 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3946 intel_enable_dp(state, encoder, pipe_config, conn_state);
3949 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3950 struct intel_encoder *encoder,
3951 const struct intel_crtc_state *pipe_config,
3952 const struct drm_connector_state *conn_state)
3954 intel_dp_prepare(encoder, pipe_config);
3956 vlv_phy_pre_pll_enable(encoder, pipe_config);
3959 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3960 struct intel_encoder *encoder,
3961 const struct intel_crtc_state *pipe_config,
3962 const struct drm_connector_state *conn_state)
3964 chv_phy_pre_encoder_enable(encoder, pipe_config);
3966 intel_enable_dp(state, encoder, pipe_config, conn_state);
3968 /* Second common lane will stay alive on its own now */
3969 chv_phy_release_cl2_override(encoder);
3972 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
3973 struct intel_encoder *encoder,
3974 const struct intel_crtc_state *pipe_config,
3975 const struct drm_connector_state *conn_state)
3977 intel_dp_prepare(encoder, pipe_config);
3979 chv_phy_pre_pll_enable(encoder, pipe_config);
3982 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3983 struct intel_encoder *encoder,
3984 const struct intel_crtc_state *old_crtc_state,
3985 const struct drm_connector_state *old_conn_state)
3987 chv_phy_post_pll_disable(encoder, old_crtc_state);
3991 * Fetch AUX CH registers 0x202 - 0x207 which contain
3992 * link status information
3995 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3997 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3998 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
4001 /* These are source-specific values. */
4003 intel_dp_voltage_max(struct intel_dp *intel_dp)
4005 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4006 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4007 enum port port = encoder->port;
4009 if (HAS_DDI(dev_priv))
4010 return intel_ddi_dp_voltage_max(encoder);
4011 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4012 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4013 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
4014 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4015 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
4016 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4018 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4022 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
4024 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4025 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4026 enum port port = encoder->port;
4028 if (HAS_DDI(dev_priv)) {
4029 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
4030 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4031 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4033 return DP_TRAIN_PRE_EMPH_LEVEL_3;
4034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4035 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4037 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4040 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4042 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4043 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4045 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4048 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4050 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4053 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4055 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4057 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4059 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4062 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4067 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
4069 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4070 unsigned long demph_reg_value, preemph_reg_value,
4071 uniqtranscale_reg_value;
4072 u8 train_set = intel_dp->train_set[0];
4074 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4075 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4076 preemph_reg_value = 0x0004000;
4077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4079 demph_reg_value = 0x2B405555;
4080 uniqtranscale_reg_value = 0x552AB83A;
4082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4083 demph_reg_value = 0x2B404040;
4084 uniqtranscale_reg_value = 0x5548B83A;
4086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4087 demph_reg_value = 0x2B245555;
4088 uniqtranscale_reg_value = 0x5560B83A;
4090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4091 demph_reg_value = 0x2B405555;
4092 uniqtranscale_reg_value = 0x5598DA3A;
4098 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4099 preemph_reg_value = 0x0002000;
4100 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4102 demph_reg_value = 0x2B404040;
4103 uniqtranscale_reg_value = 0x5552B83A;
4105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4106 demph_reg_value = 0x2B404848;
4107 uniqtranscale_reg_value = 0x5580B83A;
4109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4110 demph_reg_value = 0x2B404040;
4111 uniqtranscale_reg_value = 0x55ADDA3A;
4117 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4118 preemph_reg_value = 0x0000000;
4119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4121 demph_reg_value = 0x2B305555;
4122 uniqtranscale_reg_value = 0x5570B83A;
4124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4125 demph_reg_value = 0x2B2B4040;
4126 uniqtranscale_reg_value = 0x55ADDA3A;
4132 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4133 preemph_reg_value = 0x0006000;
4134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4136 demph_reg_value = 0x1B405555;
4137 uniqtranscale_reg_value = 0x55ADDA3A;
4147 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4148 uniqtranscale_reg_value, 0);
4153 static u32 chv_signal_levels(struct intel_dp *intel_dp)
4155 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4156 u32 deemph_reg_value, margin_reg_value;
4157 bool uniq_trans_scale = false;
4158 u8 train_set = intel_dp->train_set[0];
4160 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4161 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4164 deemph_reg_value = 128;
4165 margin_reg_value = 52;
4167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4168 deemph_reg_value = 128;
4169 margin_reg_value = 77;
4171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4172 deemph_reg_value = 128;
4173 margin_reg_value = 102;
4175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4176 deemph_reg_value = 128;
4177 margin_reg_value = 154;
4178 uniq_trans_scale = true;
4184 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4185 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4187 deemph_reg_value = 85;
4188 margin_reg_value = 78;
4190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4191 deemph_reg_value = 85;
4192 margin_reg_value = 116;
4194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4195 deemph_reg_value = 85;
4196 margin_reg_value = 154;
4202 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4203 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4205 deemph_reg_value = 64;
4206 margin_reg_value = 104;
4208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4209 deemph_reg_value = 64;
4210 margin_reg_value = 154;
4216 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4217 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4219 deemph_reg_value = 43;
4220 margin_reg_value = 154;
4230 chv_set_phy_signal_level(encoder, deemph_reg_value,
4231 margin_reg_value, uniq_trans_scale);
4237 g4x_signal_levels(u8 train_set)
4239 u32 signal_levels = 0;
4241 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4244 signal_levels |= DP_VOLTAGE_0_4;
4246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4247 signal_levels |= DP_VOLTAGE_0_6;
4249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4250 signal_levels |= DP_VOLTAGE_0_8;
4252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4253 signal_levels |= DP_VOLTAGE_1_2;
4256 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4257 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4259 signal_levels |= DP_PRE_EMPHASIS_0;
4261 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4262 signal_levels |= DP_PRE_EMPHASIS_3_5;
4264 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4265 signal_levels |= DP_PRE_EMPHASIS_6;
4267 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4268 signal_levels |= DP_PRE_EMPHASIS_9_5;
4271 return signal_levels;
4274 /* SNB CPU eDP voltage swing and pre-emphasis control */
4276 snb_cpu_edp_signal_levels(u8 train_set)
4278 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4279 DP_TRAIN_PRE_EMPHASIS_MASK);
4280 switch (signal_levels) {
4281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4283 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4285 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4288 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4291 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4294 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4296 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4297 "0x%x\n", signal_levels);
4298 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4302 /* IVB CPU eDP voltage swing and pre-emphasis control */
4304 ivb_cpu_edp_signal_levels(u8 train_set)
4306 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4307 DP_TRAIN_PRE_EMPHASIS_MASK);
4308 switch (signal_levels) {
4309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4310 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4312 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4314 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4317 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4319 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4322 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4324 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4328 "0x%x\n", signal_levels);
4329 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4334 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4336 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4338 enum port port = intel_dig_port->base.port;
4339 u32 signal_levels, mask = 0;
4340 u8 train_set = intel_dp->train_set[0];
4342 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4343 signal_levels = bxt_signal_levels(intel_dp);
4344 } else if (HAS_DDI(dev_priv)) {
4345 signal_levels = ddi_signal_levels(intel_dp);
4346 mask = DDI_BUF_EMP_MASK;
4347 } else if (IS_CHERRYVIEW(dev_priv)) {
4348 signal_levels = chv_signal_levels(intel_dp);
4349 } else if (IS_VALLEYVIEW(dev_priv)) {
4350 signal_levels = vlv_signal_levels(intel_dp);
4351 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4352 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4353 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4354 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4355 signal_levels = snb_cpu_edp_signal_levels(train_set);
4356 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4358 signal_levels = g4x_signal_levels(train_set);
4359 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4363 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4366 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4367 train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4368 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4369 drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4370 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4371 DP_TRAIN_PRE_EMPHASIS_SHIFT,
4372 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4375 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4377 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4378 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4382 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4386 struct drm_i915_private *dev_priv =
4387 to_i915(intel_dig_port->base.base.dev);
4389 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4391 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4392 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4395 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4397 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4399 enum port port = intel_dig_port->base.port;
4402 if (!HAS_DDI(dev_priv))
4405 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4406 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4407 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4408 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4411 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4412 * reason we need to set idle transmission mode is to work around a HW
4413 * issue where we enable the pipe while not in idle link-training mode.
4414 * In this case there is requirement to wait for a minimum number of
4415 * idle patterns to be sent.
4417 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4420 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4421 DP_TP_STATUS_IDLE_DONE, 1))
4422 drm_err(&dev_priv->drm,
4423 "Timed out waiting for DP idle patterns\n");
4427 intel_dp_link_down(struct intel_encoder *encoder,
4428 const struct intel_crtc_state *old_crtc_state)
4430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4431 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4432 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4433 enum port port = encoder->port;
4434 u32 DP = intel_dp->DP;
4436 if (drm_WARN_ON(&dev_priv->drm,
4437 (intel_de_read(dev_priv, intel_dp->output_reg) &
4441 drm_dbg_kms(&dev_priv->drm, "\n");
4443 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4444 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4445 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4446 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4448 DP &= ~DP_LINK_TRAIN_MASK;
4449 DP |= DP_LINK_TRAIN_PAT_IDLE;
4451 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4452 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4454 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4455 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4456 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4459 * HW workaround for IBX, we need to move the port
4460 * to transcoder A after disabling it to allow the
4461 * matching HDMI port to be enabled on transcoder A.
4463 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4465 * We get CPU/PCH FIFO underruns on the other pipe when
4466 * doing the workaround. Sweep them under the rug.
4468 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4469 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4471 /* always enable with pattern 1 (as per spec) */
4472 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4473 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4474 DP_LINK_TRAIN_PAT_1;
4475 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4476 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4479 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4480 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4482 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4483 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4484 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4487 msleep(intel_dp->panel_power_down_delay);
4491 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4492 intel_wakeref_t wakeref;
4494 with_pps_lock(intel_dp, wakeref)
4495 intel_dp->active_pipe = INVALID_PIPE;
4500 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4502 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4506 * Prior to DP1.3 the bit represented by
4507 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4508 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4509 * the true capability of the panel. The only way to check is to
4510 * then compare 0000h and 2200h.
4512 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4513 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4516 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4517 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4519 "DPCD failed read at extended capabilities\n");
4523 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4524 drm_dbg_kms(&i915->drm,
4525 "DPCD extended DPCD rev less than base DPCD rev\n");
4529 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4532 drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n",
4533 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4535 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4539 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4541 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4543 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4544 sizeof(intel_dp->dpcd)) < 0)
4545 return false; /* aux transfer failed */
4547 intel_dp_extended_receiver_capabilities(intel_dp);
4549 drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd),
4552 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4555 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4559 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4562 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4565 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4567 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4570 * Clear the cached register set to avoid using stale values
4571 * for the sinks that do not support DSC.
4573 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4575 /* Clear fec_capable to avoid using stale values */
4576 intel_dp->fec_capable = 0;
4578 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4579 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4580 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4581 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4583 sizeof(intel_dp->dsc_dpcd)) < 0)
4585 "Failed to read DPCD register 0x%x\n",
4588 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4589 (int)sizeof(intel_dp->dsc_dpcd),
4590 intel_dp->dsc_dpcd);
4592 /* FEC is supported only on DP 1.4 */
4593 if (!intel_dp_is_edp(intel_dp) &&
4594 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4595 &intel_dp->fec_capable) < 0)
4597 "Failed to read FEC DPCD register\n");
4599 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4600 intel_dp->fec_capable);
4605 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4607 struct drm_i915_private *dev_priv =
4608 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4610 /* this function is meant to be called only once */
4611 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4613 if (!intel_dp_read_dpcd(intel_dp))
4616 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4617 drm_dp_is_branch(intel_dp->dpcd));
4620 * Read the eDP display control registers.
4622 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4623 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4624 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4625 * method). The display control registers should read zero if they're
4626 * not supported anyway.
4628 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4629 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4630 sizeof(intel_dp->edp_dpcd))
4631 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4632 (int)sizeof(intel_dp->edp_dpcd),
4633 intel_dp->edp_dpcd);
4636 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4637 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4639 intel_psr_init_dpcd(intel_dp);
4641 /* Read the eDP 1.4+ supported link rates. */
4642 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4643 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4646 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4647 sink_rates, sizeof(sink_rates));
4649 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4650 int val = le16_to_cpu(sink_rates[i]);
4655 /* Value read multiplied by 200kHz gives the per-lane
4656 * link rate in kHz. The source rates are, however,
4657 * stored in terms of LS_Clk kHz. The full conversion
4658 * back to symbols is
4659 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4661 intel_dp->sink_rates[i] = (val * 200) / 10;
4663 intel_dp->num_sink_rates = i;
4667 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4668 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4670 if (intel_dp->num_sink_rates)
4671 intel_dp->use_rate_select = true;
4673 intel_dp_set_sink_rates(intel_dp);
4675 intel_dp_set_common_rates(intel_dp);
4677 /* Read the eDP DSC DPCD registers */
4678 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4679 intel_dp_get_dsc_sink_cap(intel_dp);
4686 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4688 if (!intel_dp_read_dpcd(intel_dp))
4692 * Don't clobber cached eDP rates. Also skip re-reading
4693 * the OUI/ID since we know it won't change.
4695 if (!intel_dp_is_edp(intel_dp)) {
4696 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4697 drm_dp_is_branch(intel_dp->dpcd));
4699 intel_dp_set_sink_rates(intel_dp);
4700 intel_dp_set_common_rates(intel_dp);
4704 * Some eDP panels do not set a valid value for sink count, that is why
4705 * it don't care about read it here and in intel_edp_init_dpcd().
4707 if (!intel_dp_is_edp(intel_dp) &&
4708 !drm_dp_has_quirk(&intel_dp->desc, 0,
4709 DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4713 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4718 * Sink count can change between short pulse hpd hence
4719 * a member variable in intel_dp will track any changes
4720 * between short pulse interrupts.
4722 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4725 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4726 * a dongle is present but no display. Unless we require to know
4727 * if a dongle is present or not, we don't need to update
4728 * downstream port information. So, an early return here saves
4729 * time from performing other operations which are not required.
4731 if (!intel_dp->sink_count)
4735 if (!drm_dp_is_branch(intel_dp->dpcd))
4736 return true; /* native DP sink */
4738 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4739 return true; /* no per-port downstream info */
4741 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4742 intel_dp->downstream_ports,
4743 DP_MAX_DOWNSTREAM_PORTS) < 0)
4744 return false; /* downstream port status fetch failed */
4750 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4754 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4757 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4760 return mstm_cap & DP_MST_CAP;
4764 intel_dp_can_mst(struct intel_dp *intel_dp)
4766 return i915_modparams.enable_dp_mst &&
4767 intel_dp->can_mst &&
4768 intel_dp_sink_can_mst(intel_dp);
4772 intel_dp_configure_mst(struct intel_dp *intel_dp)
4774 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4775 struct intel_encoder *encoder =
4776 &dp_to_dig_port(intel_dp)->base;
4777 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4779 drm_dbg_kms(&i915->drm,
4780 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4781 encoder->base.base.id, encoder->base.name,
4782 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4783 yesno(i915_modparams.enable_dp_mst));
4785 if (!intel_dp->can_mst)
4788 intel_dp->is_mst = sink_can_mst &&
4789 i915_modparams.enable_dp_mst;
4791 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4796 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4798 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4799 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4804 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4805 const struct drm_connector_state *conn_state)
4808 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4809 * of Color Encoding Format and Content Color Gamut], in order to
4810 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4812 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4815 switch (conn_state->colorspace) {
4816 case DRM_MODE_COLORIMETRY_SYCC_601:
4817 case DRM_MODE_COLORIMETRY_OPYCC_601:
4818 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4819 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4820 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4829 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4830 struct dp_sdp *sdp, size_t size)
4832 size_t length = sizeof(struct dp_sdp);
4837 memset(sdp, 0, size);
4840 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4841 * VSC SDP Header Bytes
4843 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4844 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4845 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4846 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4848 /* VSC SDP Payload for DB16 through DB18 */
4849 /* Pixel Encoding and Colorimetry Formats */
4850 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4851 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4858 sdp->db[17] = 0x1; /* DB17[3:0] */
4870 MISSING_CASE(vsc->bpc);
4873 /* Dynamic Range and Component Bit Depth */
4874 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4875 sdp->db[17] |= 0x80; /* DB17[7] */
4878 sdp->db[18] = vsc->content_type & 0x7;
4884 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4888 size_t length = sizeof(struct dp_sdp);
4889 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4890 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4896 memset(sdp, 0, size);
4898 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4900 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4904 if (len != infoframe_size) {
4905 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4910 * Set up the infoframe sdp packet for HDR static metadata.
4911 * Prepare VSC Header for SU as per DP 1.4a spec,
4912 * Table 2-100 and Table 2-101
4915 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4916 sdp->sdp_header.HB0 = 0;
4918 * Packet Type 80h + Non-audio INFOFRAME Type value
4919 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4920 * - 80h + Non-audio INFOFRAME Type value
4921 * - InfoFrame Type: 0x07
4922 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4924 sdp->sdp_header.HB1 = drm_infoframe->type;
4926 * Least Significant Eight Bits of (Data Byte Count – 1)
4927 * infoframe_size - 1
4929 sdp->sdp_header.HB2 = 0x1D;
4930 /* INFOFRAME SDP Version Number */
4931 sdp->sdp_header.HB3 = (0x13 << 2);
4932 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4933 sdp->db[0] = drm_infoframe->version;
4934 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4935 sdp->db[1] = drm_infoframe->length;
4937 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4938 * HDMI_INFOFRAME_HEADER_SIZE
4940 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4941 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4942 HDMI_DRM_INFOFRAME_SIZE);
4945 * Size of DP infoframe sdp packet for HDR static metadata consists of
4946 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4947 * - Two Data Blocks: 2 bytes
4948 * CTA Header Byte2 (INFOFRAME Version Number)
4949 * CTA Header Byte3 (Length of INFOFRAME)
4950 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4952 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4953 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4954 * will pad rest of the size.
4956 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4959 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4960 const struct intel_crtc_state *crtc_state,
4963 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4965 struct dp_sdp sdp = {};
4968 if ((crtc_state->infoframes.enable &
4969 intel_hdmi_infoframe_enable(type)) == 0)
4974 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4977 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4978 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4986 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4989 intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4992 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4994 const struct intel_crtc_state *crtc_state,
4995 const struct drm_connector_state *conn_state)
4997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4998 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4999 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5000 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5001 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5002 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5003 u32 val = intel_de_read(dev_priv, reg);
5005 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5006 /* When PSR is enabled, this routine doesn't disable VSC DIP */
5007 if (intel_psr_enabled(intel_dp))
5010 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5013 intel_de_write(dev_priv, reg, val);
5014 intel_de_posting_read(dev_priv, reg);
5018 intel_de_write(dev_priv, reg, val);
5019 intel_de_posting_read(dev_priv, reg);
5021 /* When PSR is enabled, VSC SDP is handled by PSR routine */
5022 if (!intel_psr_enabled(intel_dp))
5023 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5025 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5029 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
5030 const struct intel_crtc_state *crtc_state,
5031 const struct drm_connector_state *conn_state)
5033 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5034 struct dp_sdp vsc_sdp = {};
5036 /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
5037 vsc_sdp.sdp_header.HB0 = 0;
5038 vsc_sdp.sdp_header.HB1 = 0x7;
5041 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
5042 * Colorimetry Format indication.
5044 vsc_sdp.sdp_header.HB2 = 0x5;
5047 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
5048 * Colorimetry Format indication (HB2 = 05h).
5050 vsc_sdp.sdp_header.HB3 = 0x13;
5052 /* DP 1.4a spec, Table 2-120 */
5053 switch (crtc_state->output_format) {
5054 case INTEL_OUTPUT_FORMAT_YCBCR444:
5055 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
5057 case INTEL_OUTPUT_FORMAT_YCBCR420:
5058 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
5060 case INTEL_OUTPUT_FORMAT_RGB:
5062 /* RGB: DB16[7:4] = 0h */
5066 switch (conn_state->colorspace) {
5067 case DRM_MODE_COLORIMETRY_BT709_YCC:
5068 vsc_sdp.db[16] |= 0x1;
5070 case DRM_MODE_COLORIMETRY_XVYCC_601:
5071 vsc_sdp.db[16] |= 0x2;
5073 case DRM_MODE_COLORIMETRY_XVYCC_709:
5074 vsc_sdp.db[16] |= 0x3;
5076 case DRM_MODE_COLORIMETRY_SYCC_601:
5077 vsc_sdp.db[16] |= 0x4;
5079 case DRM_MODE_COLORIMETRY_OPYCC_601:
5080 vsc_sdp.db[16] |= 0x5;
5082 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5083 case DRM_MODE_COLORIMETRY_BT2020_RGB:
5084 vsc_sdp.db[16] |= 0x6;
5086 case DRM_MODE_COLORIMETRY_BT2020_YCC:
5087 vsc_sdp.db[16] |= 0x7;
5089 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
5090 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
5091 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
5094 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
5096 /* RGB->YCBCR color conversion uses the BT.709 color space. */
5097 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5098 vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
5103 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
5104 * the following Component Bit Depth values are defined:
5110 switch (crtc_state->pipe_bpp) {
5112 vsc_sdp.db[17] = 0x1;
5114 case 30: /* 10bpc */
5115 vsc_sdp.db[17] = 0x2;
5117 case 36: /* 12bpc */
5118 vsc_sdp.db[17] = 0x3;
5120 case 48: /* 16bpc */
5121 vsc_sdp.db[17] = 0x4;
5124 MISSING_CASE(crtc_state->pipe_bpp);
5129 * Dynamic Range (Bit 7)
5130 * 0 = VESA range, 1 = CTA range.
5131 * all YCbCr are always limited range
5133 vsc_sdp.db[17] |= 0x80;
5136 * Content Type (Bits 2:0)
5137 * 000b = Not defined.
5142 * All other values are RESERVED.
5143 * Note: See CTA-861-G for the definition and expected
5144 * processing by a stream sink for the above contect types.
5148 intel_dig_port->write_infoframe(&intel_dig_port->base,
5149 crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
5153 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
5154 const struct intel_crtc_state *crtc_state,
5155 const struct drm_connector_state *conn_state)
5157 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5158 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5159 struct dp_sdp infoframe_sdp = {};
5160 struct hdmi_drm_infoframe drm_infoframe = {};
5161 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5162 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5166 ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
5168 drm_dbg_kms(&i915->drm,
5169 "couldn't set HDR metadata in infoframe\n");
5173 len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
5175 drm_dbg_kms(&i915->drm,
5176 "buffer size is smaller than hdr metadata infoframe\n");
5180 if (len != infoframe_size) {
5181 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
5186 * Set up the infoframe sdp packet for HDR static metadata.
5187 * Prepare VSC Header for SU as per DP 1.4a spec,
5188 * Table 2-100 and Table 2-101
5191 /* Packet ID, 00h for non-Audio INFOFRAME */
5192 infoframe_sdp.sdp_header.HB0 = 0;
5194 * Packet Type 80h + Non-audio INFOFRAME Type value
5195 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
5197 infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
5199 * Least Significant Eight Bits of (Data Byte Count – 1)
5200 * infoframe_size - 1,
5202 infoframe_sdp.sdp_header.HB2 = 0x1D;
5203 /* INFOFRAME SDP Version Number */
5204 infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
5205 /* CTA Header Byte 2 (INFOFRAME Version Number) */
5206 infoframe_sdp.db[0] = drm_infoframe.version;
5207 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5208 infoframe_sdp.db[1] = drm_infoframe.length;
5210 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5211 * HDMI_INFOFRAME_HEADER_SIZE
5213 BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5214 memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5215 HDMI_DRM_INFOFRAME_SIZE);
5218 * Size of DP infoframe sdp packet for HDR static metadata is consist of
5219 * - DP SDP Header(struct dp_sdp_header): 4 bytes
5220 * - Two Data Blocks: 2 bytes
5221 * CTA Header Byte2 (INFOFRAME Version Number)
5222 * CTA Header Byte3 (Length of INFOFRAME)
5223 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5225 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5226 * infoframe size. But GEN11+ has larger than that size, write_infoframe
5227 * will pad rest of the size.
5229 intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
5230 HDMI_PACKET_TYPE_GAMUT_METADATA,
5232 sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
5235 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
5236 const struct intel_crtc_state *crtc_state,
5237 const struct drm_connector_state *conn_state)
5239 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
5242 intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
5245 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
5246 const struct intel_crtc_state *crtc_state,
5247 const struct drm_connector_state *conn_state)
5249 if (!conn_state->hdr_output_metadata)
5252 intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
5257 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5259 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5262 u8 test_lane_count, test_link_bw;
5266 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5267 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5271 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5274 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5276 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5279 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5282 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5284 /* Validate the requested link rate and lane count */
5285 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5289 intel_dp->compliance.test_lane_count = test_lane_count;
5290 intel_dp->compliance.test_link_rate = test_link_rate;
5295 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5297 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5300 __be16 h_width, v_height;
5303 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5304 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5307 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5310 if (test_pattern != DP_COLOR_RAMP)
5313 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5316 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5320 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5323 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5327 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5330 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5333 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5335 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5337 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5338 case DP_TEST_BIT_DEPTH_6:
5339 intel_dp->compliance.test_data.bpc = 6;
5341 case DP_TEST_BIT_DEPTH_8:
5342 intel_dp->compliance.test_data.bpc = 8;
5348 intel_dp->compliance.test_data.video_pattern = test_pattern;
5349 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5350 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5351 /* Set test active flag here so userspace doesn't interrupt things */
5352 intel_dp->compliance.test_active = true;
5357 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5359 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5360 u8 test_result = DP_TEST_ACK;
5361 struct intel_connector *intel_connector = intel_dp->attached_connector;
5362 struct drm_connector *connector = &intel_connector->base;
5364 if (intel_connector->detect_edid == NULL ||
5365 connector->edid_corrupt ||
5366 intel_dp->aux.i2c_defer_count > 6) {
5367 /* Check EDID read for NACKs, DEFERs and corruption
5368 * (DP CTS 1.2 Core r1.1)
5369 * 4.2.2.4 : Failed EDID read, I2C_NAK
5370 * 4.2.2.5 : Failed EDID read, I2C_DEFER
5371 * 4.2.2.6 : EDID corruption detected
5372 * Use failsafe mode for all cases
5374 if (intel_dp->aux.i2c_nack_count > 0 ||
5375 intel_dp->aux.i2c_defer_count > 0)
5376 drm_dbg_kms(&i915->drm,
5377 "EDID read had %d NACKs, %d DEFERs\n",
5378 intel_dp->aux.i2c_nack_count,
5379 intel_dp->aux.i2c_defer_count);
5380 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5382 struct edid *block = intel_connector->detect_edid;
5384 /* We have to write the checksum
5385 * of the last block read
5387 block += intel_connector->detect_edid->extensions;
5389 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5390 block->checksum) <= 0)
5391 drm_dbg_kms(&i915->drm,
5392 "Failed to write EDID checksum\n");
5394 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5395 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5398 /* Set test active flag here so userspace doesn't interrupt things */
5399 intel_dp->compliance.test_active = true;
5404 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5406 u8 test_result = DP_TEST_NAK;
5410 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5412 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5413 u8 response = DP_TEST_NAK;
5417 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5419 drm_dbg_kms(&i915->drm,
5420 "Could not read test request from sink\n");
5425 case DP_TEST_LINK_TRAINING:
5426 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5427 response = intel_dp_autotest_link_training(intel_dp);
5429 case DP_TEST_LINK_VIDEO_PATTERN:
5430 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5431 response = intel_dp_autotest_video_pattern(intel_dp);
5433 case DP_TEST_LINK_EDID_READ:
5434 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5435 response = intel_dp_autotest_edid(intel_dp);
5437 case DP_TEST_LINK_PHY_TEST_PATTERN:
5438 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5439 response = intel_dp_autotest_phy_pattern(intel_dp);
5442 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5447 if (response & DP_TEST_ACK)
5448 intel_dp->compliance.test_type = request;
5451 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5453 drm_dbg_kms(&i915->drm,
5454 "Could not write test response to sink\n");
5458 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5460 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5463 if (intel_dp->is_mst) {
5464 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
5469 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5470 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5474 /* check link status - esi[10] = 0x200c */
5475 if (intel_dp->active_mst_links > 0 &&
5476 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5477 drm_dbg_kms(&i915->drm,
5478 "channel EQ not ok, retraining\n");
5479 intel_dp_start_link_train(intel_dp);
5480 intel_dp_stop_link_train(intel_dp);
5483 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5484 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5487 for (retry = 0; retry < 3; retry++) {
5489 wret = drm_dp_dpcd_write(&intel_dp->aux,
5490 DP_SINK_COUNT_ESI+1,
5497 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5499 drm_dbg_kms(&i915->drm,
5500 "got esi2 %3ph\n", esi);
5508 drm_dbg_kms(&i915->drm,
5509 "failed to get ESI - device may have failed\n");
5510 intel_dp->is_mst = false;
5511 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5519 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5521 u8 link_status[DP_LINK_STATUS_SIZE];
5523 if (!intel_dp->link_trained)
5527 * While PSR source HW is enabled, it will control main-link sending
5528 * frames, enabling and disabling it so trying to do a retrain will fail
5529 * as the link would or not be on or it could mix training patterns
5530 * and frame data at the same time causing retrain to fail.
5531 * Also when exiting PSR, HW will retrain the link anyways fixing
5532 * any link status error.
5534 if (intel_psr_enabled(intel_dp))
5537 if (!intel_dp_get_link_status(intel_dp, link_status))
5541 * Validate the cached values of intel_dp->link_rate and
5542 * intel_dp->lane_count before attempting to retrain.
5544 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5545 intel_dp->lane_count))
5548 /* Retrain if Channel EQ or CR not ok */
5549 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5552 int intel_dp_retrain_link(struct intel_encoder *encoder,
5553 struct drm_modeset_acquire_ctx *ctx)
5555 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5556 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5557 struct intel_connector *connector = intel_dp->attached_connector;
5558 struct drm_connector_state *conn_state;
5559 struct intel_crtc_state *crtc_state;
5560 struct intel_crtc *crtc;
5563 /* FIXME handle the MST connectors as well */
5565 if (!connector || connector->base.status != connector_status_connected)
5568 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5573 conn_state = connector->base.state;
5575 crtc = to_intel_crtc(conn_state->crtc);
5579 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5583 crtc_state = to_intel_crtc_state(crtc->base.state);
5585 drm_WARN_ON(&dev_priv->drm, !intel_crtc_has_dp_encoder(crtc_state));
5587 if (!crtc_state->hw.active)
5590 if (conn_state->commit &&
5591 !try_wait_for_completion(&conn_state->commit->hw_done))
5594 if (!intel_dp_needs_link_retrain(intel_dp))
5597 /* Suppress underruns caused by re-training */
5598 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5599 if (crtc_state->has_pch_encoder)
5600 intel_set_pch_fifo_underrun_reporting(dev_priv,
5601 intel_crtc_pch_transcoder(crtc), false);
5603 intel_dp_start_link_train(intel_dp);
5604 intel_dp_stop_link_train(intel_dp);
5606 /* Keep underrun reporting disabled until things are stable */
5607 intel_wait_for_vblank(dev_priv, crtc->pipe);
5609 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5610 if (crtc_state->has_pch_encoder)
5611 intel_set_pch_fifo_underrun_reporting(dev_priv,
5612 intel_crtc_pch_transcoder(crtc), true);
5618 * If display is now connected check links status,
5619 * there has been known issues of link loss triggering
5622 * Some sinks (eg. ASUS PB287Q) seem to perform some
5623 * weird HPD ping pong during modesets. So we can apparently
5624 * end up with HPD going low during a modeset, and then
5625 * going back up soon after. And once that happens we must
5626 * retrain the link to get a picture. That's in case no
5627 * userspace component reacted to intermittent HPD dip.
5629 static enum intel_hotplug_state
5630 intel_dp_hotplug(struct intel_encoder *encoder,
5631 struct intel_connector *connector)
5633 struct drm_modeset_acquire_ctx ctx;
5634 enum intel_hotplug_state state;
5637 state = intel_encoder_hotplug(encoder, connector);
5639 drm_modeset_acquire_init(&ctx, 0);
5642 ret = intel_dp_retrain_link(encoder, &ctx);
5644 if (ret == -EDEADLK) {
5645 drm_modeset_backoff(&ctx);
5652 drm_modeset_drop_locks(&ctx);
5653 drm_modeset_acquire_fini(&ctx);
5654 drm_WARN(encoder->base.dev, ret,
5655 "Acquiring modeset locks failed with %i\n", ret);
5658 * Keeping it consistent with intel_ddi_hotplug() and
5659 * intel_hdmi_hotplug().
5661 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5662 state = INTEL_HOTPLUG_RETRY;
5667 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5669 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5672 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5675 if (drm_dp_dpcd_readb(&intel_dp->aux,
5676 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5679 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5681 if (val & DP_AUTOMATED_TEST_REQUEST)
5682 intel_dp_handle_test_request(intel_dp);
5684 if (val & DP_CP_IRQ)
5685 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5687 if (val & DP_SINK_SPECIFIC_IRQ)
5688 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5692 * According to DP spec
5695 * 2. Configure link according to Receiver Capabilities
5696 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5697 * 4. Check link status on receipt of hot-plug interrupt
5699 * intel_dp_short_pulse - handles short pulse interrupts
5700 * when full detection is not required.
5701 * Returns %true if short pulse is handled and full detection
5702 * is NOT required and %false otherwise.
5705 intel_dp_short_pulse(struct intel_dp *intel_dp)
5707 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5708 u8 old_sink_count = intel_dp->sink_count;
5712 * Clearing compliance test variables to allow capturing
5713 * of values for next automated test request.
5715 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5718 * Now read the DPCD to see if it's actually running
5719 * If the current value of sink count doesn't match with
5720 * the value that was stored earlier or dpcd read failed
5721 * we need to do full detection
5723 ret = intel_dp_get_dpcd(intel_dp);
5725 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5726 /* No need to proceed if we are going to do full detect */
5730 intel_dp_check_service_irq(intel_dp);
5732 /* Handle CEC interrupts, if any */
5733 drm_dp_cec_irq(&intel_dp->aux);
5735 /* defer to the hotplug work for link retraining if needed */
5736 if (intel_dp_needs_link_retrain(intel_dp))
5739 intel_psr_short_pulse(intel_dp);
5741 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5742 drm_dbg_kms(&dev_priv->drm,
5743 "Link Training Compliance Test requested\n");
5744 /* Send a Hotplug Uevent to userspace to start modeset */
5745 drm_kms_helper_hotplug_event(&dev_priv->drm);
5751 /* XXX this is probably wrong for multiple downstream ports */
5752 static enum drm_connector_status
5753 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5755 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5756 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5757 u8 *dpcd = intel_dp->dpcd;
5760 if (WARN_ON(intel_dp_is_edp(intel_dp)))
5761 return connector_status_connected;
5764 lspcon_resume(lspcon);
5766 if (!intel_dp_get_dpcd(intel_dp))
5767 return connector_status_disconnected;
5769 /* if there's no downstream port, we're done */
5770 if (!drm_dp_is_branch(dpcd))
5771 return connector_status_connected;
5773 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5774 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5775 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5777 return intel_dp->sink_count ?
5778 connector_status_connected : connector_status_disconnected;
5781 if (intel_dp_can_mst(intel_dp))
5782 return connector_status_connected;
5784 /* If no HPD, poke DDC gently */
5785 if (drm_probe_ddc(&intel_dp->aux.ddc))
5786 return connector_status_connected;
5788 /* Well we tried, say unknown for unreliable port types */
5789 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5790 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5791 if (type == DP_DS_PORT_TYPE_VGA ||
5792 type == DP_DS_PORT_TYPE_NON_EDID)
5793 return connector_status_unknown;
5795 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5796 DP_DWN_STRM_PORT_TYPE_MASK;
5797 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5798 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5799 return connector_status_unknown;
5802 /* Anything else is out of spec, warn and ignore */
5803 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5804 return connector_status_disconnected;
5807 static enum drm_connector_status
5808 edp_detect(struct intel_dp *intel_dp)
5810 return connector_status_connected;
5813 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5818 switch (encoder->hpd_pin) {
5820 bit = SDE_PORTB_HOTPLUG;
5823 bit = SDE_PORTC_HOTPLUG;
5826 bit = SDE_PORTD_HOTPLUG;
5829 MISSING_CASE(encoder->hpd_pin);
5833 return intel_de_read(dev_priv, SDEISR) & bit;
5836 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5838 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5841 switch (encoder->hpd_pin) {
5843 bit = SDE_PORTB_HOTPLUG_CPT;
5846 bit = SDE_PORTC_HOTPLUG_CPT;
5849 bit = SDE_PORTD_HOTPLUG_CPT;
5852 MISSING_CASE(encoder->hpd_pin);
5856 return intel_de_read(dev_priv, SDEISR) & bit;
5859 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5864 switch (encoder->hpd_pin) {
5866 bit = SDE_PORTA_HOTPLUG_SPT;
5869 bit = SDE_PORTE_HOTPLUG_SPT;
5872 return cpt_digital_port_connected(encoder);
5875 return intel_de_read(dev_priv, SDEISR) & bit;
5878 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5880 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5883 switch (encoder->hpd_pin) {
5885 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5888 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5891 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5894 MISSING_CASE(encoder->hpd_pin);
5898 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5901 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5903 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5906 switch (encoder->hpd_pin) {
5908 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5911 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5914 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5917 MISSING_CASE(encoder->hpd_pin);
5921 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5924 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5926 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5928 if (encoder->hpd_pin == HPD_PORT_A)
5929 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
5931 return ibx_digital_port_connected(encoder);
5934 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5938 if (encoder->hpd_pin == HPD_PORT_A)
5939 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
5941 return cpt_digital_port_connected(encoder);
5944 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5946 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5948 if (encoder->hpd_pin == HPD_PORT_A)
5949 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
5951 return cpt_digital_port_connected(encoder);
5954 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5958 if (encoder->hpd_pin == HPD_PORT_A)
5959 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5961 return cpt_digital_port_connected(encoder);
5964 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5966 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5969 switch (encoder->hpd_pin) {
5971 bit = BXT_DE_PORT_HP_DDIA;
5974 bit = BXT_DE_PORT_HP_DDIB;
5977 bit = BXT_DE_PORT_HP_DDIC;
5980 MISSING_CASE(encoder->hpd_pin);
5984 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
5987 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
5990 if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
5991 return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
5993 return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
5996 static bool icp_digital_port_connected(struct intel_encoder *encoder)
5998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5999 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6000 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
6002 if (intel_phy_is_combo(dev_priv, phy))
6003 return intel_combo_phy_connected(dev_priv, phy);
6004 else if (intel_phy_is_tc(dev_priv, phy))
6005 return intel_tc_port_connected(dig_port);
6007 MISSING_CASE(encoder->hpd_pin);
6013 * intel_digital_port_connected - is the specified port connected?
6014 * @encoder: intel_encoder
6016 * In cases where there's a connector physically connected but it can't be used
6017 * by our hardware we also return false, since the rest of the driver should
6018 * pretty much treat the port as disconnected. This is relevant for type-C
6019 * (starting on ICL) where there's ownership involved.
6021 * Return %true if port is connected, %false otherwise.
6023 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
6025 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6027 if (HAS_GMCH(dev_priv)) {
6028 if (IS_GM45(dev_priv))
6029 return gm45_digital_port_connected(encoder);
6031 return g4x_digital_port_connected(encoder);
6034 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
6035 return icp_digital_port_connected(encoder);
6036 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
6037 return spt_digital_port_connected(encoder);
6038 else if (IS_GEN9_LP(dev_priv))
6039 return bxt_digital_port_connected(encoder);
6040 else if (IS_GEN(dev_priv, 8))
6041 return bdw_digital_port_connected(encoder);
6042 else if (IS_GEN(dev_priv, 7))
6043 return ivb_digital_port_connected(encoder);
6044 else if (IS_GEN(dev_priv, 6))
6045 return snb_digital_port_connected(encoder);
6046 else if (IS_GEN(dev_priv, 5))
6047 return ilk_digital_port_connected(encoder);
6049 MISSING_CASE(INTEL_GEN(dev_priv));
6053 bool intel_digital_port_connected(struct intel_encoder *encoder)
6055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6056 bool is_connected = false;
6057 intel_wakeref_t wakeref;
6059 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6060 is_connected = __intel_digital_port_connected(encoder);
6062 return is_connected;
6065 static struct edid *
6066 intel_dp_get_edid(struct intel_dp *intel_dp)
6068 struct intel_connector *intel_connector = intel_dp->attached_connector;
6070 /* use cached edid if we have one */
6071 if (intel_connector->edid) {
6073 if (IS_ERR(intel_connector->edid))
6076 return drm_edid_duplicate(intel_connector->edid);
6078 return drm_get_edid(&intel_connector->base,
6079 &intel_dp->aux.ddc);
6083 intel_dp_set_edid(struct intel_dp *intel_dp)
6085 struct intel_connector *intel_connector = intel_dp->attached_connector;
6088 intel_dp_unset_edid(intel_dp);
6089 edid = intel_dp_get_edid(intel_dp);
6090 intel_connector->detect_edid = edid;
6092 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6093 drm_dp_cec_set_edid(&intel_dp->aux, edid);
6094 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6098 intel_dp_unset_edid(struct intel_dp *intel_dp)
6100 struct intel_connector *intel_connector = intel_dp->attached_connector;
6102 drm_dp_cec_unset_edid(&intel_dp->aux);
6103 kfree(intel_connector->detect_edid);
6104 intel_connector->detect_edid = NULL;
6106 intel_dp->has_audio = false;
6107 intel_dp->edid_quirks = 0;
6111 intel_dp_detect(struct drm_connector *connector,
6112 struct drm_modeset_acquire_ctx *ctx,
6115 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6116 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6117 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6118 struct intel_encoder *encoder = &dig_port->base;
6119 enum drm_connector_status status;
6121 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6122 connector->base.id, connector->name);
6123 drm_WARN_ON(&dev_priv->drm,
6124 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6126 /* Can't disconnect eDP */
6127 if (intel_dp_is_edp(intel_dp))
6128 status = edp_detect(intel_dp);
6129 else if (intel_digital_port_connected(encoder))
6130 status = intel_dp_detect_dpcd(intel_dp);
6132 status = connector_status_disconnected;
6134 if (status == connector_status_disconnected) {
6135 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6136 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6138 if (intel_dp->is_mst) {
6139 drm_dbg_kms(&dev_priv->drm,
6140 "MST device may have disappeared %d vs %d\n",
6142 intel_dp->mst_mgr.mst_state);
6143 intel_dp->is_mst = false;
6144 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6151 if (intel_dp->reset_link_params) {
6152 /* Initial max link lane count */
6153 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6155 /* Initial max link rate */
6156 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6158 intel_dp->reset_link_params = false;
6161 intel_dp_print_rates(intel_dp);
6163 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6164 if (INTEL_GEN(dev_priv) >= 11)
6165 intel_dp_get_dsc_sink_cap(intel_dp);
6167 intel_dp_configure_mst(intel_dp);
6169 if (intel_dp->is_mst) {
6171 * If we are in MST mode then this connector
6172 * won't appear connected or have anything
6175 status = connector_status_disconnected;
6180 * Some external monitors do not signal loss of link synchronization
6181 * with an IRQ_HPD, so force a link status check.
6183 if (!intel_dp_is_edp(intel_dp)) {
6186 ret = intel_dp_retrain_link(encoder, ctx);
6192 * Clearing NACK and defer counts to get their exact values
6193 * while reading EDID which are required by Compliance tests
6194 * 4.2.2.4 and 4.2.2.5
6196 intel_dp->aux.i2c_nack_count = 0;
6197 intel_dp->aux.i2c_defer_count = 0;
6199 intel_dp_set_edid(intel_dp);
6200 if (intel_dp_is_edp(intel_dp) ||
6201 to_intel_connector(connector)->detect_edid)
6202 status = connector_status_connected;
6204 intel_dp_check_service_irq(intel_dp);
6207 if (status != connector_status_connected && !intel_dp->is_mst)
6208 intel_dp_unset_edid(intel_dp);
6211 * Make sure the refs for power wells enabled during detect are
6212 * dropped to avoid a new detect cycle triggered by HPD polling.
6214 intel_display_power_flush_work(dev_priv);
6220 intel_dp_force(struct drm_connector *connector)
6222 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6223 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6224 struct intel_encoder *intel_encoder = &dig_port->base;
6225 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6226 enum intel_display_power_domain aux_domain =
6227 intel_aux_power_domain(dig_port);
6228 intel_wakeref_t wakeref;
6230 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6231 connector->base.id, connector->name);
6232 intel_dp_unset_edid(intel_dp);
6234 if (connector->status != connector_status_connected)
6237 wakeref = intel_display_power_get(dev_priv, aux_domain);
6239 intel_dp_set_edid(intel_dp);
6241 intel_display_power_put(dev_priv, aux_domain, wakeref);
6244 static int intel_dp_get_modes(struct drm_connector *connector)
6246 struct intel_connector *intel_connector = to_intel_connector(connector);
6249 edid = intel_connector->detect_edid;
6251 int ret = intel_connector_update_modes(connector, edid);
6256 /* if eDP has no EDID, fall back to fixed mode */
6257 if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6258 intel_connector->panel.fixed_mode) {
6259 struct drm_display_mode *mode;
6261 mode = drm_mode_duplicate(connector->dev,
6262 intel_connector->panel.fixed_mode);
6264 drm_mode_probed_add(connector, mode);
6273 intel_dp_connector_register(struct drm_connector *connector)
6275 struct drm_i915_private *i915 = to_i915(connector->dev);
6276 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6279 ret = intel_connector_register(connector);
6283 intel_connector_debugfs_add(connector);
6285 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6286 intel_dp->aux.name, connector->kdev->kobj.name);
6288 intel_dp->aux.dev = connector->kdev;
6289 ret = drm_dp_aux_register(&intel_dp->aux);
6291 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6296 intel_dp_connector_unregister(struct drm_connector *connector)
6298 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6300 drm_dp_cec_unregister_connector(&intel_dp->aux);
6301 drm_dp_aux_unregister(&intel_dp->aux);
6302 intel_connector_unregister(connector);
6305 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6307 struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6308 struct intel_dp *intel_dp = &intel_dig_port->dp;
6310 intel_dp_mst_encoder_cleanup(intel_dig_port);
6311 if (intel_dp_is_edp(intel_dp)) {
6312 intel_wakeref_t wakeref;
6314 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6316 * vdd might still be enabled do to the delayed vdd off.
6317 * Make sure vdd is actually turned off here.
6319 with_pps_lock(intel_dp, wakeref)
6320 edp_panel_vdd_off_sync(intel_dp);
6322 if (intel_dp->edp_notifier.notifier_call) {
6323 unregister_reboot_notifier(&intel_dp->edp_notifier);
6324 intel_dp->edp_notifier.notifier_call = NULL;
6328 intel_dp_aux_fini(intel_dp);
6331 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6333 intel_dp_encoder_flush_work(encoder);
6335 drm_encoder_cleanup(encoder);
6336 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6339 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6341 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6342 intel_wakeref_t wakeref;
6344 if (!intel_dp_is_edp(intel_dp))
6348 * vdd might still be enabled do to the delayed vdd off.
6349 * Make sure vdd is actually turned off here.
6351 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6352 with_pps_lock(intel_dp, wakeref)
6353 edp_panel_vdd_off_sync(intel_dp);
6356 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
6360 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
6361 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
6362 msecs_to_jiffies(timeout));
6365 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
6369 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
6372 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6373 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
6374 static const struct drm_dp_aux_msg msg = {
6375 .request = DP_AUX_NATIVE_WRITE,
6376 .address = DP_AUX_HDCP_AKSV,
6377 .size = DRM_HDCP_KSV_LEN,
6379 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
6383 /* Output An first, that's easy */
6384 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
6385 an, DRM_HDCP_AN_LEN);
6386 if (dpcd_ret != DRM_HDCP_AN_LEN) {
6387 drm_dbg_kms(&i915->drm,
6388 "Failed to write An over DP/AUX (%zd)\n",
6390 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
6394 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
6395 * order to get it on the wire, we need to create the AUX header as if
6396 * we were writing the data, and then tickle the hardware to output the
6397 * data once the header is sent out.
6399 intel_dp_aux_header(txbuf, &msg);
6401 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
6402 rxbuf, sizeof(rxbuf),
6403 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
6405 drm_dbg_kms(&i915->drm,
6406 "Write Aksv over DP/AUX failed (%d)\n", ret);
6408 } else if (ret == 0) {
6409 drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n");
6413 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
6414 if (reply != DP_AUX_NATIVE_REPLY_ACK) {
6415 drm_dbg_kms(&i915->drm,
6416 "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
6423 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
6426 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6429 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
6431 if (ret != DRM_HDCP_KSV_LEN) {
6432 drm_dbg_kms(&i915->drm,
6433 "Read Bksv from DP/AUX failed (%zd)\n", ret);
6434 return ret >= 0 ? -EIO : ret;
6439 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6442 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6446 * For some reason the HDMI and DP HDCP specs call this register
6447 * definition by different names. In the HDMI spec, it's called BSTATUS,
6448 * but in DP it's called BINFO.
6450 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6451 bstatus, DRM_HDCP_BSTATUS_LEN);
6452 if (ret != DRM_HDCP_BSTATUS_LEN) {
6453 drm_dbg_kms(&i915->drm,
6454 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6455 return ret >= 0 ? -EIO : ret;
6461 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6464 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6467 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6470 drm_dbg_kms(&i915->drm,
6471 "Read bcaps from DP/AUX failed (%zd)\n", ret);
6472 return ret >= 0 ? -EIO : ret;
6479 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6480 bool *repeater_present)
6485 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6489 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6494 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6497 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6500 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6501 ri_prime, DRM_HDCP_RI_LEN);
6502 if (ret != DRM_HDCP_RI_LEN) {
6503 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
6505 return ret >= 0 ? -EIO : ret;
6511 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6514 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6518 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6521 drm_dbg_kms(&i915->drm,
6522 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6523 return ret >= 0 ? -EIO : ret;
6525 *ksv_ready = bstatus & DP_BSTATUS_READY;
6530 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6531 int num_downstream, u8 *ksv_fifo)
6533 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6537 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6538 for (i = 0; i < num_downstream; i += 3) {
6539 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6540 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6541 DP_AUX_HDCP_KSV_FIFO,
6542 ksv_fifo + i * DRM_HDCP_KSV_LEN,
6545 drm_dbg_kms(&i915->drm,
6546 "Read ksv[%d] from DP/AUX failed (%zd)\n",
6548 return ret >= 0 ? -EIO : ret;
6555 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6558 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6561 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6564 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6565 DP_AUX_HDCP_V_PRIME(i), part,
6566 DRM_HDCP_V_PRIME_PART_LEN);
6567 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6568 drm_dbg_kms(&i915->drm,
6569 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6570 return ret >= 0 ? -EIO : ret;
6576 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6579 /* Not used for single stream DisplayPort setups */
6584 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6586 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6590 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6593 drm_dbg_kms(&i915->drm,
6594 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6598 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6602 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6608 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6612 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6616 struct hdcp2_dp_errata_stream_type {
6621 struct hdcp2_dp_msg_data {
6624 bool msg_detectable;
6626 u32 timeout2; /* Added for non_paired situation */
6629 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6630 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6631 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6632 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6633 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6635 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6637 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6638 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6639 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6640 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6641 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6642 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6643 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6644 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6645 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6646 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6648 { HDCP_2_2_REP_SEND_RECVID_LIST,
6649 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6650 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6651 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6653 { HDCP_2_2_REP_STREAM_MANAGE,
6654 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6656 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6657 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6658 /* local define to shovel this through the write_2_2 interface */
6659 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
6660 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6661 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6666 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6669 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6672 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6673 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6674 HDCP_2_2_DP_RXSTATUS_LEN);
6675 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6676 drm_dbg_kms(&i915->drm,
6677 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6678 return ret >= 0 ? -EIO : ret;
6685 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6686 u8 msg_id, bool *msg_ready)
6692 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6697 case HDCP_2_2_AKE_SEND_HPRIME:
6698 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6701 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6702 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6705 case HDCP_2_2_REP_SEND_RECVID_LIST:
6706 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6710 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6718 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6719 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6721 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6722 struct intel_dp *dp = &intel_dig_port->dp;
6723 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6724 u8 msg_id = hdcp2_msg_data->msg_id;
6726 bool msg_ready = false;
6728 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6729 timeout = hdcp2_msg_data->timeout2;
6731 timeout = hdcp2_msg_data->timeout;
6734 * There is no way to detect the CERT, LPRIME and STREAM_READY
6735 * availability. So Wait for timeout and read the msg.
6737 if (!hdcp2_msg_data->msg_detectable) {
6742 * As we want to check the msg availability at timeout, Ignoring
6743 * the timeout at wait for CP_IRQ.
6745 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6746 ret = hdcp2_detect_msg_availability(intel_dig_port,
6747 msg_id, &msg_ready);
6753 drm_dbg_kms(&i915->drm,
6754 "msg_id %d, ret %d, timeout(mSec): %d\n",
6755 hdcp2_msg_data->msg_id, ret, timeout);
6760 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6764 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6765 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6766 return &hdcp2_dp_msg_data[i];
6772 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6773 void *buf, size_t size)
6775 struct intel_dp *dp = &intel_dig_port->dp;
6776 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6777 unsigned int offset;
6779 ssize_t ret, bytes_to_write, len;
6780 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6782 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6783 if (!hdcp2_msg_data)
6786 offset = hdcp2_msg_data->offset;
6788 /* No msg_id in DP HDCP2.2 msgs */
6789 bytes_to_write = size - 1;
6792 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6794 while (bytes_to_write) {
6795 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6796 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6798 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6799 offset, (void *)byte, len);
6803 bytes_to_write -= ret;
6812 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6814 u8 rx_info[HDCP_2_2_RXINFO_LEN];
6818 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6819 DP_HDCP_2_2_REG_RXINFO_OFFSET,
6820 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6821 if (ret != HDCP_2_2_RXINFO_LEN)
6822 return ret >= 0 ? -EIO : ret;
6824 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6825 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6827 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6828 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6830 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6831 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6832 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6838 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6839 u8 msg_id, void *buf, size_t size)
6841 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6842 unsigned int offset;
6844 ssize_t ret, bytes_to_recv, len;
6845 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6847 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6848 if (!hdcp2_msg_data)
6850 offset = hdcp2_msg_data->offset;
6852 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6856 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6857 ret = get_receiver_id_list_size(intel_dig_port);
6863 bytes_to_recv = size - 1;
6865 /* DP adaptation msgs has no msg_id */
6868 while (bytes_to_recv) {
6869 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6870 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6872 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6875 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
6880 bytes_to_recv -= ret;
6891 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6892 bool is_repeater, u8 content_type)
6895 struct hdcp2_dp_errata_stream_type stream_type_msg;
6901 * Errata for DP: As Stream type is used for encryption, Receiver
6902 * should be communicated with stream type for the decryption of the
6904 * Repeater will be communicated with stream type as a part of it's
6905 * auth later in time.
6907 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6908 stream_type_msg.stream_type = content_type;
6910 ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6911 sizeof(stream_type_msg));
6913 return ret < 0 ? ret : 0;
6918 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6923 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6927 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6928 ret = HDCP_REAUTH_REQUEST;
6929 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6930 ret = HDCP_LINK_INTEGRITY_FAILURE;
6931 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6932 ret = HDCP_TOPOLOGY_CHANGE;
6938 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6945 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6946 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6947 rx_caps, HDCP_2_2_RXCAPS_LEN);
6948 if (ret != HDCP_2_2_RXCAPS_LEN)
6949 return ret >= 0 ? -EIO : ret;
6951 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6952 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6958 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6959 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6960 .read_bksv = intel_dp_hdcp_read_bksv,
6961 .read_bstatus = intel_dp_hdcp_read_bstatus,
6962 .repeater_present = intel_dp_hdcp_repeater_present,
6963 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6964 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6965 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6966 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6967 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6968 .check_link = intel_dp_hdcp_check_link,
6969 .hdcp_capable = intel_dp_hdcp_capable,
6970 .write_2_2_msg = intel_dp_hdcp2_write_msg,
6971 .read_2_2_msg = intel_dp_hdcp2_read_msg,
6972 .config_stream_type = intel_dp_hdcp2_config_stream_type,
6973 .check_2_2_link = intel_dp_hdcp2_check_link,
6974 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6975 .protocol = HDCP_PROTOCOL_DP,
6978 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6980 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6983 lockdep_assert_held(&dev_priv->pps_mutex);
6985 if (!edp_have_panel_vdd(intel_dp))
6989 * The VDD bit needs a power domain reference, so if the bit is
6990 * already enabled when we boot or resume, grab this reference and
6991 * schedule a vdd off, so we don't hold on to the reference
6994 drm_dbg_kms(&dev_priv->drm,
6995 "VDD left on by BIOS, adjusting state tracking\n");
6996 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6998 edp_panel_vdd_schedule_off(intel_dp);
7001 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7003 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7004 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7007 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7008 encoder->port, &pipe))
7011 return INVALID_PIPE;
7014 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7016 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7017 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7018 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
7019 intel_wakeref_t wakeref;
7021 if (!HAS_DDI(dev_priv))
7022 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7025 lspcon_resume(lspcon);
7027 intel_dp->reset_link_params = true;
7029 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7030 !intel_dp_is_edp(intel_dp))
7033 with_pps_lock(intel_dp, wakeref) {
7034 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7035 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7037 if (intel_dp_is_edp(intel_dp)) {
7039 * Reinit the power sequencer, in case BIOS did
7040 * something nasty with it.
7042 intel_dp_pps_init(intel_dp);
7043 intel_edp_panel_vdd_sanitize(intel_dp);
7048 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7051 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7052 struct drm_connector_list_iter conn_iter;
7053 struct drm_connector *connector;
7056 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7057 drm_for_each_connector_iter(connector, &conn_iter) {
7058 struct drm_connector_state *conn_state;
7059 struct intel_crtc_state *crtc_state;
7060 struct intel_crtc *crtc;
7062 if (!connector->has_tile ||
7063 connector->tile_group->id != tile_group_id)
7066 conn_state = drm_atomic_get_connector_state(&state->base,
7068 if (IS_ERR(conn_state)) {
7069 ret = PTR_ERR(conn_state);
7073 crtc = to_intel_crtc(conn_state->crtc);
7078 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7079 crtc_state->uapi.mode_changed = true;
7081 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7085 drm_connector_list_iter_end(&conn_iter);
7090 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7092 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7093 struct intel_crtc *crtc;
7095 if (transcoders == 0)
7098 for_each_intel_crtc(&dev_priv->drm, crtc) {
7099 struct intel_crtc_state *crtc_state;
7102 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7103 if (IS_ERR(crtc_state))
7104 return PTR_ERR(crtc_state);
7106 if (!crtc_state->hw.enable)
7109 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7112 crtc_state->uapi.mode_changed = true;
7114 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7118 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7122 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7125 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7130 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7131 struct drm_connector *connector)
7133 const struct drm_connector_state *old_conn_state =
7134 drm_atomic_get_old_connector_state(&state->base, connector);
7135 const struct intel_crtc_state *old_crtc_state;
7136 struct intel_crtc *crtc;
7139 crtc = to_intel_crtc(old_conn_state->crtc);
7143 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7145 if (!old_crtc_state->hw.active)
7148 transcoders = old_crtc_state->sync_mode_slaves_mask;
7149 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7150 transcoders |= BIT(old_crtc_state->master_transcoder);
7152 return intel_modeset_affected_transcoders(state,
7156 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7157 struct drm_atomic_state *_state)
7159 struct drm_i915_private *dev_priv = to_i915(conn->dev);
7160 struct intel_atomic_state *state = to_intel_atomic_state(_state);
7163 ret = intel_digital_connector_atomic_check(conn, &state->base);
7168 * We don't enable port sync on BDW due to missing w/as and
7169 * due to not having adjusted the modeset sequence appropriately.
7171 if (INTEL_GEN(dev_priv) < 9)
7174 if (!intel_connector_needs_modeset(state, conn))
7177 if (conn->has_tile) {
7178 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7183 return intel_modeset_synced_crtcs(state, conn);
7186 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7187 .force = intel_dp_force,
7188 .fill_modes = drm_helper_probe_single_connector_modes,
7189 .atomic_get_property = intel_digital_connector_atomic_get_property,
7190 .atomic_set_property = intel_digital_connector_atomic_set_property,
7191 .late_register = intel_dp_connector_register,
7192 .early_unregister = intel_dp_connector_unregister,
7193 .destroy = intel_connector_destroy,
7194 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7195 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7198 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7199 .detect_ctx = intel_dp_detect,
7200 .get_modes = intel_dp_get_modes,
7201 .mode_valid = intel_dp_mode_valid,
7202 .atomic_check = intel_dp_connector_atomic_check,
7205 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7206 .reset = intel_dp_encoder_reset,
7207 .destroy = intel_dp_encoder_destroy,
7210 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7212 intel_wakeref_t wakeref;
7213 bool have_power = false;
7215 with_pps_lock(intel_dp, wakeref) {
7216 have_power = edp_have_panel_power(intel_dp) &&
7217 edp_have_panel_vdd(intel_dp);
7224 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
7226 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7227 struct intel_dp *intel_dp = &intel_dig_port->dp;
7229 if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
7230 (long_hpd || !intel_edp_have_power(intel_dp))) {
7232 * vdd off can generate a long/short pulse on eDP which
7233 * would require vdd on to handle it, and thus we
7234 * would end up in an endless cycle of
7235 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7237 drm_dbg_kms(&i915->drm,
7238 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7239 long_hpd ? "long" : "short",
7240 intel_dig_port->base.base.base.id,
7241 intel_dig_port->base.base.name);
7245 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7246 intel_dig_port->base.base.base.id,
7247 intel_dig_port->base.base.name,
7248 long_hpd ? "long" : "short");
7251 intel_dp->reset_link_params = true;
7255 if (intel_dp->is_mst) {
7256 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
7258 * If we were in MST mode, and device is not
7259 * there, get out of MST mode
7261 drm_dbg_kms(&i915->drm,
7262 "MST device may have disappeared %d vs %d\n",
7264 intel_dp->mst_mgr.mst_state);
7265 intel_dp->is_mst = false;
7266 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7273 if (!intel_dp->is_mst) {
7276 handled = intel_dp_short_pulse(intel_dp);
7285 /* check the VBT to see whether the eDP is on another port */
7286 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7289 * eDP not supported on g4x. so bail out early just
7290 * for a bit extra safety in case the VBT is bonkers.
7292 if (INTEL_GEN(dev_priv) < 5)
7295 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7298 return intel_bios_is_port_edp(dev_priv, port);
7302 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7304 struct drm_i915_private *dev_priv = to_i915(connector->dev);
7305 enum port port = dp_to_dig_port(intel_dp)->base.port;
7307 if (!IS_G4X(dev_priv) && port != PORT_A)
7308 intel_attach_force_audio_property(connector);
7310 intel_attach_broadcast_rgb_property(connector);
7311 if (HAS_GMCH(dev_priv))
7312 drm_connector_attach_max_bpc_property(connector, 6, 10);
7313 else if (INTEL_GEN(dev_priv) >= 5)
7314 drm_connector_attach_max_bpc_property(connector, 6, 12);
7316 intel_attach_colorspace_property(connector);
7318 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7319 drm_object_attach_property(&connector->base,
7320 connector->dev->mode_config.hdr_output_metadata_property,
7323 if (intel_dp_is_edp(intel_dp)) {
7324 u32 allowed_scalers;
7326 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7327 if (!HAS_GMCH(dev_priv))
7328 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7330 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7332 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7337 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7339 intel_dp->panel_power_off_time = ktime_get_boottime();
7340 intel_dp->last_power_on = jiffies;
7341 intel_dp->last_backlight_off = jiffies;
7345 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7347 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7348 u32 pp_on, pp_off, pp_ctl;
7349 struct pps_registers regs;
7351 intel_pps_get_registers(intel_dp, ®s);
7353 pp_ctl = ilk_get_pp_control(intel_dp);
7355 /* Ensure PPS is unlocked */
7356 if (!HAS_DDI(dev_priv))
7357 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7359 pp_on = intel_de_read(dev_priv, regs.pp_on);
7360 pp_off = intel_de_read(dev_priv, regs.pp_off);
7362 /* Pull timing values out of registers */
7363 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7364 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7365 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7366 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7368 if (i915_mmio_reg_valid(regs.pp_div)) {
7371 pp_div = intel_de_read(dev_priv, regs.pp_div);
7373 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7375 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7380 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7382 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7384 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7388 intel_pps_verify_state(struct intel_dp *intel_dp)
7390 struct edp_power_seq hw;
7391 struct edp_power_seq *sw = &intel_dp->pps_delays;
7393 intel_pps_readout_hw_state(intel_dp, &hw);
7395 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7396 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7397 DRM_ERROR("PPS state mismatch\n");
7398 intel_pps_dump_state("sw", sw);
7399 intel_pps_dump_state("hw", &hw);
7404 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7406 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7407 struct edp_power_seq cur, vbt, spec,
7408 *final = &intel_dp->pps_delays;
7410 lockdep_assert_held(&dev_priv->pps_mutex);
7412 /* already initialized? */
7413 if (final->t11_t12 != 0)
7416 intel_pps_readout_hw_state(intel_dp, &cur);
7418 intel_pps_dump_state("cur", &cur);
7420 vbt = dev_priv->vbt.edp.pps;
7421 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7422 * of 500ms appears to be too short. Ocassionally the panel
7423 * just fails to power back on. Increasing the delay to 800ms
7424 * seems sufficient to avoid this problem.
7426 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7427 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7428 drm_dbg_kms(&dev_priv->drm,
7429 "Increasing T12 panel delay as per the quirk to %d\n",
7432 /* T11_T12 delay is special and actually in units of 100ms, but zero
7433 * based in the hw (so we need to add 100 ms). But the sw vbt
7434 * table multiplies it with 1000 to make it in units of 100usec,
7436 vbt.t11_t12 += 100 * 10;
7438 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7439 * our hw here, which are all in 100usec. */
7440 spec.t1_t3 = 210 * 10;
7441 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7442 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7443 spec.t10 = 500 * 10;
7444 /* This one is special and actually in units of 100ms, but zero
7445 * based in the hw (so we need to add 100 ms). But the sw vbt
7446 * table multiplies it with 1000 to make it in units of 100usec,
7448 spec.t11_t12 = (510 + 100) * 10;
7450 intel_pps_dump_state("vbt", &vbt);
7452 /* Use the max of the register settings and vbt. If both are
7453 * unset, fall back to the spec limits. */
7454 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
7456 max(cur.field, vbt.field))
7457 assign_final(t1_t3);
7461 assign_final(t11_t12);
7464 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
7465 intel_dp->panel_power_up_delay = get_delay(t1_t3);
7466 intel_dp->backlight_on_delay = get_delay(t8);
7467 intel_dp->backlight_off_delay = get_delay(t9);
7468 intel_dp->panel_power_down_delay = get_delay(t10);
7469 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7472 drm_dbg_kms(&dev_priv->drm,
7473 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7474 intel_dp->panel_power_up_delay,
7475 intel_dp->panel_power_down_delay,
7476 intel_dp->panel_power_cycle_delay);
7478 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7479 intel_dp->backlight_on_delay,
7480 intel_dp->backlight_off_delay);
7483 * We override the HW backlight delays to 1 because we do manual waits
7484 * on them. For T8, even BSpec recommends doing it. For T9, if we
7485 * don't do this, we'll end up waiting for the backlight off delay
7486 * twice: once when we do the manual sleep, and once when we disable
7487 * the panel and wait for the PP_STATUS bit to become zero.
7493 * HW has only a 100msec granularity for t11_t12 so round it up
7496 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7500 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7501 bool force_disable_vdd)
7503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7504 u32 pp_on, pp_off, port_sel = 0;
7505 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7506 struct pps_registers regs;
7507 enum port port = dp_to_dig_port(intel_dp)->base.port;
7508 const struct edp_power_seq *seq = &intel_dp->pps_delays;
7510 lockdep_assert_held(&dev_priv->pps_mutex);
7512 intel_pps_get_registers(intel_dp, ®s);
7515 * On some VLV machines the BIOS can leave the VDD
7516 * enabled even on power sequencers which aren't
7517 * hooked up to any port. This would mess up the
7518 * power domain tracking the first time we pick
7519 * one of these power sequencers for use since
7520 * edp_panel_vdd_on() would notice that the VDD was
7521 * already on and therefore wouldn't grab the power
7522 * domain reference. Disable VDD first to avoid this.
7523 * This also avoids spuriously turning the VDD on as
7524 * soon as the new power sequencer gets initialized.
7526 if (force_disable_vdd) {
7527 u32 pp = ilk_get_pp_control(intel_dp);
7529 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7530 "Panel power already on\n");
7532 if (pp & EDP_FORCE_VDD)
7533 drm_dbg_kms(&dev_priv->drm,
7534 "VDD already on, disabling first\n");
7536 pp &= ~EDP_FORCE_VDD;
7538 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7541 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7542 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7543 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7544 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7546 /* Haswell doesn't have any port selection bits for the panel
7547 * power sequencer any more. */
7548 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7549 port_sel = PANEL_PORT_SELECT_VLV(port);
7550 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7553 port_sel = PANEL_PORT_SELECT_DPA;
7556 port_sel = PANEL_PORT_SELECT_DPC;
7559 port_sel = PANEL_PORT_SELECT_DPD;
7569 intel_de_write(dev_priv, regs.pp_on, pp_on);
7570 intel_de_write(dev_priv, regs.pp_off, pp_off);
7573 * Compute the divisor for the pp clock, simply match the Bspec formula.
7575 if (i915_mmio_reg_valid(regs.pp_div)) {
7576 intel_de_write(dev_priv, regs.pp_div,
7577 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7581 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7582 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7583 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7584 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7587 drm_dbg_kms(&dev_priv->drm,
7588 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7589 intel_de_read(dev_priv, regs.pp_on),
7590 intel_de_read(dev_priv, regs.pp_off),
7591 i915_mmio_reg_valid(regs.pp_div) ?
7592 intel_de_read(dev_priv, regs.pp_div) :
7593 (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7596 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7598 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7600 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7601 vlv_initial_power_sequencer_setup(intel_dp);
7603 intel_dp_init_panel_power_sequencer(intel_dp);
7604 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7609 * intel_dp_set_drrs_state - program registers for RR switch to take effect
7610 * @dev_priv: i915 device
7611 * @crtc_state: a pointer to the active intel_crtc_state
7612 * @refresh_rate: RR to be programmed
7614 * This function gets called when refresh rate (RR) has to be changed from
7615 * one frequency to another. Switches can be between high and low RR
7616 * supported by the panel or to any other RR based on media playback (in
7617 * this case, RR value needs to be passed from user space).
7619 * The caller of this function needs to take a lock on dev_priv->drrs.
7621 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7622 const struct intel_crtc_state *crtc_state,
7625 struct intel_dp *intel_dp = dev_priv->drrs.dp;
7626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7627 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7629 if (refresh_rate <= 0) {
7630 drm_dbg_kms(&dev_priv->drm,
7631 "Refresh rate should be positive non-zero.\n");
7635 if (intel_dp == NULL) {
7636 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7641 drm_dbg_kms(&dev_priv->drm,
7642 "DRRS: intel_crtc not initialized\n");
7646 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7647 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7651 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7653 index = DRRS_LOW_RR;
7655 if (index == dev_priv->drrs.refresh_rate_type) {
7656 drm_dbg_kms(&dev_priv->drm,
7657 "DRRS requested for previously set RR...ignoring\n");
7661 if (!crtc_state->hw.active) {
7662 drm_dbg_kms(&dev_priv->drm,
7663 "eDP encoder disabled. CRTC not Active\n");
7667 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7670 intel_dp_set_m_n(crtc_state, M1_N1);
7673 intel_dp_set_m_n(crtc_state, M2_N2);
7677 drm_err(&dev_priv->drm,
7678 "Unsupported refreshrate type\n");
7680 } else if (INTEL_GEN(dev_priv) > 6) {
7681 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7684 val = intel_de_read(dev_priv, reg);
7685 if (index > DRRS_HIGH_RR) {
7686 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7687 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7689 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7691 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7692 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7694 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7696 intel_de_write(dev_priv, reg, val);
7699 dev_priv->drrs.refresh_rate_type = index;
7701 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7706 * intel_edp_drrs_enable - init drrs struct if supported
7707 * @intel_dp: DP struct
7708 * @crtc_state: A pointer to the active crtc state.
7710 * Initializes frontbuffer_bits and drrs.dp
7712 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7713 const struct intel_crtc_state *crtc_state)
7715 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7717 if (!crtc_state->has_drrs) {
7718 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7722 if (dev_priv->psr.enabled) {
7723 drm_dbg_kms(&dev_priv->drm,
7724 "PSR enabled. Not enabling DRRS.\n");
7728 mutex_lock(&dev_priv->drrs.mutex);
7729 if (dev_priv->drrs.dp) {
7730 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7734 dev_priv->drrs.busy_frontbuffer_bits = 0;
7736 dev_priv->drrs.dp = intel_dp;
7739 mutex_unlock(&dev_priv->drrs.mutex);
7743 * intel_edp_drrs_disable - Disable DRRS
7744 * @intel_dp: DP struct
7745 * @old_crtc_state: Pointer to old crtc_state.
7748 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7749 const struct intel_crtc_state *old_crtc_state)
7751 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7753 if (!old_crtc_state->has_drrs)
7756 mutex_lock(&dev_priv->drrs.mutex);
7757 if (!dev_priv->drrs.dp) {
7758 mutex_unlock(&dev_priv->drrs.mutex);
7762 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7763 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7764 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7766 dev_priv->drrs.dp = NULL;
7767 mutex_unlock(&dev_priv->drrs.mutex);
7769 cancel_delayed_work_sync(&dev_priv->drrs.work);
7772 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7774 struct drm_i915_private *dev_priv =
7775 container_of(work, typeof(*dev_priv), drrs.work.work);
7776 struct intel_dp *intel_dp;
7778 mutex_lock(&dev_priv->drrs.mutex);
7780 intel_dp = dev_priv->drrs.dp;
7786 * The delayed work can race with an invalidate hence we need to
7790 if (dev_priv->drrs.busy_frontbuffer_bits)
7793 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7794 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7796 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7797 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7801 mutex_unlock(&dev_priv->drrs.mutex);
7805 * intel_edp_drrs_invalidate - Disable Idleness DRRS
7806 * @dev_priv: i915 device
7807 * @frontbuffer_bits: frontbuffer plane tracking bits
7809 * This function gets called everytime rendering on the given planes start.
7810 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7812 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7814 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7815 unsigned int frontbuffer_bits)
7817 struct drm_crtc *crtc;
7820 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7823 cancel_delayed_work(&dev_priv->drrs.work);
7825 mutex_lock(&dev_priv->drrs.mutex);
7826 if (!dev_priv->drrs.dp) {
7827 mutex_unlock(&dev_priv->drrs.mutex);
7831 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7832 pipe = to_intel_crtc(crtc)->pipe;
7834 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7835 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7837 /* invalidate means busy screen hence upclock */
7838 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7839 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7840 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7842 mutex_unlock(&dev_priv->drrs.mutex);
7846 * intel_edp_drrs_flush - Restart Idleness DRRS
7847 * @dev_priv: i915 device
7848 * @frontbuffer_bits: frontbuffer plane tracking bits
7850 * This function gets called every time rendering on the given planes has
7851 * completed or flip on a crtc is completed. So DRRS should be upclocked
7852 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7853 * if no other planes are dirty.
7855 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7857 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7858 unsigned int frontbuffer_bits)
7860 struct drm_crtc *crtc;
7863 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7866 cancel_delayed_work(&dev_priv->drrs.work);
7868 mutex_lock(&dev_priv->drrs.mutex);
7869 if (!dev_priv->drrs.dp) {
7870 mutex_unlock(&dev_priv->drrs.mutex);
7874 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7875 pipe = to_intel_crtc(crtc)->pipe;
7877 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7878 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7880 /* flush means busy screen hence upclock */
7881 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7882 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7883 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7886 * flush also means no more activity hence schedule downclock, if all
7887 * other fbs are quiescent too
7889 if (!dev_priv->drrs.busy_frontbuffer_bits)
7890 schedule_delayed_work(&dev_priv->drrs.work,
7891 msecs_to_jiffies(1000));
7892 mutex_unlock(&dev_priv->drrs.mutex);
7896 * DOC: Display Refresh Rate Switching (DRRS)
7898 * Display Refresh Rate Switching (DRRS) is a power conservation feature
7899 * which enables swtching between low and high refresh rates,
7900 * dynamically, based on the usage scenario. This feature is applicable
7901 * for internal panels.
7903 * Indication that the panel supports DRRS is given by the panel EDID, which
7904 * would list multiple refresh rates for one resolution.
7906 * DRRS is of 2 types - static and seamless.
7907 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7908 * (may appear as a blink on screen) and is used in dock-undock scenario.
7909 * Seamless DRRS involves changing RR without any visual effect to the user
7910 * and can be used during normal system usage. This is done by programming
7911 * certain registers.
7913 * Support for static/seamless DRRS may be indicated in the VBT based on
7914 * inputs from the panel spec.
7916 * DRRS saves power by switching to low RR based on usage scenarios.
7918 * The implementation is based on frontbuffer tracking implementation. When
7919 * there is a disturbance on the screen triggered by user activity or a periodic
7920 * system activity, DRRS is disabled (RR is changed to high RR). When there is
7921 * no movement on screen, after a timeout of 1 second, a switch to low RR is
7924 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7925 * and intel_edp_drrs_flush() are called.
7927 * DRRS can be further extended to support other internal panels and also
7928 * the scenario of video playback wherein RR is set based on the rate
7929 * requested by userspace.
7933 * intel_dp_drrs_init - Init basic DRRS work and mutex.
7934 * @connector: eDP connector
7935 * @fixed_mode: preferred mode of panel
7937 * This function is called only once at driver load to initialize basic
7941 * Downclock mode if panel supports it, else return NULL.
7942 * DRRS support is determined by the presence of downclock mode (apart
7943 * from VBT setting).
7945 static struct drm_display_mode *
7946 intel_dp_drrs_init(struct intel_connector *connector,
7947 struct drm_display_mode *fixed_mode)
7949 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7950 struct drm_display_mode *downclock_mode = NULL;
7952 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7953 mutex_init(&dev_priv->drrs.mutex);
7955 if (INTEL_GEN(dev_priv) <= 6) {
7956 drm_dbg_kms(&dev_priv->drm,
7957 "DRRS supported for Gen7 and above\n");
7961 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7962 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
7966 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7967 if (!downclock_mode) {
7968 drm_dbg_kms(&dev_priv->drm,
7969 "Downclock mode is not found. DRRS not supported\n");
7973 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7975 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7976 drm_dbg_kms(&dev_priv->drm,
7977 "seamless DRRS supported for eDP panel.\n");
7978 return downclock_mode;
7981 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7982 struct intel_connector *intel_connector)
7984 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7985 struct drm_device *dev = &dev_priv->drm;
7986 struct drm_connector *connector = &intel_connector->base;
7987 struct drm_display_mode *fixed_mode = NULL;
7988 struct drm_display_mode *downclock_mode = NULL;
7990 enum pipe pipe = INVALID_PIPE;
7991 intel_wakeref_t wakeref;
7994 if (!intel_dp_is_edp(intel_dp))
7997 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8000 * On IBX/CPT we may get here with LVDS already registered. Since the
8001 * driver uses the only internal power sequencer available for both
8002 * eDP and LVDS bail out early in this case to prevent interfering
8003 * with an already powered-on LVDS power sequencer.
8005 if (intel_get_lvds_encoder(dev_priv)) {
8007 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8008 drm_info(&dev_priv->drm,
8009 "LVDS was detected, not registering eDP\n");
8014 with_pps_lock(intel_dp, wakeref) {
8015 intel_dp_init_panel_power_timestamps(intel_dp);
8016 intel_dp_pps_init(intel_dp);
8017 intel_edp_panel_vdd_sanitize(intel_dp);
8020 /* Cache DPCD and EDID for edp. */
8021 has_dpcd = intel_edp_init_dpcd(intel_dp);
8024 /* if this fails, presume the device is a ghost */
8025 drm_info(&dev_priv->drm,
8026 "failed to retrieve link info, disabling eDP\n");
8030 mutex_lock(&dev->mode_config.mutex);
8031 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8033 if (drm_add_edid_modes(connector, edid)) {
8034 drm_connector_update_edid_property(connector, edid);
8035 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8038 edid = ERR_PTR(-EINVAL);
8041 edid = ERR_PTR(-ENOENT);
8043 intel_connector->edid = edid;
8045 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8047 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8049 /* fallback to VBT if available for eDP */
8051 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8052 mutex_unlock(&dev->mode_config.mutex);
8054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8055 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
8056 register_reboot_notifier(&intel_dp->edp_notifier);
8059 * Figure out the current pipe for the initial backlight setup.
8060 * If the current pipe isn't valid, try the PPS pipe, and if that
8061 * fails just assume pipe A.
8063 pipe = vlv_active_pipe(intel_dp);
8065 if (pipe != PIPE_A && pipe != PIPE_B)
8066 pipe = intel_dp->pps_pipe;
8068 if (pipe != PIPE_A && pipe != PIPE_B)
8071 drm_dbg_kms(&dev_priv->drm,
8072 "using pipe %c for initial backlight setup\n",
8076 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8077 intel_connector->panel.backlight.power = intel_edp_backlight_power;
8078 intel_panel_setup_backlight(connector, pipe);
8081 drm_connector_set_panel_orientation_with_quirk(connector,
8082 dev_priv->vbt.orientation,
8083 fixed_mode->hdisplay, fixed_mode->vdisplay);
8089 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8091 * vdd might still be enabled do to the delayed vdd off.
8092 * Make sure vdd is actually turned off here.
8094 with_pps_lock(intel_dp, wakeref)
8095 edp_panel_vdd_off_sync(intel_dp);
8100 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8102 struct intel_connector *intel_connector;
8103 struct drm_connector *connector;
8105 intel_connector = container_of(work, typeof(*intel_connector),
8106 modeset_retry_work);
8107 connector = &intel_connector->base;
8108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8111 /* Grab the locks before changing connector property*/
8112 mutex_lock(&connector->dev->mode_config.mutex);
8113 /* Set connector link status to BAD and send a Uevent to notify
8114 * userspace to do a modeset.
8116 drm_connector_set_link_status_property(connector,
8117 DRM_MODE_LINK_STATUS_BAD);
8118 mutex_unlock(&connector->dev->mode_config.mutex);
8119 /* Send Hotplug uevent so userspace can reprobe */
8120 drm_kms_helper_hotplug_event(connector->dev);
8124 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
8125 struct intel_connector *intel_connector)
8127 struct drm_connector *connector = &intel_connector->base;
8128 struct intel_dp *intel_dp = &intel_dig_port->dp;
8129 struct intel_encoder *intel_encoder = &intel_dig_port->base;
8130 struct drm_device *dev = intel_encoder->base.dev;
8131 struct drm_i915_private *dev_priv = to_i915(dev);
8132 enum port port = intel_encoder->port;
8133 enum phy phy = intel_port_to_phy(dev_priv, port);
8136 /* Initialize the work for modeset in case of link train failure */
8137 INIT_WORK(&intel_connector->modeset_retry_work,
8138 intel_dp_modeset_retry_work_fn);
8140 if (drm_WARN(dev, intel_dig_port->max_lanes < 1,
8141 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8142 intel_dig_port->max_lanes, intel_encoder->base.base.id,
8143 intel_encoder->base.name))
8146 intel_dp_set_source_rates(intel_dp);
8148 intel_dp->reset_link_params = true;
8149 intel_dp->pps_pipe = INVALID_PIPE;
8150 intel_dp->active_pipe = INVALID_PIPE;
8152 /* Preserve the current hw state. */
8153 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8154 intel_dp->attached_connector = intel_connector;
8156 if (intel_dp_is_port_edp(dev_priv, port)) {
8158 * Currently we don't support eDP on TypeC ports, although in
8159 * theory it could work on TypeC legacy ports.
8161 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8162 type = DRM_MODE_CONNECTOR_eDP;
8164 type = DRM_MODE_CONNECTOR_DisplayPort;
8167 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8168 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8171 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8172 * for DP the encoder type can be set by the caller to
8173 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8175 if (type == DRM_MODE_CONNECTOR_eDP)
8176 intel_encoder->type = INTEL_OUTPUT_EDP;
8178 /* eDP only on port B and/or C on vlv/chv */
8179 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8180 IS_CHERRYVIEW(dev_priv)) &&
8181 intel_dp_is_edp(intel_dp) &&
8182 port != PORT_B && port != PORT_C))
8185 drm_dbg_kms(&dev_priv->drm,
8186 "Adding %s connector on [ENCODER:%d:%s]\n",
8187 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8188 intel_encoder->base.base.id, intel_encoder->base.name);
8190 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8191 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8193 if (!HAS_GMCH(dev_priv))
8194 connector->interlace_allowed = true;
8195 connector->doublescan_allowed = 0;
8197 if (INTEL_GEN(dev_priv) >= 11)
8198 connector->ycbcr_420_allowed = true;
8200 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8201 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8203 intel_dp_aux_init(intel_dp);
8205 intel_connector_attach_encoder(intel_connector, intel_encoder);
8207 if (HAS_DDI(dev_priv))
8208 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8210 intel_connector->get_hw_state = intel_connector_get_hw_state;
8212 /* init MST on ports that can support it */
8213 intel_dp_mst_encoder_init(intel_dig_port,
8214 intel_connector->base.base.id);
8216 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8217 intel_dp_aux_fini(intel_dp);
8218 intel_dp_mst_encoder_cleanup(intel_dig_port);
8222 intel_dp_add_properties(intel_dp, connector);
8224 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8225 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
8227 drm_dbg_kms(&dev_priv->drm,
8228 "HDCP init failed, skipping.\n");
8231 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8232 * 0xd. Failure to do so will result in spurious interrupts being
8233 * generated on the port when a cable is not attached.
8235 if (IS_G45(dev_priv)) {
8236 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8237 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8238 (temp & ~0xf) | 0xd);
8244 drm_connector_cleanup(connector);
8249 bool intel_dp_init(struct drm_i915_private *dev_priv,
8250 i915_reg_t output_reg,
8253 struct intel_digital_port *intel_dig_port;
8254 struct intel_encoder *intel_encoder;
8255 struct drm_encoder *encoder;
8256 struct intel_connector *intel_connector;
8258 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
8259 if (!intel_dig_port)
8262 intel_connector = intel_connector_alloc();
8263 if (!intel_connector)
8264 goto err_connector_alloc;
8266 intel_encoder = &intel_dig_port->base;
8267 encoder = &intel_encoder->base;
8269 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8270 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8271 "DP %c", port_name(port)))
8272 goto err_encoder_init;
8274 intel_encoder->hotplug = intel_dp_hotplug;
8275 intel_encoder->compute_config = intel_dp_compute_config;
8276 intel_encoder->get_hw_state = intel_dp_get_hw_state;
8277 intel_encoder->get_config = intel_dp_get_config;
8278 intel_encoder->update_pipe = intel_panel_update_backlight;
8279 intel_encoder->suspend = intel_dp_encoder_suspend;
8280 if (IS_CHERRYVIEW(dev_priv)) {
8281 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8282 intel_encoder->pre_enable = chv_pre_enable_dp;
8283 intel_encoder->enable = vlv_enable_dp;
8284 intel_encoder->disable = vlv_disable_dp;
8285 intel_encoder->post_disable = chv_post_disable_dp;
8286 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8287 } else if (IS_VALLEYVIEW(dev_priv)) {
8288 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8289 intel_encoder->pre_enable = vlv_pre_enable_dp;
8290 intel_encoder->enable = vlv_enable_dp;
8291 intel_encoder->disable = vlv_disable_dp;
8292 intel_encoder->post_disable = vlv_post_disable_dp;
8294 intel_encoder->pre_enable = g4x_pre_enable_dp;
8295 intel_encoder->enable = g4x_enable_dp;
8296 intel_encoder->disable = g4x_disable_dp;
8297 intel_encoder->post_disable = g4x_post_disable_dp;
8300 intel_dig_port->dp.output_reg = output_reg;
8301 intel_dig_port->max_lanes = 4;
8303 intel_encoder->type = INTEL_OUTPUT_DP;
8304 intel_encoder->power_domain = intel_port_to_power_domain(port);
8305 if (IS_CHERRYVIEW(dev_priv)) {
8307 intel_encoder->pipe_mask = BIT(PIPE_C);
8309 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8311 intel_encoder->pipe_mask = ~0;
8313 intel_encoder->cloneable = 0;
8314 intel_encoder->port = port;
8316 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
8319 intel_infoframe_init(intel_dig_port);
8321 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8322 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
8323 goto err_init_connector;
8328 drm_encoder_cleanup(encoder);
8330 kfree(intel_connector);
8331 err_connector_alloc:
8332 kfree(intel_dig_port);
8336 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8338 struct intel_encoder *encoder;
8340 for_each_intel_encoder(&dev_priv->drm, encoder) {
8341 struct intel_dp *intel_dp;
8343 if (encoder->type != INTEL_OUTPUT_DDI)
8346 intel_dp = enc_to_intel_dp(encoder);
8348 if (!intel_dp->can_mst)
8351 if (intel_dp->is_mst)
8352 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8356 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8358 struct intel_encoder *encoder;
8360 for_each_intel_encoder(&dev_priv->drm, encoder) {
8361 struct intel_dp *intel_dp;
8364 if (encoder->type != INTEL_OUTPUT_DDI)
8367 intel_dp = enc_to_intel_dp(encoder);
8369 if (!intel_dp->can_mst)
8372 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8375 intel_dp->is_mst = false;
8376 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,