drivers/gpu/drm/i915/display/intel_display.h

   1 /*
   2  * Copyright © 2006-2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29 #include <drm/i915_drm.h>
  30
  31 enum link_m_n_set;
  32 struct dpll;
  33 struct drm_connector;
  34 struct drm_device;
  35 struct drm_display_mode;
  36 struct drm_encoder;
  37 struct drm_file;
  38 struct drm_format_info;
  39 struct drm_framebuffer;
  40 struct drm_i915_error_state_buf;
  41 struct drm_i915_gem_object;
  42 struct drm_i915_private;
  43 struct drm_modeset_acquire_ctx;
  44 struct drm_plane;
  45 struct drm_plane_state;
  46 struct i915_ggtt_view;
  47 struct intel_crtc;
  48 struct intel_crtc_state;
  49 struct intel_digital_port;
  50 struct intel_dp;
  51 struct intel_encoder;
  52 struct intel_load_detect_pipe;
  53 struct intel_plane;
  54 struct intel_plane_state;
  55 struct intel_remapped_info;
  56 struct intel_rotation_info;
  57 struct intel_crtc_state;
  58
  59 enum i915_gpio {
  60         GPIOA,
  61         GPIOB,
  62         GPIOC,
  63         GPIOD,
  64         GPIOE,
  65         GPIOF,
  66         GPIOG,
  67         GPIOH,
  68         __GPIOI_UNUSED,
  69         GPIOJ,
  70         GPIOK,
  71         GPIOL,
  72         GPIOM,
  73         GPION,
  74         GPIOO,
  75 };
  76
  77 /*
  78  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  79  * rest have consecutive values and match the enum values of transcoders
  80  * with a 1:1 transcoder -> pipe mapping.
  81  */
  82 enum pipe {
  83         INVALID_PIPE = -1,
  84
  85         PIPE_A = 0,
  86         PIPE_B,
  87         PIPE_C,
  88         PIPE_D,
  89         _PIPE_EDP,
  90
  91         I915_MAX_PIPES = _PIPE_EDP
  92 };
  93
  94 #define pipe_name(p) ((p) + 'A')
  95
  96 enum transcoder {
  97         INVALID_TRANSCODER = -1,
  98         /*
  99          * The following transcoders have a 1:1 transcoder -> pipe mapping,
 100          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
 101          * rest have consecutive values and match the enum values of the pipes
 102          * they map to.
 103          */
 104         TRANSCODER_A = PIPE_A,
 105         TRANSCODER_B = PIPE_B,
 106         TRANSCODER_C = PIPE_C,
 107         TRANSCODER_D = PIPE_D,
 108
 109         /*
 110          * The following transcoders can map to any pipe, their enum value
 111          * doesn't need to stay fixed.
 112          */
 113         TRANSCODER_EDP,
 114         TRANSCODER_DSI_0,
 115         TRANSCODER_DSI_1,
 116         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
 117         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
 118
 119         I915_MAX_TRANSCODERS
 120 };
 121
 122 static inline const char *transcoder_name(enum transcoder transcoder)
 123 {
 124         switch (transcoder) {
 125         case TRANSCODER_A:
 126                 return "A";
 127         case TRANSCODER_B:
 128                 return "B";
 129         case TRANSCODER_C:
 130                 return "C";
 131         case TRANSCODER_D:
 132                 return "D";
 133         case TRANSCODER_EDP:
 134                 return "EDP";
 135         case TRANSCODER_DSI_A:
 136                 return "DSI A";
 137         case TRANSCODER_DSI_C:
 138                 return "DSI C";
 139         default:
 140                 return "<invalid>";
 141         }
 142 }
 143
 144 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 145 {
 146         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 147 }
 148
 149 /*
 150  * Global legacy plane identifier. Valid only for primary/sprite
 151  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 152  */
 153 enum i9xx_plane_id {
 154         PLANE_A,
 155         PLANE_B,
 156         PLANE_C,
 157 };
 158
 159 #define plane_name(p) ((p) + 'A')
 160 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 161
 162 /*
 163  * Per-pipe plane identifier.
 164  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 165  * number of planes per CRTC.  Not all platforms really have this many planes,
 166  * which means some arrays of size I915_MAX_PLANES may have unused entries
 167  * between the topmost sprite plane and the cursor plane.
 168  *
 169  * This is expected to be passed to various register macros
 170  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 171  */
 172 enum plane_id {
 173         PLANE_PRIMARY,
 174         PLANE_SPRITE0,
 175         PLANE_SPRITE1,
 176         PLANE_SPRITE2,
 177         PLANE_SPRITE3,
 178         PLANE_SPRITE4,
 179         PLANE_SPRITE5,
 180         PLANE_CURSOR,
 181
 182         I915_MAX_PLANES,
 183 };
 184
 185 #define for_each_plane_id_on_crtc(__crtc, __p) \
 186         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 187                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 188
 189 enum port {
 190         PORT_NONE = -1,
 191
 192         PORT_A = 0,
 193         PORT_B,
 194         PORT_C,
 195         PORT_D,
 196         PORT_E,
 197         PORT_F,
 198         PORT_G,
 199         PORT_H,
 200         PORT_I,
 201
 202         I915_MAX_PORTS
 203 };
 204
 205 #define port_name(p) ((p) + 'A')
 206
 207 /*
 208  * Ports identifier referenced from other drivers.
 209  * Expected to remain stable over time
 210  */
 211 static inline const char *port_identifier(enum port port)
 212 {
 213         switch (port) {
 214         case PORT_A:
 215                 return "Port A";
 216         case PORT_B:
 217                 return "Port B";
 218         case PORT_C:
 219                 return "Port C";
 220         case PORT_D:
 221                 return "Port D";
 222         case PORT_E:
 223                 return "Port E";
 224         case PORT_F:
 225                 return "Port F";
 226         case PORT_G:
 227                 return "Port G";
 228         case PORT_H:
 229                 return "Port H";
 230         case PORT_I:
 231                 return "Port I";
 232         default:
 233                 return "<invalid>";
 234         }
 235 }
 236
 237 enum tc_port {
 238         PORT_TC_NONE = -1,
 239
 240         PORT_TC1 = 0,
 241         PORT_TC2,
 242         PORT_TC3,
 243         PORT_TC4,
 244         PORT_TC5,
 245         PORT_TC6,
 246
 247         I915_MAX_TC_PORTS
 248 };
 249
 250 enum tc_port_mode {
 251         TC_PORT_TBT_ALT,
 252         TC_PORT_DP_ALT,
 253         TC_PORT_LEGACY,
 254 };
 255
 256 enum dpio_channel {
 257         DPIO_CH0,
 258         DPIO_CH1
 259 };
 260
 261 enum dpio_phy {
 262         DPIO_PHY0,
 263         DPIO_PHY1,
 264         DPIO_PHY2,
 265 };
 266
 267 #define I915_NUM_PHYS_VLV 2
 268
 269 enum aux_ch {
 270         AUX_CH_A,
 271         AUX_CH_B,
 272         AUX_CH_C,
 273         AUX_CH_D,
 274         AUX_CH_E, /* ICL+ */
 275         AUX_CH_F,
 276         AUX_CH_G,
 277 };
 278
 279 #define aux_ch_name(a) ((a) + 'A')
 280
 281 /* Used by dp and fdi links */
 282 struct intel_link_m_n {
 283         u32 tu;
 284         u32 gmch_m;
 285         u32 gmch_n;
 286         u32 link_m;
 287         u32 link_n;
 288 };
 289
 290 enum phy {
 291         PHY_NONE = -1,
 292
 293         PHY_A = 0,
 294         PHY_B,
 295         PHY_C,
 296         PHY_D,
 297         PHY_E,
 298         PHY_F,
 299         PHY_G,
 300         PHY_H,
 301         PHY_I,
 302
 303         I915_MAX_PHYS
 304 };
 305
 306 #define phy_name(a) ((a) + 'A')
 307
 308 enum phy_fia {
 309         FIA1,
 310         FIA2,
 311         FIA3,
 312 };
 313
 314 #define for_each_pipe(__dev_priv, __p) \
 315         for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
 316
 317 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 318         for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
 319                 for_each_if((__mask) & BIT(__p))
 320
 321 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 322         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 323                 for_each_if ((__mask) & (1 << (__t)))
 324
 325 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 326         for ((__p) = 0;                                                 \
 327              (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;       \
 328              (__p)++)
 329
 330 #define for_each_sprite(__dev_priv, __p, __s)                           \
 331         for ((__s) = 0;                                                 \
 332              (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 333              (__s)++)
 334
 335 #define for_each_port(__port) \
 336         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
 337
 338 #define for_each_port_masked(__port, __ports_mask)                      \
 339         for_each_port(__port)                                           \
 340                 for_each_if((__ports_mask) & BIT(__port))
 341
 342 #define for_each_phy_masked(__phy, __phys_mask) \
 343         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
 344                 for_each_if((__phys_mask) & BIT(__phy))
 345
 346 #define for_each_crtc(dev, crtc) \
 347         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 348
 349 #define for_each_intel_plane(dev, intel_plane) \
 350         list_for_each_entry(intel_plane,                        \
 351                             &(dev)->mode_config.plane_list,     \
 352                             base.head)
 353
 354 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 355         list_for_each_entry(intel_plane,                                \
 356                             &(dev)->mode_config.plane_list,             \
 357                             base.head)                                  \
 358                 for_each_if((plane_mask) &                              \
 359                             drm_plane_mask(&intel_plane->base))
 360
 361 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 362         list_for_each_entry(intel_plane,                                \
 363                             &(dev)->mode_config.plane_list,             \
 364                             base.head)                                  \
 365                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 366
 367 #define for_each_intel_crtc(dev, intel_crtc)                            \
 368         list_for_each_entry(intel_crtc,                                 \
 369                             &(dev)->mode_config.crtc_list,              \
 370                             base.head)
 371
 372 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 373         list_for_each_entry(intel_crtc,                                 \
 374                             &(dev)->mode_config.crtc_list,              \
 375                             base.head)                                  \
 376                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 377
 378 #define for_each_intel_encoder(dev, intel_encoder)              \
 379         list_for_each_entry(intel_encoder,                      \
 380                             &(dev)->mode_config.encoder_list,   \
 381                             base.head)
 382
 383 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
 384         list_for_each_entry(intel_encoder,                              \
 385                             &(dev)->mode_config.encoder_list,           \
 386                             base.head)                                  \
 387                 for_each_if((encoder_mask) &                            \
 388                             drm_encoder_mask(&intel_encoder->base))
 389
 390 #define for_each_intel_dp(dev, intel_encoder)                   \
 391         for_each_intel_encoder(dev, intel_encoder)              \
 392                 for_each_if(intel_encoder_is_dp(intel_encoder))
 393
 394 #define for_each_intel_connector_iter(intel_connector, iter) \
 395         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 396
 397 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 398         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 399                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 400
 401 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 402         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 403                 for_each_if((intel_connector)->base.encoder == (__encoder))
 404
 405 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 406         for ((__i) = 0; \
 407              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 408                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 409                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 410              (__i)++) \
 411                 for_each_if(plane)
 412
 413 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 414         for ((__i) = 0; \
 415              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 416                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 417                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 418              (__i)++) \
 419                 for_each_if(plane)
 420
 421 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 422         for ((__i) = 0; \
 423              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 424                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 425                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 426              (__i)++) \
 427                 for_each_if(crtc)
 428
 429 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 430         for ((__i) = 0; \
 431              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 432                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 433                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 434                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 435              (__i)++) \
 436                 for_each_if(plane)
 437
 438 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 439         for ((__i) = 0; \
 440              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 441                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 442                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 443                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 444              (__i)++) \
 445                 for_each_if(crtc)
 446
 447 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 448         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 449              (__i) >= 0  && \
 450              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 451               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 452               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 453              (__i)--) \
 454                 for_each_if(crtc)
 455
 456 #define intel_atomic_crtc_state_for_each_plane_state( \
 457                   plane, plane_state, \
 458                   crtc_state) \
 459         for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
 460                                 ((crtc_state)->uapi.plane_mask)) \
 461                 for_each_if ((plane_state = \
 462                               to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
 463
 464 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
 465         for ((__i) = 0; \
 466              (__i) < (__state)->base.num_connector; \
 467              (__i)++) \
 468                 for_each_if ((__state)->base.connectors[__i].ptr && \
 469                              ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
 470                              (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
 471
 472 void intel_link_compute_m_n(u16 bpp, int nlanes,
 473                             int pixel_clock, int link_clock,
 474                             struct intel_link_m_n *m_n,
 475                             bool constant_n, bool fec_enable);
 476 bool is_ccs_modifier(u64 modifier);
 477 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 478 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 479                               u32 pixel_format, u64 modifier);
 480 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 481 enum drm_mode_status
 482 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 483                                 const struct drm_display_mode *mode);
 484 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 485 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 486
 487 void intel_plane_destroy(struct drm_plane *plane);
 488 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
 489 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 490 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 491 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
 492 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 493 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 494                       const char *name, u32 reg, int ref_freq);
 495 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 496                            const char *name, u32 reg);
 497 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
 498 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
 499 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 500 unsigned int intel_fb_xy_to_linear(int x, int y,
 501                                    const struct intel_plane_state *state,
 502                                    int plane);
 503 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 504                                    int color_plane, unsigned int height);
 505 void intel_add_fb_offsets(int *x, int *y,
 506                           const struct intel_plane_state *state, int plane);
 507 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 508 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 509 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 510 int intel_display_suspend(struct drm_device *dev);
 511 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 512 void intel_encoder_destroy(struct drm_encoder *encoder);
 513 struct drm_display_mode *
 514 intel_encoder_current_mode(struct intel_encoder *encoder);
 515 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 516 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 517 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 518                               enum port port);
 519 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 520                                       struct drm_file *file_priv);
 521 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
 522 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
 523
 524 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 525 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 526                          struct intel_digital_port *dport,
 527                          unsigned int expected_mask);
 528 int intel_get_load_detect_pipe(struct drm_connector *connector,
 529                                struct intel_load_detect_pipe *old,
 530                                struct drm_modeset_acquire_ctx *ctx);
 531 void intel_release_load_detect_pipe(struct drm_connector *connector,
 532                                     struct intel_load_detect_pipe *old,
 533                                     struct drm_modeset_acquire_ctx *ctx);
 534 struct i915_vma *
 535 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 536                            const struct i915_ggtt_view *view,
 537                            bool uses_fence,
 538                            unsigned long *out_flags);
 539 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
 540 struct drm_framebuffer *
 541 intel_framebuffer_create(struct drm_i915_gem_object *obj,
 542                          struct drm_mode_fb_cmd2 *mode_cmd);
 543 int intel_prepare_plane_fb(struct drm_plane *plane,
 544                            struct drm_plane_state *new_state);
 545 void intel_cleanup_plane_fb(struct drm_plane *plane,
 546                             struct drm_plane_state *old_state);
 547
 548 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 549                                     enum pipe pipe);
 550
 551 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
 552                      const struct dpll *dpll);
 553 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
 554 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
 555 bool intel_fuzzy_clock_check(int clock1, int clock2);
 556
 557 void intel_prepare_reset(struct drm_i915_private *dev_priv);
 558 void intel_finish_reset(struct drm_i915_private *dev_priv);
 559 void intel_dp_get_m_n(struct intel_crtc *crtc,
 560                       struct intel_crtc_state *pipe_config);
 561 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
 562                       enum link_m_n_set m_n);
 563 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 564 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 565                         struct dpll *best_clock);
 566 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
 567
 568 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 569 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
 570 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 571 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 572 enum intel_display_power_domain
 573 intel_aux_power_domain(struct intel_digital_port *dig_port);
 574 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 575                                  struct intel_crtc_state *pipe_config);
 576 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 577                                   struct intel_crtc_state *crtc_state);
 578
 579 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
 580 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
 581 void skylake_scaler_disable(const struct intel_crtc_state *old_crtc_state);
 582 void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 583 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 584                         const struct intel_plane_state *plane_state);
 585 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
 586 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 587                   const struct intel_plane_state *plane_state);
 588 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
 589 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 590                      int plane);
 591 int skl_check_plane_surface(struct intel_plane_state *plane_state);
 592 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
 593 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 594 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
 595                                    u32 pixel_format, u64 modifier,
 596                                    unsigned int rotation);
 597 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
 598
 599 struct intel_display_error_state *
 600 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
 601 void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 602                                      struct intel_display_error_state *error);
 603
 604 /* modesetting */
 605 void intel_modeset_init_hw(struct drm_i915_private *i915);
 606 int intel_modeset_init(struct drm_i915_private *i915);
 607 void intel_modeset_driver_remove(struct drm_i915_private *i915);
 608 void intel_display_resume(struct drm_device *dev);
 609 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 610
 611 /* modesetting asserts */
 612 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 613                            enum pipe pipe);
 614 void assert_pll(struct drm_i915_private *dev_priv,
 615                 enum pipe pipe, bool state);
 616 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 617 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 618 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
 619 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 620 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 621 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 622                        enum pipe pipe, bool state);
 623 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 624 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 625 void assert_pipe(struct drm_i915_private *dev_priv,
 626                  enum transcoder cpu_transcoder, bool state);
 627 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
 628 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
 629
 630 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 631  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 632  * which may not necessarily be a user visible problem.  This will either
 633  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 634  * enable distros and users to tailor their preferred amount of i915 abrt
 635  * spam.
 636  */
 637 #define I915_STATE_WARN(condition, format...) ({                        \
 638         int __ret_warn_on = !!(condition);                              \
 639         if (unlikely(__ret_warn_on))                                    \
 640                 if (!WARN(i915_modparams.verbose_state_checks, format)) \
 641                         DRM_ERROR(format);                              \
 642         unlikely(__ret_warn_on);                                        \
 643 })
 644
 645 #define I915_STATE_WARN_ON(x)                                           \
 646         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 647
 648 #endif