drivers/gpu/drm/i915/display/intel_display.h

   1 /*
   2  * Copyright © 2006-2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29
  30 #include "i915_reg_defs.h"
  31 #include "intel_display_limits.h"
  32
  33 enum drm_scaling_filter;
  34 struct dpll;
  35 struct drm_atomic_state;
  36 struct drm_connector;
  37 struct drm_device;
  38 struct drm_display_mode;
  39 struct drm_encoder;
  40 struct drm_file;
  41 struct drm_format_info;
  42 struct drm_framebuffer;
  43 struct drm_i915_gem_object;
  44 struct drm_i915_private;
  45 struct drm_mode_fb_cmd2;
  46 struct drm_modeset_acquire_ctx;
  47 struct drm_plane;
  48 struct drm_plane_state;
  49 struct i915_address_space;
  50 struct i915_gtt_view;
  51 struct intel_atomic_state;
  52 struct intel_crtc;
  53 struct intel_crtc_state;
  54 struct intel_digital_port;
  55 struct intel_dp;
  56 struct intel_encoder;
  57 struct intel_initial_plane_config;
  58 struct intel_link_m_n;
  59 struct intel_plane;
  60 struct intel_plane_state;
  61 struct intel_power_domain_mask;
  62 struct intel_remapped_info;
  63 struct intel_rotation_info;
  64 struct pci_dev;
  65 struct work_struct;
  66
  67
  68 #define pipe_name(p) ((p) + 'A')
  69
  70 static inline const char *transcoder_name(enum transcoder transcoder)
  71 {
  72         switch (transcoder) {
  73         case TRANSCODER_A:
  74                 return "A";
  75         case TRANSCODER_B:
  76                 return "B";
  77         case TRANSCODER_C:
  78                 return "C";
  79         case TRANSCODER_D:
  80                 return "D";
  81         case TRANSCODER_EDP:
  82                 return "EDP";
  83         case TRANSCODER_DSI_A:
  84                 return "DSI A";
  85         case TRANSCODER_DSI_C:
  86                 return "DSI C";
  87         default:
  88                 return "<invalid>";
  89         }
  90 }
  91
  92 static inline bool transcoder_is_dsi(enum transcoder transcoder)
  93 {
  94         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
  95 }
  96
  97 /*
  98  * Global legacy plane identifier. Valid only for primary/sprite
  99  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 100  */
 101 enum i9xx_plane_id {
 102         PLANE_A,
 103         PLANE_B,
 104         PLANE_C,
 105 };
 106
 107 #define plane_name(p) ((p) + 'A')
 108
 109 #define for_each_plane_id_on_crtc(__crtc, __p) \
 110         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 111                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 112
 113 #define for_each_dbuf_slice(__dev_priv, __slice) \
 114         for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
 115                 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
 116
 117 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
 118         for_each_dbuf_slice((__dev_priv), (__slice)) \
 119                 for_each_if((__mask) & BIT(__slice))
 120
 121 #define port_name(p) ((p) + 'A')
 122
 123 /*
 124  * Ports identifier referenced from other drivers.
 125  * Expected to remain stable over time
 126  */
 127 static inline const char *port_identifier(enum port port)
 128 {
 129         switch (port) {
 130         case PORT_A:
 131                 return "Port A";
 132         case PORT_B:
 133                 return "Port B";
 134         case PORT_C:
 135                 return "Port C";
 136         case PORT_D:
 137                 return "Port D";
 138         case PORT_E:
 139                 return "Port E";
 140         case PORT_F:
 141                 return "Port F";
 142         case PORT_G:
 143                 return "Port G";
 144         case PORT_H:
 145                 return "Port H";
 146         case PORT_I:
 147                 return "Port I";
 148         default:
 149                 return "<invalid>";
 150         }
 151 }
 152
 153 enum tc_port {
 154         TC_PORT_NONE = -1,
 155
 156         TC_PORT_1 = 0,
 157         TC_PORT_2,
 158         TC_PORT_3,
 159         TC_PORT_4,
 160         TC_PORT_5,
 161         TC_PORT_6,
 162
 163         I915_MAX_TC_PORTS
 164 };
 165
 166 enum aux_ch {
 167         AUX_CH_NONE = -1,
 168
 169         AUX_CH_A,
 170         AUX_CH_B,
 171         AUX_CH_C,
 172         AUX_CH_D,
 173         AUX_CH_E, /* ICL+ */
 174         AUX_CH_F,
 175         AUX_CH_G,
 176         AUX_CH_H,
 177         AUX_CH_I,
 178
 179         /* tgl+ */
 180         AUX_CH_USBC1 = AUX_CH_D,
 181         AUX_CH_USBC2,
 182         AUX_CH_USBC3,
 183         AUX_CH_USBC4,
 184         AUX_CH_USBC5,
 185         AUX_CH_USBC6,
 186
 187         /* XE_LPD repositions D/E offsets and bitfields */
 188         AUX_CH_D_XELPD = AUX_CH_USBC5,
 189         AUX_CH_E_XELPD,
 190 };
 191
 192 enum phy {
 193         PHY_NONE = -1,
 194
 195         PHY_A = 0,
 196         PHY_B,
 197         PHY_C,
 198         PHY_D,
 199         PHY_E,
 200         PHY_F,
 201         PHY_G,
 202         PHY_H,
 203         PHY_I,
 204
 205         I915_MAX_PHYS
 206 };
 207
 208 #define phy_name(a) ((a) + 'A')
 209
 210 enum phy_fia {
 211         FIA1,
 212         FIA2,
 213         FIA3,
 214 };
 215
 216 #define for_each_hpd_pin(__pin) \
 217         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 218
 219 #define for_each_pipe(__dev_priv, __p) \
 220         for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
 221                 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
 222
 223 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 224         for_each_pipe(__dev_priv, __p) \
 225                 for_each_if((__mask) & BIT(__p))
 226
 227 #define for_each_cpu_transcoder(__dev_priv, __t) \
 228         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 229                 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
 230
 231 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 232         for_each_cpu_transcoder(__dev_priv, __t) \
 233                 for_each_if ((__mask) & BIT(__t))
 234
 235 #define for_each_sprite(__dev_priv, __p, __s)                           \
 236         for ((__s) = 0;                                                 \
 237              (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 238              (__s)++)
 239
 240 #define for_each_port(__port) \
 241         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
 242
 243 #define for_each_port_masked(__port, __ports_mask)                      \
 244         for_each_port(__port)                                           \
 245                 for_each_if((__ports_mask) & BIT(__port))
 246
 247 #define for_each_phy_masked(__phy, __phys_mask) \
 248         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
 249                 for_each_if((__phys_mask) & BIT(__phy))
 250
 251 #define for_each_crtc(dev, crtc) \
 252         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 253
 254 #define for_each_intel_plane(dev, intel_plane) \
 255         list_for_each_entry(intel_plane,                        \
 256                             &(dev)->mode_config.plane_list,     \
 257                             base.head)
 258
 259 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 260         list_for_each_entry(intel_plane,                                \
 261                             &(dev)->mode_config.plane_list,             \
 262                             base.head)                                  \
 263                 for_each_if((plane_mask) &                              \
 264                             drm_plane_mask(&intel_plane->base))
 265
 266 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 267         list_for_each_entry(intel_plane,                                \
 268                             &(dev)->mode_config.plane_list,             \
 269                             base.head)                                  \
 270                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 271
 272 #define for_each_intel_crtc(dev, intel_crtc)                            \
 273         list_for_each_entry(intel_crtc,                                 \
 274                             &(dev)->mode_config.crtc_list,              \
 275                             base.head)
 276
 277 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask)    \
 278         list_for_each_entry(intel_crtc,                                 \
 279                             &(dev)->mode_config.crtc_list,              \
 280                             base.head)                                  \
 281                 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
 282
 283 #define for_each_intel_encoder(dev, intel_encoder)              \
 284         list_for_each_entry(intel_encoder,                      \
 285                             &(dev)->mode_config.encoder_list,   \
 286                             base.head)
 287
 288 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
 289         list_for_each_entry(intel_encoder,                              \
 290                             &(dev)->mode_config.encoder_list,           \
 291                             base.head)                                  \
 292                 for_each_if((encoder_mask) &                            \
 293                             drm_encoder_mask(&intel_encoder->base))
 294
 295 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
 296         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 297                 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
 298                             intel_encoder_can_psr(intel_encoder))
 299
 300 #define for_each_intel_dp(dev, intel_encoder)                   \
 301         for_each_intel_encoder(dev, intel_encoder)              \
 302                 for_each_if(intel_encoder_is_dp(intel_encoder))
 303
 304 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
 305         for_each_intel_encoder((dev), (intel_encoder)) \
 306                 for_each_if(intel_encoder_can_psr(intel_encoder))
 307
 308 #define for_each_intel_connector_iter(intel_connector, iter) \
 309         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 310
 311 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 312         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 313                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 314
 315 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 316         for ((__i) = 0; \
 317              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 318                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 319                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 320              (__i)++) \
 321                 for_each_if(plane)
 322
 323 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
 324         for ((__i) = 0; \
 325              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 326                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 327                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
 328              (__i)++) \
 329                 for_each_if(crtc)
 330
 331 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 332         for ((__i) = 0; \
 333              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 334                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 335                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 336              (__i)++) \
 337                 for_each_if(plane)
 338
 339 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 340         for ((__i) = 0; \
 341              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 342                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 343                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 344              (__i)++) \
 345                 for_each_if(crtc)
 346
 347 #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \
 348         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 349              (__i) >= 0  && \
 350              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 351               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 352              (__i)--) \
 353                 for_each_if(crtc)
 354
 355 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 356         for ((__i) = 0; \
 357              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 358                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 359                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 360                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 361              (__i)++) \
 362                 for_each_if(plane)
 363
 364 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 365         for ((__i) = 0; \
 366              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 367                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 368                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 369                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 370              (__i)++) \
 371                 for_each_if(crtc)
 372
 373 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 374         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 375              (__i) >= 0  && \
 376              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 377               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 378               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 379              (__i)--) \
 380                 for_each_if(crtc)
 381
 382 #define intel_atomic_crtc_state_for_each_plane_state( \
 383                   plane, plane_state, \
 384                   crtc_state) \
 385         for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
 386                                 ((crtc_state)->uapi.plane_mask)) \
 387                 for_each_if ((plane_state = \
 388                               to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
 389
 390 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
 391         for ((__i) = 0; \
 392              (__i) < (__state)->base.num_connector; \
 393              (__i)++) \
 394                 for_each_if ((__state)->base.connectors[__i].ptr && \
 395                              ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
 396                              (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
 397
 398 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
 399 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
 400                                      struct intel_crtc *crtc);
 401 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 402                            u8 active_pipes);
 403 void intel_link_compute_m_n(u16 bpp, int nlanes,
 404                             int pixel_clock, int link_clock,
 405                             int bw_overhead,
 406                             struct intel_link_m_n *m_n);
 407 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 408                               u32 pixel_format, u64 modifier);
 409 enum drm_mode_status
 410 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 411                                 const struct drm_display_mode *mode,
 412                                 bool bigjoiner);
 413 enum drm_mode_status
 414 intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
 415                                 const struct drm_display_mode *mode);
 416 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 417 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 418 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
 419 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
 420 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
 421 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
 422 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
 423 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
 424 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
 425 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 426                                const struct intel_crtc_state *pipe_config,
 427                                bool fastset);
 428
 429 void intel_plane_destroy(struct drm_plane *plane);
 430 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 431 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 432 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
 433 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
 434 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 435 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 436 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 437 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 438                       const char *name, u32 reg, int ref_freq);
 439 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 440                            const char *name, u32 reg);
 441 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 442 unsigned int intel_fb_xy_to_linear(int x, int y,
 443                                    const struct intel_plane_state *state,
 444                                    int plane);
 445 void intel_add_fb_offsets(int *x, int *y,
 446                           const struct intel_plane_state *state, int plane);
 447 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 448 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 449 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 450 void intel_encoder_destroy(struct drm_encoder *encoder);
 451 struct drm_display_mode *
 452 intel_encoder_current_mode(struct intel_encoder *encoder);
 453 void intel_encoder_get_config(struct intel_encoder *encoder,
 454                               struct intel_crtc_state *crtc_state);
 455 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 456 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 457 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
 458 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 459                               enum port port);
 460
 461 enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
 462 bool intel_encoder_is_combo(struct intel_encoder *encoder);
 463 bool intel_encoder_is_snps(struct intel_encoder *encoder);
 464 bool intel_encoder_is_tc(struct intel_encoder *encoder);
 465 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
 466
 467 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 468                                       struct drm_file *file_priv);
 469
 470 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
 471 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 472                          struct intel_digital_port *dig_port,
 473                          unsigned int expected_mask);
 474 struct drm_framebuffer *
 475 intel_framebuffer_create(struct drm_i915_gem_object *obj,
 476                          struct drm_mode_fb_cmd2 *mode_cmd);
 477
 478 bool intel_fuzzy_clock_check(int clock1, int clock2);
 479
 480 void intel_zero_m_n(struct intel_link_m_n *m_n);
 481 void intel_set_m_n(struct drm_i915_private *i915,
 482                    const struct intel_link_m_n *m_n,
 483                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 484                    i915_reg_t link_m_reg, i915_reg_t link_n_reg);
 485 void intel_get_m_n(struct drm_i915_private *i915,
 486                    struct intel_link_m_n *m_n,
 487                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 488                    i915_reg_t link_m_reg, i915_reg_t link_n_reg);
 489 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
 490                                     enum transcoder transcoder);
 491 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 492                                     enum transcoder cpu_transcoder,
 493                                     const struct intel_link_m_n *m_n);
 494 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 495                                     enum transcoder cpu_transcoder,
 496                                     const struct intel_link_m_n *m_n);
 497 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 498                                     enum transcoder cpu_transcoder,
 499                                     struct intel_link_m_n *m_n);
 500 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 501                                     enum transcoder cpu_transcoder,
 502                                     struct intel_link_m_n *m_n);
 503 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 504 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
 505 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
 506 enum intel_display_power_domain
 507 intel_aux_power_domain(struct intel_digital_port *dig_port);
 508 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 509                                   struct intel_crtc_state *crtc_state);
 510 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 511
 512 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
 513 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
 514
 515 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
 516
 517 struct intel_encoder *
 518 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 519                            const struct intel_crtc_state *crtc_state);
 520 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 521                                   struct intel_plane *plane);
 522 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 523                              struct intel_plane_state *plane_state,
 524                              bool visible);
 525 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
 526
 527 void intel_update_watermarks(struct drm_i915_private *i915);
 528
 529 /* modesetting */
 530 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
 531                                       const char *reason, u8 pipe_mask);
 532 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
 533                                  const char *reason);
 534 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
 535                                           struct intel_power_domain_mask *old_domains);
 536 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
 537                                           struct intel_power_domain_mask *domains);
 538
 539 /* interface for intel_display_driver.c */
 540 void intel_setup_outputs(struct drm_i915_private *i915);
 541 int intel_initial_commit(struct drm_device *dev);
 542 void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
 543 void intel_update_czclk(struct drm_i915_private *i915);
 544 void intel_atomic_helper_free_state_worker(struct work_struct *work);
 545 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
 546                                       const struct drm_display_mode *mode);
 547 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
 548                         bool nonblock);
 549
 550 void intel_hpd_poll_fini(struct drm_i915_private *i915);
 551
 552 /* modesetting asserts */
 553 void assert_transcoder(struct drm_i915_private *dev_priv,
 554                        enum transcoder cpu_transcoder, bool state);
 555 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
 556 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
 557
 558 bool assert_port_valid(struct drm_i915_private *i915, enum port port);
 559
 560 /*
 561  * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity
 562  * checks to check for unexpected conditions which may not necessarily be a user
 563  * visible problem. This will either WARN() or DRM_ERROR() depending on the
 564  * verbose_state_checks module param, to enable distros and users to tailor
 565  * their preferred amount of i915 abrt spam.
 566  */
 567 #define I915_STATE_WARN(__i915, condition, format...) ({                \
 568         struct drm_device *drm = &(__i915)->drm;                        \
 569         int __ret_warn_on = !!(condition);                              \
 570         if (unlikely(__ret_warn_on))                                    \
 571                 if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \
 572                         drm_err(drm, format);                           \
 573         unlikely(__ret_warn_on);                                        \
 574 })
 575
 576 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
 577
 578 #endif