drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_damage_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "gem/i915_gem_lmem.h"
  46 #include "gem/i915_gem_object.h"
  47
  48 #include "g4x_dp.h"
  49 #include "g4x_hdmi.h"
  50 #include "hsw_ips.h"
  51 #include "i915_config.h"
  52 #include "i915_drv.h"
  53 #include "i915_reg.h"
  54 #include "i915_utils.h"
  55 #include "i9xx_plane.h"
  56 #include "i9xx_wm.h"
  57 #include "intel_atomic.h"
  58 #include "intel_atomic_plane.h"
  59 #include "intel_audio.h"
  60 #include "intel_bw.h"
  61 #include "intel_cdclk.h"
  62 #include "intel_clock_gating.h"
  63 #include "intel_color.h"
  64 #include "intel_crt.h"
  65 #include "intel_crtc.h"
  66 #include "intel_crtc_state_dump.h"
  67 #include "intel_ddi.h"
  68 #include "intel_de.h"
  69 #include "intel_display_driver.h"
  70 #include "intel_display_power.h"
  71 #include "intel_display_types.h"
  72 #include "intel_dmc.h"
  73 #include "intel_dp.h"
  74 #include "intel_dp_link_training.h"
  75 #include "intel_dp_mst.h"
  76 #include "intel_dpll.h"
  77 #include "intel_dpll_mgr.h"
  78 #include "intel_dpt.h"
  79 #include "intel_drrs.h"
  80 #include "intel_dsb.h"
  81 #include "intel_dsi.h"
  82 #include "intel_dvo.h"
  83 #include "intel_fb.h"
  84 #include "intel_fbc.h"
  85 #include "intel_fbdev.h"
  86 #include "intel_fdi.h"
  87 #include "intel_fifo_underrun.h"
  88 #include "intel_frontbuffer.h"
  89 #include "intel_hdmi.h"
  90 #include "intel_hotplug.h"
  91 #include "intel_link_bw.h"
  92 #include "intel_lvds.h"
  93 #include "intel_lvds_regs.h"
  94 #include "intel_modeset_setup.h"
  95 #include "intel_modeset_verify.h"
  96 #include "intel_overlay.h"
  97 #include "intel_panel.h"
  98 #include "intel_pch_display.h"
  99 #include "intel_pch_refclk.h"
 100 #include "intel_pcode.h"
 101 #include "intel_pipe_crc.h"
 102 #include "intel_plane_initial.h"
 103 #include "intel_pmdemand.h"
 104 #include "intel_pps.h"
 105 #include "intel_psr.h"
 106 #include "intel_sdvo.h"
 107 #include "intel_snps_phy.h"
 108 #include "intel_tc.h"
 109 #include "intel_tv.h"
 110 #include "intel_vblank.h"
 111 #include "intel_vdsc.h"
 112 #include "intel_vdsc_regs.h"
 113 #include "intel_vga.h"
 114 #include "intel_vrr.h"
 115 #include "intel_wm.h"
 116 #include "skl_scaler.h"
 117 #include "skl_universal_plane.h"
 118 #include "skl_watermark.h"
 119 #include "vlv_dsi.h"
 120 #include "vlv_dsi_pll.h"
 121 #include "vlv_dsi_regs.h"
 122 #include "vlv_sideband.h"
 123
 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 126 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 127 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 128
 129 /* returns HPLL frequency in kHz */
 130 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 131 {
 132         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 133
 134         /* Obtain SKU information */
 135         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 136                 CCK_FUSE_HPLL_FREQ_MASK;
 137
 138         return vco_freq[hpll_freq] * 1000;
 139 }
 140
 141 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 142                       const char *name, u32 reg, int ref_freq)
 143 {
 144         u32 val;
 145         int divider;
 146
 147         val = vlv_cck_read(dev_priv, reg);
 148         divider = val & CCK_FREQUENCY_VALUES;
 149
 150         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 151                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 152                  "%s change in progress\n", name);
 153
 154         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 155 }
 156
 157 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 158                            const char *name, u32 reg)
 159 {
 160         int hpll;
 161
 162         vlv_cck_get(dev_priv);
 163
 164         if (dev_priv->hpll_freq == 0)
 165                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 166
 167         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 168
 169         vlv_cck_put(dev_priv);
 170
 171         return hpll;
 172 }
 173
 174 void intel_update_czclk(struct drm_i915_private *dev_priv)
 175 {
 176         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 177                 return;
 178
 179         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 180                                                       CCK_CZ_CLOCK_CONTROL);
 181
 182         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 183                 dev_priv->czclk_freq);
 184 }
 185
 186 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 187 {
 188         return (crtc_state->active_planes &
 189                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 190 }
 191
 192 /* WA Display #0827: Gen9:all */
 193 static void
 194 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 195 {
 196         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 197                      DUPS1_GATING_DIS | DUPS2_GATING_DIS,
 198                      enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
 199 }
 200
 201 /* Wa_2006604312:icl,ehl */
 202 static void
 203 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 204                        bool enable)
 205 {
 206         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 207                      DPFR_GATING_DIS,
 208                      enable ? DPFR_GATING_DIS : 0);
 209 }
 210
 211 /* Wa_1604331009:icl,jsl,ehl */
 212 static void
 213 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 214                        bool enable)
 215 {
 216         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 217                      CURSOR_GATING_DIS,
 218                      enable ? CURSOR_GATING_DIS : 0);
 219 }
 220
 221 static bool
 222 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 223 {
 224         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 225 }
 226
 227 bool
 228 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 229 {
 230         return crtc_state->sync_mode_slaves_mask != 0;
 231 }
 232
 233 bool
 234 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 235 {
 236         return is_trans_port_sync_master(crtc_state) ||
 237                 is_trans_port_sync_slave(crtc_state);
 238 }
 239
 240 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 241 {
 242         return ffs(crtc_state->bigjoiner_pipes) - 1;
 243 }
 244
 245 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 246 {
 247         if (crtc_state->bigjoiner_pipes)
 248                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 249         else
 250                 return 0;
 251 }
 252
 253 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 254 {
 255         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 256
 257         return crtc_state->bigjoiner_pipes &&
 258                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 259 }
 260
 261 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 262 {
 263         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 264
 265         return crtc_state->bigjoiner_pipes &&
 266                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 267 }
 268
 269 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 270 {
 271         return hweight8(crtc_state->bigjoiner_pipes);
 272 }
 273
 274 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 275 {
 276         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 277
 278         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 279                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 280         else
 281                 return to_intel_crtc(crtc_state->uapi.crtc);
 282 }
 283
 284 static void
 285 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 286 {
 287         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 288         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 289
 290         if (DISPLAY_VER(dev_priv) >= 4) {
 291                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 292
 293                 /* Wait for the Pipe State to go off */
 294                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 295                                             TRANSCONF_STATE_ENABLE, 100))
 296                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 297         } else {
 298                 intel_wait_for_pipe_scanline_stopped(crtc);
 299         }
 300 }
 301
 302 void assert_transcoder(struct drm_i915_private *dev_priv,
 303                        enum transcoder cpu_transcoder, bool state)
 304 {
 305         bool cur_state;
 306         enum intel_display_power_domain power_domain;
 307         intel_wakeref_t wakeref;
 308
 309         /* we keep both pipes enabled on 830 */
 310         if (IS_I830(dev_priv))
 311                 state = true;
 312
 313         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 314         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 315         if (wakeref) {
 316                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 317                 cur_state = !!(val & TRANSCONF_ENABLE);
 318
 319                 intel_display_power_put(dev_priv, power_domain, wakeref);
 320         } else {
 321                 cur_state = false;
 322         }
 323
 324         I915_STATE_WARN(dev_priv, cur_state != state,
 325                         "transcoder %s assertion failure (expected %s, current %s)\n",
 326                         transcoder_name(cpu_transcoder), str_on_off(state),
 327                         str_on_off(cur_state));
 328 }
 329
 330 static void assert_plane(struct intel_plane *plane, bool state)
 331 {
 332         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 333         enum pipe pipe;
 334         bool cur_state;
 335
 336         cur_state = plane->get_hw_state(plane, &pipe);
 337
 338         I915_STATE_WARN(i915, cur_state != state,
 339                         "%s assertion failure (expected %s, current %s)\n",
 340                         plane->base.name, str_on_off(state),
 341                         str_on_off(cur_state));
 342 }
 343
 344 #define assert_plane_enabled(p) assert_plane(p, true)
 345 #define assert_plane_disabled(p) assert_plane(p, false)
 346
 347 static void assert_planes_disabled(struct intel_crtc *crtc)
 348 {
 349         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 350         struct intel_plane *plane;
 351
 352         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 353                 assert_plane_disabled(plane);
 354 }
 355
 356 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 357                          struct intel_digital_port *dig_port,
 358                          unsigned int expected_mask)
 359 {
 360         u32 port_mask;
 361         i915_reg_t dpll_reg;
 362
 363         switch (dig_port->base.port) {
 364         default:
 365                 MISSING_CASE(dig_port->base.port);
 366                 fallthrough;
 367         case PORT_B:
 368                 port_mask = DPLL_PORTB_READY_MASK;
 369                 dpll_reg = DPLL(0);
 370                 break;
 371         case PORT_C:
 372                 port_mask = DPLL_PORTC_READY_MASK;
 373                 dpll_reg = DPLL(0);
 374                 expected_mask <<= 4;
 375                 break;
 376         case PORT_D:
 377                 port_mask = DPLL_PORTD_READY_MASK;
 378                 dpll_reg = DPIO_PHY_STATUS;
 379                 break;
 380         }
 381
 382         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 383                                        port_mask, expected_mask, 1000))
 384                 drm_WARN(&dev_priv->drm, 1,
 385                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 386                          dig_port->base.base.base.id, dig_port->base.base.name,
 387                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 388                          expected_mask);
 389 }
 390
 391 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 392 {
 393         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 394         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 395         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 396         enum pipe pipe = crtc->pipe;
 397         u32 val;
 398
 399         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 400
 401         assert_planes_disabled(crtc);
 402
 403         /*
 404          * A pipe without a PLL won't actually be able to drive bits from
 405          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 406          * need the check.
 407          */
 408         if (HAS_GMCH(dev_priv)) {
 409                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 410                         assert_dsi_pll_enabled(dev_priv);
 411                 else
 412                         assert_pll_enabled(dev_priv, pipe);
 413         } else {
 414                 if (new_crtc_state->has_pch_encoder) {
 415                         /* if driving the PCH, we need FDI enabled */
 416                         assert_fdi_rx_pll_enabled(dev_priv,
 417                                                   intel_crtc_pch_transcoder(crtc));
 418                         assert_fdi_tx_pll_enabled(dev_priv,
 419                                                   (enum pipe) cpu_transcoder);
 420                 }
 421                 /* FIXME: assert CPU port conditions for SNB+ */
 422         }
 423
 424         /* Wa_22012358565:adl-p */
 425         if (DISPLAY_VER(dev_priv) == 13)
 426                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 427                              0, PIPE_ARB_USE_PROG_SLOTS);
 428
 429         val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 430         if (val & TRANSCONF_ENABLE) {
 431                 /* we keep both pipes enabled on 830 */
 432                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 433                 return;
 434         }
 435
 436         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
 437                        val | TRANSCONF_ENABLE);
 438         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
 439
 440         /*
 441          * Until the pipe starts PIPEDSL reads will return a stale value,
 442          * which causes an apparent vblank timestamp jump when PIPEDSL
 443          * resets to its proper value. That also messes up the frame count
 444          * when it's derived from the timestamps. So let's wait for the
 445          * pipe to start properly before we call drm_crtc_vblank_on()
 446          */
 447         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 448                 intel_wait_for_pipe_scanline_moving(crtc);
 449 }
 450
 451 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 452 {
 453         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 454         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 455         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 456         enum pipe pipe = crtc->pipe;
 457         u32 val;
 458
 459         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 460
 461         /*
 462          * Make sure planes won't keep trying to pump pixels to us,
 463          * or we might hang the display.
 464          */
 465         assert_planes_disabled(crtc);
 466
 467         val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 468         if ((val & TRANSCONF_ENABLE) == 0)
 469                 return;
 470
 471         /*
 472          * Double wide has implications for planes
 473          * so best keep it disabled when not needed.
 474          */
 475         if (old_crtc_state->double_wide)
 476                 val &= ~TRANSCONF_DOUBLE_WIDE;
 477
 478         /* Don't disable pipe or pipe PLLs if needed */
 479         if (!IS_I830(dev_priv))
 480                 val &= ~TRANSCONF_ENABLE;
 481
 482         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
 483
 484         if (DISPLAY_VER(dev_priv) >= 12)
 485                 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
 486                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 487
 488         if ((val & TRANSCONF_ENABLE) == 0)
 489                 intel_wait_for_pipe_off(old_crtc_state);
 490 }
 491
 492 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 493 {
 494         unsigned int size = 0;
 495         int i;
 496
 497         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 498                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 499
 500         return size;
 501 }
 502
 503 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 504 {
 505         unsigned int size = 0;
 506         int i;
 507
 508         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 509                 unsigned int plane_size;
 510
 511                 if (rem_info->plane[i].linear)
 512                         plane_size = rem_info->plane[i].size;
 513                 else
 514                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 515
 516                 if (plane_size == 0)
 517                         continue;
 518
 519                 if (rem_info->plane_alignment)
 520                         size = ALIGN(size, rem_info->plane_alignment);
 521
 522                 size += plane_size;
 523         }
 524
 525         return size;
 526 }
 527
 528 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 529 {
 530         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 531         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 532
 533         return DISPLAY_VER(dev_priv) < 4 ||
 534                 (plane->fbc &&
 535                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 536 }
 537
 538 /*
 539  * Convert the x/y offsets into a linear offset.
 540  * Only valid with 0/180 degree rotation, which is fine since linear
 541  * offset is only used with linear buffers on pre-hsw and tiled buffers
 542  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 543  */
 544 u32 intel_fb_xy_to_linear(int x, int y,
 545                           const struct intel_plane_state *state,
 546                           int color_plane)
 547 {
 548         const struct drm_framebuffer *fb = state->hw.fb;
 549         unsigned int cpp = fb->format->cpp[color_plane];
 550         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 551
 552         return y * pitch + x * cpp;
 553 }
 554
 555 /*
 556  * Add the x/y offsets derived from fb->offsets[] to the user
 557  * specified plane src x/y offsets. The resulting x/y offsets
 558  * specify the start of scanout from the beginning of the gtt mapping.
 559  */
 560 void intel_add_fb_offsets(int *x, int *y,
 561                           const struct intel_plane_state *state,
 562                           int color_plane)
 563
 564 {
 565         *x += state->view.color_plane[color_plane].x;
 566         *y += state->view.color_plane[color_plane].y;
 567 }
 568
 569 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 570                               u32 pixel_format, u64 modifier)
 571 {
 572         struct intel_crtc *crtc;
 573         struct intel_plane *plane;
 574
 575         if (!HAS_DISPLAY(dev_priv))
 576                 return 0;
 577
 578         /*
 579          * We assume the primary plane for pipe A has
 580          * the highest stride limits of them all,
 581          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 582          */
 583         crtc = intel_first_crtc(dev_priv);
 584         if (!crtc)
 585                 return 0;
 586
 587         plane = to_intel_plane(crtc->base.primary);
 588
 589         return plane->max_stride(plane, pixel_format, modifier,
 590                                  DRM_MODE_ROTATE_0);
 591 }
 592
 593 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 594                              struct intel_plane_state *plane_state,
 595                              bool visible)
 596 {
 597         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 598
 599         plane_state->uapi.visible = visible;
 600
 601         if (visible)
 602                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 603         else
 604                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 605 }
 606
 607 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 608 {
 609         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 610         struct drm_plane *plane;
 611
 612         /*
 613          * Active_planes aliases if multiple "primary" or cursor planes
 614          * have been used on the same (or wrong) pipe. plane_mask uses
 615          * unique ids, hence we can use that to reconstruct active_planes.
 616          */
 617         crtc_state->enabled_planes = 0;
 618         crtc_state->active_planes = 0;
 619
 620         drm_for_each_plane_mask(plane, &dev_priv->drm,
 621                                 crtc_state->uapi.plane_mask) {
 622                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 623                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 624         }
 625 }
 626
 627 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 628                                   struct intel_plane *plane)
 629 {
 630         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 631         struct intel_crtc_state *crtc_state =
 632                 to_intel_crtc_state(crtc->base.state);
 633         struct intel_plane_state *plane_state =
 634                 to_intel_plane_state(plane->base.state);
 635
 636         drm_dbg_kms(&dev_priv->drm,
 637                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 638                     plane->base.base.id, plane->base.name,
 639                     crtc->base.base.id, crtc->base.name);
 640
 641         intel_set_plane_visible(crtc_state, plane_state, false);
 642         intel_plane_fixup_bitmasks(crtc_state);
 643         crtc_state->data_rate[plane->id] = 0;
 644         crtc_state->data_rate_y[plane->id] = 0;
 645         crtc_state->rel_data_rate[plane->id] = 0;
 646         crtc_state->rel_data_rate_y[plane->id] = 0;
 647         crtc_state->min_cdclk[plane->id] = 0;
 648
 649         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 650             hsw_ips_disable(crtc_state)) {
 651                 crtc_state->ips_enabled = false;
 652                 intel_crtc_wait_for_next_vblank(crtc);
 653         }
 654
 655         /*
 656          * Vblank time updates from the shadow to live plane control register
 657          * are blocked if the memory self-refresh mode is active at that
 658          * moment. So to make sure the plane gets truly disabled, disable
 659          * first the self-refresh mode. The self-refresh enable bit in turn
 660          * will be checked/applied by the HW only at the next frame start
 661          * event which is after the vblank start event, so we need to have a
 662          * wait-for-vblank between disabling the plane and the pipe.
 663          */
 664         if (HAS_GMCH(dev_priv) &&
 665             intel_set_memory_cxsr(dev_priv, false))
 666                 intel_crtc_wait_for_next_vblank(crtc);
 667
 668         /*
 669          * Gen2 reports pipe underruns whenever all planes are disabled.
 670          * So disable underrun reporting before all the planes get disabled.
 671          */
 672         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 673                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 674
 675         intel_plane_disable_arm(plane, crtc_state);
 676         intel_crtc_wait_for_next_vblank(crtc);
 677 }
 678
 679 unsigned int
 680 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 681 {
 682         int x = 0, y = 0;
 683
 684         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 685                                           plane_state->view.color_plane[0].offset, 0);
 686
 687         return y;
 688 }
 689
 690 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 691 {
 692         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 693         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 694         enum pipe pipe = crtc->pipe;
 695         u32 tmp;
 696
 697         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 698
 699         /*
 700          * Display WA #1153: icl
 701          * enable hardware to bypass the alpha math
 702          * and rounding for per-pixel values 00 and 0xff
 703          */
 704         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 705         /*
 706          * Display WA # 1605353570: icl
 707          * Set the pixel rounding bit to 1 for allowing
 708          * passthrough of Frame buffer pixels unmodified
 709          * across pipe
 710          */
 711         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 712
 713         /*
 714          * Underrun recovery must always be disabled on display 13+.
 715          * DG2 chicken bit meaning is inverted compared to other platforms.
 716          */
 717         if (IS_DG2(dev_priv))
 718                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 719         else if (DISPLAY_VER(dev_priv) >= 13)
 720                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 721
 722         /* Wa_14010547955:dg2 */
 723         if (IS_DG2(dev_priv))
 724                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 725
 726         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 727 }
 728
 729 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 730 {
 731         struct drm_crtc *crtc;
 732         bool cleanup_done;
 733
 734         drm_for_each_crtc(crtc, &dev_priv->drm) {
 735                 struct drm_crtc_commit *commit;
 736                 spin_lock(&crtc->commit_lock);
 737                 commit = list_first_entry_or_null(&crtc->commit_list,
 738                                                   struct drm_crtc_commit, commit_entry);
 739                 cleanup_done = commit ?
 740                         try_wait_for_completion(&commit->cleanup_done) : true;
 741                 spin_unlock(&crtc->commit_lock);
 742
 743                 if (cleanup_done)
 744                         continue;
 745
 746                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 747
 748                 return true;
 749         }
 750
 751         return false;
 752 }
 753
 754 /*
 755  * Finds the encoder associated with the given CRTC. This can only be
 756  * used when we know that the CRTC isn't feeding multiple encoders!
 757  */
 758 struct intel_encoder *
 759 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 760                            const struct intel_crtc_state *crtc_state)
 761 {
 762         const struct drm_connector_state *connector_state;
 763         const struct drm_connector *connector;
 764         struct intel_encoder *encoder = NULL;
 765         struct intel_crtc *master_crtc;
 766         int num_encoders = 0;
 767         int i;
 768
 769         master_crtc = intel_master_crtc(crtc_state);
 770
 771         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 772                 if (connector_state->crtc != &master_crtc->base)
 773                         continue;
 774
 775                 encoder = to_intel_encoder(connector_state->best_encoder);
 776                 num_encoders++;
 777         }
 778
 779         drm_WARN(state->base.dev, num_encoders != 1,
 780                  "%d encoders for pipe %c\n",
 781                  num_encoders, pipe_name(master_crtc->pipe));
 782
 783         return encoder;
 784 }
 785
 786 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 787 {
 788         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 789         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 790         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 791         enum pipe pipe = crtc->pipe;
 792         int width = drm_rect_width(dst);
 793         int height = drm_rect_height(dst);
 794         int x = dst->x1;
 795         int y = dst->y1;
 796
 797         if (!crtc_state->pch_pfit.enabled)
 798                 return;
 799
 800         /* Force use of hard-coded filter coefficients
 801          * as some pre-programmed values are broken,
 802          * e.g. x201.
 803          */
 804         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 805                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 806                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 807         else
 808                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 809                                   PF_FILTER_MED_3x3);
 810         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
 811                           PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
 812         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
 813                           PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 814 }
 815
 816 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 817 {
 818         if (crtc->overlay)
 819                 (void) intel_overlay_switch_off(crtc->overlay);
 820
 821         /* Let userspace switch the overlay on again. In most cases userspace
 822          * has to recompute where to put it anyway.
 823          */
 824 }
 825
 826 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 827 {
 828         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 829
 830         if (!crtc_state->nv12_planes)
 831                 return false;
 832
 833         /* WA Display #0827: Gen9:all */
 834         if (DISPLAY_VER(dev_priv) == 9)
 835                 return true;
 836
 837         return false;
 838 }
 839
 840 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 841 {
 842         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 843
 844         /* Wa_2006604312:icl,ehl */
 845         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
 846                 return true;
 847
 848         return false;
 849 }
 850
 851 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 852 {
 853         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 854
 855         /* Wa_1604331009:icl,jsl,ehl */
 856         if (is_hdr_mode(crtc_state) &&
 857             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 858             DISPLAY_VER(dev_priv) == 11)
 859                 return true;
 860
 861         return false;
 862 }
 863
 864 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
 865                                     enum pipe pipe, bool enable)
 866 {
 867         if (DISPLAY_VER(i915) == 9) {
 868                 /*
 869                  * "Plane N strech max must be programmed to 11b (x1)
 870                  *  when Async flips are enabled on that plane."
 871                  */
 872                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 873                              SKL_PLANE1_STRETCH_MAX_MASK,
 874                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 875         } else {
 876                 /* Also needed on HSW/BDW albeit undocumented */
 877                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 878                              HSW_PRI_STRETCH_MAX_MASK,
 879                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 880         }
 881 }
 882
 883 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 884 {
 885         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 886
 887         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
 888                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
 889 }
 890
 891 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
 892         ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 893          (new_crtc_state)->feature)
 894 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
 895         ((old_crtc_state)->feature && \
 896          (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 897
 898 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 899                             const struct intel_crtc_state *new_crtc_state)
 900 {
 901         if (!new_crtc_state->hw.active)
 902                 return false;
 903
 904         return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 905 }
 906
 907 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 908                              const struct intel_crtc_state *new_crtc_state)
 909 {
 910         if (!old_crtc_state->hw.active)
 911                 return false;
 912
 913         return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 914 }
 915
 916 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 917                                const struct intel_crtc_state *new_crtc_state)
 918 {
 919         return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
 920                 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
 921                 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
 922                 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
 923                 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
 924 }
 925
 926 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 927                          const struct intel_crtc_state *new_crtc_state)
 928 {
 929         if (!new_crtc_state->hw.active)
 930                 return false;
 931
 932         return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 933                 (new_crtc_state->vrr.enable &&
 934                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 935                   vrr_params_changed(old_crtc_state, new_crtc_state)));
 936 }
 937
 938 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 939                           const struct intel_crtc_state *new_crtc_state)
 940 {
 941         if (!old_crtc_state->hw.active)
 942                 return false;
 943
 944         return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 945                 (old_crtc_state->vrr.enable &&
 946                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 947                   vrr_params_changed(old_crtc_state, new_crtc_state)));
 948 }
 949
 950 #undef is_disabling
 951 #undef is_enabling
 952
 953 static void intel_post_plane_update(struct intel_atomic_state *state,
 954                                     struct intel_crtc *crtc)
 955 {
 956         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 957         const struct intel_crtc_state *old_crtc_state =
 958                 intel_atomic_get_old_crtc_state(state, crtc);
 959         const struct intel_crtc_state *new_crtc_state =
 960                 intel_atomic_get_new_crtc_state(state, crtc);
 961         enum pipe pipe = crtc->pipe;
 962
 963         intel_psr_post_plane_update(state, crtc);
 964
 965         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 966
 967         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 968                 intel_update_watermarks(dev_priv);
 969
 970         intel_fbc_post_update(state, crtc);
 971
 972         if (needs_async_flip_vtd_wa(old_crtc_state) &&
 973             !needs_async_flip_vtd_wa(new_crtc_state))
 974                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
 975
 976         if (needs_nv12_wa(old_crtc_state) &&
 977             !needs_nv12_wa(new_crtc_state))
 978                 skl_wa_827(dev_priv, pipe, false);
 979
 980         if (needs_scalerclk_wa(old_crtc_state) &&
 981             !needs_scalerclk_wa(new_crtc_state))
 982                 icl_wa_scalerclkgating(dev_priv, pipe, false);
 983
 984         if (needs_cursorclk_wa(old_crtc_state) &&
 985             !needs_cursorclk_wa(new_crtc_state))
 986                 icl_wa_cursorclkgating(dev_priv, pipe, false);
 987
 988         if (intel_crtc_needs_color_update(new_crtc_state))
 989                 intel_color_post_update(new_crtc_state);
 990 }
 991
 992 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
 993                                         struct intel_crtc *crtc)
 994 {
 995         const struct intel_crtc_state *crtc_state =
 996                 intel_atomic_get_new_crtc_state(state, crtc);
 997         u8 update_planes = crtc_state->update_planes;
 998         const struct intel_plane_state __maybe_unused *plane_state;
 999         struct intel_plane *plane;
1000         int i;
1001
1002         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1003                 if (plane->pipe == crtc->pipe &&
1004                     update_planes & BIT(plane->id))
1005                         plane->enable_flip_done(plane);
1006         }
1007 }
1008
1009 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1010                                          struct intel_crtc *crtc)
1011 {
1012         const struct intel_crtc_state *crtc_state =
1013                 intel_atomic_get_new_crtc_state(state, crtc);
1014         u8 update_planes = crtc_state->update_planes;
1015         const struct intel_plane_state __maybe_unused *plane_state;
1016         struct intel_plane *plane;
1017         int i;
1018
1019         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1020                 if (plane->pipe == crtc->pipe &&
1021                     update_planes & BIT(plane->id))
1022                         plane->disable_flip_done(plane);
1023         }
1024 }
1025
1026 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1027                                              struct intel_crtc *crtc)
1028 {
1029         const struct intel_crtc_state *old_crtc_state =
1030                 intel_atomic_get_old_crtc_state(state, crtc);
1031         const struct intel_crtc_state *new_crtc_state =
1032                 intel_atomic_get_new_crtc_state(state, crtc);
1033         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1034                                        ~new_crtc_state->async_flip_planes;
1035         const struct intel_plane_state *old_plane_state;
1036         struct intel_plane *plane;
1037         bool need_vbl_wait = false;
1038         int i;
1039
1040         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1041                 if (plane->need_async_flip_disable_wa &&
1042                     plane->pipe == crtc->pipe &&
1043                     disable_async_flip_planes & BIT(plane->id)) {
1044                         /*
1045                          * Apart from the async flip bit we want to
1046                          * preserve the old state for the plane.
1047                          */
1048                         plane->async_flip(plane, old_crtc_state,
1049                                           old_plane_state, false);
1050                         need_vbl_wait = true;
1051                 }
1052         }
1053
1054         if (need_vbl_wait)
1055                 intel_crtc_wait_for_next_vblank(crtc);
1056 }
1057
1058 static void intel_pre_plane_update(struct intel_atomic_state *state,
1059                                    struct intel_crtc *crtc)
1060 {
1061         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1062         const struct intel_crtc_state *old_crtc_state =
1063                 intel_atomic_get_old_crtc_state(state, crtc);
1064         const struct intel_crtc_state *new_crtc_state =
1065                 intel_atomic_get_new_crtc_state(state, crtc);
1066         enum pipe pipe = crtc->pipe;
1067
1068         if (vrr_disabling(old_crtc_state, new_crtc_state)) {
1069                 intel_vrr_disable(old_crtc_state);
1070                 intel_crtc_update_active_timings(old_crtc_state, false);
1071         }
1072
1073         intel_drrs_deactivate(old_crtc_state);
1074
1075         intel_psr_pre_plane_update(state, crtc);
1076
1077         if (hsw_ips_pre_update(state, crtc))
1078                 intel_crtc_wait_for_next_vblank(crtc);
1079
1080         if (intel_fbc_pre_update(state, crtc))
1081                 intel_crtc_wait_for_next_vblank(crtc);
1082
1083         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1084             needs_async_flip_vtd_wa(new_crtc_state))
1085                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1086
1087         /* Display WA 827 */
1088         if (!needs_nv12_wa(old_crtc_state) &&
1089             needs_nv12_wa(new_crtc_state))
1090                 skl_wa_827(dev_priv, pipe, true);
1091
1092         /* Wa_2006604312:icl,ehl */
1093         if (!needs_scalerclk_wa(old_crtc_state) &&
1094             needs_scalerclk_wa(new_crtc_state))
1095                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1096
1097         /* Wa_1604331009:icl,jsl,ehl */
1098         if (!needs_cursorclk_wa(old_crtc_state) &&
1099             needs_cursorclk_wa(new_crtc_state))
1100                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1101
1102         /*
1103          * Vblank time updates from the shadow to live plane control register
1104          * are blocked if the memory self-refresh mode is active at that
1105          * moment. So to make sure the plane gets truly disabled, disable
1106          * first the self-refresh mode. The self-refresh enable bit in turn
1107          * will be checked/applied by the HW only at the next frame start
1108          * event which is after the vblank start event, so we need to have a
1109          * wait-for-vblank between disabling the plane and the pipe.
1110          */
1111         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1112             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1113                 intel_crtc_wait_for_next_vblank(crtc);
1114
1115         /*
1116          * IVB workaround: must disable low power watermarks for at least
1117          * one frame before enabling scaling.  LP watermarks can be re-enabled
1118          * when scaling is disabled.
1119          *
1120          * WaCxSRDisabledForSpriteScaling:ivb
1121          */
1122         if (old_crtc_state->hw.active &&
1123             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1124                 intel_crtc_wait_for_next_vblank(crtc);
1125
1126         /*
1127          * If we're doing a modeset we don't need to do any
1128          * pre-vblank watermark programming here.
1129          */
1130         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1131                 /*
1132                  * For platforms that support atomic watermarks, program the
1133                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1134                  * will be the intermediate values that are safe for both pre- and
1135                  * post- vblank; when vblank happens, the 'active' values will be set
1136                  * to the final 'target' values and we'll do this again to get the
1137                  * optimal watermarks.  For gen9+ platforms, the values we program here
1138                  * will be the final target values which will get automatically latched
1139                  * at vblank time; no further programming will be necessary.
1140                  *
1141                  * If a platform hasn't been transitioned to atomic watermarks yet,
1142                  * we'll continue to update watermarks the old way, if flags tell
1143                  * us to.
1144                  */
1145                 if (!intel_initial_watermarks(state, crtc))
1146                         if (new_crtc_state->update_wm_pre)
1147                                 intel_update_watermarks(dev_priv);
1148         }
1149
1150         /*
1151          * Gen2 reports pipe underruns whenever all planes are disabled.
1152          * So disable underrun reporting before all the planes get disabled.
1153          *
1154          * We do this after .initial_watermarks() so that we have a
1155          * chance of catching underruns with the intermediate watermarks
1156          * vs. the old plane configuration.
1157          */
1158         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1159                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1160
1161         /*
1162          * WA for platforms where async address update enable bit
1163          * is double buffered and only latched at start of vblank.
1164          */
1165         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1166                 intel_crtc_async_flip_disable_wa(state, crtc);
1167 }
1168
1169 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1170                                       struct intel_crtc *crtc)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1173         const struct intel_crtc_state *new_crtc_state =
1174                 intel_atomic_get_new_crtc_state(state, crtc);
1175         unsigned int update_mask = new_crtc_state->update_planes;
1176         const struct intel_plane_state *old_plane_state;
1177         struct intel_plane *plane;
1178         unsigned fb_bits = 0;
1179         int i;
1180
1181         intel_crtc_dpms_overlay_disable(crtc);
1182
1183         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1184                 if (crtc->pipe != plane->pipe ||
1185                     !(update_mask & BIT(plane->id)))
1186                         continue;
1187
1188                 intel_plane_disable_arm(plane, new_crtc_state);
1189
1190                 if (old_plane_state->uapi.visible)
1191                         fb_bits |= plane->frontbuffer_bit;
1192         }
1193
1194         intel_frontbuffer_flip(dev_priv, fb_bits);
1195 }
1196
1197 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1198 {
1199         struct drm_i915_private *i915 = to_i915(state->base.dev);
1200         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1201         struct intel_crtc *crtc;
1202         int i;
1203
1204         /*
1205          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1206          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1207          */
1208         if (i915->display.dpll.mgr) {
1209                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1210                         if (intel_crtc_needs_modeset(new_crtc_state))
1211                                 continue;
1212
1213                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1214                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1215                 }
1216         }
1217 }
1218
1219 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1220                                           struct intel_crtc *crtc)
1221 {
1222         const struct intel_crtc_state *crtc_state =
1223                 intel_atomic_get_new_crtc_state(state, crtc);
1224         const struct drm_connector_state *conn_state;
1225         struct drm_connector *conn;
1226         int i;
1227
1228         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1229                 struct intel_encoder *encoder =
1230                         to_intel_encoder(conn_state->best_encoder);
1231
1232                 if (conn_state->crtc != &crtc->base)
1233                         continue;
1234
1235                 if (encoder->pre_pll_enable)
1236                         encoder->pre_pll_enable(state, encoder,
1237                                                 crtc_state, conn_state);
1238         }
1239 }
1240
1241 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1242                                       struct intel_crtc *crtc)
1243 {
1244         const struct intel_crtc_state *crtc_state =
1245                 intel_atomic_get_new_crtc_state(state, crtc);
1246         const struct drm_connector_state *conn_state;
1247         struct drm_connector *conn;
1248         int i;
1249
1250         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1251                 struct intel_encoder *encoder =
1252                         to_intel_encoder(conn_state->best_encoder);
1253
1254                 if (conn_state->crtc != &crtc->base)
1255                         continue;
1256
1257                 if (encoder->pre_enable)
1258                         encoder->pre_enable(state, encoder,
1259                                             crtc_state, conn_state);
1260         }
1261 }
1262
1263 static void intel_encoders_enable(struct intel_atomic_state *state,
1264                                   struct intel_crtc *crtc)
1265 {
1266         const struct intel_crtc_state *crtc_state =
1267                 intel_atomic_get_new_crtc_state(state, crtc);
1268         const struct drm_connector_state *conn_state;
1269         struct drm_connector *conn;
1270         int i;
1271
1272         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1273                 struct intel_encoder *encoder =
1274                         to_intel_encoder(conn_state->best_encoder);
1275
1276                 if (conn_state->crtc != &crtc->base)
1277                         continue;
1278
1279                 if (encoder->enable)
1280                         encoder->enable(state, encoder,
1281                                         crtc_state, conn_state);
1282                 intel_opregion_notify_encoder(encoder, true);
1283         }
1284 }
1285
1286 static void intel_encoders_disable(struct intel_atomic_state *state,
1287                                    struct intel_crtc *crtc)
1288 {
1289         const struct intel_crtc_state *old_crtc_state =
1290                 intel_atomic_get_old_crtc_state(state, crtc);
1291         const struct drm_connector_state *old_conn_state;
1292         struct drm_connector *conn;
1293         int i;
1294
1295         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1296                 struct intel_encoder *encoder =
1297                         to_intel_encoder(old_conn_state->best_encoder);
1298
1299                 if (old_conn_state->crtc != &crtc->base)
1300                         continue;
1301
1302                 intel_opregion_notify_encoder(encoder, false);
1303                 if (encoder->disable)
1304                         encoder->disable(state, encoder,
1305                                          old_crtc_state, old_conn_state);
1306         }
1307 }
1308
1309 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1310                                         struct intel_crtc *crtc)
1311 {
1312         const struct intel_crtc_state *old_crtc_state =
1313                 intel_atomic_get_old_crtc_state(state, crtc);
1314         const struct drm_connector_state *old_conn_state;
1315         struct drm_connector *conn;
1316         int i;
1317
1318         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1319                 struct intel_encoder *encoder =
1320                         to_intel_encoder(old_conn_state->best_encoder);
1321
1322                 if (old_conn_state->crtc != &crtc->base)
1323                         continue;
1324
1325                 if (encoder->post_disable)
1326                         encoder->post_disable(state, encoder,
1327                                               old_crtc_state, old_conn_state);
1328         }
1329 }
1330
1331 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1332                                             struct intel_crtc *crtc)
1333 {
1334         const struct intel_crtc_state *old_crtc_state =
1335                 intel_atomic_get_old_crtc_state(state, crtc);
1336         const struct drm_connector_state *old_conn_state;
1337         struct drm_connector *conn;
1338         int i;
1339
1340         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1341                 struct intel_encoder *encoder =
1342                         to_intel_encoder(old_conn_state->best_encoder);
1343
1344                 if (old_conn_state->crtc != &crtc->base)
1345                         continue;
1346
1347                 if (encoder->post_pll_disable)
1348                         encoder->post_pll_disable(state, encoder,
1349                                                   old_crtc_state, old_conn_state);
1350         }
1351 }
1352
1353 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1354                                        struct intel_crtc *crtc)
1355 {
1356         const struct intel_crtc_state *crtc_state =
1357                 intel_atomic_get_new_crtc_state(state, crtc);
1358         const struct drm_connector_state *conn_state;
1359         struct drm_connector *conn;
1360         int i;
1361
1362         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1363                 struct intel_encoder *encoder =
1364                         to_intel_encoder(conn_state->best_encoder);
1365
1366                 if (conn_state->crtc != &crtc->base)
1367                         continue;
1368
1369                 if (encoder->update_pipe)
1370                         encoder->update_pipe(state, encoder,
1371                                              crtc_state, conn_state);
1372         }
1373 }
1374
1375 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1376 {
1377         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1378         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1379
1380         plane->disable_arm(plane, crtc_state);
1381 }
1382
1383 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1384 {
1385         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1386         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1387
1388         if (crtc_state->has_pch_encoder) {
1389                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1390                                                &crtc_state->fdi_m_n);
1391         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1392                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1393                                                &crtc_state->dp_m_n);
1394                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1395                                                &crtc_state->dp_m2_n2);
1396         }
1397
1398         intel_set_transcoder_timings(crtc_state);
1399
1400         ilk_set_pipeconf(crtc_state);
1401 }
1402
1403 static void ilk_crtc_enable(struct intel_atomic_state *state,
1404                             struct intel_crtc *crtc)
1405 {
1406         const struct intel_crtc_state *new_crtc_state =
1407                 intel_atomic_get_new_crtc_state(state, crtc);
1408         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1409         enum pipe pipe = crtc->pipe;
1410
1411         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1412                 return;
1413
1414         /*
1415          * Sometimes spurious CPU pipe underruns happen during FDI
1416          * training, at least with VGA+HDMI cloning. Suppress them.
1417          *
1418          * On ILK we get an occasional spurious CPU pipe underruns
1419          * between eDP port A enable and vdd enable. Also PCH port
1420          * enable seems to result in the occasional CPU pipe underrun.
1421          *
1422          * Spurious PCH underruns also occur during PCH enabling.
1423          */
1424         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1425         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1426
1427         ilk_configure_cpu_transcoder(new_crtc_state);
1428
1429         intel_set_pipe_src_size(new_crtc_state);
1430
1431         crtc->active = true;
1432
1433         intel_encoders_pre_enable(state, crtc);
1434
1435         if (new_crtc_state->has_pch_encoder) {
1436                 ilk_pch_pre_enable(state, crtc);
1437         } else {
1438                 assert_fdi_tx_disabled(dev_priv, pipe);
1439                 assert_fdi_rx_disabled(dev_priv, pipe);
1440         }
1441
1442         ilk_pfit_enable(new_crtc_state);
1443
1444         /*
1445          * On ILK+ LUT must be loaded before the pipe is running but with
1446          * clocks enabled
1447          */
1448         intel_color_load_luts(new_crtc_state);
1449         intel_color_commit_noarm(new_crtc_state);
1450         intel_color_commit_arm(new_crtc_state);
1451         /* update DSPCNTR to configure gamma for pipe bottom color */
1452         intel_disable_primary_plane(new_crtc_state);
1453
1454         intel_initial_watermarks(state, crtc);
1455         intel_enable_transcoder(new_crtc_state);
1456
1457         if (new_crtc_state->has_pch_encoder)
1458                 ilk_pch_enable(state, crtc);
1459
1460         intel_crtc_vblank_on(new_crtc_state);
1461
1462         intel_encoders_enable(state, crtc);
1463
1464         if (HAS_PCH_CPT(dev_priv))
1465                 intel_wait_for_pipe_scanline_moving(crtc);
1466
1467         /*
1468          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1469          * And a second vblank wait is needed at least on ILK with
1470          * some interlaced HDMI modes. Let's do the double wait always
1471          * in case there are more corner cases we don't know about.
1472          */
1473         if (new_crtc_state->has_pch_encoder) {
1474                 intel_crtc_wait_for_next_vblank(crtc);
1475                 intel_crtc_wait_for_next_vblank(crtc);
1476         }
1477         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1478         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1479 }
1480
1481 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1482                                             enum pipe pipe, bool apply)
1483 {
1484         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1485         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1486
1487         if (apply)
1488                 val |= mask;
1489         else
1490                 val &= ~mask;
1491
1492         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1493 }
1494
1495 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1496 {
1497         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1498         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1499
1500         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1501                        HSW_LINETIME(crtc_state->linetime) |
1502                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1503 }
1504
1505 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1506 {
1507         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1508         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1509
1510         intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder),
1511                      HSW_FRAME_START_DELAY_MASK,
1512                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1513 }
1514
1515 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1516                                          const struct intel_crtc_state *crtc_state)
1517 {
1518         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1519
1520         /*
1521          * Enable sequence steps 1-7 on bigjoiner master
1522          */
1523         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1524                 intel_encoders_pre_pll_enable(state, master_crtc);
1525
1526         if (crtc_state->shared_dpll)
1527                 intel_enable_shared_dpll(crtc_state);
1528
1529         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1530                 intel_encoders_pre_enable(state, master_crtc);
1531 }
1532
1533 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1534 {
1535         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1536         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1537         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1538
1539         if (crtc_state->has_pch_encoder) {
1540                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1541                                                &crtc_state->fdi_m_n);
1542         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1543                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1544                                                &crtc_state->dp_m_n);
1545                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1546                                                &crtc_state->dp_m2_n2);
1547         }
1548
1549         intel_set_transcoder_timings(crtc_state);
1550         if (HAS_VRR(dev_priv))
1551                 intel_vrr_set_transcoder_timings(crtc_state);
1552
1553         if (cpu_transcoder != TRANSCODER_EDP)
1554                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1555                                crtc_state->pixel_multiplier - 1);
1556
1557         hsw_set_frame_start_delay(crtc_state);
1558
1559         hsw_set_transconf(crtc_state);
1560 }
1561
1562 static void hsw_crtc_enable(struct intel_atomic_state *state,
1563                             struct intel_crtc *crtc)
1564 {
1565         const struct intel_crtc_state *new_crtc_state =
1566                 intel_atomic_get_new_crtc_state(state, crtc);
1567         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1569         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1570         bool psl_clkgate_wa;
1571
1572         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1573                 return;
1574
1575         intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1576
1577         if (!new_crtc_state->bigjoiner_pipes) {
1578                 intel_encoders_pre_pll_enable(state, crtc);
1579
1580                 if (new_crtc_state->shared_dpll)
1581                         intel_enable_shared_dpll(new_crtc_state);
1582
1583                 intel_encoders_pre_enable(state, crtc);
1584         } else {
1585                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1586         }
1587
1588         intel_dsc_enable(new_crtc_state);
1589
1590         if (DISPLAY_VER(dev_priv) >= 13)
1591                 intel_uncompressed_joiner_enable(new_crtc_state);
1592
1593         intel_set_pipe_src_size(new_crtc_state);
1594         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1595                 bdw_set_pipe_misc(new_crtc_state);
1596
1597         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1598             !transcoder_is_dsi(cpu_transcoder))
1599                 hsw_configure_cpu_transcoder(new_crtc_state);
1600
1601         crtc->active = true;
1602
1603         /* Display WA #1180: WaDisableScalarClockGating: glk */
1604         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1605                 new_crtc_state->pch_pfit.enabled;
1606         if (psl_clkgate_wa)
1607                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1608
1609         if (DISPLAY_VER(dev_priv) >= 9)
1610                 skl_pfit_enable(new_crtc_state);
1611         else
1612                 ilk_pfit_enable(new_crtc_state);
1613
1614         /*
1615          * On ILK+ LUT must be loaded before the pipe is running but with
1616          * clocks enabled
1617          */
1618         intel_color_load_luts(new_crtc_state);
1619         intel_color_commit_noarm(new_crtc_state);
1620         intel_color_commit_arm(new_crtc_state);
1621         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1622         if (DISPLAY_VER(dev_priv) < 9)
1623                 intel_disable_primary_plane(new_crtc_state);
1624
1625         hsw_set_linetime_wm(new_crtc_state);
1626
1627         if (DISPLAY_VER(dev_priv) >= 11)
1628                 icl_set_pipe_chicken(new_crtc_state);
1629
1630         intel_initial_watermarks(state, crtc);
1631
1632         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1633                 intel_crtc_vblank_on(new_crtc_state);
1634
1635         intel_encoders_enable(state, crtc);
1636
1637         if (psl_clkgate_wa) {
1638                 intel_crtc_wait_for_next_vblank(crtc);
1639                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1640         }
1641
1642         /* If we change the relative order between pipe/planes enabling, we need
1643          * to change the workaround. */
1644         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1645         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1646                 struct intel_crtc *wa_crtc;
1647
1648                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1649
1650                 intel_crtc_wait_for_next_vblank(wa_crtc);
1651                 intel_crtc_wait_for_next_vblank(wa_crtc);
1652         }
1653 }
1654
1655 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1656 {
1657         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1658         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1659         enum pipe pipe = crtc->pipe;
1660
1661         /* To avoid upsetting the power well on haswell only disable the pfit if
1662          * it's in use. The hw state code will make sure we get this right. */
1663         if (!old_crtc_state->pch_pfit.enabled)
1664                 return;
1665
1666         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1667         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1668         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1669 }
1670
1671 static void ilk_crtc_disable(struct intel_atomic_state *state,
1672                              struct intel_crtc *crtc)
1673 {
1674         const struct intel_crtc_state *old_crtc_state =
1675                 intel_atomic_get_old_crtc_state(state, crtc);
1676         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1677         enum pipe pipe = crtc->pipe;
1678
1679         /*
1680          * Sometimes spurious CPU pipe underruns happen when the
1681          * pipe is already disabled, but FDI RX/TX is still enabled.
1682          * Happens at least with VGA+HDMI cloning. Suppress them.
1683          */
1684         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1685         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1686
1687         intel_encoders_disable(state, crtc);
1688
1689         intel_crtc_vblank_off(old_crtc_state);
1690
1691         intel_disable_transcoder(old_crtc_state);
1692
1693         ilk_pfit_disable(old_crtc_state);
1694
1695         if (old_crtc_state->has_pch_encoder)
1696                 ilk_pch_disable(state, crtc);
1697
1698         intel_encoders_post_disable(state, crtc);
1699
1700         if (old_crtc_state->has_pch_encoder)
1701                 ilk_pch_post_disable(state, crtc);
1702
1703         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1704         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1705
1706         intel_disable_shared_dpll(old_crtc_state);
1707 }
1708
1709 static void hsw_crtc_disable(struct intel_atomic_state *state,
1710                              struct intel_crtc *crtc)
1711 {
1712         const struct intel_crtc_state *old_crtc_state =
1713                 intel_atomic_get_old_crtc_state(state, crtc);
1714         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1715
1716         /*
1717          * FIXME collapse everything to one hook.
1718          * Need care with mst->ddi interactions.
1719          */
1720         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1721                 intel_encoders_disable(state, crtc);
1722                 intel_encoders_post_disable(state, crtc);
1723         }
1724
1725         intel_disable_shared_dpll(old_crtc_state);
1726
1727         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1728                 struct intel_crtc *slave_crtc;
1729
1730                 intel_encoders_post_pll_disable(state, crtc);
1731
1732                 intel_dmc_disable_pipe(i915, crtc->pipe);
1733
1734                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
1735                                                  intel_crtc_bigjoiner_slave_pipes(old_crtc_state))
1736                         intel_dmc_disable_pipe(i915, slave_crtc->pipe);
1737         }
1738 }
1739
1740 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1741 {
1742         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1743         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1744
1745         if (!crtc_state->gmch_pfit.control)
1746                 return;
1747
1748         /*
1749          * The panel fitter should only be adjusted whilst the pipe is disabled,
1750          * according to register description and PRM.
1751          */
1752         drm_WARN_ON(&dev_priv->drm,
1753                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1754         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1755
1756         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1757                        crtc_state->gmch_pfit.pgm_ratios);
1758         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1759
1760         /* Border color in case we don't scale up to the full screen. Black by
1761          * default, change to something else for debugging. */
1762         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1763 }
1764
1765 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1766 {
1767         if (phy == PHY_NONE)
1768                 return false;
1769         else if (IS_ALDERLAKE_S(dev_priv))
1770                 return phy <= PHY_E;
1771         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1772                 return phy <= PHY_D;
1773         else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
1774                 return phy <= PHY_C;
1775         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1776                 return phy <= PHY_B;
1777         else
1778                 /*
1779                  * DG2 outputs labelled as "combo PHY" in the bspec use
1780                  * SNPS PHYs with completely different programming,
1781                  * hence we always return false here.
1782                  */
1783                 return false;
1784 }
1785
1786 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1787 {
1788         /*
1789          * DG2's "TC1", although TC-capable output, doesn't share the same flow
1790          * as other platforms on the display engine side and rather rely on the
1791          * SNPS PHY, that is programmed separately
1792          */
1793         if (IS_DG2(dev_priv))
1794                 return false;
1795
1796         if (DISPLAY_VER(dev_priv) >= 13)
1797                 return phy >= PHY_F && phy <= PHY_I;
1798         else if (IS_TIGERLAKE(dev_priv))
1799                 return phy >= PHY_D && phy <= PHY_I;
1800         else if (IS_ICELAKE(dev_priv))
1801                 return phy >= PHY_C && phy <= PHY_F;
1802
1803         return false;
1804 }
1805
1806 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1807 {
1808         /*
1809          * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1810          * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1811          */
1812         return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
1813 }
1814
1815 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1816 {
1817         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1818                 return PHY_D + port - PORT_D_XELPD;
1819         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1820                 return PHY_F + port - PORT_TC1;
1821         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1822                 return PHY_B + port - PORT_TC1;
1823         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1824                 return PHY_C + port - PORT_TC1;
1825         else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1826                  port == PORT_D)
1827                 return PHY_A;
1828
1829         return PHY_A + port - PORT_A;
1830 }
1831
1832 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1833 {
1834         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1835                 return TC_PORT_NONE;
1836
1837         if (DISPLAY_VER(dev_priv) >= 12)
1838                 return TC_PORT_1 + port - PORT_TC1;
1839         else
1840                 return TC_PORT_1 + port - PORT_C;
1841 }
1842
1843 enum intel_display_power_domain
1844 intel_aux_power_domain(struct intel_digital_port *dig_port)
1845 {
1846         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1847
1848         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1849                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1850
1851         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1852 }
1853
1854 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1855                                    struct intel_power_domain_mask *mask)
1856 {
1857         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1858         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1860         struct drm_encoder *encoder;
1861         enum pipe pipe = crtc->pipe;
1862
1863         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1864
1865         if (!crtc_state->hw.active)
1866                 return;
1867
1868         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1869         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1870         if (crtc_state->pch_pfit.enabled ||
1871             crtc_state->pch_pfit.force_thru)
1872                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1873
1874         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
1875                                   crtc_state->uapi.encoder_mask) {
1876                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1877
1878                 set_bit(intel_encoder->power_domain, mask->bits);
1879         }
1880
1881         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
1882                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1883
1884         if (crtc_state->shared_dpll)
1885                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1886
1887         if (crtc_state->dsc.compression_enable)
1888                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1889 }
1890
1891 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1892                                           struct intel_power_domain_mask *old_domains)
1893 {
1894         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1895         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896         enum intel_display_power_domain domain;
1897         struct intel_power_domain_mask domains, new_domains;
1898
1899         get_crtc_power_domains(crtc_state, &domains);
1900
1901         bitmap_andnot(new_domains.bits,
1902                       domains.bits,
1903                       crtc->enabled_power_domains.mask.bits,
1904                       POWER_DOMAIN_NUM);
1905         bitmap_andnot(old_domains->bits,
1906                       crtc->enabled_power_domains.mask.bits,
1907                       domains.bits,
1908                       POWER_DOMAIN_NUM);
1909
1910         for_each_power_domain(domain, &new_domains)
1911                 intel_display_power_get_in_set(dev_priv,
1912                                                &crtc->enabled_power_domains,
1913                                                domain);
1914 }
1915
1916 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1917                                           struct intel_power_domain_mask *domains)
1918 {
1919         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
1920                                             &crtc->enabled_power_domains,
1921                                             domains);
1922 }
1923
1924 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1925 {
1926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1927         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1928
1929         if (intel_crtc_has_dp_encoder(crtc_state)) {
1930                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1931                                                &crtc_state->dp_m_n);
1932                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1933                                                &crtc_state->dp_m2_n2);
1934         }
1935
1936         intel_set_transcoder_timings(crtc_state);
1937
1938         i9xx_set_pipeconf(crtc_state);
1939 }
1940
1941 static void valleyview_crtc_enable(struct intel_atomic_state *state,
1942                                    struct intel_crtc *crtc)
1943 {
1944         const struct intel_crtc_state *new_crtc_state =
1945                 intel_atomic_get_new_crtc_state(state, crtc);
1946         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947         enum pipe pipe = crtc->pipe;
1948
1949         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1950                 return;
1951
1952         i9xx_configure_cpu_transcoder(new_crtc_state);
1953
1954         intel_set_pipe_src_size(new_crtc_state);
1955
1956         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
1957
1958         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1959                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
1960                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
1961         }
1962
1963         crtc->active = true;
1964
1965         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1966
1967         intel_encoders_pre_pll_enable(state, crtc);
1968
1969         if (IS_CHERRYVIEW(dev_priv))
1970                 chv_enable_pll(new_crtc_state);
1971         else
1972                 vlv_enable_pll(new_crtc_state);
1973
1974         intel_encoders_pre_enable(state, crtc);
1975
1976         i9xx_pfit_enable(new_crtc_state);
1977
1978         intel_color_load_luts(new_crtc_state);
1979         intel_color_commit_noarm(new_crtc_state);
1980         intel_color_commit_arm(new_crtc_state);
1981         /* update DSPCNTR to configure gamma for pipe bottom color */
1982         intel_disable_primary_plane(new_crtc_state);
1983
1984         intel_initial_watermarks(state, crtc);
1985         intel_enable_transcoder(new_crtc_state);
1986
1987         intel_crtc_vblank_on(new_crtc_state);
1988
1989         intel_encoders_enable(state, crtc);
1990 }
1991
1992 static void i9xx_crtc_enable(struct intel_atomic_state *state,
1993                              struct intel_crtc *crtc)
1994 {
1995         const struct intel_crtc_state *new_crtc_state =
1996                 intel_atomic_get_new_crtc_state(state, crtc);
1997         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1998         enum pipe pipe = crtc->pipe;
1999
2000         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2001                 return;
2002
2003         i9xx_configure_cpu_transcoder(new_crtc_state);
2004
2005         intel_set_pipe_src_size(new_crtc_state);
2006
2007         crtc->active = true;
2008
2009         if (DISPLAY_VER(dev_priv) != 2)
2010                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2011
2012         intel_encoders_pre_enable(state, crtc);
2013
2014         i9xx_enable_pll(new_crtc_state);
2015
2016         i9xx_pfit_enable(new_crtc_state);
2017
2018         intel_color_load_luts(new_crtc_state);
2019         intel_color_commit_noarm(new_crtc_state);
2020         intel_color_commit_arm(new_crtc_state);
2021         /* update DSPCNTR to configure gamma for pipe bottom color */
2022         intel_disable_primary_plane(new_crtc_state);
2023
2024         if (!intel_initial_watermarks(state, crtc))
2025                 intel_update_watermarks(dev_priv);
2026         intel_enable_transcoder(new_crtc_state);
2027
2028         intel_crtc_vblank_on(new_crtc_state);
2029
2030         intel_encoders_enable(state, crtc);
2031
2032         /* prevents spurious underruns */
2033         if (DISPLAY_VER(dev_priv) == 2)
2034                 intel_crtc_wait_for_next_vblank(crtc);
2035 }
2036
2037 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2038 {
2039         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2040         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2041
2042         if (!old_crtc_state->gmch_pfit.control)
2043                 return;
2044
2045         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2046
2047         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2048                     intel_de_read(dev_priv, PFIT_CONTROL));
2049         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2050 }
2051
2052 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2053                               struct intel_crtc *crtc)
2054 {
2055         struct intel_crtc_state *old_crtc_state =
2056                 intel_atomic_get_old_crtc_state(state, crtc);
2057         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2058         enum pipe pipe = crtc->pipe;
2059
2060         /*
2061          * On gen2 planes are double buffered but the pipe isn't, so we must
2062          * wait for planes to fully turn off before disabling the pipe.
2063          */
2064         if (DISPLAY_VER(dev_priv) == 2)
2065                 intel_crtc_wait_for_next_vblank(crtc);
2066
2067         intel_encoders_disable(state, crtc);
2068
2069         intel_crtc_vblank_off(old_crtc_state);
2070
2071         intel_disable_transcoder(old_crtc_state);
2072
2073         i9xx_pfit_disable(old_crtc_state);
2074
2075         intel_encoders_post_disable(state, crtc);
2076
2077         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2078                 if (IS_CHERRYVIEW(dev_priv))
2079                         chv_disable_pll(dev_priv, pipe);
2080                 else if (IS_VALLEYVIEW(dev_priv))
2081                         vlv_disable_pll(dev_priv, pipe);
2082                 else
2083                         i9xx_disable_pll(old_crtc_state);
2084         }
2085
2086         intel_encoders_post_pll_disable(state, crtc);
2087
2088         if (DISPLAY_VER(dev_priv) != 2)
2089                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2090
2091         if (!dev_priv->display.funcs.wm->initial_watermarks)
2092                 intel_update_watermarks(dev_priv);
2093
2094         /* clock the pipe down to 640x480@60 to potentially save power */
2095         if (IS_I830(dev_priv))
2096                 i830_enable_pipe(dev_priv, pipe);
2097 }
2098
2099 void intel_encoder_destroy(struct drm_encoder *encoder)
2100 {
2101         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2102
2103         drm_encoder_cleanup(encoder);
2104         kfree(intel_encoder);
2105 }
2106
2107 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2108 {
2109         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2110
2111         /* GDG double wide on either pipe, otherwise pipe A only */
2112         return DISPLAY_VER(dev_priv) < 4 &&
2113                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2114 }
2115
2116 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2117 {
2118         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2119         struct drm_rect src;
2120
2121         /*
2122          * We only use IF-ID interlacing. If we ever use
2123          * PF-ID we'll need to adjust the pixel_rate here.
2124          */
2125
2126         if (!crtc_state->pch_pfit.enabled)
2127                 return pixel_rate;
2128
2129         drm_rect_init(&src, 0, 0,
2130                       drm_rect_width(&crtc_state->pipe_src) << 16,
2131                       drm_rect_height(&crtc_state->pipe_src) << 16);
2132
2133         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2134                                    pixel_rate);
2135 }
2136
2137 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2138                                          const struct drm_display_mode *timings)
2139 {
2140         mode->hdisplay = timings->crtc_hdisplay;
2141         mode->htotal = timings->crtc_htotal;
2142         mode->hsync_start = timings->crtc_hsync_start;
2143         mode->hsync_end = timings->crtc_hsync_end;
2144
2145         mode->vdisplay = timings->crtc_vdisplay;
2146         mode->vtotal = timings->crtc_vtotal;
2147         mode->vsync_start = timings->crtc_vsync_start;
2148         mode->vsync_end = timings->crtc_vsync_end;
2149
2150         mode->flags = timings->flags;
2151         mode->type = DRM_MODE_TYPE_DRIVER;
2152
2153         mode->clock = timings->crtc_clock;
2154
2155         drm_mode_set_name(mode);
2156 }
2157
2158 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2159 {
2160         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2161
2162         if (HAS_GMCH(dev_priv))
2163                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2164                 crtc_state->pixel_rate =
2165                         crtc_state->hw.pipe_mode.crtc_clock;
2166         else
2167                 crtc_state->pixel_rate =
2168                         ilk_pipe_pixel_rate(crtc_state);
2169 }
2170
2171 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2172                                            struct drm_display_mode *mode)
2173 {
2174         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2175
2176         if (num_pipes < 2)
2177                 return;
2178
2179         mode->crtc_clock /= num_pipes;
2180         mode->crtc_hdisplay /= num_pipes;
2181         mode->crtc_hblank_start /= num_pipes;
2182         mode->crtc_hblank_end /= num_pipes;
2183         mode->crtc_hsync_start /= num_pipes;
2184         mode->crtc_hsync_end /= num_pipes;
2185         mode->crtc_htotal /= num_pipes;
2186 }
2187
2188 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2189                                           struct drm_display_mode *mode)
2190 {
2191         int overlap = crtc_state->splitter.pixel_overlap;
2192         int n = crtc_state->splitter.link_count;
2193
2194         if (!crtc_state->splitter.enable)
2195                 return;
2196
2197         /*
2198          * eDP MSO uses segment timings from EDID for transcoder
2199          * timings, but full mode for everything else.
2200          *
2201          * h_full = (h_segment - pixel_overlap) * link_count
2202          */
2203         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2204         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2205         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2206         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2207         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2208         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2209         mode->crtc_clock *= n;
2210 }
2211
2212 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2213 {
2214         struct drm_display_mode *mode = &crtc_state->hw.mode;
2215         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2216         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2217
2218         /*
2219          * Start with the adjusted_mode crtc timings, which
2220          * have been filled with the transcoder timings.
2221          */
2222         drm_mode_copy(pipe_mode, adjusted_mode);
2223
2224         /* Expand MSO per-segment transcoder timings to full */
2225         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2226
2227         /*
2228          * We want the full numbers in adjusted_mode normal timings,
2229          * adjusted_mode crtc timings are left with the raw transcoder
2230          * timings.
2231          */
2232         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2233
2234         /* Populate the "user" mode with full numbers */
2235         drm_mode_copy(mode, pipe_mode);
2236         intel_mode_from_crtc_timings(mode, mode);
2237         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2238                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2239         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2240
2241         /* Derive per-pipe timings in case bigjoiner is used */
2242         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2243         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2244
2245         intel_crtc_compute_pixel_rate(crtc_state);
2246 }
2247
2248 void intel_encoder_get_config(struct intel_encoder *encoder,
2249                               struct intel_crtc_state *crtc_state)
2250 {
2251         encoder->get_config(encoder, crtc_state);
2252
2253         intel_crtc_readout_derived_state(crtc_state);
2254 }
2255
2256 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2257 {
2258         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2259         int width, height;
2260
2261         if (num_pipes < 2)
2262                 return;
2263
2264         width = drm_rect_width(&crtc_state->pipe_src);
2265         height = drm_rect_height(&crtc_state->pipe_src);
2266
2267         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2268                       width / num_pipes, height);
2269 }
2270
2271 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2272 {
2273         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2274         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2275
2276         intel_bigjoiner_compute_pipe_src(crtc_state);
2277
2278         /*
2279          * Pipe horizontal size must be even in:
2280          * - DVO ganged mode
2281          * - LVDS dual channel mode
2282          * - Double wide pipe
2283          */
2284         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2285                 if (crtc_state->double_wide) {
2286                         drm_dbg_kms(&i915->drm,
2287                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2288                                     crtc->base.base.id, crtc->base.name);
2289                         return -EINVAL;
2290                 }
2291
2292                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2293                     intel_is_dual_link_lvds(i915)) {
2294                         drm_dbg_kms(&i915->drm,
2295                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2296                                     crtc->base.base.id, crtc->base.name);
2297                         return -EINVAL;
2298                 }
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2305 {
2306         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2307         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2308         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2309         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2310         int clock_limit = i915->max_dotclk_freq;
2311
2312         /*
2313          * Start with the adjusted_mode crtc timings, which
2314          * have been filled with the transcoder timings.
2315          */
2316         drm_mode_copy(pipe_mode, adjusted_mode);
2317
2318         /* Expand MSO per-segment transcoder timings to full */
2319         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2320
2321         /* Derive per-pipe timings in case bigjoiner is used */
2322         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2323         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2324
2325         if (DISPLAY_VER(i915) < 4) {
2326                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2327
2328                 /*
2329                  * Enable double wide mode when the dot clock
2330                  * is > 90% of the (display) core speed.
2331                  */
2332                 if (intel_crtc_supports_double_wide(crtc) &&
2333                     pipe_mode->crtc_clock > clock_limit) {
2334                         clock_limit = i915->max_dotclk_freq;
2335                         crtc_state->double_wide = true;
2336                 }
2337         }
2338
2339         if (pipe_mode->crtc_clock > clock_limit) {
2340                 drm_dbg_kms(&i915->drm,
2341                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2342                             crtc->base.base.id, crtc->base.name,
2343                             pipe_mode->crtc_clock, clock_limit,
2344                             str_yes_no(crtc_state->double_wide));
2345                 return -EINVAL;
2346         }
2347
2348         return 0;
2349 }
2350
2351 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2352                                      struct intel_crtc *crtc)
2353 {
2354         struct intel_crtc_state *crtc_state =
2355                 intel_atomic_get_new_crtc_state(state, crtc);
2356         int ret;
2357
2358         ret = intel_dpll_crtc_compute_clock(state, crtc);
2359         if (ret)
2360                 return ret;
2361
2362         ret = intel_crtc_compute_pipe_src(crtc_state);
2363         if (ret)
2364                 return ret;
2365
2366         ret = intel_crtc_compute_pipe_mode(crtc_state);
2367         if (ret)
2368                 return ret;
2369
2370         intel_crtc_compute_pixel_rate(crtc_state);
2371
2372         if (crtc_state->has_pch_encoder)
2373                 return ilk_fdi_compute_config(crtc, crtc_state);
2374
2375         return 0;
2376 }
2377
2378 static void
2379 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2380 {
2381         while (*num > DATA_LINK_M_N_MASK ||
2382                *den > DATA_LINK_M_N_MASK) {
2383                 *num >>= 1;
2384                 *den >>= 1;
2385         }
2386 }
2387
2388 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2389                         u32 m, u32 n, u32 constant_n)
2390 {
2391         if (constant_n)
2392                 *ret_n = constant_n;
2393         else
2394                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2395
2396         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2397         intel_reduce_m_n_ratio(ret_m, ret_n);
2398 }
2399
2400 void
2401 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2402                        int pixel_clock, int link_clock,
2403                        int bw_overhead,
2404                        struct intel_link_m_n *m_n)
2405 {
2406         u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
2407         u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
2408                                                   bw_overhead);
2409         u32 data_n = intel_dp_max_data_rate(link_clock, nlanes);
2410
2411         /*
2412          * Windows/BIOS uses fixed M/N values always. Follow suit.
2413          *
2414          * Also several DP dongles in particular seem to be fussy
2415          * about too large link M/N values. Presumably the 20bit
2416          * value used by Windows/BIOS is acceptable to everyone.
2417          */
2418         m_n->tu = 64;
2419         compute_m_n(&m_n->data_m, &m_n->data_n,
2420                     data_m, data_n,
2421                     0x8000000);
2422
2423         compute_m_n(&m_n->link_m, &m_n->link_n,
2424                     pixel_clock, link_symbol_clock,
2425                     0x80000);
2426 }
2427
2428 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2429 {
2430         /*
2431          * There may be no VBT; and if the BIOS enabled SSC we can
2432          * just keep using it to avoid unnecessary flicker.  Whereas if the
2433          * BIOS isn't using it, don't assume it will work even if the VBT
2434          * indicates as much.
2435          */
2436         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2437                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2438                                                        PCH_DREF_CONTROL) &
2439                         DREF_SSC1_ENABLE;
2440
2441                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2442                         drm_dbg_kms(&dev_priv->drm,
2443                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2444                                     str_enabled_disabled(bios_lvds_use_ssc),
2445                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2446                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2447                 }
2448         }
2449 }
2450
2451 void intel_zero_m_n(struct intel_link_m_n *m_n)
2452 {
2453         /* corresponds to 0 register value */
2454         memset(m_n, 0, sizeof(*m_n));
2455         m_n->tu = 1;
2456 }
2457
2458 void intel_set_m_n(struct drm_i915_private *i915,
2459                    const struct intel_link_m_n *m_n,
2460                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2461                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2462 {
2463         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2464         intel_de_write(i915, data_n_reg, m_n->data_n);
2465         intel_de_write(i915, link_m_reg, m_n->link_m);
2466         /*
2467          * On BDW+ writing LINK_N arms the double buffered update
2468          * of all the M/N registers, so it must be written last.
2469          */
2470         intel_de_write(i915, link_n_reg, m_n->link_n);
2471 }
2472
2473 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2474                                     enum transcoder transcoder)
2475 {
2476         if (IS_HASWELL(dev_priv))
2477                 return transcoder == TRANSCODER_EDP;
2478
2479         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2480 }
2481
2482 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2483                                     enum transcoder transcoder,
2484                                     const struct intel_link_m_n *m_n)
2485 {
2486         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2487         enum pipe pipe = crtc->pipe;
2488
2489         if (DISPLAY_VER(dev_priv) >= 5)
2490                 intel_set_m_n(dev_priv, m_n,
2491                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2492                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2493         else
2494                 intel_set_m_n(dev_priv, m_n,
2495                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2496                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2497 }
2498
2499 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2500                                     enum transcoder transcoder,
2501                                     const struct intel_link_m_n *m_n)
2502 {
2503         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2504
2505         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2506                 return;
2507
2508         intel_set_m_n(dev_priv, m_n,
2509                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2510                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2511 }
2512
2513 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2514 {
2515         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2517         enum pipe pipe = crtc->pipe;
2518         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2519         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2520         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2521         int vsyncshift = 0;
2522
2523         /* We need to be careful not to changed the adjusted mode, for otherwise
2524          * the hw state checker will get angry at the mismatch. */
2525         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2526         crtc_vtotal = adjusted_mode->crtc_vtotal;
2527         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2528         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2529
2530         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2531                 /* the chip adds 2 halflines automatically */
2532                 crtc_vtotal -= 1;
2533                 crtc_vblank_end -= 1;
2534
2535                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2536                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2537                 else
2538                         vsyncshift = adjusted_mode->crtc_hsync_start -
2539                                 adjusted_mode->crtc_htotal / 2;
2540                 if (vsyncshift < 0)
2541                         vsyncshift += adjusted_mode->crtc_htotal;
2542         }
2543
2544         /*
2545          * VBLANK_START no longer works on ADL+, instead we must use
2546          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2547          */
2548         if (DISPLAY_VER(dev_priv) >= 13) {
2549                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2550                                crtc_vblank_start - crtc_vdisplay);
2551
2552                 /*
2553                  * VBLANK_START not used by hw, just clear it
2554                  * to make it stand out in register dumps.
2555                  */
2556                 crtc_vblank_start = 1;
2557         }
2558
2559         if (DISPLAY_VER(dev_priv) > 3)
2560                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2561                                vsyncshift);
2562
2563         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2564                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2565                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2566         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2567                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2568                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2569         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2570                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2571                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2572
2573         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2574                        VACTIVE(crtc_vdisplay - 1) |
2575                        VTOTAL(crtc_vtotal - 1));
2576         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2577                        VBLANK_START(crtc_vblank_start - 1) |
2578                        VBLANK_END(crtc_vblank_end - 1));
2579         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2580                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2581                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2582
2583         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2584          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2585          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2586          * bits. */
2587         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2588             (pipe == PIPE_B || pipe == PIPE_C))
2589                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2590                                VACTIVE(crtc_vdisplay - 1) |
2591                                VTOTAL(crtc_vtotal - 1));
2592 }
2593
2594 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2595 {
2596         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2597         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2598         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2599         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2600         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2601
2602         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2603         crtc_vtotal = adjusted_mode->crtc_vtotal;
2604         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2605         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2606
2607         drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2608
2609         /*
2610          * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2611          * But let's write it anyway to keep the state checker happy.
2612          */
2613         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2614                        VBLANK_START(crtc_vblank_start - 1) |
2615                        VBLANK_END(crtc_vblank_end - 1));
2616         /*
2617          * The double buffer latch point for TRANS_VTOTAL
2618          * is the transcoder's undelayed vblank.
2619          */
2620         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2621                        VACTIVE(crtc_vdisplay - 1) |
2622                        VTOTAL(crtc_vtotal - 1));
2623 }
2624
2625 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2626 {
2627         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2628         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2629         int width = drm_rect_width(&crtc_state->pipe_src);
2630         int height = drm_rect_height(&crtc_state->pipe_src);
2631         enum pipe pipe = crtc->pipe;
2632
2633         /* pipesrc controls the size that is scaled from, which should
2634          * always be the user's requested size.
2635          */
2636         intel_de_write(dev_priv, PIPESRC(pipe),
2637                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2638 }
2639
2640 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2641 {
2642         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2643         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2644
2645         if (DISPLAY_VER(dev_priv) == 2)
2646                 return false;
2647
2648         if (DISPLAY_VER(dev_priv) >= 9 ||
2649             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2650                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2651         else
2652                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2653 }
2654
2655 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2656                                          struct intel_crtc_state *pipe_config)
2657 {
2658         struct drm_device *dev = crtc->base.dev;
2659         struct drm_i915_private *dev_priv = to_i915(dev);
2660         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2661         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2662         u32 tmp;
2663
2664         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2665         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2666         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2667
2668         if (!transcoder_is_dsi(cpu_transcoder)) {
2669                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2670                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2671                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2672         }
2673
2674         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2675         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2676         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2677
2678         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2679         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2680         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2681
2682         /* FIXME TGL+ DSI transcoders have this! */
2683         if (!transcoder_is_dsi(cpu_transcoder)) {
2684                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2685                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2686                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2687         }
2688         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2689         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2690         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2691
2692         if (intel_pipe_is_interlaced(pipe_config)) {
2693                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2694                 adjusted_mode->crtc_vtotal += 1;
2695                 adjusted_mode->crtc_vblank_end += 1;
2696         }
2697
2698         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2699                 adjusted_mode->crtc_vblank_start =
2700                         adjusted_mode->crtc_vdisplay +
2701                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2702 }
2703
2704 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2705 {
2706         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2707         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2708         enum pipe master_pipe, pipe = crtc->pipe;
2709         int width;
2710
2711         if (num_pipes < 2)
2712                 return;
2713
2714         master_pipe = bigjoiner_master_pipe(crtc_state);
2715         width = drm_rect_width(&crtc_state->pipe_src);
2716
2717         drm_rect_translate_to(&crtc_state->pipe_src,
2718                               (pipe - master_pipe) * width, 0);
2719 }
2720
2721 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2722                                     struct intel_crtc_state *pipe_config)
2723 {
2724         struct drm_device *dev = crtc->base.dev;
2725         struct drm_i915_private *dev_priv = to_i915(dev);
2726         u32 tmp;
2727
2728         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2729
2730         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2731                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2732                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2733
2734         intel_bigjoiner_adjust_pipe_src(pipe_config);
2735 }
2736
2737 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2738 {
2739         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2740         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2741         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2742         u32 val = 0;
2743
2744         /*
2745          * - We keep both pipes enabled on 830
2746          * - During modeset the pipe is still disabled and must remain so
2747          * - During fastset the pipe is already enabled and must remain so
2748          */
2749         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2750                 val |= TRANSCONF_ENABLE;
2751
2752         if (crtc_state->double_wide)
2753                 val |= TRANSCONF_DOUBLE_WIDE;
2754
2755         /* only g4x and later have fancy bpc/dither controls */
2756         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2757             IS_CHERRYVIEW(dev_priv)) {
2758                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2759                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2760                         val |= TRANSCONF_DITHER_EN |
2761                                 TRANSCONF_DITHER_TYPE_SP;
2762
2763                 switch (crtc_state->pipe_bpp) {
2764                 default:
2765                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2766                         MISSING_CASE(crtc_state->pipe_bpp);
2767                         fallthrough;
2768                 case 18:
2769                         val |= TRANSCONF_BPC_6;
2770                         break;
2771                 case 24:
2772                         val |= TRANSCONF_BPC_8;
2773                         break;
2774                 case 30:
2775                         val |= TRANSCONF_BPC_10;
2776                         break;
2777                 }
2778         }
2779
2780         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2781                 if (DISPLAY_VER(dev_priv) < 4 ||
2782                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2783                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2784                 else
2785                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2786         } else {
2787                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2788         }
2789
2790         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2791              crtc_state->limited_color_range)
2792                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2793
2794         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2795
2796         if (crtc_state->wgc_enable)
2797                 val |= TRANSCONF_WGC_ENABLE;
2798
2799         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2800
2801         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2802         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2803 }
2804
2805 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2806 {
2807         if (IS_I830(dev_priv))
2808                 return false;
2809
2810         return DISPLAY_VER(dev_priv) >= 4 ||
2811                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2812 }
2813
2814 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2815 {
2816         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2818         enum pipe pipe;
2819         u32 tmp;
2820
2821         if (!i9xx_has_pfit(dev_priv))
2822                 return;
2823
2824         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2825         if (!(tmp & PFIT_ENABLE))
2826                 return;
2827
2828         /* Check whether the pfit is attached to our pipe. */
2829         if (DISPLAY_VER(dev_priv) >= 4)
2830                 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
2831         else
2832                 pipe = PIPE_B;
2833
2834         if (pipe != crtc->pipe)
2835                 return;
2836
2837         crtc_state->gmch_pfit.control = tmp;
2838         crtc_state->gmch_pfit.pgm_ratios =
2839                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2840 }
2841
2842 static enum intel_output_format
2843 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2844 {
2845         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2846         u32 tmp;
2847
2848         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2849
2850         if (tmp & PIPE_MISC_YUV420_ENABLE) {
2851                 /* We support 4:2:0 in full blend mode only */
2852                 drm_WARN_ON(&dev_priv->drm,
2853                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
2854
2855                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2856         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
2857                 return INTEL_OUTPUT_FORMAT_YCBCR444;
2858         } else {
2859                 return INTEL_OUTPUT_FORMAT_RGB;
2860         }
2861 }
2862
2863 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
2864                                  struct intel_crtc_state *pipe_config)
2865 {
2866         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2867         enum intel_display_power_domain power_domain;
2868         intel_wakeref_t wakeref;
2869         u32 tmp;
2870         bool ret;
2871
2872         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
2873         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
2874         if (!wakeref)
2875                 return false;
2876
2877         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2878         pipe_config->sink_format = pipe_config->output_format;
2879         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
2880         pipe_config->shared_dpll = NULL;
2881
2882         ret = false;
2883
2884         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
2885         if (!(tmp & TRANSCONF_ENABLE))
2886                 goto out;
2887
2888         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2889             IS_CHERRYVIEW(dev_priv)) {
2890                 switch (tmp & TRANSCONF_BPC_MASK) {
2891                 case TRANSCONF_BPC_6:
2892                         pipe_config->pipe_bpp = 18;
2893                         break;
2894                 case TRANSCONF_BPC_8:
2895                         pipe_config->pipe_bpp = 24;
2896                         break;
2897                 case TRANSCONF_BPC_10:
2898                         pipe_config->pipe_bpp = 30;
2899                         break;
2900                 default:
2901                         MISSING_CASE(tmp);
2902                         break;
2903                 }
2904         }
2905
2906         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2907             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
2908                 pipe_config->limited_color_range = true;
2909
2910         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
2911
2912         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
2913
2914         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2915             (tmp & TRANSCONF_WGC_ENABLE))
2916                 pipe_config->wgc_enable = true;
2917
2918         intel_color_get_config(pipe_config);
2919
2920         if (DISPLAY_VER(dev_priv) < 4)
2921                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
2922
2923         intel_get_transcoder_timings(crtc, pipe_config);
2924         intel_get_pipe_src_size(crtc, pipe_config);
2925
2926         i9xx_get_pfit_config(pipe_config);
2927
2928         if (DISPLAY_VER(dev_priv) >= 4) {
2929                 /* No way to read it out on pipes B and C */
2930                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
2931                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
2932                 else
2933                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
2934                 pipe_config->pixel_multiplier =
2935                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
2936                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
2937                 pipe_config->dpll_hw_state.dpll_md = tmp;
2938         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
2939                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
2940                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
2941                 pipe_config->pixel_multiplier =
2942                         ((tmp & SDVO_MULTIPLIER_MASK)
2943                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
2944         } else {
2945                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
2946                  * port and will be fixed up in the encoder->get_config
2947                  * function. */
2948                 pipe_config->pixel_multiplier = 1;
2949         }
2950         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
2951                                                         DPLL(crtc->pipe));
2952         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
2953                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
2954                                                                FP0(crtc->pipe));
2955                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
2956                                                                FP1(crtc->pipe));
2957         } else {
2958                 /* Mask out read-only status bits. */
2959                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
2960                                                      DPLL_PORTC_READY_MASK |
2961                                                      DPLL_PORTB_READY_MASK);
2962         }
2963
2964         if (IS_CHERRYVIEW(dev_priv))
2965                 chv_crtc_clock_get(crtc, pipe_config);
2966         else if (IS_VALLEYVIEW(dev_priv))
2967                 vlv_crtc_clock_get(crtc, pipe_config);
2968         else
2969                 i9xx_crtc_clock_get(crtc, pipe_config);
2970
2971         /*
2972          * Normally the dotclock is filled in by the encoder .get_config()
2973          * but in case the pipe is enabled w/o any ports we need a sane
2974          * default.
2975          */
2976         pipe_config->hw.adjusted_mode.crtc_clock =
2977                 pipe_config->port_clock / pipe_config->pixel_multiplier;
2978
2979         ret = true;
2980
2981 out:
2982         intel_display_power_put(dev_priv, power_domain, wakeref);
2983
2984         return ret;
2985 }
2986
2987 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
2988 {
2989         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2991         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2992         u32 val = 0;
2993
2994         /*
2995          * - During modeset the pipe is still disabled and must remain so
2996          * - During fastset the pipe is already enabled and must remain so
2997          */
2998         if (!intel_crtc_needs_modeset(crtc_state))
2999                 val |= TRANSCONF_ENABLE;
3000
3001         switch (crtc_state->pipe_bpp) {
3002         default:
3003                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3004                 MISSING_CASE(crtc_state->pipe_bpp);
3005                 fallthrough;
3006         case 18:
3007                 val |= TRANSCONF_BPC_6;
3008                 break;
3009         case 24:
3010                 val |= TRANSCONF_BPC_8;
3011                 break;
3012         case 30:
3013                 val |= TRANSCONF_BPC_10;
3014                 break;
3015         case 36:
3016                 val |= TRANSCONF_BPC_12;
3017                 break;
3018         }
3019
3020         if (crtc_state->dither)
3021                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3022
3023         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3024                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3025         else
3026                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3027
3028         /*
3029          * This would end up with an odd purple hue over
3030          * the entire display. Make sure we don't do it.
3031          */
3032         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3033                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3034
3035         if (crtc_state->limited_color_range &&
3036             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3037                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3038
3039         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3040                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3041
3042         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3043
3044         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3045         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3046
3047         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3048         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3049 }
3050
3051 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3052 {
3053         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3054         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3055         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3056         u32 val = 0;
3057
3058         /*
3059          * - During modeset the pipe is still disabled and must remain so
3060          * - During fastset the pipe is already enabled and must remain so
3061          */
3062         if (!intel_crtc_needs_modeset(crtc_state))
3063                 val |= TRANSCONF_ENABLE;
3064
3065         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3066                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3067
3068         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3069                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3070         else
3071                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3072
3073         if (IS_HASWELL(dev_priv) &&
3074             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3075                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3076
3077         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3078         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3079 }
3080
3081 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3082 {
3083         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3084         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3085         u32 val = 0;
3086
3087         switch (crtc_state->pipe_bpp) {
3088         case 18:
3089                 val |= PIPE_MISC_BPC_6;
3090                 break;
3091         case 24:
3092                 val |= PIPE_MISC_BPC_8;
3093                 break;
3094         case 30:
3095                 val |= PIPE_MISC_BPC_10;
3096                 break;
3097         case 36:
3098                 /* Port output 12BPC defined for ADLP+ */
3099                 if (DISPLAY_VER(dev_priv) > 12)
3100                         val |= PIPE_MISC_BPC_12_ADLP;
3101                 break;
3102         default:
3103                 MISSING_CASE(crtc_state->pipe_bpp);
3104                 break;
3105         }
3106
3107         if (crtc_state->dither)
3108                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3109
3110         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3111             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3112                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3113
3114         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3115                 val |= PIPE_MISC_YUV420_ENABLE |
3116                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3117
3118         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3119                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3120
3121         if (DISPLAY_VER(dev_priv) >= 12)
3122                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3123
3124         /* allow PSR with sprite enabled */
3125         if (IS_BROADWELL(dev_priv))
3126                 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3127
3128         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3129 }
3130
3131 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3132 {
3133         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3134         u32 tmp;
3135
3136         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3137
3138         switch (tmp & PIPE_MISC_BPC_MASK) {
3139         case PIPE_MISC_BPC_6:
3140                 return 18;
3141         case PIPE_MISC_BPC_8:
3142                 return 24;
3143         case PIPE_MISC_BPC_10:
3144                 return 30;
3145         /*
3146          * PORT OUTPUT 12 BPC defined for ADLP+.
3147          *
3148          * TODO:
3149          * For previous platforms with DSI interface, bits 5:7
3150          * are used for storing pipe_bpp irrespective of dithering.
3151          * Since the value of 12 BPC is not defined for these bits
3152          * on older platforms, need to find a workaround for 12 BPC
3153          * MIPI DSI HW readout.
3154          */
3155         case PIPE_MISC_BPC_12_ADLP:
3156                 if (DISPLAY_VER(dev_priv) > 12)
3157                         return 36;
3158                 fallthrough;
3159         default:
3160                 MISSING_CASE(tmp);
3161                 return 0;
3162         }
3163 }
3164
3165 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3166 {
3167         /*
3168          * Account for spread spectrum to avoid
3169          * oversubscribing the link. Max center spread
3170          * is 2.5%; use 5% for safety's sake.
3171          */
3172         u32 bps = target_clock * bpp * 21 / 20;
3173         return DIV_ROUND_UP(bps, link_bw * 8);
3174 }
3175
3176 void intel_get_m_n(struct drm_i915_private *i915,
3177                    struct intel_link_m_n *m_n,
3178                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3179                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3180 {
3181         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3182         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3183         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3184         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3185         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3186 }
3187
3188 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3189                                     enum transcoder transcoder,
3190                                     struct intel_link_m_n *m_n)
3191 {
3192         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3193         enum pipe pipe = crtc->pipe;
3194
3195         if (DISPLAY_VER(dev_priv) >= 5)
3196                 intel_get_m_n(dev_priv, m_n,
3197                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3198                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3199         else
3200                 intel_get_m_n(dev_priv, m_n,
3201                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3202                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3203 }
3204
3205 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3206                                     enum transcoder transcoder,
3207                                     struct intel_link_m_n *m_n)
3208 {
3209         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3210
3211         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3212                 return;
3213
3214         intel_get_m_n(dev_priv, m_n,
3215                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3216                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3217 }
3218
3219 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3220 {
3221         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3222         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3223         u32 ctl, pos, size;
3224         enum pipe pipe;
3225
3226         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3227         if ((ctl & PF_ENABLE) == 0)
3228                 return;
3229
3230         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3231                 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3232         else
3233                 pipe = crtc->pipe;
3234
3235         crtc_state->pch_pfit.enabled = true;
3236
3237         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3238         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3239
3240         drm_rect_init(&crtc_state->pch_pfit.dst,
3241                       REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3242                       REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3243                       REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3244                       REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3245
3246         /*
3247          * We currently do not free assignements of panel fitters on
3248          * ivb/hsw (since we don't use the higher upscaling modes which
3249          * differentiates them) so just WARN about this case for now.
3250          */
3251         drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3252 }
3253
3254 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3255                                 struct intel_crtc_state *pipe_config)
3256 {
3257         struct drm_device *dev = crtc->base.dev;
3258         struct drm_i915_private *dev_priv = to_i915(dev);
3259         enum intel_display_power_domain power_domain;
3260         intel_wakeref_t wakeref;
3261         u32 tmp;
3262         bool ret;
3263
3264         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3265         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3266         if (!wakeref)
3267                 return false;
3268
3269         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3270         pipe_config->shared_dpll = NULL;
3271
3272         ret = false;
3273         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3274         if (!(tmp & TRANSCONF_ENABLE))
3275                 goto out;
3276
3277         switch (tmp & TRANSCONF_BPC_MASK) {
3278         case TRANSCONF_BPC_6:
3279                 pipe_config->pipe_bpp = 18;
3280                 break;
3281         case TRANSCONF_BPC_8:
3282                 pipe_config->pipe_bpp = 24;
3283                 break;
3284         case TRANSCONF_BPC_10:
3285                 pipe_config->pipe_bpp = 30;
3286                 break;
3287         case TRANSCONF_BPC_12:
3288                 pipe_config->pipe_bpp = 36;
3289                 break;
3290         default:
3291                 break;
3292         }
3293
3294         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3295                 pipe_config->limited_color_range = true;
3296
3297         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3298         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3299         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3300                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3301                 break;
3302         default:
3303                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3304                 break;
3305         }
3306
3307         pipe_config->sink_format = pipe_config->output_format;
3308
3309         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3310
3311         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3312
3313         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3314
3315         intel_color_get_config(pipe_config);
3316
3317         pipe_config->pixel_multiplier = 1;
3318
3319         ilk_pch_get_config(pipe_config);
3320
3321         intel_get_transcoder_timings(crtc, pipe_config);
3322         intel_get_pipe_src_size(crtc, pipe_config);
3323
3324         ilk_get_pfit_config(pipe_config);
3325
3326         ret = true;
3327
3328 out:
3329         intel_display_power_put(dev_priv, power_domain, wakeref);
3330
3331         return ret;
3332 }
3333
3334 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3335 {
3336         u8 pipes;
3337
3338         if (DISPLAY_VER(i915) >= 12)
3339                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3340         else if (DISPLAY_VER(i915) >= 11)
3341                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3342         else
3343                 pipes = 0;
3344
3345         return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3346 }
3347
3348 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3349                                            enum transcoder cpu_transcoder)
3350 {
3351         enum intel_display_power_domain power_domain;
3352         intel_wakeref_t wakeref;
3353         u32 tmp = 0;
3354
3355         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3356
3357         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3358                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3359
3360         return tmp & TRANS_DDI_FUNC_ENABLE;
3361 }
3362
3363 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3364                                     u8 *master_pipes, u8 *slave_pipes)
3365 {
3366         struct intel_crtc *crtc;
3367
3368         *master_pipes = 0;
3369         *slave_pipes = 0;
3370
3371         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3372                                          bigjoiner_pipes(dev_priv)) {
3373                 enum intel_display_power_domain power_domain;
3374                 enum pipe pipe = crtc->pipe;
3375                 intel_wakeref_t wakeref;
3376
3377                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3378                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3379                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3380
3381                         if (!(tmp & BIG_JOINER_ENABLE))
3382                                 continue;
3383
3384                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3385                                 *master_pipes |= BIT(pipe);
3386                         else
3387                                 *slave_pipes |= BIT(pipe);
3388                 }
3389
3390                 if (DISPLAY_VER(dev_priv) < 13)
3391                         continue;
3392
3393                 power_domain = POWER_DOMAIN_PIPE(pipe);
3394                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3395                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3396
3397                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3398                                 *master_pipes |= BIT(pipe);
3399                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3400                                 *slave_pipes |= BIT(pipe);
3401                 }
3402         }
3403
3404         /* Bigjoiner pipes should always be consecutive master and slave */
3405         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3406                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3407                  *master_pipes, *slave_pipes);
3408 }
3409
3410 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3411 {
3412         if ((slave_pipes & BIT(pipe)) == 0)
3413                 return pipe;
3414
3415         /* ignore everything above our pipe */
3416         master_pipes &= ~GENMASK(7, pipe);
3417
3418         /* highest remaining bit should be our master pipe */
3419         return fls(master_pipes) - 1;
3420 }
3421
3422 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3423 {
3424         enum pipe master_pipe, next_master_pipe;
3425
3426         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3427
3428         if ((master_pipes & BIT(master_pipe)) == 0)
3429                 return 0;
3430
3431         /* ignore our master pipe and everything below it */
3432         master_pipes &= ~GENMASK(master_pipe, 0);
3433         /* make sure a high bit is set for the ffs() */
3434         master_pipes |= BIT(7);
3435         /* lowest remaining bit should be the next master pipe */
3436         next_master_pipe = ffs(master_pipes) - 1;
3437
3438         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3439 }
3440
3441 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3442 {
3443         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3444
3445         if (DISPLAY_VER(i915) >= 11)
3446                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3447
3448         return panel_transcoder_mask;
3449 }
3450
3451 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3452 {
3453         struct drm_device *dev = crtc->base.dev;
3454         struct drm_i915_private *dev_priv = to_i915(dev);
3455         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3456         enum transcoder cpu_transcoder;
3457         u8 master_pipes, slave_pipes;
3458         u8 enabled_transcoders = 0;
3459
3460         /*
3461          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3462          * consistency and less surprising code; it's in always on power).
3463          */
3464         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3465                                        panel_transcoder_mask) {
3466                 enum intel_display_power_domain power_domain;
3467                 intel_wakeref_t wakeref;
3468                 enum pipe trans_pipe;
3469                 u32 tmp = 0;
3470
3471                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3472                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3473                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3474
3475                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3476                         continue;
3477
3478                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3479                 default:
3480                         drm_WARN(dev, 1,
3481                                  "unknown pipe linked to transcoder %s\n",
3482                                  transcoder_name(cpu_transcoder));
3483                         fallthrough;
3484                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3485                 case TRANS_DDI_EDP_INPUT_A_ON:
3486                         trans_pipe = PIPE_A;
3487                         break;
3488                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3489                         trans_pipe = PIPE_B;
3490                         break;
3491                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3492                         trans_pipe = PIPE_C;
3493                         break;
3494                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3495                         trans_pipe = PIPE_D;
3496                         break;
3497                 }
3498
3499                 if (trans_pipe == crtc->pipe)
3500                         enabled_transcoders |= BIT(cpu_transcoder);
3501         }
3502
3503         /* single pipe or bigjoiner master */
3504         cpu_transcoder = (enum transcoder) crtc->pipe;
3505         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3506                 enabled_transcoders |= BIT(cpu_transcoder);
3507
3508         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3509         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3510         if (slave_pipes & BIT(crtc->pipe)) {
3511                 cpu_transcoder = (enum transcoder)
3512                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3513                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3514                         enabled_transcoders |= BIT(cpu_transcoder);
3515         }
3516
3517         return enabled_transcoders;
3518 }
3519
3520 static bool has_edp_transcoders(u8 enabled_transcoders)
3521 {
3522         return enabled_transcoders & BIT(TRANSCODER_EDP);
3523 }
3524
3525 static bool has_dsi_transcoders(u8 enabled_transcoders)
3526 {
3527         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3528                                       BIT(TRANSCODER_DSI_1));
3529 }
3530
3531 static bool has_pipe_transcoders(u8 enabled_transcoders)
3532 {
3533         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3534                                        BIT(TRANSCODER_DSI_0) |
3535                                        BIT(TRANSCODER_DSI_1));
3536 }
3537
3538 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3539                                        u8 enabled_transcoders)
3540 {
3541         /* Only one type of transcoder please */
3542         drm_WARN_ON(&i915->drm,
3543                     has_edp_transcoders(enabled_transcoders) +
3544                     has_dsi_transcoders(enabled_transcoders) +
3545                     has_pipe_transcoders(enabled_transcoders) > 1);
3546
3547         /* Only DSI transcoders can be ganged */
3548         drm_WARN_ON(&i915->drm,
3549                     !has_dsi_transcoders(enabled_transcoders) &&
3550                     !is_power_of_2(enabled_transcoders));
3551 }
3552
3553 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3554                                      struct intel_crtc_state *pipe_config,
3555                                      struct intel_display_power_domain_set *power_domain_set)
3556 {
3557         struct drm_device *dev = crtc->base.dev;
3558         struct drm_i915_private *dev_priv = to_i915(dev);
3559         unsigned long enabled_transcoders;
3560         u32 tmp;
3561
3562         enabled_transcoders = hsw_enabled_transcoders(crtc);
3563         if (!enabled_transcoders)
3564                 return false;
3565
3566         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3567
3568         /*
3569          * With the exception of DSI we should only ever have
3570          * a single enabled transcoder. With DSI let's just
3571          * pick the first one.
3572          */
3573         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3574
3575         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3576                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3577                 return false;
3578
3579         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3580                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3581
3582                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3583                         pipe_config->pch_pfit.force_thru = true;
3584         }
3585
3586         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3587
3588         return tmp & TRANSCONF_ENABLE;
3589 }
3590
3591 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3592                                          struct intel_crtc_state *pipe_config,
3593                                          struct intel_display_power_domain_set *power_domain_set)
3594 {
3595         struct drm_device *dev = crtc->base.dev;
3596         struct drm_i915_private *dev_priv = to_i915(dev);
3597         enum transcoder cpu_transcoder;
3598         enum port port;
3599         u32 tmp;
3600
3601         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3602                 if (port == PORT_A)
3603                         cpu_transcoder = TRANSCODER_DSI_A;
3604                 else
3605                         cpu_transcoder = TRANSCODER_DSI_C;
3606
3607                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3608                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3609                         continue;
3610
3611                 /*
3612                  * The PLL needs to be enabled with a valid divider
3613                  * configuration, otherwise accessing DSI registers will hang
3614                  * the machine. See BSpec North Display Engine
3615                  * registers/MIPI[BXT]. We can break out here early, since we
3616                  * need the same DSI PLL to be enabled for both DSI ports.
3617                  */
3618                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3619                         break;
3620
3621                 /* XXX: this works for video mode only */
3622                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3623                 if (!(tmp & DPI_ENABLE))
3624                         continue;
3625
3626                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3627                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3628                         continue;
3629
3630                 pipe_config->cpu_transcoder = cpu_transcoder;
3631                 break;
3632         }
3633
3634         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3635 }
3636
3637 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3638 {
3639         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3640         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3641         u8 master_pipes, slave_pipes;
3642         enum pipe pipe = crtc->pipe;
3643
3644         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3645
3646         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3647                 return;
3648
3649         crtc_state->bigjoiner_pipes =
3650                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3651                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3652 }
3653
3654 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3655                                 struct intel_crtc_state *pipe_config)
3656 {
3657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3658         bool active;
3659         u32 tmp;
3660
3661         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3662                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3663                 return false;
3664
3665         pipe_config->shared_dpll = NULL;
3666
3667         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3668
3669         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3670             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3671                 drm_WARN_ON(&dev_priv->drm, active);
3672                 active = true;
3673         }
3674
3675         if (!active)
3676                 goto out;
3677
3678         intel_dsc_get_config(pipe_config);
3679         intel_bigjoiner_get_config(pipe_config);
3680
3681         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3682             DISPLAY_VER(dev_priv) >= 11)
3683                 intel_get_transcoder_timings(crtc, pipe_config);
3684
3685         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3686                 intel_vrr_get_config(pipe_config);
3687
3688         intel_get_pipe_src_size(crtc, pipe_config);
3689
3690         if (IS_HASWELL(dev_priv)) {
3691                 u32 tmp = intel_de_read(dev_priv,
3692                                         TRANSCONF(pipe_config->cpu_transcoder));
3693
3694                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3695                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3696                 else
3697                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3698         } else {
3699                 pipe_config->output_format =
3700                         bdw_get_pipe_misc_output_format(crtc);
3701         }
3702
3703         pipe_config->sink_format = pipe_config->output_format;
3704
3705         intel_color_get_config(pipe_config);
3706
3707         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3708         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3709         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3710                 pipe_config->ips_linetime =
3711                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3712
3713         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3714                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3715                 if (DISPLAY_VER(dev_priv) >= 9)
3716                         skl_scaler_get_config(pipe_config);
3717                 else
3718                         ilk_get_pfit_config(pipe_config);
3719         }
3720
3721         hsw_ips_get_config(pipe_config);
3722
3723         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3724             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3725                 pipe_config->pixel_multiplier =
3726                         intel_de_read(dev_priv,
3727                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3728         } else {
3729                 pipe_config->pixel_multiplier = 1;
3730         }
3731
3732         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3733                 tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));
3734
3735                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3736         } else {
3737                 /* no idea if this is correct */
3738                 pipe_config->framestart_delay = 1;
3739         }
3740
3741 out:
3742         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3743
3744         return active;
3745 }
3746
3747 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3748 {
3749         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3750         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3751
3752         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3753                 return false;
3754
3755         crtc_state->hw.active = true;
3756
3757         intel_crtc_readout_derived_state(crtc_state);
3758
3759         return true;
3760 }
3761
3762 int intel_dotclock_calculate(int link_freq,
3763                              const struct intel_link_m_n *m_n)
3764 {
3765         /*
3766          * The calculation for the data clock -> pixel clock is:
3767          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3768          * But we want to avoid losing precison if possible, so:
3769          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3770          *
3771          * and for link freq (10kbs units) -> pixel clock it is:
3772          * link_symbol_clock = link_freq * 10 / link_symbol_size
3773          * pixel_clock = (m * link_symbol_clock) / n
3774          *    or for more precision:
3775          * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
3776          */
3777
3778         if (!m_n->link_n)
3779                 return 0;
3780
3781         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
3782                                 m_n->link_n * intel_dp_link_symbol_size(link_freq));
3783 }
3784
3785 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
3786 {
3787         int dotclock;
3788
3789         if (intel_crtc_has_dp_encoder(pipe_config))
3790                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
3791                                                     &pipe_config->dp_m_n);
3792         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3793                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
3794                                              pipe_config->pipe_bpp);
3795         else
3796                 dotclock = pipe_config->port_clock;
3797
3798         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3799             !intel_crtc_has_dp_encoder(pipe_config))
3800                 dotclock *= 2;
3801
3802         if (pipe_config->pixel_multiplier)
3803                 dotclock /= pipe_config->pixel_multiplier;
3804
3805         return dotclock;
3806 }
3807
3808 /* Returns the currently programmed mode of the given encoder. */
3809 struct drm_display_mode *
3810 intel_encoder_current_mode(struct intel_encoder *encoder)
3811 {
3812         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3813         struct intel_crtc_state *crtc_state;
3814         struct drm_display_mode *mode;
3815         struct intel_crtc *crtc;
3816         enum pipe pipe;
3817
3818         if (!encoder->get_hw_state(encoder, &pipe))
3819                 return NULL;
3820
3821         crtc = intel_crtc_for_pipe(dev_priv, pipe);
3822
3823         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3824         if (!mode)
3825                 return NULL;
3826
3827         crtc_state = intel_crtc_state_alloc(crtc);
3828         if (!crtc_state) {
3829                 kfree(mode);
3830                 return NULL;
3831         }
3832
3833         if (!intel_crtc_get_pipe_config(crtc_state)) {
3834                 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
3835                 kfree(mode);
3836                 return NULL;
3837         }
3838
3839         intel_encoder_get_config(encoder, crtc_state);
3840
3841         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
3842
3843         intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
3844
3845         return mode;
3846 }
3847
3848 static bool encoders_cloneable(const struct intel_encoder *a,
3849                                const struct intel_encoder *b)
3850 {
3851         /* masks could be asymmetric, so check both ways */
3852         return a == b || (a->cloneable & BIT(b->type) &&
3853                           b->cloneable & BIT(a->type));
3854 }
3855
3856 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
3857                                          struct intel_crtc *crtc,
3858                                          struct intel_encoder *encoder)
3859 {
3860         struct intel_encoder *source_encoder;
3861         struct drm_connector *connector;
3862         struct drm_connector_state *connector_state;
3863         int i;
3864
3865         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
3866                 if (connector_state->crtc != &crtc->base)
3867                         continue;
3868
3869                 source_encoder =
3870                         to_intel_encoder(connector_state->best_encoder);
3871                 if (!encoders_cloneable(encoder, source_encoder))
3872                         return false;
3873         }
3874
3875         return true;
3876 }
3877
3878 static int icl_add_linked_planes(struct intel_atomic_state *state)
3879 {
3880         struct intel_plane *plane, *linked;
3881         struct intel_plane_state *plane_state, *linked_plane_state;
3882         int i;
3883
3884         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3885                 linked = plane_state->planar_linked_plane;
3886
3887                 if (!linked)
3888                         continue;
3889
3890                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
3891                 if (IS_ERR(linked_plane_state))
3892                         return PTR_ERR(linked_plane_state);
3893
3894                 drm_WARN_ON(state->base.dev,
3895                             linked_plane_state->planar_linked_plane != plane);
3896                 drm_WARN_ON(state->base.dev,
3897                             linked_plane_state->planar_slave == plane_state->planar_slave);
3898         }
3899
3900         return 0;
3901 }
3902
3903 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
3904 {
3905         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3906         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3907         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
3908         struct intel_plane *plane, *linked;
3909         struct intel_plane_state *plane_state;
3910         int i;
3911
3912         if (DISPLAY_VER(dev_priv) < 11)
3913                 return 0;
3914
3915         /*
3916          * Destroy all old plane links and make the slave plane invisible
3917          * in the crtc_state->active_planes mask.
3918          */
3919         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3920                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
3921                         continue;
3922
3923                 plane_state->planar_linked_plane = NULL;
3924                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
3925                         crtc_state->enabled_planes &= ~BIT(plane->id);
3926                         crtc_state->active_planes &= ~BIT(plane->id);
3927                         crtc_state->update_planes |= BIT(plane->id);
3928                         crtc_state->data_rate[plane->id] = 0;
3929                         crtc_state->rel_data_rate[plane->id] = 0;
3930                 }
3931
3932                 plane_state->planar_slave = false;
3933         }
3934
3935         if (!crtc_state->nv12_planes)
3936                 return 0;
3937
3938         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3939                 struct intel_plane_state *linked_state = NULL;
3940
3941                 if (plane->pipe != crtc->pipe ||
3942                     !(crtc_state->nv12_planes & BIT(plane->id)))
3943                         continue;
3944
3945                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
3946                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
3947                                 continue;
3948
3949                         if (crtc_state->active_planes & BIT(linked->id))
3950                                 continue;
3951
3952                         linked_state = intel_atomic_get_plane_state(state, linked);
3953                         if (IS_ERR(linked_state))
3954                                 return PTR_ERR(linked_state);
3955
3956                         break;
3957                 }
3958
3959                 if (!linked_state) {
3960                         drm_dbg_kms(&dev_priv->drm,
3961                                     "Need %d free Y planes for planar YUV\n",
3962                                     hweight8(crtc_state->nv12_planes));
3963
3964                         return -EINVAL;
3965                 }
3966
3967                 plane_state->planar_linked_plane = linked;
3968
3969                 linked_state->planar_slave = true;
3970                 linked_state->planar_linked_plane = plane;
3971                 crtc_state->enabled_planes |= BIT(linked->id);
3972                 crtc_state->active_planes |= BIT(linked->id);
3973                 crtc_state->update_planes |= BIT(linked->id);
3974                 crtc_state->data_rate[linked->id] =
3975                         crtc_state->data_rate_y[plane->id];
3976                 crtc_state->rel_data_rate[linked->id] =
3977                         crtc_state->rel_data_rate_y[plane->id];
3978                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
3979                             linked->base.name, plane->base.name);
3980
3981                 /* Copy parameters to slave plane */
3982                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
3983                 linked_state->color_ctl = plane_state->color_ctl;
3984                 linked_state->view = plane_state->view;
3985                 linked_state->decrypt = plane_state->decrypt;
3986
3987                 intel_plane_copy_hw_state(linked_state, plane_state);
3988                 linked_state->uapi.src = plane_state->uapi.src;
3989                 linked_state->uapi.dst = plane_state->uapi.dst;
3990
3991                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
3992                         if (linked->id == PLANE_SPRITE5)
3993                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
3994                         else if (linked->id == PLANE_SPRITE4)
3995                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
3996                         else if (linked->id == PLANE_SPRITE3)
3997                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
3998                         else if (linked->id == PLANE_SPRITE2)
3999                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4000                         else
4001                                 MISSING_CASE(linked->id);
4002                 }
4003         }
4004
4005         return 0;
4006 }
4007
4008 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4009 {
4010         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4011         struct intel_atomic_state *state =
4012                 to_intel_atomic_state(new_crtc_state->uapi.state);
4013         const struct intel_crtc_state *old_crtc_state =
4014                 intel_atomic_get_old_crtc_state(state, crtc);
4015
4016         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4017 }
4018
4019 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4020 {
4021         const struct drm_display_mode *pipe_mode =
4022                 &crtc_state->hw.pipe_mode;
4023         int linetime_wm;
4024
4025         if (!crtc_state->hw.enable)
4026                 return 0;
4027
4028         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4029                                         pipe_mode->crtc_clock);
4030
4031         return min(linetime_wm, 0x1ff);
4032 }
4033
4034 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4035                                const struct intel_cdclk_state *cdclk_state)
4036 {
4037         const struct drm_display_mode *pipe_mode =
4038                 &crtc_state->hw.pipe_mode;
4039         int linetime_wm;
4040
4041         if (!crtc_state->hw.enable)
4042                 return 0;
4043
4044         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4045                                         cdclk_state->logical.cdclk);
4046
4047         return min(linetime_wm, 0x1ff);
4048 }
4049
4050 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4051 {
4052         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4053         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4054         const struct drm_display_mode *pipe_mode =
4055                 &crtc_state->hw.pipe_mode;
4056         int linetime_wm;
4057
4058         if (!crtc_state->hw.enable)
4059                 return 0;
4060
4061         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4062                                    crtc_state->pixel_rate);
4063
4064         /* Display WA #1135: BXT:ALL GLK:ALL */
4065         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4066             skl_watermark_ipc_enabled(dev_priv))
4067                 linetime_wm /= 2;
4068
4069         return min(linetime_wm, 0x1ff);
4070 }
4071
4072 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4073                                    struct intel_crtc *crtc)
4074 {
4075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4076         struct intel_crtc_state *crtc_state =
4077                 intel_atomic_get_new_crtc_state(state, crtc);
4078         const struct intel_cdclk_state *cdclk_state;
4079
4080         if (DISPLAY_VER(dev_priv) >= 9)
4081                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4082         else
4083                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4084
4085         if (!hsw_crtc_supports_ips(crtc))
4086                 return 0;
4087
4088         cdclk_state = intel_atomic_get_cdclk_state(state);
4089         if (IS_ERR(cdclk_state))
4090                 return PTR_ERR(cdclk_state);
4091
4092         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4093                                                        cdclk_state);
4094
4095         return 0;
4096 }
4097
4098 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4099                                    struct intel_crtc *crtc)
4100 {
4101         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4102         struct intel_crtc_state *crtc_state =
4103                 intel_atomic_get_new_crtc_state(state, crtc);
4104         int ret;
4105
4106         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4107             intel_crtc_needs_modeset(crtc_state) &&
4108             !crtc_state->hw.active)
4109                 crtc_state->update_wm_post = true;
4110
4111         if (intel_crtc_needs_modeset(crtc_state)) {
4112                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4113                 if (ret)
4114                         return ret;
4115         }
4116
4117         /*
4118          * May need to update pipe gamma enable bits
4119          * when C8 planes are getting enabled/disabled.
4120          */
4121         if (c8_planes_changed(crtc_state))
4122                 crtc_state->uapi.color_mgmt_changed = true;
4123
4124         if (intel_crtc_needs_color_update(crtc_state)) {
4125                 ret = intel_color_check(crtc_state);
4126                 if (ret)
4127                         return ret;
4128         }
4129
4130         ret = intel_compute_pipe_wm(state, crtc);
4131         if (ret) {
4132                 drm_dbg_kms(&dev_priv->drm,
4133                             "Target pipe watermarks are invalid\n");
4134                 return ret;
4135         }
4136
4137         /*
4138          * Calculate 'intermediate' watermarks that satisfy both the
4139          * old state and the new state.  We can program these
4140          * immediately.
4141          */
4142         ret = intel_compute_intermediate_wm(state, crtc);
4143         if (ret) {
4144                 drm_dbg_kms(&dev_priv->drm,
4145                             "No valid intermediate pipe watermarks are possible\n");
4146                 return ret;
4147         }
4148
4149         if (DISPLAY_VER(dev_priv) >= 9) {
4150                 if (intel_crtc_needs_modeset(crtc_state) ||
4151                     intel_crtc_needs_fastset(crtc_state)) {
4152                         ret = skl_update_scaler_crtc(crtc_state);
4153                         if (ret)
4154                                 return ret;
4155                 }
4156
4157                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4158                 if (ret)
4159                         return ret;
4160         }
4161
4162         if (HAS_IPS(dev_priv)) {
4163                 ret = hsw_ips_compute_config(state, crtc);
4164                 if (ret)
4165                         return ret;
4166         }
4167
4168         if (DISPLAY_VER(dev_priv) >= 9 ||
4169             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4170                 ret = hsw_compute_linetime_wm(state, crtc);
4171                 if (ret)
4172                         return ret;
4173
4174         }
4175
4176         ret = intel_psr2_sel_fetch_update(state, crtc);
4177         if (ret)
4178                 return ret;
4179
4180         return 0;
4181 }
4182
4183 static int
4184 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4185                       struct intel_crtc_state *crtc_state)
4186 {
4187         struct drm_connector *connector = conn_state->connector;
4188         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4189         const struct drm_display_info *info = &connector->display_info;
4190         int bpp;
4191
4192         switch (conn_state->max_bpc) {
4193         case 6 ... 7:
4194                 bpp = 6 * 3;
4195                 break;
4196         case 8 ... 9:
4197                 bpp = 8 * 3;
4198                 break;
4199         case 10 ... 11:
4200                 bpp = 10 * 3;
4201                 break;
4202         case 12 ... 16:
4203                 bpp = 12 * 3;
4204                 break;
4205         default:
4206                 MISSING_CASE(conn_state->max_bpc);
4207                 return -EINVAL;
4208         }
4209
4210         if (bpp < crtc_state->pipe_bpp) {
4211                 drm_dbg_kms(&i915->drm,
4212                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4213                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4214                             connector->base.id, connector->name,
4215                             bpp, 3 * info->bpc,
4216                             3 * conn_state->max_requested_bpc,
4217                             crtc_state->pipe_bpp);
4218
4219                 crtc_state->pipe_bpp = bpp;
4220         }
4221
4222         return 0;
4223 }
4224
4225 static int
4226 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4227                           struct intel_crtc *crtc)
4228 {
4229         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4230         struct intel_crtc_state *crtc_state =
4231                 intel_atomic_get_new_crtc_state(state, crtc);
4232         struct drm_connector *connector;
4233         struct drm_connector_state *connector_state;
4234         int bpp, i;
4235
4236         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4237             IS_CHERRYVIEW(dev_priv)))
4238                 bpp = 10*3;
4239         else if (DISPLAY_VER(dev_priv) >= 5)
4240                 bpp = 12*3;
4241         else
4242                 bpp = 8*3;
4243
4244         crtc_state->pipe_bpp = bpp;
4245
4246         /* Clamp display bpp to connector max bpp */
4247         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4248                 int ret;
4249
4250                 if (connector_state->crtc != &crtc->base)
4251                         continue;
4252
4253                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4254                 if (ret)
4255                         return ret;
4256         }
4257
4258         return 0;
4259 }
4260
4261 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4262 {
4263         struct drm_device *dev = state->base.dev;
4264         struct drm_connector *connector;
4265         struct drm_connector_list_iter conn_iter;
4266         unsigned int used_ports = 0;
4267         unsigned int used_mst_ports = 0;
4268         bool ret = true;
4269
4270         /*
4271          * We're going to peek into connector->state,
4272          * hence connection_mutex must be held.
4273          */
4274         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4275
4276         /*
4277          * Walk the connector list instead of the encoder
4278          * list to detect the problem on ddi platforms
4279          * where there's just one encoder per digital port.
4280          */
4281         drm_connector_list_iter_begin(dev, &conn_iter);
4282         drm_for_each_connector_iter(connector, &conn_iter) {
4283                 struct drm_connector_state *connector_state;
4284                 struct intel_encoder *encoder;
4285
4286                 connector_state =
4287                         drm_atomic_get_new_connector_state(&state->base,
4288                                                            connector);
4289                 if (!connector_state)
4290                         connector_state = connector->state;
4291
4292                 if (!connector_state->best_encoder)
4293                         continue;
4294
4295                 encoder = to_intel_encoder(connector_state->best_encoder);
4296
4297                 drm_WARN_ON(dev, !connector_state->crtc);
4298
4299                 switch (encoder->type) {
4300                 case INTEL_OUTPUT_DDI:
4301                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4302                                 break;
4303                         fallthrough;
4304                 case INTEL_OUTPUT_DP:
4305                 case INTEL_OUTPUT_HDMI:
4306                 case INTEL_OUTPUT_EDP:
4307                         /* the same port mustn't appear more than once */
4308                         if (used_ports & BIT(encoder->port))
4309                                 ret = false;
4310
4311                         used_ports |= BIT(encoder->port);
4312                         break;
4313                 case INTEL_OUTPUT_DP_MST:
4314                         used_mst_ports |=
4315                                 1 << encoder->port;
4316                         break;
4317                 default:
4318                         break;
4319                 }
4320         }
4321         drm_connector_list_iter_end(&conn_iter);
4322
4323         /* can't mix MST and SST/HDMI on the same port */
4324         if (used_ports & used_mst_ports)
4325                 return false;
4326
4327         return ret;
4328 }
4329
4330 static void
4331 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4332                                            struct intel_crtc *crtc)
4333 {
4334         struct intel_crtc_state *crtc_state =
4335                 intel_atomic_get_new_crtc_state(state, crtc);
4336
4337         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4338
4339         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4340                                   crtc_state->uapi.degamma_lut);
4341         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4342                                   crtc_state->uapi.gamma_lut);
4343         drm_property_replace_blob(&crtc_state->hw.ctm,
4344                                   crtc_state->uapi.ctm);
4345 }
4346
4347 static void
4348 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4349                                          struct intel_crtc *crtc)
4350 {
4351         struct intel_crtc_state *crtc_state =
4352                 intel_atomic_get_new_crtc_state(state, crtc);
4353
4354         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4355
4356         crtc_state->hw.enable = crtc_state->uapi.enable;
4357         crtc_state->hw.active = crtc_state->uapi.active;
4358         drm_mode_copy(&crtc_state->hw.mode,
4359                       &crtc_state->uapi.mode);
4360         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4361                       &crtc_state->uapi.adjusted_mode);
4362         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4363
4364         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4365 }
4366
4367 static void
4368 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4369                                     struct intel_crtc *slave_crtc)
4370 {
4371         struct intel_crtc_state *slave_crtc_state =
4372                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4373         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4374         const struct intel_crtc_state *master_crtc_state =
4375                 intel_atomic_get_new_crtc_state(state, master_crtc);
4376
4377         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4378                                   master_crtc_state->hw.degamma_lut);
4379         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4380                                   master_crtc_state->hw.gamma_lut);
4381         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4382                                   master_crtc_state->hw.ctm);
4383
4384         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4385 }
4386
4387 static int
4388 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4389                                   struct intel_crtc *slave_crtc)
4390 {
4391         struct intel_crtc_state *slave_crtc_state =
4392                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4393         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4394         const struct intel_crtc_state *master_crtc_state =
4395                 intel_atomic_get_new_crtc_state(state, master_crtc);
4396         struct intel_crtc_state *saved_state;
4397
4398         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4399                 slave_crtc_state->bigjoiner_pipes);
4400
4401         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4402         if (!saved_state)
4403                 return -ENOMEM;
4404
4405         /* preserve some things from the slave's original crtc state */
4406         saved_state->uapi = slave_crtc_state->uapi;
4407         saved_state->scaler_state = slave_crtc_state->scaler_state;
4408         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4409         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4410
4411         intel_crtc_free_hw_state(slave_crtc_state);
4412         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4413         kfree(saved_state);
4414
4415         /* Re-init hw state */
4416         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4417         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4418         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4419         drm_mode_copy(&slave_crtc_state->hw.mode,
4420                       &master_crtc_state->hw.mode);
4421         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4422                       &master_crtc_state->hw.pipe_mode);
4423         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4424                       &master_crtc_state->hw.adjusted_mode);
4425         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4426
4427         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4428
4429         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4430         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4431         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4432
4433         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4434                 slave_crtc_state->bigjoiner_pipes);
4435
4436         return 0;
4437 }
4438
4439 static int
4440 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4441                                  struct intel_crtc *crtc)
4442 {
4443         struct intel_crtc_state *crtc_state =
4444                 intel_atomic_get_new_crtc_state(state, crtc);
4445         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4446         struct intel_crtc_state *saved_state;
4447
4448         saved_state = intel_crtc_state_alloc(crtc);
4449         if (!saved_state)
4450                 return -ENOMEM;
4451
4452         /* free the old crtc_state->hw members */
4453         intel_crtc_free_hw_state(crtc_state);
4454
4455         /* FIXME: before the switch to atomic started, a new pipe_config was
4456          * kzalloc'd. Code that depends on any field being zero should be
4457          * fixed, so that the crtc_state can be safely duplicated. For now,
4458          * only fields that are know to not cause problems are preserved. */
4459
4460         saved_state->uapi = crtc_state->uapi;
4461         saved_state->inherited = crtc_state->inherited;
4462         saved_state->scaler_state = crtc_state->scaler_state;
4463         saved_state->shared_dpll = crtc_state->shared_dpll;
4464         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4465         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4466                sizeof(saved_state->icl_port_dplls));
4467         saved_state->crc_enabled = crtc_state->crc_enabled;
4468         if (IS_G4X(dev_priv) ||
4469             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4470                 saved_state->wm = crtc_state->wm;
4471
4472         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4473         kfree(saved_state);
4474
4475         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4476
4477         return 0;
4478 }
4479
4480 static int
4481 intel_modeset_pipe_config(struct intel_atomic_state *state,
4482                           struct intel_crtc *crtc,
4483                           const struct intel_link_bw_limits *limits)
4484 {
4485         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4486         struct intel_crtc_state *crtc_state =
4487                 intel_atomic_get_new_crtc_state(state, crtc);
4488         struct drm_connector *connector;
4489         struct drm_connector_state *connector_state;
4490         int pipe_src_w, pipe_src_h;
4491         int base_bpp, ret, i;
4492
4493         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4494
4495         crtc_state->framestart_delay = 1;
4496
4497         /*
4498          * Sanitize sync polarity flags based on requested ones. If neither
4499          * positive or negative polarity is requested, treat this as meaning
4500          * negative polarity.
4501          */
4502         if (!(crtc_state->hw.adjusted_mode.flags &
4503               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4504                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4505
4506         if (!(crtc_state->hw.adjusted_mode.flags &
4507               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4508                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4509
4510         ret = compute_baseline_pipe_bpp(state, crtc);
4511         if (ret)
4512                 return ret;
4513
4514         crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
4515         crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4516
4517         if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
4518                 drm_dbg_kms(&i915->drm,
4519                             "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
4520                             crtc->base.base.id, crtc->base.name,
4521                             BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
4522                 crtc_state->bw_constrained = true;
4523         }
4524
4525         base_bpp = crtc_state->pipe_bpp;
4526
4527         /*
4528          * Determine the real pipe dimensions. Note that stereo modes can
4529          * increase the actual pipe size due to the frame doubling and
4530          * insertion of additional space for blanks between the frame. This
4531          * is stored in the crtc timings. We use the requested mode to do this
4532          * computation to clearly distinguish it from the adjusted mode, which
4533          * can be changed by the connectors in the below retry loop.
4534          */
4535         drm_mode_get_hv_timing(&crtc_state->hw.mode,
4536                                &pipe_src_w, &pipe_src_h);
4537         drm_rect_init(&crtc_state->pipe_src, 0, 0,
4538                       pipe_src_w, pipe_src_h);
4539
4540         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4541                 struct intel_encoder *encoder =
4542                         to_intel_encoder(connector_state->best_encoder);
4543
4544                 if (connector_state->crtc != &crtc->base)
4545                         continue;
4546
4547                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4548                         drm_dbg_kms(&i915->drm,
4549                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4550                                     encoder->base.base.id, encoder->base.name);
4551                         return -EINVAL;
4552                 }
4553
4554                 /*
4555                  * Determine output_types before calling the .compute_config()
4556                  * hooks so that the hooks can use this information safely.
4557                  */
4558                 if (encoder->compute_output_type)
4559                         crtc_state->output_types |=
4560                                 BIT(encoder->compute_output_type(encoder, crtc_state,
4561                                                                  connector_state));
4562                 else
4563                         crtc_state->output_types |= BIT(encoder->type);
4564         }
4565
4566         /* Ensure the port clock defaults are reset when retrying. */
4567         crtc_state->port_clock = 0;
4568         crtc_state->pixel_multiplier = 1;
4569
4570         /* Fill in default crtc timings, allow encoders to overwrite them. */
4571         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4572                               CRTC_STEREO_DOUBLE);
4573
4574         /* Pass our mode to the connectors and the CRTC to give them a chance to
4575          * adjust it according to limitations or connector properties, and also
4576          * a chance to reject the mode entirely.
4577          */
4578         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4579                 struct intel_encoder *encoder =
4580                         to_intel_encoder(connector_state->best_encoder);
4581
4582                 if (connector_state->crtc != &crtc->base)
4583                         continue;
4584
4585                 ret = encoder->compute_config(encoder, crtc_state,
4586                                               connector_state);
4587                 if (ret == -EDEADLK)
4588                         return ret;
4589                 if (ret < 0) {
4590                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
4591                                     encoder->base.base.id, encoder->base.name, ret);
4592                         return ret;
4593                 }
4594         }
4595
4596         /* Set default port clock if not overwritten by the encoder. Needs to be
4597          * done afterwards in case the encoder adjusts the mode. */
4598         if (!crtc_state->port_clock)
4599                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4600                         * crtc_state->pixel_multiplier;
4601
4602         ret = intel_crtc_compute_config(state, crtc);
4603         if (ret == -EDEADLK)
4604                 return ret;
4605         if (ret < 0) {
4606                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
4607                             crtc->base.base.id, crtc->base.name, ret);
4608                 return ret;
4609         }
4610
4611         /* Dithering seems to not pass-through bits correctly when it should, so
4612          * only enable it on 6bpc panels and when its not a compliance
4613          * test requesting 6bpc video pattern.
4614          */
4615         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4616                 !crtc_state->dither_force_disable;
4617         drm_dbg_kms(&i915->drm,
4618                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4619                     crtc->base.base.id, crtc->base.name,
4620                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4621
4622         return 0;
4623 }
4624
4625 static int
4626 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4627                                struct intel_crtc *crtc)
4628 {
4629         struct intel_crtc_state *crtc_state =
4630                 intel_atomic_get_new_crtc_state(state, crtc);
4631         struct drm_connector_state *conn_state;
4632         struct drm_connector *connector;
4633         int i;
4634
4635         intel_bigjoiner_adjust_pipe_src(crtc_state);
4636
4637         for_each_new_connector_in_state(&state->base, connector,
4638                                         conn_state, i) {
4639                 struct intel_encoder *encoder =
4640                         to_intel_encoder(conn_state->best_encoder);
4641                 int ret;
4642
4643                 if (conn_state->crtc != &crtc->base ||
4644                     !encoder->compute_config_late)
4645                         continue;
4646
4647                 ret = encoder->compute_config_late(encoder, crtc_state,
4648                                                    conn_state);
4649                 if (ret)
4650                         return ret;
4651         }
4652
4653         return 0;
4654 }
4655
4656 bool intel_fuzzy_clock_check(int clock1, int clock2)
4657 {
4658         int diff;
4659
4660         if (clock1 == clock2)
4661                 return true;
4662
4663         if (!clock1 || !clock2)
4664                 return false;
4665
4666         diff = abs(clock1 - clock2);
4667
4668         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4669                 return true;
4670
4671         return false;
4672 }
4673
4674 static bool
4675 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4676                        const struct intel_link_m_n *m2_n2)
4677 {
4678         return m_n->tu == m2_n2->tu &&
4679                 m_n->data_m == m2_n2->data_m &&
4680                 m_n->data_n == m2_n2->data_n &&
4681                 m_n->link_m == m2_n2->link_m &&
4682                 m_n->link_n == m2_n2->link_n;
4683 }
4684
4685 static bool
4686 intel_compare_infoframe(const union hdmi_infoframe *a,
4687                         const union hdmi_infoframe *b)
4688 {
4689         return memcmp(a, b, sizeof(*a)) == 0;
4690 }
4691
4692 static bool
4693 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4694                          const struct drm_dp_vsc_sdp *b)
4695 {
4696         return memcmp(a, b, sizeof(*a)) == 0;
4697 }
4698
4699 static bool
4700 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4701 {
4702         return memcmp(a, b, len) == 0;
4703 }
4704
4705 static void
4706 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
4707                                bool fastset, const char *name,
4708                                const union hdmi_infoframe *a,
4709                                const union hdmi_infoframe *b)
4710 {
4711         if (fastset) {
4712                 if (!drm_debug_enabled(DRM_UT_KMS))
4713                         return;
4714
4715                 drm_dbg_kms(&dev_priv->drm,
4716                             "fastset requirement not met in %s infoframe\n", name);
4717                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4718                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
4719                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4720                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
4721         } else {
4722                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
4723                 drm_err(&dev_priv->drm, "expected:\n");
4724                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
4725                 drm_err(&dev_priv->drm, "found:\n");
4726                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
4727         }
4728 }
4729
4730 static void
4731 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
4732                                 bool fastset, const char *name,
4733                                 const struct drm_dp_vsc_sdp *a,
4734                                 const struct drm_dp_vsc_sdp *b)
4735 {
4736         if (fastset) {
4737                 if (!drm_debug_enabled(DRM_UT_KMS))
4738                         return;
4739
4740                 drm_dbg_kms(&dev_priv->drm,
4741                             "fastset requirement not met in %s dp sdp\n", name);
4742                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4743                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
4744                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4745                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
4746         } else {
4747                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
4748                 drm_err(&dev_priv->drm, "expected:\n");
4749                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
4750                 drm_err(&dev_priv->drm, "found:\n");
4751                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
4752         }
4753 }
4754
4755 /* Returns the length up to and including the last differing byte */
4756 static size_t
4757 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4758 {
4759         int i;
4760
4761         for (i = len - 1; i >= 0; i--) {
4762                 if (a[i] != b[i])
4763                         return i + 1;
4764         }
4765
4766         return 0;
4767 }
4768
4769 static void
4770 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
4771                             bool fastset, const char *name,
4772                             const u8 *a, const u8 *b, size_t len)
4773 {
4774         if (fastset) {
4775                 if (!drm_debug_enabled(DRM_UT_KMS))
4776                         return;
4777
4778                 /* only dump up to the last difference */
4779                 len = memcmp_diff_len(a, b, len);
4780
4781                 drm_dbg_kms(&dev_priv->drm,
4782                             "fastset requirement not met in %s buffer\n", name);
4783                 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
4784                                16, 0, a, len, false);
4785                 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
4786                                16, 0, b, len, false);
4787         } else {
4788                 /* only dump up to the last difference */
4789                 len = memcmp_diff_len(a, b, len);
4790
4791                 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
4792                 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
4793                                16, 0, a, len, false);
4794                 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
4795                                16, 0, b, len, false);
4796         }
4797 }
4798
4799 static void __printf(4, 5)
4800 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
4801                      const char *name, const char *format, ...)
4802 {
4803         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4804         struct va_format vaf;
4805         va_list args;
4806
4807         va_start(args, format);
4808         vaf.fmt = format;
4809         vaf.va = &args;
4810
4811         if (fastset)
4812                 drm_dbg_kms(&i915->drm,
4813                             "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4814                             crtc->base.base.id, crtc->base.name, name, &vaf);
4815         else
4816                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
4817                         crtc->base.base.id, crtc->base.name, name, &vaf);
4818
4819         va_end(args);
4820 }
4821
4822 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
4823 {
4824         /* Enable fastboot by default on Skylake and newer */
4825         if (DISPLAY_VER(dev_priv) >= 9)
4826                 return true;
4827
4828         /* Enable fastboot by default on VLV and CHV */
4829         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4830                 return true;
4831
4832         /* Disabled by default on all others */
4833         return false;
4834 }
4835
4836 bool
4837 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
4838                           const struct intel_crtc_state *pipe_config,
4839                           bool fastset)
4840 {
4841         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
4842         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4843         bool ret = true;
4844         bool fixup_inherited = fastset &&
4845                 current_config->inherited && !pipe_config->inherited;
4846
4847         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
4848                 drm_dbg_kms(&dev_priv->drm,
4849                             "initial modeset and fastboot not set\n");
4850                 ret = false;
4851         }
4852
4853 #define PIPE_CONF_CHECK_X(name) do { \
4854         if (current_config->name != pipe_config->name) { \
4855                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4856                                      "(expected 0x%08x, found 0x%08x)", \
4857                                      current_config->name, \
4858                                      pipe_config->name); \
4859                 ret = false; \
4860         } \
4861 } while (0)
4862
4863 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
4864         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
4865                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4866                                      "(expected 0x%08x, found 0x%08x)", \
4867                                      current_config->name & (mask), \
4868                                      pipe_config->name & (mask)); \
4869                 ret = false; \
4870         } \
4871 } while (0)
4872
4873 #define PIPE_CONF_CHECK_I(name) do { \
4874         if (current_config->name != pipe_config->name) { \
4875                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4876                                      "(expected %i, found %i)", \
4877                                      current_config->name, \
4878                                      pipe_config->name); \
4879                 ret = false; \
4880         } \
4881 } while (0)
4882
4883 #define PIPE_CONF_CHECK_BOOL(name) do { \
4884         if (current_config->name != pipe_config->name) { \
4885                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
4886                                      "(expected %s, found %s)", \
4887                                      str_yes_no(current_config->name), \
4888                                      str_yes_no(pipe_config->name)); \
4889                 ret = false; \
4890         } \
4891 } while (0)
4892
4893 /*
4894  * Checks state where we only read out the enabling, but not the entire
4895  * state itself (like full infoframes or ELD for audio). These states
4896  * require a full modeset on bootup to fix up.
4897  */
4898 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
4899         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
4900                 PIPE_CONF_CHECK_BOOL(name); \
4901         } else { \
4902                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4903                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
4904                                      str_yes_no(current_config->name), \
4905                                      str_yes_no(pipe_config->name)); \
4906                 ret = false; \
4907         } \
4908 } while (0)
4909
4910 #define PIPE_CONF_CHECK_P(name) do { \
4911         if (current_config->name != pipe_config->name) { \
4912                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4913                                      "(expected %p, found %p)", \
4914                                      current_config->name, \
4915                                      pipe_config->name); \
4916                 ret = false; \
4917         } \
4918 } while (0)
4919
4920 #define PIPE_CONF_CHECK_M_N(name) do { \
4921         if (!intel_compare_link_m_n(&current_config->name, \
4922                                     &pipe_config->name)) { \
4923                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4924                                      "(expected tu %i data %i/%i link %i/%i, " \
4925                                      "found tu %i, data %i/%i link %i/%i)", \
4926                                      current_config->name.tu, \
4927                                      current_config->name.data_m, \
4928                                      current_config->name.data_n, \
4929                                      current_config->name.link_m, \
4930                                      current_config->name.link_n, \
4931                                      pipe_config->name.tu, \
4932                                      pipe_config->name.data_m, \
4933                                      pipe_config->name.data_n, \
4934                                      pipe_config->name.link_m, \
4935                                      pipe_config->name.link_n); \
4936                 ret = false; \
4937         } \
4938 } while (0)
4939
4940 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
4941         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
4942         PIPE_CONF_CHECK_I(name.crtc_htotal); \
4943         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
4944         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
4945         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
4946         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
4947         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
4948         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
4949         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
4950         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
4951         if (!fastset || !pipe_config->update_lrr) { \
4952                 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
4953                 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
4954         } \
4955 } while (0)
4956
4957 #define PIPE_CONF_CHECK_RECT(name) do { \
4958         PIPE_CONF_CHECK_I(name.x1); \
4959         PIPE_CONF_CHECK_I(name.x2); \
4960         PIPE_CONF_CHECK_I(name.y1); \
4961         PIPE_CONF_CHECK_I(name.y2); \
4962 } while (0)
4963
4964 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
4965         if ((current_config->name ^ pipe_config->name) & (mask)) { \
4966                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4967                                      "(%x) (expected %i, found %i)", \
4968                                      (mask), \
4969                                      current_config->name & (mask), \
4970                                      pipe_config->name & (mask)); \
4971                 ret = false; \
4972         } \
4973 } while (0)
4974
4975 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
4976         if (!intel_compare_infoframe(&current_config->infoframes.name, \
4977                                      &pipe_config->infoframes.name)) { \
4978                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
4979                                                &current_config->infoframes.name, \
4980                                                &pipe_config->infoframes.name); \
4981                 ret = false; \
4982         } \
4983 } while (0)
4984
4985 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
4986         if (!current_config->has_psr && !pipe_config->has_psr && \
4987             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
4988                                       &pipe_config->infoframes.name)) { \
4989                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
4990                                                 &current_config->infoframes.name, \
4991                                                 &pipe_config->infoframes.name); \
4992                 ret = false; \
4993         } \
4994 } while (0)
4995
4996 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
4997         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
4998         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
4999         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5000                 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5001                                             current_config->name, \
5002                                             pipe_config->name, \
5003                                             (len)); \
5004                 ret = false; \
5005         } \
5006 } while (0)
5007
5008 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5009         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5010             !intel_color_lut_equal(current_config, \
5011                                    current_config->lut, pipe_config->lut, \
5012                                    is_pre_csc_lut)) {   \
5013                 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5014                                      "hw_state doesn't match sw_state"); \
5015                 ret = false; \
5016         } \
5017 } while (0)
5018
5019 #define PIPE_CONF_CHECK_CSC(name) do { \
5020         PIPE_CONF_CHECK_X(name.preoff[0]); \
5021         PIPE_CONF_CHECK_X(name.preoff[1]); \
5022         PIPE_CONF_CHECK_X(name.preoff[2]); \
5023         PIPE_CONF_CHECK_X(name.coeff[0]); \
5024         PIPE_CONF_CHECK_X(name.coeff[1]); \
5025         PIPE_CONF_CHECK_X(name.coeff[2]); \
5026         PIPE_CONF_CHECK_X(name.coeff[3]); \
5027         PIPE_CONF_CHECK_X(name.coeff[4]); \
5028         PIPE_CONF_CHECK_X(name.coeff[5]); \
5029         PIPE_CONF_CHECK_X(name.coeff[6]); \
5030         PIPE_CONF_CHECK_X(name.coeff[7]); \
5031         PIPE_CONF_CHECK_X(name.coeff[8]); \
5032         PIPE_CONF_CHECK_X(name.postoff[0]); \
5033         PIPE_CONF_CHECK_X(name.postoff[1]); \
5034         PIPE_CONF_CHECK_X(name.postoff[2]); \
5035 } while (0)
5036
5037 #define PIPE_CONF_QUIRK(quirk) \
5038         ((current_config->quirks | pipe_config->quirks) & (quirk))
5039
5040         PIPE_CONF_CHECK_I(hw.enable);
5041         PIPE_CONF_CHECK_I(hw.active);
5042
5043         PIPE_CONF_CHECK_I(cpu_transcoder);
5044         PIPE_CONF_CHECK_I(mst_master_transcoder);
5045
5046         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5047         PIPE_CONF_CHECK_I(fdi_lanes);
5048         PIPE_CONF_CHECK_M_N(fdi_m_n);
5049
5050         PIPE_CONF_CHECK_I(lane_count);
5051         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5052
5053         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5054                 if (!fastset || !pipe_config->update_m_n)
5055                         PIPE_CONF_CHECK_M_N(dp_m_n);
5056         } else {
5057                 PIPE_CONF_CHECK_M_N(dp_m_n);
5058                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5059         }
5060
5061         PIPE_CONF_CHECK_X(output_types);
5062
5063         PIPE_CONF_CHECK_I(framestart_delay);
5064         PIPE_CONF_CHECK_I(msa_timing_delay);
5065
5066         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5067         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5068
5069         PIPE_CONF_CHECK_I(pixel_multiplier);
5070
5071         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5072                               DRM_MODE_FLAG_INTERLACE);
5073
5074         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5075                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5076                                       DRM_MODE_FLAG_PHSYNC);
5077                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5078                                       DRM_MODE_FLAG_NHSYNC);
5079                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5080                                       DRM_MODE_FLAG_PVSYNC);
5081                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5082                                       DRM_MODE_FLAG_NVSYNC);
5083         }
5084
5085         PIPE_CONF_CHECK_I(output_format);
5086         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5087         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5088             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5089                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5090
5091         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5092         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5093         PIPE_CONF_CHECK_BOOL(has_infoframe);
5094         PIPE_CONF_CHECK_BOOL(enhanced_framing);
5095         PIPE_CONF_CHECK_BOOL(fec_enable);
5096
5097         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5098         PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5099
5100         PIPE_CONF_CHECK_X(gmch_pfit.control);
5101         /* pfit ratios are autocomputed by the hw on gen4+ */
5102         if (DISPLAY_VER(dev_priv) < 4)
5103                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5104         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5105
5106         /*
5107          * Changing the EDP transcoder input mux
5108          * (A_ONOFF vs. A_ON) requires a full modeset.
5109          */
5110         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5111
5112         if (!fastset) {
5113                 PIPE_CONF_CHECK_RECT(pipe_src);
5114
5115                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5116                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5117
5118                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5119                 PIPE_CONF_CHECK_I(pixel_rate);
5120
5121                 PIPE_CONF_CHECK_X(gamma_mode);
5122                 if (IS_CHERRYVIEW(dev_priv))
5123                         PIPE_CONF_CHECK_X(cgm_mode);
5124                 else
5125                         PIPE_CONF_CHECK_X(csc_mode);
5126                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5127                 PIPE_CONF_CHECK_BOOL(csc_enable);
5128                 PIPE_CONF_CHECK_BOOL(wgc_enable);
5129
5130                 PIPE_CONF_CHECK_I(linetime);
5131                 PIPE_CONF_CHECK_I(ips_linetime);
5132
5133                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5134                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5135
5136                 PIPE_CONF_CHECK_CSC(csc);
5137                 PIPE_CONF_CHECK_CSC(output_csc);
5138
5139                 if (current_config->active_planes) {
5140                         PIPE_CONF_CHECK_BOOL(has_psr);
5141                         PIPE_CONF_CHECK_BOOL(has_psr2);
5142                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5143                         PIPE_CONF_CHECK_I(dc3co_exitline);
5144                 }
5145         }
5146
5147         PIPE_CONF_CHECK_BOOL(double_wide);
5148
5149         if (dev_priv->display.dpll.mgr) {
5150                 PIPE_CONF_CHECK_P(shared_dpll);
5151
5152                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5153                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5154                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5155                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5156                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5157                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5158                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5159                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5160                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5161                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5162                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5163                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5164                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5165                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5166                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5167                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5168                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5169                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5170                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5171                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5172                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5173                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5174                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5175                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5176                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5177                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5178                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5179                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5180                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5181                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5182                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5183                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5184         }
5185
5186         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5187         PIPE_CONF_CHECK_X(dsi_pll.div);
5188
5189         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5190                 PIPE_CONF_CHECK_I(pipe_bpp);
5191
5192         if (!fastset || !pipe_config->update_m_n) {
5193                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5194                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5195         }
5196         PIPE_CONF_CHECK_I(port_clock);
5197
5198         PIPE_CONF_CHECK_I(min_voltage_level);
5199
5200         if (current_config->has_psr || pipe_config->has_psr)
5201                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5202                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5203         else
5204                 PIPE_CONF_CHECK_X(infoframes.enable);
5205
5206         PIPE_CONF_CHECK_X(infoframes.gcp);
5207         PIPE_CONF_CHECK_INFOFRAME(avi);
5208         PIPE_CONF_CHECK_INFOFRAME(spd);
5209         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5210         PIPE_CONF_CHECK_INFOFRAME(drm);
5211         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5212
5213         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5214         PIPE_CONF_CHECK_I(master_transcoder);
5215         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5216
5217         PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5218         PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5219         PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5220         PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5221         PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5222         PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5223         PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5224         PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5225         PIPE_CONF_CHECK_I(dsc.config.pic_width);
5226         PIPE_CONF_CHECK_I(dsc.config.pic_height);
5227         PIPE_CONF_CHECK_I(dsc.config.slice_width);
5228         PIPE_CONF_CHECK_I(dsc.config.slice_height);
5229         PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5230         PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5231         PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5232         PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5233         PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5234         PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5235         PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5236         PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5237         PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5238         PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5239         PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5240         PIPE_CONF_CHECK_I(dsc.config.final_offset);
5241         PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5242         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5243         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5244         PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5245         PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5246         PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5247
5248         PIPE_CONF_CHECK_I(dsc.compression_enable);
5249         PIPE_CONF_CHECK_I(dsc.dsc_split);
5250         PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5251
5252         PIPE_CONF_CHECK_BOOL(splitter.enable);
5253         PIPE_CONF_CHECK_I(splitter.link_count);
5254         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5255
5256         if (!fastset) {
5257                 PIPE_CONF_CHECK_BOOL(vrr.enable);
5258                 PIPE_CONF_CHECK_I(vrr.vmin);
5259                 PIPE_CONF_CHECK_I(vrr.vmax);
5260                 PIPE_CONF_CHECK_I(vrr.flipline);
5261                 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5262                 PIPE_CONF_CHECK_I(vrr.guardband);
5263         }
5264
5265 #undef PIPE_CONF_CHECK_X
5266 #undef PIPE_CONF_CHECK_I
5267 #undef PIPE_CONF_CHECK_BOOL
5268 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5269 #undef PIPE_CONF_CHECK_P
5270 #undef PIPE_CONF_CHECK_FLAGS
5271 #undef PIPE_CONF_CHECK_COLOR_LUT
5272 #undef PIPE_CONF_CHECK_TIMINGS
5273 #undef PIPE_CONF_CHECK_RECT
5274 #undef PIPE_CONF_QUIRK
5275
5276         return ret;
5277 }
5278
5279 static void
5280 intel_verify_planes(struct intel_atomic_state *state)
5281 {
5282         struct intel_plane *plane;
5283         const struct intel_plane_state *plane_state;
5284         int i;
5285
5286         for_each_new_intel_plane_in_state(state, plane,
5287                                           plane_state, i)
5288                 assert_plane(plane, plane_state->planar_slave ||
5289                              plane_state->uapi.visible);
5290 }
5291
5292 static int intel_modeset_pipe(struct intel_atomic_state *state,
5293                               struct intel_crtc_state *crtc_state,
5294                               const char *reason)
5295 {
5296         struct drm_i915_private *i915 = to_i915(state->base.dev);
5297         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5298         int ret;
5299
5300         drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5301                     crtc->base.base.id, crtc->base.name, reason);
5302
5303         ret = drm_atomic_add_affected_connectors(&state->base,
5304                                                  &crtc->base);
5305         if (ret)
5306                 return ret;
5307
5308         ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5309         if (ret)
5310                 return ret;
5311
5312         ret = intel_atomic_add_affected_planes(state, crtc);
5313         if (ret)
5314                 return ret;
5315
5316         crtc_state->uapi.mode_changed = true;
5317
5318         return 0;
5319 }
5320
5321 /**
5322  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5323  * @state: intel atomic state
5324  * @reason: the reason for the full modeset
5325  * @mask: mask of pipes to modeset
5326  *
5327  * Add pipes in @mask to @state and force a full modeset on the enabled ones
5328  * due to the description in @reason.
5329  * This function can be called only before new plane states are computed.
5330  *
5331  * Returns 0 in case of success, negative error code otherwise.
5332  */
5333 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5334                                       const char *reason, u8 mask)
5335 {
5336         struct drm_i915_private *i915 = to_i915(state->base.dev);
5337         struct intel_crtc *crtc;
5338
5339         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
5340                 struct intel_crtc_state *crtc_state;
5341                 int ret;
5342
5343                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5344                 if (IS_ERR(crtc_state))
5345                         return PTR_ERR(crtc_state);
5346
5347                 if (!crtc_state->hw.enable ||
5348                     intel_crtc_needs_modeset(crtc_state))
5349                         continue;
5350
5351                 ret = intel_modeset_pipe(state, crtc_state, reason);
5352                 if (ret)
5353                         return ret;
5354         }
5355
5356         return 0;
5357 }
5358
5359 static void
5360 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5361 {
5362         crtc_state->uapi.mode_changed = true;
5363
5364         crtc_state->update_pipe = false;
5365         crtc_state->update_m_n = false;
5366         crtc_state->update_lrr = false;
5367 }
5368
5369 /**
5370  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5371  * @state: intel atomic state
5372  * @reason: the reason for the full modeset
5373  *
5374  * Add all pipes to @state and force a full modeset on the active ones due to
5375  * the description in @reason.
5376  * This function can be called only after new plane states are computed already.
5377  *
5378  * Returns 0 in case of success, negative error code otherwise.
5379  */
5380 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5381                                  const char *reason)
5382 {
5383         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5384         struct intel_crtc *crtc;
5385
5386         for_each_intel_crtc(&dev_priv->drm, crtc) {
5387                 struct intel_crtc_state *crtc_state;
5388                 int ret;
5389
5390                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5391                 if (IS_ERR(crtc_state))
5392                         return PTR_ERR(crtc_state);
5393
5394                 if (!crtc_state->hw.active ||
5395                     intel_crtc_needs_modeset(crtc_state))
5396                         continue;
5397
5398                 ret = intel_modeset_pipe(state, crtc_state, reason);
5399                 if (ret)
5400                         return ret;
5401
5402                 intel_crtc_flag_modeset(crtc_state);
5403
5404                 crtc_state->update_planes |= crtc_state->active_planes;
5405                 crtc_state->async_flip_planes = 0;
5406                 crtc_state->do_async_flip = false;
5407         }
5408
5409         return 0;
5410 }
5411
5412 /*
5413  * This implements the workaround described in the "notes" section of the mode
5414  * set sequence documentation. When going from no pipes or single pipe to
5415  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5416  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5417  */
5418 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5419 {
5420         struct intel_crtc_state *crtc_state;
5421         struct intel_crtc *crtc;
5422         struct intel_crtc_state *first_crtc_state = NULL;
5423         struct intel_crtc_state *other_crtc_state = NULL;
5424         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5425         int i;
5426
5427         /* look at all crtc's that are going to be enabled in during modeset */
5428         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5429                 if (!crtc_state->hw.active ||
5430                     !intel_crtc_needs_modeset(crtc_state))
5431                         continue;
5432
5433                 if (first_crtc_state) {
5434                         other_crtc_state = crtc_state;
5435                         break;
5436                 } else {
5437                         first_crtc_state = crtc_state;
5438                         first_pipe = crtc->pipe;
5439                 }
5440         }
5441
5442         /* No workaround needed? */
5443         if (!first_crtc_state)
5444                 return 0;
5445
5446         /* w/a possibly needed, check how many crtc's are already enabled. */
5447         for_each_intel_crtc(state->base.dev, crtc) {
5448                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5449                 if (IS_ERR(crtc_state))
5450                         return PTR_ERR(crtc_state);
5451
5452                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5453
5454                 if (!crtc_state->hw.active ||
5455                     intel_crtc_needs_modeset(crtc_state))
5456                         continue;
5457
5458                 /* 2 or more enabled crtcs means no need for w/a */
5459                 if (enabled_pipe != INVALID_PIPE)
5460                         return 0;
5461
5462                 enabled_pipe = crtc->pipe;
5463         }
5464
5465         if (enabled_pipe != INVALID_PIPE)
5466                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5467         else if (other_crtc_state)
5468                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5469
5470         return 0;
5471 }
5472
5473 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5474                            u8 active_pipes)
5475 {
5476         const struct intel_crtc_state *crtc_state;
5477         struct intel_crtc *crtc;
5478         int i;
5479
5480         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5481                 if (crtc_state->hw.active)
5482                         active_pipes |= BIT(crtc->pipe);
5483                 else
5484                         active_pipes &= ~BIT(crtc->pipe);
5485         }
5486
5487         return active_pipes;
5488 }
5489
5490 static int intel_modeset_checks(struct intel_atomic_state *state)
5491 {
5492         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5493
5494         state->modeset = true;
5495
5496         if (IS_HASWELL(dev_priv))
5497                 return hsw_mode_set_planes_workaround(state);
5498
5499         return 0;
5500 }
5501
5502 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5503                                      struct intel_crtc_state *new_crtc_state)
5504 {
5505         struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
5506
5507         /* only allow LRR when the timings stay within the VRR range */
5508         if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5509                 new_crtc_state->update_lrr = false;
5510
5511         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5512                 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
5513         else
5514                 new_crtc_state->uapi.mode_changed = false;
5515
5516         if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5517                                    &new_crtc_state->dp_m_n))
5518                 new_crtc_state->update_m_n = false;
5519
5520         if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
5521              old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
5522                 new_crtc_state->update_lrr = false;
5523
5524         if (intel_crtc_needs_modeset(new_crtc_state))
5525                 intel_crtc_flag_modeset(new_crtc_state);
5526         else
5527                 new_crtc_state->update_pipe = true;
5528 }
5529
5530 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5531                                           struct intel_crtc *crtc,
5532                                           u8 plane_ids_mask)
5533 {
5534         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5535         struct intel_plane *plane;
5536
5537         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5538                 struct intel_plane_state *plane_state;
5539
5540                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5541                         continue;
5542
5543                 plane_state = intel_atomic_get_plane_state(state, plane);
5544                 if (IS_ERR(plane_state))
5545                         return PTR_ERR(plane_state);
5546         }
5547
5548         return 0;
5549 }
5550
5551 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5552                                      struct intel_crtc *crtc)
5553 {
5554         const struct intel_crtc_state *old_crtc_state =
5555                 intel_atomic_get_old_crtc_state(state, crtc);
5556         const struct intel_crtc_state *new_crtc_state =
5557                 intel_atomic_get_new_crtc_state(state, crtc);
5558
5559         return intel_crtc_add_planes_to_state(state, crtc,
5560                                               old_crtc_state->enabled_planes |
5561                                               new_crtc_state->enabled_planes);
5562 }
5563
5564 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5565 {
5566         /* See {hsw,vlv,ivb}_plane_ratio() */
5567         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5568                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5569                 IS_IVYBRIDGE(dev_priv);
5570 }
5571
5572 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5573                                            struct intel_crtc *crtc,
5574                                            struct intel_crtc *other)
5575 {
5576         const struct intel_plane_state __maybe_unused *plane_state;
5577         struct intel_plane *plane;
5578         u8 plane_ids = 0;
5579         int i;
5580
5581         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5582                 if (plane->pipe == crtc->pipe)
5583                         plane_ids |= BIT(plane->id);
5584         }
5585
5586         return intel_crtc_add_planes_to_state(state, other, plane_ids);
5587 }
5588
5589 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
5590 {
5591         struct drm_i915_private *i915 = to_i915(state->base.dev);
5592         const struct intel_crtc_state *crtc_state;
5593         struct intel_crtc *crtc;
5594         int i;
5595
5596         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5597                 struct intel_crtc *other;
5598
5599                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5600                                                  crtc_state->bigjoiner_pipes) {
5601                         int ret;
5602
5603                         if (crtc == other)
5604                                 continue;
5605
5606                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
5607                         if (ret)
5608                                 return ret;
5609                 }
5610         }
5611
5612         return 0;
5613 }
5614
5615 static int intel_atomic_check_planes(struct intel_atomic_state *state)
5616 {
5617         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5618         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5619         struct intel_plane_state __maybe_unused *plane_state;
5620         struct intel_plane *plane;
5621         struct intel_crtc *crtc;
5622         int i, ret;
5623
5624         ret = icl_add_linked_planes(state);
5625         if (ret)
5626                 return ret;
5627
5628         ret = intel_bigjoiner_add_affected_planes(state);
5629         if (ret)
5630                 return ret;
5631
5632         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5633                 ret = intel_plane_atomic_check(state, plane);
5634                 if (ret) {
5635                         drm_dbg_atomic(&dev_priv->drm,
5636                                        "[PLANE:%d:%s] atomic driver check failed\n",
5637                                        plane->base.base.id, plane->base.name);
5638                         return ret;
5639                 }
5640         }
5641
5642         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5643                                             new_crtc_state, i) {
5644                 u8 old_active_planes, new_active_planes;
5645
5646                 ret = icl_check_nv12_planes(new_crtc_state);
5647                 if (ret)
5648                         return ret;
5649
5650                 /*
5651                  * On some platforms the number of active planes affects
5652                  * the planes' minimum cdclk calculation. Add such planes
5653                  * to the state before we compute the minimum cdclk.
5654                  */
5655                 if (!active_planes_affects_min_cdclk(dev_priv))
5656                         continue;
5657
5658                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5659                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5660
5661                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
5662                         continue;
5663
5664                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
5665                 if (ret)
5666                         return ret;
5667         }
5668
5669         return 0;
5670 }
5671
5672 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5673 {
5674         struct intel_crtc_state __maybe_unused *crtc_state;
5675         struct intel_crtc *crtc;
5676         int i;
5677
5678         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5679                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5680                 int ret;
5681
5682                 ret = intel_crtc_atomic_check(state, crtc);
5683                 if (ret) {
5684                         drm_dbg_atomic(&i915->drm,
5685                                        "[CRTC:%d:%s] atomic driver check failed\n",
5686                                        crtc->base.base.id, crtc->base.name);
5687                         return ret;
5688                 }
5689         }
5690
5691         return 0;
5692 }
5693
5694 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5695                                                u8 transcoders)
5696 {
5697         const struct intel_crtc_state *new_crtc_state;
5698         struct intel_crtc *crtc;
5699         int i;
5700
5701         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5702                 if (new_crtc_state->hw.enable &&
5703                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5704                     intel_crtc_needs_modeset(new_crtc_state))
5705                         return true;
5706         }
5707
5708         return false;
5709 }
5710
5711 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5712                                      u8 pipes)
5713 {
5714         const struct intel_crtc_state *new_crtc_state;
5715         struct intel_crtc *crtc;
5716         int i;
5717
5718         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5719                 if (new_crtc_state->hw.enable &&
5720                     pipes & BIT(crtc->pipe) &&
5721                     intel_crtc_needs_modeset(new_crtc_state))
5722                         return true;
5723         }
5724
5725         return false;
5726 }
5727
5728 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
5729                                         struct intel_crtc *master_crtc)
5730 {
5731         struct drm_i915_private *i915 = to_i915(state->base.dev);
5732         struct intel_crtc_state *master_crtc_state =
5733                 intel_atomic_get_new_crtc_state(state, master_crtc);
5734         struct intel_crtc *slave_crtc;
5735
5736         if (!master_crtc_state->bigjoiner_pipes)
5737                 return 0;
5738
5739         /* sanity check */
5740         if (drm_WARN_ON(&i915->drm,
5741                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
5742                 return -EINVAL;
5743
5744         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
5745                 drm_dbg_kms(&i915->drm,
5746                             "[CRTC:%d:%s] Cannot act as big joiner master "
5747                             "(need 0x%x as pipes, only 0x%x possible)\n",
5748                             master_crtc->base.base.id, master_crtc->base.name,
5749                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
5750                 return -EINVAL;
5751         }
5752
5753         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5754                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5755                 struct intel_crtc_state *slave_crtc_state;
5756                 int ret;
5757
5758                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
5759                 if (IS_ERR(slave_crtc_state))
5760                         return PTR_ERR(slave_crtc_state);
5761
5762                 /* master being enabled, slave was already configured? */
5763                 if (slave_crtc_state->uapi.enable) {
5764                         drm_dbg_kms(&i915->drm,
5765                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5766                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5767                                     slave_crtc->base.base.id, slave_crtc->base.name,
5768                                     master_crtc->base.base.id, master_crtc->base.name);
5769                         return -EINVAL;
5770                 }
5771
5772                 /*
5773                  * The state copy logic assumes the master crtc gets processed
5774                  * before the slave crtc during the main compute_config loop.
5775                  * This works because the crtcs are created in pipe order,
5776                  * and the hardware requires master pipe < slave pipe as well.
5777                  * Should that change we need to rethink the logic.
5778                  */
5779                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
5780                             drm_crtc_index(&slave_crtc->base)))
5781                         return -EINVAL;
5782
5783                 drm_dbg_kms(&i915->drm,
5784                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5785                             slave_crtc->base.base.id, slave_crtc->base.name,
5786                             master_crtc->base.base.id, master_crtc->base.name);
5787
5788                 slave_crtc_state->bigjoiner_pipes =
5789                         master_crtc_state->bigjoiner_pipes;
5790
5791                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
5792                 if (ret)
5793                         return ret;
5794         }
5795
5796         return 0;
5797 }
5798
5799 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
5800                                  struct intel_crtc *master_crtc)
5801 {
5802         struct drm_i915_private *i915 = to_i915(state->base.dev);
5803         struct intel_crtc_state *master_crtc_state =
5804                 intel_atomic_get_new_crtc_state(state, master_crtc);
5805         struct intel_crtc *slave_crtc;
5806
5807         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5808                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5809                 struct intel_crtc_state *slave_crtc_state =
5810                         intel_atomic_get_new_crtc_state(state, slave_crtc);
5811
5812                 slave_crtc_state->bigjoiner_pipes = 0;
5813
5814                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
5815         }
5816
5817         master_crtc_state->bigjoiner_pipes = 0;
5818 }
5819
5820 /**
5821  * DOC: asynchronous flip implementation
5822  *
5823  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5824  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5825  * Correspondingly, support is currently added for primary plane only.
5826  *
5827  * Async flip can only change the plane surface address, so anything else
5828  * changing is rejected from the intel_async_flip_check_hw() function.
5829  * Once this check is cleared, flip done interrupt is enabled using
5830  * the intel_crtc_enable_flip_done() function.
5831  *
5832  * As soon as the surface address register is written, flip done interrupt is
5833  * generated and the requested events are sent to the usersapce in the interrupt
5834  * handler itself. The timestamp and sequence sent during the flip done event
5835  * correspond to the last vblank and have no relation to the actual time when
5836  * the flip done event was sent.
5837  */
5838 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5839                                        struct intel_crtc *crtc)
5840 {
5841         struct drm_i915_private *i915 = to_i915(state->base.dev);
5842         const struct intel_crtc_state *new_crtc_state =
5843                 intel_atomic_get_new_crtc_state(state, crtc);
5844         const struct intel_plane_state *old_plane_state;
5845         struct intel_plane_state *new_plane_state;
5846         struct intel_plane *plane;
5847         int i;
5848
5849         if (!new_crtc_state->uapi.async_flip)
5850                 return 0;
5851
5852         if (!new_crtc_state->uapi.active) {
5853                 drm_dbg_kms(&i915->drm,
5854                             "[CRTC:%d:%s] not active\n",
5855                             crtc->base.base.id, crtc->base.name);
5856                 return -EINVAL;
5857         }
5858
5859         if (intel_crtc_needs_modeset(new_crtc_state)) {
5860                 drm_dbg_kms(&i915->drm,
5861                             "[CRTC:%d:%s] modeset required\n",
5862                             crtc->base.base.id, crtc->base.name);
5863                 return -EINVAL;
5864         }
5865
5866         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5867                                              new_plane_state, i) {
5868                 if (plane->pipe != crtc->pipe)
5869                         continue;
5870
5871                 /*
5872                  * TODO: Async flip is only supported through the page flip IOCTL
5873                  * as of now. So support currently added for primary plane only.
5874                  * Support for other planes on platforms on which supports
5875                  * this(vlv/chv and icl+) should be added when async flip is
5876                  * enabled in the atomic IOCTL path.
5877                  */
5878                 if (!plane->async_flip) {
5879                         drm_dbg_kms(&i915->drm,
5880                                     "[PLANE:%d:%s] async flip not supported\n",
5881                                     plane->base.base.id, plane->base.name);
5882                         return -EINVAL;
5883                 }
5884
5885                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
5886                         drm_dbg_kms(&i915->drm,
5887                                     "[PLANE:%d:%s] no old or new framebuffer\n",
5888                                     plane->base.base.id, plane->base.name);
5889                         return -EINVAL;
5890                 }
5891         }
5892
5893         return 0;
5894 }
5895
5896 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
5897 {
5898         struct drm_i915_private *i915 = to_i915(state->base.dev);
5899         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5900         const struct intel_plane_state *new_plane_state, *old_plane_state;
5901         struct intel_plane *plane;
5902         int i;
5903
5904         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5905         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5906
5907         if (!new_crtc_state->uapi.async_flip)
5908                 return 0;
5909
5910         if (!new_crtc_state->hw.active) {
5911                 drm_dbg_kms(&i915->drm,
5912                             "[CRTC:%d:%s] not active\n",
5913                             crtc->base.base.id, crtc->base.name);
5914                 return -EINVAL;
5915         }
5916
5917         if (intel_crtc_needs_modeset(new_crtc_state)) {
5918                 drm_dbg_kms(&i915->drm,
5919                             "[CRTC:%d:%s] modeset required\n",
5920                             crtc->base.base.id, crtc->base.name);
5921                 return -EINVAL;
5922         }
5923
5924         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
5925                 drm_dbg_kms(&i915->drm,
5926                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
5927                             crtc->base.base.id, crtc->base.name);
5928                 return -EINVAL;
5929         }
5930
5931         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5932                                              new_plane_state, i) {
5933                 if (plane->pipe != crtc->pipe)
5934                         continue;
5935
5936                 /*
5937                  * Only async flip capable planes should be in the state
5938                  * if we're really about to ask the hardware to perform
5939                  * an async flip. We should never get this far otherwise.
5940                  */
5941                 if (drm_WARN_ON(&i915->drm,
5942                                 new_crtc_state->do_async_flip && !plane->async_flip))
5943                         return -EINVAL;
5944
5945                 /*
5946                  * Only check async flip capable planes other planes
5947                  * may be involved in the initial commit due to
5948                  * the wm0/ddb optimization.
5949                  *
5950                  * TODO maybe should track which planes actually
5951                  * were requested to do the async flip...
5952                  */
5953                 if (!plane->async_flip)
5954                         continue;
5955
5956                 /*
5957                  * FIXME: This check is kept generic for all platforms.
5958                  * Need to verify this for all gen9 platforms to enable
5959                  * this selectively if required.
5960                  */
5961                 switch (new_plane_state->hw.fb->modifier) {
5962                 case DRM_FORMAT_MOD_LINEAR:
5963                         /*
5964                          * FIXME: Async on Linear buffer is supported on ICL as
5965                          * but with additional alignment and fbc restrictions
5966                          * need to be taken care of. These aren't applicable for
5967                          * gen12+.
5968                          */
5969                         if (DISPLAY_VER(i915) < 12) {
5970                                 drm_dbg_kms(&i915->drm,
5971                                             "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
5972                                             plane->base.base.id, plane->base.name,
5973                                             new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
5974                                 return -EINVAL;
5975                         }
5976                         break;
5977
5978                 case I915_FORMAT_MOD_X_TILED:
5979                 case I915_FORMAT_MOD_Y_TILED:
5980                 case I915_FORMAT_MOD_Yf_TILED:
5981                 case I915_FORMAT_MOD_4_TILED:
5982                         break;
5983                 default:
5984                         drm_dbg_kms(&i915->drm,
5985                                     "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
5986                                     plane->base.base.id, plane->base.name,
5987                                     new_plane_state->hw.fb->modifier);
5988                         return -EINVAL;
5989                 }
5990
5991                 if (new_plane_state->hw.fb->format->num_planes > 1) {
5992                         drm_dbg_kms(&i915->drm,
5993                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
5994                                     plane->base.base.id, plane->base.name);
5995                         return -EINVAL;
5996                 }
5997
5998                 if (old_plane_state->view.color_plane[0].mapping_stride !=
5999                     new_plane_state->view.color_plane[0].mapping_stride) {
6000                         drm_dbg_kms(&i915->drm,
6001                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6002                                     plane->base.base.id, plane->base.name);
6003                         return -EINVAL;
6004                 }
6005
6006                 if (old_plane_state->hw.fb->modifier !=
6007                     new_plane_state->hw.fb->modifier) {
6008                         drm_dbg_kms(&i915->drm,
6009                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6010                                     plane->base.base.id, plane->base.name);
6011                         return -EINVAL;
6012                 }
6013
6014                 if (old_plane_state->hw.fb->format !=
6015                     new_plane_state->hw.fb->format) {
6016                         drm_dbg_kms(&i915->drm,
6017                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6018                                     plane->base.base.id, plane->base.name);
6019                         return -EINVAL;
6020                 }
6021
6022                 if (old_plane_state->hw.rotation !=
6023                     new_plane_state->hw.rotation) {
6024                         drm_dbg_kms(&i915->drm,
6025                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6026                                     plane->base.base.id, plane->base.name);
6027                         return -EINVAL;
6028                 }
6029
6030                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6031                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6032                         drm_dbg_kms(&i915->drm,
6033                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6034                                     plane->base.base.id, plane->base.name);
6035                         return -EINVAL;
6036                 }
6037
6038                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6039                         drm_dbg_kms(&i915->drm,
6040                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6041                                     plane->base.base.id, plane->base.name);
6042                         return -EINVAL;
6043                 }
6044
6045                 if (old_plane_state->hw.pixel_blend_mode !=
6046                     new_plane_state->hw.pixel_blend_mode) {
6047                         drm_dbg_kms(&i915->drm,
6048                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6049                                     plane->base.base.id, plane->base.name);
6050                         return -EINVAL;
6051                 }
6052
6053                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6054                         drm_dbg_kms(&i915->drm,
6055                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6056                                     plane->base.base.id, plane->base.name);
6057                         return -EINVAL;
6058                 }
6059
6060                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6061                         drm_dbg_kms(&i915->drm,
6062                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6063                                     plane->base.base.id, plane->base.name);
6064                         return -EINVAL;
6065                 }
6066
6067                 /* plane decryption is allow to change only in synchronous flips */
6068                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6069                         drm_dbg_kms(&i915->drm,
6070                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6071                                     plane->base.base.id, plane->base.name);
6072                         return -EINVAL;
6073                 }
6074         }
6075
6076         return 0;
6077 }
6078
6079 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6080 {
6081         struct drm_i915_private *i915 = to_i915(state->base.dev);
6082         struct intel_crtc_state *crtc_state;
6083         struct intel_crtc *crtc;
6084         u8 affected_pipes = 0;
6085         u8 modeset_pipes = 0;
6086         int i;
6087
6088         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6089                 affected_pipes |= crtc_state->bigjoiner_pipes;
6090                 if (intel_crtc_needs_modeset(crtc_state))
6091                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6092         }
6093
6094         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6095                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6096                 if (IS_ERR(crtc_state))
6097                         return PTR_ERR(crtc_state);
6098         }
6099
6100         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6101                 int ret;
6102
6103                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6104
6105                 crtc_state->uapi.mode_changed = true;
6106
6107                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6108                 if (ret)
6109                         return ret;
6110
6111                 ret = intel_atomic_add_affected_planes(state, crtc);
6112                 if (ret)
6113                         return ret;
6114         }
6115
6116         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6117                 /* Kill old bigjoiner link, we may re-establish afterwards */
6118                 if (intel_crtc_needs_modeset(crtc_state) &&
6119                     intel_crtc_is_bigjoiner_master(crtc_state))
6120                         kill_bigjoiner_slave(state, crtc);
6121         }
6122
6123         return 0;
6124 }
6125
6126 static int intel_atomic_check_config(struct intel_atomic_state *state,
6127                                      struct intel_link_bw_limits *limits,
6128                                      enum pipe *failed_pipe)
6129 {
6130         struct drm_i915_private *i915 = to_i915(state->base.dev);
6131         struct intel_crtc_state *new_crtc_state;
6132         struct intel_crtc *crtc;
6133         int ret;
6134         int i;
6135
6136         *failed_pipe = INVALID_PIPE;
6137
6138         ret = intel_bigjoiner_add_affected_crtcs(state);
6139         if (ret)
6140                 return ret;
6141
6142         ret = intel_fdi_add_affected_crtcs(state);
6143         if (ret)
6144                 return ret;
6145
6146         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6147                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6148                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6149                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6150                         else
6151                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6152                         continue;
6153                 }
6154
6155                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6156                         drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
6157                         continue;
6158                 }
6159
6160                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6161                 if (ret)
6162                         break;
6163
6164                 if (!new_crtc_state->hw.enable)
6165                         continue;
6166
6167                 ret = intel_modeset_pipe_config(state, crtc, limits);
6168                 if (ret)
6169                         break;
6170
6171                 ret = intel_atomic_check_bigjoiner(state, crtc);
6172                 if (ret)
6173                         break;
6174         }
6175
6176         if (ret)
6177                 *failed_pipe = crtc->pipe;
6178
6179         return ret;
6180 }
6181
6182 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6183 {
6184         struct drm_i915_private *i915 = to_i915(state->base.dev);
6185         struct intel_link_bw_limits new_limits;
6186         struct intel_link_bw_limits old_limits;
6187         int ret;
6188
6189         intel_link_bw_init_limits(i915, &new_limits);
6190         old_limits = new_limits;
6191
6192         while (true) {
6193                 enum pipe failed_pipe;
6194
6195                 ret = intel_atomic_check_config(state, &new_limits,
6196                                                 &failed_pipe);
6197                 if (ret) {
6198                         /*
6199                          * The bpp limit for a pipe is below the minimum it supports, set the
6200                          * limit to the minimum and recalculate the config.
6201                          */
6202                         if (ret == -EINVAL &&
6203                             intel_link_bw_set_bpp_limit_for_pipe(state,
6204                                                                  &old_limits,
6205                                                                  &new_limits,
6206                                                                  failed_pipe))
6207                                 continue;
6208
6209                         break;
6210                 }
6211
6212                 old_limits = new_limits;
6213
6214                 ret = intel_link_bw_atomic_check(state, &new_limits);
6215                 if (ret != -EAGAIN)
6216                         break;
6217         }
6218
6219         return ret;
6220 }
6221 /**
6222  * intel_atomic_check - validate state object
6223  * @dev: drm device
6224  * @_state: state to validate
6225  */
6226 int intel_atomic_check(struct drm_device *dev,
6227                        struct drm_atomic_state *_state)
6228 {
6229         struct drm_i915_private *dev_priv = to_i915(dev);
6230         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6231         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6232         struct intel_crtc *crtc;
6233         int ret, i;
6234         bool any_ms = false;
6235
6236         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6237                                             new_crtc_state, i) {
6238                 /*
6239                  * crtc's state no longer considered to be inherited
6240                  * after the first userspace/client initiated commit.
6241                  */
6242                 if (!state->internal)
6243                         new_crtc_state->inherited = false;
6244
6245                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6246                         new_crtc_state->uapi.mode_changed = true;
6247
6248                 if (new_crtc_state->uapi.scaling_filter !=
6249                     old_crtc_state->uapi.scaling_filter)
6250                         new_crtc_state->uapi.mode_changed = true;
6251         }
6252
6253         intel_vrr_check_modeset(state);
6254
6255         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6256         if (ret)
6257                 goto fail;
6258
6259         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6260                 ret = intel_async_flip_check_uapi(state, crtc);
6261                 if (ret)
6262                         return ret;
6263         }
6264
6265         ret = intel_atomic_check_config_and_link(state);
6266         if (ret)
6267                 goto fail;
6268
6269         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6270                                             new_crtc_state, i) {
6271                 if (!intel_crtc_needs_modeset(new_crtc_state))
6272                         continue;
6273
6274                 if (new_crtc_state->hw.enable) {
6275                         ret = intel_modeset_pipe_config_late(state, crtc);
6276                         if (ret)
6277                                 goto fail;
6278                 }
6279
6280                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6281         }
6282
6283         /**
6284          * Check if fastset is allowed by external dependencies like other
6285          * pipes and transcoders.
6286          *
6287          * Right now it only forces a fullmodeset when the MST master
6288          * transcoder did not changed but the pipe of the master transcoder
6289          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6290          * in case of port synced crtcs, if one of the synced crtcs
6291          * needs a full modeset, all other synced crtcs should be
6292          * forced a full modeset.
6293          */
6294         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6295                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6296                         continue;
6297
6298                 if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6299                         intel_crtc_flag_modeset(new_crtc_state);
6300
6301                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6302                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6303
6304                         if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6305                                 intel_crtc_flag_modeset(new_crtc_state);
6306                 }
6307
6308                 if (is_trans_port_sync_mode(new_crtc_state)) {
6309                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6310
6311                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6312                                 trans |= BIT(new_crtc_state->master_transcoder);
6313
6314                         if (intel_cpu_transcoders_need_modeset(state, trans))
6315                                 intel_crtc_flag_modeset(new_crtc_state);
6316                 }
6317
6318                 if (new_crtc_state->bigjoiner_pipes) {
6319                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
6320                                 intel_crtc_flag_modeset(new_crtc_state);
6321                 }
6322         }
6323
6324         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6325                                             new_crtc_state, i) {
6326                 if (!intel_crtc_needs_modeset(new_crtc_state))
6327                         continue;
6328
6329                 any_ms = true;
6330
6331                 intel_release_shared_dplls(state, crtc);
6332         }
6333
6334         if (any_ms && !check_digital_port_conflicts(state)) {
6335                 drm_dbg_kms(&dev_priv->drm,
6336                             "rejecting conflicting digital port configuration\n");
6337                 ret = -EINVAL;
6338                 goto fail;
6339         }
6340
6341         ret = intel_atomic_check_planes(state);
6342         if (ret)
6343                 goto fail;
6344
6345         ret = intel_compute_global_watermarks(state);
6346         if (ret)
6347                 goto fail;
6348
6349         ret = intel_bw_atomic_check(state);
6350         if (ret)
6351                 goto fail;
6352
6353         ret = intel_cdclk_atomic_check(state, &any_ms);
6354         if (ret)
6355                 goto fail;
6356
6357         if (intel_any_crtc_needs_modeset(state))
6358                 any_ms = true;
6359
6360         if (any_ms) {
6361                 ret = intel_modeset_checks(state);
6362                 if (ret)
6363                         goto fail;
6364
6365                 ret = intel_modeset_calc_cdclk(state);
6366                 if (ret)
6367                         return ret;
6368         }
6369
6370         ret = intel_pmdemand_atomic_check(state);
6371         if (ret)
6372                 goto fail;
6373
6374         ret = intel_atomic_check_crtcs(state);
6375         if (ret)
6376                 goto fail;
6377
6378         ret = intel_fbc_atomic_check(state);
6379         if (ret)
6380                 goto fail;
6381
6382         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6383                                             new_crtc_state, i) {
6384                 intel_color_assert_luts(new_crtc_state);
6385
6386                 ret = intel_async_flip_check_hw(state, crtc);
6387                 if (ret)
6388                         goto fail;
6389
6390                 /* Either full modeset or fastset (or neither), never both */
6391                 drm_WARN_ON(&dev_priv->drm,
6392                             intel_crtc_needs_modeset(new_crtc_state) &&
6393                             intel_crtc_needs_fastset(new_crtc_state));
6394
6395                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6396                     !intel_crtc_needs_fastset(new_crtc_state))
6397                         continue;
6398
6399                 intel_crtc_state_dump(new_crtc_state, state,
6400                                       intel_crtc_needs_modeset(new_crtc_state) ?
6401                                       "modeset" : "fastset");
6402         }
6403
6404         return 0;
6405
6406  fail:
6407         if (ret == -EDEADLK)
6408                 return ret;
6409
6410         /*
6411          * FIXME would probably be nice to know which crtc specifically
6412          * caused the failure, in cases where we can pinpoint it.
6413          */
6414         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6415                                             new_crtc_state, i)
6416                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6417
6418         return ret;
6419 }
6420
6421 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6422 {
6423         struct intel_crtc_state *crtc_state;
6424         struct intel_crtc *crtc;
6425         int i, ret;
6426
6427         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6428         if (ret < 0)
6429                 return ret;
6430
6431         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6432                 if (intel_crtc_needs_color_update(crtc_state))
6433                         intel_color_prepare_commit(crtc_state);
6434         }
6435
6436         return 0;
6437 }
6438
6439 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6440                                   struct intel_crtc_state *crtc_state)
6441 {
6442         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6443
6444         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6445                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6446
6447         if (crtc_state->has_pch_encoder) {
6448                 enum pipe pch_transcoder =
6449                         intel_crtc_pch_transcoder(crtc);
6450
6451                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6452         }
6453 }
6454
6455 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6456                                const struct intel_crtc_state *new_crtc_state)
6457 {
6458         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6460
6461         /*
6462          * Update pipe size and adjust fitter if needed: the reason for this is
6463          * that in compute_mode_changes we check the native mode (not the pfit
6464          * mode) to see if we can flip rather than do a full mode set. In the
6465          * fastboot case, we'll flip, but if we don't update the pipesrc and
6466          * pfit state, we'll end up with a big fb scanned out into the wrong
6467          * sized surface.
6468          */
6469         intel_set_pipe_src_size(new_crtc_state);
6470
6471         /* on skylake this is done by detaching scalers */
6472         if (DISPLAY_VER(dev_priv) >= 9) {
6473                 if (new_crtc_state->pch_pfit.enabled)
6474                         skl_pfit_enable(new_crtc_state);
6475         } else if (HAS_PCH_SPLIT(dev_priv)) {
6476                 if (new_crtc_state->pch_pfit.enabled)
6477                         ilk_pfit_enable(new_crtc_state);
6478                 else if (old_crtc_state->pch_pfit.enabled)
6479                         ilk_pfit_disable(old_crtc_state);
6480         }
6481
6482         /*
6483          * The register is supposedly single buffered so perhaps
6484          * not 100% correct to do this here. But SKL+ calculate
6485          * this based on the adjust pixel rate so pfit changes do
6486          * affect it and so it must be updated for fastsets.
6487          * HSW/BDW only really need this here for fastboot, after
6488          * that the value should not change without a full modeset.
6489          */
6490         if (DISPLAY_VER(dev_priv) >= 9 ||
6491             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6492                 hsw_set_linetime_wm(new_crtc_state);
6493
6494         if (new_crtc_state->update_m_n)
6495                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6496                                                &new_crtc_state->dp_m_n);
6497
6498         if (new_crtc_state->update_lrr)
6499                 intel_set_transcoder_timings_lrr(new_crtc_state);
6500 }
6501
6502 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6503                                    struct intel_crtc *crtc)
6504 {
6505         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6506         const struct intel_crtc_state *old_crtc_state =
6507                 intel_atomic_get_old_crtc_state(state, crtc);
6508         const struct intel_crtc_state *new_crtc_state =
6509                 intel_atomic_get_new_crtc_state(state, crtc);
6510         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6511
6512         /*
6513          * During modesets pipe configuration was programmed as the
6514          * CRTC was enabled.
6515          */
6516         if (!modeset) {
6517                 if (intel_crtc_needs_color_update(new_crtc_state))
6518                         intel_color_commit_arm(new_crtc_state);
6519
6520                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6521                         bdw_set_pipe_misc(new_crtc_state);
6522
6523                 if (intel_crtc_needs_fastset(new_crtc_state))
6524                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6525         }
6526
6527         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6528
6529         intel_atomic_update_watermarks(state, crtc);
6530 }
6531
6532 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6533                                     struct intel_crtc *crtc)
6534 {
6535         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6536         const struct intel_crtc_state *old_crtc_state =
6537                 intel_atomic_get_old_crtc_state(state, crtc);
6538         const struct intel_crtc_state *new_crtc_state =
6539                 intel_atomic_get_new_crtc_state(state, crtc);
6540
6541         /*
6542          * Disable the scaler(s) after the plane(s) so that we don't
6543          * get a catastrophic underrun even if the two operations
6544          * end up happening in two different frames.
6545          */
6546         if (DISPLAY_VER(dev_priv) >= 9 &&
6547             !intel_crtc_needs_modeset(new_crtc_state))
6548                 skl_detach_scalers(new_crtc_state);
6549
6550         if (vrr_enabling(old_crtc_state, new_crtc_state))
6551                 intel_vrr_enable(new_crtc_state);
6552 }
6553
6554 static void intel_enable_crtc(struct intel_atomic_state *state,
6555                               struct intel_crtc *crtc)
6556 {
6557         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6558         const struct intel_crtc_state *new_crtc_state =
6559                 intel_atomic_get_new_crtc_state(state, crtc);
6560
6561         if (!intel_crtc_needs_modeset(new_crtc_state))
6562                 return;
6563
6564         /* VRR will be enable later, if required */
6565         intel_crtc_update_active_timings(new_crtc_state, false);
6566
6567         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6568
6569         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6570                 return;
6571
6572         /* vblanks work again, re-enable pipe CRC. */
6573         intel_crtc_enable_pipe_crc(crtc);
6574 }
6575
6576 static void intel_pre_update_crtc(struct intel_atomic_state *state,
6577                                   struct intel_crtc *crtc)
6578 {
6579         struct drm_i915_private *i915 = to_i915(state->base.dev);
6580         const struct intel_crtc_state *old_crtc_state =
6581                 intel_atomic_get_old_crtc_state(state, crtc);
6582         struct intel_crtc_state *new_crtc_state =
6583                 intel_atomic_get_new_crtc_state(state, crtc);
6584         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6585
6586         if (old_crtc_state->inherited ||
6587             intel_crtc_needs_modeset(new_crtc_state)) {
6588                 if (HAS_DPT(i915))
6589                         intel_dpt_configure(crtc);
6590         }
6591
6592         if (!modeset) {
6593                 if (new_crtc_state->preload_luts &&
6594                     intel_crtc_needs_color_update(new_crtc_state))
6595                         intel_color_load_luts(new_crtc_state);
6596
6597                 intel_pre_plane_update(state, crtc);
6598
6599                 if (intel_crtc_needs_fastset(new_crtc_state))
6600                         intel_encoders_update_pipe(state, crtc);
6601
6602                 if (DISPLAY_VER(i915) >= 11 &&
6603                     intel_crtc_needs_fastset(new_crtc_state))
6604                         icl_set_pipe_chicken(new_crtc_state);
6605
6606                 if (vrr_params_changed(old_crtc_state, new_crtc_state))
6607                         intel_vrr_set_transcoder_timings(new_crtc_state);
6608         }
6609
6610         intel_fbc_update(state, crtc);
6611
6612         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6613
6614         if (!modeset &&
6615             intel_crtc_needs_color_update(new_crtc_state))
6616                 intel_color_commit_noarm(new_crtc_state);
6617
6618         intel_crtc_planes_update_noarm(state, crtc);
6619 }
6620
6621 static void intel_update_crtc(struct intel_atomic_state *state,
6622                               struct intel_crtc *crtc)
6623 {
6624         const struct intel_crtc_state *old_crtc_state =
6625                 intel_atomic_get_old_crtc_state(state, crtc);
6626         struct intel_crtc_state *new_crtc_state =
6627                 intel_atomic_get_new_crtc_state(state, crtc);
6628
6629         /* Perform vblank evasion around commit operation */
6630         intel_pipe_update_start(state, crtc);
6631
6632         commit_pipe_pre_planes(state, crtc);
6633
6634         intel_crtc_planes_update_arm(state, crtc);
6635
6636         commit_pipe_post_planes(state, crtc);
6637
6638         intel_pipe_update_end(state, crtc);
6639
6640         /*
6641          * VRR/Seamless M/N update may need to update frame timings.
6642          *
6643          * FIXME Should be synchronized with the start of vblank somehow...
6644          */
6645         if (vrr_enabling(old_crtc_state, new_crtc_state) ||
6646             new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6647                 intel_crtc_update_active_timings(new_crtc_state,
6648                                                  new_crtc_state->vrr.enable);
6649
6650         /*
6651          * We usually enable FIFO underrun interrupts as part of the
6652          * CRTC enable sequence during modesets.  But when we inherit a
6653          * valid pipe configuration from the BIOS we need to take care
6654          * of enabling them on the CRTC's first fastset.
6655          */
6656         if (intel_crtc_needs_fastset(new_crtc_state) &&
6657             old_crtc_state->inherited)
6658                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6659 }
6660
6661 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6662                                           struct intel_crtc_state *old_crtc_state,
6663                                           struct intel_crtc_state *new_crtc_state,
6664                                           struct intel_crtc *crtc)
6665 {
6666         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6667
6668         /*
6669          * We need to disable pipe CRC before disabling the pipe,
6670          * or we race against vblank off.
6671          */
6672         intel_crtc_disable_pipe_crc(crtc);
6673
6674         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6675         crtc->active = false;
6676         intel_fbc_disable(crtc);
6677
6678         if (!new_crtc_state->hw.active)
6679                 intel_initial_watermarks(state, crtc);
6680 }
6681
6682 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6683 {
6684         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6685         struct intel_crtc *crtc;
6686         u32 handled = 0;
6687         int i;
6688
6689         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6690                                             new_crtc_state, i) {
6691                 if (!intel_crtc_needs_modeset(new_crtc_state))
6692                         continue;
6693
6694                 intel_pre_plane_update(state, crtc);
6695
6696                 if (!old_crtc_state->hw.active)
6697                         continue;
6698
6699                 intel_crtc_disable_planes(state, crtc);
6700         }
6701
6702         /* Only disable port sync and MST slaves */
6703         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6704                                             new_crtc_state, i) {
6705                 if (!intel_crtc_needs_modeset(new_crtc_state))
6706                         continue;
6707
6708                 if (!old_crtc_state->hw.active)
6709                         continue;
6710
6711                 /* In case of Transcoder port Sync master slave CRTCs can be
6712                  * assigned in any order and we need to make sure that
6713                  * slave CRTCs are disabled first and then master CRTC since
6714                  * Slave vblanks are masked till Master Vblanks.
6715                  */
6716                 if (!is_trans_port_sync_slave(old_crtc_state) &&
6717                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
6718                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
6719                         continue;
6720
6721                 intel_old_crtc_state_disables(state, old_crtc_state,
6722                                               new_crtc_state, crtc);
6723                 handled |= BIT(crtc->pipe);
6724         }
6725
6726         /* Disable everything else left on */
6727         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6728                                             new_crtc_state, i) {
6729                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
6730                     (handled & BIT(crtc->pipe)))
6731                         continue;
6732
6733                 if (!old_crtc_state->hw.active)
6734                         continue;
6735
6736                 intel_old_crtc_state_disables(state, old_crtc_state,
6737                                               new_crtc_state, crtc);
6738         }
6739 }
6740
6741 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6742 {
6743         struct intel_crtc_state *new_crtc_state;
6744         struct intel_crtc *crtc;
6745         int i;
6746
6747         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6748                 if (!new_crtc_state->hw.active)
6749                         continue;
6750
6751                 intel_enable_crtc(state, crtc);
6752                 intel_pre_update_crtc(state, crtc);
6753         }
6754
6755         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6756                 if (!new_crtc_state->hw.active)
6757                         continue;
6758
6759                 intel_update_crtc(state, crtc);
6760         }
6761 }
6762
6763 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6764 {
6765         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6766         struct intel_crtc *crtc;
6767         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6768         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6769         u8 update_pipes = 0, modeset_pipes = 0;
6770         int i;
6771
6772         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6773                 enum pipe pipe = crtc->pipe;
6774
6775                 if (!new_crtc_state->hw.active)
6776                         continue;
6777
6778                 /* ignore allocations for crtc's that have been turned off. */
6779                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6780                         entries[pipe] = old_crtc_state->wm.skl.ddb;
6781                         update_pipes |= BIT(pipe);
6782                 } else {
6783                         modeset_pipes |= BIT(pipe);
6784                 }
6785         }
6786
6787         /*
6788          * Whenever the number of active pipes changes, we need to make sure we
6789          * update the pipes in the right order so that their ddb allocations
6790          * never overlap with each other between CRTC updates. Otherwise we'll
6791          * cause pipe underruns and other bad stuff.
6792          *
6793          * So first lets enable all pipes that do not need a fullmodeset as
6794          * those don't have any external dependency.
6795          */
6796         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6797                 enum pipe pipe = crtc->pipe;
6798
6799                 if ((update_pipes & BIT(pipe)) == 0)
6800                         continue;
6801
6802                 intel_pre_update_crtc(state, crtc);
6803         }
6804
6805         while (update_pipes) {
6806                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6807                                                     new_crtc_state, i) {
6808                         enum pipe pipe = crtc->pipe;
6809
6810                         if ((update_pipes & BIT(pipe)) == 0)
6811                                 continue;
6812
6813                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6814                                                         entries, I915_MAX_PIPES, pipe))
6815                                 continue;
6816
6817                         entries[pipe] = new_crtc_state->wm.skl.ddb;
6818                         update_pipes &= ~BIT(pipe);
6819
6820                         intel_update_crtc(state, crtc);
6821
6822                         /*
6823                          * If this is an already active pipe, it's DDB changed,
6824                          * and this isn't the last pipe that needs updating
6825                          * then we need to wait for a vblank to pass for the
6826                          * new ddb allocation to take effect.
6827                          */
6828                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
6829                                                  &old_crtc_state->wm.skl.ddb) &&
6830                             (update_pipes | modeset_pipes))
6831                                 intel_crtc_wait_for_next_vblank(crtc);
6832                 }
6833         }
6834
6835         update_pipes = modeset_pipes;
6836
6837         /*
6838          * Enable all pipes that needs a modeset and do not depends on other
6839          * pipes
6840          */
6841         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6842                 enum pipe pipe = crtc->pipe;
6843
6844                 if ((modeset_pipes & BIT(pipe)) == 0)
6845                         continue;
6846
6847                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
6848                     is_trans_port_sync_master(new_crtc_state) ||
6849                     intel_crtc_is_bigjoiner_master(new_crtc_state))
6850                         continue;
6851
6852                 modeset_pipes &= ~BIT(pipe);
6853
6854                 intel_enable_crtc(state, crtc);
6855         }
6856
6857         /*
6858          * Then we enable all remaining pipes that depend on other
6859          * pipes: MST slaves and port sync masters, big joiner master
6860          */
6861         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6862                 enum pipe pipe = crtc->pipe;
6863
6864                 if ((modeset_pipes & BIT(pipe)) == 0)
6865                         continue;
6866
6867                 modeset_pipes &= ~BIT(pipe);
6868
6869                 intel_enable_crtc(state, crtc);
6870         }
6871
6872         /*
6873          * Finally we do the plane updates/etc. for all pipes that got enabled.
6874          */
6875         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6876                 enum pipe pipe = crtc->pipe;
6877
6878                 if ((update_pipes & BIT(pipe)) == 0)
6879                         continue;
6880
6881                 intel_pre_update_crtc(state, crtc);
6882         }
6883
6884         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6885                 enum pipe pipe = crtc->pipe;
6886
6887                 if ((update_pipes & BIT(pipe)) == 0)
6888                         continue;
6889
6890                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6891                                                                         entries, I915_MAX_PIPES, pipe));
6892
6893                 entries[pipe] = new_crtc_state->wm.skl.ddb;
6894                 update_pipes &= ~BIT(pipe);
6895
6896                 intel_update_crtc(state, crtc);
6897         }
6898
6899         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
6900         drm_WARN_ON(&dev_priv->drm, update_pipes);
6901 }
6902
6903 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
6904 {
6905         struct intel_atomic_state *state, *next;
6906         struct llist_node *freed;
6907
6908         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
6909         llist_for_each_entry_safe(state, next, freed, freed)
6910                 drm_atomic_state_put(&state->base);
6911 }
6912
6913 void intel_atomic_helper_free_state_worker(struct work_struct *work)
6914 {
6915         struct drm_i915_private *dev_priv =
6916                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
6917
6918         intel_atomic_helper_free_state(dev_priv);
6919 }
6920
6921 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
6922 {
6923         struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
6924         struct drm_plane *plane;
6925         struct drm_plane_state *new_plane_state;
6926         int ret, i;
6927
6928         for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
6929                 if (new_plane_state->fence) {
6930                         ret = dma_fence_wait_timeout(new_plane_state->fence, false,
6931                                                      i915_fence_timeout(i915));
6932                         if (ret <= 0)
6933                                 break;
6934
6935                         dma_fence_put(new_plane_state->fence);
6936                         new_plane_state->fence = NULL;
6937                 }
6938         }
6939 }
6940
6941 static void intel_atomic_cleanup_work(struct work_struct *work)
6942 {
6943         struct intel_atomic_state *state =
6944                 container_of(work, struct intel_atomic_state, base.commit_work);
6945         struct drm_i915_private *i915 = to_i915(state->base.dev);
6946         struct intel_crtc_state *old_crtc_state;
6947         struct intel_crtc *crtc;
6948         int i;
6949
6950         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
6951                 intel_color_cleanup_commit(old_crtc_state);
6952
6953         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
6954         drm_atomic_helper_commit_cleanup_done(&state->base);
6955         drm_atomic_state_put(&state->base);
6956
6957         intel_atomic_helper_free_state(i915);
6958 }
6959
6960 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
6961 {
6962         struct drm_i915_private *i915 = to_i915(state->base.dev);
6963         struct intel_plane *plane;
6964         struct intel_plane_state *plane_state;
6965         int i;
6966
6967         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6968                 struct drm_framebuffer *fb = plane_state->hw.fb;
6969                 int cc_plane;
6970                 int ret;
6971
6972                 if (!fb)
6973                         continue;
6974
6975                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
6976                 if (cc_plane < 0)
6977                         continue;
6978
6979                 /*
6980                  * The layout of the fast clear color value expected by HW
6981                  * (the DRM ABI requiring this value to be located in fb at
6982                  * offset 0 of cc plane, plane #2 previous generations or
6983                  * plane #1 for flat ccs):
6984                  * - 4 x 4 bytes per-channel value
6985                  *   (in surface type specific float/int format provided by the fb user)
6986                  * - 8 bytes native color value used by the display
6987                  *   (converted/written by GPU during a fast clear operation using the
6988                  *    above per-channel values)
6989                  *
6990                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
6991                  * caller made sure that the object is synced wrt. the related color clear value
6992                  * GPU write on it.
6993                  */
6994                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
6995                                                      fb->offsets[cc_plane] + 16,
6996                                                      &plane_state->ccval,
6997                                                      sizeof(plane_state->ccval));
6998                 /* The above could only fail if the FB obj has an unexpected backing store type. */
6999                 drm_WARN_ON(&i915->drm, ret);
7000         }
7001 }
7002
7003 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7004 {
7005         struct drm_device *dev = state->base.dev;
7006         struct drm_i915_private *dev_priv = to_i915(dev);
7007         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7008         struct intel_crtc *crtc;
7009         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7010         intel_wakeref_t wakeref = 0;
7011         int i;
7012
7013         intel_atomic_commit_fence_wait(state);
7014
7015         drm_atomic_helper_wait_for_dependencies(&state->base);
7016         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7017
7018         /*
7019          * During full modesets we write a lot of registers, wait
7020          * for PLLs, etc. Doing that while DC states are enabled
7021          * is not a good idea.
7022          *
7023          * During fastsets and other updates we also need to
7024          * disable DC states due to the following scenario:
7025          * 1. DC5 exit and PSR exit happen
7026          * 2. Some or all _noarm() registers are written
7027          * 3. Due to some long delay PSR is re-entered
7028          * 4. DC5 entry -> DMC saves the already written new
7029          *    _noarm() registers and the old not yet written
7030          *    _arm() registers
7031          * 5. DC5 exit -> DMC restores a mixture of old and
7032          *    new register values and arms the update
7033          * 6. PSR exit -> hardware latches a mixture of old and
7034          *    new register values -> corrupted frame, or worse
7035          * 7. New _arm() registers are finally written
7036          * 8. Hardware finally latches a complete set of new
7037          *    register values, and subsequent frames will be OK again
7038          *
7039          * Also note that due to the pipe CSC hardware issues on
7040          * SKL/GLK DC states must remain off until the pipe CSC
7041          * state readout has happened. Otherwise we risk corrupting
7042          * the CSC latched register values with the readout (see
7043          * skl_read_csc() and skl_color_commit_noarm()).
7044          */
7045         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7046
7047         intel_atomic_prepare_plane_clear_colors(state);
7048
7049         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7050                                             new_crtc_state, i) {
7051                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7052                     intel_crtc_needs_fastset(new_crtc_state))
7053                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7054         }
7055
7056         intel_commit_modeset_disables(state);
7057
7058         /* FIXME: Eventually get rid of our crtc->config pointer */
7059         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7060                 crtc->config = new_crtc_state;
7061
7062         /*
7063          * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7064          * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7065          * index, cdclk/ddiclk frequencies are supposed to be configured before
7066          * the cdclk config is set.
7067          */
7068         intel_pmdemand_pre_plane_update(state);
7069
7070         if (state->modeset) {
7071                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7072
7073                 intel_set_cdclk_pre_plane_update(state);
7074
7075                 intel_modeset_verify_disabled(state);
7076         }
7077
7078         intel_sagv_pre_plane_update(state);
7079
7080         /* Complete the events for pipes that have now been disabled */
7081         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7082                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7083
7084                 /* Complete events for now disable pipes here. */
7085                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7086                         spin_lock_irq(&dev->event_lock);
7087                         drm_crtc_send_vblank_event(&crtc->base,
7088                                                    new_crtc_state->uapi.event);
7089                         spin_unlock_irq(&dev->event_lock);
7090
7091                         new_crtc_state->uapi.event = NULL;
7092                 }
7093         }
7094
7095         intel_encoders_update_prepare(state);
7096
7097         intel_dbuf_pre_plane_update(state);
7098         intel_mbus_dbox_update(state);
7099
7100         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7101                 if (new_crtc_state->do_async_flip)
7102                         intel_crtc_enable_flip_done(state, crtc);
7103         }
7104
7105         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7106         dev_priv->display.funcs.display->commit_modeset_enables(state);
7107
7108         if (state->modeset)
7109                 intel_set_cdclk_post_plane_update(state);
7110
7111         intel_wait_for_vblank_workers(state);
7112
7113         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7114          * already, but still need the state for the delayed optimization. To
7115          * fix this:
7116          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7117          * - schedule that vblank worker _before_ calling hw_done
7118          * - at the start of commit_tail, cancel it _synchrously
7119          * - switch over to the vblank wait helper in the core after that since
7120          *   we don't need out special handling any more.
7121          */
7122         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7123
7124         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7125                 if (new_crtc_state->do_async_flip)
7126                         intel_crtc_disable_flip_done(state, crtc);
7127
7128                 intel_color_wait_commit(new_crtc_state);
7129         }
7130
7131         /*
7132          * Now that the vblank has passed, we can go ahead and program the
7133          * optimal watermarks on platforms that need two-step watermark
7134          * programming.
7135          *
7136          * TODO: Move this (and other cleanup) to an async worker eventually.
7137          */
7138         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7139                                             new_crtc_state, i) {
7140                 /*
7141                  * Gen2 reports pipe underruns whenever all planes are disabled.
7142                  * So re-enable underrun reporting after some planes get enabled.
7143                  *
7144                  * We do this before .optimize_watermarks() so that we have a
7145                  * chance of catching underruns with the intermediate watermarks
7146                  * vs. the new plane configuration.
7147                  */
7148                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7149                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7150
7151                 intel_optimize_watermarks(state, crtc);
7152         }
7153
7154         intel_dbuf_post_plane_update(state);
7155
7156         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7157                 intel_post_plane_update(state, crtc);
7158
7159                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7160
7161                 intel_modeset_verify_crtc(state, crtc);
7162
7163                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7164                 hsw_ips_post_update(state, crtc);
7165
7166                 /*
7167                  * Activate DRRS after state readout to avoid
7168                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7169                  */
7170                 intel_drrs_activate(new_crtc_state);
7171
7172                 /*
7173                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7174                  * cleanup. So copy and reset the dsb structure to sync with
7175                  * commit_done and later do dsb cleanup in cleanup_work.
7176                  *
7177                  * FIXME get rid of this funny new->old swapping
7178                  */
7179                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7180         }
7181
7182         /* Underruns don't always raise interrupts, so check manually */
7183         intel_check_cpu_fifo_underruns(dev_priv);
7184         intel_check_pch_fifo_underruns(dev_priv);
7185
7186         if (state->modeset)
7187                 intel_verify_planes(state);
7188
7189         intel_sagv_post_plane_update(state);
7190         intel_pmdemand_post_plane_update(state);
7191
7192         drm_atomic_helper_commit_hw_done(&state->base);
7193
7194         if (state->modeset) {
7195                 /* As one of the primary mmio accessors, KMS has a high
7196                  * likelihood of triggering bugs in unclaimed access. After we
7197                  * finish modesetting, see if an error has been flagged, and if
7198                  * so enable debugging for the next modeset - and hope we catch
7199                  * the culprit.
7200                  */
7201                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7202         }
7203         /*
7204          * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7205          * toggling overhead at and above 60 FPS.
7206          */
7207         intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7208         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7209
7210         /*
7211          * Defer the cleanup of the old state to a separate worker to not
7212          * impede the current task (userspace for blocking modesets) that
7213          * are executed inline. For out-of-line asynchronous modesets/flips,
7214          * deferring to a new worker seems overkill, but we would place a
7215          * schedule point (cond_resched()) here anyway to keep latencies
7216          * down.
7217          */
7218         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7219         queue_work(system_highpri_wq, &state->base.commit_work);
7220 }
7221
7222 static void intel_atomic_commit_work(struct work_struct *work)
7223 {
7224         struct intel_atomic_state *state =
7225                 container_of(work, struct intel_atomic_state, base.commit_work);
7226
7227         intel_atomic_commit_tail(state);
7228 }
7229
7230 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7231 {
7232         struct intel_plane_state *old_plane_state, *new_plane_state;
7233         struct intel_plane *plane;
7234         int i;
7235
7236         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7237                                              new_plane_state, i)
7238                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7239                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7240                                         plane->frontbuffer_bit);
7241 }
7242
7243 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7244                         bool nonblock)
7245 {
7246         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7247         struct drm_i915_private *dev_priv = to_i915(dev);
7248         int ret = 0;
7249
7250         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7251
7252         /*
7253          * The intel_legacy_cursor_update() fast path takes care
7254          * of avoiding the vblank waits for simple cursor
7255          * movement and flips. For cursor on/off and size changes,
7256          * we want to perform the vblank waits so that watermark
7257          * updates happen during the correct frames. Gen9+ have
7258          * double buffered watermarks and so shouldn't need this.
7259          *
7260          * Unset state->legacy_cursor_update before the call to
7261          * drm_atomic_helper_setup_commit() because otherwise
7262          * drm_atomic_helper_wait_for_flip_done() is a noop and
7263          * we get FIFO underruns because we didn't wait
7264          * for vblank.
7265          *
7266          * FIXME doing watermarks and fb cleanup from a vblank worker
7267          * (assuming we had any) would solve these problems.
7268          */
7269         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7270                 struct intel_crtc_state *new_crtc_state;
7271                 struct intel_crtc *crtc;
7272                 int i;
7273
7274                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7275                         if (new_crtc_state->wm.need_postvbl_update ||
7276                             new_crtc_state->update_wm_post)
7277                                 state->base.legacy_cursor_update = false;
7278         }
7279
7280         ret = intel_atomic_prepare_commit(state);
7281         if (ret) {
7282                 drm_dbg_atomic(&dev_priv->drm,
7283                                "Preparing state failed with %i\n", ret);
7284                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7285                 return ret;
7286         }
7287
7288         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7289         if (!ret)
7290                 ret = drm_atomic_helper_swap_state(&state->base, true);
7291         if (!ret)
7292                 intel_atomic_swap_global_state(state);
7293
7294         if (ret) {
7295                 struct intel_crtc_state *new_crtc_state;
7296                 struct intel_crtc *crtc;
7297                 int i;
7298
7299                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7300                         intel_color_cleanup_commit(new_crtc_state);
7301
7302                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7303                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7304                 return ret;
7305         }
7306         intel_shared_dpll_swap_state(state);
7307         intel_atomic_track_fbs(state);
7308
7309         drm_atomic_state_get(&state->base);
7310         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7311
7312         if (nonblock && state->modeset) {
7313                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7314         } else if (nonblock) {
7315                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7316         } else {
7317                 if (state->modeset)
7318                         flush_workqueue(dev_priv->display.wq.modeset);
7319                 intel_atomic_commit_tail(state);
7320         }
7321
7322         return 0;
7323 }
7324
7325 /**
7326  * intel_plane_destroy - destroy a plane
7327  * @plane: plane to destroy
7328  *
7329  * Common destruction function for all types of planes (primary, cursor,
7330  * sprite).
7331  */
7332 void intel_plane_destroy(struct drm_plane *plane)
7333 {
7334         drm_plane_cleanup(plane);
7335         kfree(to_intel_plane(plane));
7336 }
7337
7338 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7339                                       struct drm_file *file)
7340 {
7341         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7342         struct drm_crtc *drmmode_crtc;
7343         struct intel_crtc *crtc;
7344
7345         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7346         if (!drmmode_crtc)
7347                 return -ENOENT;
7348
7349         crtc = to_intel_crtc(drmmode_crtc);
7350         pipe_from_crtc_id->pipe = crtc->pipe;
7351
7352         return 0;
7353 }
7354
7355 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7356 {
7357         struct drm_device *dev = encoder->base.dev;
7358         struct intel_encoder *source_encoder;
7359         u32 possible_clones = 0;
7360
7361         for_each_intel_encoder(dev, source_encoder) {
7362                 if (encoders_cloneable(encoder, source_encoder))
7363                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7364         }
7365
7366         return possible_clones;
7367 }
7368
7369 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7370 {
7371         struct drm_device *dev = encoder->base.dev;
7372         struct intel_crtc *crtc;
7373         u32 possible_crtcs = 0;
7374
7375         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7376                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7377
7378         return possible_crtcs;
7379 }
7380
7381 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7382 {
7383         if (!IS_MOBILE(dev_priv))
7384                 return false;
7385
7386         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7387                 return false;
7388
7389         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7390                 return false;
7391
7392         return true;
7393 }
7394
7395 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7396 {
7397         if (DISPLAY_VER(dev_priv) >= 9)
7398                 return false;
7399
7400         if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
7401                 return false;
7402
7403         if (HAS_PCH_LPT_H(dev_priv) &&
7404             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7405                 return false;
7406
7407         /* DDI E can't be used if DDI A requires 4 lanes */
7408         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7409                 return false;
7410
7411         if (!dev_priv->display.vbt.int_crt_support)
7412                 return false;
7413
7414         return true;
7415 }
7416
7417 bool assert_port_valid(struct drm_i915_private *i915, enum port port)
7418 {
7419         return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
7420                          "Platform does not support port %c\n", port_name(port));
7421 }
7422
7423 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7424 {
7425         struct intel_encoder *encoder;
7426         bool dpd_is_edp = false;
7427
7428         intel_pps_unlock_regs_wa(dev_priv);
7429
7430         if (!HAS_DISPLAY(dev_priv))
7431                 return;
7432
7433         if (HAS_DDI(dev_priv)) {
7434                 if (intel_ddi_crt_present(dev_priv))
7435                         intel_crt_init(dev_priv);
7436
7437                 intel_bios_for_each_encoder(dev_priv, intel_ddi_init);
7438
7439                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
7440                         vlv_dsi_init(dev_priv);
7441         } else if (HAS_PCH_SPLIT(dev_priv)) {
7442                 int found;
7443
7444                 /*
7445                  * intel_edp_init_connector() depends on this completing first,
7446                  * to prevent the registration of both eDP and LVDS and the
7447                  * incorrect sharing of the PPS.
7448                  */
7449                 intel_lvds_init(dev_priv);
7450                 intel_crt_init(dev_priv);
7451
7452                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7453
7454                 if (ilk_has_edp_a(dev_priv))
7455                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7456
7457                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7458                         /* PCH SDVOB multiplex with HDMIB */
7459                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7460                         if (!found)
7461                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7462                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7463                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7464                 }
7465
7466                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7467                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7468
7469                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7470                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7471
7472                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7473                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7474
7475                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7476                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7477         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7478                 bool has_edp, has_port;
7479
7480                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7481                         intel_crt_init(dev_priv);
7482
7483                 /*
7484                  * The DP_DETECTED bit is the latched state of the DDC
7485                  * SDA pin at boot. However since eDP doesn't require DDC
7486                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7487                  * eDP ports may have been muxed to an alternate function.
7488                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7489                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7490                  * detect eDP ports.
7491                  *
7492                  * Sadly the straps seem to be missing sometimes even for HDMI
7493                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7494                  * and VBT for the presence of the port. Additionally we can't
7495                  * trust the port type the VBT declares as we've seen at least
7496                  * HDMI ports that the VBT claim are DP or eDP.
7497                  */
7498                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7499                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7500                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7501                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7502                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7503                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7504
7505                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7506                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7507                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7508                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7509                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7510                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7511
7512                 if (IS_CHERRYVIEW(dev_priv)) {
7513                         /*
7514                          * eDP not supported on port D,
7515                          * so no need to worry about it
7516                          */
7517                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7518                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7519                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7520                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7521                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7522                 }
7523
7524                 vlv_dsi_init(dev_priv);
7525         } else if (IS_PINEVIEW(dev_priv)) {
7526                 intel_lvds_init(dev_priv);
7527                 intel_crt_init(dev_priv);
7528         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7529                 bool found = false;
7530
7531                 if (IS_MOBILE(dev_priv))
7532                         intel_lvds_init(dev_priv);
7533
7534                 intel_crt_init(dev_priv);
7535
7536                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7537                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7538                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7539                         if (!found && IS_G4X(dev_priv)) {
7540                                 drm_dbg_kms(&dev_priv->drm,
7541                                             "probing HDMI on SDVOB\n");
7542                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7543                         }
7544
7545                         if (!found && IS_G4X(dev_priv))
7546                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7547                 }
7548
7549                 /* Before G4X SDVOC doesn't have its own detect register */
7550
7551                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7552                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7553                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7554                 }
7555
7556                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7557
7558                         if (IS_G4X(dev_priv)) {
7559                                 drm_dbg_kms(&dev_priv->drm,
7560                                             "probing HDMI on SDVOC\n");
7561                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7562                         }
7563                         if (IS_G4X(dev_priv))
7564                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7565                 }
7566
7567                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7568                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7569
7570                 if (SUPPORTS_TV(dev_priv))
7571                         intel_tv_init(dev_priv);
7572         } else if (DISPLAY_VER(dev_priv) == 2) {
7573                 if (IS_I85X(dev_priv))
7574                         intel_lvds_init(dev_priv);
7575
7576                 intel_crt_init(dev_priv);
7577                 intel_dvo_init(dev_priv);
7578         }
7579
7580         for_each_intel_encoder(&dev_priv->drm, encoder) {
7581                 encoder->base.possible_crtcs =
7582                         intel_encoder_possible_crtcs(encoder);
7583                 encoder->base.possible_clones =
7584                         intel_encoder_possible_clones(encoder);
7585         }
7586
7587         intel_init_pch_refclk(dev_priv);
7588
7589         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7590 }
7591
7592 static int max_dotclock(struct drm_i915_private *i915)
7593 {
7594         int max_dotclock = i915->max_dotclk_freq;
7595
7596         /* icl+ might use bigjoiner */
7597         if (DISPLAY_VER(i915) >= 11)
7598                 max_dotclock *= 2;
7599
7600         return max_dotclock;
7601 }
7602
7603 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7604                                       const struct drm_display_mode *mode)
7605 {
7606         struct drm_i915_private *dev_priv = to_i915(dev);
7607         int hdisplay_max, htotal_max;
7608         int vdisplay_max, vtotal_max;
7609
7610         /*
7611          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7612          * of DBLSCAN modes to the output's mode list when they detect
7613          * the scaling mode property on the connector. And they don't
7614          * ask the kernel to validate those modes in any way until
7615          * modeset time at which point the client gets a protocol error.
7616          * So in order to not upset those clients we silently ignore the
7617          * DBLSCAN flag on such connectors. For other connectors we will
7618          * reject modes with the DBLSCAN flag in encoder->compute_config().
7619          * And we always reject DBLSCAN modes in connector->mode_valid()
7620          * as we never want such modes on the connector's mode list.
7621          */
7622
7623         if (mode->vscan > 1)
7624                 return MODE_NO_VSCAN;
7625
7626         if (mode->flags & DRM_MODE_FLAG_HSKEW)
7627                 return MODE_H_ILLEGAL;
7628
7629         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7630                            DRM_MODE_FLAG_NCSYNC |
7631                            DRM_MODE_FLAG_PCSYNC))
7632                 return MODE_HSYNC;
7633
7634         if (mode->flags & (DRM_MODE_FLAG_BCAST |
7635                            DRM_MODE_FLAG_PIXMUX |
7636                            DRM_MODE_FLAG_CLKDIV2))
7637                 return MODE_BAD;
7638
7639         /*
7640          * Reject clearly excessive dotclocks early to
7641          * avoid having to worry about huge integers later.
7642          */
7643         if (mode->clock > max_dotclock(dev_priv))
7644                 return MODE_CLOCK_HIGH;
7645
7646         /* Transcoder timing limits */
7647         if (DISPLAY_VER(dev_priv) >= 11) {
7648                 hdisplay_max = 16384;
7649                 vdisplay_max = 8192;
7650                 htotal_max = 16384;
7651                 vtotal_max = 8192;
7652         } else if (DISPLAY_VER(dev_priv) >= 9 ||
7653                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7654                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7655                 vdisplay_max = 4096;
7656                 htotal_max = 8192;
7657                 vtotal_max = 8192;
7658         } else if (DISPLAY_VER(dev_priv) >= 3) {
7659                 hdisplay_max = 4096;
7660                 vdisplay_max = 4096;
7661                 htotal_max = 8192;
7662                 vtotal_max = 8192;
7663         } else {
7664                 hdisplay_max = 2048;
7665                 vdisplay_max = 2048;
7666                 htotal_max = 4096;
7667                 vtotal_max = 4096;
7668         }
7669
7670         if (mode->hdisplay > hdisplay_max ||
7671             mode->hsync_start > htotal_max ||
7672             mode->hsync_end > htotal_max ||
7673             mode->htotal > htotal_max)
7674                 return MODE_H_ILLEGAL;
7675
7676         if (mode->vdisplay > vdisplay_max ||
7677             mode->vsync_start > vtotal_max ||
7678             mode->vsync_end > vtotal_max ||
7679             mode->vtotal > vtotal_max)
7680                 return MODE_V_ILLEGAL;
7681
7682         if (DISPLAY_VER(dev_priv) >= 5) {
7683                 if (mode->hdisplay < 64 ||
7684                     mode->htotal - mode->hdisplay < 32)
7685                         return MODE_H_ILLEGAL;
7686
7687                 if (mode->vtotal - mode->vdisplay < 5)
7688                         return MODE_V_ILLEGAL;
7689         } else {
7690                 if (mode->htotal - mode->hdisplay < 32)
7691                         return MODE_H_ILLEGAL;
7692
7693                 if (mode->vtotal - mode->vdisplay < 3)
7694                         return MODE_V_ILLEGAL;
7695         }
7696
7697         /*
7698          * Cantiga+ cannot handle modes with a hsync front porch of 0.
7699          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7700          */
7701         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7702             mode->hsync_start == mode->hdisplay)
7703                 return MODE_H_ILLEGAL;
7704
7705         return MODE_OK;
7706 }
7707
7708 enum drm_mode_status
7709 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7710                                 const struct drm_display_mode *mode,
7711                                 bool bigjoiner)
7712 {
7713         int plane_width_max, plane_height_max;
7714
7715         /*
7716          * intel_mode_valid() should be
7717          * sufficient on older platforms.
7718          */
7719         if (DISPLAY_VER(dev_priv) < 9)
7720                 return MODE_OK;
7721
7722         /*
7723          * Most people will probably want a fullscreen
7724          * plane so let's not advertize modes that are
7725          * too big for that.
7726          */
7727         if (DISPLAY_VER(dev_priv) >= 11) {
7728                 plane_width_max = 5120 << bigjoiner;
7729                 plane_height_max = 4320;
7730         } else {
7731                 plane_width_max = 5120;
7732                 plane_height_max = 4096;
7733         }
7734
7735         if (mode->hdisplay > plane_width_max)
7736                 return MODE_H_ILLEGAL;
7737
7738         if (mode->vdisplay > plane_height_max)
7739                 return MODE_V_ILLEGAL;
7740
7741         return MODE_OK;
7742 }
7743
7744 static const struct intel_display_funcs skl_display_funcs = {
7745         .get_pipe_config = hsw_get_pipe_config,
7746         .crtc_enable = hsw_crtc_enable,
7747         .crtc_disable = hsw_crtc_disable,
7748         .commit_modeset_enables = skl_commit_modeset_enables,
7749         .get_initial_plane_config = skl_get_initial_plane_config,
7750 };
7751
7752 static const struct intel_display_funcs ddi_display_funcs = {
7753         .get_pipe_config = hsw_get_pipe_config,
7754         .crtc_enable = hsw_crtc_enable,
7755         .crtc_disable = hsw_crtc_disable,
7756         .commit_modeset_enables = intel_commit_modeset_enables,
7757         .get_initial_plane_config = i9xx_get_initial_plane_config,
7758 };
7759
7760 static const struct intel_display_funcs pch_split_display_funcs = {
7761         .get_pipe_config = ilk_get_pipe_config,
7762         .crtc_enable = ilk_crtc_enable,
7763         .crtc_disable = ilk_crtc_disable,
7764         .commit_modeset_enables = intel_commit_modeset_enables,
7765         .get_initial_plane_config = i9xx_get_initial_plane_config,
7766 };
7767
7768 static const struct intel_display_funcs vlv_display_funcs = {
7769         .get_pipe_config = i9xx_get_pipe_config,
7770         .crtc_enable = valleyview_crtc_enable,
7771         .crtc_disable = i9xx_crtc_disable,
7772         .commit_modeset_enables = intel_commit_modeset_enables,
7773         .get_initial_plane_config = i9xx_get_initial_plane_config,
7774 };
7775
7776 static const struct intel_display_funcs i9xx_display_funcs = {
7777         .get_pipe_config = i9xx_get_pipe_config,
7778         .crtc_enable = i9xx_crtc_enable,
7779         .crtc_disable = i9xx_crtc_disable,
7780         .commit_modeset_enables = intel_commit_modeset_enables,
7781         .get_initial_plane_config = i9xx_get_initial_plane_config,
7782 };
7783
7784 /**
7785  * intel_init_display_hooks - initialize the display modesetting hooks
7786  * @dev_priv: device private
7787  */
7788 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
7789 {
7790         if (DISPLAY_VER(dev_priv) >= 9) {
7791                 dev_priv->display.funcs.display = &skl_display_funcs;
7792         } else if (HAS_DDI(dev_priv)) {
7793                 dev_priv->display.funcs.display = &ddi_display_funcs;
7794         } else if (HAS_PCH_SPLIT(dev_priv)) {
7795                 dev_priv->display.funcs.display = &pch_split_display_funcs;
7796         } else if (IS_CHERRYVIEW(dev_priv) ||
7797                    IS_VALLEYVIEW(dev_priv)) {
7798                 dev_priv->display.funcs.display = &vlv_display_funcs;
7799         } else {
7800                 dev_priv->display.funcs.display = &i9xx_display_funcs;
7801         }
7802 }
7803
7804 int intel_initial_commit(struct drm_device *dev)
7805 {
7806         struct drm_atomic_state *state = NULL;
7807         struct drm_modeset_acquire_ctx ctx;
7808         struct intel_crtc *crtc;
7809         int ret = 0;
7810
7811         state = drm_atomic_state_alloc(dev);
7812         if (!state)
7813                 return -ENOMEM;
7814
7815         drm_modeset_acquire_init(&ctx, 0);
7816
7817         state->acquire_ctx = &ctx;
7818         to_intel_atomic_state(state)->internal = true;
7819
7820 retry:
7821         for_each_intel_crtc(dev, crtc) {
7822                 struct intel_crtc_state *crtc_state =
7823                         intel_atomic_get_crtc_state(state, crtc);
7824
7825                 if (IS_ERR(crtc_state)) {
7826                         ret = PTR_ERR(crtc_state);
7827                         goto out;
7828                 }
7829
7830                 if (crtc_state->hw.active) {
7831                         struct intel_encoder *encoder;
7832
7833                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
7834                         if (ret)
7835                                 goto out;
7836
7837                         /*
7838                          * FIXME hack to force a LUT update to avoid the
7839                          * plane update forcing the pipe gamma on without
7840                          * having a proper LUT loaded. Remove once we
7841                          * have readout for pipe gamma enable.
7842                          */
7843                         crtc_state->uapi.color_mgmt_changed = true;
7844
7845                         for_each_intel_encoder_mask(dev, encoder,
7846                                                     crtc_state->uapi.encoder_mask) {
7847                                 if (encoder->initial_fastset_check &&
7848                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
7849                                         ret = drm_atomic_add_affected_connectors(state,
7850                                                                                  &crtc->base);
7851                                         if (ret)
7852                                                 goto out;
7853                                 }
7854                         }
7855                 }
7856         }
7857
7858         ret = drm_atomic_commit(state);
7859
7860 out:
7861         if (ret == -EDEADLK) {
7862                 drm_atomic_state_clear(state);
7863                 drm_modeset_backoff(&ctx);
7864                 goto retry;
7865         }
7866
7867         drm_atomic_state_put(state);
7868
7869         drm_modeset_drop_locks(&ctx);
7870         drm_modeset_acquire_fini(&ctx);
7871
7872         return ret;
7873 }
7874
7875 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
7876 {
7877         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
7878         enum transcoder cpu_transcoder = (enum transcoder)pipe;
7879         /* 640x480@60Hz, ~25175 kHz */
7880         struct dpll clock = {
7881                 .m1 = 18,
7882                 .m2 = 7,
7883                 .p1 = 13,
7884                 .p2 = 4,
7885                 .n = 2,
7886         };
7887         u32 dpll, fp;
7888         int i;
7889
7890         drm_WARN_ON(&dev_priv->drm,
7891                     i9xx_calc_dpll_params(48000, &clock) != 25154);
7892
7893         drm_dbg_kms(&dev_priv->drm,
7894                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
7895                     pipe_name(pipe), clock.vco, clock.dot);
7896
7897         fp = i9xx_dpll_compute_fp(&clock);
7898         dpll = DPLL_DVO_2X_MODE |
7899                 DPLL_VGA_MODE_DIS |
7900                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
7901                 PLL_P2_DIVIDE_BY_4 |
7902                 PLL_REF_INPUT_DREFCLK |
7903                 DPLL_VCO_ENABLE;
7904
7905         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
7906                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
7907         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
7908                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
7909         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
7910                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
7911         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
7912                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
7913         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
7914                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
7915         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
7916                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
7917         intel_de_write(dev_priv, PIPESRC(pipe),
7918                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
7919
7920         intel_de_write(dev_priv, FP0(pipe), fp);
7921         intel_de_write(dev_priv, FP1(pipe), fp);
7922
7923         /*
7924          * Apparently we need to have VGA mode enabled prior to changing
7925          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
7926          * dividers, even though the register value does change.
7927          */
7928         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
7929         intel_de_write(dev_priv, DPLL(pipe), dpll);
7930
7931         /* Wait for the clocks to stabilize. */
7932         intel_de_posting_read(dev_priv, DPLL(pipe));
7933         udelay(150);
7934
7935         /* The pixel multiplier can only be updated once the
7936          * DPLL is enabled and the clocks are stable.
7937          *
7938          * So write it again.
7939          */
7940         intel_de_write(dev_priv, DPLL(pipe), dpll);
7941
7942         /* We do this three times for luck */
7943         for (i = 0; i < 3 ; i++) {
7944                 intel_de_write(dev_priv, DPLL(pipe), dpll);
7945                 intel_de_posting_read(dev_priv, DPLL(pipe));
7946                 udelay(150); /* wait for warmup */
7947         }
7948
7949         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
7950         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
7951
7952         intel_wait_for_pipe_scanline_moving(crtc);
7953 }
7954
7955 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
7956 {
7957         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
7958
7959         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
7960                     pipe_name(pipe));
7961
7962         drm_WARN_ON(&dev_priv->drm,
7963                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
7964         drm_WARN_ON(&dev_priv->drm,
7965                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
7966         drm_WARN_ON(&dev_priv->drm,
7967                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
7968         drm_WARN_ON(&dev_priv->drm,
7969                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
7970         drm_WARN_ON(&dev_priv->drm,
7971                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
7972
7973         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
7974         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
7975
7976         intel_wait_for_pipe_scanline_stopped(crtc);
7977
7978         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
7979         intel_de_posting_read(dev_priv, DPLL(pipe));
7980 }
7981
7982 void intel_hpd_poll_fini(struct drm_i915_private *i915)
7983 {
7984         struct intel_connector *connector;
7985         struct drm_connector_list_iter conn_iter;
7986
7987         /* Kill all the work that may have been queued by hpd. */
7988         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
7989         for_each_intel_connector_iter(connector, &conn_iter) {
7990                 if (connector->modeset_retry_work.func)
7991                         cancel_work_sync(&connector->modeset_retry_work);
7992                 if (connector->hdcp.shim) {
7993                         cancel_delayed_work_sync(&connector->hdcp.check_work);
7994                         cancel_work_sync(&connector->hdcp.prop_work);
7995                 }
7996         }
7997         drm_connector_list_iter_end(&conn_iter);
7998 }
7999
8000 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8001 {
8002         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8003 }