drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_damage_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "gem/i915_gem_lmem.h"
  46 #include "gem/i915_gem_object.h"
  47
  48 #include "g4x_dp.h"
  49 #include "g4x_hdmi.h"
  50 #include "hsw_ips.h"
  51 #include "i915_drv.h"
  52 #include "i915_reg.h"
  53 #include "i915_utils.h"
  54 #include "i9xx_plane.h"
  55 #include "i9xx_wm.h"
  56 #include "icl_dsi.h"
  57 #include "intel_atomic.h"
  58 #include "intel_atomic_plane.h"
  59 #include "intel_audio.h"
  60 #include "intel_bw.h"
  61 #include "intel_cdclk.h"
  62 #include "intel_clock_gating.h"
  63 #include "intel_color.h"
  64 #include "intel_crt.h"
  65 #include "intel_crtc.h"
  66 #include "intel_crtc_state_dump.h"
  67 #include "intel_ddi.h"
  68 #include "intel_de.h"
  69 #include "intel_display_driver.h"
  70 #include "intel_display_power.h"
  71 #include "intel_display_types.h"
  72 #include "intel_dmc.h"
  73 #include "intel_dp.h"
  74 #include "intel_dp_link_training.h"
  75 #include "intel_dp_mst.h"
  76 #include "intel_dpio_phy.h"
  77 #include "intel_dpll.h"
  78 #include "intel_dpll_mgr.h"
  79 #include "intel_dpt.h"
  80 #include "intel_drrs.h"
  81 #include "intel_dsi.h"
  82 #include "intel_dvo.h"
  83 #include "intel_fb.h"
  84 #include "intel_fbc.h"
  85 #include "intel_fbdev.h"
  86 #include "intel_fdi.h"
  87 #include "intel_fifo_underrun.h"
  88 #include "intel_frontbuffer.h"
  89 #include "intel_hdmi.h"
  90 #include "intel_hotplug.h"
  91 #include "intel_lvds.h"
  92 #include "intel_lvds_regs.h"
  93 #include "intel_modeset_setup.h"
  94 #include "intel_modeset_verify.h"
  95 #include "intel_overlay.h"
  96 #include "intel_panel.h"
  97 #include "intel_pch_display.h"
  98 #include "intel_pch_refclk.h"
  99 #include "intel_pcode.h"
 100 #include "intel_pipe_crc.h"
 101 #include "intel_plane_initial.h"
 102 #include "intel_pmdemand.h"
 103 #include "intel_pps.h"
 104 #include "intel_psr.h"
 105 #include "intel_sdvo.h"
 106 #include "intel_snps_phy.h"
 107 #include "intel_tc.h"
 108 #include "intel_tv.h"
 109 #include "intel_vblank.h"
 110 #include "intel_vdsc.h"
 111 #include "intel_vdsc_regs.h"
 112 #include "intel_vga.h"
 113 #include "intel_vrr.h"
 114 #include "intel_wm.h"
 115 #include "skl_scaler.h"
 116 #include "skl_universal_plane.h"
 117 #include "skl_watermark.h"
 118 #include "vlv_dsi.h"
 119 #include "vlv_dsi_pll.h"
 120 #include "vlv_dsi_regs.h"
 121 #include "vlv_sideband.h"
 122
 123 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 124 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 125 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 126 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 127
 128 /* returns HPLL frequency in kHz */
 129 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 130 {
 131         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 132
 133         /* Obtain SKU information */
 134         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 135                 CCK_FUSE_HPLL_FREQ_MASK;
 136
 137         return vco_freq[hpll_freq] * 1000;
 138 }
 139
 140 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 141                       const char *name, u32 reg, int ref_freq)
 142 {
 143         u32 val;
 144         int divider;
 145
 146         val = vlv_cck_read(dev_priv, reg);
 147         divider = val & CCK_FREQUENCY_VALUES;
 148
 149         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 150                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 151                  "%s change in progress\n", name);
 152
 153         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 154 }
 155
 156 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 157                            const char *name, u32 reg)
 158 {
 159         int hpll;
 160
 161         vlv_cck_get(dev_priv);
 162
 163         if (dev_priv->hpll_freq == 0)
 164                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 165
 166         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 167
 168         vlv_cck_put(dev_priv);
 169
 170         return hpll;
 171 }
 172
 173 void intel_update_czclk(struct drm_i915_private *dev_priv)
 174 {
 175         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 176                 return;
 177
 178         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 179                                                       CCK_CZ_CLOCK_CONTROL);
 180
 181         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 182                 dev_priv->czclk_freq);
 183 }
 184
 185 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 186 {
 187         return (crtc_state->active_planes &
 188                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 189 }
 190
 191 /* WA Display #0827: Gen9:all */
 192 static void
 193 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 194 {
 195         if (enable)
 196                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 197                              0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 198         else
 199                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 200                              DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);
 201 }
 202
 203 /* Wa_2006604312:icl,ehl */
 204 static void
 205 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 206                        bool enable)
 207 {
 208         if (enable)
 209                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);
 210         else
 211                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);
 212 }
 213
 214 /* Wa_1604331009:icl,jsl,ehl */
 215 static void
 216 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 217                        bool enable)
 218 {
 219         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 220                      enable ? CURSOR_GATING_DIS : 0);
 221 }
 222
 223 static bool
 224 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 225 {
 226         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 227 }
 228
 229 bool
 230 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 231 {
 232         return crtc_state->sync_mode_slaves_mask != 0;
 233 }
 234
 235 bool
 236 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 237 {
 238         return is_trans_port_sync_master(crtc_state) ||
 239                 is_trans_port_sync_slave(crtc_state);
 240 }
 241
 242 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 243 {
 244         return ffs(crtc_state->bigjoiner_pipes) - 1;
 245 }
 246
 247 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 248 {
 249         if (crtc_state->bigjoiner_pipes)
 250                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 251         else
 252                 return 0;
 253 }
 254
 255 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 256 {
 257         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 258
 259         return crtc_state->bigjoiner_pipes &&
 260                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 261 }
 262
 263 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 264 {
 265         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 266
 267         return crtc_state->bigjoiner_pipes &&
 268                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 269 }
 270
 271 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 272 {
 273         return hweight8(crtc_state->bigjoiner_pipes);
 274 }
 275
 276 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 277 {
 278         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 279
 280         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 281                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 282         else
 283                 return to_intel_crtc(crtc_state->uapi.crtc);
 284 }
 285
 286 static void
 287 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 288 {
 289         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 290         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 291
 292         if (DISPLAY_VER(dev_priv) >= 4) {
 293                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 294
 295                 /* Wait for the Pipe State to go off */
 296                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 297                                             TRANSCONF_STATE_ENABLE, 100))
 298                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 299         } else {
 300                 intel_wait_for_pipe_scanline_stopped(crtc);
 301         }
 302 }
 303
 304 void assert_transcoder(struct drm_i915_private *dev_priv,
 305                        enum transcoder cpu_transcoder, bool state)
 306 {
 307         bool cur_state;
 308         enum intel_display_power_domain power_domain;
 309         intel_wakeref_t wakeref;
 310
 311         /* we keep both pipes enabled on 830 */
 312         if (IS_I830(dev_priv))
 313                 state = true;
 314
 315         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 316         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 317         if (wakeref) {
 318                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 319                 cur_state = !!(val & TRANSCONF_ENABLE);
 320
 321                 intel_display_power_put(dev_priv, power_domain, wakeref);
 322         } else {
 323                 cur_state = false;
 324         }
 325
 326         I915_STATE_WARN(dev_priv, cur_state != state,
 327                         "transcoder %s assertion failure (expected %s, current %s)\n",
 328                         transcoder_name(cpu_transcoder), str_on_off(state),
 329                         str_on_off(cur_state));
 330 }
 331
 332 static void assert_plane(struct intel_plane *plane, bool state)
 333 {
 334         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 335         enum pipe pipe;
 336         bool cur_state;
 337
 338         cur_state = plane->get_hw_state(plane, &pipe);
 339
 340         I915_STATE_WARN(i915, cur_state != state,
 341                         "%s assertion failure (expected %s, current %s)\n",
 342                         plane->base.name, str_on_off(state),
 343                         str_on_off(cur_state));
 344 }
 345
 346 #define assert_plane_enabled(p) assert_plane(p, true)
 347 #define assert_plane_disabled(p) assert_plane(p, false)
 348
 349 static void assert_planes_disabled(struct intel_crtc *crtc)
 350 {
 351         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 352         struct intel_plane *plane;
 353
 354         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 355                 assert_plane_disabled(plane);
 356 }
 357
 358 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 359                          struct intel_digital_port *dig_port,
 360                          unsigned int expected_mask)
 361 {
 362         u32 port_mask;
 363         i915_reg_t dpll_reg;
 364
 365         switch (dig_port->base.port) {
 366         default:
 367                 MISSING_CASE(dig_port->base.port);
 368                 fallthrough;
 369         case PORT_B:
 370                 port_mask = DPLL_PORTB_READY_MASK;
 371                 dpll_reg = DPLL(0);
 372                 break;
 373         case PORT_C:
 374                 port_mask = DPLL_PORTC_READY_MASK;
 375                 dpll_reg = DPLL(0);
 376                 expected_mask <<= 4;
 377                 break;
 378         case PORT_D:
 379                 port_mask = DPLL_PORTD_READY_MASK;
 380                 dpll_reg = DPIO_PHY_STATUS;
 381                 break;
 382         }
 383
 384         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 385                                        port_mask, expected_mask, 1000))
 386                 drm_WARN(&dev_priv->drm, 1,
 387                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 388                          dig_port->base.base.base.id, dig_port->base.base.name,
 389                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 390                          expected_mask);
 391 }
 392
 393 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 394 {
 395         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 396         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 397         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 398         enum pipe pipe = crtc->pipe;
 399         i915_reg_t reg;
 400         u32 val;
 401
 402         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 403
 404         assert_planes_disabled(crtc);
 405
 406         /*
 407          * A pipe without a PLL won't actually be able to drive bits from
 408          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 409          * need the check.
 410          */
 411         if (HAS_GMCH(dev_priv)) {
 412                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 413                         assert_dsi_pll_enabled(dev_priv);
 414                 else
 415                         assert_pll_enabled(dev_priv, pipe);
 416         } else {
 417                 if (new_crtc_state->has_pch_encoder) {
 418                         /* if driving the PCH, we need FDI enabled */
 419                         assert_fdi_rx_pll_enabled(dev_priv,
 420                                                   intel_crtc_pch_transcoder(crtc));
 421                         assert_fdi_tx_pll_enabled(dev_priv,
 422                                                   (enum pipe) cpu_transcoder);
 423                 }
 424                 /* FIXME: assert CPU port conditions for SNB+ */
 425         }
 426
 427         /* Wa_22012358565:adl-p */
 428         if (DISPLAY_VER(dev_priv) == 13)
 429                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 430                              0, PIPE_ARB_USE_PROG_SLOTS);
 431
 432         reg = TRANSCONF(cpu_transcoder);
 433         val = intel_de_read(dev_priv, reg);
 434         if (val & TRANSCONF_ENABLE) {
 435                 /* we keep both pipes enabled on 830 */
 436                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 437                 return;
 438         }
 439
 440         intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
 441         intel_de_posting_read(dev_priv, reg);
 442
 443         /*
 444          * Until the pipe starts PIPEDSL reads will return a stale value,
 445          * which causes an apparent vblank timestamp jump when PIPEDSL
 446          * resets to its proper value. That also messes up the frame count
 447          * when it's derived from the timestamps. So let's wait for the
 448          * pipe to start properly before we call drm_crtc_vblank_on()
 449          */
 450         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 451                 intel_wait_for_pipe_scanline_moving(crtc);
 452 }
 453
 454 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 455 {
 456         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 458         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 459         enum pipe pipe = crtc->pipe;
 460         i915_reg_t reg;
 461         u32 val;
 462
 463         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 464
 465         /*
 466          * Make sure planes won't keep trying to pump pixels to us,
 467          * or we might hang the display.
 468          */
 469         assert_planes_disabled(crtc);
 470
 471         reg = TRANSCONF(cpu_transcoder);
 472         val = intel_de_read(dev_priv, reg);
 473         if ((val & TRANSCONF_ENABLE) == 0)
 474                 return;
 475
 476         /*
 477          * Double wide has implications for planes
 478          * so best keep it disabled when not needed.
 479          */
 480         if (old_crtc_state->double_wide)
 481                 val &= ~TRANSCONF_DOUBLE_WIDE;
 482
 483         /* Don't disable pipe or pipe PLLs if needed */
 484         if (!IS_I830(dev_priv))
 485                 val &= ~TRANSCONF_ENABLE;
 486
 487         if (DISPLAY_VER(dev_priv) >= 14)
 488                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
 489                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 490         else if (DISPLAY_VER(dev_priv) >= 12)
 491                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 492                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 493
 494         intel_de_write(dev_priv, reg, val);
 495         if ((val & TRANSCONF_ENABLE) == 0)
 496                 intel_wait_for_pipe_off(old_crtc_state);
 497 }
 498
 499 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 500 {
 501         unsigned int size = 0;
 502         int i;
 503
 504         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 505                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 506
 507         return size;
 508 }
 509
 510 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 511 {
 512         unsigned int size = 0;
 513         int i;
 514
 515         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 516                 unsigned int plane_size;
 517
 518                 if (rem_info->plane[i].linear)
 519                         plane_size = rem_info->plane[i].size;
 520                 else
 521                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 522
 523                 if (plane_size == 0)
 524                         continue;
 525
 526                 if (rem_info->plane_alignment)
 527                         size = ALIGN(size, rem_info->plane_alignment);
 528
 529                 size += plane_size;
 530         }
 531
 532         return size;
 533 }
 534
 535 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 536 {
 537         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 538         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 539
 540         return DISPLAY_VER(dev_priv) < 4 ||
 541                 (plane->fbc &&
 542                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 543 }
 544
 545 /*
 546  * Convert the x/y offsets into a linear offset.
 547  * Only valid with 0/180 degree rotation, which is fine since linear
 548  * offset is only used with linear buffers on pre-hsw and tiled buffers
 549  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 550  */
 551 u32 intel_fb_xy_to_linear(int x, int y,
 552                           const struct intel_plane_state *state,
 553                           int color_plane)
 554 {
 555         const struct drm_framebuffer *fb = state->hw.fb;
 556         unsigned int cpp = fb->format->cpp[color_plane];
 557         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 558
 559         return y * pitch + x * cpp;
 560 }
 561
 562 /*
 563  * Add the x/y offsets derived from fb->offsets[] to the user
 564  * specified plane src x/y offsets. The resulting x/y offsets
 565  * specify the start of scanout from the beginning of the gtt mapping.
 566  */
 567 void intel_add_fb_offsets(int *x, int *y,
 568                           const struct intel_plane_state *state,
 569                           int color_plane)
 570
 571 {
 572         *x += state->view.color_plane[color_plane].x;
 573         *y += state->view.color_plane[color_plane].y;
 574 }
 575
 576 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 577                               u32 pixel_format, u64 modifier)
 578 {
 579         struct intel_crtc *crtc;
 580         struct intel_plane *plane;
 581
 582         if (!HAS_DISPLAY(dev_priv))
 583                 return 0;
 584
 585         /*
 586          * We assume the primary plane for pipe A has
 587          * the highest stride limits of them all,
 588          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 589          */
 590         crtc = intel_first_crtc(dev_priv);
 591         if (!crtc)
 592                 return 0;
 593
 594         plane = to_intel_plane(crtc->base.primary);
 595
 596         return plane->max_stride(plane, pixel_format, modifier,
 597                                  DRM_MODE_ROTATE_0);
 598 }
 599
 600 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 601                              struct intel_plane_state *plane_state,
 602                              bool visible)
 603 {
 604         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 605
 606         plane_state->uapi.visible = visible;
 607
 608         if (visible)
 609                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 610         else
 611                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 612 }
 613
 614 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 615 {
 616         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 617         struct drm_plane *plane;
 618
 619         /*
 620          * Active_planes aliases if multiple "primary" or cursor planes
 621          * have been used on the same (or wrong) pipe. plane_mask uses
 622          * unique ids, hence we can use that to reconstruct active_planes.
 623          */
 624         crtc_state->enabled_planes = 0;
 625         crtc_state->active_planes = 0;
 626
 627         drm_for_each_plane_mask(plane, &dev_priv->drm,
 628                                 crtc_state->uapi.plane_mask) {
 629                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 630                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 631         }
 632 }
 633
 634 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 635                                   struct intel_plane *plane)
 636 {
 637         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 638         struct intel_crtc_state *crtc_state =
 639                 to_intel_crtc_state(crtc->base.state);
 640         struct intel_plane_state *plane_state =
 641                 to_intel_plane_state(plane->base.state);
 642
 643         drm_dbg_kms(&dev_priv->drm,
 644                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 645                     plane->base.base.id, plane->base.name,
 646                     crtc->base.base.id, crtc->base.name);
 647
 648         intel_set_plane_visible(crtc_state, plane_state, false);
 649         intel_plane_fixup_bitmasks(crtc_state);
 650         crtc_state->data_rate[plane->id] = 0;
 651         crtc_state->data_rate_y[plane->id] = 0;
 652         crtc_state->rel_data_rate[plane->id] = 0;
 653         crtc_state->rel_data_rate_y[plane->id] = 0;
 654         crtc_state->min_cdclk[plane->id] = 0;
 655
 656         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 657             hsw_ips_disable(crtc_state)) {
 658                 crtc_state->ips_enabled = false;
 659                 intel_crtc_wait_for_next_vblank(crtc);
 660         }
 661
 662         /*
 663          * Vblank time updates from the shadow to live plane control register
 664          * are blocked if the memory self-refresh mode is active at that
 665          * moment. So to make sure the plane gets truly disabled, disable
 666          * first the self-refresh mode. The self-refresh enable bit in turn
 667          * will be checked/applied by the HW only at the next frame start
 668          * event which is after the vblank start event, so we need to have a
 669          * wait-for-vblank between disabling the plane and the pipe.
 670          */
 671         if (HAS_GMCH(dev_priv) &&
 672             intel_set_memory_cxsr(dev_priv, false))
 673                 intel_crtc_wait_for_next_vblank(crtc);
 674
 675         /*
 676          * Gen2 reports pipe underruns whenever all planes are disabled.
 677          * So disable underrun reporting before all the planes get disabled.
 678          */
 679         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 680                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 681
 682         intel_plane_disable_arm(plane, crtc_state);
 683         intel_crtc_wait_for_next_vblank(crtc);
 684 }
 685
 686 unsigned int
 687 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 688 {
 689         int x = 0, y = 0;
 690
 691         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 692                                           plane_state->view.color_plane[0].offset, 0);
 693
 694         return y;
 695 }
 696
 697 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 698 {
 699         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 700         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 701         enum pipe pipe = crtc->pipe;
 702         u32 tmp;
 703
 704         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 705
 706         /*
 707          * Display WA #1153: icl
 708          * enable hardware to bypass the alpha math
 709          * and rounding for per-pixel values 00 and 0xff
 710          */
 711         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 712         /*
 713          * Display WA # 1605353570: icl
 714          * Set the pixel rounding bit to 1 for allowing
 715          * passthrough of Frame buffer pixels unmodified
 716          * across pipe
 717          */
 718         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 719
 720         /*
 721          * Underrun recovery must always be disabled on display 13+.
 722          * DG2 chicken bit meaning is inverted compared to other platforms.
 723          */
 724         if (IS_DG2(dev_priv))
 725                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 726         else if (DISPLAY_VER(dev_priv) >= 13)
 727                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 728
 729         /* Wa_14010547955:dg2 */
 730         if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
 731                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 732
 733         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 734 }
 735
 736 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 737 {
 738         struct drm_crtc *crtc;
 739         bool cleanup_done;
 740
 741         drm_for_each_crtc(crtc, &dev_priv->drm) {
 742                 struct drm_crtc_commit *commit;
 743                 spin_lock(&crtc->commit_lock);
 744                 commit = list_first_entry_or_null(&crtc->commit_list,
 745                                                   struct drm_crtc_commit, commit_entry);
 746                 cleanup_done = commit ?
 747                         try_wait_for_completion(&commit->cleanup_done) : true;
 748                 spin_unlock(&crtc->commit_lock);
 749
 750                 if (cleanup_done)
 751                         continue;
 752
 753                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 754
 755                 return true;
 756         }
 757
 758         return false;
 759 }
 760
 761 /*
 762  * Finds the encoder associated with the given CRTC. This can only be
 763  * used when we know that the CRTC isn't feeding multiple encoders!
 764  */
 765 struct intel_encoder *
 766 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 767                            const struct intel_crtc_state *crtc_state)
 768 {
 769         const struct drm_connector_state *connector_state;
 770         const struct drm_connector *connector;
 771         struct intel_encoder *encoder = NULL;
 772         struct intel_crtc *master_crtc;
 773         int num_encoders = 0;
 774         int i;
 775
 776         master_crtc = intel_master_crtc(crtc_state);
 777
 778         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 779                 if (connector_state->crtc != &master_crtc->base)
 780                         continue;
 781
 782                 encoder = to_intel_encoder(connector_state->best_encoder);
 783                 num_encoders++;
 784         }
 785
 786         drm_WARN(state->base.dev, num_encoders != 1,
 787                  "%d encoders for pipe %c\n",
 788                  num_encoders, pipe_name(master_crtc->pipe));
 789
 790         return encoder;
 791 }
 792
 793 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 794 {
 795         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 796         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 797         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 798         enum pipe pipe = crtc->pipe;
 799         int width = drm_rect_width(dst);
 800         int height = drm_rect_height(dst);
 801         int x = dst->x1;
 802         int y = dst->y1;
 803
 804         if (!crtc_state->pch_pfit.enabled)
 805                 return;
 806
 807         /* Force use of hard-coded filter coefficients
 808          * as some pre-programmed values are broken,
 809          * e.g. x201.
 810          */
 811         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 812                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 813                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 814         else
 815                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 816                                   PF_FILTER_MED_3x3);
 817         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
 818                           PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
 819         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
 820                           PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 821 }
 822
 823 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 824 {
 825         if (crtc->overlay)
 826                 (void) intel_overlay_switch_off(crtc->overlay);
 827
 828         /* Let userspace switch the overlay on again. In most cases userspace
 829          * has to recompute where to put it anyway.
 830          */
 831 }
 832
 833 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 834 {
 835         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 836
 837         if (!crtc_state->nv12_planes)
 838                 return false;
 839
 840         /* WA Display #0827: Gen9:all */
 841         if (DISPLAY_VER(dev_priv) == 9)
 842                 return true;
 843
 844         return false;
 845 }
 846
 847 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 850
 851         /* Wa_2006604312:icl,ehl */
 852         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
 853                 return true;
 854
 855         return false;
 856 }
 857
 858 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 859 {
 860         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 861
 862         /* Wa_1604331009:icl,jsl,ehl */
 863         if (is_hdr_mode(crtc_state) &&
 864             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 865             DISPLAY_VER(dev_priv) == 11)
 866                 return true;
 867
 868         return false;
 869 }
 870
 871 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
 872                                     enum pipe pipe, bool enable)
 873 {
 874         if (DISPLAY_VER(i915) == 9) {
 875                 /*
 876                  * "Plane N strech max must be programmed to 11b (x1)
 877                  *  when Async flips are enabled on that plane."
 878                  */
 879                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 880                              SKL_PLANE1_STRETCH_MAX_MASK,
 881                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 882         } else {
 883                 /* Also needed on HSW/BDW albeit undocumented */
 884                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 885                              HSW_PRI_STRETCH_MAX_MASK,
 886                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 887         }
 888 }
 889
 890 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 891 {
 892         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 893
 894         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
 895                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
 896 }
 897
 898 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
 899         ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 900          (new_crtc_state)->feature)
 901 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
 902         ((old_crtc_state)->feature && \
 903          (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 904
 905 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 906                             const struct intel_crtc_state *new_crtc_state)
 907 {
 908         return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 909 }
 910
 911 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 912                              const struct intel_crtc_state *new_crtc_state)
 913 {
 914         return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 915 }
 916
 917 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 918                          const struct intel_crtc_state *new_crtc_state)
 919 {
 920         return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
 921 }
 922
 923 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 924                           const struct intel_crtc_state *new_crtc_state)
 925 {
 926         return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
 927 }
 928
 929 #undef is_disabling
 930 #undef is_enabling
 931
 932 static void intel_post_plane_update(struct intel_atomic_state *state,
 933                                     struct intel_crtc *crtc)
 934 {
 935         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 936         const struct intel_crtc_state *old_crtc_state =
 937                 intel_atomic_get_old_crtc_state(state, crtc);
 938         const struct intel_crtc_state *new_crtc_state =
 939                 intel_atomic_get_new_crtc_state(state, crtc);
 940         enum pipe pipe = crtc->pipe;
 941
 942         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 943
 944         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 945                 intel_update_watermarks(dev_priv);
 946
 947         intel_fbc_post_update(state, crtc);
 948
 949         if (needs_async_flip_vtd_wa(old_crtc_state) &&
 950             !needs_async_flip_vtd_wa(new_crtc_state))
 951                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
 952
 953         if (needs_nv12_wa(old_crtc_state) &&
 954             !needs_nv12_wa(new_crtc_state))
 955                 skl_wa_827(dev_priv, pipe, false);
 956
 957         if (needs_scalerclk_wa(old_crtc_state) &&
 958             !needs_scalerclk_wa(new_crtc_state))
 959                 icl_wa_scalerclkgating(dev_priv, pipe, false);
 960
 961         if (needs_cursorclk_wa(old_crtc_state) &&
 962             !needs_cursorclk_wa(new_crtc_state))
 963                 icl_wa_cursorclkgating(dev_priv, pipe, false);
 964
 965         if (intel_crtc_needs_color_update(new_crtc_state))
 966                 intel_color_post_update(new_crtc_state);
 967 }
 968
 969 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
 970                                         struct intel_crtc *crtc)
 971 {
 972         const struct intel_crtc_state *crtc_state =
 973                 intel_atomic_get_new_crtc_state(state, crtc);
 974         u8 update_planes = crtc_state->update_planes;
 975         const struct intel_plane_state __maybe_unused *plane_state;
 976         struct intel_plane *plane;
 977         int i;
 978
 979         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 980                 if (plane->pipe == crtc->pipe &&
 981                     update_planes & BIT(plane->id))
 982                         plane->enable_flip_done(plane);
 983         }
 984 }
 985
 986 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
 987                                          struct intel_crtc *crtc)
 988 {
 989         const struct intel_crtc_state *crtc_state =
 990                 intel_atomic_get_new_crtc_state(state, crtc);
 991         u8 update_planes = crtc_state->update_planes;
 992         const struct intel_plane_state __maybe_unused *plane_state;
 993         struct intel_plane *plane;
 994         int i;
 995
 996         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 997                 if (plane->pipe == crtc->pipe &&
 998                     update_planes & BIT(plane->id))
 999                         plane->disable_flip_done(plane);
1000         }
1001 }
1002
1003 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1004                                              struct intel_crtc *crtc)
1005 {
1006         const struct intel_crtc_state *old_crtc_state =
1007                 intel_atomic_get_old_crtc_state(state, crtc);
1008         const struct intel_crtc_state *new_crtc_state =
1009                 intel_atomic_get_new_crtc_state(state, crtc);
1010         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1011                                        ~new_crtc_state->async_flip_planes;
1012         const struct intel_plane_state *old_plane_state;
1013         struct intel_plane *plane;
1014         bool need_vbl_wait = false;
1015         int i;
1016
1017         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1018                 if (plane->need_async_flip_disable_wa &&
1019                     plane->pipe == crtc->pipe &&
1020                     disable_async_flip_planes & BIT(plane->id)) {
1021                         /*
1022                          * Apart from the async flip bit we want to
1023                          * preserve the old state for the plane.
1024                          */
1025                         plane->async_flip(plane, old_crtc_state,
1026                                           old_plane_state, false);
1027                         need_vbl_wait = true;
1028                 }
1029         }
1030
1031         if (need_vbl_wait)
1032                 intel_crtc_wait_for_next_vblank(crtc);
1033 }
1034
1035 static void intel_pre_plane_update(struct intel_atomic_state *state,
1036                                    struct intel_crtc *crtc)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1039         const struct intel_crtc_state *old_crtc_state =
1040                 intel_atomic_get_old_crtc_state(state, crtc);
1041         const struct intel_crtc_state *new_crtc_state =
1042                 intel_atomic_get_new_crtc_state(state, crtc);
1043         enum pipe pipe = crtc->pipe;
1044
1045         if (vrr_disabling(old_crtc_state, new_crtc_state)) {
1046                 intel_vrr_disable(old_crtc_state);
1047                 intel_crtc_update_active_timings(old_crtc_state, false);
1048         }
1049
1050         intel_drrs_deactivate(old_crtc_state);
1051
1052         intel_psr_pre_plane_update(state, crtc);
1053
1054         if (hsw_ips_pre_update(state, crtc))
1055                 intel_crtc_wait_for_next_vblank(crtc);
1056
1057         if (intel_fbc_pre_update(state, crtc))
1058                 intel_crtc_wait_for_next_vblank(crtc);
1059
1060         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1061             needs_async_flip_vtd_wa(new_crtc_state))
1062                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1063
1064         /* Display WA 827 */
1065         if (!needs_nv12_wa(old_crtc_state) &&
1066             needs_nv12_wa(new_crtc_state))
1067                 skl_wa_827(dev_priv, pipe, true);
1068
1069         /* Wa_2006604312:icl,ehl */
1070         if (!needs_scalerclk_wa(old_crtc_state) &&
1071             needs_scalerclk_wa(new_crtc_state))
1072                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1073
1074         /* Wa_1604331009:icl,jsl,ehl */
1075         if (!needs_cursorclk_wa(old_crtc_state) &&
1076             needs_cursorclk_wa(new_crtc_state))
1077                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1078
1079         /*
1080          * Vblank time updates from the shadow to live plane control register
1081          * are blocked if the memory self-refresh mode is active at that
1082          * moment. So to make sure the plane gets truly disabled, disable
1083          * first the self-refresh mode. The self-refresh enable bit in turn
1084          * will be checked/applied by the HW only at the next frame start
1085          * event which is after the vblank start event, so we need to have a
1086          * wait-for-vblank between disabling the plane and the pipe.
1087          */
1088         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1089             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1090                 intel_crtc_wait_for_next_vblank(crtc);
1091
1092         /*
1093          * IVB workaround: must disable low power watermarks for at least
1094          * one frame before enabling scaling.  LP watermarks can be re-enabled
1095          * when scaling is disabled.
1096          *
1097          * WaCxSRDisabledForSpriteScaling:ivb
1098          */
1099         if (old_crtc_state->hw.active &&
1100             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1101                 intel_crtc_wait_for_next_vblank(crtc);
1102
1103         /*
1104          * If we're doing a modeset we don't need to do any
1105          * pre-vblank watermark programming here.
1106          */
1107         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1108                 /*
1109                  * For platforms that support atomic watermarks, program the
1110                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1111                  * will be the intermediate values that are safe for both pre- and
1112                  * post- vblank; when vblank happens, the 'active' values will be set
1113                  * to the final 'target' values and we'll do this again to get the
1114                  * optimal watermarks.  For gen9+ platforms, the values we program here
1115                  * will be the final target values which will get automatically latched
1116                  * at vblank time; no further programming will be necessary.
1117                  *
1118                  * If a platform hasn't been transitioned to atomic watermarks yet,
1119                  * we'll continue to update watermarks the old way, if flags tell
1120                  * us to.
1121                  */
1122                 if (!intel_initial_watermarks(state, crtc))
1123                         if (new_crtc_state->update_wm_pre)
1124                                 intel_update_watermarks(dev_priv);
1125         }
1126
1127         /*
1128          * Gen2 reports pipe underruns whenever all planes are disabled.
1129          * So disable underrun reporting before all the planes get disabled.
1130          *
1131          * We do this after .initial_watermarks() so that we have a
1132          * chance of catching underruns with the intermediate watermarks
1133          * vs. the old plane configuration.
1134          */
1135         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1136                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1137
1138         /*
1139          * WA for platforms where async address update enable bit
1140          * is double buffered and only latched at start of vblank.
1141          */
1142         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1143                 intel_crtc_async_flip_disable_wa(state, crtc);
1144 }
1145
1146 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1147                                       struct intel_crtc *crtc)
1148 {
1149         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1150         const struct intel_crtc_state *new_crtc_state =
1151                 intel_atomic_get_new_crtc_state(state, crtc);
1152         unsigned int update_mask = new_crtc_state->update_planes;
1153         const struct intel_plane_state *old_plane_state;
1154         struct intel_plane *plane;
1155         unsigned fb_bits = 0;
1156         int i;
1157
1158         intel_crtc_dpms_overlay_disable(crtc);
1159
1160         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1161                 if (crtc->pipe != plane->pipe ||
1162                     !(update_mask & BIT(plane->id)))
1163                         continue;
1164
1165                 intel_plane_disable_arm(plane, new_crtc_state);
1166
1167                 if (old_plane_state->uapi.visible)
1168                         fb_bits |= plane->frontbuffer_bit;
1169         }
1170
1171         intel_frontbuffer_flip(dev_priv, fb_bits);
1172 }
1173
1174 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1175 {
1176         struct drm_i915_private *i915 = to_i915(state->base.dev);
1177         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1178         struct intel_crtc *crtc;
1179         int i;
1180
1181         /*
1182          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1183          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1184          */
1185         if (i915->display.dpll.mgr) {
1186                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1187                         if (intel_crtc_needs_modeset(new_crtc_state))
1188                                 continue;
1189
1190                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1191                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1192                 }
1193         }
1194 }
1195
1196 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1197                                           struct intel_crtc *crtc)
1198 {
1199         const struct intel_crtc_state *crtc_state =
1200                 intel_atomic_get_new_crtc_state(state, crtc);
1201         const struct drm_connector_state *conn_state;
1202         struct drm_connector *conn;
1203         int i;
1204
1205         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1206                 struct intel_encoder *encoder =
1207                         to_intel_encoder(conn_state->best_encoder);
1208
1209                 if (conn_state->crtc != &crtc->base)
1210                         continue;
1211
1212                 if (encoder->pre_pll_enable)
1213                         encoder->pre_pll_enable(state, encoder,
1214                                                 crtc_state, conn_state);
1215         }
1216 }
1217
1218 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1219                                       struct intel_crtc *crtc)
1220 {
1221         const struct intel_crtc_state *crtc_state =
1222                 intel_atomic_get_new_crtc_state(state, crtc);
1223         const struct drm_connector_state *conn_state;
1224         struct drm_connector *conn;
1225         int i;
1226
1227         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1228                 struct intel_encoder *encoder =
1229                         to_intel_encoder(conn_state->best_encoder);
1230
1231                 if (conn_state->crtc != &crtc->base)
1232                         continue;
1233
1234                 if (encoder->pre_enable)
1235                         encoder->pre_enable(state, encoder,
1236                                             crtc_state, conn_state);
1237         }
1238 }
1239
1240 static void intel_encoders_enable(struct intel_atomic_state *state,
1241                                   struct intel_crtc *crtc)
1242 {
1243         const struct intel_crtc_state *crtc_state =
1244                 intel_atomic_get_new_crtc_state(state, crtc);
1245         const struct drm_connector_state *conn_state;
1246         struct drm_connector *conn;
1247         int i;
1248
1249         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1250                 struct intel_encoder *encoder =
1251                         to_intel_encoder(conn_state->best_encoder);
1252
1253                 if (conn_state->crtc != &crtc->base)
1254                         continue;
1255
1256                 if (encoder->enable)
1257                         encoder->enable(state, encoder,
1258                                         crtc_state, conn_state);
1259                 intel_opregion_notify_encoder(encoder, true);
1260         }
1261 }
1262
1263 static void intel_encoders_disable(struct intel_atomic_state *state,
1264                                    struct intel_crtc *crtc)
1265 {
1266         const struct intel_crtc_state *old_crtc_state =
1267                 intel_atomic_get_old_crtc_state(state, crtc);
1268         const struct drm_connector_state *old_conn_state;
1269         struct drm_connector *conn;
1270         int i;
1271
1272         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1273                 struct intel_encoder *encoder =
1274                         to_intel_encoder(old_conn_state->best_encoder);
1275
1276                 if (old_conn_state->crtc != &crtc->base)
1277                         continue;
1278
1279                 intel_opregion_notify_encoder(encoder, false);
1280                 if (encoder->disable)
1281                         encoder->disable(state, encoder,
1282                                          old_crtc_state, old_conn_state);
1283         }
1284 }
1285
1286 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1287                                         struct intel_crtc *crtc)
1288 {
1289         const struct intel_crtc_state *old_crtc_state =
1290                 intel_atomic_get_old_crtc_state(state, crtc);
1291         const struct drm_connector_state *old_conn_state;
1292         struct drm_connector *conn;
1293         int i;
1294
1295         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1296                 struct intel_encoder *encoder =
1297                         to_intel_encoder(old_conn_state->best_encoder);
1298
1299                 if (old_conn_state->crtc != &crtc->base)
1300                         continue;
1301
1302                 if (encoder->post_disable)
1303                         encoder->post_disable(state, encoder,
1304                                               old_crtc_state, old_conn_state);
1305         }
1306 }
1307
1308 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1309                                             struct intel_crtc *crtc)
1310 {
1311         const struct intel_crtc_state *old_crtc_state =
1312                 intel_atomic_get_old_crtc_state(state, crtc);
1313         const struct drm_connector_state *old_conn_state;
1314         struct drm_connector *conn;
1315         int i;
1316
1317         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1318                 struct intel_encoder *encoder =
1319                         to_intel_encoder(old_conn_state->best_encoder);
1320
1321                 if (old_conn_state->crtc != &crtc->base)
1322                         continue;
1323
1324                 if (encoder->post_pll_disable)
1325                         encoder->post_pll_disable(state, encoder,
1326                                                   old_crtc_state, old_conn_state);
1327         }
1328 }
1329
1330 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1331                                        struct intel_crtc *crtc)
1332 {
1333         const struct intel_crtc_state *crtc_state =
1334                 intel_atomic_get_new_crtc_state(state, crtc);
1335         const struct drm_connector_state *conn_state;
1336         struct drm_connector *conn;
1337         int i;
1338
1339         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1340                 struct intel_encoder *encoder =
1341                         to_intel_encoder(conn_state->best_encoder);
1342
1343                 if (conn_state->crtc != &crtc->base)
1344                         continue;
1345
1346                 if (encoder->update_pipe)
1347                         encoder->update_pipe(state, encoder,
1348                                              crtc_state, conn_state);
1349         }
1350 }
1351
1352 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1353 {
1354         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1355         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1356
1357         plane->disable_arm(plane, crtc_state);
1358 }
1359
1360 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1361 {
1362         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1363         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1364
1365         if (crtc_state->has_pch_encoder) {
1366                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1367                                                &crtc_state->fdi_m_n);
1368         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1369                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1370                                                &crtc_state->dp_m_n);
1371                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1372                                                &crtc_state->dp_m2_n2);
1373         }
1374
1375         intel_set_transcoder_timings(crtc_state);
1376
1377         ilk_set_pipeconf(crtc_state);
1378 }
1379
1380 static void ilk_crtc_enable(struct intel_atomic_state *state,
1381                             struct intel_crtc *crtc)
1382 {
1383         const struct intel_crtc_state *new_crtc_state =
1384                 intel_atomic_get_new_crtc_state(state, crtc);
1385         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1386         enum pipe pipe = crtc->pipe;
1387
1388         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1389                 return;
1390
1391         /*
1392          * Sometimes spurious CPU pipe underruns happen during FDI
1393          * training, at least with VGA+HDMI cloning. Suppress them.
1394          *
1395          * On ILK we get an occasional spurious CPU pipe underruns
1396          * between eDP port A enable and vdd enable. Also PCH port
1397          * enable seems to result in the occasional CPU pipe underrun.
1398          *
1399          * Spurious PCH underruns also occur during PCH enabling.
1400          */
1401         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1402         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1403
1404         ilk_configure_cpu_transcoder(new_crtc_state);
1405
1406         intel_set_pipe_src_size(new_crtc_state);
1407
1408         crtc->active = true;
1409
1410         intel_encoders_pre_enable(state, crtc);
1411
1412         if (new_crtc_state->has_pch_encoder) {
1413                 ilk_pch_pre_enable(state, crtc);
1414         } else {
1415                 assert_fdi_tx_disabled(dev_priv, pipe);
1416                 assert_fdi_rx_disabled(dev_priv, pipe);
1417         }
1418
1419         ilk_pfit_enable(new_crtc_state);
1420
1421         /*
1422          * On ILK+ LUT must be loaded before the pipe is running but with
1423          * clocks enabled
1424          */
1425         intel_color_load_luts(new_crtc_state);
1426         intel_color_commit_noarm(new_crtc_state);
1427         intel_color_commit_arm(new_crtc_state);
1428         /* update DSPCNTR to configure gamma for pipe bottom color */
1429         intel_disable_primary_plane(new_crtc_state);
1430
1431         intel_initial_watermarks(state, crtc);
1432         intel_enable_transcoder(new_crtc_state);
1433
1434         if (new_crtc_state->has_pch_encoder)
1435                 ilk_pch_enable(state, crtc);
1436
1437         intel_crtc_vblank_on(new_crtc_state);
1438
1439         intel_encoders_enable(state, crtc);
1440
1441         if (HAS_PCH_CPT(dev_priv))
1442                 intel_wait_for_pipe_scanline_moving(crtc);
1443
1444         /*
1445          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1446          * And a second vblank wait is needed at least on ILK with
1447          * some interlaced HDMI modes. Let's do the double wait always
1448          * in case there are more corner cases we don't know about.
1449          */
1450         if (new_crtc_state->has_pch_encoder) {
1451                 intel_crtc_wait_for_next_vblank(crtc);
1452                 intel_crtc_wait_for_next_vblank(crtc);
1453         }
1454         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1455         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1456 }
1457
1458 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1459                                             enum pipe pipe, bool apply)
1460 {
1461         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1462         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1463
1464         if (apply)
1465                 val |= mask;
1466         else
1467                 val &= ~mask;
1468
1469         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1470 }
1471
1472 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1473 {
1474         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1475         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1476
1477         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1478                        HSW_LINETIME(crtc_state->linetime) |
1479                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1480 }
1481
1482 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1483 {
1484         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1485         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1486         enum transcoder transcoder = crtc_state->cpu_transcoder;
1487         i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1488                          CHICKEN_TRANS(transcoder);
1489
1490         intel_de_rmw(dev_priv, reg,
1491                      HSW_FRAME_START_DELAY_MASK,
1492                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1493 }
1494
1495 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1496                                          const struct intel_crtc_state *crtc_state)
1497 {
1498         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1499
1500         /*
1501          * Enable sequence steps 1-7 on bigjoiner master
1502          */
1503         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1504                 intel_encoders_pre_pll_enable(state, master_crtc);
1505
1506         if (crtc_state->shared_dpll)
1507                 intel_enable_shared_dpll(crtc_state);
1508
1509         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1510                 intel_encoders_pre_enable(state, master_crtc);
1511 }
1512
1513 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1514 {
1515         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1517         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1518
1519         if (crtc_state->has_pch_encoder) {
1520                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1521                                                &crtc_state->fdi_m_n);
1522         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1523                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1524                                                &crtc_state->dp_m_n);
1525                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1526                                                &crtc_state->dp_m2_n2);
1527         }
1528
1529         intel_set_transcoder_timings(crtc_state);
1530         if (HAS_VRR(dev_priv))
1531                 intel_vrr_set_transcoder_timings(crtc_state);
1532
1533         if (cpu_transcoder != TRANSCODER_EDP)
1534                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1535                                crtc_state->pixel_multiplier - 1);
1536
1537         hsw_set_frame_start_delay(crtc_state);
1538
1539         hsw_set_transconf(crtc_state);
1540 }
1541
1542 static void hsw_crtc_enable(struct intel_atomic_state *state,
1543                             struct intel_crtc *crtc)
1544 {
1545         const struct intel_crtc_state *new_crtc_state =
1546                 intel_atomic_get_new_crtc_state(state, crtc);
1547         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1548         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1549         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1550         bool psl_clkgate_wa;
1551
1552         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1553                 return;
1554
1555         intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1556
1557         if (!new_crtc_state->bigjoiner_pipes) {
1558                 intel_encoders_pre_pll_enable(state, crtc);
1559
1560                 if (new_crtc_state->shared_dpll)
1561                         intel_enable_shared_dpll(new_crtc_state);
1562
1563                 intel_encoders_pre_enable(state, crtc);
1564         } else {
1565                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1566         }
1567
1568         intel_dsc_enable(new_crtc_state);
1569
1570         if (DISPLAY_VER(dev_priv) >= 13)
1571                 intel_uncompressed_joiner_enable(new_crtc_state);
1572
1573         intel_set_pipe_src_size(new_crtc_state);
1574         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1575                 bdw_set_pipe_misc(new_crtc_state);
1576
1577         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1578             !transcoder_is_dsi(cpu_transcoder))
1579                 hsw_configure_cpu_transcoder(new_crtc_state);
1580
1581         crtc->active = true;
1582
1583         /* Display WA #1180: WaDisableScalarClockGating: glk */
1584         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1585                 new_crtc_state->pch_pfit.enabled;
1586         if (psl_clkgate_wa)
1587                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1588
1589         if (DISPLAY_VER(dev_priv) >= 9)
1590                 skl_pfit_enable(new_crtc_state);
1591         else
1592                 ilk_pfit_enable(new_crtc_state);
1593
1594         /*
1595          * On ILK+ LUT must be loaded before the pipe is running but with
1596          * clocks enabled
1597          */
1598         intel_color_load_luts(new_crtc_state);
1599         intel_color_commit_noarm(new_crtc_state);
1600         intel_color_commit_arm(new_crtc_state);
1601         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1602         if (DISPLAY_VER(dev_priv) < 9)
1603                 intel_disable_primary_plane(new_crtc_state);
1604
1605         hsw_set_linetime_wm(new_crtc_state);
1606
1607         if (DISPLAY_VER(dev_priv) >= 11)
1608                 icl_set_pipe_chicken(new_crtc_state);
1609
1610         intel_initial_watermarks(state, crtc);
1611
1612         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1613                 intel_crtc_vblank_on(new_crtc_state);
1614
1615         intel_encoders_enable(state, crtc);
1616
1617         if (psl_clkgate_wa) {
1618                 intel_crtc_wait_for_next_vblank(crtc);
1619                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1620         }
1621
1622         /* If we change the relative order between pipe/planes enabling, we need
1623          * to change the workaround. */
1624         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1625         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1626                 struct intel_crtc *wa_crtc;
1627
1628                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1629
1630                 intel_crtc_wait_for_next_vblank(wa_crtc);
1631                 intel_crtc_wait_for_next_vblank(wa_crtc);
1632         }
1633 }
1634
1635 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1636 {
1637         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1638         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1639         enum pipe pipe = crtc->pipe;
1640
1641         /* To avoid upsetting the power well on haswell only disable the pfit if
1642          * it's in use. The hw state code will make sure we get this right. */
1643         if (!old_crtc_state->pch_pfit.enabled)
1644                 return;
1645
1646         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1647         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1648         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1649 }
1650
1651 static void ilk_crtc_disable(struct intel_atomic_state *state,
1652                              struct intel_crtc *crtc)
1653 {
1654         const struct intel_crtc_state *old_crtc_state =
1655                 intel_atomic_get_old_crtc_state(state, crtc);
1656         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1657         enum pipe pipe = crtc->pipe;
1658
1659         /*
1660          * Sometimes spurious CPU pipe underruns happen when the
1661          * pipe is already disabled, but FDI RX/TX is still enabled.
1662          * Happens at least with VGA+HDMI cloning. Suppress them.
1663          */
1664         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1665         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1666
1667         intel_encoders_disable(state, crtc);
1668
1669         intel_crtc_vblank_off(old_crtc_state);
1670
1671         intel_disable_transcoder(old_crtc_state);
1672
1673         ilk_pfit_disable(old_crtc_state);
1674
1675         if (old_crtc_state->has_pch_encoder)
1676                 ilk_pch_disable(state, crtc);
1677
1678         intel_encoders_post_disable(state, crtc);
1679
1680         if (old_crtc_state->has_pch_encoder)
1681                 ilk_pch_post_disable(state, crtc);
1682
1683         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1684         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1685
1686         intel_disable_shared_dpll(old_crtc_state);
1687 }
1688
1689 static void hsw_crtc_disable(struct intel_atomic_state *state,
1690                              struct intel_crtc *crtc)
1691 {
1692         const struct intel_crtc_state *old_crtc_state =
1693                 intel_atomic_get_old_crtc_state(state, crtc);
1694         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1695
1696         /*
1697          * FIXME collapse everything to one hook.
1698          * Need care with mst->ddi interactions.
1699          */
1700         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1701                 intel_encoders_disable(state, crtc);
1702                 intel_encoders_post_disable(state, crtc);
1703         }
1704
1705         intel_disable_shared_dpll(old_crtc_state);
1706
1707         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1708                 struct intel_crtc *slave_crtc;
1709
1710                 intel_encoders_post_pll_disable(state, crtc);
1711
1712                 intel_dmc_disable_pipe(i915, crtc->pipe);
1713
1714                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
1715                                                  intel_crtc_bigjoiner_slave_pipes(old_crtc_state))
1716                         intel_dmc_disable_pipe(i915, slave_crtc->pipe);
1717         }
1718 }
1719
1720 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1721 {
1722         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1723         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1724
1725         if (!crtc_state->gmch_pfit.control)
1726                 return;
1727
1728         /*
1729          * The panel fitter should only be adjusted whilst the pipe is disabled,
1730          * according to register description and PRM.
1731          */
1732         drm_WARN_ON(&dev_priv->drm,
1733                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1734         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1735
1736         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1737                        crtc_state->gmch_pfit.pgm_ratios);
1738         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1739
1740         /* Border color in case we don't scale up to the full screen. Black by
1741          * default, change to something else for debugging. */
1742         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1743 }
1744
1745 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1746 {
1747         if (phy == PHY_NONE)
1748                 return false;
1749         else if (IS_ALDERLAKE_S(dev_priv))
1750                 return phy <= PHY_E;
1751         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1752                 return phy <= PHY_D;
1753         else if (IS_JSL_EHL(dev_priv))
1754                 return phy <= PHY_C;
1755         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1756                 return phy <= PHY_B;
1757         else
1758                 /*
1759                  * DG2 outputs labelled as "combo PHY" in the bspec use
1760                  * SNPS PHYs with completely different programming,
1761                  * hence we always return false here.
1762                  */
1763                 return false;
1764 }
1765
1766 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1767 {
1768         if (IS_DG2(dev_priv))
1769                 /* DG2's "TC1" output uses a SNPS PHY */
1770                 return false;
1771         else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
1772                 return phy >= PHY_F && phy <= PHY_I;
1773         else if (IS_TIGERLAKE(dev_priv))
1774                 return phy >= PHY_D && phy <= PHY_I;
1775         else if (IS_ICELAKE(dev_priv))
1776                 return phy >= PHY_C && phy <= PHY_F;
1777         else
1778                 return false;
1779 }
1780
1781 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1782 {
1783         if (phy == PHY_NONE)
1784                 return false;
1785         else if (IS_DG2(dev_priv))
1786                 /*
1787                  * All four "combo" ports and the TC1 port (PHY E) use
1788                  * Synopsis PHYs.
1789                  */
1790                 return phy <= PHY_E;
1791
1792         return false;
1793 }
1794
1795 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1796 {
1797         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1798                 return PHY_D + port - PORT_D_XELPD;
1799         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1800                 return PHY_F + port - PORT_TC1;
1801         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1802                 return PHY_B + port - PORT_TC1;
1803         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1804                 return PHY_C + port - PORT_TC1;
1805         else if (IS_JSL_EHL(i915) && port == PORT_D)
1806                 return PHY_A;
1807
1808         return PHY_A + port - PORT_A;
1809 }
1810
1811 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1812 {
1813         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1814                 return TC_PORT_NONE;
1815
1816         if (DISPLAY_VER(dev_priv) >= 12)
1817                 return TC_PORT_1 + port - PORT_TC1;
1818         else
1819                 return TC_PORT_1 + port - PORT_C;
1820 }
1821
1822 enum intel_display_power_domain
1823 intel_aux_power_domain(struct intel_digital_port *dig_port)
1824 {
1825         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1826
1827         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1828                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1829
1830         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1831 }
1832
1833 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1834                                    struct intel_power_domain_mask *mask)
1835 {
1836         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1837         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1838         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1839         struct drm_encoder *encoder;
1840         enum pipe pipe = crtc->pipe;
1841
1842         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1843
1844         if (!crtc_state->hw.active)
1845                 return;
1846
1847         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1848         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1849         if (crtc_state->pch_pfit.enabled ||
1850             crtc_state->pch_pfit.force_thru)
1851                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1852
1853         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
1854                                   crtc_state->uapi.encoder_mask) {
1855                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1856
1857                 set_bit(intel_encoder->power_domain, mask->bits);
1858         }
1859
1860         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
1861                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1862
1863         if (crtc_state->shared_dpll)
1864                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1865
1866         if (crtc_state->dsc.compression_enable)
1867                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1868 }
1869
1870 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1871                                           struct intel_power_domain_mask *old_domains)
1872 {
1873         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1874         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1875         enum intel_display_power_domain domain;
1876         struct intel_power_domain_mask domains, new_domains;
1877
1878         get_crtc_power_domains(crtc_state, &domains);
1879
1880         bitmap_andnot(new_domains.bits,
1881                       domains.bits,
1882                       crtc->enabled_power_domains.mask.bits,
1883                       POWER_DOMAIN_NUM);
1884         bitmap_andnot(old_domains->bits,
1885                       crtc->enabled_power_domains.mask.bits,
1886                       domains.bits,
1887                       POWER_DOMAIN_NUM);
1888
1889         for_each_power_domain(domain, &new_domains)
1890                 intel_display_power_get_in_set(dev_priv,
1891                                                &crtc->enabled_power_domains,
1892                                                domain);
1893 }
1894
1895 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1896                                           struct intel_power_domain_mask *domains)
1897 {
1898         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
1899                                             &crtc->enabled_power_domains,
1900                                             domains);
1901 }
1902
1903 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1904 {
1905         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1906         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1907
1908         if (intel_crtc_has_dp_encoder(crtc_state)) {
1909                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1910                                                &crtc_state->dp_m_n);
1911                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1912                                                &crtc_state->dp_m2_n2);
1913         }
1914
1915         intel_set_transcoder_timings(crtc_state);
1916
1917         i9xx_set_pipeconf(crtc_state);
1918 }
1919
1920 static void valleyview_crtc_enable(struct intel_atomic_state *state,
1921                                    struct intel_crtc *crtc)
1922 {
1923         const struct intel_crtc_state *new_crtc_state =
1924                 intel_atomic_get_new_crtc_state(state, crtc);
1925         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1926         enum pipe pipe = crtc->pipe;
1927
1928         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1929                 return;
1930
1931         i9xx_configure_cpu_transcoder(new_crtc_state);
1932
1933         intel_set_pipe_src_size(new_crtc_state);
1934
1935         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
1936
1937         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1938                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
1939                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
1940         }
1941
1942         crtc->active = true;
1943
1944         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1945
1946         intel_encoders_pre_pll_enable(state, crtc);
1947
1948         if (IS_CHERRYVIEW(dev_priv))
1949                 chv_enable_pll(new_crtc_state);
1950         else
1951                 vlv_enable_pll(new_crtc_state);
1952
1953         intel_encoders_pre_enable(state, crtc);
1954
1955         i9xx_pfit_enable(new_crtc_state);
1956
1957         intel_color_load_luts(new_crtc_state);
1958         intel_color_commit_noarm(new_crtc_state);
1959         intel_color_commit_arm(new_crtc_state);
1960         /* update DSPCNTR to configure gamma for pipe bottom color */
1961         intel_disable_primary_plane(new_crtc_state);
1962
1963         intel_initial_watermarks(state, crtc);
1964         intel_enable_transcoder(new_crtc_state);
1965
1966         intel_crtc_vblank_on(new_crtc_state);
1967
1968         intel_encoders_enable(state, crtc);
1969 }
1970
1971 static void i9xx_crtc_enable(struct intel_atomic_state *state,
1972                              struct intel_crtc *crtc)
1973 {
1974         const struct intel_crtc_state *new_crtc_state =
1975                 intel_atomic_get_new_crtc_state(state, crtc);
1976         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1977         enum pipe pipe = crtc->pipe;
1978
1979         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1980                 return;
1981
1982         i9xx_configure_cpu_transcoder(new_crtc_state);
1983
1984         intel_set_pipe_src_size(new_crtc_state);
1985
1986         crtc->active = true;
1987
1988         if (DISPLAY_VER(dev_priv) != 2)
1989                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1990
1991         intel_encoders_pre_enable(state, crtc);
1992
1993         i9xx_enable_pll(new_crtc_state);
1994
1995         i9xx_pfit_enable(new_crtc_state);
1996
1997         intel_color_load_luts(new_crtc_state);
1998         intel_color_commit_noarm(new_crtc_state);
1999         intel_color_commit_arm(new_crtc_state);
2000         /* update DSPCNTR to configure gamma for pipe bottom color */
2001         intel_disable_primary_plane(new_crtc_state);
2002
2003         if (!intel_initial_watermarks(state, crtc))
2004                 intel_update_watermarks(dev_priv);
2005         intel_enable_transcoder(new_crtc_state);
2006
2007         intel_crtc_vblank_on(new_crtc_state);
2008
2009         intel_encoders_enable(state, crtc);
2010
2011         /* prevents spurious underruns */
2012         if (DISPLAY_VER(dev_priv) == 2)
2013                 intel_crtc_wait_for_next_vblank(crtc);
2014 }
2015
2016 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2017 {
2018         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2019         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2020
2021         if (!old_crtc_state->gmch_pfit.control)
2022                 return;
2023
2024         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2025
2026         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2027                     intel_de_read(dev_priv, PFIT_CONTROL));
2028         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2029 }
2030
2031 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2032                               struct intel_crtc *crtc)
2033 {
2034         struct intel_crtc_state *old_crtc_state =
2035                 intel_atomic_get_old_crtc_state(state, crtc);
2036         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2037         enum pipe pipe = crtc->pipe;
2038
2039         /*
2040          * On gen2 planes are double buffered but the pipe isn't, so we must
2041          * wait for planes to fully turn off before disabling the pipe.
2042          */
2043         if (DISPLAY_VER(dev_priv) == 2)
2044                 intel_crtc_wait_for_next_vblank(crtc);
2045
2046         intel_encoders_disable(state, crtc);
2047
2048         intel_crtc_vblank_off(old_crtc_state);
2049
2050         intel_disable_transcoder(old_crtc_state);
2051
2052         i9xx_pfit_disable(old_crtc_state);
2053
2054         intel_encoders_post_disable(state, crtc);
2055
2056         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2057                 if (IS_CHERRYVIEW(dev_priv))
2058                         chv_disable_pll(dev_priv, pipe);
2059                 else if (IS_VALLEYVIEW(dev_priv))
2060                         vlv_disable_pll(dev_priv, pipe);
2061                 else
2062                         i9xx_disable_pll(old_crtc_state);
2063         }
2064
2065         intel_encoders_post_pll_disable(state, crtc);
2066
2067         if (DISPLAY_VER(dev_priv) != 2)
2068                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2069
2070         if (!dev_priv->display.funcs.wm->initial_watermarks)
2071                 intel_update_watermarks(dev_priv);
2072
2073         /* clock the pipe down to 640x480@60 to potentially save power */
2074         if (IS_I830(dev_priv))
2075                 i830_enable_pipe(dev_priv, pipe);
2076 }
2077
2078 void intel_encoder_destroy(struct drm_encoder *encoder)
2079 {
2080         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2081
2082         drm_encoder_cleanup(encoder);
2083         kfree(intel_encoder);
2084 }
2085
2086 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2087 {
2088         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2089
2090         /* GDG double wide on either pipe, otherwise pipe A only */
2091         return DISPLAY_VER(dev_priv) < 4 &&
2092                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2093 }
2094
2095 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2096 {
2097         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2098         struct drm_rect src;
2099
2100         /*
2101          * We only use IF-ID interlacing. If we ever use
2102          * PF-ID we'll need to adjust the pixel_rate here.
2103          */
2104
2105         if (!crtc_state->pch_pfit.enabled)
2106                 return pixel_rate;
2107
2108         drm_rect_init(&src, 0, 0,
2109                       drm_rect_width(&crtc_state->pipe_src) << 16,
2110                       drm_rect_height(&crtc_state->pipe_src) << 16);
2111
2112         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2113                                    pixel_rate);
2114 }
2115
2116 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2117                                          const struct drm_display_mode *timings)
2118 {
2119         mode->hdisplay = timings->crtc_hdisplay;
2120         mode->htotal = timings->crtc_htotal;
2121         mode->hsync_start = timings->crtc_hsync_start;
2122         mode->hsync_end = timings->crtc_hsync_end;
2123
2124         mode->vdisplay = timings->crtc_vdisplay;
2125         mode->vtotal = timings->crtc_vtotal;
2126         mode->vsync_start = timings->crtc_vsync_start;
2127         mode->vsync_end = timings->crtc_vsync_end;
2128
2129         mode->flags = timings->flags;
2130         mode->type = DRM_MODE_TYPE_DRIVER;
2131
2132         mode->clock = timings->crtc_clock;
2133
2134         drm_mode_set_name(mode);
2135 }
2136
2137 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2138 {
2139         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2140
2141         if (HAS_GMCH(dev_priv))
2142                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2143                 crtc_state->pixel_rate =
2144                         crtc_state->hw.pipe_mode.crtc_clock;
2145         else
2146                 crtc_state->pixel_rate =
2147                         ilk_pipe_pixel_rate(crtc_state);
2148 }
2149
2150 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2151                                            struct drm_display_mode *mode)
2152 {
2153         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2154
2155         if (num_pipes < 2)
2156                 return;
2157
2158         mode->crtc_clock /= num_pipes;
2159         mode->crtc_hdisplay /= num_pipes;
2160         mode->crtc_hblank_start /= num_pipes;
2161         mode->crtc_hblank_end /= num_pipes;
2162         mode->crtc_hsync_start /= num_pipes;
2163         mode->crtc_hsync_end /= num_pipes;
2164         mode->crtc_htotal /= num_pipes;
2165 }
2166
2167 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2168                                           struct drm_display_mode *mode)
2169 {
2170         int overlap = crtc_state->splitter.pixel_overlap;
2171         int n = crtc_state->splitter.link_count;
2172
2173         if (!crtc_state->splitter.enable)
2174                 return;
2175
2176         /*
2177          * eDP MSO uses segment timings from EDID for transcoder
2178          * timings, but full mode for everything else.
2179          *
2180          * h_full = (h_segment - pixel_overlap) * link_count
2181          */
2182         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2183         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2184         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2185         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2186         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2187         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2188         mode->crtc_clock *= n;
2189 }
2190
2191 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2192 {
2193         struct drm_display_mode *mode = &crtc_state->hw.mode;
2194         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2195         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2196
2197         /*
2198          * Start with the adjusted_mode crtc timings, which
2199          * have been filled with the transcoder timings.
2200          */
2201         drm_mode_copy(pipe_mode, adjusted_mode);
2202
2203         /* Expand MSO per-segment transcoder timings to full */
2204         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2205
2206         /*
2207          * We want the full numbers in adjusted_mode normal timings,
2208          * adjusted_mode crtc timings are left with the raw transcoder
2209          * timings.
2210          */
2211         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2212
2213         /* Populate the "user" mode with full numbers */
2214         drm_mode_copy(mode, pipe_mode);
2215         intel_mode_from_crtc_timings(mode, mode);
2216         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2217                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2218         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2219
2220         /* Derive per-pipe timings in case bigjoiner is used */
2221         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2222         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2223
2224         intel_crtc_compute_pixel_rate(crtc_state);
2225 }
2226
2227 void intel_encoder_get_config(struct intel_encoder *encoder,
2228                               struct intel_crtc_state *crtc_state)
2229 {
2230         encoder->get_config(encoder, crtc_state);
2231
2232         intel_crtc_readout_derived_state(crtc_state);
2233 }
2234
2235 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2236 {
2237         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2238         int width, height;
2239
2240         if (num_pipes < 2)
2241                 return;
2242
2243         width = drm_rect_width(&crtc_state->pipe_src);
2244         height = drm_rect_height(&crtc_state->pipe_src);
2245
2246         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2247                       width / num_pipes, height);
2248 }
2249
2250 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2251 {
2252         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2253         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2254
2255         intel_bigjoiner_compute_pipe_src(crtc_state);
2256
2257         /*
2258          * Pipe horizontal size must be even in:
2259          * - DVO ganged mode
2260          * - LVDS dual channel mode
2261          * - Double wide pipe
2262          */
2263         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2264                 if (crtc_state->double_wide) {
2265                         drm_dbg_kms(&i915->drm,
2266                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2267                                     crtc->base.base.id, crtc->base.name);
2268                         return -EINVAL;
2269                 }
2270
2271                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2272                     intel_is_dual_link_lvds(i915)) {
2273                         drm_dbg_kms(&i915->drm,
2274                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2275                                     crtc->base.base.id, crtc->base.name);
2276                         return -EINVAL;
2277                 }
2278         }
2279
2280         return 0;
2281 }
2282
2283 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2284 {
2285         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2286         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2287         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2288         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2289         int clock_limit = i915->max_dotclk_freq;
2290
2291         /*
2292          * Start with the adjusted_mode crtc timings, which
2293          * have been filled with the transcoder timings.
2294          */
2295         drm_mode_copy(pipe_mode, adjusted_mode);
2296
2297         /* Expand MSO per-segment transcoder timings to full */
2298         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2299
2300         /* Derive per-pipe timings in case bigjoiner is used */
2301         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2302         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2303
2304         if (DISPLAY_VER(i915) < 4) {
2305                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2306
2307                 /*
2308                  * Enable double wide mode when the dot clock
2309                  * is > 90% of the (display) core speed.
2310                  */
2311                 if (intel_crtc_supports_double_wide(crtc) &&
2312                     pipe_mode->crtc_clock > clock_limit) {
2313                         clock_limit = i915->max_dotclk_freq;
2314                         crtc_state->double_wide = true;
2315                 }
2316         }
2317
2318         if (pipe_mode->crtc_clock > clock_limit) {
2319                 drm_dbg_kms(&i915->drm,
2320                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2321                             crtc->base.base.id, crtc->base.name,
2322                             pipe_mode->crtc_clock, clock_limit,
2323                             str_yes_no(crtc_state->double_wide));
2324                 return -EINVAL;
2325         }
2326
2327         return 0;
2328 }
2329
2330 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2331                                      struct intel_crtc *crtc)
2332 {
2333         struct intel_crtc_state *crtc_state =
2334                 intel_atomic_get_new_crtc_state(state, crtc);
2335         int ret;
2336
2337         ret = intel_dpll_crtc_compute_clock(state, crtc);
2338         if (ret)
2339                 return ret;
2340
2341         ret = intel_crtc_compute_pipe_src(crtc_state);
2342         if (ret)
2343                 return ret;
2344
2345         ret = intel_crtc_compute_pipe_mode(crtc_state);
2346         if (ret)
2347                 return ret;
2348
2349         intel_crtc_compute_pixel_rate(crtc_state);
2350
2351         if (crtc_state->has_pch_encoder)
2352                 return ilk_fdi_compute_config(crtc, crtc_state);
2353
2354         return 0;
2355 }
2356
2357 static void
2358 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2359 {
2360         while (*num > DATA_LINK_M_N_MASK ||
2361                *den > DATA_LINK_M_N_MASK) {
2362                 *num >>= 1;
2363                 *den >>= 1;
2364         }
2365 }
2366
2367 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2368                         u32 m, u32 n, u32 constant_n)
2369 {
2370         if (constant_n)
2371                 *ret_n = constant_n;
2372         else
2373                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2374
2375         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2376         intel_reduce_m_n_ratio(ret_m, ret_n);
2377 }
2378
2379 void
2380 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2381                        int pixel_clock, int link_clock,
2382                        struct intel_link_m_n *m_n,
2383                        bool fec_enable)
2384 {
2385         u32 data_clock = bits_per_pixel * pixel_clock;
2386
2387         if (fec_enable)
2388                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2389
2390         /*
2391          * Windows/BIOS uses fixed M/N values always. Follow suit.
2392          *
2393          * Also several DP dongles in particular seem to be fussy
2394          * about too large link M/N values. Presumably the 20bit
2395          * value used by Windows/BIOS is acceptable to everyone.
2396          */
2397         m_n->tu = 64;
2398         compute_m_n(&m_n->data_m, &m_n->data_n,
2399                     data_clock, link_clock * nlanes * 8,
2400                     0x8000000);
2401
2402         compute_m_n(&m_n->link_m, &m_n->link_n,
2403                     pixel_clock, link_clock,
2404                     0x80000);
2405 }
2406
2407 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2408 {
2409         /*
2410          * There may be no VBT; and if the BIOS enabled SSC we can
2411          * just keep using it to avoid unnecessary flicker.  Whereas if the
2412          * BIOS isn't using it, don't assume it will work even if the VBT
2413          * indicates as much.
2414          */
2415         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2416                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2417                                                        PCH_DREF_CONTROL) &
2418                         DREF_SSC1_ENABLE;
2419
2420                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2421                         drm_dbg_kms(&dev_priv->drm,
2422                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2423                                     str_enabled_disabled(bios_lvds_use_ssc),
2424                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2425                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2426                 }
2427         }
2428 }
2429
2430 void intel_zero_m_n(struct intel_link_m_n *m_n)
2431 {
2432         /* corresponds to 0 register value */
2433         memset(m_n, 0, sizeof(*m_n));
2434         m_n->tu = 1;
2435 }
2436
2437 void intel_set_m_n(struct drm_i915_private *i915,
2438                    const struct intel_link_m_n *m_n,
2439                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2440                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2441 {
2442         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2443         intel_de_write(i915, data_n_reg, m_n->data_n);
2444         intel_de_write(i915, link_m_reg, m_n->link_m);
2445         /*
2446          * On BDW+ writing LINK_N arms the double buffered update
2447          * of all the M/N registers, so it must be written last.
2448          */
2449         intel_de_write(i915, link_n_reg, m_n->link_n);
2450 }
2451
2452 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2453                                     enum transcoder transcoder)
2454 {
2455         if (IS_HASWELL(dev_priv))
2456                 return transcoder == TRANSCODER_EDP;
2457
2458         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2459 }
2460
2461 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2462                                     enum transcoder transcoder,
2463                                     const struct intel_link_m_n *m_n)
2464 {
2465         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2466         enum pipe pipe = crtc->pipe;
2467
2468         if (DISPLAY_VER(dev_priv) >= 5)
2469                 intel_set_m_n(dev_priv, m_n,
2470                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2471                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2472         else
2473                 intel_set_m_n(dev_priv, m_n,
2474                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2475                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2476 }
2477
2478 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2479                                     enum transcoder transcoder,
2480                                     const struct intel_link_m_n *m_n)
2481 {
2482         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2483
2484         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2485                 return;
2486
2487         intel_set_m_n(dev_priv, m_n,
2488                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2489                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2490 }
2491
2492 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2493 {
2494         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2496         enum pipe pipe = crtc->pipe;
2497         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2498         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2499         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2500         int vsyncshift = 0;
2501
2502         /* We need to be careful not to changed the adjusted mode, for otherwise
2503          * the hw state checker will get angry at the mismatch. */
2504         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2505         crtc_vtotal = adjusted_mode->crtc_vtotal;
2506         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2507         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2508
2509         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2510                 /* the chip adds 2 halflines automatically */
2511                 crtc_vtotal -= 1;
2512                 crtc_vblank_end -= 1;
2513
2514                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2515                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2516                 else
2517                         vsyncshift = adjusted_mode->crtc_hsync_start -
2518                                 adjusted_mode->crtc_htotal / 2;
2519                 if (vsyncshift < 0)
2520                         vsyncshift += adjusted_mode->crtc_htotal;
2521         }
2522
2523         /*
2524          * VBLANK_START no longer works on ADL+, instead we must use
2525          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2526          */
2527         if (DISPLAY_VER(dev_priv) >= 13) {
2528                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2529                                crtc_vblank_start - crtc_vdisplay);
2530
2531                 /*
2532                  * VBLANK_START not used by hw, just clear it
2533                  * to make it stand out in register dumps.
2534                  */
2535                 crtc_vblank_start = 1;
2536         }
2537
2538         if (DISPLAY_VER(dev_priv) > 3)
2539                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2540                                vsyncshift);
2541
2542         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2543                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2544                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2545         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2546                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2547                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2548         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2549                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2550                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2551
2552         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2553                        VACTIVE(crtc_vdisplay - 1) |
2554                        VTOTAL(crtc_vtotal - 1));
2555         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2556                        VBLANK_START(crtc_vblank_start - 1) |
2557                        VBLANK_END(crtc_vblank_end - 1));
2558         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2559                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2560                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2561
2562         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2563          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2564          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2565          * bits. */
2566         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2567             (pipe == PIPE_B || pipe == PIPE_C))
2568                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2569                                VACTIVE(crtc_vdisplay - 1) |
2570                                VTOTAL(crtc_vtotal - 1));
2571 }
2572
2573 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2574 {
2575         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2576         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2577         int width = drm_rect_width(&crtc_state->pipe_src);
2578         int height = drm_rect_height(&crtc_state->pipe_src);
2579         enum pipe pipe = crtc->pipe;
2580
2581         /* pipesrc controls the size that is scaled from, which should
2582          * always be the user's requested size.
2583          */
2584         intel_de_write(dev_priv, PIPESRC(pipe),
2585                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2586 }
2587
2588 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2589 {
2590         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2591         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2592
2593         if (DISPLAY_VER(dev_priv) == 2)
2594                 return false;
2595
2596         if (DISPLAY_VER(dev_priv) >= 9 ||
2597             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2598                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2599         else
2600                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2601 }
2602
2603 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2604                                          struct intel_crtc_state *pipe_config)
2605 {
2606         struct drm_device *dev = crtc->base.dev;
2607         struct drm_i915_private *dev_priv = to_i915(dev);
2608         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2609         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2610         u32 tmp;
2611
2612         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2613         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2614         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2615
2616         if (!transcoder_is_dsi(cpu_transcoder)) {
2617                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2618                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2619                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2620         }
2621
2622         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2623         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2624         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2625
2626         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2627         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2628         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2629
2630         /* FIXME TGL+ DSI transcoders have this! */
2631         if (!transcoder_is_dsi(cpu_transcoder)) {
2632                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2633                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2634                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2635         }
2636         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2637         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2638         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2639
2640         if (intel_pipe_is_interlaced(pipe_config)) {
2641                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2642                 adjusted_mode->crtc_vtotal += 1;
2643                 adjusted_mode->crtc_vblank_end += 1;
2644         }
2645
2646         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2647                 adjusted_mode->crtc_vblank_start =
2648                         adjusted_mode->crtc_vdisplay +
2649                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2650 }
2651
2652 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2653 {
2654         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2655         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2656         enum pipe master_pipe, pipe = crtc->pipe;
2657         int width;
2658
2659         if (num_pipes < 2)
2660                 return;
2661
2662         master_pipe = bigjoiner_master_pipe(crtc_state);
2663         width = drm_rect_width(&crtc_state->pipe_src);
2664
2665         drm_rect_translate_to(&crtc_state->pipe_src,
2666                               (pipe - master_pipe) * width, 0);
2667 }
2668
2669 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2670                                     struct intel_crtc_state *pipe_config)
2671 {
2672         struct drm_device *dev = crtc->base.dev;
2673         struct drm_i915_private *dev_priv = to_i915(dev);
2674         u32 tmp;
2675
2676         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2677
2678         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2679                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2680                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2681
2682         intel_bigjoiner_adjust_pipe_src(pipe_config);
2683 }
2684
2685 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2686 {
2687         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2688         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2689         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2690         u32 val = 0;
2691
2692         /*
2693          * - We keep both pipes enabled on 830
2694          * - During modeset the pipe is still disabled and must remain so
2695          * - During fastset the pipe is already enabled and must remain so
2696          */
2697         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2698                 val |= TRANSCONF_ENABLE;
2699
2700         if (crtc_state->double_wide)
2701                 val |= TRANSCONF_DOUBLE_WIDE;
2702
2703         /* only g4x and later have fancy bpc/dither controls */
2704         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2705             IS_CHERRYVIEW(dev_priv)) {
2706                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2707                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2708                         val |= TRANSCONF_DITHER_EN |
2709                                 TRANSCONF_DITHER_TYPE_SP;
2710
2711                 switch (crtc_state->pipe_bpp) {
2712                 default:
2713                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2714                         MISSING_CASE(crtc_state->pipe_bpp);
2715                         fallthrough;
2716                 case 18:
2717                         val |= TRANSCONF_BPC_6;
2718                         break;
2719                 case 24:
2720                         val |= TRANSCONF_BPC_8;
2721                         break;
2722                 case 30:
2723                         val |= TRANSCONF_BPC_10;
2724                         break;
2725                 }
2726         }
2727
2728         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2729                 if (DISPLAY_VER(dev_priv) < 4 ||
2730                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2731                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2732                 else
2733                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2734         } else {
2735                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2736         }
2737
2738         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2739              crtc_state->limited_color_range)
2740                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2741
2742         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2743
2744         if (crtc_state->wgc_enable)
2745                 val |= TRANSCONF_WGC_ENABLE;
2746
2747         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2748
2749         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2750         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2751 }
2752
2753 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2754 {
2755         if (IS_I830(dev_priv))
2756                 return false;
2757
2758         return DISPLAY_VER(dev_priv) >= 4 ||
2759                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2760 }
2761
2762 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2763 {
2764         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2765         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2766         enum pipe pipe;
2767         u32 tmp;
2768
2769         if (!i9xx_has_pfit(dev_priv))
2770                 return;
2771
2772         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2773         if (!(tmp & PFIT_ENABLE))
2774                 return;
2775
2776         /* Check whether the pfit is attached to our pipe. */
2777         if (DISPLAY_VER(dev_priv) >= 4)
2778                 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
2779         else
2780                 pipe = PIPE_B;
2781
2782         if (pipe != crtc->pipe)
2783                 return;
2784
2785         crtc_state->gmch_pfit.control = tmp;
2786         crtc_state->gmch_pfit.pgm_ratios =
2787                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2788 }
2789
2790 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
2791                                struct intel_crtc_state *pipe_config)
2792 {
2793         struct drm_device *dev = crtc->base.dev;
2794         struct drm_i915_private *dev_priv = to_i915(dev);
2795         enum pipe pipe = crtc->pipe;
2796         struct dpll clock;
2797         u32 mdiv;
2798         int refclk = 100000;
2799
2800         /* In case of DSI, DPLL will not be used */
2801         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2802                 return;
2803
2804         vlv_dpio_get(dev_priv);
2805         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2806         vlv_dpio_put(dev_priv);
2807
2808         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2809         clock.m2 = mdiv & DPIO_M2DIV_MASK;
2810         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2811         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2812         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
2813
2814         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
2815 }
2816
2817 static void chv_crtc_clock_get(struct intel_crtc *crtc,
2818                                struct intel_crtc_state *pipe_config)
2819 {
2820         struct drm_device *dev = crtc->base.dev;
2821         struct drm_i915_private *dev_priv = to_i915(dev);
2822         enum pipe pipe = crtc->pipe;
2823         enum dpio_channel port = vlv_pipe_to_channel(pipe);
2824         struct dpll clock;
2825         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
2826         int refclk = 100000;
2827
2828         /* In case of DSI, DPLL will not be used */
2829         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2830                 return;
2831
2832         vlv_dpio_get(dev_priv);
2833         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
2834         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
2835         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
2836         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
2837         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
2838         vlv_dpio_put(dev_priv);
2839
2840         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
2841         clock.m2 = (pll_dw0 & 0xff) << 22;
2842         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
2843                 clock.m2 |= pll_dw2 & 0x3fffff;
2844         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
2845         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
2846         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
2847
2848         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
2849 }
2850
2851 static enum intel_output_format
2852 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2853 {
2854         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2855         u32 tmp;
2856
2857         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2858
2859         if (tmp & PIPE_MISC_YUV420_ENABLE) {
2860                 /* We support 4:2:0 in full blend mode only */
2861                 drm_WARN_ON(&dev_priv->drm,
2862                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
2863
2864                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2865         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
2866                 return INTEL_OUTPUT_FORMAT_YCBCR444;
2867         } else {
2868                 return INTEL_OUTPUT_FORMAT_RGB;
2869         }
2870 }
2871
2872 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
2873 {
2874         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2875         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2876         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2877         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
2878         u32 tmp;
2879
2880         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
2881
2882         if (tmp & DISP_PIPE_GAMMA_ENABLE)
2883                 crtc_state->gamma_enable = true;
2884
2885         if (!HAS_GMCH(dev_priv) &&
2886             tmp & DISP_PIPE_CSC_ENABLE)
2887                 crtc_state->csc_enable = true;
2888 }
2889
2890 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
2891                                  struct intel_crtc_state *pipe_config)
2892 {
2893         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2894         enum intel_display_power_domain power_domain;
2895         intel_wakeref_t wakeref;
2896         u32 tmp;
2897         bool ret;
2898
2899         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
2900         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
2901         if (!wakeref)
2902                 return false;
2903
2904         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2905         pipe_config->sink_format = pipe_config->output_format;
2906         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
2907         pipe_config->shared_dpll = NULL;
2908
2909         ret = false;
2910
2911         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
2912         if (!(tmp & TRANSCONF_ENABLE))
2913                 goto out;
2914
2915         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2916             IS_CHERRYVIEW(dev_priv)) {
2917                 switch (tmp & TRANSCONF_BPC_MASK) {
2918                 case TRANSCONF_BPC_6:
2919                         pipe_config->pipe_bpp = 18;
2920                         break;
2921                 case TRANSCONF_BPC_8:
2922                         pipe_config->pipe_bpp = 24;
2923                         break;
2924                 case TRANSCONF_BPC_10:
2925                         pipe_config->pipe_bpp = 30;
2926                         break;
2927                 default:
2928                         MISSING_CASE(tmp);
2929                         break;
2930                 }
2931         }
2932
2933         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2934             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
2935                 pipe_config->limited_color_range = true;
2936
2937         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
2938
2939         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
2940
2941         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2942             (tmp & TRANSCONF_WGC_ENABLE))
2943                 pipe_config->wgc_enable = true;
2944
2945         if (IS_CHERRYVIEW(dev_priv))
2946                 pipe_config->cgm_mode = intel_de_read(dev_priv,
2947                                                       CGM_PIPE_MODE(crtc->pipe));
2948
2949         i9xx_get_pipe_color_config(pipe_config);
2950         intel_color_get_config(pipe_config);
2951
2952         if (DISPLAY_VER(dev_priv) < 4)
2953                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
2954
2955         intel_get_transcoder_timings(crtc, pipe_config);
2956         intel_get_pipe_src_size(crtc, pipe_config);
2957
2958         i9xx_get_pfit_config(pipe_config);
2959
2960         if (DISPLAY_VER(dev_priv) >= 4) {
2961                 /* No way to read it out on pipes B and C */
2962                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
2963                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
2964                 else
2965                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
2966                 pipe_config->pixel_multiplier =
2967                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
2968                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
2969                 pipe_config->dpll_hw_state.dpll_md = tmp;
2970         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
2971                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
2972                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
2973                 pipe_config->pixel_multiplier =
2974                         ((tmp & SDVO_MULTIPLIER_MASK)
2975                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
2976         } else {
2977                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
2978                  * port and will be fixed up in the encoder->get_config
2979                  * function. */
2980                 pipe_config->pixel_multiplier = 1;
2981         }
2982         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
2983                                                         DPLL(crtc->pipe));
2984         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
2985                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
2986                                                                FP0(crtc->pipe));
2987                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
2988                                                                FP1(crtc->pipe));
2989         } else {
2990                 /* Mask out read-only status bits. */
2991                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
2992                                                      DPLL_PORTC_READY_MASK |
2993                                                      DPLL_PORTB_READY_MASK);
2994         }
2995
2996         if (IS_CHERRYVIEW(dev_priv))
2997                 chv_crtc_clock_get(crtc, pipe_config);
2998         else if (IS_VALLEYVIEW(dev_priv))
2999                 vlv_crtc_clock_get(crtc, pipe_config);
3000         else
3001                 i9xx_crtc_clock_get(crtc, pipe_config);
3002
3003         /*
3004          * Normally the dotclock is filled in by the encoder .get_config()
3005          * but in case the pipe is enabled w/o any ports we need a sane
3006          * default.
3007          */
3008         pipe_config->hw.adjusted_mode.crtc_clock =
3009                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3010
3011         ret = true;
3012
3013 out:
3014         intel_display_power_put(dev_priv, power_domain, wakeref);
3015
3016         return ret;
3017 }
3018
3019 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3020 {
3021         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3022         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3023         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3024         u32 val = 0;
3025
3026         /*
3027          * - During modeset the pipe is still disabled and must remain so
3028          * - During fastset the pipe is already enabled and must remain so
3029          */
3030         if (!intel_crtc_needs_modeset(crtc_state))
3031                 val |= TRANSCONF_ENABLE;
3032
3033         switch (crtc_state->pipe_bpp) {
3034         default:
3035                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3036                 MISSING_CASE(crtc_state->pipe_bpp);
3037                 fallthrough;
3038         case 18:
3039                 val |= TRANSCONF_BPC_6;
3040                 break;
3041         case 24:
3042                 val |= TRANSCONF_BPC_8;
3043                 break;
3044         case 30:
3045                 val |= TRANSCONF_BPC_10;
3046                 break;
3047         case 36:
3048                 val |= TRANSCONF_BPC_12;
3049                 break;
3050         }
3051
3052         if (crtc_state->dither)
3053                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3054
3055         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3056                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3057         else
3058                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3059
3060         /*
3061          * This would end up with an odd purple hue over
3062          * the entire display. Make sure we don't do it.
3063          */
3064         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3065                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3066
3067         if (crtc_state->limited_color_range &&
3068             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3069                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3070
3071         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3072                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3073
3074         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3075
3076         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3077         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3078
3079         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3080         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3081 }
3082
3083 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3084 {
3085         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3086         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3087         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3088         u32 val = 0;
3089
3090         /*
3091          * - During modeset the pipe is still disabled and must remain so
3092          * - During fastset the pipe is already enabled and must remain so
3093          */
3094         if (!intel_crtc_needs_modeset(crtc_state))
3095                 val |= TRANSCONF_ENABLE;
3096
3097         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3098                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3099
3100         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3101                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3102         else
3103                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3104
3105         if (IS_HASWELL(dev_priv) &&
3106             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3107                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3108
3109         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3110         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3111 }
3112
3113 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3114 {
3115         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3116         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3117         u32 val = 0;
3118
3119         switch (crtc_state->pipe_bpp) {
3120         case 18:
3121                 val |= PIPE_MISC_BPC_6;
3122                 break;
3123         case 24:
3124                 val |= PIPE_MISC_BPC_8;
3125                 break;
3126         case 30:
3127                 val |= PIPE_MISC_BPC_10;
3128                 break;
3129         case 36:
3130                 /* Port output 12BPC defined for ADLP+ */
3131                 if (DISPLAY_VER(dev_priv) > 12)
3132                         val |= PIPE_MISC_BPC_12_ADLP;
3133                 break;
3134         default:
3135                 MISSING_CASE(crtc_state->pipe_bpp);
3136                 break;
3137         }
3138
3139         if (crtc_state->dither)
3140                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3141
3142         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3143             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3144                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3145
3146         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3147                 val |= PIPE_MISC_YUV420_ENABLE |
3148                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3149
3150         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3151                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3152
3153         if (DISPLAY_VER(dev_priv) >= 12)
3154                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3155
3156         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3157 }
3158
3159 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3160 {
3161         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3162         u32 tmp;
3163
3164         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3165
3166         switch (tmp & PIPE_MISC_BPC_MASK) {
3167         case PIPE_MISC_BPC_6:
3168                 return 18;
3169         case PIPE_MISC_BPC_8:
3170                 return 24;
3171         case PIPE_MISC_BPC_10:
3172                 return 30;
3173         /*
3174          * PORT OUTPUT 12 BPC defined for ADLP+.
3175          *
3176          * TODO:
3177          * For previous platforms with DSI interface, bits 5:7
3178          * are used for storing pipe_bpp irrespective of dithering.
3179          * Since the value of 12 BPC is not defined for these bits
3180          * on older platforms, need to find a workaround for 12 BPC
3181          * MIPI DSI HW readout.
3182          */
3183         case PIPE_MISC_BPC_12_ADLP:
3184                 if (DISPLAY_VER(dev_priv) > 12)
3185                         return 36;
3186                 fallthrough;
3187         default:
3188                 MISSING_CASE(tmp);
3189                 return 0;
3190         }
3191 }
3192
3193 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3194 {
3195         /*
3196          * Account for spread spectrum to avoid
3197          * oversubscribing the link. Max center spread
3198          * is 2.5%; use 5% for safety's sake.
3199          */
3200         u32 bps = target_clock * bpp * 21 / 20;
3201         return DIV_ROUND_UP(bps, link_bw * 8);
3202 }
3203
3204 void intel_get_m_n(struct drm_i915_private *i915,
3205                    struct intel_link_m_n *m_n,
3206                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3207                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3208 {
3209         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3210         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3211         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3212         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3213         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3214 }
3215
3216 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3217                                     enum transcoder transcoder,
3218                                     struct intel_link_m_n *m_n)
3219 {
3220         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3221         enum pipe pipe = crtc->pipe;
3222
3223         if (DISPLAY_VER(dev_priv) >= 5)
3224                 intel_get_m_n(dev_priv, m_n,
3225                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3226                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3227         else
3228                 intel_get_m_n(dev_priv, m_n,
3229                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3230                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3231 }
3232
3233 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3234                                     enum transcoder transcoder,
3235                                     struct intel_link_m_n *m_n)
3236 {
3237         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3238
3239         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3240                 return;
3241
3242         intel_get_m_n(dev_priv, m_n,
3243                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3244                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3245 }
3246
3247 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3248 {
3249         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3250         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3251         u32 ctl, pos, size;
3252         enum pipe pipe;
3253
3254         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3255         if ((ctl & PF_ENABLE) == 0)
3256                 return;
3257
3258         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3259                 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3260         else
3261                 pipe = crtc->pipe;
3262
3263         crtc_state->pch_pfit.enabled = true;
3264
3265         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3266         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3267
3268         drm_rect_init(&crtc_state->pch_pfit.dst,
3269                       REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3270                       REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3271                       REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3272                       REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3273
3274         /*
3275          * We currently do not free assignements of panel fitters on
3276          * ivb/hsw (since we don't use the higher upscaling modes which
3277          * differentiates them) so just WARN about this case for now.
3278          */
3279         drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3280 }
3281
3282 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3283                                 struct intel_crtc_state *pipe_config)
3284 {
3285         struct drm_device *dev = crtc->base.dev;
3286         struct drm_i915_private *dev_priv = to_i915(dev);
3287         enum intel_display_power_domain power_domain;
3288         intel_wakeref_t wakeref;
3289         u32 tmp;
3290         bool ret;
3291
3292         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3293         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3294         if (!wakeref)
3295                 return false;
3296
3297         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3298         pipe_config->shared_dpll = NULL;
3299
3300         ret = false;
3301         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3302         if (!(tmp & TRANSCONF_ENABLE))
3303                 goto out;
3304
3305         switch (tmp & TRANSCONF_BPC_MASK) {
3306         case TRANSCONF_BPC_6:
3307                 pipe_config->pipe_bpp = 18;
3308                 break;
3309         case TRANSCONF_BPC_8:
3310                 pipe_config->pipe_bpp = 24;
3311                 break;
3312         case TRANSCONF_BPC_10:
3313                 pipe_config->pipe_bpp = 30;
3314                 break;
3315         case TRANSCONF_BPC_12:
3316                 pipe_config->pipe_bpp = 36;
3317                 break;
3318         default:
3319                 break;
3320         }
3321
3322         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3323                 pipe_config->limited_color_range = true;
3324
3325         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3326         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3327         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3328                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3329                 break;
3330         default:
3331                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3332                 break;
3333         }
3334
3335         pipe_config->sink_format = pipe_config->output_format;
3336
3337         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3338
3339         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3340
3341         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3342
3343         pipe_config->csc_mode = intel_de_read(dev_priv,
3344                                               PIPE_CSC_MODE(crtc->pipe));
3345
3346         i9xx_get_pipe_color_config(pipe_config);
3347         intel_color_get_config(pipe_config);
3348
3349         pipe_config->pixel_multiplier = 1;
3350
3351         ilk_pch_get_config(pipe_config);
3352
3353         intel_get_transcoder_timings(crtc, pipe_config);
3354         intel_get_pipe_src_size(crtc, pipe_config);
3355
3356         ilk_get_pfit_config(pipe_config);
3357
3358         ret = true;
3359
3360 out:
3361         intel_display_power_put(dev_priv, power_domain, wakeref);
3362
3363         return ret;
3364 }
3365
3366 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3367 {
3368         u8 pipes;
3369
3370         if (DISPLAY_VER(i915) >= 12)
3371                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3372         else if (DISPLAY_VER(i915) >= 11)
3373                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3374         else
3375                 pipes = 0;
3376
3377         return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3378 }
3379
3380 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3381                                            enum transcoder cpu_transcoder)
3382 {
3383         enum intel_display_power_domain power_domain;
3384         intel_wakeref_t wakeref;
3385         u32 tmp = 0;
3386
3387         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3388
3389         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3390                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3391
3392         return tmp & TRANS_DDI_FUNC_ENABLE;
3393 }
3394
3395 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3396                                     u8 *master_pipes, u8 *slave_pipes)
3397 {
3398         struct intel_crtc *crtc;
3399
3400         *master_pipes = 0;
3401         *slave_pipes = 0;
3402
3403         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3404                                          bigjoiner_pipes(dev_priv)) {
3405                 enum intel_display_power_domain power_domain;
3406                 enum pipe pipe = crtc->pipe;
3407                 intel_wakeref_t wakeref;
3408
3409                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3410                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3411                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3412
3413                         if (!(tmp & BIG_JOINER_ENABLE))
3414                                 continue;
3415
3416                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3417                                 *master_pipes |= BIT(pipe);
3418                         else
3419                                 *slave_pipes |= BIT(pipe);
3420                 }
3421
3422                 if (DISPLAY_VER(dev_priv) < 13)
3423                         continue;
3424
3425                 power_domain = POWER_DOMAIN_PIPE(pipe);
3426                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3427                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3428
3429                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3430                                 *master_pipes |= BIT(pipe);
3431                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3432                                 *slave_pipes |= BIT(pipe);
3433                 }
3434         }
3435
3436         /* Bigjoiner pipes should always be consecutive master and slave */
3437         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3438                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3439                  *master_pipes, *slave_pipes);
3440 }
3441
3442 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3443 {
3444         if ((slave_pipes & BIT(pipe)) == 0)
3445                 return pipe;
3446
3447         /* ignore everything above our pipe */
3448         master_pipes &= ~GENMASK(7, pipe);
3449
3450         /* highest remaining bit should be our master pipe */
3451         return fls(master_pipes) - 1;
3452 }
3453
3454 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3455 {
3456         enum pipe master_pipe, next_master_pipe;
3457
3458         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3459
3460         if ((master_pipes & BIT(master_pipe)) == 0)
3461                 return 0;
3462
3463         /* ignore our master pipe and everything below it */
3464         master_pipes &= ~GENMASK(master_pipe, 0);
3465         /* make sure a high bit is set for the ffs() */
3466         master_pipes |= BIT(7);
3467         /* lowest remaining bit should be the next master pipe */
3468         next_master_pipe = ffs(master_pipes) - 1;
3469
3470         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3471 }
3472
3473 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3474 {
3475         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3476
3477         if (DISPLAY_VER(i915) >= 11)
3478                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3479
3480         return panel_transcoder_mask;
3481 }
3482
3483 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3484 {
3485         struct drm_device *dev = crtc->base.dev;
3486         struct drm_i915_private *dev_priv = to_i915(dev);
3487         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3488         enum transcoder cpu_transcoder;
3489         u8 master_pipes, slave_pipes;
3490         u8 enabled_transcoders = 0;
3491
3492         /*
3493          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3494          * consistency and less surprising code; it's in always on power).
3495          */
3496         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3497                                        panel_transcoder_mask) {
3498                 enum intel_display_power_domain power_domain;
3499                 intel_wakeref_t wakeref;
3500                 enum pipe trans_pipe;
3501                 u32 tmp = 0;
3502
3503                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3504                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3505                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3506
3507                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3508                         continue;
3509
3510                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3511                 default:
3512                         drm_WARN(dev, 1,
3513                                  "unknown pipe linked to transcoder %s\n",
3514                                  transcoder_name(cpu_transcoder));
3515                         fallthrough;
3516                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3517                 case TRANS_DDI_EDP_INPUT_A_ON:
3518                         trans_pipe = PIPE_A;
3519                         break;
3520                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3521                         trans_pipe = PIPE_B;
3522                         break;
3523                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3524                         trans_pipe = PIPE_C;
3525                         break;
3526                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3527                         trans_pipe = PIPE_D;
3528                         break;
3529                 }
3530
3531                 if (trans_pipe == crtc->pipe)
3532                         enabled_transcoders |= BIT(cpu_transcoder);
3533         }
3534
3535         /* single pipe or bigjoiner master */
3536         cpu_transcoder = (enum transcoder) crtc->pipe;
3537         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3538                 enabled_transcoders |= BIT(cpu_transcoder);
3539
3540         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3541         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3542         if (slave_pipes & BIT(crtc->pipe)) {
3543                 cpu_transcoder = (enum transcoder)
3544                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3545                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3546                         enabled_transcoders |= BIT(cpu_transcoder);
3547         }
3548
3549         return enabled_transcoders;
3550 }
3551
3552 static bool has_edp_transcoders(u8 enabled_transcoders)
3553 {
3554         return enabled_transcoders & BIT(TRANSCODER_EDP);
3555 }
3556
3557 static bool has_dsi_transcoders(u8 enabled_transcoders)
3558 {
3559         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3560                                       BIT(TRANSCODER_DSI_1));
3561 }
3562
3563 static bool has_pipe_transcoders(u8 enabled_transcoders)
3564 {
3565         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3566                                        BIT(TRANSCODER_DSI_0) |
3567                                        BIT(TRANSCODER_DSI_1));
3568 }
3569
3570 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3571                                        u8 enabled_transcoders)
3572 {
3573         /* Only one type of transcoder please */
3574         drm_WARN_ON(&i915->drm,
3575                     has_edp_transcoders(enabled_transcoders) +
3576                     has_dsi_transcoders(enabled_transcoders) +
3577                     has_pipe_transcoders(enabled_transcoders) > 1);
3578
3579         /* Only DSI transcoders can be ganged */
3580         drm_WARN_ON(&i915->drm,
3581                     !has_dsi_transcoders(enabled_transcoders) &&
3582                     !is_power_of_2(enabled_transcoders));
3583 }
3584
3585 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3586                                      struct intel_crtc_state *pipe_config,
3587                                      struct intel_display_power_domain_set *power_domain_set)
3588 {
3589         struct drm_device *dev = crtc->base.dev;
3590         struct drm_i915_private *dev_priv = to_i915(dev);
3591         unsigned long enabled_transcoders;
3592         u32 tmp;
3593
3594         enabled_transcoders = hsw_enabled_transcoders(crtc);
3595         if (!enabled_transcoders)
3596                 return false;
3597
3598         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3599
3600         /*
3601          * With the exception of DSI we should only ever have
3602          * a single enabled transcoder. With DSI let's just
3603          * pick the first one.
3604          */
3605         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3606
3607         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3608                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3609                 return false;
3610
3611         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3612                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3613
3614                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3615                         pipe_config->pch_pfit.force_thru = true;
3616         }
3617
3618         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3619
3620         return tmp & TRANSCONF_ENABLE;
3621 }
3622
3623 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3624                                          struct intel_crtc_state *pipe_config,
3625                                          struct intel_display_power_domain_set *power_domain_set)
3626 {
3627         struct drm_device *dev = crtc->base.dev;
3628         struct drm_i915_private *dev_priv = to_i915(dev);
3629         enum transcoder cpu_transcoder;
3630         enum port port;
3631         u32 tmp;
3632
3633         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3634                 if (port == PORT_A)
3635                         cpu_transcoder = TRANSCODER_DSI_A;
3636                 else
3637                         cpu_transcoder = TRANSCODER_DSI_C;
3638
3639                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3640                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3641                         continue;
3642
3643                 /*
3644                  * The PLL needs to be enabled with a valid divider
3645                  * configuration, otherwise accessing DSI registers will hang
3646                  * the machine. See BSpec North Display Engine
3647                  * registers/MIPI[BXT]. We can break out here early, since we
3648                  * need the same DSI PLL to be enabled for both DSI ports.
3649                  */
3650                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3651                         break;
3652
3653                 /* XXX: this works for video mode only */
3654                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3655                 if (!(tmp & DPI_ENABLE))
3656                         continue;
3657
3658                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3659                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3660                         continue;
3661
3662                 pipe_config->cpu_transcoder = cpu_transcoder;
3663                 break;
3664         }
3665
3666         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3667 }
3668
3669 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3670 {
3671         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3672         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3673         u8 master_pipes, slave_pipes;
3674         enum pipe pipe = crtc->pipe;
3675
3676         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3677
3678         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3679                 return;
3680
3681         crtc_state->bigjoiner_pipes =
3682                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3683                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3684 }
3685
3686 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3687                                 struct intel_crtc_state *pipe_config)
3688 {
3689         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3690         bool active;
3691         u32 tmp;
3692
3693         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3694                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3695                 return false;
3696
3697         pipe_config->shared_dpll = NULL;
3698
3699         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3700
3701         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3702             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3703                 drm_WARN_ON(&dev_priv->drm, active);
3704                 active = true;
3705         }
3706
3707         if (!active)
3708                 goto out;
3709
3710         intel_dsc_get_config(pipe_config);
3711         intel_bigjoiner_get_config(pipe_config);
3712
3713         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3714             DISPLAY_VER(dev_priv) >= 11)
3715                 intel_get_transcoder_timings(crtc, pipe_config);
3716
3717         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3718                 intel_vrr_get_config(pipe_config);
3719
3720         intel_get_pipe_src_size(crtc, pipe_config);
3721
3722         if (IS_HASWELL(dev_priv)) {
3723                 u32 tmp = intel_de_read(dev_priv,
3724                                         TRANSCONF(pipe_config->cpu_transcoder));
3725
3726                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3727                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3728                 else
3729                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3730         } else {
3731                 pipe_config->output_format =
3732                         bdw_get_pipe_misc_output_format(crtc);
3733         }
3734
3735         pipe_config->sink_format = pipe_config->output_format;
3736
3737         pipe_config->gamma_mode = intel_de_read(dev_priv,
3738                                                 GAMMA_MODE(crtc->pipe));
3739
3740         pipe_config->csc_mode = intel_de_read(dev_priv,
3741                                               PIPE_CSC_MODE(crtc->pipe));
3742
3743         if (DISPLAY_VER(dev_priv) >= 9) {
3744                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
3745
3746                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
3747                         pipe_config->gamma_enable = true;
3748
3749                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
3750                         pipe_config->csc_enable = true;
3751         } else {
3752                 i9xx_get_pipe_color_config(pipe_config);
3753         }
3754
3755         intel_color_get_config(pipe_config);
3756
3757         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3758         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3759         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3760                 pipe_config->ips_linetime =
3761                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3762
3763         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3764                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3765                 if (DISPLAY_VER(dev_priv) >= 9)
3766                         skl_scaler_get_config(pipe_config);
3767                 else
3768                         ilk_get_pfit_config(pipe_config);
3769         }
3770
3771         hsw_ips_get_config(pipe_config);
3772
3773         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3774             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3775                 pipe_config->pixel_multiplier =
3776                         intel_de_read(dev_priv,
3777                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3778         } else {
3779                 pipe_config->pixel_multiplier = 1;
3780         }
3781
3782         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3783                 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
3784                                     MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
3785                                     CHICKEN_TRANS(pipe_config->cpu_transcoder));
3786
3787                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3788         } else {
3789                 /* no idea if this is correct */
3790                 pipe_config->framestart_delay = 1;
3791         }
3792
3793 out:
3794         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3795
3796         return active;
3797 }
3798
3799 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3800 {
3801         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3802         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3803
3804         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3805                 return false;
3806
3807         crtc_state->hw.active = true;
3808
3809         intel_crtc_readout_derived_state(crtc_state);
3810
3811         return true;
3812 }
3813
3814 static int i9xx_pll_refclk(struct drm_device *dev,
3815                            const struct intel_crtc_state *pipe_config)
3816 {
3817         struct drm_i915_private *dev_priv = to_i915(dev);
3818         u32 dpll = pipe_config->dpll_hw_state.dpll;
3819
3820         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
3821                 return dev_priv->display.vbt.lvds_ssc_freq;
3822         else if (HAS_PCH_SPLIT(dev_priv))
3823                 return 120000;
3824         else if (DISPLAY_VER(dev_priv) != 2)
3825                 return 96000;
3826         else
3827                 return 48000;
3828 }
3829
3830 /* Returns the clock of the currently programmed mode of the given pipe. */
3831 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
3832                          struct intel_crtc_state *pipe_config)
3833 {
3834         struct drm_device *dev = crtc->base.dev;
3835         struct drm_i915_private *dev_priv = to_i915(dev);
3836         u32 dpll = pipe_config->dpll_hw_state.dpll;
3837         u32 fp;
3838         struct dpll clock;
3839         int port_clock;
3840         int refclk = i9xx_pll_refclk(dev, pipe_config);
3841
3842         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3843                 fp = pipe_config->dpll_hw_state.fp0;
3844         else
3845                 fp = pipe_config->dpll_hw_state.fp1;
3846
3847         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3848         if (IS_PINEVIEW(dev_priv)) {
3849                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3850                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3851         } else {
3852                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3853                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3854         }
3855
3856         if (DISPLAY_VER(dev_priv) != 2) {
3857                 if (IS_PINEVIEW(dev_priv))
3858                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3859                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3860                 else
3861                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3862                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3863
3864                 switch (dpll & DPLL_MODE_MASK) {
3865                 case DPLLB_MODE_DAC_SERIAL:
3866                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3867                                 5 : 10;
3868                         break;
3869                 case DPLLB_MODE_LVDS:
3870                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3871                                 7 : 14;
3872                         break;
3873                 default:
3874                         drm_dbg_kms(&dev_priv->drm,
3875                                     "Unknown DPLL mode %08x in programmed "
3876                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
3877                         return;
3878                 }
3879
3880                 if (IS_PINEVIEW(dev_priv))
3881                         port_clock = pnv_calc_dpll_params(refclk, &clock);
3882                 else
3883                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
3884         } else {
3885                 enum pipe lvds_pipe;
3886
3887                 if (IS_I85X(dev_priv) &&
3888                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
3889                     lvds_pipe == crtc->pipe) {
3890                         u32 lvds = intel_de_read(dev_priv, LVDS);
3891
3892                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3893                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3894
3895                         if (lvds & LVDS_CLKB_POWER_UP)
3896                                 clock.p2 = 7;
3897                         else
3898                                 clock.p2 = 14;
3899                 } else {
3900                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3901                                 clock.p1 = 2;
3902                         else {
3903                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3904                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3905                         }
3906                         if (dpll & PLL_P2_DIVIDE_BY_4)
3907                                 clock.p2 = 4;
3908                         else
3909                                 clock.p2 = 2;
3910                 }
3911
3912                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
3913         }
3914
3915         /*
3916          * This value includes pixel_multiplier. We will use
3917          * port_clock to compute adjusted_mode.crtc_clock in the
3918          * encoder's get_config() function.
3919          */
3920         pipe_config->port_clock = port_clock;
3921 }
3922
3923 int intel_dotclock_calculate(int link_freq,
3924                              const struct intel_link_m_n *m_n)
3925 {
3926         /*
3927          * The calculation for the data clock is:
3928          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3929          * But we want to avoid losing precison if possible, so:
3930          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3931          *
3932          * and the link clock is simpler:
3933          * link_clock = (m * link_clock) / n
3934          */
3935
3936         if (!m_n->link_n)
3937                 return 0;
3938
3939         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
3940                                 m_n->link_n);
3941 }
3942
3943 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
3944 {
3945         int dotclock;
3946
3947         if (intel_crtc_has_dp_encoder(pipe_config))
3948                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
3949                                                     &pipe_config->dp_m_n);
3950         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3951                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
3952                                              pipe_config->pipe_bpp);
3953         else
3954                 dotclock = pipe_config->port_clock;
3955
3956         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3957             !intel_crtc_has_dp_encoder(pipe_config))
3958                 dotclock *= 2;
3959
3960         if (pipe_config->pixel_multiplier)
3961                 dotclock /= pipe_config->pixel_multiplier;
3962
3963         return dotclock;
3964 }
3965
3966 /* Returns the currently programmed mode of the given encoder. */
3967 struct drm_display_mode *
3968 intel_encoder_current_mode(struct intel_encoder *encoder)
3969 {
3970         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3971         struct intel_crtc_state *crtc_state;
3972         struct drm_display_mode *mode;
3973         struct intel_crtc *crtc;
3974         enum pipe pipe;
3975
3976         if (!encoder->get_hw_state(encoder, &pipe))
3977                 return NULL;
3978
3979         crtc = intel_crtc_for_pipe(dev_priv, pipe);
3980
3981         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3982         if (!mode)
3983                 return NULL;
3984
3985         crtc_state = intel_crtc_state_alloc(crtc);
3986         if (!crtc_state) {
3987                 kfree(mode);
3988                 return NULL;
3989         }
3990
3991         if (!intel_crtc_get_pipe_config(crtc_state)) {
3992                 kfree(crtc_state);
3993                 kfree(mode);
3994                 return NULL;
3995         }
3996
3997         intel_encoder_get_config(encoder, crtc_state);
3998
3999         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4000
4001         kfree(crtc_state);
4002
4003         return mode;
4004 }
4005
4006 static bool encoders_cloneable(const struct intel_encoder *a,
4007                                const struct intel_encoder *b)
4008 {
4009         /* masks could be asymmetric, so check both ways */
4010         return a == b || (a->cloneable & BIT(b->type) &&
4011                           b->cloneable & BIT(a->type));
4012 }
4013
4014 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4015                                          struct intel_crtc *crtc,
4016                                          struct intel_encoder *encoder)
4017 {
4018         struct intel_encoder *source_encoder;
4019         struct drm_connector *connector;
4020         struct drm_connector_state *connector_state;
4021         int i;
4022
4023         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4024                 if (connector_state->crtc != &crtc->base)
4025                         continue;
4026
4027                 source_encoder =
4028                         to_intel_encoder(connector_state->best_encoder);
4029                 if (!encoders_cloneable(encoder, source_encoder))
4030                         return false;
4031         }
4032
4033         return true;
4034 }
4035
4036 static int icl_add_linked_planes(struct intel_atomic_state *state)
4037 {
4038         struct intel_plane *plane, *linked;
4039         struct intel_plane_state *plane_state, *linked_plane_state;
4040         int i;
4041
4042         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4043                 linked = plane_state->planar_linked_plane;
4044
4045                 if (!linked)
4046                         continue;
4047
4048                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4049                 if (IS_ERR(linked_plane_state))
4050                         return PTR_ERR(linked_plane_state);
4051
4052                 drm_WARN_ON(state->base.dev,
4053                             linked_plane_state->planar_linked_plane != plane);
4054                 drm_WARN_ON(state->base.dev,
4055                             linked_plane_state->planar_slave == plane_state->planar_slave);
4056         }
4057
4058         return 0;
4059 }
4060
4061 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4062 {
4063         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4064         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4065         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4066         struct intel_plane *plane, *linked;
4067         struct intel_plane_state *plane_state;
4068         int i;
4069
4070         if (DISPLAY_VER(dev_priv) < 11)
4071                 return 0;
4072
4073         /*
4074          * Destroy all old plane links and make the slave plane invisible
4075          * in the crtc_state->active_planes mask.
4076          */
4077         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4078                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4079                         continue;
4080
4081                 plane_state->planar_linked_plane = NULL;
4082                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4083                         crtc_state->enabled_planes &= ~BIT(plane->id);
4084                         crtc_state->active_planes &= ~BIT(plane->id);
4085                         crtc_state->update_planes |= BIT(plane->id);
4086                         crtc_state->data_rate[plane->id] = 0;
4087                         crtc_state->rel_data_rate[plane->id] = 0;
4088                 }
4089
4090                 plane_state->planar_slave = false;
4091         }
4092
4093         if (!crtc_state->nv12_planes)
4094                 return 0;
4095
4096         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4097                 struct intel_plane_state *linked_state = NULL;
4098
4099                 if (plane->pipe != crtc->pipe ||
4100                     !(crtc_state->nv12_planes & BIT(plane->id)))
4101                         continue;
4102
4103                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4104                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4105                                 continue;
4106
4107                         if (crtc_state->active_planes & BIT(linked->id))
4108                                 continue;
4109
4110                         linked_state = intel_atomic_get_plane_state(state, linked);
4111                         if (IS_ERR(linked_state))
4112                                 return PTR_ERR(linked_state);
4113
4114                         break;
4115                 }
4116
4117                 if (!linked_state) {
4118                         drm_dbg_kms(&dev_priv->drm,
4119                                     "Need %d free Y planes for planar YUV\n",
4120                                     hweight8(crtc_state->nv12_planes));
4121
4122                         return -EINVAL;
4123                 }
4124
4125                 plane_state->planar_linked_plane = linked;
4126
4127                 linked_state->planar_slave = true;
4128                 linked_state->planar_linked_plane = plane;
4129                 crtc_state->enabled_planes |= BIT(linked->id);
4130                 crtc_state->active_planes |= BIT(linked->id);
4131                 crtc_state->update_planes |= BIT(linked->id);
4132                 crtc_state->data_rate[linked->id] =
4133                         crtc_state->data_rate_y[plane->id];
4134                 crtc_state->rel_data_rate[linked->id] =
4135                         crtc_state->rel_data_rate_y[plane->id];
4136                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4137                             linked->base.name, plane->base.name);
4138
4139                 /* Copy parameters to slave plane */
4140                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4141                 linked_state->color_ctl = plane_state->color_ctl;
4142                 linked_state->view = plane_state->view;
4143                 linked_state->decrypt = plane_state->decrypt;
4144
4145                 intel_plane_copy_hw_state(linked_state, plane_state);
4146                 linked_state->uapi.src = plane_state->uapi.src;
4147                 linked_state->uapi.dst = plane_state->uapi.dst;
4148
4149                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4150                         if (linked->id == PLANE_SPRITE5)
4151                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4152                         else if (linked->id == PLANE_SPRITE4)
4153                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4154                         else if (linked->id == PLANE_SPRITE3)
4155                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4156                         else if (linked->id == PLANE_SPRITE2)
4157                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4158                         else
4159                                 MISSING_CASE(linked->id);
4160                 }
4161         }
4162
4163         return 0;
4164 }
4165
4166 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4167 {
4168         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4169         struct intel_atomic_state *state =
4170                 to_intel_atomic_state(new_crtc_state->uapi.state);
4171         const struct intel_crtc_state *old_crtc_state =
4172                 intel_atomic_get_old_crtc_state(state, crtc);
4173
4174         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4175 }
4176
4177 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4178 {
4179         const struct drm_display_mode *pipe_mode =
4180                 &crtc_state->hw.pipe_mode;
4181         int linetime_wm;
4182
4183         if (!crtc_state->hw.enable)
4184                 return 0;
4185
4186         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4187                                         pipe_mode->crtc_clock);
4188
4189         return min(linetime_wm, 0x1ff);
4190 }
4191
4192 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4193                                const struct intel_cdclk_state *cdclk_state)
4194 {
4195         const struct drm_display_mode *pipe_mode =
4196                 &crtc_state->hw.pipe_mode;
4197         int linetime_wm;
4198
4199         if (!crtc_state->hw.enable)
4200                 return 0;
4201
4202         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4203                                         cdclk_state->logical.cdclk);
4204
4205         return min(linetime_wm, 0x1ff);
4206 }
4207
4208 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4209 {
4210         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4211         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4212         const struct drm_display_mode *pipe_mode =
4213                 &crtc_state->hw.pipe_mode;
4214         int linetime_wm;
4215
4216         if (!crtc_state->hw.enable)
4217                 return 0;
4218
4219         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4220                                    crtc_state->pixel_rate);
4221
4222         /* Display WA #1135: BXT:ALL GLK:ALL */
4223         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4224             skl_watermark_ipc_enabled(dev_priv))
4225                 linetime_wm /= 2;
4226
4227         return min(linetime_wm, 0x1ff);
4228 }
4229
4230 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4231                                    struct intel_crtc *crtc)
4232 {
4233         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4234         struct intel_crtc_state *crtc_state =
4235                 intel_atomic_get_new_crtc_state(state, crtc);
4236         const struct intel_cdclk_state *cdclk_state;
4237
4238         if (DISPLAY_VER(dev_priv) >= 9)
4239                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4240         else
4241                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4242
4243         if (!hsw_crtc_supports_ips(crtc))
4244                 return 0;
4245
4246         cdclk_state = intel_atomic_get_cdclk_state(state);
4247         if (IS_ERR(cdclk_state))
4248                 return PTR_ERR(cdclk_state);
4249
4250         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4251                                                        cdclk_state);
4252
4253         return 0;
4254 }
4255
4256 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4257                                    struct intel_crtc *crtc)
4258 {
4259         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4260         struct intel_crtc_state *crtc_state =
4261                 intel_atomic_get_new_crtc_state(state, crtc);
4262         int ret;
4263
4264         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4265             intel_crtc_needs_modeset(crtc_state) &&
4266             !crtc_state->hw.active)
4267                 crtc_state->update_wm_post = true;
4268
4269         if (intel_crtc_needs_modeset(crtc_state)) {
4270                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4271                 if (ret)
4272                         return ret;
4273         }
4274
4275         /*
4276          * May need to update pipe gamma enable bits
4277          * when C8 planes are getting enabled/disabled.
4278          */
4279         if (c8_planes_changed(crtc_state))
4280                 crtc_state->uapi.color_mgmt_changed = true;
4281
4282         if (intel_crtc_needs_color_update(crtc_state)) {
4283                 ret = intel_color_check(crtc_state);
4284                 if (ret)
4285                         return ret;
4286         }
4287
4288         ret = intel_compute_pipe_wm(state, crtc);
4289         if (ret) {
4290                 drm_dbg_kms(&dev_priv->drm,
4291                             "Target pipe watermarks are invalid\n");
4292                 return ret;
4293         }
4294
4295         /*
4296          * Calculate 'intermediate' watermarks that satisfy both the
4297          * old state and the new state.  We can program these
4298          * immediately.
4299          */
4300         ret = intel_compute_intermediate_wm(state, crtc);
4301         if (ret) {
4302                 drm_dbg_kms(&dev_priv->drm,
4303                             "No valid intermediate pipe watermarks are possible\n");
4304                 return ret;
4305         }
4306
4307         if (DISPLAY_VER(dev_priv) >= 9) {
4308                 if (intel_crtc_needs_modeset(crtc_state) ||
4309                     intel_crtc_needs_fastset(crtc_state)) {
4310                         ret = skl_update_scaler_crtc(crtc_state);
4311                         if (ret)
4312                                 return ret;
4313                 }
4314
4315                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4316                 if (ret)
4317                         return ret;
4318         }
4319
4320         if (HAS_IPS(dev_priv)) {
4321                 ret = hsw_ips_compute_config(state, crtc);
4322                 if (ret)
4323                         return ret;
4324         }
4325
4326         if (DISPLAY_VER(dev_priv) >= 9 ||
4327             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4328                 ret = hsw_compute_linetime_wm(state, crtc);
4329                 if (ret)
4330                         return ret;
4331
4332         }
4333
4334         ret = intel_psr2_sel_fetch_update(state, crtc);
4335         if (ret)
4336                 return ret;
4337
4338         return 0;
4339 }
4340
4341 static int
4342 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4343                       struct intel_crtc_state *crtc_state)
4344 {
4345         struct drm_connector *connector = conn_state->connector;
4346         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4347         const struct drm_display_info *info = &connector->display_info;
4348         int bpp;
4349
4350         switch (conn_state->max_bpc) {
4351         case 6 ... 7:
4352                 bpp = 6 * 3;
4353                 break;
4354         case 8 ... 9:
4355                 bpp = 8 * 3;
4356                 break;
4357         case 10 ... 11:
4358                 bpp = 10 * 3;
4359                 break;
4360         case 12 ... 16:
4361                 bpp = 12 * 3;
4362                 break;
4363         default:
4364                 MISSING_CASE(conn_state->max_bpc);
4365                 return -EINVAL;
4366         }
4367
4368         if (bpp < crtc_state->pipe_bpp) {
4369                 drm_dbg_kms(&i915->drm,
4370                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4371                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4372                             connector->base.id, connector->name,
4373                             bpp, 3 * info->bpc,
4374                             3 * conn_state->max_requested_bpc,
4375                             crtc_state->pipe_bpp);
4376
4377                 crtc_state->pipe_bpp = bpp;
4378         }
4379
4380         return 0;
4381 }
4382
4383 static int
4384 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4385                           struct intel_crtc *crtc)
4386 {
4387         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4388         struct intel_crtc_state *crtc_state =
4389                 intel_atomic_get_new_crtc_state(state, crtc);
4390         struct drm_connector *connector;
4391         struct drm_connector_state *connector_state;
4392         int bpp, i;
4393
4394         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4395             IS_CHERRYVIEW(dev_priv)))
4396                 bpp = 10*3;
4397         else if (DISPLAY_VER(dev_priv) >= 5)
4398                 bpp = 12*3;
4399         else
4400                 bpp = 8*3;
4401
4402         crtc_state->pipe_bpp = bpp;
4403
4404         /* Clamp display bpp to connector max bpp */
4405         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4406                 int ret;
4407
4408                 if (connector_state->crtc != &crtc->base)
4409                         continue;
4410
4411                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4412                 if (ret)
4413                         return ret;
4414         }
4415
4416         return 0;
4417 }
4418
4419 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4420 {
4421         struct drm_device *dev = state->base.dev;
4422         struct drm_connector *connector;
4423         struct drm_connector_list_iter conn_iter;
4424         unsigned int used_ports = 0;
4425         unsigned int used_mst_ports = 0;
4426         bool ret = true;
4427
4428         /*
4429          * We're going to peek into connector->state,
4430          * hence connection_mutex must be held.
4431          */
4432         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4433
4434         /*
4435          * Walk the connector list instead of the encoder
4436          * list to detect the problem on ddi platforms
4437          * where there's just one encoder per digital port.
4438          */
4439         drm_connector_list_iter_begin(dev, &conn_iter);
4440         drm_for_each_connector_iter(connector, &conn_iter) {
4441                 struct drm_connector_state *connector_state;
4442                 struct intel_encoder *encoder;
4443
4444                 connector_state =
4445                         drm_atomic_get_new_connector_state(&state->base,
4446                                                            connector);
4447                 if (!connector_state)
4448                         connector_state = connector->state;
4449
4450                 if (!connector_state->best_encoder)
4451                         continue;
4452
4453                 encoder = to_intel_encoder(connector_state->best_encoder);
4454
4455                 drm_WARN_ON(dev, !connector_state->crtc);
4456
4457                 switch (encoder->type) {
4458                 case INTEL_OUTPUT_DDI:
4459                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4460                                 break;
4461                         fallthrough;
4462                 case INTEL_OUTPUT_DP:
4463                 case INTEL_OUTPUT_HDMI:
4464                 case INTEL_OUTPUT_EDP:
4465                         /* the same port mustn't appear more than once */
4466                         if (used_ports & BIT(encoder->port))
4467                                 ret = false;
4468
4469                         used_ports |= BIT(encoder->port);
4470                         break;
4471                 case INTEL_OUTPUT_DP_MST:
4472                         used_mst_ports |=
4473                                 1 << encoder->port;
4474                         break;
4475                 default:
4476                         break;
4477                 }
4478         }
4479         drm_connector_list_iter_end(&conn_iter);
4480
4481         /* can't mix MST and SST/HDMI on the same port */
4482         if (used_ports & used_mst_ports)
4483                 return false;
4484
4485         return ret;
4486 }
4487
4488 static void
4489 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4490                                            struct intel_crtc *crtc)
4491 {
4492         struct intel_crtc_state *crtc_state =
4493                 intel_atomic_get_new_crtc_state(state, crtc);
4494
4495         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4496
4497         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4498                                   crtc_state->uapi.degamma_lut);
4499         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4500                                   crtc_state->uapi.gamma_lut);
4501         drm_property_replace_blob(&crtc_state->hw.ctm,
4502                                   crtc_state->uapi.ctm);
4503 }
4504
4505 static void
4506 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4507                                          struct intel_crtc *crtc)
4508 {
4509         struct intel_crtc_state *crtc_state =
4510                 intel_atomic_get_new_crtc_state(state, crtc);
4511
4512         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4513
4514         crtc_state->hw.enable = crtc_state->uapi.enable;
4515         crtc_state->hw.active = crtc_state->uapi.active;
4516         drm_mode_copy(&crtc_state->hw.mode,
4517                       &crtc_state->uapi.mode);
4518         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4519                       &crtc_state->uapi.adjusted_mode);
4520         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4521
4522         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4523 }
4524
4525 static void
4526 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4527                                     struct intel_crtc *slave_crtc)
4528 {
4529         struct intel_crtc_state *slave_crtc_state =
4530                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4531         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4532         const struct intel_crtc_state *master_crtc_state =
4533                 intel_atomic_get_new_crtc_state(state, master_crtc);
4534
4535         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4536                                   master_crtc_state->hw.degamma_lut);
4537         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4538                                   master_crtc_state->hw.gamma_lut);
4539         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4540                                   master_crtc_state->hw.ctm);
4541
4542         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4543 }
4544
4545 static int
4546 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4547                                   struct intel_crtc *slave_crtc)
4548 {
4549         struct intel_crtc_state *slave_crtc_state =
4550                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4551         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4552         const struct intel_crtc_state *master_crtc_state =
4553                 intel_atomic_get_new_crtc_state(state, master_crtc);
4554         struct intel_crtc_state *saved_state;
4555
4556         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4557                 slave_crtc_state->bigjoiner_pipes);
4558
4559         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4560         if (!saved_state)
4561                 return -ENOMEM;
4562
4563         /* preserve some things from the slave's original crtc state */
4564         saved_state->uapi = slave_crtc_state->uapi;
4565         saved_state->scaler_state = slave_crtc_state->scaler_state;
4566         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4567         saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
4568         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4569
4570         intel_crtc_free_hw_state(slave_crtc_state);
4571         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4572         kfree(saved_state);
4573
4574         /* Re-init hw state */
4575         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4576         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4577         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4578         drm_mode_copy(&slave_crtc_state->hw.mode,
4579                       &master_crtc_state->hw.mode);
4580         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4581                       &master_crtc_state->hw.pipe_mode);
4582         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4583                       &master_crtc_state->hw.adjusted_mode);
4584         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4585
4586         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4587
4588         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4589         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4590         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4591
4592         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4593                 slave_crtc_state->bigjoiner_pipes);
4594
4595         return 0;
4596 }
4597
4598 static int
4599 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4600                                  struct intel_crtc *crtc)
4601 {
4602         struct intel_crtc_state *crtc_state =
4603                 intel_atomic_get_new_crtc_state(state, crtc);
4604         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4605         struct intel_crtc_state *saved_state;
4606
4607         saved_state = intel_crtc_state_alloc(crtc);
4608         if (!saved_state)
4609                 return -ENOMEM;
4610
4611         /* free the old crtc_state->hw members */
4612         intel_crtc_free_hw_state(crtc_state);
4613
4614         /* FIXME: before the switch to atomic started, a new pipe_config was
4615          * kzalloc'd. Code that depends on any field being zero should be
4616          * fixed, so that the crtc_state can be safely duplicated. For now,
4617          * only fields that are know to not cause problems are preserved. */
4618
4619         saved_state->uapi = crtc_state->uapi;
4620         saved_state->inherited = crtc_state->inherited;
4621         saved_state->scaler_state = crtc_state->scaler_state;
4622         saved_state->shared_dpll = crtc_state->shared_dpll;
4623         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4624         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4625                sizeof(saved_state->icl_port_dplls));
4626         saved_state->crc_enabled = crtc_state->crc_enabled;
4627         if (IS_G4X(dev_priv) ||
4628             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4629                 saved_state->wm = crtc_state->wm;
4630
4631         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4632         kfree(saved_state);
4633
4634         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4635
4636         return 0;
4637 }
4638
4639 static int
4640 intel_modeset_pipe_config(struct intel_atomic_state *state,
4641                           struct intel_crtc *crtc)
4642 {
4643         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4644         struct intel_crtc_state *crtc_state =
4645                 intel_atomic_get_new_crtc_state(state, crtc);
4646         struct drm_connector *connector;
4647         struct drm_connector_state *connector_state;
4648         int pipe_src_w, pipe_src_h;
4649         int base_bpp, ret, i;
4650         bool retry = true;
4651
4652         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4653
4654         crtc_state->framestart_delay = 1;
4655
4656         /*
4657          * Sanitize sync polarity flags based on requested ones. If neither
4658          * positive or negative polarity is requested, treat this as meaning
4659          * negative polarity.
4660          */
4661         if (!(crtc_state->hw.adjusted_mode.flags &
4662               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4663                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4664
4665         if (!(crtc_state->hw.adjusted_mode.flags &
4666               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4667                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4668
4669         ret = compute_baseline_pipe_bpp(state, crtc);
4670         if (ret)
4671                 return ret;
4672
4673         base_bpp = crtc_state->pipe_bpp;
4674
4675         /*
4676          * Determine the real pipe dimensions. Note that stereo modes can
4677          * increase the actual pipe size due to the frame doubling and
4678          * insertion of additional space for blanks between the frame. This
4679          * is stored in the crtc timings. We use the requested mode to do this
4680          * computation to clearly distinguish it from the adjusted mode, which
4681          * can be changed by the connectors in the below retry loop.
4682          */
4683         drm_mode_get_hv_timing(&crtc_state->hw.mode,
4684                                &pipe_src_w, &pipe_src_h);
4685         drm_rect_init(&crtc_state->pipe_src, 0, 0,
4686                       pipe_src_w, pipe_src_h);
4687
4688         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4689                 struct intel_encoder *encoder =
4690                         to_intel_encoder(connector_state->best_encoder);
4691
4692                 if (connector_state->crtc != &crtc->base)
4693                         continue;
4694
4695                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4696                         drm_dbg_kms(&i915->drm,
4697                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4698                                     encoder->base.base.id, encoder->base.name);
4699                         return -EINVAL;
4700                 }
4701
4702                 /*
4703                  * Determine output_types before calling the .compute_config()
4704                  * hooks so that the hooks can use this information safely.
4705                  */
4706                 if (encoder->compute_output_type)
4707                         crtc_state->output_types |=
4708                                 BIT(encoder->compute_output_type(encoder, crtc_state,
4709                                                                  connector_state));
4710                 else
4711                         crtc_state->output_types |= BIT(encoder->type);
4712         }
4713
4714 encoder_retry:
4715         /* Ensure the port clock defaults are reset when retrying. */
4716         crtc_state->port_clock = 0;
4717         crtc_state->pixel_multiplier = 1;
4718
4719         /* Fill in default crtc timings, allow encoders to overwrite them. */
4720         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4721                               CRTC_STEREO_DOUBLE);
4722
4723         /* Pass our mode to the connectors and the CRTC to give them a chance to
4724          * adjust it according to limitations or connector properties, and also
4725          * a chance to reject the mode entirely.
4726          */
4727         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4728                 struct intel_encoder *encoder =
4729                         to_intel_encoder(connector_state->best_encoder);
4730
4731                 if (connector_state->crtc != &crtc->base)
4732                         continue;
4733
4734                 ret = encoder->compute_config(encoder, crtc_state,
4735                                               connector_state);
4736                 if (ret == -EDEADLK)
4737                         return ret;
4738                 if (ret < 0) {
4739                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
4740                                     encoder->base.base.id, encoder->base.name, ret);
4741                         return ret;
4742                 }
4743         }
4744
4745         /* Set default port clock if not overwritten by the encoder. Needs to be
4746          * done afterwards in case the encoder adjusts the mode. */
4747         if (!crtc_state->port_clock)
4748                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4749                         * crtc_state->pixel_multiplier;
4750
4751         ret = intel_crtc_compute_config(state, crtc);
4752         if (ret == -EDEADLK)
4753                 return ret;
4754         if (ret == -EAGAIN) {
4755                 if (drm_WARN(&i915->drm, !retry,
4756                              "[CRTC:%d:%s] loop in pipe configuration computation\n",
4757                              crtc->base.base.id, crtc->base.name))
4758                         return -EINVAL;
4759
4760                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
4761                             crtc->base.base.id, crtc->base.name);
4762                 retry = false;
4763                 goto encoder_retry;
4764         }
4765         if (ret < 0) {
4766                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
4767                             crtc->base.base.id, crtc->base.name, ret);
4768                 return ret;
4769         }
4770
4771         /* Dithering seems to not pass-through bits correctly when it should, so
4772          * only enable it on 6bpc panels and when its not a compliance
4773          * test requesting 6bpc video pattern.
4774          */
4775         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4776                 !crtc_state->dither_force_disable;
4777         drm_dbg_kms(&i915->drm,
4778                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4779                     crtc->base.base.id, crtc->base.name,
4780                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4781
4782         return 0;
4783 }
4784
4785 static int
4786 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4787                                struct intel_crtc *crtc)
4788 {
4789         struct intel_crtc_state *crtc_state =
4790                 intel_atomic_get_new_crtc_state(state, crtc);
4791         struct drm_connector_state *conn_state;
4792         struct drm_connector *connector;
4793         int i;
4794
4795         intel_bigjoiner_adjust_pipe_src(crtc_state);
4796
4797         for_each_new_connector_in_state(&state->base, connector,
4798                                         conn_state, i) {
4799                 struct intel_encoder *encoder =
4800                         to_intel_encoder(conn_state->best_encoder);
4801                 int ret;
4802
4803                 if (conn_state->crtc != &crtc->base ||
4804                     !encoder->compute_config_late)
4805                         continue;
4806
4807                 ret = encoder->compute_config_late(encoder, crtc_state,
4808                                                    conn_state);
4809                 if (ret)
4810                         return ret;
4811         }
4812
4813         return 0;
4814 }
4815
4816 bool intel_fuzzy_clock_check(int clock1, int clock2)
4817 {
4818         int diff;
4819
4820         if (clock1 == clock2)
4821                 return true;
4822
4823         if (!clock1 || !clock2)
4824                 return false;
4825
4826         diff = abs(clock1 - clock2);
4827
4828         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4829                 return true;
4830
4831         return false;
4832 }
4833
4834 static bool
4835 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4836                        const struct intel_link_m_n *m2_n2)
4837 {
4838         return m_n->tu == m2_n2->tu &&
4839                 m_n->data_m == m2_n2->data_m &&
4840                 m_n->data_n == m2_n2->data_n &&
4841                 m_n->link_m == m2_n2->link_m &&
4842                 m_n->link_n == m2_n2->link_n;
4843 }
4844
4845 static bool
4846 intel_compare_infoframe(const union hdmi_infoframe *a,
4847                         const union hdmi_infoframe *b)
4848 {
4849         return memcmp(a, b, sizeof(*a)) == 0;
4850 }
4851
4852 static bool
4853 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4854                          const struct drm_dp_vsc_sdp *b)
4855 {
4856         return memcmp(a, b, sizeof(*a)) == 0;
4857 }
4858
4859 static bool
4860 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4861 {
4862         return memcmp(a, b, len) == 0;
4863 }
4864
4865 static void
4866 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
4867                                bool fastset, const char *name,
4868                                const union hdmi_infoframe *a,
4869                                const union hdmi_infoframe *b)
4870 {
4871         if (fastset) {
4872                 if (!drm_debug_enabled(DRM_UT_KMS))
4873                         return;
4874
4875                 drm_dbg_kms(&dev_priv->drm,
4876                             "fastset requirement not met in %s infoframe\n", name);
4877                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4878                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
4879                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4880                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
4881         } else {
4882                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
4883                 drm_err(&dev_priv->drm, "expected:\n");
4884                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
4885                 drm_err(&dev_priv->drm, "found:\n");
4886                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
4887         }
4888 }
4889
4890 static void
4891 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
4892                                 bool fastset, const char *name,
4893                                 const struct drm_dp_vsc_sdp *a,
4894                                 const struct drm_dp_vsc_sdp *b)
4895 {
4896         if (fastset) {
4897                 if (!drm_debug_enabled(DRM_UT_KMS))
4898                         return;
4899
4900                 drm_dbg_kms(&dev_priv->drm,
4901                             "fastset requirement not met in %s dp sdp\n", name);
4902                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4903                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
4904                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4905                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
4906         } else {
4907                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
4908                 drm_err(&dev_priv->drm, "expected:\n");
4909                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
4910                 drm_err(&dev_priv->drm, "found:\n");
4911                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
4912         }
4913 }
4914
4915 /* Returns the length up to and including the last differing byte */
4916 static size_t
4917 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4918 {
4919         int i;
4920
4921         for (i = len - 1; i >= 0; i--) {
4922                 if (a[i] != b[i])
4923                         return i + 1;
4924         }
4925
4926         return 0;
4927 }
4928
4929 static void
4930 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
4931                             bool fastset, const char *name,
4932                             const u8 *a, const u8 *b, size_t len)
4933 {
4934         if (fastset) {
4935                 if (!drm_debug_enabled(DRM_UT_KMS))
4936                         return;
4937
4938                 /* only dump up to the last difference */
4939                 len = memcmp_diff_len(a, b, len);
4940
4941                 drm_dbg_kms(&dev_priv->drm,
4942                             "fastset requirement not met in %s buffer\n", name);
4943                 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
4944                                16, 0, a, len, false);
4945                 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
4946                                16, 0, b, len, false);
4947         } else {
4948                 /* only dump up to the last difference */
4949                 len = memcmp_diff_len(a, b, len);
4950
4951                 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
4952                 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
4953                                16, 0, a, len, false);
4954                 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
4955                                16, 0, b, len, false);
4956         }
4957 }
4958
4959 static void __printf(4, 5)
4960 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
4961                      const char *name, const char *format, ...)
4962 {
4963         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4964         struct va_format vaf;
4965         va_list args;
4966
4967         va_start(args, format);
4968         vaf.fmt = format;
4969         vaf.va = &args;
4970
4971         if (fastset)
4972                 drm_dbg_kms(&i915->drm,
4973                             "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4974                             crtc->base.base.id, crtc->base.name, name, &vaf);
4975         else
4976                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
4977                         crtc->base.base.id, crtc->base.name, name, &vaf);
4978
4979         va_end(args);
4980 }
4981
4982 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
4983 {
4984         if (dev_priv->params.fastboot != -1)
4985                 return dev_priv->params.fastboot;
4986
4987         /* Enable fastboot by default on Skylake and newer */
4988         if (DISPLAY_VER(dev_priv) >= 9)
4989                 return true;
4990
4991         /* Enable fastboot by default on VLV and CHV */
4992         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4993                 return true;
4994
4995         /* Disabled by default on all others */
4996         return false;
4997 }
4998
4999 bool
5000 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5001                           const struct intel_crtc_state *pipe_config,
5002                           bool fastset)
5003 {
5004         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5005         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5006         bool ret = true;
5007         bool fixup_inherited = fastset &&
5008                 current_config->inherited && !pipe_config->inherited;
5009
5010         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5011                 drm_dbg_kms(&dev_priv->drm,
5012                             "initial modeset and fastboot not set\n");
5013                 ret = false;
5014         }
5015
5016 #define PIPE_CONF_CHECK_X(name) do { \
5017         if (current_config->name != pipe_config->name) { \
5018                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5019                                      "(expected 0x%08x, found 0x%08x)", \
5020                                      current_config->name, \
5021                                      pipe_config->name); \
5022                 ret = false; \
5023         } \
5024 } while (0)
5025
5026 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5027         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5028                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5029                                      "(expected 0x%08x, found 0x%08x)", \
5030                                      current_config->name & (mask), \
5031                                      pipe_config->name & (mask)); \
5032                 ret = false; \
5033         } \
5034 } while (0)
5035
5036 #define PIPE_CONF_CHECK_I(name) do { \
5037         if (current_config->name != pipe_config->name) { \
5038                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5039                                      "(expected %i, found %i)", \
5040                                      current_config->name, \
5041                                      pipe_config->name); \
5042                 ret = false; \
5043         } \
5044 } while (0)
5045
5046 #define PIPE_CONF_CHECK_BOOL(name) do { \
5047         if (current_config->name != pipe_config->name) { \
5048                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5049                                      "(expected %s, found %s)", \
5050                                      str_yes_no(current_config->name), \
5051                                      str_yes_no(pipe_config->name)); \
5052                 ret = false; \
5053         } \
5054 } while (0)
5055
5056 /*
5057  * Checks state where we only read out the enabling, but not the entire
5058  * state itself (like full infoframes or ELD for audio). These states
5059  * require a full modeset on bootup to fix up.
5060  */
5061 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5062         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5063                 PIPE_CONF_CHECK_BOOL(name); \
5064         } else { \
5065                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5066                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5067                                      str_yes_no(current_config->name), \
5068                                      str_yes_no(pipe_config->name)); \
5069                 ret = false; \
5070         } \
5071 } while (0)
5072
5073 #define PIPE_CONF_CHECK_P(name) do { \
5074         if (current_config->name != pipe_config->name) { \
5075                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5076                                      "(expected %p, found %p)", \
5077                                      current_config->name, \
5078                                      pipe_config->name); \
5079                 ret = false; \
5080         } \
5081 } while (0)
5082
5083 #define PIPE_CONF_CHECK_M_N(name) do { \
5084         if (!intel_compare_link_m_n(&current_config->name, \
5085                                     &pipe_config->name)) { \
5086                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5087                                      "(expected tu %i data %i/%i link %i/%i, " \
5088                                      "found tu %i, data %i/%i link %i/%i)", \
5089                                      current_config->name.tu, \
5090                                      current_config->name.data_m, \
5091                                      current_config->name.data_n, \
5092                                      current_config->name.link_m, \
5093                                      current_config->name.link_n, \
5094                                      pipe_config->name.tu, \
5095                                      pipe_config->name.data_m, \
5096                                      pipe_config->name.data_n, \
5097                                      pipe_config->name.link_m, \
5098                                      pipe_config->name.link_n); \
5099                 ret = false; \
5100         } \
5101 } while (0)
5102
5103 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5104         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5105         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5106         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5107         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5108         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5109         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5110         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5111         PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5112         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5113         PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5114         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5115         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5116 } while (0)
5117
5118 #define PIPE_CONF_CHECK_RECT(name) do { \
5119         PIPE_CONF_CHECK_I(name.x1); \
5120         PIPE_CONF_CHECK_I(name.x2); \
5121         PIPE_CONF_CHECK_I(name.y1); \
5122         PIPE_CONF_CHECK_I(name.y2); \
5123 } while (0)
5124
5125 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5126         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5127                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5128                                      "(%x) (expected %i, found %i)", \
5129                                      (mask), \
5130                                      current_config->name & (mask), \
5131                                      pipe_config->name & (mask)); \
5132                 ret = false; \
5133         } \
5134 } while (0)
5135
5136 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5137         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5138                                      &pipe_config->infoframes.name)) { \
5139                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5140                                                &current_config->infoframes.name, \
5141                                                &pipe_config->infoframes.name); \
5142                 ret = false; \
5143         } \
5144 } while (0)
5145
5146 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5147         if (!current_config->has_psr && !pipe_config->has_psr && \
5148             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5149                                       &pipe_config->infoframes.name)) { \
5150                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5151                                                 &current_config->infoframes.name, \
5152                                                 &pipe_config->infoframes.name); \
5153                 ret = false; \
5154         } \
5155 } while (0)
5156
5157 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5158         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5159         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5160         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5161                 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5162                                             current_config->name, \
5163                                             pipe_config->name, \
5164                                             (len)); \
5165                 ret = false; \
5166         } \
5167 } while (0)
5168
5169 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5170         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5171             !intel_color_lut_equal(current_config, \
5172                                    current_config->lut, pipe_config->lut, \
5173                                    is_pre_csc_lut)) {   \
5174                 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5175                                      "hw_state doesn't match sw_state"); \
5176                 ret = false; \
5177         } \
5178 } while (0)
5179
5180 #define PIPE_CONF_CHECK_CSC(name) do { \
5181         PIPE_CONF_CHECK_X(name.preoff[0]); \
5182         PIPE_CONF_CHECK_X(name.preoff[1]); \
5183         PIPE_CONF_CHECK_X(name.preoff[2]); \
5184         PIPE_CONF_CHECK_X(name.coeff[0]); \
5185         PIPE_CONF_CHECK_X(name.coeff[1]); \
5186         PIPE_CONF_CHECK_X(name.coeff[2]); \
5187         PIPE_CONF_CHECK_X(name.coeff[3]); \
5188         PIPE_CONF_CHECK_X(name.coeff[4]); \
5189         PIPE_CONF_CHECK_X(name.coeff[5]); \
5190         PIPE_CONF_CHECK_X(name.coeff[6]); \
5191         PIPE_CONF_CHECK_X(name.coeff[7]); \
5192         PIPE_CONF_CHECK_X(name.coeff[8]); \
5193         PIPE_CONF_CHECK_X(name.postoff[0]); \
5194         PIPE_CONF_CHECK_X(name.postoff[1]); \
5195         PIPE_CONF_CHECK_X(name.postoff[2]); \
5196 } while (0)
5197
5198 #define PIPE_CONF_QUIRK(quirk) \
5199         ((current_config->quirks | pipe_config->quirks) & (quirk))
5200
5201         PIPE_CONF_CHECK_I(hw.enable);
5202         PIPE_CONF_CHECK_I(hw.active);
5203
5204         PIPE_CONF_CHECK_I(cpu_transcoder);
5205         PIPE_CONF_CHECK_I(mst_master_transcoder);
5206
5207         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5208         PIPE_CONF_CHECK_I(fdi_lanes);
5209         PIPE_CONF_CHECK_M_N(fdi_m_n);
5210
5211         PIPE_CONF_CHECK_I(lane_count);
5212         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5213
5214         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5215                 if (!fastset || !pipe_config->seamless_m_n)
5216                         PIPE_CONF_CHECK_M_N(dp_m_n);
5217         } else {
5218                 PIPE_CONF_CHECK_M_N(dp_m_n);
5219                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5220         }
5221
5222         PIPE_CONF_CHECK_X(output_types);
5223
5224         PIPE_CONF_CHECK_I(framestart_delay);
5225         PIPE_CONF_CHECK_I(msa_timing_delay);
5226
5227         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5228         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5229
5230         PIPE_CONF_CHECK_I(pixel_multiplier);
5231
5232         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5233                               DRM_MODE_FLAG_INTERLACE);
5234
5235         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5236                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5237                                       DRM_MODE_FLAG_PHSYNC);
5238                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5239                                       DRM_MODE_FLAG_NHSYNC);
5240                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5241                                       DRM_MODE_FLAG_PVSYNC);
5242                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5243                                       DRM_MODE_FLAG_NVSYNC);
5244         }
5245
5246         PIPE_CONF_CHECK_I(output_format);
5247         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5248         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5249             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5250                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5251
5252         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5253         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5254         PIPE_CONF_CHECK_BOOL(has_infoframe);
5255         PIPE_CONF_CHECK_BOOL(fec_enable);
5256
5257         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5258         PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5259
5260         PIPE_CONF_CHECK_X(gmch_pfit.control);
5261         /* pfit ratios are autocomputed by the hw on gen4+ */
5262         if (DISPLAY_VER(dev_priv) < 4)
5263                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5264         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5265
5266         /*
5267          * Changing the EDP transcoder input mux
5268          * (A_ONOFF vs. A_ON) requires a full modeset.
5269          */
5270         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5271
5272         if (!fastset) {
5273                 PIPE_CONF_CHECK_RECT(pipe_src);
5274
5275                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5276                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5277
5278                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5279                 PIPE_CONF_CHECK_I(pixel_rate);
5280
5281                 PIPE_CONF_CHECK_X(gamma_mode);
5282                 if (IS_CHERRYVIEW(dev_priv))
5283                         PIPE_CONF_CHECK_X(cgm_mode);
5284                 else
5285                         PIPE_CONF_CHECK_X(csc_mode);
5286                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5287                 PIPE_CONF_CHECK_BOOL(csc_enable);
5288                 PIPE_CONF_CHECK_BOOL(wgc_enable);
5289
5290                 PIPE_CONF_CHECK_I(linetime);
5291                 PIPE_CONF_CHECK_I(ips_linetime);
5292
5293                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5294                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5295
5296                 PIPE_CONF_CHECK_CSC(csc);
5297                 PIPE_CONF_CHECK_CSC(output_csc);
5298
5299                 if (current_config->active_planes) {
5300                         PIPE_CONF_CHECK_BOOL(has_psr);
5301                         PIPE_CONF_CHECK_BOOL(has_psr2);
5302                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5303                         PIPE_CONF_CHECK_I(dc3co_exitline);
5304                 }
5305         }
5306
5307         PIPE_CONF_CHECK_BOOL(double_wide);
5308
5309         if (dev_priv->display.dpll.mgr) {
5310                 PIPE_CONF_CHECK_P(shared_dpll);
5311
5312                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5313                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5314                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5315                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5316                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5317                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5318                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5319                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5320                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5321                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5322                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5323                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5324                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5325                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5326                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5327                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5328                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5329                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5330                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5331                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5332                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5333                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5334                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5335                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5336                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5337                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5338                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5339                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5340                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5341                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5342                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5343                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5344         }
5345
5346         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5347         PIPE_CONF_CHECK_X(dsi_pll.div);
5348
5349         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5350                 PIPE_CONF_CHECK_I(pipe_bpp);
5351
5352         if (!fastset || !pipe_config->seamless_m_n) {
5353                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5354                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5355         }
5356         PIPE_CONF_CHECK_I(port_clock);
5357
5358         PIPE_CONF_CHECK_I(min_voltage_level);
5359
5360         if (current_config->has_psr || pipe_config->has_psr)
5361                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5362                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5363         else
5364                 PIPE_CONF_CHECK_X(infoframes.enable);
5365
5366         PIPE_CONF_CHECK_X(infoframes.gcp);
5367         PIPE_CONF_CHECK_INFOFRAME(avi);
5368         PIPE_CONF_CHECK_INFOFRAME(spd);
5369         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5370         PIPE_CONF_CHECK_INFOFRAME(drm);
5371         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5372
5373         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5374         PIPE_CONF_CHECK_I(master_transcoder);
5375         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5376
5377         PIPE_CONF_CHECK_I(dsc.compression_enable);
5378         PIPE_CONF_CHECK_I(dsc.dsc_split);
5379         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5380
5381         PIPE_CONF_CHECK_BOOL(splitter.enable);
5382         PIPE_CONF_CHECK_I(splitter.link_count);
5383         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5384
5385         if (!fastset)
5386                 PIPE_CONF_CHECK_BOOL(vrr.enable);
5387         PIPE_CONF_CHECK_I(vrr.vmin);
5388         PIPE_CONF_CHECK_I(vrr.vmax);
5389         PIPE_CONF_CHECK_I(vrr.flipline);
5390         PIPE_CONF_CHECK_I(vrr.pipeline_full);
5391         PIPE_CONF_CHECK_I(vrr.guardband);
5392
5393 #undef PIPE_CONF_CHECK_X
5394 #undef PIPE_CONF_CHECK_I
5395 #undef PIPE_CONF_CHECK_BOOL
5396 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5397 #undef PIPE_CONF_CHECK_P
5398 #undef PIPE_CONF_CHECK_FLAGS
5399 #undef PIPE_CONF_CHECK_COLOR_LUT
5400 #undef PIPE_CONF_CHECK_TIMINGS
5401 #undef PIPE_CONF_CHECK_RECT
5402 #undef PIPE_CONF_QUIRK
5403
5404         return ret;
5405 }
5406
5407 static void
5408 intel_verify_planes(struct intel_atomic_state *state)
5409 {
5410         struct intel_plane *plane;
5411         const struct intel_plane_state *plane_state;
5412         int i;
5413
5414         for_each_new_intel_plane_in_state(state, plane,
5415                                           plane_state, i)
5416                 assert_plane(plane, plane_state->planar_slave ||
5417                              plane_state->uapi.visible);
5418 }
5419
5420 int intel_modeset_all_pipes(struct intel_atomic_state *state,
5421                             const char *reason)
5422 {
5423         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5424         struct intel_crtc *crtc;
5425
5426         /*
5427          * Add all pipes to the state, and force
5428          * a modeset on all the active ones.
5429          */
5430         for_each_intel_crtc(&dev_priv->drm, crtc) {
5431                 struct intel_crtc_state *crtc_state;
5432                 int ret;
5433
5434                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5435                 if (IS_ERR(crtc_state))
5436                         return PTR_ERR(crtc_state);
5437
5438                 if (!crtc_state->hw.active ||
5439                     intel_crtc_needs_modeset(crtc_state))
5440                         continue;
5441
5442                 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5443                             crtc->base.base.id, crtc->base.name, reason);
5444
5445                 crtc_state->uapi.mode_changed = true;
5446                 crtc_state->update_pipe = false;
5447
5448                 ret = drm_atomic_add_affected_connectors(&state->base,
5449                                                          &crtc->base);
5450                 if (ret)
5451                         return ret;
5452
5453                 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5454                 if (ret)
5455                         return ret;
5456
5457                 ret = intel_atomic_add_affected_planes(state, crtc);
5458                 if (ret)
5459                         return ret;
5460
5461                 crtc_state->update_planes |= crtc_state->active_planes;
5462                 crtc_state->async_flip_planes = 0;
5463                 crtc_state->do_async_flip = false;
5464         }
5465
5466         return 0;
5467 }
5468
5469 /*
5470  * This implements the workaround described in the "notes" section of the mode
5471  * set sequence documentation. When going from no pipes or single pipe to
5472  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5473  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5474  */
5475 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5476 {
5477         struct intel_crtc_state *crtc_state;
5478         struct intel_crtc *crtc;
5479         struct intel_crtc_state *first_crtc_state = NULL;
5480         struct intel_crtc_state *other_crtc_state = NULL;
5481         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5482         int i;
5483
5484         /* look at all crtc's that are going to be enabled in during modeset */
5485         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5486                 if (!crtc_state->hw.active ||
5487                     !intel_crtc_needs_modeset(crtc_state))
5488                         continue;
5489
5490                 if (first_crtc_state) {
5491                         other_crtc_state = crtc_state;
5492                         break;
5493                 } else {
5494                         first_crtc_state = crtc_state;
5495                         first_pipe = crtc->pipe;
5496                 }
5497         }
5498
5499         /* No workaround needed? */
5500         if (!first_crtc_state)
5501                 return 0;
5502
5503         /* w/a possibly needed, check how many crtc's are already enabled. */
5504         for_each_intel_crtc(state->base.dev, crtc) {
5505                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5506                 if (IS_ERR(crtc_state))
5507                         return PTR_ERR(crtc_state);
5508
5509                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5510
5511                 if (!crtc_state->hw.active ||
5512                     intel_crtc_needs_modeset(crtc_state))
5513                         continue;
5514
5515                 /* 2 or more enabled crtcs means no need for w/a */
5516                 if (enabled_pipe != INVALID_PIPE)
5517                         return 0;
5518
5519                 enabled_pipe = crtc->pipe;
5520         }
5521
5522         if (enabled_pipe != INVALID_PIPE)
5523                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5524         else if (other_crtc_state)
5525                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5526
5527         return 0;
5528 }
5529
5530 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5531                            u8 active_pipes)
5532 {
5533         const struct intel_crtc_state *crtc_state;
5534         struct intel_crtc *crtc;
5535         int i;
5536
5537         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5538                 if (crtc_state->hw.active)
5539                         active_pipes |= BIT(crtc->pipe);
5540                 else
5541                         active_pipes &= ~BIT(crtc->pipe);
5542         }
5543
5544         return active_pipes;
5545 }
5546
5547 static int intel_modeset_checks(struct intel_atomic_state *state)
5548 {
5549         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5550
5551         state->modeset = true;
5552
5553         if (IS_HASWELL(dev_priv))
5554                 return hsw_mode_set_planes_workaround(state);
5555
5556         return 0;
5557 }
5558
5559 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5560                                      struct intel_crtc_state *new_crtc_state)
5561 {
5562         struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
5563
5564         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
5565                 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
5566
5567                 return;
5568         }
5569
5570         new_crtc_state->uapi.mode_changed = false;
5571         if (!intel_crtc_needs_modeset(new_crtc_state))
5572                 new_crtc_state->update_pipe = true;
5573 }
5574
5575 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5576                                           struct intel_crtc *crtc,
5577                                           u8 plane_ids_mask)
5578 {
5579         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5580         struct intel_plane *plane;
5581
5582         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5583                 struct intel_plane_state *plane_state;
5584
5585                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5586                         continue;
5587
5588                 plane_state = intel_atomic_get_plane_state(state, plane);
5589                 if (IS_ERR(plane_state))
5590                         return PTR_ERR(plane_state);
5591         }
5592
5593         return 0;
5594 }
5595
5596 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5597                                      struct intel_crtc *crtc)
5598 {
5599         const struct intel_crtc_state *old_crtc_state =
5600                 intel_atomic_get_old_crtc_state(state, crtc);
5601         const struct intel_crtc_state *new_crtc_state =
5602                 intel_atomic_get_new_crtc_state(state, crtc);
5603
5604         return intel_crtc_add_planes_to_state(state, crtc,
5605                                               old_crtc_state->enabled_planes |
5606                                               new_crtc_state->enabled_planes);
5607 }
5608
5609 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5610 {
5611         /* See {hsw,vlv,ivb}_plane_ratio() */
5612         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5613                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5614                 IS_IVYBRIDGE(dev_priv);
5615 }
5616
5617 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5618                                            struct intel_crtc *crtc,
5619                                            struct intel_crtc *other)
5620 {
5621         const struct intel_plane_state __maybe_unused *plane_state;
5622         struct intel_plane *plane;
5623         u8 plane_ids = 0;
5624         int i;
5625
5626         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5627                 if (plane->pipe == crtc->pipe)
5628                         plane_ids |= BIT(plane->id);
5629         }
5630
5631         return intel_crtc_add_planes_to_state(state, other, plane_ids);
5632 }
5633
5634 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
5635 {
5636         struct drm_i915_private *i915 = to_i915(state->base.dev);
5637         const struct intel_crtc_state *crtc_state;
5638         struct intel_crtc *crtc;
5639         int i;
5640
5641         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5642                 struct intel_crtc *other;
5643
5644                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5645                                                  crtc_state->bigjoiner_pipes) {
5646                         int ret;
5647
5648                         if (crtc == other)
5649                                 continue;
5650
5651                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
5652                         if (ret)
5653                                 return ret;
5654                 }
5655         }
5656
5657         return 0;
5658 }
5659
5660 static int intel_atomic_check_planes(struct intel_atomic_state *state)
5661 {
5662         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5663         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5664         struct intel_plane_state __maybe_unused *plane_state;
5665         struct intel_plane *plane;
5666         struct intel_crtc *crtc;
5667         int i, ret;
5668
5669         ret = icl_add_linked_planes(state);
5670         if (ret)
5671                 return ret;
5672
5673         ret = intel_bigjoiner_add_affected_planes(state);
5674         if (ret)
5675                 return ret;
5676
5677         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5678                 ret = intel_plane_atomic_check(state, plane);
5679                 if (ret) {
5680                         drm_dbg_atomic(&dev_priv->drm,
5681                                        "[PLANE:%d:%s] atomic driver check failed\n",
5682                                        plane->base.base.id, plane->base.name);
5683                         return ret;
5684                 }
5685         }
5686
5687         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5688                                             new_crtc_state, i) {
5689                 u8 old_active_planes, new_active_planes;
5690
5691                 ret = icl_check_nv12_planes(new_crtc_state);
5692                 if (ret)
5693                         return ret;
5694
5695                 /*
5696                  * On some platforms the number of active planes affects
5697                  * the planes' minimum cdclk calculation. Add such planes
5698                  * to the state before we compute the minimum cdclk.
5699                  */
5700                 if (!active_planes_affects_min_cdclk(dev_priv))
5701                         continue;
5702
5703                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5704                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5705
5706                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
5707                         continue;
5708
5709                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
5710                 if (ret)
5711                         return ret;
5712         }
5713
5714         return 0;
5715 }
5716
5717 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5718 {
5719         struct intel_crtc_state __maybe_unused *crtc_state;
5720         struct intel_crtc *crtc;
5721         int i;
5722
5723         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5724                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5725                 int ret;
5726
5727                 ret = intel_crtc_atomic_check(state, crtc);
5728                 if (ret) {
5729                         drm_dbg_atomic(&i915->drm,
5730                                        "[CRTC:%d:%s] atomic driver check failed\n",
5731                                        crtc->base.base.id, crtc->base.name);
5732                         return ret;
5733                 }
5734         }
5735
5736         return 0;
5737 }
5738
5739 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5740                                                u8 transcoders)
5741 {
5742         const struct intel_crtc_state *new_crtc_state;
5743         struct intel_crtc *crtc;
5744         int i;
5745
5746         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5747                 if (new_crtc_state->hw.enable &&
5748                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5749                     intel_crtc_needs_modeset(new_crtc_state))
5750                         return true;
5751         }
5752
5753         return false;
5754 }
5755
5756 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5757                                      u8 pipes)
5758 {
5759         const struct intel_crtc_state *new_crtc_state;
5760         struct intel_crtc *crtc;
5761         int i;
5762
5763         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5764                 if (new_crtc_state->hw.enable &&
5765                     pipes & BIT(crtc->pipe) &&
5766                     intel_crtc_needs_modeset(new_crtc_state))
5767                         return true;
5768         }
5769
5770         return false;
5771 }
5772
5773 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
5774                                         struct intel_crtc *master_crtc)
5775 {
5776         struct drm_i915_private *i915 = to_i915(state->base.dev);
5777         struct intel_crtc_state *master_crtc_state =
5778                 intel_atomic_get_new_crtc_state(state, master_crtc);
5779         struct intel_crtc *slave_crtc;
5780
5781         if (!master_crtc_state->bigjoiner_pipes)
5782                 return 0;
5783
5784         /* sanity check */
5785         if (drm_WARN_ON(&i915->drm,
5786                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
5787                 return -EINVAL;
5788
5789         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
5790                 drm_dbg_kms(&i915->drm,
5791                             "[CRTC:%d:%s] Cannot act as big joiner master "
5792                             "(need 0x%x as pipes, only 0x%x possible)\n",
5793                             master_crtc->base.base.id, master_crtc->base.name,
5794                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
5795                 return -EINVAL;
5796         }
5797
5798         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5799                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5800                 struct intel_crtc_state *slave_crtc_state;
5801                 int ret;
5802
5803                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
5804                 if (IS_ERR(slave_crtc_state))
5805                         return PTR_ERR(slave_crtc_state);
5806
5807                 /* master being enabled, slave was already configured? */
5808                 if (slave_crtc_state->uapi.enable) {
5809                         drm_dbg_kms(&i915->drm,
5810                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5811                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5812                                     slave_crtc->base.base.id, slave_crtc->base.name,
5813                                     master_crtc->base.base.id, master_crtc->base.name);
5814                         return -EINVAL;
5815                 }
5816
5817                 /*
5818                  * The state copy logic assumes the master crtc gets processed
5819                  * before the slave crtc during the main compute_config loop.
5820                  * This works because the crtcs are created in pipe order,
5821                  * and the hardware requires master pipe < slave pipe as well.
5822                  * Should that change we need to rethink the logic.
5823                  */
5824                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
5825                             drm_crtc_index(&slave_crtc->base)))
5826                         return -EINVAL;
5827
5828                 drm_dbg_kms(&i915->drm,
5829                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5830                             slave_crtc->base.base.id, slave_crtc->base.name,
5831                             master_crtc->base.base.id, master_crtc->base.name);
5832
5833                 slave_crtc_state->bigjoiner_pipes =
5834                         master_crtc_state->bigjoiner_pipes;
5835
5836                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
5837                 if (ret)
5838                         return ret;
5839         }
5840
5841         return 0;
5842 }
5843
5844 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
5845                                  struct intel_crtc *master_crtc)
5846 {
5847         struct drm_i915_private *i915 = to_i915(state->base.dev);
5848         struct intel_crtc_state *master_crtc_state =
5849                 intel_atomic_get_new_crtc_state(state, master_crtc);
5850         struct intel_crtc *slave_crtc;
5851
5852         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5853                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5854                 struct intel_crtc_state *slave_crtc_state =
5855                         intel_atomic_get_new_crtc_state(state, slave_crtc);
5856
5857                 slave_crtc_state->bigjoiner_pipes = 0;
5858
5859                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
5860         }
5861
5862         master_crtc_state->bigjoiner_pipes = 0;
5863 }
5864
5865 /**
5866  * DOC: asynchronous flip implementation
5867  *
5868  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5869  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5870  * Correspondingly, support is currently added for primary plane only.
5871  *
5872  * Async flip can only change the plane surface address, so anything else
5873  * changing is rejected from the intel_async_flip_check_hw() function.
5874  * Once this check is cleared, flip done interrupt is enabled using
5875  * the intel_crtc_enable_flip_done() function.
5876  *
5877  * As soon as the surface address register is written, flip done interrupt is
5878  * generated and the requested events are sent to the usersapce in the interrupt
5879  * handler itself. The timestamp and sequence sent during the flip done event
5880  * correspond to the last vblank and have no relation to the actual time when
5881  * the flip done event was sent.
5882  */
5883 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5884                                        struct intel_crtc *crtc)
5885 {
5886         struct drm_i915_private *i915 = to_i915(state->base.dev);
5887         const struct intel_crtc_state *new_crtc_state =
5888                 intel_atomic_get_new_crtc_state(state, crtc);
5889         const struct intel_plane_state *old_plane_state;
5890         struct intel_plane_state *new_plane_state;
5891         struct intel_plane *plane;
5892         int i;
5893
5894         if (!new_crtc_state->uapi.async_flip)
5895                 return 0;
5896
5897         if (!new_crtc_state->uapi.active) {
5898                 drm_dbg_kms(&i915->drm,
5899                             "[CRTC:%d:%s] not active\n",
5900                             crtc->base.base.id, crtc->base.name);
5901                 return -EINVAL;
5902         }
5903
5904         if (intel_crtc_needs_modeset(new_crtc_state)) {
5905                 drm_dbg_kms(&i915->drm,
5906                             "[CRTC:%d:%s] modeset required\n",
5907                             crtc->base.base.id, crtc->base.name);
5908                 return -EINVAL;
5909         }
5910
5911         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5912                                              new_plane_state, i) {
5913                 if (plane->pipe != crtc->pipe)
5914                         continue;
5915
5916                 /*
5917                  * TODO: Async flip is only supported through the page flip IOCTL
5918                  * as of now. So support currently added for primary plane only.
5919                  * Support for other planes on platforms on which supports
5920                  * this(vlv/chv and icl+) should be added when async flip is
5921                  * enabled in the atomic IOCTL path.
5922                  */
5923                 if (!plane->async_flip) {
5924                         drm_dbg_kms(&i915->drm,
5925                                     "[PLANE:%d:%s] async flip not supported\n",
5926                                     plane->base.base.id, plane->base.name);
5927                         return -EINVAL;
5928                 }
5929
5930                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
5931                         drm_dbg_kms(&i915->drm,
5932                                     "[PLANE:%d:%s] no old or new framebuffer\n",
5933                                     plane->base.base.id, plane->base.name);
5934                         return -EINVAL;
5935                 }
5936         }
5937
5938         return 0;
5939 }
5940
5941 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
5942 {
5943         struct drm_i915_private *i915 = to_i915(state->base.dev);
5944         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5945         const struct intel_plane_state *new_plane_state, *old_plane_state;
5946         struct intel_plane *plane;
5947         int i;
5948
5949         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5950         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5951
5952         if (!new_crtc_state->uapi.async_flip)
5953                 return 0;
5954
5955         if (!new_crtc_state->hw.active) {
5956                 drm_dbg_kms(&i915->drm,
5957                             "[CRTC:%d:%s] not active\n",
5958                             crtc->base.base.id, crtc->base.name);
5959                 return -EINVAL;
5960         }
5961
5962         if (intel_crtc_needs_modeset(new_crtc_state)) {
5963                 drm_dbg_kms(&i915->drm,
5964                             "[CRTC:%d:%s] modeset required\n",
5965                             crtc->base.base.id, crtc->base.name);
5966                 return -EINVAL;
5967         }
5968
5969         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
5970                 drm_dbg_kms(&i915->drm,
5971                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
5972                             crtc->base.base.id, crtc->base.name);
5973                 return -EINVAL;
5974         }
5975
5976         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5977                                              new_plane_state, i) {
5978                 if (plane->pipe != crtc->pipe)
5979                         continue;
5980
5981                 /*
5982                  * Only async flip capable planes should be in the state
5983                  * if we're really about to ask the hardware to perform
5984                  * an async flip. We should never get this far otherwise.
5985                  */
5986                 if (drm_WARN_ON(&i915->drm,
5987                                 new_crtc_state->do_async_flip && !plane->async_flip))
5988                         return -EINVAL;
5989
5990                 /*
5991                  * Only check async flip capable planes other planes
5992                  * may be involved in the initial commit due to
5993                  * the wm0/ddb optimization.
5994                  *
5995                  * TODO maybe should track which planes actually
5996                  * were requested to do the async flip...
5997                  */
5998                 if (!plane->async_flip)
5999                         continue;
6000
6001                 /*
6002                  * FIXME: This check is kept generic for all platforms.
6003                  * Need to verify this for all gen9 platforms to enable
6004                  * this selectively if required.
6005                  */
6006                 switch (new_plane_state->hw.fb->modifier) {
6007                 case DRM_FORMAT_MOD_LINEAR:
6008                         /*
6009                          * FIXME: Async on Linear buffer is supported on ICL as
6010                          * but with additional alignment and fbc restrictions
6011                          * need to be taken care of. These aren't applicable for
6012                          * gen12+.
6013                          */
6014                         if (DISPLAY_VER(i915) < 12) {
6015                                 drm_dbg_kms(&i915->drm,
6016                                             "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6017                                             plane->base.base.id, plane->base.name,
6018                                             new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
6019                                 return -EINVAL;
6020                         }
6021                         break;
6022
6023                 case I915_FORMAT_MOD_X_TILED:
6024                 case I915_FORMAT_MOD_Y_TILED:
6025                 case I915_FORMAT_MOD_Yf_TILED:
6026                 case I915_FORMAT_MOD_4_TILED:
6027                         break;
6028                 default:
6029                         drm_dbg_kms(&i915->drm,
6030                                     "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6031                                     plane->base.base.id, plane->base.name,
6032                                     new_plane_state->hw.fb->modifier);
6033                         return -EINVAL;
6034                 }
6035
6036                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6037                         drm_dbg_kms(&i915->drm,
6038                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6039                                     plane->base.base.id, plane->base.name);
6040                         return -EINVAL;
6041                 }
6042
6043                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6044                     new_plane_state->view.color_plane[0].mapping_stride) {
6045                         drm_dbg_kms(&i915->drm,
6046                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6047                                     plane->base.base.id, plane->base.name);
6048                         return -EINVAL;
6049                 }
6050
6051                 if (old_plane_state->hw.fb->modifier !=
6052                     new_plane_state->hw.fb->modifier) {
6053                         drm_dbg_kms(&i915->drm,
6054                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6055                                     plane->base.base.id, plane->base.name);
6056                         return -EINVAL;
6057                 }
6058
6059                 if (old_plane_state->hw.fb->format !=
6060                     new_plane_state->hw.fb->format) {
6061                         drm_dbg_kms(&i915->drm,
6062                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6063                                     plane->base.base.id, plane->base.name);
6064                         return -EINVAL;
6065                 }
6066
6067                 if (old_plane_state->hw.rotation !=
6068                     new_plane_state->hw.rotation) {
6069                         drm_dbg_kms(&i915->drm,
6070                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6071                                     plane->base.base.id, plane->base.name);
6072                         return -EINVAL;
6073                 }
6074
6075                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6076                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6077                         drm_dbg_kms(&i915->drm,
6078                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6079                                     plane->base.base.id, plane->base.name);
6080                         return -EINVAL;
6081                 }
6082
6083                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6084                         drm_dbg_kms(&i915->drm,
6085                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6086                                     plane->base.base.id, plane->base.name);
6087                         return -EINVAL;
6088                 }
6089
6090                 if (old_plane_state->hw.pixel_blend_mode !=
6091                     new_plane_state->hw.pixel_blend_mode) {
6092                         drm_dbg_kms(&i915->drm,
6093                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6094                                     plane->base.base.id, plane->base.name);
6095                         return -EINVAL;
6096                 }
6097
6098                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6099                         drm_dbg_kms(&i915->drm,
6100                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6101                                     plane->base.base.id, plane->base.name);
6102                         return -EINVAL;
6103                 }
6104
6105                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6106                         drm_dbg_kms(&i915->drm,
6107                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6108                                     plane->base.base.id, plane->base.name);
6109                         return -EINVAL;
6110                 }
6111
6112                 /* plane decryption is allow to change only in synchronous flips */
6113                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6114                         drm_dbg_kms(&i915->drm,
6115                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6116                                     plane->base.base.id, plane->base.name);
6117                         return -EINVAL;
6118                 }
6119         }
6120
6121         return 0;
6122 }
6123
6124 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6125 {
6126         struct drm_i915_private *i915 = to_i915(state->base.dev);
6127         struct intel_crtc_state *crtc_state;
6128         struct intel_crtc *crtc;
6129         u8 affected_pipes = 0;
6130         u8 modeset_pipes = 0;
6131         int i;
6132
6133         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6134                 affected_pipes |= crtc_state->bigjoiner_pipes;
6135                 if (intel_crtc_needs_modeset(crtc_state))
6136                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6137         }
6138
6139         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6140                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6141                 if (IS_ERR(crtc_state))
6142                         return PTR_ERR(crtc_state);
6143         }
6144
6145         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6146                 int ret;
6147
6148                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6149
6150                 crtc_state->uapi.mode_changed = true;
6151
6152                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6153                 if (ret)
6154                         return ret;
6155
6156                 ret = intel_atomic_add_affected_planes(state, crtc);
6157                 if (ret)
6158                         return ret;
6159         }
6160
6161         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6162                 /* Kill old bigjoiner link, we may re-establish afterwards */
6163                 if (intel_crtc_needs_modeset(crtc_state) &&
6164                     intel_crtc_is_bigjoiner_master(crtc_state))
6165                         kill_bigjoiner_slave(state, crtc);
6166         }
6167
6168         return 0;
6169 }
6170
6171 /**
6172  * intel_atomic_check - validate state object
6173  * @dev: drm device
6174  * @_state: state to validate
6175  */
6176 int intel_atomic_check(struct drm_device *dev,
6177                        struct drm_atomic_state *_state)
6178 {
6179         struct drm_i915_private *dev_priv = to_i915(dev);
6180         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6181         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6182         struct intel_crtc *crtc;
6183         int ret, i;
6184         bool any_ms = false;
6185
6186         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6187                                             new_crtc_state, i) {
6188                 /*
6189                  * crtc's state no longer considered to be inherited
6190                  * after the first userspace/client initiated commit.
6191                  */
6192                 if (!state->internal)
6193                         new_crtc_state->inherited = false;
6194
6195                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6196                         new_crtc_state->uapi.mode_changed = true;
6197
6198                 if (new_crtc_state->uapi.scaling_filter !=
6199                     old_crtc_state->uapi.scaling_filter)
6200                         new_crtc_state->uapi.mode_changed = true;
6201         }
6202
6203         intel_vrr_check_modeset(state);
6204
6205         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6206         if (ret)
6207                 goto fail;
6208
6209         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6210                 ret = intel_async_flip_check_uapi(state, crtc);
6211                 if (ret)
6212                         return ret;
6213         }
6214
6215         ret = intel_bigjoiner_add_affected_crtcs(state);
6216         if (ret)
6217                 goto fail;
6218
6219         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6220                                             new_crtc_state, i) {
6221                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6222                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6223                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6224                         else
6225                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6226                         continue;
6227                 }
6228
6229                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6230                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6231                         continue;
6232                 }
6233
6234                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6235                 if (ret)
6236                         goto fail;
6237
6238                 if (!new_crtc_state->hw.enable)
6239                         continue;
6240
6241                 ret = intel_modeset_pipe_config(state, crtc);
6242                 if (ret)
6243                         goto fail;
6244
6245                 ret = intel_atomic_check_bigjoiner(state, crtc);
6246                 if (ret)
6247                         goto fail;
6248         }
6249
6250         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6251                                             new_crtc_state, i) {
6252                 if (!intel_crtc_needs_modeset(new_crtc_state))
6253                         continue;
6254
6255                 if (new_crtc_state->hw.enable) {
6256                         ret = intel_modeset_pipe_config_late(state, crtc);
6257                         if (ret)
6258                                 goto fail;
6259                 }
6260
6261                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6262         }
6263
6264         /**
6265          * Check if fastset is allowed by external dependencies like other
6266          * pipes and transcoders.
6267          *
6268          * Right now it only forces a fullmodeset when the MST master
6269          * transcoder did not changed but the pipe of the master transcoder
6270          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6271          * in case of port synced crtcs, if one of the synced crtcs
6272          * needs a full modeset, all other synced crtcs should be
6273          * forced a full modeset.
6274          */
6275         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6276                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6277                         continue;
6278
6279                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6280                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6281
6282                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6283                                 new_crtc_state->uapi.mode_changed = true;
6284                                 new_crtc_state->update_pipe = false;
6285                         }
6286                 }
6287
6288                 if (is_trans_port_sync_mode(new_crtc_state)) {
6289                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6290
6291                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6292                                 trans |= BIT(new_crtc_state->master_transcoder);
6293
6294                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6295                                 new_crtc_state->uapi.mode_changed = true;
6296                                 new_crtc_state->update_pipe = false;
6297                         }
6298                 }
6299
6300                 if (new_crtc_state->bigjoiner_pipes) {
6301                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6302                                 new_crtc_state->uapi.mode_changed = true;
6303                                 new_crtc_state->update_pipe = false;
6304                         }
6305                 }
6306         }
6307
6308         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6309                                             new_crtc_state, i) {
6310                 if (!intel_crtc_needs_modeset(new_crtc_state))
6311                         continue;
6312
6313                 any_ms = true;
6314
6315                 intel_release_shared_dplls(state, crtc);
6316         }
6317
6318         if (any_ms && !check_digital_port_conflicts(state)) {
6319                 drm_dbg_kms(&dev_priv->drm,
6320                             "rejecting conflicting digital port configuration\n");
6321                 ret = -EINVAL;
6322                 goto fail;
6323         }
6324
6325         ret = drm_dp_mst_atomic_check(&state->base);
6326         if (ret)
6327                 goto fail;
6328
6329         ret = intel_atomic_check_planes(state);
6330         if (ret)
6331                 goto fail;
6332
6333         ret = intel_compute_global_watermarks(state);
6334         if (ret)
6335                 goto fail;
6336
6337         ret = intel_bw_atomic_check(state);
6338         if (ret)
6339                 goto fail;
6340
6341         ret = intel_cdclk_atomic_check(state, &any_ms);
6342         if (ret)
6343                 goto fail;
6344
6345         if (intel_any_crtc_needs_modeset(state))
6346                 any_ms = true;
6347
6348         if (any_ms) {
6349                 ret = intel_modeset_checks(state);
6350                 if (ret)
6351                         goto fail;
6352
6353                 ret = intel_modeset_calc_cdclk(state);
6354                 if (ret)
6355                         return ret;
6356         }
6357
6358         ret = intel_pmdemand_atomic_check(state);
6359         if (ret)
6360                 goto fail;
6361
6362         ret = intel_atomic_check_crtcs(state);
6363         if (ret)
6364                 goto fail;
6365
6366         ret = intel_fbc_atomic_check(state);
6367         if (ret)
6368                 goto fail;
6369
6370         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6371                                             new_crtc_state, i) {
6372                 intel_color_assert_luts(new_crtc_state);
6373
6374                 ret = intel_async_flip_check_hw(state, crtc);
6375                 if (ret)
6376                         goto fail;
6377
6378                 /* Either full modeset or fastset (or neither), never both */
6379                 drm_WARN_ON(&dev_priv->drm,
6380                             intel_crtc_needs_modeset(new_crtc_state) &&
6381                             intel_crtc_needs_fastset(new_crtc_state));
6382
6383                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6384                     !intel_crtc_needs_fastset(new_crtc_state))
6385                         continue;
6386
6387                 intel_crtc_state_dump(new_crtc_state, state,
6388                                       intel_crtc_needs_modeset(new_crtc_state) ?
6389                                       "modeset" : "fastset");
6390         }
6391
6392         return 0;
6393
6394  fail:
6395         if (ret == -EDEADLK)
6396                 return ret;
6397
6398         /*
6399          * FIXME would probably be nice to know which crtc specifically
6400          * caused the failure, in cases where we can pinpoint it.
6401          */
6402         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6403                                             new_crtc_state, i)
6404                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6405
6406         return ret;
6407 }
6408
6409 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6410 {
6411         struct intel_crtc_state *crtc_state;
6412         struct intel_crtc *crtc;
6413         int i, ret;
6414
6415         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6416         if (ret < 0)
6417                 return ret;
6418
6419         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6420                 if (intel_crtc_needs_color_update(crtc_state))
6421                         intel_color_prepare_commit(crtc_state);
6422         }
6423
6424         return 0;
6425 }
6426
6427 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6428                                   struct intel_crtc_state *crtc_state)
6429 {
6430         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6431
6432         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6433                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6434
6435         if (crtc_state->has_pch_encoder) {
6436                 enum pipe pch_transcoder =
6437                         intel_crtc_pch_transcoder(crtc);
6438
6439                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6440         }
6441 }
6442
6443 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6444                                const struct intel_crtc_state *new_crtc_state)
6445 {
6446         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6447         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6448
6449         /*
6450          * Update pipe size and adjust fitter if needed: the reason for this is
6451          * that in compute_mode_changes we check the native mode (not the pfit
6452          * mode) to see if we can flip rather than do a full mode set. In the
6453          * fastboot case, we'll flip, but if we don't update the pipesrc and
6454          * pfit state, we'll end up with a big fb scanned out into the wrong
6455          * sized surface.
6456          */
6457         intel_set_pipe_src_size(new_crtc_state);
6458
6459         /* on skylake this is done by detaching scalers */
6460         if (DISPLAY_VER(dev_priv) >= 9) {
6461                 if (new_crtc_state->pch_pfit.enabled)
6462                         skl_pfit_enable(new_crtc_state);
6463         } else if (HAS_PCH_SPLIT(dev_priv)) {
6464                 if (new_crtc_state->pch_pfit.enabled)
6465                         ilk_pfit_enable(new_crtc_state);
6466                 else if (old_crtc_state->pch_pfit.enabled)
6467                         ilk_pfit_disable(old_crtc_state);
6468         }
6469
6470         /*
6471          * The register is supposedly single buffered so perhaps
6472          * not 100% correct to do this here. But SKL+ calculate
6473          * this based on the adjust pixel rate so pfit changes do
6474          * affect it and so it must be updated for fastsets.
6475          * HSW/BDW only really need this here for fastboot, after
6476          * that the value should not change without a full modeset.
6477          */
6478         if (DISPLAY_VER(dev_priv) >= 9 ||
6479             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6480                 hsw_set_linetime_wm(new_crtc_state);
6481
6482         if (new_crtc_state->seamless_m_n)
6483                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6484                                                &new_crtc_state->dp_m_n);
6485 }
6486
6487 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6488                                    struct intel_crtc *crtc)
6489 {
6490         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6491         const struct intel_crtc_state *old_crtc_state =
6492                 intel_atomic_get_old_crtc_state(state, crtc);
6493         const struct intel_crtc_state *new_crtc_state =
6494                 intel_atomic_get_new_crtc_state(state, crtc);
6495         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6496
6497         /*
6498          * During modesets pipe configuration was programmed as the
6499          * CRTC was enabled.
6500          */
6501         if (!modeset) {
6502                 if (intel_crtc_needs_color_update(new_crtc_state))
6503                         intel_color_commit_arm(new_crtc_state);
6504
6505                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6506                         bdw_set_pipe_misc(new_crtc_state);
6507
6508                 if (intel_crtc_needs_fastset(new_crtc_state))
6509                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6510         }
6511
6512         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6513
6514         intel_atomic_update_watermarks(state, crtc);
6515 }
6516
6517 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6518                                     struct intel_crtc *crtc)
6519 {
6520         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6521         const struct intel_crtc_state *new_crtc_state =
6522                 intel_atomic_get_new_crtc_state(state, crtc);
6523
6524         /*
6525          * Disable the scaler(s) after the plane(s) so that we don't
6526          * get a catastrophic underrun even if the two operations
6527          * end up happening in two different frames.
6528          */
6529         if (DISPLAY_VER(dev_priv) >= 9 &&
6530             !intel_crtc_needs_modeset(new_crtc_state))
6531                 skl_detach_scalers(new_crtc_state);
6532 }
6533
6534 static void intel_enable_crtc(struct intel_atomic_state *state,
6535                               struct intel_crtc *crtc)
6536 {
6537         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6538         const struct intel_crtc_state *new_crtc_state =
6539                 intel_atomic_get_new_crtc_state(state, crtc);
6540
6541         if (!intel_crtc_needs_modeset(new_crtc_state))
6542                 return;
6543
6544         /* VRR will be enable later, if required */
6545         intel_crtc_update_active_timings(new_crtc_state, false);
6546
6547         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6548
6549         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6550                 return;
6551
6552         /* vblanks work again, re-enable pipe CRC. */
6553         intel_crtc_enable_pipe_crc(crtc);
6554 }
6555
6556 static void intel_update_crtc(struct intel_atomic_state *state,
6557                               struct intel_crtc *crtc)
6558 {
6559         struct drm_i915_private *i915 = to_i915(state->base.dev);
6560         const struct intel_crtc_state *old_crtc_state =
6561                 intel_atomic_get_old_crtc_state(state, crtc);
6562         struct intel_crtc_state *new_crtc_state =
6563                 intel_atomic_get_new_crtc_state(state, crtc);
6564         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6565
6566         if (old_crtc_state->inherited ||
6567             intel_crtc_needs_modeset(new_crtc_state)) {
6568                 if (HAS_DPT(i915))
6569                         intel_dpt_configure(crtc);
6570         }
6571
6572         if (vrr_enabling(old_crtc_state, new_crtc_state)) {
6573                 intel_vrr_enable(new_crtc_state);
6574                 intel_crtc_update_active_timings(new_crtc_state,
6575                                                  new_crtc_state->vrr.enable);
6576         }
6577
6578         if (!modeset) {
6579                 if (new_crtc_state->preload_luts &&
6580                     intel_crtc_needs_color_update(new_crtc_state))
6581                         intel_color_load_luts(new_crtc_state);
6582
6583                 intel_pre_plane_update(state, crtc);
6584
6585                 if (intel_crtc_needs_fastset(new_crtc_state))
6586                         intel_encoders_update_pipe(state, crtc);
6587
6588                 if (DISPLAY_VER(i915) >= 11 &&
6589                     intel_crtc_needs_fastset(new_crtc_state))
6590                         icl_set_pipe_chicken(new_crtc_state);
6591         }
6592
6593         intel_fbc_update(state, crtc);
6594
6595         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6596
6597         if (!modeset &&
6598             intel_crtc_needs_color_update(new_crtc_state))
6599                 intel_color_commit_noarm(new_crtc_state);
6600
6601         intel_crtc_planes_update_noarm(state, crtc);
6602
6603         /* Perform vblank evasion around commit operation */
6604         intel_pipe_update_start(new_crtc_state);
6605
6606         commit_pipe_pre_planes(state, crtc);
6607
6608         intel_crtc_planes_update_arm(state, crtc);
6609
6610         commit_pipe_post_planes(state, crtc);
6611
6612         intel_pipe_update_end(new_crtc_state);
6613
6614         /*
6615          * We usually enable FIFO underrun interrupts as part of the
6616          * CRTC enable sequence during modesets.  But when we inherit a
6617          * valid pipe configuration from the BIOS we need to take care
6618          * of enabling them on the CRTC's first fastset.
6619          */
6620         if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
6621             old_crtc_state->inherited)
6622                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6623 }
6624
6625 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6626                                           struct intel_crtc_state *old_crtc_state,
6627                                           struct intel_crtc_state *new_crtc_state,
6628                                           struct intel_crtc *crtc)
6629 {
6630         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6631
6632         /*
6633          * We need to disable pipe CRC before disabling the pipe,
6634          * or we race against vblank off.
6635          */
6636         intel_crtc_disable_pipe_crc(crtc);
6637
6638         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6639         crtc->active = false;
6640         intel_fbc_disable(crtc);
6641
6642         if (!new_crtc_state->hw.active)
6643                 intel_initial_watermarks(state, crtc);
6644 }
6645
6646 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6647 {
6648         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6649         struct intel_crtc *crtc;
6650         u32 handled = 0;
6651         int i;
6652
6653         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6654                                             new_crtc_state, i) {
6655                 if (!intel_crtc_needs_modeset(new_crtc_state))
6656                         continue;
6657
6658                 if (!old_crtc_state->hw.active)
6659                         continue;
6660
6661                 intel_pre_plane_update(state, crtc);
6662                 intel_crtc_disable_planes(state, crtc);
6663         }
6664
6665         /* Only disable port sync and MST slaves */
6666         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6667                                             new_crtc_state, i) {
6668                 if (!intel_crtc_needs_modeset(new_crtc_state))
6669                         continue;
6670
6671                 if (!old_crtc_state->hw.active)
6672                         continue;
6673
6674                 /* In case of Transcoder port Sync master slave CRTCs can be
6675                  * assigned in any order and we need to make sure that
6676                  * slave CRTCs are disabled first and then master CRTC since
6677                  * Slave vblanks are masked till Master Vblanks.
6678                  */
6679                 if (!is_trans_port_sync_slave(old_crtc_state) &&
6680                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
6681                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
6682                         continue;
6683
6684                 intel_old_crtc_state_disables(state, old_crtc_state,
6685                                               new_crtc_state, crtc);
6686                 handled |= BIT(crtc->pipe);
6687         }
6688
6689         /* Disable everything else left on */
6690         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6691                                             new_crtc_state, i) {
6692                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
6693                     (handled & BIT(crtc->pipe)))
6694                         continue;
6695
6696                 if (!old_crtc_state->hw.active)
6697                         continue;
6698
6699                 intel_old_crtc_state_disables(state, old_crtc_state,
6700                                               new_crtc_state, crtc);
6701         }
6702 }
6703
6704 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6705 {
6706         struct intel_crtc_state *new_crtc_state;
6707         struct intel_crtc *crtc;
6708         int i;
6709
6710         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6711                 if (!new_crtc_state->hw.active)
6712                         continue;
6713
6714                 intel_enable_crtc(state, crtc);
6715                 intel_update_crtc(state, crtc);
6716         }
6717 }
6718
6719 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6720 {
6721         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6722         struct intel_crtc *crtc;
6723         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6724         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6725         u8 update_pipes = 0, modeset_pipes = 0;
6726         int i;
6727
6728         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6729                 enum pipe pipe = crtc->pipe;
6730
6731                 if (!new_crtc_state->hw.active)
6732                         continue;
6733
6734                 /* ignore allocations for crtc's that have been turned off. */
6735                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6736                         entries[pipe] = old_crtc_state->wm.skl.ddb;
6737                         update_pipes |= BIT(pipe);
6738                 } else {
6739                         modeset_pipes |= BIT(pipe);
6740                 }
6741         }
6742
6743         /*
6744          * Whenever the number of active pipes changes, we need to make sure we
6745          * update the pipes in the right order so that their ddb allocations
6746          * never overlap with each other between CRTC updates. Otherwise we'll
6747          * cause pipe underruns and other bad stuff.
6748          *
6749          * So first lets enable all pipes that do not need a fullmodeset as
6750          * those don't have any external dependency.
6751          */
6752         while (update_pipes) {
6753                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6754                                                     new_crtc_state, i) {
6755                         enum pipe pipe = crtc->pipe;
6756
6757                         if ((update_pipes & BIT(pipe)) == 0)
6758                                 continue;
6759
6760                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6761                                                         entries, I915_MAX_PIPES, pipe))
6762                                 continue;
6763
6764                         entries[pipe] = new_crtc_state->wm.skl.ddb;
6765                         update_pipes &= ~BIT(pipe);
6766
6767                         intel_update_crtc(state, crtc);
6768
6769                         /*
6770                          * If this is an already active pipe, it's DDB changed,
6771                          * and this isn't the last pipe that needs updating
6772                          * then we need to wait for a vblank to pass for the
6773                          * new ddb allocation to take effect.
6774                          */
6775                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
6776                                                  &old_crtc_state->wm.skl.ddb) &&
6777                             (update_pipes | modeset_pipes))
6778                                 intel_crtc_wait_for_next_vblank(crtc);
6779                 }
6780         }
6781
6782         update_pipes = modeset_pipes;
6783
6784         /*
6785          * Enable all pipes that needs a modeset and do not depends on other
6786          * pipes
6787          */
6788         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6789                 enum pipe pipe = crtc->pipe;
6790
6791                 if ((modeset_pipes & BIT(pipe)) == 0)
6792                         continue;
6793
6794                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
6795                     is_trans_port_sync_master(new_crtc_state) ||
6796                     intel_crtc_is_bigjoiner_master(new_crtc_state))
6797                         continue;
6798
6799                 modeset_pipes &= ~BIT(pipe);
6800
6801                 intel_enable_crtc(state, crtc);
6802         }
6803
6804         /*
6805          * Then we enable all remaining pipes that depend on other
6806          * pipes: MST slaves and port sync masters, big joiner master
6807          */
6808         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6809                 enum pipe pipe = crtc->pipe;
6810
6811                 if ((modeset_pipes & BIT(pipe)) == 0)
6812                         continue;
6813
6814                 modeset_pipes &= ~BIT(pipe);
6815
6816                 intel_enable_crtc(state, crtc);
6817         }
6818
6819         /*
6820          * Finally we do the plane updates/etc. for all pipes that got enabled.
6821          */
6822         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6823                 enum pipe pipe = crtc->pipe;
6824
6825                 if ((update_pipes & BIT(pipe)) == 0)
6826                         continue;
6827
6828                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6829                                                                         entries, I915_MAX_PIPES, pipe));
6830
6831                 entries[pipe] = new_crtc_state->wm.skl.ddb;
6832                 update_pipes &= ~BIT(pipe);
6833
6834                 intel_update_crtc(state, crtc);
6835         }
6836
6837         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
6838         drm_WARN_ON(&dev_priv->drm, update_pipes);
6839 }
6840
6841 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
6842 {
6843         struct intel_atomic_state *state, *next;
6844         struct llist_node *freed;
6845
6846         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
6847         llist_for_each_entry_safe(state, next, freed, freed)
6848                 drm_atomic_state_put(&state->base);
6849 }
6850
6851 void intel_atomic_helper_free_state_worker(struct work_struct *work)
6852 {
6853         struct drm_i915_private *dev_priv =
6854                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
6855
6856         intel_atomic_helper_free_state(dev_priv);
6857 }
6858
6859 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
6860 {
6861         struct wait_queue_entry wait_fence, wait_reset;
6862         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
6863
6864         init_wait_entry(&wait_fence, 0);
6865         init_wait_entry(&wait_reset, 0);
6866         for (;;) {
6867                 prepare_to_wait(&intel_state->commit_ready.wait,
6868                                 &wait_fence, TASK_UNINTERRUPTIBLE);
6869                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
6870                                               I915_RESET_MODESET),
6871                                 &wait_reset, TASK_UNINTERRUPTIBLE);
6872
6873
6874                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
6875                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
6876                         break;
6877
6878                 schedule();
6879         }
6880         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
6881         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
6882                                   I915_RESET_MODESET),
6883                     &wait_reset);
6884 }
6885
6886 static void intel_atomic_cleanup_work(struct work_struct *work)
6887 {
6888         struct intel_atomic_state *state =
6889                 container_of(work, struct intel_atomic_state, base.commit_work);
6890         struct drm_i915_private *i915 = to_i915(state->base.dev);
6891         struct intel_crtc_state *old_crtc_state;
6892         struct intel_crtc *crtc;
6893         int i;
6894
6895         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
6896                 intel_color_cleanup_commit(old_crtc_state);
6897
6898         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
6899         drm_atomic_helper_commit_cleanup_done(&state->base);
6900         drm_atomic_state_put(&state->base);
6901
6902         intel_atomic_helper_free_state(i915);
6903 }
6904
6905 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
6906 {
6907         struct drm_i915_private *i915 = to_i915(state->base.dev);
6908         struct intel_plane *plane;
6909         struct intel_plane_state *plane_state;
6910         int i;
6911
6912         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6913                 struct drm_framebuffer *fb = plane_state->hw.fb;
6914                 int cc_plane;
6915                 int ret;
6916
6917                 if (!fb)
6918                         continue;
6919
6920                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
6921                 if (cc_plane < 0)
6922                         continue;
6923
6924                 /*
6925                  * The layout of the fast clear color value expected by HW
6926                  * (the DRM ABI requiring this value to be located in fb at
6927                  * offset 0 of cc plane, plane #2 previous generations or
6928                  * plane #1 for flat ccs):
6929                  * - 4 x 4 bytes per-channel value
6930                  *   (in surface type specific float/int format provided by the fb user)
6931                  * - 8 bytes native color value used by the display
6932                  *   (converted/written by GPU during a fast clear operation using the
6933                  *    above per-channel values)
6934                  *
6935                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
6936                  * caller made sure that the object is synced wrt. the related color clear value
6937                  * GPU write on it.
6938                  */
6939                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
6940                                                      fb->offsets[cc_plane] + 16,
6941                                                      &plane_state->ccval,
6942                                                      sizeof(plane_state->ccval));
6943                 /* The above could only fail if the FB obj has an unexpected backing store type. */
6944                 drm_WARN_ON(&i915->drm, ret);
6945         }
6946 }
6947
6948 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
6949 {
6950         struct drm_device *dev = state->base.dev;
6951         struct drm_i915_private *dev_priv = to_i915(dev);
6952         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6953         struct intel_crtc *crtc;
6954         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
6955         intel_wakeref_t wakeref = 0;
6956         int i;
6957
6958         intel_atomic_commit_fence_wait(state);
6959
6960         drm_atomic_helper_wait_for_dependencies(&state->base);
6961         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
6962
6963         /*
6964          * During full modesets we write a lot of registers, wait
6965          * for PLLs, etc. Doing that while DC states are enabled
6966          * is not a good idea.
6967          *
6968          * During fastsets and other updates we also need to
6969          * disable DC states due to the following scenario:
6970          * 1. DC5 exit and PSR exit happen
6971          * 2. Some or all _noarm() registers are written
6972          * 3. Due to some long delay PSR is re-entered
6973          * 4. DC5 entry -> DMC saves the already written new
6974          *    _noarm() registers and the old not yet written
6975          *    _arm() registers
6976          * 5. DC5 exit -> DMC restores a mixture of old and
6977          *    new register values and arms the update
6978          * 6. PSR exit -> hardware latches a mixture of old and
6979          *    new register values -> corrupted frame, or worse
6980          * 7. New _arm() registers are finally written
6981          * 8. Hardware finally latches a complete set of new
6982          *    register values, and subsequent frames will be OK again
6983          *
6984          * Also note that due to the pipe CSC hardware issues on
6985          * SKL/GLK DC states must remain off until the pipe CSC
6986          * state readout has happened. Otherwise we risk corrupting
6987          * the CSC latched register values with the readout (see
6988          * skl_read_csc() and skl_color_commit_noarm()).
6989          */
6990         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
6991
6992         intel_atomic_prepare_plane_clear_colors(state);
6993
6994         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6995                                             new_crtc_state, i) {
6996                 if (intel_crtc_needs_modeset(new_crtc_state) ||
6997                     intel_crtc_needs_fastset(new_crtc_state))
6998                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
6999         }
7000
7001         intel_commit_modeset_disables(state);
7002
7003         /* FIXME: Eventually get rid of our crtc->config pointer */
7004         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7005                 crtc->config = new_crtc_state;
7006
7007         /*
7008          * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7009          * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7010          * index, cdclk/ddiclk frequencies are supposed to be configured before
7011          * the cdclk config is set.
7012          */
7013         intel_pmdemand_pre_plane_update(state);
7014
7015         if (state->modeset) {
7016                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7017
7018                 intel_set_cdclk_pre_plane_update(state);
7019
7020                 intel_modeset_verify_disabled(dev_priv, state);
7021         }
7022
7023         intel_sagv_pre_plane_update(state);
7024
7025         /* Complete the events for pipes that have now been disabled */
7026         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7027                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7028
7029                 /* Complete events for now disable pipes here. */
7030                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7031                         spin_lock_irq(&dev->event_lock);
7032                         drm_crtc_send_vblank_event(&crtc->base,
7033                                                    new_crtc_state->uapi.event);
7034                         spin_unlock_irq(&dev->event_lock);
7035
7036                         new_crtc_state->uapi.event = NULL;
7037                 }
7038         }
7039
7040         intel_encoders_update_prepare(state);
7041
7042         intel_dbuf_pre_plane_update(state);
7043         intel_mbus_dbox_update(state);
7044
7045         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7046                 if (new_crtc_state->do_async_flip)
7047                         intel_crtc_enable_flip_done(state, crtc);
7048         }
7049
7050         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7051         dev_priv->display.funcs.display->commit_modeset_enables(state);
7052
7053         if (state->modeset)
7054                 intel_set_cdclk_post_plane_update(state);
7055
7056         intel_wait_for_vblank_workers(state);
7057
7058         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7059          * already, but still need the state for the delayed optimization. To
7060          * fix this:
7061          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7062          * - schedule that vblank worker _before_ calling hw_done
7063          * - at the start of commit_tail, cancel it _synchrously
7064          * - switch over to the vblank wait helper in the core after that since
7065          *   we don't need out special handling any more.
7066          */
7067         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7068
7069         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7070                 if (new_crtc_state->do_async_flip)
7071                         intel_crtc_disable_flip_done(state, crtc);
7072         }
7073
7074         /*
7075          * Now that the vblank has passed, we can go ahead and program the
7076          * optimal watermarks on platforms that need two-step watermark
7077          * programming.
7078          *
7079          * TODO: Move this (and other cleanup) to an async worker eventually.
7080          */
7081         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7082                                             new_crtc_state, i) {
7083                 /*
7084                  * Gen2 reports pipe underruns whenever all planes are disabled.
7085                  * So re-enable underrun reporting after some planes get enabled.
7086                  *
7087                  * We do this before .optimize_watermarks() so that we have a
7088                  * chance of catching underruns with the intermediate watermarks
7089                  * vs. the new plane configuration.
7090                  */
7091                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7092                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7093
7094                 intel_optimize_watermarks(state, crtc);
7095         }
7096
7097         intel_dbuf_post_plane_update(state);
7098         intel_psr_post_plane_update(state);
7099
7100         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7101                 intel_post_plane_update(state, crtc);
7102
7103                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7104
7105                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7106
7107                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7108                 hsw_ips_post_update(state, crtc);
7109
7110                 /*
7111                  * Activate DRRS after state readout to avoid
7112                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7113                  */
7114                 intel_drrs_activate(new_crtc_state);
7115
7116                 /*
7117                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7118                  * cleanup. So copy and reset the dsb structure to sync with
7119                  * commit_done and later do dsb cleanup in cleanup_work.
7120                  *
7121                  * FIXME get rid of this funny new->old swapping
7122                  */
7123                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7124         }
7125
7126         /* Underruns don't always raise interrupts, so check manually */
7127         intel_check_cpu_fifo_underruns(dev_priv);
7128         intel_check_pch_fifo_underruns(dev_priv);
7129
7130         if (state->modeset)
7131                 intel_verify_planes(state);
7132
7133         intel_sagv_post_plane_update(state);
7134         intel_pmdemand_post_plane_update(state);
7135
7136         drm_atomic_helper_commit_hw_done(&state->base);
7137
7138         if (state->modeset) {
7139                 /* As one of the primary mmio accessors, KMS has a high
7140                  * likelihood of triggering bugs in unclaimed access. After we
7141                  * finish modesetting, see if an error has been flagged, and if
7142                  * so enable debugging for the next modeset - and hope we catch
7143                  * the culprit.
7144                  */
7145                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7146         }
7147         intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref);
7148         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7149
7150         /*
7151          * Defer the cleanup of the old state to a separate worker to not
7152          * impede the current task (userspace for blocking modesets) that
7153          * are executed inline. For out-of-line asynchronous modesets/flips,
7154          * deferring to a new worker seems overkill, but we would place a
7155          * schedule point (cond_resched()) here anyway to keep latencies
7156          * down.
7157          */
7158         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7159         queue_work(system_highpri_wq, &state->base.commit_work);
7160 }
7161
7162 static void intel_atomic_commit_work(struct work_struct *work)
7163 {
7164         struct intel_atomic_state *state =
7165                 container_of(work, struct intel_atomic_state, base.commit_work);
7166
7167         intel_atomic_commit_tail(state);
7168 }
7169
7170 static int
7171 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7172                           enum i915_sw_fence_notify notify)
7173 {
7174         struct intel_atomic_state *state =
7175                 container_of(fence, struct intel_atomic_state, commit_ready);
7176
7177         switch (notify) {
7178         case FENCE_COMPLETE:
7179                 /* we do blocking waits in the worker, nothing to do here */
7180                 break;
7181         case FENCE_FREE:
7182                 {
7183                         struct drm_i915_private *i915 = to_i915(state->base.dev);
7184                         struct intel_atomic_helper *helper =
7185                                 &i915->display.atomic_helper;
7186
7187                         if (llist_add(&state->freed, &helper->free_list))
7188                                 queue_work(i915->unordered_wq, &helper->free_work);
7189                         break;
7190                 }
7191         }
7192
7193         return NOTIFY_DONE;
7194 }
7195
7196 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7197 {
7198         struct intel_plane_state *old_plane_state, *new_plane_state;
7199         struct intel_plane *plane;
7200         int i;
7201
7202         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7203                                              new_plane_state, i)
7204                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7205                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7206                                         plane->frontbuffer_bit);
7207 }
7208
7209 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7210                         bool nonblock)
7211 {
7212         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7213         struct drm_i915_private *dev_priv = to_i915(dev);
7214         int ret = 0;
7215
7216         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7217
7218         drm_atomic_state_get(&state->base);
7219         i915_sw_fence_init(&state->commit_ready,
7220                            intel_atomic_commit_ready);
7221
7222         /*
7223          * The intel_legacy_cursor_update() fast path takes care
7224          * of avoiding the vblank waits for simple cursor
7225          * movement and flips. For cursor on/off and size changes,
7226          * we want to perform the vblank waits so that watermark
7227          * updates happen during the correct frames. Gen9+ have
7228          * double buffered watermarks and so shouldn't need this.
7229          *
7230          * Unset state->legacy_cursor_update before the call to
7231          * drm_atomic_helper_setup_commit() because otherwise
7232          * drm_atomic_helper_wait_for_flip_done() is a noop and
7233          * we get FIFO underruns because we didn't wait
7234          * for vblank.
7235          *
7236          * FIXME doing watermarks and fb cleanup from a vblank worker
7237          * (assuming we had any) would solve these problems.
7238          */
7239         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7240                 struct intel_crtc_state *new_crtc_state;
7241                 struct intel_crtc *crtc;
7242                 int i;
7243
7244                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7245                         if (new_crtc_state->wm.need_postvbl_update ||
7246                             new_crtc_state->update_wm_post)
7247                                 state->base.legacy_cursor_update = false;
7248         }
7249
7250         ret = intel_atomic_prepare_commit(state);
7251         if (ret) {
7252                 drm_dbg_atomic(&dev_priv->drm,
7253                                "Preparing state failed with %i\n", ret);
7254                 i915_sw_fence_commit(&state->commit_ready);
7255                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7256                 return ret;
7257         }
7258
7259         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7260         if (!ret)
7261                 ret = drm_atomic_helper_swap_state(&state->base, true);
7262         if (!ret)
7263                 intel_atomic_swap_global_state(state);
7264
7265         if (ret) {
7266                 struct intel_crtc_state *new_crtc_state;
7267                 struct intel_crtc *crtc;
7268                 int i;
7269
7270                 i915_sw_fence_commit(&state->commit_ready);
7271
7272                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7273                         intel_color_cleanup_commit(new_crtc_state);
7274
7275                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7276                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7277                 return ret;
7278         }
7279         intel_shared_dpll_swap_state(state);
7280         intel_atomic_track_fbs(state);
7281
7282         drm_atomic_state_get(&state->base);
7283         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7284
7285         i915_sw_fence_commit(&state->commit_ready);
7286         if (nonblock && state->modeset) {
7287                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7288         } else if (nonblock) {
7289                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7290         } else {
7291                 if (state->modeset)
7292                         flush_workqueue(dev_priv->display.wq.modeset);
7293                 intel_atomic_commit_tail(state);
7294         }
7295
7296         return 0;
7297 }
7298
7299 /**
7300  * intel_plane_destroy - destroy a plane
7301  * @plane: plane to destroy
7302  *
7303  * Common destruction function for all types of planes (primary, cursor,
7304  * sprite).
7305  */
7306 void intel_plane_destroy(struct drm_plane *plane)
7307 {
7308         drm_plane_cleanup(plane);
7309         kfree(to_intel_plane(plane));
7310 }
7311
7312 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7313                                       struct drm_file *file)
7314 {
7315         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7316         struct drm_crtc *drmmode_crtc;
7317         struct intel_crtc *crtc;
7318
7319         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7320         if (!drmmode_crtc)
7321                 return -ENOENT;
7322
7323         crtc = to_intel_crtc(drmmode_crtc);
7324         pipe_from_crtc_id->pipe = crtc->pipe;
7325
7326         return 0;
7327 }
7328
7329 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7330 {
7331         struct drm_device *dev = encoder->base.dev;
7332         struct intel_encoder *source_encoder;
7333         u32 possible_clones = 0;
7334
7335         for_each_intel_encoder(dev, source_encoder) {
7336                 if (encoders_cloneable(encoder, source_encoder))
7337                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7338         }
7339
7340         return possible_clones;
7341 }
7342
7343 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7344 {
7345         struct drm_device *dev = encoder->base.dev;
7346         struct intel_crtc *crtc;
7347         u32 possible_crtcs = 0;
7348
7349         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7350                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7351
7352         return possible_crtcs;
7353 }
7354
7355 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7356 {
7357         if (!IS_MOBILE(dev_priv))
7358                 return false;
7359
7360         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7361                 return false;
7362
7363         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7364                 return false;
7365
7366         return true;
7367 }
7368
7369 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7370 {
7371         if (DISPLAY_VER(dev_priv) >= 9)
7372                 return false;
7373
7374         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7375                 return false;
7376
7377         if (HAS_PCH_LPT_H(dev_priv) &&
7378             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7379                 return false;
7380
7381         /* DDI E can't be used if DDI A requires 4 lanes */
7382         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7383                 return false;
7384
7385         if (!dev_priv->display.vbt.int_crt_support)
7386                 return false;
7387
7388         return true;
7389 }
7390
7391 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7392 {
7393         struct intel_encoder *encoder;
7394         bool dpd_is_edp = false;
7395
7396         intel_pps_unlock_regs_wa(dev_priv);
7397
7398         if (!HAS_DISPLAY(dev_priv))
7399                 return;
7400
7401         if (IS_METEORLAKE(dev_priv)) {
7402                 intel_ddi_init(dev_priv, PORT_A);
7403                 intel_ddi_init(dev_priv, PORT_B);
7404                 intel_ddi_init(dev_priv, PORT_TC1);
7405                 intel_ddi_init(dev_priv, PORT_TC2);
7406                 intel_ddi_init(dev_priv, PORT_TC3);
7407                 intel_ddi_init(dev_priv, PORT_TC4);
7408         } else if (IS_DG2(dev_priv)) {
7409                 intel_ddi_init(dev_priv, PORT_A);
7410                 intel_ddi_init(dev_priv, PORT_B);
7411                 intel_ddi_init(dev_priv, PORT_C);
7412                 intel_ddi_init(dev_priv, PORT_D_XELPD);
7413                 intel_ddi_init(dev_priv, PORT_TC1);
7414         } else if (IS_ALDERLAKE_P(dev_priv)) {
7415                 intel_ddi_init(dev_priv, PORT_A);
7416                 intel_ddi_init(dev_priv, PORT_B);
7417                 intel_ddi_init(dev_priv, PORT_TC1);
7418                 intel_ddi_init(dev_priv, PORT_TC2);
7419                 intel_ddi_init(dev_priv, PORT_TC3);
7420                 intel_ddi_init(dev_priv, PORT_TC4);
7421                 icl_dsi_init(dev_priv);
7422         } else if (IS_ALDERLAKE_S(dev_priv)) {
7423                 intel_ddi_init(dev_priv, PORT_A);
7424                 intel_ddi_init(dev_priv, PORT_TC1);
7425                 intel_ddi_init(dev_priv, PORT_TC2);
7426                 intel_ddi_init(dev_priv, PORT_TC3);
7427                 intel_ddi_init(dev_priv, PORT_TC4);
7428         } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7429                 intel_ddi_init(dev_priv, PORT_A);
7430                 intel_ddi_init(dev_priv, PORT_B);
7431                 intel_ddi_init(dev_priv, PORT_TC1);
7432                 intel_ddi_init(dev_priv, PORT_TC2);
7433         } else if (DISPLAY_VER(dev_priv) >= 12) {
7434                 intel_ddi_init(dev_priv, PORT_A);
7435                 intel_ddi_init(dev_priv, PORT_B);
7436                 intel_ddi_init(dev_priv, PORT_TC1);
7437                 intel_ddi_init(dev_priv, PORT_TC2);
7438                 intel_ddi_init(dev_priv, PORT_TC3);
7439                 intel_ddi_init(dev_priv, PORT_TC4);
7440                 intel_ddi_init(dev_priv, PORT_TC5);
7441                 intel_ddi_init(dev_priv, PORT_TC6);
7442                 icl_dsi_init(dev_priv);
7443         } else if (IS_JSL_EHL(dev_priv)) {
7444                 intel_ddi_init(dev_priv, PORT_A);
7445                 intel_ddi_init(dev_priv, PORT_B);
7446                 intel_ddi_init(dev_priv, PORT_C);
7447                 intel_ddi_init(dev_priv, PORT_D);
7448                 icl_dsi_init(dev_priv);
7449         } else if (DISPLAY_VER(dev_priv) == 11) {
7450                 intel_ddi_init(dev_priv, PORT_A);
7451                 intel_ddi_init(dev_priv, PORT_B);
7452                 intel_ddi_init(dev_priv, PORT_C);
7453                 intel_ddi_init(dev_priv, PORT_D);
7454                 intel_ddi_init(dev_priv, PORT_E);
7455                 intel_ddi_init(dev_priv, PORT_F);
7456                 icl_dsi_init(dev_priv);
7457         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7458                 intel_ddi_init(dev_priv, PORT_A);
7459                 intel_ddi_init(dev_priv, PORT_B);
7460                 intel_ddi_init(dev_priv, PORT_C);
7461                 vlv_dsi_init(dev_priv);
7462         } else if (DISPLAY_VER(dev_priv) >= 9) {
7463                 intel_ddi_init(dev_priv, PORT_A);
7464                 intel_ddi_init(dev_priv, PORT_B);
7465                 intel_ddi_init(dev_priv, PORT_C);
7466                 intel_ddi_init(dev_priv, PORT_D);
7467                 intel_ddi_init(dev_priv, PORT_E);
7468         } else if (HAS_DDI(dev_priv)) {
7469                 u32 found;
7470
7471                 if (intel_ddi_crt_present(dev_priv))
7472                         intel_crt_init(dev_priv);
7473
7474                 /* Haswell uses DDI functions to detect digital outputs. */
7475                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
7476                 if (found)
7477                         intel_ddi_init(dev_priv, PORT_A);
7478
7479                 found = intel_de_read(dev_priv, SFUSE_STRAP);
7480                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7481                         intel_ddi_init(dev_priv, PORT_B);
7482                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7483                         intel_ddi_init(dev_priv, PORT_C);
7484                 if (found & SFUSE_STRAP_DDID_DETECTED)
7485                         intel_ddi_init(dev_priv, PORT_D);
7486                 if (found & SFUSE_STRAP_DDIF_DETECTED)
7487                         intel_ddi_init(dev_priv, PORT_F);
7488         } else if (HAS_PCH_SPLIT(dev_priv)) {
7489                 int found;
7490
7491                 /*
7492                  * intel_edp_init_connector() depends on this completing first,
7493                  * to prevent the registration of both eDP and LVDS and the
7494                  * incorrect sharing of the PPS.
7495                  */
7496                 intel_lvds_init(dev_priv);
7497                 intel_crt_init(dev_priv);
7498
7499                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7500
7501                 if (ilk_has_edp_a(dev_priv))
7502                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7503
7504                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7505                         /* PCH SDVOB multiplex with HDMIB */
7506                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7507                         if (!found)
7508                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7509                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7510                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7511                 }
7512
7513                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7514                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7515
7516                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7517                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7518
7519                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7520                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7521
7522                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7523                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7524         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7525                 bool has_edp, has_port;
7526
7527                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7528                         intel_crt_init(dev_priv);
7529
7530                 /*
7531                  * The DP_DETECTED bit is the latched state of the DDC
7532                  * SDA pin at boot. However since eDP doesn't require DDC
7533                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7534                  * eDP ports may have been muxed to an alternate function.
7535                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7536                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7537                  * detect eDP ports.
7538                  *
7539                  * Sadly the straps seem to be missing sometimes even for HDMI
7540                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7541                  * and VBT for the presence of the port. Additionally we can't
7542                  * trust the port type the VBT declares as we've seen at least
7543                  * HDMI ports that the VBT claim are DP or eDP.
7544                  */
7545                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7546                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7547                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7548                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7549                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7550                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7551
7552                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7553                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7554                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7555                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7556                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7557                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7558
7559                 if (IS_CHERRYVIEW(dev_priv)) {
7560                         /*
7561                          * eDP not supported on port D,
7562                          * so no need to worry about it
7563                          */
7564                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7565                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7566                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7567                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7568                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7569                 }
7570
7571                 vlv_dsi_init(dev_priv);
7572         } else if (IS_PINEVIEW(dev_priv)) {
7573                 intel_lvds_init(dev_priv);
7574                 intel_crt_init(dev_priv);
7575         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7576                 bool found = false;
7577
7578                 if (IS_MOBILE(dev_priv))
7579                         intel_lvds_init(dev_priv);
7580
7581                 intel_crt_init(dev_priv);
7582
7583                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7584                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7585                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7586                         if (!found && IS_G4X(dev_priv)) {
7587                                 drm_dbg_kms(&dev_priv->drm,
7588                                             "probing HDMI on SDVOB\n");
7589                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7590                         }
7591
7592                         if (!found && IS_G4X(dev_priv))
7593                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7594                 }
7595
7596                 /* Before G4X SDVOC doesn't have its own detect register */
7597
7598                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7599                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7600                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7601                 }
7602
7603                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7604
7605                         if (IS_G4X(dev_priv)) {
7606                                 drm_dbg_kms(&dev_priv->drm,
7607                                             "probing HDMI on SDVOC\n");
7608                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7609                         }
7610                         if (IS_G4X(dev_priv))
7611                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7612                 }
7613
7614                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7615                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7616
7617                 if (SUPPORTS_TV(dev_priv))
7618                         intel_tv_init(dev_priv);
7619         } else if (DISPLAY_VER(dev_priv) == 2) {
7620                 if (IS_I85X(dev_priv))
7621                         intel_lvds_init(dev_priv);
7622
7623                 intel_crt_init(dev_priv);
7624                 intel_dvo_init(dev_priv);
7625         }
7626
7627         for_each_intel_encoder(&dev_priv->drm, encoder) {
7628                 encoder->base.possible_crtcs =
7629                         intel_encoder_possible_crtcs(encoder);
7630                 encoder->base.possible_clones =
7631                         intel_encoder_possible_clones(encoder);
7632         }
7633
7634         intel_init_pch_refclk(dev_priv);
7635
7636         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7637 }
7638
7639 static int max_dotclock(struct drm_i915_private *i915)
7640 {
7641         int max_dotclock = i915->max_dotclk_freq;
7642
7643         /* icl+ might use bigjoiner */
7644         if (DISPLAY_VER(i915) >= 11)
7645                 max_dotclock *= 2;
7646
7647         return max_dotclock;
7648 }
7649
7650 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7651                                       const struct drm_display_mode *mode)
7652 {
7653         struct drm_i915_private *dev_priv = to_i915(dev);
7654         int hdisplay_max, htotal_max;
7655         int vdisplay_max, vtotal_max;
7656
7657         /*
7658          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7659          * of DBLSCAN modes to the output's mode list when they detect
7660          * the scaling mode property on the connector. And they don't
7661          * ask the kernel to validate those modes in any way until
7662          * modeset time at which point the client gets a protocol error.
7663          * So in order to not upset those clients we silently ignore the
7664          * DBLSCAN flag on such connectors. For other connectors we will
7665          * reject modes with the DBLSCAN flag in encoder->compute_config().
7666          * And we always reject DBLSCAN modes in connector->mode_valid()
7667          * as we never want such modes on the connector's mode list.
7668          */
7669
7670         if (mode->vscan > 1)
7671                 return MODE_NO_VSCAN;
7672
7673         if (mode->flags & DRM_MODE_FLAG_HSKEW)
7674                 return MODE_H_ILLEGAL;
7675
7676         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7677                            DRM_MODE_FLAG_NCSYNC |
7678                            DRM_MODE_FLAG_PCSYNC))
7679                 return MODE_HSYNC;
7680
7681         if (mode->flags & (DRM_MODE_FLAG_BCAST |
7682                            DRM_MODE_FLAG_PIXMUX |
7683                            DRM_MODE_FLAG_CLKDIV2))
7684                 return MODE_BAD;
7685
7686         /*
7687          * Reject clearly excessive dotclocks early to
7688          * avoid having to worry about huge integers later.
7689          */
7690         if (mode->clock > max_dotclock(dev_priv))
7691                 return MODE_CLOCK_HIGH;
7692
7693         /* Transcoder timing limits */
7694         if (DISPLAY_VER(dev_priv) >= 11) {
7695                 hdisplay_max = 16384;
7696                 vdisplay_max = 8192;
7697                 htotal_max = 16384;
7698                 vtotal_max = 8192;
7699         } else if (DISPLAY_VER(dev_priv) >= 9 ||
7700                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7701                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7702                 vdisplay_max = 4096;
7703                 htotal_max = 8192;
7704                 vtotal_max = 8192;
7705         } else if (DISPLAY_VER(dev_priv) >= 3) {
7706                 hdisplay_max = 4096;
7707                 vdisplay_max = 4096;
7708                 htotal_max = 8192;
7709                 vtotal_max = 8192;
7710         } else {
7711                 hdisplay_max = 2048;
7712                 vdisplay_max = 2048;
7713                 htotal_max = 4096;
7714                 vtotal_max = 4096;
7715         }
7716
7717         if (mode->hdisplay > hdisplay_max ||
7718             mode->hsync_start > htotal_max ||
7719             mode->hsync_end > htotal_max ||
7720             mode->htotal > htotal_max)
7721                 return MODE_H_ILLEGAL;
7722
7723         if (mode->vdisplay > vdisplay_max ||
7724             mode->vsync_start > vtotal_max ||
7725             mode->vsync_end > vtotal_max ||
7726             mode->vtotal > vtotal_max)
7727                 return MODE_V_ILLEGAL;
7728
7729         if (DISPLAY_VER(dev_priv) >= 5) {
7730                 if (mode->hdisplay < 64 ||
7731                     mode->htotal - mode->hdisplay < 32)
7732                         return MODE_H_ILLEGAL;
7733
7734                 if (mode->vtotal - mode->vdisplay < 5)
7735                         return MODE_V_ILLEGAL;
7736         } else {
7737                 if (mode->htotal - mode->hdisplay < 32)
7738                         return MODE_H_ILLEGAL;
7739
7740                 if (mode->vtotal - mode->vdisplay < 3)
7741                         return MODE_V_ILLEGAL;
7742         }
7743
7744         /*
7745          * Cantiga+ cannot handle modes with a hsync front porch of 0.
7746          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7747          */
7748         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7749             mode->hsync_start == mode->hdisplay)
7750                 return MODE_H_ILLEGAL;
7751
7752         return MODE_OK;
7753 }
7754
7755 enum drm_mode_status
7756 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7757                                 const struct drm_display_mode *mode,
7758                                 bool bigjoiner)
7759 {
7760         int plane_width_max, plane_height_max;
7761
7762         /*
7763          * intel_mode_valid() should be
7764          * sufficient on older platforms.
7765          */
7766         if (DISPLAY_VER(dev_priv) < 9)
7767                 return MODE_OK;
7768
7769         /*
7770          * Most people will probably want a fullscreen
7771          * plane so let's not advertize modes that are
7772          * too big for that.
7773          */
7774         if (DISPLAY_VER(dev_priv) >= 11) {
7775                 plane_width_max = 5120 << bigjoiner;
7776                 plane_height_max = 4320;
7777         } else {
7778                 plane_width_max = 5120;
7779                 plane_height_max = 4096;
7780         }
7781
7782         if (mode->hdisplay > plane_width_max)
7783                 return MODE_H_ILLEGAL;
7784
7785         if (mode->vdisplay > plane_height_max)
7786                 return MODE_V_ILLEGAL;
7787
7788         return MODE_OK;
7789 }
7790
7791 static const struct intel_display_funcs skl_display_funcs = {
7792         .get_pipe_config = hsw_get_pipe_config,
7793         .crtc_enable = hsw_crtc_enable,
7794         .crtc_disable = hsw_crtc_disable,
7795         .commit_modeset_enables = skl_commit_modeset_enables,
7796         .get_initial_plane_config = skl_get_initial_plane_config,
7797 };
7798
7799 static const struct intel_display_funcs ddi_display_funcs = {
7800         .get_pipe_config = hsw_get_pipe_config,
7801         .crtc_enable = hsw_crtc_enable,
7802         .crtc_disable = hsw_crtc_disable,
7803         .commit_modeset_enables = intel_commit_modeset_enables,
7804         .get_initial_plane_config = i9xx_get_initial_plane_config,
7805 };
7806
7807 static const struct intel_display_funcs pch_split_display_funcs = {
7808         .get_pipe_config = ilk_get_pipe_config,
7809         .crtc_enable = ilk_crtc_enable,
7810         .crtc_disable = ilk_crtc_disable,
7811         .commit_modeset_enables = intel_commit_modeset_enables,
7812         .get_initial_plane_config = i9xx_get_initial_plane_config,
7813 };
7814
7815 static const struct intel_display_funcs vlv_display_funcs = {
7816         .get_pipe_config = i9xx_get_pipe_config,
7817         .crtc_enable = valleyview_crtc_enable,
7818         .crtc_disable = i9xx_crtc_disable,
7819         .commit_modeset_enables = intel_commit_modeset_enables,
7820         .get_initial_plane_config = i9xx_get_initial_plane_config,
7821 };
7822
7823 static const struct intel_display_funcs i9xx_display_funcs = {
7824         .get_pipe_config = i9xx_get_pipe_config,
7825         .crtc_enable = i9xx_crtc_enable,
7826         .crtc_disable = i9xx_crtc_disable,
7827         .commit_modeset_enables = intel_commit_modeset_enables,
7828         .get_initial_plane_config = i9xx_get_initial_plane_config,
7829 };
7830
7831 /**
7832  * intel_init_display_hooks - initialize the display modesetting hooks
7833  * @dev_priv: device private
7834  */
7835 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
7836 {
7837         if (DISPLAY_VER(dev_priv) >= 9) {
7838                 dev_priv->display.funcs.display = &skl_display_funcs;
7839         } else if (HAS_DDI(dev_priv)) {
7840                 dev_priv->display.funcs.display = &ddi_display_funcs;
7841         } else if (HAS_PCH_SPLIT(dev_priv)) {
7842                 dev_priv->display.funcs.display = &pch_split_display_funcs;
7843         } else if (IS_CHERRYVIEW(dev_priv) ||
7844                    IS_VALLEYVIEW(dev_priv)) {
7845                 dev_priv->display.funcs.display = &vlv_display_funcs;
7846         } else {
7847                 dev_priv->display.funcs.display = &i9xx_display_funcs;
7848         }
7849 }
7850
7851 int intel_initial_commit(struct drm_device *dev)
7852 {
7853         struct drm_atomic_state *state = NULL;
7854         struct drm_modeset_acquire_ctx ctx;
7855         struct intel_crtc *crtc;
7856         int ret = 0;
7857
7858         state = drm_atomic_state_alloc(dev);
7859         if (!state)
7860                 return -ENOMEM;
7861
7862         drm_modeset_acquire_init(&ctx, 0);
7863
7864         state->acquire_ctx = &ctx;
7865         to_intel_atomic_state(state)->internal = true;
7866
7867 retry:
7868         for_each_intel_crtc(dev, crtc) {
7869                 struct intel_crtc_state *crtc_state =
7870                         intel_atomic_get_crtc_state(state, crtc);
7871
7872                 if (IS_ERR(crtc_state)) {
7873                         ret = PTR_ERR(crtc_state);
7874                         goto out;
7875                 }
7876
7877                 if (crtc_state->hw.active) {
7878                         struct intel_encoder *encoder;
7879
7880                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
7881                         if (ret)
7882                                 goto out;
7883
7884                         /*
7885                          * FIXME hack to force a LUT update to avoid the
7886                          * plane update forcing the pipe gamma on without
7887                          * having a proper LUT loaded. Remove once we
7888                          * have readout for pipe gamma enable.
7889                          */
7890                         crtc_state->uapi.color_mgmt_changed = true;
7891
7892                         for_each_intel_encoder_mask(dev, encoder,
7893                                                     crtc_state->uapi.encoder_mask) {
7894                                 if (encoder->initial_fastset_check &&
7895                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
7896                                         ret = drm_atomic_add_affected_connectors(state,
7897                                                                                  &crtc->base);
7898                                         if (ret)
7899                                                 goto out;
7900                                 }
7901                         }
7902                 }
7903         }
7904
7905         ret = drm_atomic_commit(state);
7906
7907 out:
7908         if (ret == -EDEADLK) {
7909                 drm_atomic_state_clear(state);
7910                 drm_modeset_backoff(&ctx);
7911                 goto retry;
7912         }
7913
7914         drm_atomic_state_put(state);
7915
7916         drm_modeset_drop_locks(&ctx);
7917         drm_modeset_acquire_fini(&ctx);
7918
7919         return ret;
7920 }
7921
7922 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
7923 {
7924         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
7925         enum transcoder cpu_transcoder = (enum transcoder)pipe;
7926         /* 640x480@60Hz, ~25175 kHz */
7927         struct dpll clock = {
7928                 .m1 = 18,
7929                 .m2 = 7,
7930                 .p1 = 13,
7931                 .p2 = 4,
7932                 .n = 2,
7933         };
7934         u32 dpll, fp;
7935         int i;
7936
7937         drm_WARN_ON(&dev_priv->drm,
7938                     i9xx_calc_dpll_params(48000, &clock) != 25154);
7939
7940         drm_dbg_kms(&dev_priv->drm,
7941                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
7942                     pipe_name(pipe), clock.vco, clock.dot);
7943
7944         fp = i9xx_dpll_compute_fp(&clock);
7945         dpll = DPLL_DVO_2X_MODE |
7946                 DPLL_VGA_MODE_DIS |
7947                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
7948                 PLL_P2_DIVIDE_BY_4 |
7949                 PLL_REF_INPUT_DREFCLK |
7950                 DPLL_VCO_ENABLE;
7951
7952         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
7953                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
7954         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
7955                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
7956         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
7957                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
7958         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
7959                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
7960         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
7961                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
7962         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
7963                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
7964         intel_de_write(dev_priv, PIPESRC(pipe),
7965                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
7966
7967         intel_de_write(dev_priv, FP0(pipe), fp);
7968         intel_de_write(dev_priv, FP1(pipe), fp);
7969
7970         /*
7971          * Apparently we need to have VGA mode enabled prior to changing
7972          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
7973          * dividers, even though the register value does change.
7974          */
7975         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
7976         intel_de_write(dev_priv, DPLL(pipe), dpll);
7977
7978         /* Wait for the clocks to stabilize. */
7979         intel_de_posting_read(dev_priv, DPLL(pipe));
7980         udelay(150);
7981
7982         /* The pixel multiplier can only be updated once the
7983          * DPLL is enabled and the clocks are stable.
7984          *
7985          * So write it again.
7986          */
7987         intel_de_write(dev_priv, DPLL(pipe), dpll);
7988
7989         /* We do this three times for luck */
7990         for (i = 0; i < 3 ; i++) {
7991                 intel_de_write(dev_priv, DPLL(pipe), dpll);
7992                 intel_de_posting_read(dev_priv, DPLL(pipe));
7993                 udelay(150); /* wait for warmup */
7994         }
7995
7996         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
7997         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
7998
7999         intel_wait_for_pipe_scanline_moving(crtc);
8000 }
8001
8002 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8003 {
8004         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8005
8006         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8007                     pipe_name(pipe));
8008
8009         drm_WARN_ON(&dev_priv->drm,
8010                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8011         drm_WARN_ON(&dev_priv->drm,
8012                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8013         drm_WARN_ON(&dev_priv->drm,
8014                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8015         drm_WARN_ON(&dev_priv->drm,
8016                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8017         drm_WARN_ON(&dev_priv->drm,
8018                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8019
8020         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8021         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8022
8023         intel_wait_for_pipe_scanline_stopped(crtc);
8024
8025         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8026         intel_de_posting_read(dev_priv, DPLL(pipe));
8027 }
8028
8029 void intel_hpd_poll_fini(struct drm_i915_private *i915)
8030 {
8031         struct intel_connector *connector;
8032         struct drm_connector_list_iter conn_iter;
8033
8034         /* Kill all the work that may have been queued by hpd. */
8035         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8036         for_each_intel_connector_iter(connector, &conn_iter) {
8037                 if (connector->modeset_retry_work.func)
8038                         cancel_work_sync(&connector->modeset_retry_work);
8039                 if (connector->hdcp.shim) {
8040                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8041                         cancel_work_sync(&connector->hdcp.prop_work);
8042                 }
8043         }
8044         drm_connector_list_iter_end(&conn_iter);
8045 }
8046
8047 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8048 {
8049         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8050 }