drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 149                                    struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 168 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 169 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 170 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 171                                          struct drm_modeset_acquire_ctx *ctx);
 172
 173 struct intel_limit {
 174         struct {
 175                 int min, max;
 176         } dot, vco, n, m, m1, m2, p, p1;
 177
 178         struct {
 179                 int dot_limit;
 180                 int p2_slow, p2_fast;
 181         } p2;
 182 };
 183
 184 /* returns HPLL frequency in kHz */
 185 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 186 {
 187         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 188
 189         /* Obtain SKU information */
 190         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 191                 CCK_FUSE_HPLL_FREQ_MASK;
 192
 193         return vco_freq[hpll_freq] * 1000;
 194 }
 195
 196 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 197                       const char *name, u32 reg, int ref_freq)
 198 {
 199         u32 val;
 200         int divider;
 201
 202         val = vlv_cck_read(dev_priv, reg);
 203         divider = val & CCK_FREQUENCY_VALUES;
 204
 205         WARN((val & CCK_FREQUENCY_STATUS) !=
 206              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 207              "%s change in progress\n", name);
 208
 209         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 210 }
 211
 212 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 213                            const char *name, u32 reg)
 214 {
 215         int hpll;
 216
 217         vlv_cck_get(dev_priv);
 218
 219         if (dev_priv->hpll_freq == 0)
 220                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 221
 222         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 223
 224         vlv_cck_put(dev_priv);
 225
 226         return hpll;
 227 }
 228
 229 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 230 {
 231         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 232                 return;
 233
 234         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 235                                                       CCK_CZ_CLOCK_CONTROL);
 236
 237         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 238 }
 239
 240 static inline u32 /* units of 100MHz */
 241 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 242                     const struct intel_crtc_state *pipe_config)
 243 {
 244         if (HAS_DDI(dev_priv))
 245                 return pipe_config->port_clock; /* SPLL */
 246         else
 247                 return dev_priv->fdi_pll_freq;
 248 }
 249
 250 static const struct intel_limit intel_limits_i8xx_dac = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 908000, .max = 1512000 },
 253         .n = { .min = 2, .max = 16 },
 254         .m = { .min = 96, .max = 140 },
 255         .m1 = { .min = 18, .max = 26 },
 256         .m2 = { .min = 6, .max = 16 },
 257         .p = { .min = 4, .max = 128 },
 258         .p1 = { .min = 2, .max = 33 },
 259         .p2 = { .dot_limit = 165000,
 260                 .p2_slow = 4, .p2_fast = 2 },
 261 };
 262
 263 static const struct intel_limit intel_limits_i8xx_dvo = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 4 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_lvds = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 1, .max = 6 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 14, .p2_fast = 7 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i9xx_sdvo = {
 290         .dot = { .min = 20000, .max = 400000 },
 291         .vco = { .min = 1400000, .max = 2800000 },
 292         .n = { .min = 1, .max = 6 },
 293         .m = { .min = 70, .max = 120 },
 294         .m1 = { .min = 8, .max = 18 },
 295         .m2 = { .min = 3, .max = 7 },
 296         .p = { .min = 5, .max = 80 },
 297         .p1 = { .min = 1, .max = 8 },
 298         .p2 = { .dot_limit = 200000,
 299                 .p2_slow = 10, .p2_fast = 5 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_lvds = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 7, .max = 98 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 112000,
 312                 .p2_slow = 14, .p2_fast = 7 },
 313 };
 314
 315
 316 static const struct intel_limit intel_limits_g4x_sdvo = {
 317         .dot = { .min = 25000, .max = 270000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 17, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 10, .max = 30 },
 324         .p1 = { .min = 1, .max = 3},
 325         .p2 = { .dot_limit = 270000,
 326                 .p2_slow = 10,
 327                 .p2_fast = 10
 328         },
 329 };
 330
 331 static const struct intel_limit intel_limits_g4x_hdmi = {
 332         .dot = { .min = 22000, .max = 400000 },
 333         .vco = { .min = 1750000, .max = 3500000},
 334         .n = { .min = 1, .max = 4 },
 335         .m = { .min = 104, .max = 138 },
 336         .m1 = { .min = 16, .max = 23 },
 337         .m2 = { .min = 5, .max = 11 },
 338         .p = { .min = 5, .max = 80 },
 339         .p1 = { .min = 1, .max = 8},
 340         .p2 = { .dot_limit = 165000,
 341                 .p2_slow = 10, .p2_fast = 5 },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 345         .dot = { .min = 20000, .max = 115000 },
 346         .vco = { .min = 1750000, .max = 3500000 },
 347         .n = { .min = 1, .max = 3 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 17, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 28, .max = 112 },
 352         .p1 = { .min = 2, .max = 8 },
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 14, .p2_fast = 14
 355         },
 356 };
 357
 358 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 359         .dot = { .min = 80000, .max = 224000 },
 360         .vco = { .min = 1750000, .max = 3500000 },
 361         .n = { .min = 1, .max = 3 },
 362         .m = { .min = 104, .max = 138 },
 363         .m1 = { .min = 17, .max = 23 },
 364         .m2 = { .min = 5, .max = 11 },
 365         .p = { .min = 14, .max = 42 },
 366         .p1 = { .min = 2, .max = 6 },
 367         .p2 = { .dot_limit = 0,
 368                 .p2_slow = 7, .p2_fast = 7
 369         },
 370 };
 371
 372 static const struct intel_limit intel_limits_pineview_sdvo = {
 373         .dot = { .min = 20000, .max = 400000},
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         /* Pineview's Ncounter is a ring counter */
 376         .n = { .min = 3, .max = 6 },
 377         .m = { .min = 2, .max = 256 },
 378         /* Pineview only has one combined m divider, which we treat as m2. */
 379         .m1 = { .min = 0, .max = 0 },
 380         .m2 = { .min = 0, .max = 254 },
 381         .p = { .min = 5, .max = 80 },
 382         .p1 = { .min = 1, .max = 8 },
 383         .p2 = { .dot_limit = 200000,
 384                 .p2_slow = 10, .p2_fast = 5 },
 385 };
 386
 387 static const struct intel_limit intel_limits_pineview_lvds = {
 388         .dot = { .min = 20000, .max = 400000 },
 389         .vco = { .min = 1700000, .max = 3500000 },
 390         .n = { .min = 3, .max = 6 },
 391         .m = { .min = 2, .max = 256 },
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 7, .max = 112 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 112000,
 397                 .p2_slow = 14, .p2_fast = 14 },
 398 };
 399
 400 /* Ironlake / Sandybridge
 401  *
 402  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 403  * the range value for them is (actual_value - 2).
 404  */
 405 static const struct intel_limit intel_limits_ironlake_dac = {
 406         .dot = { .min = 25000, .max = 350000 },
 407         .vco = { .min = 1760000, .max = 3510000 },
 408         .n = { .min = 1, .max = 5 },
 409         .m = { .min = 79, .max = 127 },
 410         .m1 = { .min = 12, .max = 22 },
 411         .m2 = { .min = 5, .max = 9 },
 412         .p = { .min = 5, .max = 80 },
 413         .p1 = { .min = 1, .max = 8 },
 414         .p2 = { .dot_limit = 225000,
 415                 .p2_slow = 10, .p2_fast = 5 },
 416 };
 417
 418 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 3 },
 422         .m = { .min = 79, .max = 118 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 28, .max = 112 },
 426         .p1 = { .min = 2, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 14, .p2_fast = 14 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 127 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 14, .max = 56 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 7, .p2_fast = 7 },
 442 };
 443
 444 /* LVDS 100mhz refclk limits. */
 445 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 446         .dot = { .min = 25000, .max = 350000 },
 447         .vco = { .min = 1760000, .max = 3510000 },
 448         .n = { .min = 1, .max = 2 },
 449         .m = { .min = 79, .max = 126 },
 450         .m1 = { .min = 12, .max = 22 },
 451         .m2 = { .min = 5, .max = 9 },
 452         .p = { .min = 28, .max = 112 },
 453         .p1 = { .min = 2, .max = 8 },
 454         .p2 = { .dot_limit = 225000,
 455                 .p2_slow = 14, .p2_fast = 14 },
 456 };
 457
 458 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 3 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 14, .max = 42 },
 466         .p1 = { .min = 2, .max = 6 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 7, .p2_fast = 7 },
 469 };
 470
 471 static const struct intel_limit intel_limits_vlv = {
 472          /*
 473           * These are the data rate limits (measured in fast clocks)
 474           * since those are the strictest limits we have. The fast
 475           * clock and actual rate limits are more relaxed, so checking
 476           * them would make no difference.
 477           */
 478         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 479         .vco = { .min = 4000000, .max = 6000000 },
 480         .n = { .min = 1, .max = 7 },
 481         .m1 = { .min = 2, .max = 3 },
 482         .m2 = { .min = 11, .max = 156 },
 483         .p1 = { .min = 2, .max = 3 },
 484         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 485 };
 486
 487 static const struct intel_limit intel_limits_chv = {
 488         /*
 489          * These are the data rate limits (measured in fast clocks)
 490          * since those are the strictest limits we have.  The fast
 491          * clock and actual rate limits are more relaxed, so checking
 492          * them would make no difference.
 493          */
 494         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 495         .vco = { .min = 4800000, .max = 6480000 },
 496         .n = { .min = 1, .max = 1 },
 497         .m1 = { .min = 2, .max = 2 },
 498         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 499         .p1 = { .min = 2, .max = 4 },
 500         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 501 };
 502
 503 static const struct intel_limit intel_limits_bxt = {
 504         /* FIXME: find real dot limits */
 505         .dot = { .min = 0, .max = INT_MAX },
 506         .vco = { .min = 4800000, .max = 6700000 },
 507         .n = { .min = 1, .max = 1 },
 508         .m1 = { .min = 2, .max = 2 },
 509         /* FIXME: find real m2 limits */
 510         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 511         .p1 = { .min = 2, .max = 4 },
 512         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 513 };
 514
 515 /* WA Display #0827: Gen9:all */
 516 static void
 517 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 518 {
 519         if (enable)
 520                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 521                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 522                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 523         else
 524                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 525                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 526                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 527 }
 528
 529 /* Wa_2006604312:icl */
 530 static void
 531 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 532                        bool enable)
 533 {
 534         if (enable)
 535                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 536                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 537         else
 538                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 539                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 540 }
 541
 542 static bool
 543 needs_modeset(const struct intel_crtc_state *state)
 544 {
 545         return drm_atomic_crtc_needs_modeset(&state->uapi);
 546 }
 547
 548 bool
 549 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 550 {
 551         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 552                 crtc_state->sync_mode_slaves_mask);
 553 }
 554
 555 static bool
 556 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 557 {
 558         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 559                 crtc_state->sync_mode_slaves_mask);
 560 }
 561
 562 static bool
 563 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 564 {
 565         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 566 }
 567
 568 /*
 569  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 570  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 571  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 572  * The helpers' return value is the rate of the clock that is fed to the
 573  * display engine's pipe which can be the above fast dot clock rate or a
 574  * divided-down version of it.
 575  */
 576 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 577 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 578 {
 579         clock->m = clock->m2 + 2;
 580         clock->p = clock->p1 * clock->p2;
 581         if (WARN_ON(clock->n == 0 || clock->p == 0))
 582                 return 0;
 583         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 584         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 585
 586         return clock->dot;
 587 }
 588
 589 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 590 {
 591         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 592 }
 593
 594 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 595 {
 596         clock->m = i9xx_dpll_compute_m(clock);
 597         clock->p = clock->p1 * clock->p2;
 598         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 599                 return 0;
 600         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 601         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 602
 603         return clock->dot;
 604 }
 605
 606 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 607 {
 608         clock->m = clock->m1 * clock->m2;
 609         clock->p = clock->p1 * clock->p2;
 610         if (WARN_ON(clock->n == 0 || clock->p == 0))
 611                 return 0;
 612         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 613         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 614
 615         return clock->dot / 5;
 616 }
 617
 618 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 619 {
 620         clock->m = clock->m1 * clock->m2;
 621         clock->p = clock->p1 * clock->p2;
 622         if (WARN_ON(clock->n == 0 || clock->p == 0))
 623                 return 0;
 624         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 625                                            clock->n << 22);
 626         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 627
 628         return clock->dot / 5;
 629 }
 630
 631 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 632
 633 /*
 634  * Returns whether the given set of divisors are valid for a given refclk with
 635  * the given connectors.
 636  */
 637 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 638                                const struct intel_limit *limit,
 639                                const struct dpll *clock)
 640 {
 641         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 642                 INTELPllInvalid("n out of range\n");
 643         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 644                 INTELPllInvalid("p1 out of range\n");
 645         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 646                 INTELPllInvalid("m2 out of range\n");
 647         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 648                 INTELPllInvalid("m1 out of range\n");
 649
 650         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 651             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 652                 if (clock->m1 <= clock->m2)
 653                         INTELPllInvalid("m1 <= m2\n");
 654
 655         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 656             !IS_GEN9_LP(dev_priv)) {
 657                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 658                         INTELPllInvalid("p out of range\n");
 659                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 660                         INTELPllInvalid("m out of range\n");
 661         }
 662
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static int
 675 i9xx_select_p2_div(const struct intel_limit *limit,
 676                    const struct intel_crtc_state *crtc_state,
 677                    int target)
 678 {
 679         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 680
 681         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 682                 /*
 683                  * For LVDS just rely on its current settings for dual-channel.
 684                  * We haven't figured out how to reliably set up different
 685                  * single/dual channel state, if we even can.
 686                  */
 687                 if (intel_is_dual_link_lvds(dev_priv))
 688                         return limit->p2.p2_fast;
 689                 else
 690                         return limit->p2.p2_slow;
 691         } else {
 692                 if (target < limit->p2.dot_limit)
 693                         return limit->p2.p2_slow;
 694                 else
 695                         return limit->p2.p2_fast;
 696         }
 697 }
 698
 699 /*
 700  * Returns a set of divisors for the desired target clock with the given
 701  * refclk, or FALSE.  The returned values represent the clock equation:
 702  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 703  *
 704  * Target and reference clocks are specified in kHz.
 705  *
 706  * If match_clock is provided, then best_clock P divider must match the P
 707  * divider from @match_clock used for LVDS downclocking.
 708  */
 709 static bool
 710 i9xx_find_best_dpll(const struct intel_limit *limit,
 711                     struct intel_crtc_state *crtc_state,
 712                     int target, int refclk, struct dpll *match_clock,
 713                     struct dpll *best_clock)
 714 {
 715         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 716         struct dpll clock;
 717         int err = target;
 718
 719         memset(best_clock, 0, sizeof(*best_clock));
 720
 721         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 722
 723         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 724              clock.m1++) {
 725                 for (clock.m2 = limit->m2.min;
 726                      clock.m2 <= limit->m2.max; clock.m2++) {
 727                         if (clock.m2 >= clock.m1)
 728                                 break;
 729                         for (clock.n = limit->n.min;
 730                              clock.n <= limit->n.max; clock.n++) {
 731                                 for (clock.p1 = limit->p1.min;
 732                                         clock.p1 <= limit->p1.max; clock.p1++) {
 733                                         int this_err;
 734
 735                                         i9xx_calc_dpll_params(refclk, &clock);
 736                                         if (!intel_PLL_is_valid(to_i915(dev),
 737                                                                 limit,
 738                                                                 &clock))
 739                                                 continue;
 740                                         if (match_clock &&
 741                                             clock.p != match_clock->p)
 742                                                 continue;
 743
 744                                         this_err = abs(clock.dot - target);
 745                                         if (this_err < err) {
 746                                                 *best_clock = clock;
 747                                                 err = this_err;
 748                                         }
 749                                 }
 750                         }
 751                 }
 752         }
 753
 754         return (err != target);
 755 }
 756
 757 /*
 758  * Returns a set of divisors for the desired target clock with the given
 759  * refclk, or FALSE.  The returned values represent the clock equation:
 760  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 761  *
 762  * Target and reference clocks are specified in kHz.
 763  *
 764  * If match_clock is provided, then best_clock P divider must match the P
 765  * divider from @match_clock used for LVDS downclocking.
 766  */
 767 static bool
 768 pnv_find_best_dpll(const struct intel_limit *limit,
 769                    struct intel_crtc_state *crtc_state,
 770                    int target, int refclk, struct dpll *match_clock,
 771                    struct dpll *best_clock)
 772 {
 773         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 774         struct dpll clock;
 775         int err = target;
 776
 777         memset(best_clock, 0, sizeof(*best_clock));
 778
 779         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 780
 781         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 782              clock.m1++) {
 783                 for (clock.m2 = limit->m2.min;
 784                      clock.m2 <= limit->m2.max; clock.m2++) {
 785                         for (clock.n = limit->n.min;
 786                              clock.n <= limit->n.max; clock.n++) {
 787                                 for (clock.p1 = limit->p1.min;
 788                                         clock.p1 <= limit->p1.max; clock.p1++) {
 789                                         int this_err;
 790
 791                                         pnv_calc_dpll_params(refclk, &clock);
 792                                         if (!intel_PLL_is_valid(to_i915(dev),
 793                                                                 limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 /*
 814  * Returns a set of divisors for the desired target clock with the given
 815  * refclk, or FALSE.  The returned values represent the clock equation:
 816  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 817  *
 818  * Target and reference clocks are specified in kHz.
 819  *
 820  * If match_clock is provided, then best_clock P divider must match the P
 821  * divider from @match_clock used for LVDS downclocking.
 822  */
 823 static bool
 824 g4x_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 830         struct dpll clock;
 831         int max_n;
 832         bool found = false;
 833         /* approximately equals target * 0.00585 */
 834         int err_most = (target >> 8) + (target >> 9);
 835
 836         memset(best_clock, 0, sizeof(*best_clock));
 837
 838         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 839
 840         max_n = limit->n.max;
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 /* based on hardware requirement, prefere larger m1,m2 */
 844                 for (clock.m1 = limit->m1.max;
 845                      clock.m1 >= limit->m1.min; clock.m1--) {
 846                         for (clock.m2 = limit->m2.max;
 847                              clock.m2 >= limit->m2.min; clock.m2--) {
 848                                 for (clock.p1 = limit->p1.max;
 849                                      clock.p1 >= limit->p1.min; clock.p1--) {
 850                                         int this_err;
 851
 852                                         i9xx_calc_dpll_params(refclk, &clock);
 853                                         if (!intel_PLL_is_valid(to_i915(dev),
 854                                                                 limit,
 855                                                                 &clock))
 856                                                 continue;
 857
 858                                         this_err = abs(clock.dot - target);
 859                                         if (this_err < err_most) {
 860                                                 *best_clock = clock;
 861                                                 err_most = this_err;
 862                                                 max_n = clock.n;
 863                                                 found = true;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869         return found;
 870 }
 871
 872 /*
 873  * Check if the calculated PLL configuration is more optimal compared to the
 874  * best configuration and error found so far. Return the calculated error.
 875  */
 876 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 877                                const struct dpll *calculated_clock,
 878                                const struct dpll *best_clock,
 879                                unsigned int best_error_ppm,
 880                                unsigned int *error_ppm)
 881 {
 882         /*
 883          * For CHV ignore the error and consider only the P value.
 884          * Prefer a bigger P value based on HW requirements.
 885          */
 886         if (IS_CHERRYVIEW(to_i915(dev))) {
 887                 *error_ppm = 0;
 888
 889                 return calculated_clock->p > best_clock->p;
 890         }
 891
 892         if (WARN_ON_ONCE(!target_freq))
 893                 return false;
 894
 895         *error_ppm = div_u64(1000000ULL *
 896                                 abs(target_freq - calculated_clock->dot),
 897                              target_freq);
 898         /*
 899          * Prefer a better P value over a better (smaller) error if the error
 900          * is small. Ensure this preference for future configurations too by
 901          * setting the error to 0.
 902          */
 903         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 904                 *error_ppm = 0;
 905
 906                 return true;
 907         }
 908
 909         return *error_ppm + 10 < best_error_ppm;
 910 }
 911
 912 /*
 913  * Returns a set of divisors for the desired target clock with the given
 914  * refclk, or FALSE.  The returned values represent the clock equation:
 915  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 916  */
 917 static bool
 918 vlv_find_best_dpll(const struct intel_limit *limit,
 919                    struct intel_crtc_state *crtc_state,
 920                    int target, int refclk, struct dpll *match_clock,
 921                    struct dpll *best_clock)
 922 {
 923         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 924         struct drm_device *dev = crtc->base.dev;
 925         struct dpll clock;
 926         unsigned int bestppm = 1000000;
 927         /* min update 19.2 MHz */
 928         int max_n = min(limit->n.max, refclk / 19200);
 929         bool found = false;
 930
 931         target *= 5; /* fast clock */
 932
 933         memset(best_clock, 0, sizeof(*best_clock));
 934
 935         /* based on hardware requirement, prefer smaller n to precision */
 936         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 937                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 938                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 939                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 940                                 clock.p = clock.p1 * clock.p2;
 941                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 942                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 943                                         unsigned int ppm;
 944
 945                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 946                                                                      refclk * clock.m1);
 947
 948                                         vlv_calc_dpll_params(refclk, &clock);
 949
 950                                         if (!intel_PLL_is_valid(to_i915(dev),
 951                                                                 limit,
 952                                                                 &clock))
 953                                                 continue;
 954
 955                                         if (!vlv_PLL_is_optimal(dev, target,
 956                                                                 &clock,
 957                                                                 best_clock,
 958                                                                 bestppm, &ppm))
 959                                                 continue;
 960
 961                                         *best_clock = clock;
 962                                         bestppm = ppm;
 963                                         found = true;
 964                                 }
 965                         }
 966                 }
 967         }
 968
 969         return found;
 970 }
 971
 972 /*
 973  * Returns a set of divisors for the desired target clock with the given
 974  * refclk, or FALSE.  The returned values represent the clock equation:
 975  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 976  */
 977 static bool
 978 chv_find_best_dpll(const struct intel_limit *limit,
 979                    struct intel_crtc_state *crtc_state,
 980                    int target, int refclk, struct dpll *match_clock,
 981                    struct dpll *best_clock)
 982 {
 983         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 984         struct drm_device *dev = crtc->base.dev;
 985         unsigned int best_error_ppm;
 986         struct dpll clock;
 987         u64 m2;
 988         int found = false;
 989
 990         memset(best_clock, 0, sizeof(*best_clock));
 991         best_error_ppm = 1000000;
 992
 993         /*
 994          * Based on hardware doc, the n always set to 1, and m1 always
 995          * set to 2.  If requires to support 200Mhz refclk, we need to
 996          * revisit this because n may not 1 anymore.
 997          */
 998         clock.n = 1, clock.m1 = 2;
 999         target *= 5;    /* fast clock */
1000
1001         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1002                 for (clock.p2 = limit->p2.p2_fast;
1003                                 clock.p2 >= limit->p2.p2_slow;
1004                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1005                         unsigned int error_ppm;
1006
1007                         clock.p = clock.p1 * clock.p2;
1008
1009                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1010                                                    refclk * clock.m1);
1011
1012                         if (m2 > INT_MAX/clock.m1)
1013                                 continue;
1014
1015                         clock.m2 = m2;
1016
1017                         chv_calc_dpll_params(refclk, &clock);
1018
1019                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1020                                 continue;
1021
1022                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1023                                                 best_error_ppm, &error_ppm))
1024                                 continue;
1025
1026                         *best_clock = clock;
1027                         best_error_ppm = error_ppm;
1028                         found = true;
1029                 }
1030         }
1031
1032         return found;
1033 }
1034
1035 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1036                         struct dpll *best_clock)
1037 {
1038         int refclk = 100000;
1039         const struct intel_limit *limit = &intel_limits_bxt;
1040
1041         return chv_find_best_dpll(limit, crtc_state,
1042                                   crtc_state->port_clock, refclk,
1043                                   NULL, best_clock);
1044 }
1045
1046 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1047                                     enum pipe pipe)
1048 {
1049         i915_reg_t reg = PIPEDSL(pipe);
1050         u32 line1, line2;
1051         u32 line_mask;
1052
1053         if (IS_GEN(dev_priv, 2))
1054                 line_mask = DSL_LINEMASK_GEN2;
1055         else
1056                 line_mask = DSL_LINEMASK_GEN3;
1057
1058         line1 = I915_READ(reg) & line_mask;
1059         msleep(5);
1060         line2 = I915_READ(reg) & line_mask;
1061
1062         return line1 != line2;
1063 }
1064
1065 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 {
1067         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1068         enum pipe pipe = crtc->pipe;
1069
1070         /* Wait for the display line to settle/start moving */
1071         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1072                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1073                           pipe_name(pipe), onoff(state));
1074 }
1075
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1077 {
1078         wait_for_pipe_scanline_moving(crtc, false);
1079 }
1080
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1082 {
1083         wait_for_pipe_scanline_moving(crtc, true);
1084 }
1085
1086 static void
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1088 {
1089         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1091
1092         if (INTEL_GEN(dev_priv) >= 4) {
1093                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1095
1096                 /* Wait for the Pipe State to go off */
1097                 if (intel_de_wait_for_clear(dev_priv, reg,
1098                                             I965_PIPECONF_ACTIVE, 100))
1099                         WARN(1, "pipe_off wait timed out\n");
1100         } else {
1101                 intel_wait_for_pipe_scanline_stopped(crtc);
1102         }
1103 }
1104
1105 /* Only for pre-ILK configs */
1106 void assert_pll(struct drm_i915_private *dev_priv,
1107                 enum pipe pipe, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111
1112         val = I915_READ(DPLL(pipe));
1113         cur_state = !!(val & DPLL_VCO_ENABLE);
1114         I915_STATE_WARN(cur_state != state,
1115              "PLL state assertion failure (expected %s, current %s)\n",
1116                         onoff(state), onoff(cur_state));
1117 }
1118
1119 /* XXX: the dsi pll is shared between MIPI DSI ports */
1120 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1121 {
1122         u32 val;
1123         bool cur_state;
1124
1125         vlv_cck_get(dev_priv);
1126         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1127         vlv_cck_put(dev_priv);
1128
1129         cur_state = val & DSI_PLL_VCO_EN;
1130         I915_STATE_WARN(cur_state != state,
1131              "DSI PLL state assertion failure (expected %s, current %s)\n",
1132                         onoff(state), onoff(cur_state));
1133 }
1134
1135 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1136                           enum pipe pipe, bool state)
1137 {
1138         bool cur_state;
1139
1140         if (HAS_DDI(dev_priv)) {
1141                 /*
1142                  * DDI does not have a specific FDI_TX register.
1143                  *
1144                  * FDI is never fed from EDP transcoder
1145                  * so pipe->transcoder cast is fine here.
1146                  */
1147                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1148                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1149                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1150         } else {
1151                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1152                 cur_state = !!(val & FDI_TX_ENABLE);
1153         }
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI TX state assertion failure (expected %s, current %s)\n",
1156                         onoff(state), onoff(cur_state));
1157 }
1158 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1159 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1160
1161 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1162                           enum pipe pipe, bool state)
1163 {
1164         u32 val;
1165         bool cur_state;
1166
1167         val = I915_READ(FDI_RX_CTL(pipe));
1168         cur_state = !!(val & FDI_RX_ENABLE);
1169         I915_STATE_WARN(cur_state != state,
1170              "FDI RX state assertion failure (expected %s, current %s)\n",
1171                         onoff(state), onoff(cur_state));
1172 }
1173 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1174 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1175
1176 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1177                                       enum pipe pipe)
1178 {
1179         u32 val;
1180
1181         /* ILK FDI PLL is always enabled */
1182         if (IS_GEN(dev_priv, 5))
1183                 return;
1184
1185         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1186         if (HAS_DDI(dev_priv))
1187                 return;
1188
1189         val = I915_READ(FDI_TX_CTL(pipe));
1190         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1191 }
1192
1193 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1194                        enum pipe pipe, bool state)
1195 {
1196         u32 val;
1197         bool cur_state;
1198
1199         val = I915_READ(FDI_RX_CTL(pipe));
1200         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1201         I915_STATE_WARN(cur_state != state,
1202              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1203                         onoff(state), onoff(cur_state));
1204 }
1205
1206 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1207 {
1208         i915_reg_t pp_reg;
1209         u32 val;
1210         enum pipe panel_pipe = INVALID_PIPE;
1211         bool locked = true;
1212
1213         if (WARN_ON(HAS_DDI(dev_priv)))
1214                 return;
1215
1216         if (HAS_PCH_SPLIT(dev_priv)) {
1217                 u32 port_sel;
1218
1219                 pp_reg = PP_CONTROL(0);
1220                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1221
1222                 switch (port_sel) {
1223                 case PANEL_PORT_SELECT_LVDS:
1224                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1225                         break;
1226                 case PANEL_PORT_SELECT_DPA:
1227                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1228                         break;
1229                 case PANEL_PORT_SELECT_DPC:
1230                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1231                         break;
1232                 case PANEL_PORT_SELECT_DPD:
1233                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1234                         break;
1235                 default:
1236                         MISSING_CASE(port_sel);
1237                         break;
1238                 }
1239         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1240                 /* presumably write lock depends on pipe, not port select */
1241                 pp_reg = PP_CONTROL(pipe);
1242                 panel_pipe = pipe;
1243         } else {
1244                 u32 port_sel;
1245
1246                 pp_reg = PP_CONTROL(0);
1247                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1248
1249                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1250                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1251         }
1252
1253         val = I915_READ(pp_reg);
1254         if (!(val & PANEL_POWER_ON) ||
1255             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1256                 locked = false;
1257
1258         I915_STATE_WARN(panel_pipe == pipe && locked,
1259              "panel assertion failure, pipe %c regs locked\n",
1260              pipe_name(pipe));
1261 }
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264                  enum transcoder cpu_transcoder, bool state)
1265 {
1266         bool cur_state;
1267         enum intel_display_power_domain power_domain;
1268         intel_wakeref_t wakeref;
1269
1270         /* we keep both pipes enabled on 830 */
1271         if (IS_I830(dev_priv))
1272                 state = true;
1273
1274         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1275         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1276         if (wakeref) {
1277                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1278                 cur_state = !!(val & PIPECONF_ENABLE);
1279
1280                 intel_display_power_put(dev_priv, power_domain, wakeref);
1281         } else {
1282                 cur_state = false;
1283         }
1284
1285         I915_STATE_WARN(cur_state != state,
1286                         "transcoder %s assertion failure (expected %s, current %s)\n",
1287                         transcoder_name(cpu_transcoder),
1288                         onoff(state), onoff(cur_state));
1289 }
1290
1291 static void assert_plane(struct intel_plane *plane, bool state)
1292 {
1293         enum pipe pipe;
1294         bool cur_state;
1295
1296         cur_state = plane->get_hw_state(plane, &pipe);
1297
1298         I915_STATE_WARN(cur_state != state,
1299                         "%s assertion failure (expected %s, current %s)\n",
1300                         plane->base.name, onoff(state), onoff(cur_state));
1301 }
1302
1303 #define assert_plane_enabled(p) assert_plane(p, true)
1304 #define assert_plane_disabled(p) assert_plane(p, false)
1305
1306 static void assert_planes_disabled(struct intel_crtc *crtc)
1307 {
1308         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1309         struct intel_plane *plane;
1310
1311         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1312                 assert_plane_disabled(plane);
1313 }
1314
1315 static void assert_vblank_disabled(struct drm_crtc *crtc)
1316 {
1317         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1318                 drm_crtc_vblank_put(crtc);
1319 }
1320
1321 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                     enum pipe pipe)
1323 {
1324         u32 val;
1325         bool enabled;
1326
1327         val = I915_READ(PCH_TRANSCONF(pipe));
1328         enabled = !!(val & TRANS_ENABLE);
1329         I915_STATE_WARN(enabled,
1330              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331              pipe_name(pipe));
1332 }
1333
1334 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1335                                    enum pipe pipe, enum port port,
1336                                    i915_reg_t dp_reg)
1337 {
1338         enum pipe port_pipe;
1339         bool state;
1340
1341         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1342
1343         I915_STATE_WARN(state && port_pipe == pipe,
1344                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1345                         port_name(port), pipe_name(pipe));
1346
1347         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1348                         "IBX PCH DP %c still using transcoder B\n",
1349                         port_name(port));
1350 }
1351
1352 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1353                                      enum pipe pipe, enum port port,
1354                                      i915_reg_t hdmi_reg)
1355 {
1356         enum pipe port_pipe;
1357         bool state;
1358
1359         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1360
1361         I915_STATE_WARN(state && port_pipe == pipe,
1362                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1363                         port_name(port), pipe_name(pipe));
1364
1365         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1366                         "IBX PCH HDMI %c still using transcoder B\n",
1367                         port_name(port));
1368 }
1369
1370 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1371                                       enum pipe pipe)
1372 {
1373         enum pipe port_pipe;
1374
1375         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1376         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1377         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1378
1379         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1380                         port_pipe == pipe,
1381                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1382                         pipe_name(pipe));
1383
1384         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1385                         port_pipe == pipe,
1386                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1387                         pipe_name(pipe));
1388
1389         /* PCH SDVOB multiplex with HDMIB */
1390         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1391         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1392         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1393 }
1394
1395 static void _vlv_enable_pll(struct intel_crtc *crtc,
1396                             const struct intel_crtc_state *pipe_config)
1397 {
1398         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1399         enum pipe pipe = crtc->pipe;
1400
1401         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1402         POSTING_READ(DPLL(pipe));
1403         udelay(150);
1404
1405         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1406                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1407 }
1408
1409 static void vlv_enable_pll(struct intel_crtc *crtc,
1410                            const struct intel_crtc_state *pipe_config)
1411 {
1412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1413         enum pipe pipe = crtc->pipe;
1414
1415         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1416
1417         /* PLL is protected by panel, make sure we can write it */
1418         assert_panel_unlocked(dev_priv, pipe);
1419
1420         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1421                 _vlv_enable_pll(crtc, pipe_config);
1422
1423         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1424         POSTING_READ(DPLL_MD(pipe));
1425 }
1426
1427
1428 static void _chv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1434         u32 tmp;
1435
1436         vlv_dpio_get(dev_priv);
1437
1438         /* Enable back the 10bit clock to display controller */
1439         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1440         tmp |= DPIO_DCLKP_EN;
1441         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1442
1443         vlv_dpio_put(dev_priv);
1444
1445         /*
1446          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1447          */
1448         udelay(1);
1449
1450         /* Enable PLL */
1451         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1452
1453         /* Check PLL is locked */
1454         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1455                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1456 }
1457
1458 static void chv_enable_pll(struct intel_crtc *crtc,
1459                            const struct intel_crtc_state *pipe_config)
1460 {
1461         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1462         enum pipe pipe = crtc->pipe;
1463
1464         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1465
1466         /* PLL is protected by panel, make sure we can write it */
1467         assert_panel_unlocked(dev_priv, pipe);
1468
1469         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1470                 _chv_enable_pll(crtc, pipe_config);
1471
1472         if (pipe != PIPE_A) {
1473                 /*
1474                  * WaPixelRepeatModeFixForC0:chv
1475                  *
1476                  * DPLLCMD is AWOL. Use chicken bits to propagate
1477                  * the value from DPLLBMD to either pipe B or C.
1478                  */
1479                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1480                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1481                 I915_WRITE(CBR4_VLV, 0);
1482                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1483
1484                 /*
1485                  * DPLLB VGA mode also seems to cause problems.
1486                  * We should always have it disabled.
1487                  */
1488                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1489         } else {
1490                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1491                 POSTING_READ(DPLL_MD(pipe));
1492         }
1493 }
1494
1495 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1496 {
1497         if (IS_I830(dev_priv))
1498                 return false;
1499
1500         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1501 }
1502
1503 static void i9xx_enable_pll(struct intel_crtc *crtc,
1504                             const struct intel_crtc_state *crtc_state)
1505 {
1506         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1507         i915_reg_t reg = DPLL(crtc->pipe);
1508         u32 dpll = crtc_state->dpll_hw_state.dpll;
1509         int i;
1510
1511         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1512
1513         /* PLL is protected by panel, make sure we can write it */
1514         if (i9xx_has_pps(dev_priv))
1515                 assert_panel_unlocked(dev_priv, crtc->pipe);
1516
1517         /*
1518          * Apparently we need to have VGA mode enabled prior to changing
1519          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1520          * dividers, even though the register value does change.
1521          */
1522         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1523         I915_WRITE(reg, dpll);
1524
1525         /* Wait for the clocks to stabilize. */
1526         POSTING_READ(reg);
1527         udelay(150);
1528
1529         if (INTEL_GEN(dev_priv) >= 4) {
1530                 I915_WRITE(DPLL_MD(crtc->pipe),
1531                            crtc_state->dpll_hw_state.dpll_md);
1532         } else {
1533                 /* The pixel multiplier can only be updated once the
1534                  * DPLL is enabled and the clocks are stable.
1535                  *
1536                  * So write it again.
1537                  */
1538                 I915_WRITE(reg, dpll);
1539         }
1540
1541         /* We do this three times for luck */
1542         for (i = 0; i < 3; i++) {
1543                 I915_WRITE(reg, dpll);
1544                 POSTING_READ(reg);
1545                 udelay(150); /* wait for warmup */
1546         }
1547 }
1548
1549 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1550 {
1551         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1552         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1553         enum pipe pipe = crtc->pipe;
1554
1555         /* Don't disable pipe or pipe PLLs if needed */
1556         if (IS_I830(dev_priv))
1557                 return;
1558
1559         /* Make sure the pipe isn't still relying on us */
1560         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1561
1562         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1563         POSTING_READ(DPLL(pipe));
1564 }
1565
1566 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1567 {
1568         u32 val;
1569
1570         /* Make sure the pipe isn't still relying on us */
1571         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1572
1573         val = DPLL_INTEGRATED_REF_CLK_VLV |
1574                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1575         if (pipe != PIPE_A)
1576                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1577
1578         I915_WRITE(DPLL(pipe), val);
1579         POSTING_READ(DPLL(pipe));
1580 }
1581
1582 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1583 {
1584         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1585         u32 val;
1586
1587         /* Make sure the pipe isn't still relying on us */
1588         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1589
1590         val = DPLL_SSC_REF_CLK_CHV |
1591                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1592         if (pipe != PIPE_A)
1593                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1594
1595         I915_WRITE(DPLL(pipe), val);
1596         POSTING_READ(DPLL(pipe));
1597
1598         vlv_dpio_get(dev_priv);
1599
1600         /* Disable 10bit clock to display controller */
1601         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1602         val &= ~DPIO_DCLKP_EN;
1603         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1604
1605         vlv_dpio_put(dev_priv);
1606 }
1607
1608 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1609                          struct intel_digital_port *dport,
1610                          unsigned int expected_mask)
1611 {
1612         u32 port_mask;
1613         i915_reg_t dpll_reg;
1614
1615         switch (dport->base.port) {
1616         case PORT_B:
1617                 port_mask = DPLL_PORTB_READY_MASK;
1618                 dpll_reg = DPLL(0);
1619                 break;
1620         case PORT_C:
1621                 port_mask = DPLL_PORTC_READY_MASK;
1622                 dpll_reg = DPLL(0);
1623                 expected_mask <<= 4;
1624                 break;
1625         case PORT_D:
1626                 port_mask = DPLL_PORTD_READY_MASK;
1627                 dpll_reg = DPIO_PHY_STATUS;
1628                 break;
1629         default:
1630                 BUG();
1631         }
1632
1633         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1634                                        port_mask, expected_mask, 1000))
1635                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1636                      dport->base.base.base.id, dport->base.base.name,
1637                      I915_READ(dpll_reg) & port_mask, expected_mask);
1638 }
1639
1640 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1641 {
1642         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1643         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1644         enum pipe pipe = crtc->pipe;
1645         i915_reg_t reg;
1646         u32 val, pipeconf_val;
1647
1648         /* Make sure PCH DPLL is enabled */
1649         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1650
1651         /* FDI must be feeding us bits for PCH ports */
1652         assert_fdi_tx_enabled(dev_priv, pipe);
1653         assert_fdi_rx_enabled(dev_priv, pipe);
1654
1655         if (HAS_PCH_CPT(dev_priv)) {
1656                 reg = TRANS_CHICKEN2(pipe);
1657                 val = I915_READ(reg);
1658                 /*
1659                  * Workaround: Set the timing override bit
1660                  * before enabling the pch transcoder.
1661                  */
1662                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1663                 /* Configure frame start delay to match the CPU */
1664                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1665                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1666                 I915_WRITE(reg, val);
1667         }
1668
1669         reg = PCH_TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv)) {
1674                 /* Configure frame start delay to match the CPU */
1675                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1676                 val |= TRANS_FRAME_START_DELAY(0);
1677
1678                 /*
1679                  * Make the BPC in transcoder be consistent with
1680                  * that in pipeconf reg. For HDMI we must use 8bpc
1681                  * here for both 8bpc and 12bpc.
1682                  */
1683                 val &= ~PIPECONF_BPC_MASK;
1684                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1685                         val |= PIPECONF_8BPC;
1686                 else
1687                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1688         }
1689
1690         val &= ~TRANS_INTERLACE_MASK;
1691         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1692                 if (HAS_PCH_IBX(dev_priv) &&
1693                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1694                         val |= TRANS_LEGACY_INTERLACED_ILK;
1695                 else
1696                         val |= TRANS_INTERLACED;
1697         } else {
1698                 val |= TRANS_PROGRESSIVE;
1699         }
1700
1701         I915_WRITE(reg, val | TRANS_ENABLE);
1702         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1703                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1704 }
1705
1706 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1707                                       enum transcoder cpu_transcoder)
1708 {
1709         u32 val, pipeconf_val;
1710
1711         /* FDI must be feeding us bits for PCH ports */
1712         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1713         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1714
1715         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1716         /* Workaround: set timing override bit. */
1717         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1718         /* Configure frame start delay to match the CPU */
1719         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1720         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1721         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1722
1723         val = TRANS_ENABLE;
1724         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1725
1726         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1727             PIPECONF_INTERLACED_ILK)
1728                 val |= TRANS_INTERLACED;
1729         else
1730                 val |= TRANS_PROGRESSIVE;
1731
1732         I915_WRITE(LPT_TRANSCONF, val);
1733         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1734                                   TRANS_STATE_ENABLE, 100))
1735                 DRM_ERROR("Failed to enable PCH transcoder\n");
1736 }
1737
1738 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1739                                             enum pipe pipe)
1740 {
1741         i915_reg_t reg;
1742         u32 val;
1743
1744         /* FDI relies on the transcoder */
1745         assert_fdi_tx_disabled(dev_priv, pipe);
1746         assert_fdi_rx_disabled(dev_priv, pipe);
1747
1748         /* Ports must be off as well */
1749         assert_pch_ports_disabled(dev_priv, pipe);
1750
1751         reg = PCH_TRANSCONF(pipe);
1752         val = I915_READ(reg);
1753         val &= ~TRANS_ENABLE;
1754         I915_WRITE(reg, val);
1755         /* wait for PCH transcoder off, transcoder state */
1756         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1757                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1758
1759         if (HAS_PCH_CPT(dev_priv)) {
1760                 /* Workaround: Clear the timing override chicken bit again. */
1761                 reg = TRANS_CHICKEN2(pipe);
1762                 val = I915_READ(reg);
1763                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1764                 I915_WRITE(reg, val);
1765         }
1766 }
1767
1768 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1769 {
1770         u32 val;
1771
1772         val = I915_READ(LPT_TRANSCONF);
1773         val &= ~TRANS_ENABLE;
1774         I915_WRITE(LPT_TRANSCONF, val);
1775         /* wait for PCH transcoder off, transcoder state */
1776         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1777                                     TRANS_STATE_ENABLE, 50))
1778                 DRM_ERROR("Failed to disable PCH transcoder\n");
1779
1780         /* Workaround: clear timing override bit. */
1781         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1782         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1783         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1784 }
1785
1786 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1787 {
1788         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1789
1790         if (HAS_PCH_LPT(dev_priv))
1791                 return PIPE_A;
1792         else
1793                 return crtc->pipe;
1794 }
1795
1796 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1797 {
1798         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1799
1800         /*
1801          * On i965gm the hardware frame counter reads
1802          * zero when the TV encoder is enabled :(
1803          */
1804         if (IS_I965GM(dev_priv) &&
1805             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1806                 return 0;
1807
1808         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1809                 return 0xffffffff; /* full 32 bit counter */
1810         else if (INTEL_GEN(dev_priv) >= 3)
1811                 return 0xffffff; /* only 24 bits of frame count */
1812         else
1813                 return 0; /* Gen2 doesn't have a hardware frame counter */
1814 }
1815
1816 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1817 {
1818         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1819
1820         assert_vblank_disabled(&crtc->base);
1821         drm_crtc_set_max_vblank_count(&crtc->base,
1822                                       intel_crtc_max_vblank_count(crtc_state));
1823         drm_crtc_vblank_on(&crtc->base);
1824 }
1825
1826 static void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1827 {
1828         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1829
1830         drm_crtc_vblank_off(&crtc->base);
1831         assert_vblank_disabled(&crtc->base);
1832 }
1833
1834 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1835 {
1836         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1837         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1838         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1839         enum pipe pipe = crtc->pipe;
1840         i915_reg_t reg;
1841         u32 val;
1842
1843         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1844
1845         assert_planes_disabled(crtc);
1846
1847         /*
1848          * A pipe without a PLL won't actually be able to drive bits from
1849          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1850          * need the check.
1851          */
1852         if (HAS_GMCH(dev_priv)) {
1853                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1854                         assert_dsi_pll_enabled(dev_priv);
1855                 else
1856                         assert_pll_enabled(dev_priv, pipe);
1857         } else {
1858                 if (new_crtc_state->has_pch_encoder) {
1859                         /* if driving the PCH, we need FDI enabled */
1860                         assert_fdi_rx_pll_enabled(dev_priv,
1861                                                   intel_crtc_pch_transcoder(crtc));
1862                         assert_fdi_tx_pll_enabled(dev_priv,
1863                                                   (enum pipe) cpu_transcoder);
1864                 }
1865                 /* FIXME: assert CPU port conditions for SNB+ */
1866         }
1867
1868         trace_intel_pipe_enable(crtc);
1869
1870         reg = PIPECONF(cpu_transcoder);
1871         val = I915_READ(reg);
1872         if (val & PIPECONF_ENABLE) {
1873                 /* we keep both pipes enabled on 830 */
1874                 WARN_ON(!IS_I830(dev_priv));
1875                 return;
1876         }
1877
1878         I915_WRITE(reg, val | PIPECONF_ENABLE);
1879         POSTING_READ(reg);
1880
1881         /*
1882          * Until the pipe starts PIPEDSL reads will return a stale value,
1883          * which causes an apparent vblank timestamp jump when PIPEDSL
1884          * resets to its proper value. That also messes up the frame count
1885          * when it's derived from the timestamps. So let's wait for the
1886          * pipe to start properly before we call drm_crtc_vblank_on()
1887          */
1888         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1889                 intel_wait_for_pipe_scanline_moving(crtc);
1890 }
1891
1892 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1893 {
1894         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1895         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1897         enum pipe pipe = crtc->pipe;
1898         i915_reg_t reg;
1899         u32 val;
1900
1901         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1902
1903         /*
1904          * Make sure planes won't keep trying to pump pixels to us,
1905          * or we might hang the display.
1906          */
1907         assert_planes_disabled(crtc);
1908
1909         trace_intel_pipe_disable(crtc);
1910
1911         reg = PIPECONF(cpu_transcoder);
1912         val = I915_READ(reg);
1913         if ((val & PIPECONF_ENABLE) == 0)
1914                 return;
1915
1916         /*
1917          * Double wide has implications for planes
1918          * so best keep it disabled when not needed.
1919          */
1920         if (old_crtc_state->double_wide)
1921                 val &= ~PIPECONF_DOUBLE_WIDE;
1922
1923         /* Don't disable pipe or pipe PLLs if needed */
1924         if (!IS_I830(dev_priv))
1925                 val &= ~PIPECONF_ENABLE;
1926
1927         I915_WRITE(reg, val);
1928         if ((val & PIPECONF_ENABLE) == 0)
1929                 intel_wait_for_pipe_off(old_crtc_state);
1930 }
1931
1932 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1933 {
1934         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1935 }
1936
1937 static unsigned int
1938 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1939 {
1940         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1941         unsigned int cpp = fb->format->cpp[color_plane];
1942
1943         switch (fb->modifier) {
1944         case DRM_FORMAT_MOD_LINEAR:
1945                 return intel_tile_size(dev_priv);
1946         case I915_FORMAT_MOD_X_TILED:
1947                 if (IS_GEN(dev_priv, 2))
1948                         return 128;
1949                 else
1950                         return 512;
1951         case I915_FORMAT_MOD_Y_TILED_CCS:
1952                 if (color_plane == 1)
1953                         return 128;
1954                 /* fall through */
1955         case I915_FORMAT_MOD_Y_TILED:
1956                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1957                         return 128;
1958                 else
1959                         return 512;
1960         case I915_FORMAT_MOD_Yf_TILED_CCS:
1961                 if (color_plane == 1)
1962                         return 128;
1963                 /* fall through */
1964         case I915_FORMAT_MOD_Yf_TILED:
1965                 switch (cpp) {
1966                 case 1:
1967                         return 64;
1968                 case 2:
1969                 case 4:
1970                         return 128;
1971                 case 8:
1972                 case 16:
1973                         return 256;
1974                 default:
1975                         MISSING_CASE(cpp);
1976                         return cpp;
1977                 }
1978                 break;
1979         default:
1980                 MISSING_CASE(fb->modifier);
1981                 return cpp;
1982         }
1983 }
1984
1985 static unsigned int
1986 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1987 {
1988         return intel_tile_size(to_i915(fb->dev)) /
1989                 intel_tile_width_bytes(fb, color_plane);
1990 }
1991
1992 /* Return the tile dimensions in pixel units */
1993 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1994                             unsigned int *tile_width,
1995                             unsigned int *tile_height)
1996 {
1997         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1998         unsigned int cpp = fb->format->cpp[color_plane];
1999
2000         *tile_width = tile_width_bytes / cpp;
2001         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2002 }
2003
2004 unsigned int
2005 intel_fb_align_height(const struct drm_framebuffer *fb,
2006                       int color_plane, unsigned int height)
2007 {
2008         unsigned int tile_height = intel_tile_height(fb, color_plane);
2009
2010         return ALIGN(height, tile_height);
2011 }
2012
2013 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2014 {
2015         unsigned int size = 0;
2016         int i;
2017
2018         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2019                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2020
2021         return size;
2022 }
2023
2024 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2025 {
2026         unsigned int size = 0;
2027         int i;
2028
2029         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2030                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2031
2032         return size;
2033 }
2034
2035 static void
2036 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2037                         const struct drm_framebuffer *fb,
2038                         unsigned int rotation)
2039 {
2040         view->type = I915_GGTT_VIEW_NORMAL;
2041         if (drm_rotation_90_or_270(rotation)) {
2042                 view->type = I915_GGTT_VIEW_ROTATED;
2043                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2044         }
2045 }
2046
2047 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2048 {
2049         if (IS_I830(dev_priv))
2050                 return 16 * 1024;
2051         else if (IS_I85X(dev_priv))
2052                 return 256;
2053         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2054                 return 32;
2055         else
2056                 return 4 * 1024;
2057 }
2058
2059 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2060 {
2061         if (INTEL_GEN(dev_priv) >= 9)
2062                 return 256 * 1024;
2063         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2064                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2065                 return 128 * 1024;
2066         else if (INTEL_GEN(dev_priv) >= 4)
2067                 return 4 * 1024;
2068         else
2069                 return 0;
2070 }
2071
2072 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2073                                          int color_plane)
2074 {
2075         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2076
2077         /* AUX_DIST needs only 4K alignment */
2078         if (color_plane == 1)
2079                 return 4096;
2080
2081         switch (fb->modifier) {
2082         case DRM_FORMAT_MOD_LINEAR:
2083                 return intel_linear_alignment(dev_priv);
2084         case I915_FORMAT_MOD_X_TILED:
2085                 if (INTEL_GEN(dev_priv) >= 9)
2086                         return 256 * 1024;
2087                 return 0;
2088         case I915_FORMAT_MOD_Y_TILED_CCS:
2089         case I915_FORMAT_MOD_Yf_TILED_CCS:
2090         case I915_FORMAT_MOD_Y_TILED:
2091         case I915_FORMAT_MOD_Yf_TILED:
2092                 return 1 * 1024 * 1024;
2093         default:
2094                 MISSING_CASE(fb->modifier);
2095                 return 0;
2096         }
2097 }
2098
2099 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2100 {
2101         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2102         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2103
2104         return INTEL_GEN(dev_priv) < 4 ||
2105                 (plane->has_fbc &&
2106                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2107 }
2108
2109 struct i915_vma *
2110 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2111                            const struct i915_ggtt_view *view,
2112                            bool uses_fence,
2113                            unsigned long *out_flags)
2114 {
2115         struct drm_device *dev = fb->dev;
2116         struct drm_i915_private *dev_priv = to_i915(dev);
2117         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2118         intel_wakeref_t wakeref;
2119         struct i915_vma *vma;
2120         unsigned int pinctl;
2121         u32 alignment;
2122
2123         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2124                 return ERR_PTR(-EINVAL);
2125
2126         alignment = intel_surf_alignment(fb, 0);
2127
2128         /* Note that the w/a also requires 64 PTE of padding following the
2129          * bo. We currently fill all unused PTE with the shadow page and so
2130          * we should always have valid PTE following the scanout preventing
2131          * the VT-d warning.
2132          */
2133         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2134                 alignment = 256 * 1024;
2135
2136         /*
2137          * Global gtt pte registers are special registers which actually forward
2138          * writes to a chunk of system memory. Which means that there is no risk
2139          * that the register values disappear as soon as we call
2140          * intel_runtime_pm_put(), so it is correct to wrap only the
2141          * pin/unpin/fence and not more.
2142          */
2143         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2144
2145         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2146
2147         /*
2148          * Valleyview is definitely limited to scanning out the first
2149          * 512MiB. Lets presume this behaviour was inherited from the
2150          * g4x display engine and that all earlier gen are similarly
2151          * limited. Testing suggests that it is a little more
2152          * complicated than this. For example, Cherryview appears quite
2153          * happy to scanout from anywhere within its global aperture.
2154          */
2155         pinctl = 0;
2156         if (HAS_GMCH(dev_priv))
2157                 pinctl |= PIN_MAPPABLE;
2158
2159         vma = i915_gem_object_pin_to_display_plane(obj,
2160                                                    alignment, view, pinctl);
2161         if (IS_ERR(vma))
2162                 goto err;
2163
2164         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2165                 int ret;
2166
2167                 /*
2168                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2169                  * fence, whereas 965+ only requires a fence if using
2170                  * framebuffer compression.  For simplicity, we always, when
2171                  * possible, install a fence as the cost is not that onerous.
2172                  *
2173                  * If we fail to fence the tiled scanout, then either the
2174                  * modeset will reject the change (which is highly unlikely as
2175                  * the affected systems, all but one, do not have unmappable
2176                  * space) or we will not be able to enable full powersaving
2177                  * techniques (also likely not to apply due to various limits
2178                  * FBC and the like impose on the size of the buffer, which
2179                  * presumably we violated anyway with this unmappable buffer).
2180                  * Anyway, it is presumably better to stumble onwards with
2181                  * something and try to run the system in a "less than optimal"
2182                  * mode that matches the user configuration.
2183                  */
2184                 ret = i915_vma_pin_fence(vma);
2185                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2186                         i915_gem_object_unpin_from_display_plane(vma);
2187                         vma = ERR_PTR(ret);
2188                         goto err;
2189                 }
2190
2191                 if (ret == 0 && vma->fence)
2192                         *out_flags |= PLANE_HAS_FENCE;
2193         }
2194
2195         i915_vma_get(vma);
2196 err:
2197         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2198         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2199         return vma;
2200 }
2201
2202 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2203 {
2204         i915_gem_object_lock(vma->obj);
2205         if (flags & PLANE_HAS_FENCE)
2206                 i915_vma_unpin_fence(vma);
2207         i915_gem_object_unpin_from_display_plane(vma);
2208         i915_gem_object_unlock(vma->obj);
2209
2210         i915_vma_put(vma);
2211 }
2212
2213 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2214                           unsigned int rotation)
2215 {
2216         if (drm_rotation_90_or_270(rotation))
2217                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2218         else
2219                 return fb->pitches[color_plane];
2220 }
2221
2222 /*
2223  * Convert the x/y offsets into a linear offset.
2224  * Only valid with 0/180 degree rotation, which is fine since linear
2225  * offset is only used with linear buffers on pre-hsw and tiled buffers
2226  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2227  */
2228 u32 intel_fb_xy_to_linear(int x, int y,
2229                           const struct intel_plane_state *state,
2230                           int color_plane)
2231 {
2232         const struct drm_framebuffer *fb = state->hw.fb;
2233         unsigned int cpp = fb->format->cpp[color_plane];
2234         unsigned int pitch = state->color_plane[color_plane].stride;
2235
2236         return y * pitch + x * cpp;
2237 }
2238
2239 /*
2240  * Add the x/y offsets derived from fb->offsets[] to the user
2241  * specified plane src x/y offsets. The resulting x/y offsets
2242  * specify the start of scanout from the beginning of the gtt mapping.
2243  */
2244 void intel_add_fb_offsets(int *x, int *y,
2245                           const struct intel_plane_state *state,
2246                           int color_plane)
2247
2248 {
2249         *x += state->color_plane[color_plane].x;
2250         *y += state->color_plane[color_plane].y;
2251 }
2252
2253 static u32 intel_adjust_tile_offset(int *x, int *y,
2254                                     unsigned int tile_width,
2255                                     unsigned int tile_height,
2256                                     unsigned int tile_size,
2257                                     unsigned int pitch_tiles,
2258                                     u32 old_offset,
2259                                     u32 new_offset)
2260 {
2261         unsigned int pitch_pixels = pitch_tiles * tile_width;
2262         unsigned int tiles;
2263
2264         WARN_ON(old_offset & (tile_size - 1));
2265         WARN_ON(new_offset & (tile_size - 1));
2266         WARN_ON(new_offset > old_offset);
2267
2268         tiles = (old_offset - new_offset) / tile_size;
2269
2270         *y += tiles / pitch_tiles * tile_height;
2271         *x += tiles % pitch_tiles * tile_width;
2272
2273         /* minimize x in case it got needlessly big */
2274         *y += *x / pitch_pixels * tile_height;
2275         *x %= pitch_pixels;
2276
2277         return new_offset;
2278 }
2279
2280 static bool is_surface_linear(u64 modifier, int color_plane)
2281 {
2282         return modifier == DRM_FORMAT_MOD_LINEAR;
2283 }
2284
2285 static u32 intel_adjust_aligned_offset(int *x, int *y,
2286                                        const struct drm_framebuffer *fb,
2287                                        int color_plane,
2288                                        unsigned int rotation,
2289                                        unsigned int pitch,
2290                                        u32 old_offset, u32 new_offset)
2291 {
2292         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2293         unsigned int cpp = fb->format->cpp[color_plane];
2294
2295         WARN_ON(new_offset > old_offset);
2296
2297         if (!is_surface_linear(fb->modifier, color_plane)) {
2298                 unsigned int tile_size, tile_width, tile_height;
2299                 unsigned int pitch_tiles;
2300
2301                 tile_size = intel_tile_size(dev_priv);
2302                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2303
2304                 if (drm_rotation_90_or_270(rotation)) {
2305                         pitch_tiles = pitch / tile_height;
2306                         swap(tile_width, tile_height);
2307                 } else {
2308                         pitch_tiles = pitch / (tile_width * cpp);
2309                 }
2310
2311                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2312                                          tile_size, pitch_tiles,
2313                                          old_offset, new_offset);
2314         } else {
2315                 old_offset += *y * pitch + *x * cpp;
2316
2317                 *y = (old_offset - new_offset) / pitch;
2318                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2319         }
2320
2321         return new_offset;
2322 }
2323
2324 /*
2325  * Adjust the tile offset by moving the difference into
2326  * the x/y offsets.
2327  */
2328 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2329                                              const struct intel_plane_state *state,
2330                                              int color_plane,
2331                                              u32 old_offset, u32 new_offset)
2332 {
2333         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2334                                            state->hw.rotation,
2335                                            state->color_plane[color_plane].stride,
2336                                            old_offset, new_offset);
2337 }
2338
2339 /*
2340  * Computes the aligned offset to the base tile and adjusts
2341  * x, y. bytes per pixel is assumed to be a power-of-two.
2342  *
2343  * In the 90/270 rotated case, x and y are assumed
2344  * to be already rotated to match the rotated GTT view, and
2345  * pitch is the tile_height aligned framebuffer height.
2346  *
2347  * This function is used when computing the derived information
2348  * under intel_framebuffer, so using any of that information
2349  * here is not allowed. Anything under drm_framebuffer can be
2350  * used. This is why the user has to pass in the pitch since it
2351  * is specified in the rotated orientation.
2352  */
2353 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2354                                         int *x, int *y,
2355                                         const struct drm_framebuffer *fb,
2356                                         int color_plane,
2357                                         unsigned int pitch,
2358                                         unsigned int rotation,
2359                                         u32 alignment)
2360 {
2361         unsigned int cpp = fb->format->cpp[color_plane];
2362         u32 offset, offset_aligned;
2363
2364         if (alignment)
2365                 alignment--;
2366
2367         if (!is_surface_linear(fb->modifier, color_plane)) {
2368                 unsigned int tile_size, tile_width, tile_height;
2369                 unsigned int tile_rows, tiles, pitch_tiles;
2370
2371                 tile_size = intel_tile_size(dev_priv);
2372                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2373
2374                 if (drm_rotation_90_or_270(rotation)) {
2375                         pitch_tiles = pitch / tile_height;
2376                         swap(tile_width, tile_height);
2377                 } else {
2378                         pitch_tiles = pitch / (tile_width * cpp);
2379                 }
2380
2381                 tile_rows = *y / tile_height;
2382                 *y %= tile_height;
2383
2384                 tiles = *x / tile_width;
2385                 *x %= tile_width;
2386
2387                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2388                 offset_aligned = offset & ~alignment;
2389
2390                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2391                                          tile_size, pitch_tiles,
2392                                          offset, offset_aligned);
2393         } else {
2394                 offset = *y * pitch + *x * cpp;
2395                 offset_aligned = offset & ~alignment;
2396
2397                 *y = (offset & alignment) / pitch;
2398                 *x = ((offset & alignment) - *y * pitch) / cpp;
2399         }
2400
2401         return offset_aligned;
2402 }
2403
2404 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2405                                               const struct intel_plane_state *state,
2406                                               int color_plane)
2407 {
2408         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2409         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2410         const struct drm_framebuffer *fb = state->hw.fb;
2411         unsigned int rotation = state->hw.rotation;
2412         int pitch = state->color_plane[color_plane].stride;
2413         u32 alignment;
2414
2415         if (intel_plane->id == PLANE_CURSOR)
2416                 alignment = intel_cursor_alignment(dev_priv);
2417         else
2418                 alignment = intel_surf_alignment(fb, color_plane);
2419
2420         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2421                                             pitch, rotation, alignment);
2422 }
2423
2424 /* Convert the fb->offset[] into x/y offsets */
2425 static int intel_fb_offset_to_xy(int *x, int *y,
2426                                  const struct drm_framebuffer *fb,
2427                                  int color_plane)
2428 {
2429         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2430         unsigned int height;
2431
2432         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2433             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2434                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2435                               fb->offsets[color_plane], color_plane);
2436                 return -EINVAL;
2437         }
2438
2439         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2440         height = ALIGN(height, intel_tile_height(fb, color_plane));
2441
2442         /* Catch potential overflows early */
2443         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2444                             fb->offsets[color_plane])) {
2445                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2446                               fb->offsets[color_plane], fb->pitches[color_plane],
2447                               color_plane);
2448                 return -ERANGE;
2449         }
2450
2451         *x = 0;
2452         *y = 0;
2453
2454         intel_adjust_aligned_offset(x, y,
2455                                     fb, color_plane, DRM_MODE_ROTATE_0,
2456                                     fb->pitches[color_plane],
2457                                     fb->offsets[color_plane], 0);
2458
2459         return 0;
2460 }
2461
2462 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2463 {
2464         switch (fb_modifier) {
2465         case I915_FORMAT_MOD_X_TILED:
2466                 return I915_TILING_X;
2467         case I915_FORMAT_MOD_Y_TILED:
2468         case I915_FORMAT_MOD_Y_TILED_CCS:
2469                 return I915_TILING_Y;
2470         default:
2471                 return I915_TILING_NONE;
2472         }
2473 }
2474
2475 /*
2476  * From the Sky Lake PRM:
2477  * "The Color Control Surface (CCS) contains the compression status of
2478  *  the cache-line pairs. The compression state of the cache-line pair
2479  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2480  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2481  *  cache-line-pairs. CCS is always Y tiled."
2482  *
2483  * Since cache line pairs refers to horizontally adjacent cache lines,
2484  * each cache line in the CCS corresponds to an area of 32x16 cache
2485  * lines on the main surface. Since each pixel is 4 bytes, this gives
2486  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2487  * main surface.
2488  */
2489 static const struct drm_format_info ccs_formats[] = {
2490         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2491           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2492         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2493           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2494         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2495           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2496         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2497           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2498 };
2499
2500 static const struct drm_format_info *
2501 lookup_format_info(const struct drm_format_info formats[],
2502                    int num_formats, u32 format)
2503 {
2504         int i;
2505
2506         for (i = 0; i < num_formats; i++) {
2507                 if (formats[i].format == format)
2508                         return &formats[i];
2509         }
2510
2511         return NULL;
2512 }
2513
2514 static const struct drm_format_info *
2515 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2516 {
2517         switch (cmd->modifier[0]) {
2518         case I915_FORMAT_MOD_Y_TILED_CCS:
2519         case I915_FORMAT_MOD_Yf_TILED_CCS:
2520                 return lookup_format_info(ccs_formats,
2521                                           ARRAY_SIZE(ccs_formats),
2522                                           cmd->pixel_format);
2523         default:
2524                 return NULL;
2525         }
2526 }
2527
2528 bool is_ccs_modifier(u64 modifier)
2529 {
2530         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2531                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2532 }
2533
2534 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2535                               u32 pixel_format, u64 modifier)
2536 {
2537         struct intel_crtc *crtc;
2538         struct intel_plane *plane;
2539
2540         /*
2541          * We assume the primary plane for pipe A has
2542          * the highest stride limits of them all.
2543          */
2544         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2545         if (!crtc)
2546                 return 0;
2547
2548         plane = to_intel_plane(crtc->base.primary);
2549
2550         return plane->max_stride(plane, pixel_format, modifier,
2551                                  DRM_MODE_ROTATE_0);
2552 }
2553
2554 static
2555 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2556                         u32 pixel_format, u64 modifier)
2557 {
2558         /*
2559          * Arbitrary limit for gen4+ chosen to match the
2560          * render engine max stride.
2561          *
2562          * The new CCS hash mode makes remapping impossible
2563          */
2564         if (!is_ccs_modifier(modifier)) {
2565                 if (INTEL_GEN(dev_priv) >= 7)
2566                         return 256*1024;
2567                 else if (INTEL_GEN(dev_priv) >= 4)
2568                         return 128*1024;
2569         }
2570
2571         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2572 }
2573
2574 static u32
2575 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2576 {
2577         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2578
2579         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2580                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2581                                                            fb->format->format,
2582                                                            fb->modifier);
2583
2584                 /*
2585                  * To make remapping with linear generally feasible
2586                  * we need the stride to be page aligned.
2587                  */
2588                 if (fb->pitches[color_plane] > max_stride)
2589                         return intel_tile_size(dev_priv);
2590                 else
2591                         return 64;
2592         } else {
2593                 return intel_tile_width_bytes(fb, color_plane);
2594         }
2595 }
2596
2597 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2598 {
2599         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2600         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2601         const struct drm_framebuffer *fb = plane_state->hw.fb;
2602         int i;
2603
2604         /* We don't want to deal with remapping with cursors */
2605         if (plane->id == PLANE_CURSOR)
2606                 return false;
2607
2608         /*
2609          * The display engine limits already match/exceed the
2610          * render engine limits, so not much point in remapping.
2611          * Would also need to deal with the fence POT alignment
2612          * and gen2 2KiB GTT tile size.
2613          */
2614         if (INTEL_GEN(dev_priv) < 4)
2615                 return false;
2616
2617         /*
2618          * The new CCS hash mode isn't compatible with remapping as
2619          * the virtual address of the pages affects the compressed data.
2620          */
2621         if (is_ccs_modifier(fb->modifier))
2622                 return false;
2623
2624         /* Linear needs a page aligned stride for remapping */
2625         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2626                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2627
2628                 for (i = 0; i < fb->format->num_planes; i++) {
2629                         if (fb->pitches[i] & alignment)
2630                                 return false;
2631                 }
2632         }
2633
2634         return true;
2635 }
2636
2637 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2638 {
2639         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2640         const struct drm_framebuffer *fb = plane_state->hw.fb;
2641         unsigned int rotation = plane_state->hw.rotation;
2642         u32 stride, max_stride;
2643
2644         /*
2645          * No remapping for invisible planes since we don't have
2646          * an actual source viewport to remap.
2647          */
2648         if (!plane_state->uapi.visible)
2649                 return false;
2650
2651         if (!intel_plane_can_remap(plane_state))
2652                 return false;
2653
2654         /*
2655          * FIXME: aux plane limits on gen9+ are
2656          * unclear in Bspec, for now no checking.
2657          */
2658         stride = intel_fb_pitch(fb, 0, rotation);
2659         max_stride = plane->max_stride(plane, fb->format->format,
2660                                        fb->modifier, rotation);
2661
2662         return stride > max_stride;
2663 }
2664
2665 static int
2666 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2667                    struct drm_framebuffer *fb)
2668 {
2669         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2670         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2671         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2672         u32 gtt_offset_rotated = 0;
2673         unsigned int max_size = 0;
2674         int i, num_planes = fb->format->num_planes;
2675         unsigned int tile_size = intel_tile_size(dev_priv);
2676
2677         for (i = 0; i < num_planes; i++) {
2678                 unsigned int width, height;
2679                 unsigned int cpp, size;
2680                 u32 offset;
2681                 int x, y;
2682                 int ret;
2683
2684                 cpp = fb->format->cpp[i];
2685                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2686                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2687
2688                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2689                 if (ret) {
2690                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2691                                       i, fb->offsets[i]);
2692                         return ret;
2693                 }
2694
2695                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2696                         int hsub = fb->format->hsub;
2697                         int vsub = fb->format->vsub;
2698                         int tile_width, tile_height;
2699                         int main_x, main_y;
2700                         int ccs_x, ccs_y;
2701
2702                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2703                         tile_width *= hsub;
2704                         tile_height *= vsub;
2705
2706                         ccs_x = (x * hsub) % tile_width;
2707                         ccs_y = (y * vsub) % tile_height;
2708                         main_x = intel_fb->normal[0].x % tile_width;
2709                         main_y = intel_fb->normal[0].y % tile_height;
2710
2711                         /*
2712                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2713                          * x/y offsets must match between CCS and the main surface.
2714                          */
2715                         if (main_x != ccs_x || main_y != ccs_y) {
2716                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2717                                               main_x, main_y,
2718                                               ccs_x, ccs_y,
2719                                               intel_fb->normal[0].x,
2720                                               intel_fb->normal[0].y,
2721                                               x, y);
2722                                 return -EINVAL;
2723                         }
2724                 }
2725
2726                 /*
2727                  * The fence (if used) is aligned to the start of the object
2728                  * so having the framebuffer wrap around across the edge of the
2729                  * fenced region doesn't really work. We have no API to configure
2730                  * the fence start offset within the object (nor could we probably
2731                  * on gen2/3). So it's just easier if we just require that the
2732                  * fb layout agrees with the fence layout. We already check that the
2733                  * fb stride matches the fence stride elsewhere.
2734                  */
2735                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2736                     (x + width) * cpp > fb->pitches[i]) {
2737                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2738                                       i, fb->offsets[i]);
2739                         return -EINVAL;
2740                 }
2741
2742                 /*
2743                  * First pixel of the framebuffer from
2744                  * the start of the normal gtt mapping.
2745                  */
2746                 intel_fb->normal[i].x = x;
2747                 intel_fb->normal[i].y = y;
2748
2749                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2750                                                       fb->pitches[i],
2751                                                       DRM_MODE_ROTATE_0,
2752                                                       tile_size);
2753                 offset /= tile_size;
2754
2755                 if (!is_surface_linear(fb->modifier, i)) {
2756                         unsigned int tile_width, tile_height;
2757                         unsigned int pitch_tiles;
2758                         struct drm_rect r;
2759
2760                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2761
2762                         rot_info->plane[i].offset = offset;
2763                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2764                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2765                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2766
2767                         intel_fb->rotated[i].pitch =
2768                                 rot_info->plane[i].height * tile_height;
2769
2770                         /* how many tiles does this plane need */
2771                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2772                         /*
2773                          * If the plane isn't horizontally tile aligned,
2774                          * we need one more tile.
2775                          */
2776                         if (x != 0)
2777                                 size++;
2778
2779                         /* rotate the x/y offsets to match the GTT view */
2780                         drm_rect_init(&r, x, y, width, height);
2781                         drm_rect_rotate(&r,
2782                                         rot_info->plane[i].width * tile_width,
2783                                         rot_info->plane[i].height * tile_height,
2784                                         DRM_MODE_ROTATE_270);
2785                         x = r.x1;
2786                         y = r.y1;
2787
2788                         /* rotate the tile dimensions to match the GTT view */
2789                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2790                         swap(tile_width, tile_height);
2791
2792                         /*
2793                          * We only keep the x/y offsets, so push all of the
2794                          * gtt offset into the x/y offsets.
2795                          */
2796                         intel_adjust_tile_offset(&x, &y,
2797                                                  tile_width, tile_height,
2798                                                  tile_size, pitch_tiles,
2799                                                  gtt_offset_rotated * tile_size, 0);
2800
2801                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2802
2803                         /*
2804                          * First pixel of the framebuffer from
2805                          * the start of the rotated gtt mapping.
2806                          */
2807                         intel_fb->rotated[i].x = x;
2808                         intel_fb->rotated[i].y = y;
2809                 } else {
2810                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2811                                             x * cpp, tile_size);
2812                 }
2813
2814                 /* how many tiles in total needed in the bo */
2815                 max_size = max(max_size, offset + size);
2816         }
2817
2818         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2819                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2820                               mul_u32_u32(max_size, tile_size), obj->base.size);
2821                 return -EINVAL;
2822         }
2823
2824         return 0;
2825 }
2826
2827 static void
2828 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2829 {
2830         struct drm_i915_private *dev_priv =
2831                 to_i915(plane_state->uapi.plane->dev);
2832         struct drm_framebuffer *fb = plane_state->hw.fb;
2833         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2834         struct intel_rotation_info *info = &plane_state->view.rotated;
2835         unsigned int rotation = plane_state->hw.rotation;
2836         int i, num_planes = fb->format->num_planes;
2837         unsigned int tile_size = intel_tile_size(dev_priv);
2838         unsigned int src_x, src_y;
2839         unsigned int src_w, src_h;
2840         u32 gtt_offset = 0;
2841
2842         memset(&plane_state->view, 0, sizeof(plane_state->view));
2843         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2844                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2845
2846         src_x = plane_state->uapi.src.x1 >> 16;
2847         src_y = plane_state->uapi.src.y1 >> 16;
2848         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2849         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2850
2851         WARN_ON(is_ccs_modifier(fb->modifier));
2852
2853         /* Make src coordinates relative to the viewport */
2854         drm_rect_translate(&plane_state->uapi.src,
2855                            -(src_x << 16), -(src_y << 16));
2856
2857         /* Rotate src coordinates to match rotated GTT view */
2858         if (drm_rotation_90_or_270(rotation))
2859                 drm_rect_rotate(&plane_state->uapi.src,
2860                                 src_w << 16, src_h << 16,
2861                                 DRM_MODE_ROTATE_270);
2862
2863         for (i = 0; i < num_planes; i++) {
2864                 unsigned int hsub = i ? fb->format->hsub : 1;
2865                 unsigned int vsub = i ? fb->format->vsub : 1;
2866                 unsigned int cpp = fb->format->cpp[i];
2867                 unsigned int tile_width, tile_height;
2868                 unsigned int width, height;
2869                 unsigned int pitch_tiles;
2870                 unsigned int x, y;
2871                 u32 offset;
2872
2873                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2874
2875                 x = src_x / hsub;
2876                 y = src_y / vsub;
2877                 width = src_w / hsub;
2878                 height = src_h / vsub;
2879
2880                 /*
2881                  * First pixel of the src viewport from the
2882                  * start of the normal gtt mapping.
2883                  */
2884                 x += intel_fb->normal[i].x;
2885                 y += intel_fb->normal[i].y;
2886
2887                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2888                                                       fb, i, fb->pitches[i],
2889                                                       DRM_MODE_ROTATE_0, tile_size);
2890                 offset /= tile_size;
2891
2892                 info->plane[i].offset = offset;
2893                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2894                                                      tile_width * cpp);
2895                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2896                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2897
2898                 if (drm_rotation_90_or_270(rotation)) {
2899                         struct drm_rect r;
2900
2901                         /* rotate the x/y offsets to match the GTT view */
2902                         drm_rect_init(&r, x, y, width, height);
2903                         drm_rect_rotate(&r,
2904                                         info->plane[i].width * tile_width,
2905                                         info->plane[i].height * tile_height,
2906                                         DRM_MODE_ROTATE_270);
2907                         x = r.x1;
2908                         y = r.y1;
2909
2910                         pitch_tiles = info->plane[i].height;
2911                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2912
2913                         /* rotate the tile dimensions to match the GTT view */
2914                         swap(tile_width, tile_height);
2915                 } else {
2916                         pitch_tiles = info->plane[i].width;
2917                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2918                 }
2919
2920                 /*
2921                  * We only keep the x/y offsets, so push all of the
2922                  * gtt offset into the x/y offsets.
2923                  */
2924                 intel_adjust_tile_offset(&x, &y,
2925                                          tile_width, tile_height,
2926                                          tile_size, pitch_tiles,
2927                                          gtt_offset * tile_size, 0);
2928
2929                 gtt_offset += info->plane[i].width * info->plane[i].height;
2930
2931                 plane_state->color_plane[i].offset = 0;
2932                 plane_state->color_plane[i].x = x;
2933                 plane_state->color_plane[i].y = y;
2934         }
2935 }
2936
2937 static int
2938 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2939 {
2940         const struct intel_framebuffer *fb =
2941                 to_intel_framebuffer(plane_state->hw.fb);
2942         unsigned int rotation = plane_state->hw.rotation;
2943         int i, num_planes;
2944
2945         if (!fb)
2946                 return 0;
2947
2948         num_planes = fb->base.format->num_planes;
2949
2950         if (intel_plane_needs_remap(plane_state)) {
2951                 intel_plane_remap_gtt(plane_state);
2952
2953                 /*
2954                  * Sometimes even remapping can't overcome
2955                  * the stride limitations :( Can happen with
2956                  * big plane sizes and suitably misaligned
2957                  * offsets.
2958                  */
2959                 return intel_plane_check_stride(plane_state);
2960         }
2961
2962         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2963
2964         for (i = 0; i < num_planes; i++) {
2965                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2966                 plane_state->color_plane[i].offset = 0;
2967
2968                 if (drm_rotation_90_or_270(rotation)) {
2969                         plane_state->color_plane[i].x = fb->rotated[i].x;
2970                         plane_state->color_plane[i].y = fb->rotated[i].y;
2971                 } else {
2972                         plane_state->color_plane[i].x = fb->normal[i].x;
2973                         plane_state->color_plane[i].y = fb->normal[i].y;
2974                 }
2975         }
2976
2977         /* Rotate src coordinates to match rotated GTT view */
2978         if (drm_rotation_90_or_270(rotation))
2979                 drm_rect_rotate(&plane_state->uapi.src,
2980                                 fb->base.width << 16, fb->base.height << 16,
2981                                 DRM_MODE_ROTATE_270);
2982
2983         return intel_plane_check_stride(plane_state);
2984 }
2985
2986 static int i9xx_format_to_fourcc(int format)
2987 {
2988         switch (format) {
2989         case DISPPLANE_8BPP:
2990                 return DRM_FORMAT_C8;
2991         case DISPPLANE_BGRA555:
2992                 return DRM_FORMAT_ARGB1555;
2993         case DISPPLANE_BGRX555:
2994                 return DRM_FORMAT_XRGB1555;
2995         case DISPPLANE_BGRX565:
2996                 return DRM_FORMAT_RGB565;
2997         default:
2998         case DISPPLANE_BGRX888:
2999                 return DRM_FORMAT_XRGB8888;
3000         case DISPPLANE_RGBX888:
3001                 return DRM_FORMAT_XBGR8888;
3002         case DISPPLANE_BGRA888:
3003                 return DRM_FORMAT_ARGB8888;
3004         case DISPPLANE_RGBA888:
3005                 return DRM_FORMAT_ABGR8888;
3006         case DISPPLANE_BGRX101010:
3007                 return DRM_FORMAT_XRGB2101010;
3008         case DISPPLANE_RGBX101010:
3009                 return DRM_FORMAT_XBGR2101010;
3010         case DISPPLANE_BGRA101010:
3011                 return DRM_FORMAT_ARGB2101010;
3012         case DISPPLANE_RGBA101010:
3013                 return DRM_FORMAT_ABGR2101010;
3014         case DISPPLANE_RGBX161616:
3015                 return DRM_FORMAT_XBGR16161616F;
3016         }
3017 }
3018
3019 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3020 {
3021         switch (format) {
3022         case PLANE_CTL_FORMAT_RGB_565:
3023                 return DRM_FORMAT_RGB565;
3024         case PLANE_CTL_FORMAT_NV12:
3025                 return DRM_FORMAT_NV12;
3026         case PLANE_CTL_FORMAT_P010:
3027                 return DRM_FORMAT_P010;
3028         case PLANE_CTL_FORMAT_P012:
3029                 return DRM_FORMAT_P012;
3030         case PLANE_CTL_FORMAT_P016:
3031                 return DRM_FORMAT_P016;
3032         case PLANE_CTL_FORMAT_Y210:
3033                 return DRM_FORMAT_Y210;
3034         case PLANE_CTL_FORMAT_Y212:
3035                 return DRM_FORMAT_Y212;
3036         case PLANE_CTL_FORMAT_Y216:
3037                 return DRM_FORMAT_Y216;
3038         case PLANE_CTL_FORMAT_Y410:
3039                 return DRM_FORMAT_XVYU2101010;
3040         case PLANE_CTL_FORMAT_Y412:
3041                 return DRM_FORMAT_XVYU12_16161616;
3042         case PLANE_CTL_FORMAT_Y416:
3043                 return DRM_FORMAT_XVYU16161616;
3044         default:
3045         case PLANE_CTL_FORMAT_XRGB_8888:
3046                 if (rgb_order) {
3047                         if (alpha)
3048                                 return DRM_FORMAT_ABGR8888;
3049                         else
3050                                 return DRM_FORMAT_XBGR8888;
3051                 } else {
3052                         if (alpha)
3053                                 return DRM_FORMAT_ARGB8888;
3054                         else
3055                                 return DRM_FORMAT_XRGB8888;
3056                 }
3057         case PLANE_CTL_FORMAT_XRGB_2101010:
3058                 if (rgb_order) {
3059                         if (alpha)
3060                                 return DRM_FORMAT_ABGR2101010;
3061                         else
3062                                 return DRM_FORMAT_XBGR2101010;
3063                 } else {
3064                         if (alpha)
3065                                 return DRM_FORMAT_ARGB2101010;
3066                         else
3067                                 return DRM_FORMAT_XRGB2101010;
3068                 }
3069         case PLANE_CTL_FORMAT_XRGB_16161616F:
3070                 if (rgb_order) {
3071                         if (alpha)
3072                                 return DRM_FORMAT_ABGR16161616F;
3073                         else
3074                                 return DRM_FORMAT_XBGR16161616F;
3075                 } else {
3076                         if (alpha)
3077                                 return DRM_FORMAT_ARGB16161616F;
3078                         else
3079                                 return DRM_FORMAT_XRGB16161616F;
3080                 }
3081         }
3082 }
3083
3084 static bool
3085 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3086                               struct intel_initial_plane_config *plane_config)
3087 {
3088         struct drm_device *dev = crtc->base.dev;
3089         struct drm_i915_private *dev_priv = to_i915(dev);
3090         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3091         struct drm_framebuffer *fb = &plane_config->fb->base;
3092         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3093         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3094                                     PAGE_SIZE);
3095         struct drm_i915_gem_object *obj;
3096         bool ret = false;
3097
3098         size_aligned -= base_aligned;
3099
3100         if (plane_config->size == 0)
3101                 return false;
3102
3103         /* If the FB is too big, just don't use it since fbdev is not very
3104          * important and we should probably use that space with FBC or other
3105          * features. */
3106         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3107                 return false;
3108
3109         switch (fb->modifier) {
3110         case DRM_FORMAT_MOD_LINEAR:
3111         case I915_FORMAT_MOD_X_TILED:
3112         case I915_FORMAT_MOD_Y_TILED:
3113                 break;
3114         default:
3115                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3116                                  fb->modifier);
3117                 return false;
3118         }
3119
3120         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3121                                                              base_aligned,
3122                                                              base_aligned,
3123                                                              size_aligned);
3124         if (IS_ERR(obj))
3125                 return false;
3126
3127         switch (plane_config->tiling) {
3128         case I915_TILING_NONE:
3129                 break;
3130         case I915_TILING_X:
3131         case I915_TILING_Y:
3132                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3133                 break;
3134         default:
3135                 MISSING_CASE(plane_config->tiling);
3136                 goto out;
3137         }
3138
3139         mode_cmd.pixel_format = fb->format->format;
3140         mode_cmd.width = fb->width;
3141         mode_cmd.height = fb->height;
3142         mode_cmd.pitches[0] = fb->pitches[0];
3143         mode_cmd.modifier[0] = fb->modifier;
3144         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3145
3146         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3147                 DRM_DEBUG_KMS("intel fb init failed\n");
3148                 goto out;
3149         }
3150
3151
3152         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3153         ret = true;
3154 out:
3155         i915_gem_object_put(obj);
3156         return ret;
3157 }
3158
3159 static void
3160 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3161                         struct intel_plane_state *plane_state,
3162                         bool visible)
3163 {
3164         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3165
3166         plane_state->uapi.visible = visible;
3167
3168         if (visible)
3169                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3170         else
3171                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3172 }
3173
3174 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3175 {
3176         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3177         struct drm_plane *plane;
3178
3179         /*
3180          * Active_planes aliases if multiple "primary" or cursor planes
3181          * have been used on the same (or wrong) pipe. plane_mask uses
3182          * unique ids, hence we can use that to reconstruct active_planes.
3183          */
3184         crtc_state->active_planes = 0;
3185
3186         drm_for_each_plane_mask(plane, &dev_priv->drm,
3187                                 crtc_state->uapi.plane_mask)
3188                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3189 }
3190
3191 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3192                                          struct intel_plane *plane)
3193 {
3194         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195         struct intel_crtc_state *crtc_state =
3196                 to_intel_crtc_state(crtc->base.state);
3197         struct intel_plane_state *plane_state =
3198                 to_intel_plane_state(plane->base.state);
3199
3200         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3201                       plane->base.base.id, plane->base.name,
3202                       crtc->base.base.id, crtc->base.name);
3203
3204         intel_set_plane_visible(crtc_state, plane_state, false);
3205         fixup_active_planes(crtc_state);
3206         crtc_state->data_rate[plane->id] = 0;
3207         crtc_state->min_cdclk[plane->id] = 0;
3208
3209         if (plane->id == PLANE_PRIMARY)
3210                 hsw_disable_ips(crtc_state);
3211
3212         /*
3213          * Vblank time updates from the shadow to live plane control register
3214          * are blocked if the memory self-refresh mode is active at that
3215          * moment. So to make sure the plane gets truly disabled, disable
3216          * first the self-refresh mode. The self-refresh enable bit in turn
3217          * will be checked/applied by the HW only at the next frame start
3218          * event which is after the vblank start event, so we need to have a
3219          * wait-for-vblank between disabling the plane and the pipe.
3220          */
3221         if (HAS_GMCH(dev_priv) &&
3222             intel_set_memory_cxsr(dev_priv, false))
3223                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3224
3225         /*
3226          * Gen2 reports pipe underruns whenever all planes are disabled.
3227          * So disable underrun reporting before all the planes get disabled.
3228          */
3229         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3230                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3231
3232         intel_disable_plane(plane, crtc_state);
3233 }
3234
3235 static struct intel_frontbuffer *
3236 to_intel_frontbuffer(struct drm_framebuffer *fb)
3237 {
3238         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3239 }
3240
3241 static void
3242 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3243                              struct intel_initial_plane_config *plane_config)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247         struct drm_crtc *c;
3248         struct drm_plane *primary = intel_crtc->base.primary;
3249         struct drm_plane_state *plane_state = primary->state;
3250         struct intel_plane *intel_plane = to_intel_plane(primary);
3251         struct intel_plane_state *intel_state =
3252                 to_intel_plane_state(plane_state);
3253         struct drm_framebuffer *fb;
3254
3255         if (!plane_config->fb)
3256                 return;
3257
3258         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3259                 fb = &plane_config->fb->base;
3260                 goto valid_fb;
3261         }
3262
3263         kfree(plane_config->fb);
3264
3265         /*
3266          * Failed to alloc the obj, check to see if we should share
3267          * an fb with another CRTC instead
3268          */
3269         for_each_crtc(dev, c) {
3270                 struct intel_plane_state *state;
3271
3272                 if (c == &intel_crtc->base)
3273                         continue;
3274
3275                 if (!to_intel_crtc(c)->active)
3276                         continue;
3277
3278                 state = to_intel_plane_state(c->primary->state);
3279                 if (!state->vma)
3280                         continue;
3281
3282                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3283                         fb = state->hw.fb;
3284                         drm_framebuffer_get(fb);
3285                         goto valid_fb;
3286                 }
3287         }
3288
3289         /*
3290          * We've failed to reconstruct the BIOS FB.  Current display state
3291          * indicates that the primary plane is visible, but has a NULL FB,
3292          * which will lead to problems later if we don't fix it up.  The
3293          * simplest solution is to just disable the primary plane now and
3294          * pretend the BIOS never had it enabled.
3295          */
3296         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3297
3298         return;
3299
3300 valid_fb:
3301         intel_state->hw.rotation = plane_config->rotation;
3302         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3303                                 intel_state->hw.rotation);
3304         intel_state->color_plane[0].stride =
3305                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3306
3307         intel_state->vma =
3308                 intel_pin_and_fence_fb_obj(fb,
3309                                            &intel_state->view,
3310                                            intel_plane_uses_fence(intel_state),
3311                                            &intel_state->flags);
3312         if (IS_ERR(intel_state->vma)) {
3313                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3314                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3315
3316                 intel_state->vma = NULL;
3317                 drm_framebuffer_put(fb);
3318                 return;
3319         }
3320
3321         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3322
3323         plane_state->src_x = 0;
3324         plane_state->src_y = 0;
3325         plane_state->src_w = fb->width << 16;
3326         plane_state->src_h = fb->height << 16;
3327
3328         plane_state->crtc_x = 0;
3329         plane_state->crtc_y = 0;
3330         plane_state->crtc_w = fb->width;
3331         plane_state->crtc_h = fb->height;
3332
3333         intel_state->uapi.src = drm_plane_state_src(plane_state);
3334         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3335
3336         if (plane_config->tiling)
3337                 dev_priv->preserve_bios_swizzle = true;
3338
3339         plane_state->fb = fb;
3340         plane_state->crtc = &intel_crtc->base;
3341         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3342
3343         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3344                   &to_intel_frontbuffer(fb)->bits);
3345 }
3346
3347 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3348                                int color_plane,
3349                                unsigned int rotation)
3350 {
3351         int cpp = fb->format->cpp[color_plane];
3352
3353         switch (fb->modifier) {
3354         case DRM_FORMAT_MOD_LINEAR:
3355         case I915_FORMAT_MOD_X_TILED:
3356                 /*
3357                  * Validated limit is 4k, but has 5k should
3358                  * work apart from the following features:
3359                  * - Ytile (already limited to 4k)
3360                  * - FP16 (already limited to 4k)
3361                  * - render compression (already limited to 4k)
3362                  * - KVMR sprite and cursor (don't care)
3363                  * - horizontal panning (TODO verify this)
3364                  * - pipe and plane scaling (TODO verify this)
3365                  */
3366                 if (cpp == 8)
3367                         return 4096;
3368                 else
3369                         return 5120;
3370         case I915_FORMAT_MOD_Y_TILED_CCS:
3371         case I915_FORMAT_MOD_Yf_TILED_CCS:
3372                 /* FIXME AUX plane? */
3373         case I915_FORMAT_MOD_Y_TILED:
3374         case I915_FORMAT_MOD_Yf_TILED:
3375                 if (cpp == 8)
3376                         return 2048;
3377                 else
3378                         return 4096;
3379         default:
3380                 MISSING_CASE(fb->modifier);
3381                 return 2048;
3382         }
3383 }
3384
3385 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3386                                int color_plane,
3387                                unsigned int rotation)
3388 {
3389         int cpp = fb->format->cpp[color_plane];
3390
3391         switch (fb->modifier) {
3392         case DRM_FORMAT_MOD_LINEAR:
3393         case I915_FORMAT_MOD_X_TILED:
3394                 if (cpp == 8)
3395                         return 4096;
3396                 else
3397                         return 5120;
3398         case I915_FORMAT_MOD_Y_TILED_CCS:
3399         case I915_FORMAT_MOD_Yf_TILED_CCS:
3400                 /* FIXME AUX plane? */
3401         case I915_FORMAT_MOD_Y_TILED:
3402         case I915_FORMAT_MOD_Yf_TILED:
3403                 if (cpp == 8)
3404                         return 2048;
3405                 else
3406                         return 5120;
3407         default:
3408                 MISSING_CASE(fb->modifier);
3409                 return 2048;
3410         }
3411 }
3412
3413 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3414                                int color_plane,
3415                                unsigned int rotation)
3416 {
3417         return 5120;
3418 }
3419
3420 static int skl_max_plane_height(void)
3421 {
3422         return 4096;
3423 }
3424
3425 static int icl_max_plane_height(void)
3426 {
3427         return 4320;
3428 }
3429
3430 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3431                                            int main_x, int main_y, u32 main_offset)
3432 {
3433         const struct drm_framebuffer *fb = plane_state->hw.fb;
3434         int hsub = fb->format->hsub;
3435         int vsub = fb->format->vsub;
3436         int aux_x = plane_state->color_plane[1].x;
3437         int aux_y = plane_state->color_plane[1].y;
3438         u32 aux_offset = plane_state->color_plane[1].offset;
3439         u32 alignment = intel_surf_alignment(fb, 1);
3440
3441         while (aux_offset >= main_offset && aux_y <= main_y) {
3442                 int x, y;
3443
3444                 if (aux_x == main_x && aux_y == main_y)
3445                         break;
3446
3447                 if (aux_offset == 0)
3448                         break;
3449
3450                 x = aux_x / hsub;
3451                 y = aux_y / vsub;
3452                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3453                                                                aux_offset, aux_offset - alignment);
3454                 aux_x = x * hsub + aux_x % hsub;
3455                 aux_y = y * vsub + aux_y % vsub;
3456         }
3457
3458         if (aux_x != main_x || aux_y != main_y)
3459                 return false;
3460
3461         plane_state->color_plane[1].offset = aux_offset;
3462         plane_state->color_plane[1].x = aux_x;
3463         plane_state->color_plane[1].y = aux_y;
3464
3465         return true;
3466 }
3467
3468 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3469 {
3470         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3471         const struct drm_framebuffer *fb = plane_state->hw.fb;
3472         unsigned int rotation = plane_state->hw.rotation;
3473         int x = plane_state->uapi.src.x1 >> 16;
3474         int y = plane_state->uapi.src.y1 >> 16;
3475         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3476         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3477         int max_width;
3478         int max_height;
3479         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3480
3481         if (INTEL_GEN(dev_priv) >= 11)
3482                 max_width = icl_max_plane_width(fb, 0, rotation);
3483         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3484                 max_width = glk_max_plane_width(fb, 0, rotation);
3485         else
3486                 max_width = skl_max_plane_width(fb, 0, rotation);
3487
3488         if (INTEL_GEN(dev_priv) >= 11)
3489                 max_height = icl_max_plane_height();
3490         else
3491                 max_height = skl_max_plane_height();
3492
3493         if (w > max_width || h > max_height) {
3494                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3495                               w, h, max_width, max_height);
3496                 return -EINVAL;
3497         }
3498
3499         intel_add_fb_offsets(&x, &y, plane_state, 0);
3500         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3501         alignment = intel_surf_alignment(fb, 0);
3502
3503         /*
3504          * AUX surface offset is specified as the distance from the
3505          * main surface offset, and it must be non-negative. Make
3506          * sure that is what we will get.
3507          */
3508         if (offset > aux_offset)
3509                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3510                                                            offset, aux_offset & ~(alignment - 1));
3511
3512         /*
3513          * When using an X-tiled surface, the plane blows up
3514          * if the x offset + width exceed the stride.
3515          *
3516          * TODO: linear and Y-tiled seem fine, Yf untested,
3517          */
3518         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3519                 int cpp = fb->format->cpp[0];
3520
3521                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3522                         if (offset == 0) {
3523                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3524                                 return -EINVAL;
3525                         }
3526
3527                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3528                                                                    offset, offset - alignment);
3529                 }
3530         }
3531
3532         /*
3533          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3534          * they match with the main surface x/y offsets.
3535          */
3536         if (is_ccs_modifier(fb->modifier)) {
3537                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3538                         if (offset == 0)
3539                                 break;
3540
3541                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3542                                                                    offset, offset - alignment);
3543                 }
3544
3545                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3546                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3547                         return -EINVAL;
3548                 }
3549         }
3550
3551         plane_state->color_plane[0].offset = offset;
3552         plane_state->color_plane[0].x = x;
3553         plane_state->color_plane[0].y = y;
3554
3555         /*
3556          * Put the final coordinates back so that the src
3557          * coordinate checks will see the right values.
3558          */
3559         drm_rect_translate_to(&plane_state->uapi.src,
3560                               x << 16, y << 16);
3561
3562         return 0;
3563 }
3564
3565 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3566 {
3567         const struct drm_framebuffer *fb = plane_state->hw.fb;
3568         unsigned int rotation = plane_state->hw.rotation;
3569         int max_width = skl_max_plane_width(fb, 1, rotation);
3570         int max_height = 4096;
3571         int x = plane_state->uapi.src.x1 >> 17;
3572         int y = plane_state->uapi.src.y1 >> 17;
3573         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3574         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3575         u32 offset;
3576
3577         intel_add_fb_offsets(&x, &y, plane_state, 1);
3578         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3579
3580         /* FIXME not quite sure how/if these apply to the chroma plane */
3581         if (w > max_width || h > max_height) {
3582                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3583                               w, h, max_width, max_height);
3584                 return -EINVAL;
3585         }
3586
3587         plane_state->color_plane[1].offset = offset;
3588         plane_state->color_plane[1].x = x;
3589         plane_state->color_plane[1].y = y;
3590
3591         return 0;
3592 }
3593
3594 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3595 {
3596         const struct drm_framebuffer *fb = plane_state->hw.fb;
3597         int src_x = plane_state->uapi.src.x1 >> 16;
3598         int src_y = plane_state->uapi.src.y1 >> 16;
3599         int hsub = fb->format->hsub;
3600         int vsub = fb->format->vsub;
3601         int x = src_x / hsub;
3602         int y = src_y / vsub;
3603         u32 offset;
3604
3605         intel_add_fb_offsets(&x, &y, plane_state, 1);
3606         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3607
3608         plane_state->color_plane[1].offset = offset;
3609         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3610         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3611
3612         return 0;
3613 }
3614
3615 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3616 {
3617         const struct drm_framebuffer *fb = plane_state->hw.fb;
3618         int ret;
3619
3620         ret = intel_plane_compute_gtt(plane_state);
3621         if (ret)
3622                 return ret;
3623
3624         if (!plane_state->uapi.visible)
3625                 return 0;
3626
3627         /*
3628          * Handle the AUX surface first since
3629          * the main surface setup depends on it.
3630          */
3631         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3632                 ret = skl_check_nv12_aux_surface(plane_state);
3633                 if (ret)
3634                         return ret;
3635         } else if (is_ccs_modifier(fb->modifier)) {
3636                 ret = skl_check_ccs_aux_surface(plane_state);
3637                 if (ret)
3638                         return ret;
3639         } else {
3640                 plane_state->color_plane[1].offset = ~0xfff;
3641                 plane_state->color_plane[1].x = 0;
3642                 plane_state->color_plane[1].y = 0;
3643         }
3644
3645         ret = skl_check_main_surface(plane_state);
3646         if (ret)
3647                 return ret;
3648
3649         return 0;
3650 }
3651
3652 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3653                              const struct intel_plane_state *plane_state,
3654                              unsigned int *num, unsigned int *den)
3655 {
3656         const struct drm_framebuffer *fb = plane_state->hw.fb;
3657         unsigned int cpp = fb->format->cpp[0];
3658
3659         /*
3660          * g4x bspec says 64bpp pixel rate can't exceed 80%
3661          * of cdclk when the sprite plane is enabled on the
3662          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3663          * never allowed to exceed 80% of cdclk. Let's just go
3664          * with the ilk/snb limit always.
3665          */
3666         if (cpp == 8) {
3667                 *num = 10;
3668                 *den = 8;
3669         } else {
3670                 *num = 1;
3671                 *den = 1;
3672         }
3673 }
3674
3675 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3676                                 const struct intel_plane_state *plane_state)
3677 {
3678         unsigned int pixel_rate;
3679         unsigned int num, den;
3680
3681         /*
3682          * Note that crtc_state->pixel_rate accounts for both
3683          * horizontal and vertical panel fitter downscaling factors.
3684          * Pre-HSW bspec tells us to only consider the horizontal
3685          * downscaling factor here. We ignore that and just consider
3686          * both for simplicity.
3687          */
3688         pixel_rate = crtc_state->pixel_rate;
3689
3690         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3691
3692         /* two pixels per clock with double wide pipe */
3693         if (crtc_state->double_wide)
3694                 den *= 2;
3695
3696         return DIV_ROUND_UP(pixel_rate * num, den);
3697 }
3698
3699 unsigned int
3700 i9xx_plane_max_stride(struct intel_plane *plane,
3701                       u32 pixel_format, u64 modifier,
3702                       unsigned int rotation)
3703 {
3704         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3705
3706         if (!HAS_GMCH(dev_priv)) {
3707                 return 32*1024;
3708         } else if (INTEL_GEN(dev_priv) >= 4) {
3709                 if (modifier == I915_FORMAT_MOD_X_TILED)
3710                         return 16*1024;
3711                 else
3712                         return 32*1024;
3713         } else if (INTEL_GEN(dev_priv) >= 3) {
3714                 if (modifier == I915_FORMAT_MOD_X_TILED)
3715                         return 8*1024;
3716                 else
3717                         return 16*1024;
3718         } else {
3719                 if (plane->i9xx_plane == PLANE_C)
3720                         return 4*1024;
3721                 else
3722                         return 8*1024;
3723         }
3724 }
3725
3726 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3727 {
3728         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3730         u32 dspcntr = 0;
3731
3732         if (crtc_state->gamma_enable)
3733                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3734
3735         if (crtc_state->csc_enable)
3736                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3737
3738         if (INTEL_GEN(dev_priv) < 5)
3739                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3740
3741         return dspcntr;
3742 }
3743
3744 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3745                           const struct intel_plane_state *plane_state)
3746 {
3747         struct drm_i915_private *dev_priv =
3748                 to_i915(plane_state->uapi.plane->dev);
3749         const struct drm_framebuffer *fb = plane_state->hw.fb;
3750         unsigned int rotation = plane_state->hw.rotation;
3751         u32 dspcntr;
3752
3753         dspcntr = DISPLAY_PLANE_ENABLE;
3754
3755         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3756             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3757                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3758
3759         switch (fb->format->format) {
3760         case DRM_FORMAT_C8:
3761                 dspcntr |= DISPPLANE_8BPP;
3762                 break;
3763         case DRM_FORMAT_XRGB1555:
3764                 dspcntr |= DISPPLANE_BGRX555;
3765                 break;
3766         case DRM_FORMAT_ARGB1555:
3767                 dspcntr |= DISPPLANE_BGRA555;
3768                 break;
3769         case DRM_FORMAT_RGB565:
3770                 dspcntr |= DISPPLANE_BGRX565;
3771                 break;
3772         case DRM_FORMAT_XRGB8888:
3773                 dspcntr |= DISPPLANE_BGRX888;
3774                 break;
3775         case DRM_FORMAT_XBGR8888:
3776                 dspcntr |= DISPPLANE_RGBX888;
3777                 break;
3778         case DRM_FORMAT_ARGB8888:
3779                 dspcntr |= DISPPLANE_BGRA888;
3780                 break;
3781         case DRM_FORMAT_ABGR8888:
3782                 dspcntr |= DISPPLANE_RGBA888;
3783                 break;
3784         case DRM_FORMAT_XRGB2101010:
3785                 dspcntr |= DISPPLANE_BGRX101010;
3786                 break;
3787         case DRM_FORMAT_XBGR2101010:
3788                 dspcntr |= DISPPLANE_RGBX101010;
3789                 break;
3790         case DRM_FORMAT_ARGB2101010:
3791                 dspcntr |= DISPPLANE_BGRA101010;
3792                 break;
3793         case DRM_FORMAT_ABGR2101010:
3794                 dspcntr |= DISPPLANE_RGBA101010;
3795                 break;
3796         case DRM_FORMAT_XBGR16161616F:
3797                 dspcntr |= DISPPLANE_RGBX161616;
3798                 break;
3799         default:
3800                 MISSING_CASE(fb->format->format);
3801                 return 0;
3802         }
3803
3804         if (INTEL_GEN(dev_priv) >= 4 &&
3805             fb->modifier == I915_FORMAT_MOD_X_TILED)
3806                 dspcntr |= DISPPLANE_TILED;
3807
3808         if (rotation & DRM_MODE_ROTATE_180)
3809                 dspcntr |= DISPPLANE_ROTATE_180;
3810
3811         if (rotation & DRM_MODE_REFLECT_X)
3812                 dspcntr |= DISPPLANE_MIRROR;
3813
3814         return dspcntr;
3815 }
3816
3817 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3818 {
3819         struct drm_i915_private *dev_priv =
3820                 to_i915(plane_state->uapi.plane->dev);
3821         const struct drm_framebuffer *fb = plane_state->hw.fb;
3822         int src_x, src_y, src_w;
3823         u32 offset;
3824         int ret;
3825
3826         ret = intel_plane_compute_gtt(plane_state);
3827         if (ret)
3828                 return ret;
3829
3830         if (!plane_state->uapi.visible)
3831                 return 0;
3832
3833         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3834         src_x = plane_state->uapi.src.x1 >> 16;
3835         src_y = plane_state->uapi.src.y1 >> 16;
3836
3837         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3838         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3839                 return -EINVAL;
3840
3841         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3842
3843         if (INTEL_GEN(dev_priv) >= 4)
3844                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3845                                                             plane_state, 0);
3846         else
3847                 offset = 0;
3848
3849         /*
3850          * Put the final coordinates back so that the src
3851          * coordinate checks will see the right values.
3852          */
3853         drm_rect_translate_to(&plane_state->uapi.src,
3854                               src_x << 16, src_y << 16);
3855
3856         /* HSW/BDW do this automagically in hardware */
3857         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3858                 unsigned int rotation = plane_state->hw.rotation;
3859                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3860                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3861
3862                 if (rotation & DRM_MODE_ROTATE_180) {
3863                         src_x += src_w - 1;
3864                         src_y += src_h - 1;
3865                 } else if (rotation & DRM_MODE_REFLECT_X) {
3866                         src_x += src_w - 1;
3867                 }
3868         }
3869
3870         plane_state->color_plane[0].offset = offset;
3871         plane_state->color_plane[0].x = src_x;
3872         plane_state->color_plane[0].y = src_y;
3873
3874         return 0;
3875 }
3876
3877 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3878 {
3879         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3880         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3881
3882         if (IS_CHERRYVIEW(dev_priv))
3883                 return i9xx_plane == PLANE_B;
3884         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3885                 return false;
3886         else if (IS_GEN(dev_priv, 4))
3887                 return i9xx_plane == PLANE_C;
3888         else
3889                 return i9xx_plane == PLANE_B ||
3890                         i9xx_plane == PLANE_C;
3891 }
3892
3893 static int
3894 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3895                  struct intel_plane_state *plane_state)
3896 {
3897         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3898         int ret;
3899
3900         ret = chv_plane_check_rotation(plane_state);
3901         if (ret)
3902                 return ret;
3903
3904         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3905                                                   &crtc_state->uapi,
3906                                                   DRM_PLANE_HELPER_NO_SCALING,
3907                                                   DRM_PLANE_HELPER_NO_SCALING,
3908                                                   i9xx_plane_has_windowing(plane),
3909                                                   true);
3910         if (ret)
3911                 return ret;
3912
3913         ret = i9xx_check_plane_surface(plane_state);
3914         if (ret)
3915                 return ret;
3916
3917         if (!plane_state->uapi.visible)
3918                 return 0;
3919
3920         ret = intel_plane_check_src_coordinates(plane_state);
3921         if (ret)
3922                 return ret;
3923
3924         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3925
3926         return 0;
3927 }
3928
3929 static void i9xx_update_plane(struct intel_plane *plane,
3930                               const struct intel_crtc_state *crtc_state,
3931                               const struct intel_plane_state *plane_state)
3932 {
3933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3934         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3935         u32 linear_offset;
3936         int x = plane_state->color_plane[0].x;
3937         int y = plane_state->color_plane[0].y;
3938         int crtc_x = plane_state->uapi.dst.x1;
3939         int crtc_y = plane_state->uapi.dst.y1;
3940         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3941         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3942         unsigned long irqflags;
3943         u32 dspaddr_offset;
3944         u32 dspcntr;
3945
3946         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3947
3948         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3949
3950         if (INTEL_GEN(dev_priv) >= 4)
3951                 dspaddr_offset = plane_state->color_plane[0].offset;
3952         else
3953                 dspaddr_offset = linear_offset;
3954
3955         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3956
3957         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3958
3959         if (INTEL_GEN(dev_priv) < 4) {
3960                 /*
3961                  * PLANE_A doesn't actually have a full window
3962                  * generator but let's assume we still need to
3963                  * program whatever is there.
3964                  */
3965                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3966                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3967                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3968         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3969                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3970                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3971                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3972                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3973         }
3974
3975         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3976                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3977         } else if (INTEL_GEN(dev_priv) >= 4) {
3978                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3979                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3980         }
3981
3982         /*
3983          * The control register self-arms if the plane was previously
3984          * disabled. Try to make the plane enable atomic by writing
3985          * the control register just before the surface register.
3986          */
3987         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3988         if (INTEL_GEN(dev_priv) >= 4)
3989                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3990                               intel_plane_ggtt_offset(plane_state) +
3991                               dspaddr_offset);
3992         else
3993                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3994                               intel_plane_ggtt_offset(plane_state) +
3995                               dspaddr_offset);
3996
3997         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3998 }
3999
4000 static void i9xx_disable_plane(struct intel_plane *plane,
4001                                const struct intel_crtc_state *crtc_state)
4002 {
4003         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4004         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4005         unsigned long irqflags;
4006         u32 dspcntr;
4007
4008         /*
4009          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4010          * enable on ilk+ affect the pipe bottom color as
4011          * well, so we must configure them even if the plane
4012          * is disabled.
4013          *
4014          * On pre-g4x there is no way to gamma correct the
4015          * pipe bottom color but we'll keep on doing this
4016          * anyway so that the crtc state readout works correctly.
4017          */
4018         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4019
4020         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4021
4022         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4023         if (INTEL_GEN(dev_priv) >= 4)
4024                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
4025         else
4026                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
4027
4028         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4029 }
4030
4031 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4032                                     enum pipe *pipe)
4033 {
4034         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4035         enum intel_display_power_domain power_domain;
4036         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4037         intel_wakeref_t wakeref;
4038         bool ret;
4039         u32 val;
4040
4041         /*
4042          * Not 100% correct for planes that can move between pipes,
4043          * but that's only the case for gen2-4 which don't have any
4044          * display power wells.
4045          */
4046         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4047         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4048         if (!wakeref)
4049                 return false;
4050
4051         val = I915_READ(DSPCNTR(i9xx_plane));
4052
4053         ret = val & DISPLAY_PLANE_ENABLE;
4054
4055         if (INTEL_GEN(dev_priv) >= 5)
4056                 *pipe = plane->pipe;
4057         else
4058                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4059                         DISPPLANE_SEL_PIPE_SHIFT;
4060
4061         intel_display_power_put(dev_priv, power_domain, wakeref);
4062
4063         return ret;
4064 }
4065
4066 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4067 {
4068         struct drm_device *dev = intel_crtc->base.dev;
4069         struct drm_i915_private *dev_priv = to_i915(dev);
4070
4071         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4072         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4073         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4074 }
4075
4076 /*
4077  * This function detaches (aka. unbinds) unused scalers in hardware
4078  */
4079 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4080 {
4081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4082         const struct intel_crtc_scaler_state *scaler_state =
4083                 &crtc_state->scaler_state;
4084         int i;
4085
4086         /* loop through and disable scalers that aren't in use */
4087         for (i = 0; i < intel_crtc->num_scalers; i++) {
4088                 if (!scaler_state->scalers[i].in_use)
4089                         skl_detach_scaler(intel_crtc, i);
4090         }
4091 }
4092
4093 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4094                                           int color_plane, unsigned int rotation)
4095 {
4096         /*
4097          * The stride is either expressed as a multiple of 64 bytes chunks for
4098          * linear buffers or in number of tiles for tiled buffers.
4099          */
4100         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4101                 return 64;
4102         else if (drm_rotation_90_or_270(rotation))
4103                 return intel_tile_height(fb, color_plane);
4104         else
4105                 return intel_tile_width_bytes(fb, color_plane);
4106 }
4107
4108 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4109                      int color_plane)
4110 {
4111         const struct drm_framebuffer *fb = plane_state->hw.fb;
4112         unsigned int rotation = plane_state->hw.rotation;
4113         u32 stride = plane_state->color_plane[color_plane].stride;
4114
4115         if (color_plane >= fb->format->num_planes)
4116                 return 0;
4117
4118         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4119 }
4120
4121 static u32 skl_plane_ctl_format(u32 pixel_format)
4122 {
4123         switch (pixel_format) {
4124         case DRM_FORMAT_C8:
4125                 return PLANE_CTL_FORMAT_INDEXED;
4126         case DRM_FORMAT_RGB565:
4127                 return PLANE_CTL_FORMAT_RGB_565;
4128         case DRM_FORMAT_XBGR8888:
4129         case DRM_FORMAT_ABGR8888:
4130                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4131         case DRM_FORMAT_XRGB8888:
4132         case DRM_FORMAT_ARGB8888:
4133                 return PLANE_CTL_FORMAT_XRGB_8888;
4134         case DRM_FORMAT_XBGR2101010:
4135         case DRM_FORMAT_ABGR2101010:
4136                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4137         case DRM_FORMAT_XRGB2101010:
4138         case DRM_FORMAT_ARGB2101010:
4139                 return PLANE_CTL_FORMAT_XRGB_2101010;
4140         case DRM_FORMAT_XBGR16161616F:
4141         case DRM_FORMAT_ABGR16161616F:
4142                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4143         case DRM_FORMAT_XRGB16161616F:
4144         case DRM_FORMAT_ARGB16161616F:
4145                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4146         case DRM_FORMAT_YUYV:
4147                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4148         case DRM_FORMAT_YVYU:
4149                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4150         case DRM_FORMAT_UYVY:
4151                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4152         case DRM_FORMAT_VYUY:
4153                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4154         case DRM_FORMAT_NV12:
4155                 return PLANE_CTL_FORMAT_NV12;
4156         case DRM_FORMAT_P010:
4157                 return PLANE_CTL_FORMAT_P010;
4158         case DRM_FORMAT_P012:
4159                 return PLANE_CTL_FORMAT_P012;
4160         case DRM_FORMAT_P016:
4161                 return PLANE_CTL_FORMAT_P016;
4162         case DRM_FORMAT_Y210:
4163                 return PLANE_CTL_FORMAT_Y210;
4164         case DRM_FORMAT_Y212:
4165                 return PLANE_CTL_FORMAT_Y212;
4166         case DRM_FORMAT_Y216:
4167                 return PLANE_CTL_FORMAT_Y216;
4168         case DRM_FORMAT_XVYU2101010:
4169                 return PLANE_CTL_FORMAT_Y410;
4170         case DRM_FORMAT_XVYU12_16161616:
4171                 return PLANE_CTL_FORMAT_Y412;
4172         case DRM_FORMAT_XVYU16161616:
4173                 return PLANE_CTL_FORMAT_Y416;
4174         default:
4175                 MISSING_CASE(pixel_format);
4176         }
4177
4178         return 0;
4179 }
4180
4181 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4182 {
4183         if (!plane_state->hw.fb->format->has_alpha)
4184                 return PLANE_CTL_ALPHA_DISABLE;
4185
4186         switch (plane_state->hw.pixel_blend_mode) {
4187         case DRM_MODE_BLEND_PIXEL_NONE:
4188                 return PLANE_CTL_ALPHA_DISABLE;
4189         case DRM_MODE_BLEND_PREMULTI:
4190                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4191         case DRM_MODE_BLEND_COVERAGE:
4192                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4193         default:
4194                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4195                 return PLANE_CTL_ALPHA_DISABLE;
4196         }
4197 }
4198
4199 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4200 {
4201         if (!plane_state->hw.fb->format->has_alpha)
4202                 return PLANE_COLOR_ALPHA_DISABLE;
4203
4204         switch (plane_state->hw.pixel_blend_mode) {
4205         case DRM_MODE_BLEND_PIXEL_NONE:
4206                 return PLANE_COLOR_ALPHA_DISABLE;
4207         case DRM_MODE_BLEND_PREMULTI:
4208                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4209         case DRM_MODE_BLEND_COVERAGE:
4210                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4211         default:
4212                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4213                 return PLANE_COLOR_ALPHA_DISABLE;
4214         }
4215 }
4216
4217 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4218 {
4219         switch (fb_modifier) {
4220         case DRM_FORMAT_MOD_LINEAR:
4221                 break;
4222         case I915_FORMAT_MOD_X_TILED:
4223                 return PLANE_CTL_TILED_X;
4224         case I915_FORMAT_MOD_Y_TILED:
4225                 return PLANE_CTL_TILED_Y;
4226         case I915_FORMAT_MOD_Y_TILED_CCS:
4227                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4228         case I915_FORMAT_MOD_Yf_TILED:
4229                 return PLANE_CTL_TILED_YF;
4230         case I915_FORMAT_MOD_Yf_TILED_CCS:
4231                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4232         default:
4233                 MISSING_CASE(fb_modifier);
4234         }
4235
4236         return 0;
4237 }
4238
4239 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4240 {
4241         switch (rotate) {
4242         case DRM_MODE_ROTATE_0:
4243                 break;
4244         /*
4245          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4246          * while i915 HW rotation is clockwise, thats why this swapping.
4247          */
4248         case DRM_MODE_ROTATE_90:
4249                 return PLANE_CTL_ROTATE_270;
4250         case DRM_MODE_ROTATE_180:
4251                 return PLANE_CTL_ROTATE_180;
4252         case DRM_MODE_ROTATE_270:
4253                 return PLANE_CTL_ROTATE_90;
4254         default:
4255                 MISSING_CASE(rotate);
4256         }
4257
4258         return 0;
4259 }
4260
4261 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4262 {
4263         switch (reflect) {
4264         case 0:
4265                 break;
4266         case DRM_MODE_REFLECT_X:
4267                 return PLANE_CTL_FLIP_HORIZONTAL;
4268         case DRM_MODE_REFLECT_Y:
4269         default:
4270                 MISSING_CASE(reflect);
4271         }
4272
4273         return 0;
4274 }
4275
4276 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4277 {
4278         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4279         u32 plane_ctl = 0;
4280
4281         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4282                 return plane_ctl;
4283
4284         if (crtc_state->gamma_enable)
4285                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4286
4287         if (crtc_state->csc_enable)
4288                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4289
4290         return plane_ctl;
4291 }
4292
4293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4294                   const struct intel_plane_state *plane_state)
4295 {
4296         struct drm_i915_private *dev_priv =
4297                 to_i915(plane_state->uapi.plane->dev);
4298         const struct drm_framebuffer *fb = plane_state->hw.fb;
4299         unsigned int rotation = plane_state->hw.rotation;
4300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4301         u32 plane_ctl;
4302
4303         plane_ctl = PLANE_CTL_ENABLE;
4304
4305         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4306                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4307                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4308
4309                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4310                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4311
4312                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4313                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4314         }
4315
4316         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4317         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4318         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4319
4320         if (INTEL_GEN(dev_priv) >= 10)
4321                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4322                                                 DRM_MODE_REFLECT_MASK);
4323
4324         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4325                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4326         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4327                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4328
4329         return plane_ctl;
4330 }
4331
4332 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4333 {
4334         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4335         u32 plane_color_ctl = 0;
4336
4337         if (INTEL_GEN(dev_priv) >= 11)
4338                 return plane_color_ctl;
4339
4340         if (crtc_state->gamma_enable)
4341                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4342
4343         if (crtc_state->csc_enable)
4344                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4345
4346         return plane_color_ctl;
4347 }
4348
4349 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4350                         const struct intel_plane_state *plane_state)
4351 {
4352         struct drm_i915_private *dev_priv =
4353                 to_i915(plane_state->uapi.plane->dev);
4354         const struct drm_framebuffer *fb = plane_state->hw.fb;
4355         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4356         u32 plane_color_ctl = 0;
4357
4358         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4359         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4360
4361         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4362                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4363                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4364                 else
4365                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4366
4367                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4368                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4369         } else if (fb->format->is_yuv) {
4370                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4371         }
4372
4373         return plane_color_ctl;
4374 }
4375
4376 static int
4377 __intel_display_resume(struct drm_device *dev,
4378                        struct drm_atomic_state *state,
4379                        struct drm_modeset_acquire_ctx *ctx)
4380 {
4381         struct drm_crtc_state *crtc_state;
4382         struct drm_crtc *crtc;
4383         int i, ret;
4384
4385         intel_modeset_setup_hw_state(dev, ctx);
4386         intel_vga_redisable(to_i915(dev));
4387
4388         if (!state)
4389                 return 0;
4390
4391         /*
4392          * We've duplicated the state, pointers to the old state are invalid.
4393          *
4394          * Don't attempt to use the old state until we commit the duplicated state.
4395          */
4396         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4397                 /*
4398                  * Force recalculation even if we restore
4399                  * current state. With fast modeset this may not result
4400                  * in a modeset when the state is compatible.
4401                  */
4402                 crtc_state->mode_changed = true;
4403         }
4404
4405         /* ignore any reset values/BIOS leftovers in the WM registers */
4406         if (!HAS_GMCH(to_i915(dev)))
4407                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4408
4409         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4410
4411         WARN_ON(ret == -EDEADLK);
4412         return ret;
4413 }
4414
4415 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4416 {
4417         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4418                 intel_has_gpu_reset(&dev_priv->gt));
4419 }
4420
4421 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4422 {
4423         struct drm_device *dev = &dev_priv->drm;
4424         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4425         struct drm_atomic_state *state;
4426         int ret;
4427
4428         /* reset doesn't touch the display */
4429         if (!i915_modparams.force_reset_modeset_test &&
4430             !gpu_reset_clobbers_display(dev_priv))
4431                 return;
4432
4433         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4434         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4435         smp_mb__after_atomic();
4436         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4437
4438         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4439                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4440                 intel_gt_set_wedged(&dev_priv->gt);
4441         }
4442
4443         /*
4444          * Need mode_config.mutex so that we don't
4445          * trample ongoing ->detect() and whatnot.
4446          */
4447         mutex_lock(&dev->mode_config.mutex);
4448         drm_modeset_acquire_init(ctx, 0);
4449         while (1) {
4450                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4451                 if (ret != -EDEADLK)
4452                         break;
4453
4454                 drm_modeset_backoff(ctx);
4455         }
4456         /*
4457          * Disabling the crtcs gracefully seems nicer. Also the
4458          * g33 docs say we should at least disable all the planes.
4459          */
4460         state = drm_atomic_helper_duplicate_state(dev, ctx);
4461         if (IS_ERR(state)) {
4462                 ret = PTR_ERR(state);
4463                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4464                 return;
4465         }
4466
4467         ret = drm_atomic_helper_disable_all(dev, ctx);
4468         if (ret) {
4469                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4470                 drm_atomic_state_put(state);
4471                 return;
4472         }
4473
4474         dev_priv->modeset_restore_state = state;
4475         state->acquire_ctx = ctx;
4476 }
4477
4478 void intel_finish_reset(struct drm_i915_private *dev_priv)
4479 {
4480         struct drm_device *dev = &dev_priv->drm;
4481         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4482         struct drm_atomic_state *state;
4483         int ret;
4484
4485         /* reset doesn't touch the display */
4486         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4487                 return;
4488
4489         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4490         if (!state)
4491                 goto unlock;
4492
4493         /* reset doesn't touch the display */
4494         if (!gpu_reset_clobbers_display(dev_priv)) {
4495                 /* for testing only restore the display */
4496                 ret = __intel_display_resume(dev, state, ctx);
4497                 if (ret)
4498                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4499         } else {
4500                 /*
4501                  * The display has been reset as well,
4502                  * so need a full re-initialization.
4503                  */
4504                 intel_pps_unlock_regs_wa(dev_priv);
4505                 intel_modeset_init_hw(dev_priv);
4506                 intel_init_clock_gating(dev_priv);
4507
4508                 spin_lock_irq(&dev_priv->irq_lock);
4509                 if (dev_priv->display.hpd_irq_setup)
4510                         dev_priv->display.hpd_irq_setup(dev_priv);
4511                 spin_unlock_irq(&dev_priv->irq_lock);
4512
4513                 ret = __intel_display_resume(dev, state, ctx);
4514                 if (ret)
4515                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4516
4517                 intel_hpd_init(dev_priv);
4518         }
4519
4520         drm_atomic_state_put(state);
4521 unlock:
4522         drm_modeset_drop_locks(ctx);
4523         drm_modeset_acquire_fini(ctx);
4524         mutex_unlock(&dev->mode_config.mutex);
4525
4526         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4527 }
4528
4529 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4530 {
4531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4532         enum pipe pipe = crtc->pipe;
4533         u32 tmp;
4534
4535         tmp = I915_READ(PIPE_CHICKEN(pipe));
4536
4537         /*
4538          * Display WA #1153: icl
4539          * enable hardware to bypass the alpha math
4540          * and rounding for per-pixel values 00 and 0xff
4541          */
4542         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4543         /*
4544          * Display WA # 1605353570: icl
4545          * Set the pixel rounding bit to 1 for allowing
4546          * passthrough of Frame buffer pixels unmodified
4547          * across pipe
4548          */
4549         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4550         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4551 }
4552
4553 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4554 {
4555         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4556         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4557         u32 trans_ddi_func_ctl2_val;
4558         u8 master_select;
4559
4560         /*
4561          * Configure the master select and enable Transcoder Port Sync for
4562          * Slave CRTCs transcoder.
4563          */
4564         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4565                 return;
4566
4567         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4568                 master_select = 0;
4569         else
4570                 master_select = crtc_state->master_transcoder + 1;
4571
4572         /* Set the master select bits for Tranascoder Port Sync */
4573         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4574                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4575                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4576         /* Enable Transcoder Port Sync */
4577         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4578
4579         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4580                    trans_ddi_func_ctl2_val);
4581 }
4582
4583 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4584 {
4585         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4587         i915_reg_t reg;
4588         u32 trans_ddi_func_ctl2_val;
4589
4590         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4591                 return;
4592
4593         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4594                       transcoder_name(old_crtc_state->cpu_transcoder));
4595
4596         reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4597         trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4598                                     PORT_SYNC_MODE_MASTER_SELECT_MASK);
4599         I915_WRITE(reg, trans_ddi_func_ctl2_val);
4600 }
4601
4602 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->base.dev;
4605         struct drm_i915_private *dev_priv = to_i915(dev);
4606         enum pipe pipe = crtc->pipe;
4607         i915_reg_t reg;
4608         u32 temp;
4609
4610         /* enable normal train */
4611         reg = FDI_TX_CTL(pipe);
4612         temp = I915_READ(reg);
4613         if (IS_IVYBRIDGE(dev_priv)) {
4614                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4615                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4616         } else {
4617                 temp &= ~FDI_LINK_TRAIN_NONE;
4618                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4619         }
4620         I915_WRITE(reg, temp);
4621
4622         reg = FDI_RX_CTL(pipe);
4623         temp = I915_READ(reg);
4624         if (HAS_PCH_CPT(dev_priv)) {
4625                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4626                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4627         } else {
4628                 temp &= ~FDI_LINK_TRAIN_NONE;
4629                 temp |= FDI_LINK_TRAIN_NONE;
4630         }
4631         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4632
4633         /* wait one idle pattern time */
4634         POSTING_READ(reg);
4635         udelay(1000);
4636
4637         /* IVB wants error correction enabled */
4638         if (IS_IVYBRIDGE(dev_priv))
4639                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4640                            FDI_FE_ERRC_ENABLE);
4641 }
4642
4643 /* The FDI link training functions for ILK/Ibexpeak. */
4644 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4645                                     const struct intel_crtc_state *crtc_state)
4646 {
4647         struct drm_device *dev = crtc->base.dev;
4648         struct drm_i915_private *dev_priv = to_i915(dev);
4649         enum pipe pipe = crtc->pipe;
4650         i915_reg_t reg;
4651         u32 temp, tries;
4652
4653         /* FDI needs bits from pipe first */
4654         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
4655
4656         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4657            for train result */
4658         reg = FDI_RX_IMR(pipe);
4659         temp = I915_READ(reg);
4660         temp &= ~FDI_RX_SYMBOL_LOCK;
4661         temp &= ~FDI_RX_BIT_LOCK;
4662         I915_WRITE(reg, temp);
4663         I915_READ(reg);
4664         udelay(150);
4665
4666         /* enable CPU FDI TX and PCH FDI RX */
4667         reg = FDI_TX_CTL(pipe);
4668         temp = I915_READ(reg);
4669         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4670         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4671         temp &= ~FDI_LINK_TRAIN_NONE;
4672         temp |= FDI_LINK_TRAIN_PATTERN_1;
4673         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4674
4675         reg = FDI_RX_CTL(pipe);
4676         temp = I915_READ(reg);
4677         temp &= ~FDI_LINK_TRAIN_NONE;
4678         temp |= FDI_LINK_TRAIN_PATTERN_1;
4679         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4680
4681         POSTING_READ(reg);
4682         udelay(150);
4683
4684         /* Ironlake workaround, enable clock pointer after FDI enable*/
4685         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4686         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4687                    FDI_RX_PHASE_SYNC_POINTER_EN);
4688
4689         reg = FDI_RX_IIR(pipe);
4690         for (tries = 0; tries < 5; tries++) {
4691                 temp = I915_READ(reg);
4692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4693
4694                 if ((temp & FDI_RX_BIT_LOCK)) {
4695                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4696                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4697                         break;
4698                 }
4699         }
4700         if (tries == 5)
4701                 DRM_ERROR("FDI train 1 fail!\n");
4702
4703         /* Train 2 */
4704         reg = FDI_TX_CTL(pipe);
4705         temp = I915_READ(reg);
4706         temp &= ~FDI_LINK_TRAIN_NONE;
4707         temp |= FDI_LINK_TRAIN_PATTERN_2;
4708         I915_WRITE(reg, temp);
4709
4710         reg = FDI_RX_CTL(pipe);
4711         temp = I915_READ(reg);
4712         temp &= ~FDI_LINK_TRAIN_NONE;
4713         temp |= FDI_LINK_TRAIN_PATTERN_2;
4714         I915_WRITE(reg, temp);
4715
4716         POSTING_READ(reg);
4717         udelay(150);
4718
4719         reg = FDI_RX_IIR(pipe);
4720         for (tries = 0; tries < 5; tries++) {
4721                 temp = I915_READ(reg);
4722                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4723
4724                 if (temp & FDI_RX_SYMBOL_LOCK) {
4725                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4726                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4727                         break;
4728                 }
4729         }
4730         if (tries == 5)
4731                 DRM_ERROR("FDI train 2 fail!\n");
4732
4733         DRM_DEBUG_KMS("FDI train done\n");
4734
4735 }
4736
4737 static const int snb_b_fdi_train_param[] = {
4738         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4739         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4740         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4741         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4742 };
4743
4744 /* The FDI link training functions for SNB/Cougarpoint. */
4745 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4746                                 const struct intel_crtc_state *crtc_state)
4747 {
4748         struct drm_device *dev = crtc->base.dev;
4749         struct drm_i915_private *dev_priv = to_i915(dev);
4750         enum pipe pipe = crtc->pipe;
4751         i915_reg_t reg;
4752         u32 temp, i, retry;
4753
4754         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4755            for train result */
4756         reg = FDI_RX_IMR(pipe);
4757         temp = I915_READ(reg);
4758         temp &= ~FDI_RX_SYMBOL_LOCK;
4759         temp &= ~FDI_RX_BIT_LOCK;
4760         I915_WRITE(reg, temp);
4761
4762         POSTING_READ(reg);
4763         udelay(150);
4764
4765         /* enable CPU FDI TX and PCH FDI RX */
4766         reg = FDI_TX_CTL(pipe);
4767         temp = I915_READ(reg);
4768         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4769         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4770         temp &= ~FDI_LINK_TRAIN_NONE;
4771         temp |= FDI_LINK_TRAIN_PATTERN_1;
4772         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4773         /* SNB-B */
4774         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4776
4777         I915_WRITE(FDI_RX_MISC(pipe),
4778                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4779
4780         reg = FDI_RX_CTL(pipe);
4781         temp = I915_READ(reg);
4782         if (HAS_PCH_CPT(dev_priv)) {
4783                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4784                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4785         } else {
4786                 temp &= ~FDI_LINK_TRAIN_NONE;
4787                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4788         }
4789         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4790
4791         POSTING_READ(reg);
4792         udelay(150);
4793
4794         for (i = 0; i < 4; i++) {
4795                 reg = FDI_TX_CTL(pipe);
4796                 temp = I915_READ(reg);
4797                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4798                 temp |= snb_b_fdi_train_param[i];
4799                 I915_WRITE(reg, temp);
4800
4801                 POSTING_READ(reg);
4802                 udelay(500);
4803
4804                 for (retry = 0; retry < 5; retry++) {
4805                         reg = FDI_RX_IIR(pipe);
4806                         temp = I915_READ(reg);
4807                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4808                         if (temp & FDI_RX_BIT_LOCK) {
4809                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4810                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4811                                 break;
4812                         }
4813                         udelay(50);
4814                 }
4815                 if (retry < 5)
4816                         break;
4817         }
4818         if (i == 4)
4819                 DRM_ERROR("FDI train 1 fail!\n");
4820
4821         /* Train 2 */
4822         reg = FDI_TX_CTL(pipe);
4823         temp = I915_READ(reg);
4824         temp &= ~FDI_LINK_TRAIN_NONE;
4825         temp |= FDI_LINK_TRAIN_PATTERN_2;
4826         if (IS_GEN(dev_priv, 6)) {
4827                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4828                 /* SNB-B */
4829                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4830         }
4831         I915_WRITE(reg, temp);
4832
4833         reg = FDI_RX_CTL(pipe);
4834         temp = I915_READ(reg);
4835         if (HAS_PCH_CPT(dev_priv)) {
4836                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4837                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4838         } else {
4839                 temp &= ~FDI_LINK_TRAIN_NONE;
4840                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4841         }
4842         I915_WRITE(reg, temp);
4843
4844         POSTING_READ(reg);
4845         udelay(150);
4846
4847         for (i = 0; i < 4; i++) {
4848                 reg = FDI_TX_CTL(pipe);
4849                 temp = I915_READ(reg);
4850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4851                 temp |= snb_b_fdi_train_param[i];
4852                 I915_WRITE(reg, temp);
4853
4854                 POSTING_READ(reg);
4855                 udelay(500);
4856
4857                 for (retry = 0; retry < 5; retry++) {
4858                         reg = FDI_RX_IIR(pipe);
4859                         temp = I915_READ(reg);
4860                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4861                         if (temp & FDI_RX_SYMBOL_LOCK) {
4862                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4863                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4864                                 break;
4865                         }
4866                         udelay(50);
4867                 }
4868                 if (retry < 5)
4869                         break;
4870         }
4871         if (i == 4)
4872                 DRM_ERROR("FDI train 2 fail!\n");
4873
4874         DRM_DEBUG_KMS("FDI train done.\n");
4875 }
4876
4877 /* Manual link training for Ivy Bridge A0 parts */
4878 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4879                                       const struct intel_crtc_state *crtc_state)
4880 {
4881         struct drm_device *dev = crtc->base.dev;
4882         struct drm_i915_private *dev_priv = to_i915(dev);
4883         enum pipe pipe = crtc->pipe;
4884         i915_reg_t reg;
4885         u32 temp, i, j;
4886
4887         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4888            for train result */
4889         reg = FDI_RX_IMR(pipe);
4890         temp = I915_READ(reg);
4891         temp &= ~FDI_RX_SYMBOL_LOCK;
4892         temp &= ~FDI_RX_BIT_LOCK;
4893         I915_WRITE(reg, temp);
4894
4895         POSTING_READ(reg);
4896         udelay(150);
4897
4898         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4899                       I915_READ(FDI_RX_IIR(pipe)));
4900
4901         /* Try each vswing and preemphasis setting twice before moving on */
4902         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4903                 /* disable first in case we need to retry */
4904                 reg = FDI_TX_CTL(pipe);
4905                 temp = I915_READ(reg);
4906                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4907                 temp &= ~FDI_TX_ENABLE;
4908                 I915_WRITE(reg, temp);
4909
4910                 reg = FDI_RX_CTL(pipe);
4911                 temp = I915_READ(reg);
4912                 temp &= ~FDI_LINK_TRAIN_AUTO;
4913                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4914                 temp &= ~FDI_RX_ENABLE;
4915                 I915_WRITE(reg, temp);
4916
4917                 /* enable CPU FDI TX and PCH FDI RX */
4918                 reg = FDI_TX_CTL(pipe);
4919                 temp = I915_READ(reg);
4920                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4921                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4922                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4923                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4924                 temp |= snb_b_fdi_train_param[j/2];
4925                 temp |= FDI_COMPOSITE_SYNC;
4926                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4927
4928                 I915_WRITE(FDI_RX_MISC(pipe),
4929                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4930
4931                 reg = FDI_RX_CTL(pipe);
4932                 temp = I915_READ(reg);
4933                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4934                 temp |= FDI_COMPOSITE_SYNC;
4935                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4936
4937                 POSTING_READ(reg);
4938                 udelay(1); /* should be 0.5us */
4939
4940                 for (i = 0; i < 4; i++) {
4941                         reg = FDI_RX_IIR(pipe);
4942                         temp = I915_READ(reg);
4943                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4944
4945                         if (temp & FDI_RX_BIT_LOCK ||
4946                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4948                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4949                                               i);
4950                                 break;
4951                         }
4952                         udelay(1); /* should be 0.5us */
4953                 }
4954                 if (i == 4) {
4955                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4956                         continue;
4957                 }
4958
4959                 /* Train 2 */
4960                 reg = FDI_TX_CTL(pipe);
4961                 temp = I915_READ(reg);
4962                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4963                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4964                 I915_WRITE(reg, temp);
4965
4966                 reg = FDI_RX_CTL(pipe);
4967                 temp = I915_READ(reg);
4968                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4969                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4970                 I915_WRITE(reg, temp);
4971
4972                 POSTING_READ(reg);
4973                 udelay(2); /* should be 1.5us */
4974
4975                 for (i = 0; i < 4; i++) {
4976                         reg = FDI_RX_IIR(pipe);
4977                         temp = I915_READ(reg);
4978                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4979
4980                         if (temp & FDI_RX_SYMBOL_LOCK ||
4981                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4982                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4983                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4984                                               i);
4985                                 goto train_done;
4986                         }
4987                         udelay(2); /* should be 1.5us */
4988                 }
4989                 if (i == 4)
4990                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4991         }
4992
4993 train_done:
4994         DRM_DEBUG_KMS("FDI train done.\n");
4995 }
4996
4997 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4998 {
4999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5000         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5001         enum pipe pipe = intel_crtc->pipe;
5002         i915_reg_t reg;
5003         u32 temp;
5004
5005         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5006         reg = FDI_RX_CTL(pipe);
5007         temp = I915_READ(reg);
5008         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5009         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5010         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5011         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
5012
5013         POSTING_READ(reg);
5014         udelay(200);
5015
5016         /* Switch from Rawclk to PCDclk */
5017         temp = I915_READ(reg);
5018         I915_WRITE(reg, temp | FDI_PCDCLK);
5019
5020         POSTING_READ(reg);
5021         udelay(200);
5022
5023         /* Enable CPU FDI TX PLL, always on for Ironlake */
5024         reg = FDI_TX_CTL(pipe);
5025         temp = I915_READ(reg);
5026         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5027                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5028
5029                 POSTING_READ(reg);
5030                 udelay(100);
5031         }
5032 }
5033
5034 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
5035 {
5036         struct drm_device *dev = intel_crtc->base.dev;
5037         struct drm_i915_private *dev_priv = to_i915(dev);
5038         enum pipe pipe = intel_crtc->pipe;
5039         i915_reg_t reg;
5040         u32 temp;
5041
5042         /* Switch from PCDclk to Rawclk */
5043         reg = FDI_RX_CTL(pipe);
5044         temp = I915_READ(reg);
5045         I915_WRITE(reg, temp & ~FDI_PCDCLK);
5046
5047         /* Disable CPU FDI TX PLL */
5048         reg = FDI_TX_CTL(pipe);
5049         temp = I915_READ(reg);
5050         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
5051
5052         POSTING_READ(reg);
5053         udelay(100);
5054
5055         reg = FDI_RX_CTL(pipe);
5056         temp = I915_READ(reg);
5057         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5058
5059         /* Wait for the clocks to turn off. */
5060         POSTING_READ(reg);
5061         udelay(100);
5062 }
5063
5064 static void ironlake_fdi_disable(struct intel_crtc *crtc)
5065 {
5066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5067         enum pipe pipe = crtc->pipe;
5068         i915_reg_t reg;
5069         u32 temp;
5070
5071         /* disable CPU FDI tx and PCH FDI rx */
5072         reg = FDI_TX_CTL(pipe);
5073         temp = I915_READ(reg);
5074         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5075         POSTING_READ(reg);
5076
5077         reg = FDI_RX_CTL(pipe);
5078         temp = I915_READ(reg);
5079         temp &= ~(0x7 << 16);
5080         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5081         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5082
5083         POSTING_READ(reg);
5084         udelay(100);
5085
5086         /* Ironlake workaround, disable clock pointer after downing FDI */
5087         if (HAS_PCH_IBX(dev_priv))
5088                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5089
5090         /* still set train pattern 1 */
5091         reg = FDI_TX_CTL(pipe);
5092         temp = I915_READ(reg);
5093         temp &= ~FDI_LINK_TRAIN_NONE;
5094         temp |= FDI_LINK_TRAIN_PATTERN_1;
5095         I915_WRITE(reg, temp);
5096
5097         reg = FDI_RX_CTL(pipe);
5098         temp = I915_READ(reg);
5099         if (HAS_PCH_CPT(dev_priv)) {
5100                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5101                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5102         } else {
5103                 temp &= ~FDI_LINK_TRAIN_NONE;
5104                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5105         }
5106         /* BPC in FDI rx is consistent with that in PIPECONF */
5107         temp &= ~(0x07 << 16);
5108         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5109         I915_WRITE(reg, temp);
5110
5111         POSTING_READ(reg);
5112         udelay(100);
5113 }
5114
5115 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5116 {
5117         struct drm_crtc *crtc;
5118         bool cleanup_done;
5119
5120         drm_for_each_crtc(crtc, &dev_priv->drm) {
5121                 struct drm_crtc_commit *commit;
5122                 spin_lock(&crtc->commit_lock);
5123                 commit = list_first_entry_or_null(&crtc->commit_list,
5124                                                   struct drm_crtc_commit, commit_entry);
5125                 cleanup_done = commit ?
5126                         try_wait_for_completion(&commit->cleanup_done) : true;
5127                 spin_unlock(&crtc->commit_lock);
5128
5129                 if (cleanup_done)
5130                         continue;
5131
5132                 drm_crtc_wait_one_vblank(crtc);
5133
5134                 return true;
5135         }
5136
5137         return false;
5138 }
5139
5140 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5141 {
5142         u32 temp;
5143
5144         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5145
5146         mutex_lock(&dev_priv->sb_lock);
5147
5148         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5149         temp |= SBI_SSCCTL_DISABLE;
5150         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5151
5152         mutex_unlock(&dev_priv->sb_lock);
5153 }
5154
5155 /* Program iCLKIP clock to the desired frequency */
5156 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5157 {
5158         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5159         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5160         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5161         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5162         u32 temp;
5163
5164         lpt_disable_iclkip(dev_priv);
5165
5166         /* The iCLK virtual clock root frequency is in MHz,
5167          * but the adjusted_mode->crtc_clock in in KHz. To get the
5168          * divisors, it is necessary to divide one by another, so we
5169          * convert the virtual clock precision to KHz here for higher
5170          * precision.
5171          */
5172         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5173                 u32 iclk_virtual_root_freq = 172800 * 1000;
5174                 u32 iclk_pi_range = 64;
5175                 u32 desired_divisor;
5176
5177                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5178                                                     clock << auxdiv);
5179                 divsel = (desired_divisor / iclk_pi_range) - 2;
5180                 phaseinc = desired_divisor % iclk_pi_range;
5181
5182                 /*
5183                  * Near 20MHz is a corner case which is
5184                  * out of range for the 7-bit divisor
5185                  */
5186                 if (divsel <= 0x7f)
5187                         break;
5188         }
5189
5190         /* This should not happen with any sane values */
5191         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5192                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5193         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5194                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5195
5196         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5197                         clock,
5198                         auxdiv,
5199                         divsel,
5200                         phasedir,
5201                         phaseinc);
5202
5203         mutex_lock(&dev_priv->sb_lock);
5204
5205         /* Program SSCDIVINTPHASE6 */
5206         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5207         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5208         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5209         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5210         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5211         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5212         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5213         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5214
5215         /* Program SSCAUXDIV */
5216         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5217         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5218         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5219         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5220
5221         /* Enable modulator and associated divider */
5222         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5223         temp &= ~SBI_SSCCTL_DISABLE;
5224         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5225
5226         mutex_unlock(&dev_priv->sb_lock);
5227
5228         /* Wait for initialization time */
5229         udelay(24);
5230
5231         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5232 }
5233
5234 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5235 {
5236         u32 divsel, phaseinc, auxdiv;
5237         u32 iclk_virtual_root_freq = 172800 * 1000;
5238         u32 iclk_pi_range = 64;
5239         u32 desired_divisor;
5240         u32 temp;
5241
5242         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5243                 return 0;
5244
5245         mutex_lock(&dev_priv->sb_lock);
5246
5247         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5248         if (temp & SBI_SSCCTL_DISABLE) {
5249                 mutex_unlock(&dev_priv->sb_lock);
5250                 return 0;
5251         }
5252
5253         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5254         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5255                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5256         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5257                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5258
5259         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5260         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5261                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5262
5263         mutex_unlock(&dev_priv->sb_lock);
5264
5265         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5266
5267         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5268                                  desired_divisor << auxdiv);
5269 }
5270
5271 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5272                                                 enum pipe pch_transcoder)
5273 {
5274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5276         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5277
5278         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5279                    I915_READ(HTOTAL(cpu_transcoder)));
5280         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5281                    I915_READ(HBLANK(cpu_transcoder)));
5282         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5283                    I915_READ(HSYNC(cpu_transcoder)));
5284
5285         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5286                    I915_READ(VTOTAL(cpu_transcoder)));
5287         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5288                    I915_READ(VBLANK(cpu_transcoder)));
5289         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5290                    I915_READ(VSYNC(cpu_transcoder)));
5291         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5292                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5293 }
5294
5295 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5296 {
5297         u32 temp;
5298
5299         temp = I915_READ(SOUTH_CHICKEN1);
5300         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5301                 return;
5302
5303         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5304         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5305
5306         temp &= ~FDI_BC_BIFURCATION_SELECT;
5307         if (enable)
5308                 temp |= FDI_BC_BIFURCATION_SELECT;
5309
5310         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5311         I915_WRITE(SOUTH_CHICKEN1, temp);
5312         POSTING_READ(SOUTH_CHICKEN1);
5313 }
5314
5315 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5316 {
5317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5319
5320         switch (crtc->pipe) {
5321         case PIPE_A:
5322                 break;
5323         case PIPE_B:
5324                 if (crtc_state->fdi_lanes > 2)
5325                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5326                 else
5327                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5328
5329                 break;
5330         case PIPE_C:
5331                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5332
5333                 break;
5334         default:
5335                 BUG();
5336         }
5337 }
5338
5339 /*
5340  * Finds the encoder associated with the given CRTC. This can only be
5341  * used when we know that the CRTC isn't feeding multiple encoders!
5342  */
5343 static struct intel_encoder *
5344 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5345                            const struct intel_crtc_state *crtc_state)
5346 {
5347         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5348         const struct drm_connector_state *connector_state;
5349         const struct drm_connector *connector;
5350         struct intel_encoder *encoder = NULL;
5351         int num_encoders = 0;
5352         int i;
5353
5354         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5355                 if (connector_state->crtc != &crtc->base)
5356                         continue;
5357
5358                 encoder = to_intel_encoder(connector_state->best_encoder);
5359                 num_encoders++;
5360         }
5361
5362         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5363              num_encoders, pipe_name(crtc->pipe));
5364
5365         return encoder;
5366 }
5367
5368 /*
5369  * Enable PCH resources required for PCH ports:
5370  *   - PCH PLLs
5371  *   - FDI training & RX/TX
5372  *   - update transcoder timings
5373  *   - DP transcoding bits
5374  *   - transcoder
5375  */
5376 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5377                                 const struct intel_crtc_state *crtc_state)
5378 {
5379         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = to_i915(dev);
5382         enum pipe pipe = crtc->pipe;
5383         u32 temp;
5384
5385         assert_pch_transcoder_disabled(dev_priv, pipe);
5386
5387         if (IS_IVYBRIDGE(dev_priv))
5388                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5389
5390         /* Write the TU size bits before fdi link training, so that error
5391          * detection works. */
5392         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5393                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5394
5395         /* For PCH output, training FDI link */
5396         dev_priv->display.fdi_link_train(crtc, crtc_state);
5397
5398         /* We need to program the right clock selection before writing the pixel
5399          * mutliplier into the DPLL. */
5400         if (HAS_PCH_CPT(dev_priv)) {
5401                 u32 sel;
5402
5403                 temp = I915_READ(PCH_DPLL_SEL);
5404                 temp |= TRANS_DPLL_ENABLE(pipe);
5405                 sel = TRANS_DPLLB_SEL(pipe);
5406                 if (crtc_state->shared_dpll ==
5407                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5408                         temp |= sel;
5409                 else
5410                         temp &= ~sel;
5411                 I915_WRITE(PCH_DPLL_SEL, temp);
5412         }
5413
5414         /* XXX: pch pll's can be enabled any time before we enable the PCH
5415          * transcoder, and we actually should do this to not upset any PCH
5416          * transcoder that already use the clock when we share it.
5417          *
5418          * Note that enable_shared_dpll tries to do the right thing, but
5419          * get_shared_dpll unconditionally resets the pll - we need that to have
5420          * the right LVDS enable sequence. */
5421         intel_enable_shared_dpll(crtc_state);
5422
5423         /* set transcoder timing, panel must allow it */
5424         assert_panel_unlocked(dev_priv, pipe);
5425         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5426
5427         intel_fdi_normal_train(crtc);
5428
5429         /* For PCH DP, enable TRANS_DP_CTL */
5430         if (HAS_PCH_CPT(dev_priv) &&
5431             intel_crtc_has_dp_encoder(crtc_state)) {
5432                 const struct drm_display_mode *adjusted_mode =
5433                         &crtc_state->hw.adjusted_mode;
5434                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5435                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5436                 enum port port;
5437
5438                 temp = I915_READ(reg);
5439                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5440                           TRANS_DP_SYNC_MASK |
5441                           TRANS_DP_BPC_MASK);
5442                 temp |= TRANS_DP_OUTPUT_ENABLE;
5443                 temp |= bpc << 9; /* same format but at 11:9 */
5444
5445                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5446                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5447                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5448                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5449
5450                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5451                 WARN_ON(port < PORT_B || port > PORT_D);
5452                 temp |= TRANS_DP_PORT_SEL(port);
5453
5454                 I915_WRITE(reg, temp);
5455         }
5456
5457         ironlake_enable_pch_transcoder(crtc_state);
5458 }
5459
5460 static void lpt_pch_enable(const struct intel_atomic_state *state,
5461                            const struct intel_crtc_state *crtc_state)
5462 {
5463         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5465         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5466
5467         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5468
5469         lpt_program_iclkip(crtc_state);
5470
5471         /* Set transcoder timing. */
5472         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5473
5474         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5475 }
5476
5477 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5478                                enum pipe pipe)
5479 {
5480         i915_reg_t dslreg = PIPEDSL(pipe);
5481         u32 temp;
5482
5483         temp = I915_READ(dslreg);
5484         udelay(500);
5485         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5486                 if (wait_for(I915_READ(dslreg) != temp, 5))
5487                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5488         }
5489 }
5490
5491 /*
5492  * The hardware phase 0.0 refers to the center of the pixel.
5493  * We want to start from the top/left edge which is phase
5494  * -0.5. That matches how the hardware calculates the scaling
5495  * factors (from top-left of the first pixel to bottom-right
5496  * of the last pixel, as opposed to the pixel centers).
5497  *
5498  * For 4:2:0 subsampled chroma planes we obviously have to
5499  * adjust that so that the chroma sample position lands in
5500  * the right spot.
5501  *
5502  * Note that for packed YCbCr 4:2:2 formats there is no way to
5503  * control chroma siting. The hardware simply replicates the
5504  * chroma samples for both of the luma samples, and thus we don't
5505  * actually get the expected MPEG2 chroma siting convention :(
5506  * The same behaviour is observed on pre-SKL platforms as well.
5507  *
5508  * Theory behind the formula (note that we ignore sub-pixel
5509  * source coordinates):
5510  * s = source sample position
5511  * d = destination sample position
5512  *
5513  * Downscaling 4:1:
5514  * -0.5
5515  * | 0.0
5516  * | |     1.5 (initial phase)
5517  * | |     |
5518  * v v     v
5519  * | s | s | s | s |
5520  * |       d       |
5521  *
5522  * Upscaling 1:4:
5523  * -0.5
5524  * | -0.375 (initial phase)
5525  * | |     0.0
5526  * | |     |
5527  * v v     v
5528  * |       s       |
5529  * | d | d | d | d |
5530  */
5531 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5532 {
5533         int phase = -0x8000;
5534         u16 trip = 0;
5535
5536         if (chroma_cosited)
5537                 phase += (sub - 1) * 0x8000 / sub;
5538
5539         phase += scale / (2 * sub);
5540
5541         /*
5542          * Hardware initial phase limited to [-0.5:1.5].
5543          * Since the max hardware scale factor is 3.0, we
5544          * should never actually excdeed 1.0 here.
5545          */
5546         WARN_ON(phase < -0x8000 || phase > 0x18000);
5547
5548         if (phase < 0)
5549                 phase = 0x10000 + phase;
5550         else
5551                 trip = PS_PHASE_TRIP;
5552
5553         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5554 }
5555
5556 #define SKL_MIN_SRC_W 8
5557 #define SKL_MAX_SRC_W 4096
5558 #define SKL_MIN_SRC_H 8
5559 #define SKL_MAX_SRC_H 4096
5560 #define SKL_MIN_DST_W 8
5561 #define SKL_MAX_DST_W 4096
5562 #define SKL_MIN_DST_H 8
5563 #define SKL_MAX_DST_H 4096
5564 #define ICL_MAX_SRC_W 5120
5565 #define ICL_MAX_SRC_H 4096
5566 #define ICL_MAX_DST_W 5120
5567 #define ICL_MAX_DST_H 4096
5568 #define SKL_MIN_YUV_420_SRC_W 16
5569 #define SKL_MIN_YUV_420_SRC_H 16
5570
5571 static int
5572 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5573                   unsigned int scaler_user, int *scaler_id,
5574                   int src_w, int src_h, int dst_w, int dst_h,
5575                   const struct drm_format_info *format, bool need_scaler)
5576 {
5577         struct intel_crtc_scaler_state *scaler_state =
5578                 &crtc_state->scaler_state;
5579         struct intel_crtc *intel_crtc =
5580                 to_intel_crtc(crtc_state->uapi.crtc);
5581         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5582         const struct drm_display_mode *adjusted_mode =
5583                 &crtc_state->hw.adjusted_mode;
5584
5585         /*
5586          * Src coordinates are already rotated by 270 degrees for
5587          * the 90/270 degree plane rotation cases (to match the
5588          * GTT mapping), hence no need to account for rotation here.
5589          */
5590         if (src_w != dst_w || src_h != dst_h)
5591                 need_scaler = true;
5592
5593         /*
5594          * Scaling/fitting not supported in IF-ID mode in GEN9+
5595          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5596          * Once NV12 is enabled, handle it here while allocating scaler
5597          * for NV12.
5598          */
5599         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5600             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5601                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5602                 return -EINVAL;
5603         }
5604
5605         /*
5606          * if plane is being disabled or scaler is no more required or force detach
5607          *  - free scaler binded to this plane/crtc
5608          *  - in order to do this, update crtc->scaler_usage
5609          *
5610          * Here scaler state in crtc_state is set free so that
5611          * scaler can be assigned to other user. Actual register
5612          * update to free the scaler is done in plane/panel-fit programming.
5613          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5614          */
5615         if (force_detach || !need_scaler) {
5616                 if (*scaler_id >= 0) {
5617                         scaler_state->scaler_users &= ~(1 << scaler_user);
5618                         scaler_state->scalers[*scaler_id].in_use = 0;
5619
5620                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5621                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5622                                 intel_crtc->pipe, scaler_user, *scaler_id,
5623                                 scaler_state->scaler_users);
5624                         *scaler_id = -1;
5625                 }
5626                 return 0;
5627         }
5628
5629         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5630             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5631                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5632                 return -EINVAL;
5633         }
5634
5635         /* range checks */
5636         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5637             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5638             (INTEL_GEN(dev_priv) >= 11 &&
5639              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5640               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5641             (INTEL_GEN(dev_priv) < 11 &&
5642              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5643               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5644                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5645                         "size is out of scaler range\n",
5646                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5647                 return -EINVAL;
5648         }
5649
5650         /* mark this plane as a scaler user in crtc_state */
5651         scaler_state->scaler_users |= (1 << scaler_user);
5652         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5653                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5654                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5655                 scaler_state->scaler_users);
5656
5657         return 0;
5658 }
5659
5660 /**
5661  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5662  *
5663  * @state: crtc's scaler state
5664  *
5665  * Return
5666  *     0 - scaler_usage updated successfully
5667  *    error - requested scaling cannot be supported or other error condition
5668  */
5669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5670 {
5671         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5672         bool need_scaler = false;
5673
5674         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5675                 need_scaler = true;
5676
5677         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5678                                  &state->scaler_state.scaler_id,
5679                                  state->pipe_src_w, state->pipe_src_h,
5680                                  adjusted_mode->crtc_hdisplay,
5681                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5682 }
5683
5684 /**
5685  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5686  * @crtc_state: crtc's scaler state
5687  * @plane_state: atomic plane state to update
5688  *
5689  * Return
5690  *     0 - scaler_usage updated successfully
5691  *    error - requested scaling cannot be supported or other error condition
5692  */
5693 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5694                                    struct intel_plane_state *plane_state)
5695 {
5696         struct intel_plane *intel_plane =
5697                 to_intel_plane(plane_state->uapi.plane);
5698         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5699         struct drm_framebuffer *fb = plane_state->hw.fb;
5700         int ret;
5701         bool force_detach = !fb || !plane_state->uapi.visible;
5702         bool need_scaler = false;
5703
5704         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5705         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5706             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5707                 need_scaler = true;
5708
5709         ret = skl_update_scaler(crtc_state, force_detach,
5710                                 drm_plane_index(&intel_plane->base),
5711                                 &plane_state->scaler_id,
5712                                 drm_rect_width(&plane_state->uapi.src) >> 16,
5713                                 drm_rect_height(&plane_state->uapi.src) >> 16,
5714                                 drm_rect_width(&plane_state->uapi.dst),
5715                                 drm_rect_height(&plane_state->uapi.dst),
5716                                 fb ? fb->format : NULL, need_scaler);
5717
5718         if (ret || plane_state->scaler_id < 0)
5719                 return ret;
5720
5721         /* check colorkey */
5722         if (plane_state->ckey.flags) {
5723                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5724                               intel_plane->base.base.id,
5725                               intel_plane->base.name);
5726                 return -EINVAL;
5727         }
5728
5729         /* Check src format */
5730         switch (fb->format->format) {
5731         case DRM_FORMAT_RGB565:
5732         case DRM_FORMAT_XBGR8888:
5733         case DRM_FORMAT_XRGB8888:
5734         case DRM_FORMAT_ABGR8888:
5735         case DRM_FORMAT_ARGB8888:
5736         case DRM_FORMAT_XRGB2101010:
5737         case DRM_FORMAT_XBGR2101010:
5738         case DRM_FORMAT_ARGB2101010:
5739         case DRM_FORMAT_ABGR2101010:
5740         case DRM_FORMAT_YUYV:
5741         case DRM_FORMAT_YVYU:
5742         case DRM_FORMAT_UYVY:
5743         case DRM_FORMAT_VYUY:
5744         case DRM_FORMAT_NV12:
5745         case DRM_FORMAT_P010:
5746         case DRM_FORMAT_P012:
5747         case DRM_FORMAT_P016:
5748         case DRM_FORMAT_Y210:
5749         case DRM_FORMAT_Y212:
5750         case DRM_FORMAT_Y216:
5751         case DRM_FORMAT_XVYU2101010:
5752         case DRM_FORMAT_XVYU12_16161616:
5753         case DRM_FORMAT_XVYU16161616:
5754                 break;
5755         case DRM_FORMAT_XBGR16161616F:
5756         case DRM_FORMAT_ABGR16161616F:
5757         case DRM_FORMAT_XRGB16161616F:
5758         case DRM_FORMAT_ARGB16161616F:
5759                 if (INTEL_GEN(dev_priv) >= 11)
5760                         break;
5761                 /* fall through */
5762         default:
5763                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5764                               intel_plane->base.base.id, intel_plane->base.name,
5765                               fb->base.id, fb->format->format);
5766                 return -EINVAL;
5767         }
5768
5769         return 0;
5770 }
5771
5772 static void skylake_scaler_disable(const struct intel_crtc_state *old_crtc_state)
5773 {
5774         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
5775         int i;
5776
5777         for (i = 0; i < crtc->num_scalers; i++)
5778                 skl_detach_scaler(crtc, i);
5779 }
5780
5781 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5782 {
5783         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5784         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5785         enum pipe pipe = crtc->pipe;
5786         const struct intel_crtc_scaler_state *scaler_state =
5787                 &crtc_state->scaler_state;
5788
5789         if (crtc_state->pch_pfit.enabled) {
5790                 u16 uv_rgb_hphase, uv_rgb_vphase;
5791                 int pfit_w, pfit_h, hscale, vscale;
5792                 int id;
5793
5794                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5795                         return;
5796
5797                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5798                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5799
5800                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5801                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5802
5803                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5804                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5805
5806                 id = scaler_state->scaler_id;
5807                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5808                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5809                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5810                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5811                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5812                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5813                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5814                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5815         }
5816 }
5817
5818 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5819 {
5820         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5821         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5822         enum pipe pipe = crtc->pipe;
5823
5824         if (crtc_state->pch_pfit.enabled) {
5825                 /* Force use of hard-coded filter coefficients
5826                  * as some pre-programmed values are broken,
5827                  * e.g. x201.
5828                  */
5829                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5830                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5831                                                  PF_PIPE_SEL_IVB(pipe));
5832                 else
5833                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5834                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5835                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5836         }
5837 }
5838
5839 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5840 {
5841         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5842         struct drm_device *dev = crtc->base.dev;
5843         struct drm_i915_private *dev_priv = to_i915(dev);
5844
5845         if (!crtc_state->ips_enabled)
5846                 return;
5847
5848         /*
5849          * We can only enable IPS after we enable a plane and wait for a vblank
5850          * This function is called from post_plane_update, which is run after
5851          * a vblank wait.
5852          */
5853         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5854
5855         if (IS_BROADWELL(dev_priv)) {
5856                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5857                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5858                 /* Quoting Art Runyan: "its not safe to expect any particular
5859                  * value in IPS_CTL bit 31 after enabling IPS through the
5860                  * mailbox." Moreover, the mailbox may return a bogus state,
5861                  * so we need to just enable it and continue on.
5862                  */
5863         } else {
5864                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5865                 /* The bit only becomes 1 in the next vblank, so this wait here
5866                  * is essentially intel_wait_for_vblank. If we don't have this
5867                  * and don't wait for vblanks until the end of crtc_enable, then
5868                  * the HW state readout code will complain that the expected
5869                  * IPS_CTL value is not the one we read. */
5870                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5871                         DRM_ERROR("Timed out waiting for IPS enable\n");
5872         }
5873 }
5874
5875 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5876 {
5877         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5878         struct drm_device *dev = crtc->base.dev;
5879         struct drm_i915_private *dev_priv = to_i915(dev);
5880
5881         if (!crtc_state->ips_enabled)
5882                 return;
5883
5884         if (IS_BROADWELL(dev_priv)) {
5885                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5886                 /*
5887                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5888                  * 42ms timeout value leads to occasional timeouts so use 100ms
5889                  * instead.
5890                  */
5891                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5892                         DRM_ERROR("Timed out waiting for IPS disable\n");
5893         } else {
5894                 I915_WRITE(IPS_CTL, 0);
5895                 POSTING_READ(IPS_CTL);
5896         }
5897
5898         /* We need to wait for a vblank before we can disable the plane. */
5899         intel_wait_for_vblank(dev_priv, crtc->pipe);
5900 }
5901
5902 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5903 {
5904         if (intel_crtc->overlay)
5905                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5906
5907         /* Let userspace switch the overlay on again. In most cases userspace
5908          * has to recompute where to put it anyway.
5909          */
5910 }
5911
5912 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5913                                        const struct intel_crtc_state *new_crtc_state)
5914 {
5915         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5916         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5917
5918         if (!old_crtc_state->ips_enabled)
5919                 return false;
5920
5921         if (needs_modeset(new_crtc_state))
5922                 return true;
5923
5924         /*
5925          * Workaround : Do not read or write the pipe palette/gamma data while
5926          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5927          *
5928          * Disable IPS before we program the LUT.
5929          */
5930         if (IS_HASWELL(dev_priv) &&
5931             (new_crtc_state->uapi.color_mgmt_changed ||
5932              new_crtc_state->update_pipe) &&
5933             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5934                 return true;
5935
5936         return !new_crtc_state->ips_enabled;
5937 }
5938
5939 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5940                                        const struct intel_crtc_state *new_crtc_state)
5941 {
5942         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5943         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5944
5945         if (!new_crtc_state->ips_enabled)
5946                 return false;
5947
5948         if (needs_modeset(new_crtc_state))
5949                 return true;
5950
5951         /*
5952          * Workaround : Do not read or write the pipe palette/gamma data while
5953          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5954          *
5955          * Re-enable IPS after the LUT has been programmed.
5956          */
5957         if (IS_HASWELL(dev_priv) &&
5958             (new_crtc_state->uapi.color_mgmt_changed ||
5959              new_crtc_state->update_pipe) &&
5960             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5961                 return true;
5962
5963         /*
5964          * We can't read out IPS on broadwell, assume the worst and
5965          * forcibly enable IPS on the first fastset.
5966          */
5967         if (new_crtc_state->update_pipe &&
5968             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5969                 return true;
5970
5971         return !old_crtc_state->ips_enabled;
5972 }
5973
5974 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
5975 {
5976         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5977
5978         if (!crtc_state->nv12_planes)
5979                 return false;
5980
5981         /* WA Display #0827: Gen9:all */
5982         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5983                 return true;
5984
5985         return false;
5986 }
5987
5988 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
5989 {
5990         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5991
5992         /* Wa_2006604312:icl */
5993         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
5994                 return true;
5995
5996         return false;
5997 }
5998
5999 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6000                             const struct intel_crtc_state *new_crtc_state)
6001 {
6002         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6003                 new_crtc_state->active_planes;
6004 }
6005
6006 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6007                              const struct intel_crtc_state *new_crtc_state)
6008 {
6009         return old_crtc_state->active_planes &&
6010                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6011 }
6012
6013 static void intel_post_plane_update(struct intel_atomic_state *state,
6014                                     struct intel_crtc *crtc)
6015 {
6016         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6017         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
6018         const struct intel_crtc_state *old_crtc_state =
6019                 intel_atomic_get_old_crtc_state(state, crtc);
6020         const struct intel_crtc_state *new_crtc_state =
6021                 intel_atomic_get_new_crtc_state(state, crtc);
6022         const struct intel_plane_state *new_primary_state =
6023                 intel_atomic_get_new_plane_state(state, primary);
6024         enum pipe pipe = crtc->pipe;
6025
6026         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6027
6028         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6029                 intel_update_watermarks(crtc);
6030
6031         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6032                 hsw_enable_ips(new_crtc_state);
6033
6034         if (new_primary_state)
6035                 intel_fbc_post_update(crtc);
6036
6037         if (needs_nv12_wa(old_crtc_state) &&
6038             !needs_nv12_wa(new_crtc_state))
6039                 skl_wa_827(dev_priv, pipe, false);
6040
6041         if (needs_scalerclk_wa(old_crtc_state) &&
6042             !needs_scalerclk_wa(new_crtc_state))
6043                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6044 }
6045
6046 static void intel_pre_plane_update(struct intel_atomic_state *state,
6047                                    struct intel_crtc *crtc)
6048 {
6049         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6050         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
6051         const struct intel_crtc_state *old_crtc_state =
6052                 intel_atomic_get_old_crtc_state(state, crtc);
6053         const struct intel_crtc_state *new_crtc_state =
6054                 intel_atomic_get_new_crtc_state(state, crtc);
6055         const struct intel_plane_state *new_primary_state =
6056                 intel_atomic_get_new_plane_state(state, primary);
6057         enum pipe pipe = crtc->pipe;
6058
6059         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6060                 hsw_disable_ips(old_crtc_state);
6061
6062         if (new_primary_state &&
6063             intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state))
6064                 intel_wait_for_vblank(dev_priv, pipe);
6065
6066         if (new_primary_state)
6067                 intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
6068
6069         /* Display WA 827 */
6070         if (!needs_nv12_wa(old_crtc_state) &&
6071             needs_nv12_wa(new_crtc_state))
6072                 skl_wa_827(dev_priv, pipe, true);
6073
6074         /* Wa_2006604312:icl */
6075         if (!needs_scalerclk_wa(old_crtc_state) &&
6076             needs_scalerclk_wa(new_crtc_state))
6077                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6078
6079         /*
6080          * Vblank time updates from the shadow to live plane control register
6081          * are blocked if the memory self-refresh mode is active at that
6082          * moment. So to make sure the plane gets truly disabled, disable
6083          * first the self-refresh mode. The self-refresh enable bit in turn
6084          * will be checked/applied by the HW only at the next frame start
6085          * event which is after the vblank start event, so we need to have a
6086          * wait-for-vblank between disabling the plane and the pipe.
6087          */
6088         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6089             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6090                 intel_wait_for_vblank(dev_priv, pipe);
6091
6092         /*
6093          * IVB workaround: must disable low power watermarks for at least
6094          * one frame before enabling scaling.  LP watermarks can be re-enabled
6095          * when scaling is disabled.
6096          *
6097          * WaCxSRDisabledForSpriteScaling:ivb
6098          */
6099         if (old_crtc_state->hw.active &&
6100             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6101                 intel_wait_for_vblank(dev_priv, pipe);
6102
6103         /*
6104          * If we're doing a modeset we don't need to do any
6105          * pre-vblank watermark programming here.
6106          */
6107         if (!needs_modeset(new_crtc_state)) {
6108                 /*
6109                  * For platforms that support atomic watermarks, program the
6110                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6111                  * will be the intermediate values that are safe for both pre- and
6112                  * post- vblank; when vblank happens, the 'active' values will be set
6113                  * to the final 'target' values and we'll do this again to get the
6114                  * optimal watermarks.  For gen9+ platforms, the values we program here
6115                  * will be the final target values which will get automatically latched
6116                  * at vblank time; no further programming will be necessary.
6117                  *
6118                  * If a platform hasn't been transitioned to atomic watermarks yet,
6119                  * we'll continue to update watermarks the old way, if flags tell
6120                  * us to.
6121                  */
6122                 if (dev_priv->display.initial_watermarks)
6123                         dev_priv->display.initial_watermarks(state, crtc);
6124                 else if (new_crtc_state->update_wm_pre)
6125                         intel_update_watermarks(crtc);
6126         }
6127
6128         /*
6129          * Gen2 reports pipe underruns whenever all planes are disabled.
6130          * So disable underrun reporting before all the planes get disabled.
6131          *
6132          * We do this after .initial_watermarks() so that we have a
6133          * chance of catching underruns with the intermediate watermarks
6134          * vs. the old plane configuration.
6135          */
6136         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6137                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6138 }
6139
6140 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6141                                       struct intel_crtc *crtc)
6142 {
6143         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6144         const struct intel_crtc_state *new_crtc_state =
6145                 intel_atomic_get_new_crtc_state(state, crtc);
6146         unsigned int update_mask = new_crtc_state->update_planes;
6147         const struct intel_plane_state *old_plane_state;
6148         struct intel_plane *plane;
6149         unsigned fb_bits = 0;
6150         int i;
6151
6152         intel_crtc_dpms_overlay_disable(crtc);
6153
6154         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6155                 if (crtc->pipe != plane->pipe ||
6156                     !(update_mask & BIT(plane->id)))
6157                         continue;
6158
6159                 intel_disable_plane(plane, new_crtc_state);
6160
6161                 if (old_plane_state->uapi.visible)
6162                         fb_bits |= plane->frontbuffer_bit;
6163         }
6164
6165         intel_frontbuffer_flip(dev_priv, fb_bits);
6166 }
6167
6168 /*
6169  * intel_connector_primary_encoder - get the primary encoder for a connector
6170  * @connector: connector for which to return the encoder
6171  *
6172  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6173  * all connectors to their encoder, except for DP-MST connectors which have
6174  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6175  * pointed to by as many DP-MST connectors as there are pipes.
6176  */
6177 static struct intel_encoder *
6178 intel_connector_primary_encoder(struct intel_connector *connector)
6179 {
6180         struct intel_encoder *encoder;
6181
6182         if (connector->mst_port)
6183                 return &dp_to_dig_port(connector->mst_port)->base;
6184
6185         encoder = intel_attached_encoder(&connector->base);
6186         WARN_ON(!encoder);
6187
6188         return encoder;
6189 }
6190
6191 static bool
6192 intel_connector_needs_modeset(struct intel_atomic_state *state,
6193                               const struct drm_connector_state *old_conn_state,
6194                               const struct drm_connector_state *new_conn_state)
6195 {
6196         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6197                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6198         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6199                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6200
6201         return new_crtc != old_crtc ||
6202                (new_crtc &&
6203                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6204 }
6205
6206 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6207 {
6208         struct drm_connector_state *old_conn_state;
6209         struct drm_connector_state *new_conn_state;
6210         struct drm_connector *conn;
6211         int i;
6212
6213         for_each_oldnew_connector_in_state(&state->base, conn,
6214                                            old_conn_state, new_conn_state, i) {
6215                 struct intel_encoder *encoder;
6216                 struct intel_crtc *crtc;
6217
6218                 if (!intel_connector_needs_modeset(state,
6219                                                    old_conn_state,
6220                                                    new_conn_state))
6221                         continue;
6222
6223                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6224                 if (!encoder->update_prepare)
6225                         continue;
6226
6227                 crtc = new_conn_state->crtc ?
6228                         to_intel_crtc(new_conn_state->crtc) : NULL;
6229                 encoder->update_prepare(state, encoder, crtc);
6230         }
6231 }
6232
6233 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6234 {
6235         struct drm_connector_state *old_conn_state;
6236         struct drm_connector_state *new_conn_state;
6237         struct drm_connector *conn;
6238         int i;
6239
6240         for_each_oldnew_connector_in_state(&state->base, conn,
6241                                            old_conn_state, new_conn_state, i) {
6242                 struct intel_encoder *encoder;
6243                 struct intel_crtc *crtc;
6244
6245                 if (!intel_connector_needs_modeset(state,
6246                                                    old_conn_state,
6247                                                    new_conn_state))
6248                         continue;
6249
6250                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6251                 if (!encoder->update_complete)
6252                         continue;
6253
6254                 crtc = new_conn_state->crtc ?
6255                         to_intel_crtc(new_conn_state->crtc) : NULL;
6256                 encoder->update_complete(state, encoder, crtc);
6257         }
6258 }
6259
6260 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6261                                           struct intel_crtc *crtc)
6262 {
6263         const struct intel_crtc_state *crtc_state =
6264                 intel_atomic_get_new_crtc_state(state, crtc);
6265         const struct drm_connector_state *conn_state;
6266         struct drm_connector *conn;
6267         int i;
6268
6269         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6270                 struct intel_encoder *encoder =
6271                         to_intel_encoder(conn_state->best_encoder);
6272
6273                 if (conn_state->crtc != &crtc->base)
6274                         continue;
6275
6276                 if (encoder->pre_pll_enable)
6277                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6278         }
6279 }
6280
6281 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6282                                       struct intel_crtc *crtc)
6283 {
6284         const struct intel_crtc_state *crtc_state =
6285                 intel_atomic_get_new_crtc_state(state, crtc);
6286         const struct drm_connector_state *conn_state;
6287         struct drm_connector *conn;
6288         int i;
6289
6290         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6291                 struct intel_encoder *encoder =
6292                         to_intel_encoder(conn_state->best_encoder);
6293
6294                 if (conn_state->crtc != &crtc->base)
6295                         continue;
6296
6297                 if (encoder->pre_enable)
6298                         encoder->pre_enable(encoder, crtc_state, conn_state);
6299         }
6300 }
6301
6302 static void intel_encoders_enable(struct intel_atomic_state *state,
6303                                   struct intel_crtc *crtc)
6304 {
6305         const struct intel_crtc_state *crtc_state =
6306                 intel_atomic_get_new_crtc_state(state, crtc);
6307         const struct drm_connector_state *conn_state;
6308         struct drm_connector *conn;
6309         int i;
6310
6311         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6312                 struct intel_encoder *encoder =
6313                         to_intel_encoder(conn_state->best_encoder);
6314
6315                 if (conn_state->crtc != &crtc->base)
6316                         continue;
6317
6318                 if (encoder->enable)
6319                         encoder->enable(encoder, crtc_state, conn_state);
6320                 intel_opregion_notify_encoder(encoder, true);
6321         }
6322 }
6323
6324 static void intel_encoders_disable(struct intel_atomic_state *state,
6325                                    struct intel_crtc *crtc)
6326 {
6327         const struct intel_crtc_state *old_crtc_state =
6328                 intel_atomic_get_old_crtc_state(state, crtc);
6329         const struct drm_connector_state *old_conn_state;
6330         struct drm_connector *conn;
6331         int i;
6332
6333         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6334                 struct intel_encoder *encoder =
6335                         to_intel_encoder(old_conn_state->best_encoder);
6336
6337                 if (old_conn_state->crtc != &crtc->base)
6338                         continue;
6339
6340                 intel_opregion_notify_encoder(encoder, false);
6341                 if (encoder->disable)
6342                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6343         }
6344 }
6345
6346 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6347                                         struct intel_crtc *crtc)
6348 {
6349         const struct intel_crtc_state *old_crtc_state =
6350                 intel_atomic_get_old_crtc_state(state, crtc);
6351         const struct drm_connector_state *old_conn_state;
6352         struct drm_connector *conn;
6353         int i;
6354
6355         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6356                 struct intel_encoder *encoder =
6357                         to_intel_encoder(old_conn_state->best_encoder);
6358
6359                 if (old_conn_state->crtc != &crtc->base)
6360                         continue;
6361
6362                 if (encoder->post_disable)
6363                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6364         }
6365 }
6366
6367 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6368                                             struct intel_crtc *crtc)
6369 {
6370         const struct intel_crtc_state *old_crtc_state =
6371                 intel_atomic_get_old_crtc_state(state, crtc);
6372         const struct drm_connector_state *old_conn_state;
6373         struct drm_connector *conn;
6374         int i;
6375
6376         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6377                 struct intel_encoder *encoder =
6378                         to_intel_encoder(old_conn_state->best_encoder);
6379
6380                 if (old_conn_state->crtc != &crtc->base)
6381                         continue;
6382
6383                 if (encoder->post_pll_disable)
6384                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6385         }
6386 }
6387
6388 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6389                                        struct intel_crtc *crtc)
6390 {
6391         const struct intel_crtc_state *crtc_state =
6392                 intel_atomic_get_new_crtc_state(state, crtc);
6393         const struct drm_connector_state *conn_state;
6394         struct drm_connector *conn;
6395         int i;
6396
6397         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6398                 struct intel_encoder *encoder =
6399                         to_intel_encoder(conn_state->best_encoder);
6400
6401                 if (conn_state->crtc != &crtc->base)
6402                         continue;
6403
6404                 if (encoder->update_pipe)
6405                         encoder->update_pipe(encoder, crtc_state, conn_state);
6406         }
6407 }
6408
6409 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6410 {
6411         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6412         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6413
6414         plane->disable_plane(plane, crtc_state);
6415 }
6416
6417 static void ironlake_crtc_enable(struct intel_atomic_state *state,
6418                                  struct intel_crtc *crtc)
6419 {
6420         const struct intel_crtc_state *new_crtc_state =
6421                 intel_atomic_get_new_crtc_state(state, crtc);
6422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6423         enum pipe pipe = crtc->pipe;
6424
6425         if (WARN_ON(crtc->active))
6426                 return;
6427
6428         /*
6429          * Sometimes spurious CPU pipe underruns happen during FDI
6430          * training, at least with VGA+HDMI cloning. Suppress them.
6431          *
6432          * On ILK we get an occasional spurious CPU pipe underruns
6433          * between eDP port A enable and vdd enable. Also PCH port
6434          * enable seems to result in the occasional CPU pipe underrun.
6435          *
6436          * Spurious PCH underruns also occur during PCH enabling.
6437          */
6438         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6439         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6440
6441         if (new_crtc_state->has_pch_encoder)
6442                 intel_prepare_shared_dpll(new_crtc_state);
6443
6444         if (intel_crtc_has_dp_encoder(new_crtc_state))
6445                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6446
6447         intel_set_pipe_timings(new_crtc_state);
6448         intel_set_pipe_src_size(new_crtc_state);
6449
6450         if (new_crtc_state->has_pch_encoder)
6451                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6452                                              &new_crtc_state->fdi_m_n, NULL);
6453
6454         ironlake_set_pipeconf(new_crtc_state);
6455
6456         crtc->active = true;
6457
6458         intel_encoders_pre_enable(state, crtc);
6459
6460         if (new_crtc_state->has_pch_encoder) {
6461                 /* Note: FDI PLL enabling _must_ be done before we enable the
6462                  * cpu pipes, hence this is separate from all the other fdi/pch
6463                  * enabling. */
6464                 ironlake_fdi_pll_enable(new_crtc_state);
6465         } else {
6466                 assert_fdi_tx_disabled(dev_priv, pipe);
6467                 assert_fdi_rx_disabled(dev_priv, pipe);
6468         }
6469
6470         ironlake_pfit_enable(new_crtc_state);
6471
6472         /*
6473          * On ILK+ LUT must be loaded before the pipe is running but with
6474          * clocks enabled
6475          */
6476         intel_color_load_luts(new_crtc_state);
6477         intel_color_commit(new_crtc_state);
6478         /* update DSPCNTR to configure gamma for pipe bottom color */
6479         intel_disable_primary_plane(new_crtc_state);
6480
6481         if (dev_priv->display.initial_watermarks)
6482                 dev_priv->display.initial_watermarks(state, crtc);
6483         intel_enable_pipe(new_crtc_state);
6484
6485         if (new_crtc_state->has_pch_encoder)
6486                 ironlake_pch_enable(state, new_crtc_state);
6487
6488         intel_crtc_vblank_on(new_crtc_state);
6489
6490         intel_encoders_enable(state, crtc);
6491
6492         if (HAS_PCH_CPT(dev_priv))
6493                 cpt_verify_modeset(dev_priv, pipe);
6494
6495         /*
6496          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6497          * And a second vblank wait is needed at least on ILK with
6498          * some interlaced HDMI modes. Let's do the double wait always
6499          * in case there are more corner cases we don't know about.
6500          */
6501         if (new_crtc_state->has_pch_encoder) {
6502                 intel_wait_for_vblank(dev_priv, pipe);
6503                 intel_wait_for_vblank(dev_priv, pipe);
6504         }
6505         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6506         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6507 }
6508
6509 /* IPS only exists on ULT machines and is tied to pipe A. */
6510 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6511 {
6512         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6513 }
6514
6515 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6516                                             enum pipe pipe, bool apply)
6517 {
6518         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6519         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6520
6521         if (apply)
6522                 val |= mask;
6523         else
6524                 val &= ~mask;
6525
6526         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6527 }
6528
6529 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6530 {
6531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6532         enum pipe pipe = crtc->pipe;
6533         u32 val;
6534
6535         val = MBUS_DBOX_A_CREDIT(2);
6536
6537         if (INTEL_GEN(dev_priv) >= 12) {
6538                 val |= MBUS_DBOX_BW_CREDIT(2);
6539                 val |= MBUS_DBOX_B_CREDIT(12);
6540         } else {
6541                 val |= MBUS_DBOX_BW_CREDIT(1);
6542                 val |= MBUS_DBOX_B_CREDIT(8);
6543         }
6544
6545         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6546 }
6547
6548 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6549 {
6550         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6551         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6552         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6553         u32 val;
6554
6555         val = I915_READ(reg);
6556         val &= ~HSW_FRAME_START_DELAY_MASK;
6557         val |= HSW_FRAME_START_DELAY(0);
6558         I915_WRITE(reg, val);
6559 }
6560
6561 static void haswell_crtc_enable(struct intel_atomic_state *state,
6562                                 struct intel_crtc *crtc)
6563 {
6564         const struct intel_crtc_state *new_crtc_state =
6565                 intel_atomic_get_new_crtc_state(state, crtc);
6566         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6567         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
6568         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
6569         bool psl_clkgate_wa;
6570
6571         if (WARN_ON(crtc->active))
6572                 return;
6573
6574         intel_encoders_pre_pll_enable(state, crtc);
6575
6576         if (new_crtc_state->shared_dpll)
6577                 intel_enable_shared_dpll(new_crtc_state);
6578
6579         intel_encoders_pre_enable(state, crtc);
6580
6581         if (intel_crtc_has_dp_encoder(new_crtc_state))
6582                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6583
6584         if (!transcoder_is_dsi(cpu_transcoder))
6585                 intel_set_pipe_timings(new_crtc_state);
6586
6587         if (INTEL_GEN(dev_priv) >= 11)
6588                 icl_enable_trans_port_sync(new_crtc_state);
6589
6590         intel_set_pipe_src_size(new_crtc_state);
6591
6592         if (cpu_transcoder != TRANSCODER_EDP &&
6593             !transcoder_is_dsi(cpu_transcoder))
6594                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6595                            new_crtc_state->pixel_multiplier - 1);
6596
6597         if (new_crtc_state->has_pch_encoder)
6598                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6599                                              &new_crtc_state->fdi_m_n, NULL);
6600
6601         if (!transcoder_is_dsi(cpu_transcoder)) {
6602                 hsw_set_frame_start_delay(new_crtc_state);
6603                 haswell_set_pipeconf(new_crtc_state);
6604         }
6605
6606         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6607                 bdw_set_pipemisc(new_crtc_state);
6608
6609         crtc->active = true;
6610
6611         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6612         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6613                 new_crtc_state->pch_pfit.enabled;
6614         if (psl_clkgate_wa)
6615                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6616
6617         if (INTEL_GEN(dev_priv) >= 9)
6618                 skylake_pfit_enable(new_crtc_state);
6619         else
6620                 ironlake_pfit_enable(new_crtc_state);
6621
6622         /*
6623          * On ILK+ LUT must be loaded before the pipe is running but with
6624          * clocks enabled
6625          */
6626         intel_color_load_luts(new_crtc_state);
6627         intel_color_commit(new_crtc_state);
6628         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6629         if (INTEL_GEN(dev_priv) < 9)
6630                 intel_disable_primary_plane(new_crtc_state);
6631
6632         if (INTEL_GEN(dev_priv) >= 11)
6633                 icl_set_pipe_chicken(crtc);
6634
6635         if (!transcoder_is_dsi(cpu_transcoder))
6636                 intel_ddi_enable_transcoder_func(new_crtc_state);
6637
6638         if (dev_priv->display.initial_watermarks)
6639                 dev_priv->display.initial_watermarks(state, crtc);
6640
6641         if (INTEL_GEN(dev_priv) >= 11)
6642                 icl_pipe_mbus_enable(crtc);
6643
6644         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6645         if (!transcoder_is_dsi(cpu_transcoder))
6646                 intel_enable_pipe(new_crtc_state);
6647
6648         if (new_crtc_state->has_pch_encoder)
6649                 lpt_pch_enable(state, new_crtc_state);
6650
6651         intel_crtc_vblank_on(new_crtc_state);
6652
6653         intel_encoders_enable(state, crtc);
6654
6655         if (psl_clkgate_wa) {
6656                 intel_wait_for_vblank(dev_priv, pipe);
6657                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6658         }
6659
6660         /* If we change the relative order between pipe/planes enabling, we need
6661          * to change the workaround. */
6662         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
6663         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6664                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6665                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6666         }
6667 }
6668
6669 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6670 {
6671         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6672         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6673         enum pipe pipe = crtc->pipe;
6674
6675         /* To avoid upsetting the power well on haswell only disable the pfit if
6676          * it's in use. The hw state code will make sure we get this right. */
6677         if (old_crtc_state->pch_pfit.enabled) {
6678                 I915_WRITE(PF_CTL(pipe), 0);
6679                 I915_WRITE(PF_WIN_POS(pipe), 0);
6680                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6681         }
6682 }
6683
6684 static void ironlake_crtc_disable(struct intel_atomic_state *state,
6685                                   struct intel_crtc *crtc)
6686 {
6687         const struct intel_crtc_state *old_crtc_state =
6688                 intel_atomic_get_old_crtc_state(state, crtc);
6689         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6690         enum pipe pipe = crtc->pipe;
6691
6692         /*
6693          * Sometimes spurious CPU pipe underruns happen when the
6694          * pipe is already disabled, but FDI RX/TX is still enabled.
6695          * Happens at least with VGA+HDMI cloning. Suppress them.
6696          */
6697         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6698         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6699
6700         intel_encoders_disable(state, crtc);
6701
6702         intel_crtc_vblank_off(old_crtc_state);
6703
6704         intel_disable_pipe(old_crtc_state);
6705
6706         ironlake_pfit_disable(old_crtc_state);
6707
6708         if (old_crtc_state->has_pch_encoder)
6709                 ironlake_fdi_disable(crtc);
6710
6711         intel_encoders_post_disable(state, crtc);
6712
6713         if (old_crtc_state->has_pch_encoder) {
6714                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6715
6716                 if (HAS_PCH_CPT(dev_priv)) {
6717                         i915_reg_t reg;
6718                         u32 temp;
6719
6720                         /* disable TRANS_DP_CTL */
6721                         reg = TRANS_DP_CTL(pipe);
6722                         temp = I915_READ(reg);
6723                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6724                                   TRANS_DP_PORT_SEL_MASK);
6725                         temp |= TRANS_DP_PORT_SEL_NONE;
6726                         I915_WRITE(reg, temp);
6727
6728                         /* disable DPLL_SEL */
6729                         temp = I915_READ(PCH_DPLL_SEL);
6730                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6731                         I915_WRITE(PCH_DPLL_SEL, temp);
6732                 }
6733
6734                 ironlake_fdi_pll_disable(crtc);
6735         }
6736
6737         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6738         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6739 }
6740
6741 static void haswell_crtc_disable(struct intel_atomic_state *state,
6742                                  struct intel_crtc *crtc)
6743 {
6744         const struct intel_crtc_state *old_crtc_state =
6745                 intel_atomic_get_old_crtc_state(state, crtc);
6746         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6747         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6748
6749         intel_encoders_disable(state, crtc);
6750
6751         intel_crtc_vblank_off(old_crtc_state);
6752
6753         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6754         if (!transcoder_is_dsi(cpu_transcoder))
6755                 intel_disable_pipe(old_crtc_state);
6756
6757         if (INTEL_GEN(dev_priv) >= 11)
6758                 icl_disable_transcoder_port_sync(old_crtc_state);
6759
6760         if (!transcoder_is_dsi(cpu_transcoder))
6761                 intel_ddi_disable_transcoder_func(old_crtc_state);
6762
6763         intel_dsc_disable(old_crtc_state);
6764
6765         if (INTEL_GEN(dev_priv) >= 9)
6766                 skylake_scaler_disable(old_crtc_state);
6767         else
6768                 ironlake_pfit_disable(old_crtc_state);
6769
6770         intel_encoders_post_disable(state, crtc);
6771 }
6772
6773 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6774 {
6775         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6776         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6777
6778         if (!crtc_state->gmch_pfit.control)
6779                 return;
6780
6781         /*
6782          * The panel fitter should only be adjusted whilst the pipe is disabled,
6783          * according to register description and PRM.
6784          */
6785         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6786         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
6787
6788         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6789         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6790
6791         /* Border color in case we don't scale up to the full screen. Black by
6792          * default, change to something else for debugging. */
6793         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6794 }
6795
6796 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6797 {
6798         if (phy == PHY_NONE)
6799                 return false;
6800
6801         if (IS_ELKHARTLAKE(dev_priv))
6802                 return phy <= PHY_C;
6803
6804         if (INTEL_GEN(dev_priv) >= 11)
6805                 return phy <= PHY_B;
6806
6807         return false;
6808 }
6809
6810 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6811 {
6812         if (INTEL_GEN(dev_priv) >= 12)
6813                 return phy >= PHY_D && phy <= PHY_I;
6814
6815         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6816                 return phy >= PHY_C && phy <= PHY_F;
6817
6818         return false;
6819 }
6820
6821 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6822 {
6823         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6824                 return PHY_A;
6825
6826         return (enum phy)port;
6827 }
6828
6829 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6830 {
6831         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6832                 return PORT_TC_NONE;
6833
6834         if (INTEL_GEN(dev_priv) >= 12)
6835                 return port - PORT_D;
6836
6837         return port - PORT_C;
6838 }
6839
6840 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6841 {
6842         switch (port) {
6843         case PORT_A:
6844                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6845         case PORT_B:
6846                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6847         case PORT_C:
6848                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6849         case PORT_D:
6850                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6851         case PORT_E:
6852                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6853         case PORT_F:
6854                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6855         case PORT_G:
6856                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6857         default:
6858                 MISSING_CASE(port);
6859                 return POWER_DOMAIN_PORT_OTHER;
6860         }
6861 }
6862
6863 enum intel_display_power_domain
6864 intel_aux_power_domain(struct intel_digital_port *dig_port)
6865 {
6866         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6867         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6868
6869         if (intel_phy_is_tc(dev_priv, phy) &&
6870             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6871                 switch (dig_port->aux_ch) {
6872                 case AUX_CH_C:
6873                         return POWER_DOMAIN_AUX_C_TBT;
6874                 case AUX_CH_D:
6875                         return POWER_DOMAIN_AUX_D_TBT;
6876                 case AUX_CH_E:
6877                         return POWER_DOMAIN_AUX_E_TBT;
6878                 case AUX_CH_F:
6879                         return POWER_DOMAIN_AUX_F_TBT;
6880                 case AUX_CH_G:
6881                         return POWER_DOMAIN_AUX_G_TBT;
6882                 default:
6883                         MISSING_CASE(dig_port->aux_ch);
6884                         return POWER_DOMAIN_AUX_C_TBT;
6885                 }
6886         }
6887
6888         switch (dig_port->aux_ch) {
6889         case AUX_CH_A:
6890                 return POWER_DOMAIN_AUX_A;
6891         case AUX_CH_B:
6892                 return POWER_DOMAIN_AUX_B;
6893         case AUX_CH_C:
6894                 return POWER_DOMAIN_AUX_C;
6895         case AUX_CH_D:
6896                 return POWER_DOMAIN_AUX_D;
6897         case AUX_CH_E:
6898                 return POWER_DOMAIN_AUX_E;
6899         case AUX_CH_F:
6900                 return POWER_DOMAIN_AUX_F;
6901         case AUX_CH_G:
6902                 return POWER_DOMAIN_AUX_G;
6903         default:
6904                 MISSING_CASE(dig_port->aux_ch);
6905                 return POWER_DOMAIN_AUX_A;
6906         }
6907 }
6908
6909 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6910 {
6911         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6912         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6913         struct drm_encoder *encoder;
6914         enum pipe pipe = crtc->pipe;
6915         u64 mask;
6916         enum transcoder transcoder = crtc_state->cpu_transcoder;
6917
6918         if (!crtc_state->hw.active)
6919                 return 0;
6920
6921         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6922         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6923         if (crtc_state->pch_pfit.enabled ||
6924             crtc_state->pch_pfit.force_thru)
6925                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6926
6927         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6928                                   crtc_state->uapi.encoder_mask) {
6929                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6930
6931                 mask |= BIT_ULL(intel_encoder->power_domain);
6932         }
6933
6934         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6935                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6936
6937         if (crtc_state->shared_dpll)
6938                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6939
6940         return mask;
6941 }
6942
6943 static u64
6944 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6945 {
6946         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6947         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6948         enum intel_display_power_domain domain;
6949         u64 domains, new_domains, old_domains;
6950
6951         old_domains = crtc->enabled_power_domains;
6952         crtc->enabled_power_domains = new_domains =
6953                 get_crtc_power_domains(crtc_state);
6954
6955         domains = new_domains & ~old_domains;
6956
6957         for_each_power_domain(domain, domains)
6958                 intel_display_power_get(dev_priv, domain);
6959
6960         return old_domains & ~new_domains;
6961 }
6962
6963 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6964                                       u64 domains)
6965 {
6966         enum intel_display_power_domain domain;
6967
6968         for_each_power_domain(domain, domains)
6969                 intel_display_power_put_unchecked(dev_priv, domain);
6970 }
6971
6972 static void valleyview_crtc_enable(struct intel_atomic_state *state,
6973                                    struct intel_crtc *crtc)
6974 {
6975         const struct intel_crtc_state *new_crtc_state =
6976                 intel_atomic_get_new_crtc_state(state, crtc);
6977         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6978         enum pipe pipe = crtc->pipe;
6979
6980         if (WARN_ON(crtc->active))
6981                 return;
6982
6983         if (intel_crtc_has_dp_encoder(new_crtc_state))
6984                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6985
6986         intel_set_pipe_timings(new_crtc_state);
6987         intel_set_pipe_src_size(new_crtc_state);
6988
6989         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6990                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6991                 I915_WRITE(CHV_CANVAS(pipe), 0);
6992         }
6993
6994         i9xx_set_pipeconf(new_crtc_state);
6995
6996         crtc->active = true;
6997
6998         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6999
7000         intel_encoders_pre_pll_enable(state, crtc);
7001
7002         if (IS_CHERRYVIEW(dev_priv)) {
7003                 chv_prepare_pll(crtc, new_crtc_state);
7004                 chv_enable_pll(crtc, new_crtc_state);
7005         } else {
7006                 vlv_prepare_pll(crtc, new_crtc_state);
7007                 vlv_enable_pll(crtc, new_crtc_state);
7008         }
7009
7010         intel_encoders_pre_enable(state, crtc);
7011
7012         i9xx_pfit_enable(new_crtc_state);
7013
7014         intel_color_load_luts(new_crtc_state);
7015         intel_color_commit(new_crtc_state);
7016         /* update DSPCNTR to configure gamma for pipe bottom color */
7017         intel_disable_primary_plane(new_crtc_state);
7018
7019         dev_priv->display.initial_watermarks(state, crtc);
7020         intel_enable_pipe(new_crtc_state);
7021
7022         intel_crtc_vblank_on(new_crtc_state);
7023
7024         intel_encoders_enable(state, crtc);
7025 }
7026
7027 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7028 {
7029         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7030         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7031
7032         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7033         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7034 }
7035
7036 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7037                              struct intel_crtc *crtc)
7038 {
7039         const struct intel_crtc_state *new_crtc_state =
7040                 intel_atomic_get_new_crtc_state(state, crtc);
7041         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7042         enum pipe pipe = crtc->pipe;
7043
7044         if (WARN_ON(crtc->active))
7045                 return;
7046
7047         i9xx_set_pll_dividers(new_crtc_state);
7048
7049         if (intel_crtc_has_dp_encoder(new_crtc_state))
7050                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7051
7052         intel_set_pipe_timings(new_crtc_state);
7053         intel_set_pipe_src_size(new_crtc_state);
7054
7055         i9xx_set_pipeconf(new_crtc_state);
7056
7057         crtc->active = true;
7058
7059         if (!IS_GEN(dev_priv, 2))
7060                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7061
7062         intel_encoders_pre_enable(state, crtc);
7063
7064         i9xx_enable_pll(crtc, new_crtc_state);
7065
7066         i9xx_pfit_enable(new_crtc_state);
7067
7068         intel_color_load_luts(new_crtc_state);
7069         intel_color_commit(new_crtc_state);
7070         /* update DSPCNTR to configure gamma for pipe bottom color */
7071         intel_disable_primary_plane(new_crtc_state);
7072
7073         if (dev_priv->display.initial_watermarks)
7074                 dev_priv->display.initial_watermarks(state, crtc);
7075         else
7076                 intel_update_watermarks(crtc);
7077         intel_enable_pipe(new_crtc_state);
7078
7079         intel_crtc_vblank_on(new_crtc_state);
7080
7081         intel_encoders_enable(state, crtc);
7082 }
7083
7084 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7085 {
7086         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7088
7089         if (!old_crtc_state->gmch_pfit.control)
7090                 return;
7091
7092         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7093
7094         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7095                       I915_READ(PFIT_CONTROL));
7096         I915_WRITE(PFIT_CONTROL, 0);
7097 }
7098
7099 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7100                               struct intel_crtc *crtc)
7101 {
7102         struct intel_crtc_state *old_crtc_state =
7103                 intel_atomic_get_old_crtc_state(state, crtc);
7104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7105         enum pipe pipe = crtc->pipe;
7106
7107         /*
7108          * On gen2 planes are double buffered but the pipe isn't, so we must
7109          * wait for planes to fully turn off before disabling the pipe.
7110          */
7111         if (IS_GEN(dev_priv, 2))
7112                 intel_wait_for_vblank(dev_priv, pipe);
7113
7114         intel_encoders_disable(state, crtc);
7115
7116         intel_crtc_vblank_off(old_crtc_state);
7117
7118         intel_disable_pipe(old_crtc_state);
7119
7120         i9xx_pfit_disable(old_crtc_state);
7121
7122         intel_encoders_post_disable(state, crtc);
7123
7124         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7125                 if (IS_CHERRYVIEW(dev_priv))
7126                         chv_disable_pll(dev_priv, pipe);
7127                 else if (IS_VALLEYVIEW(dev_priv))
7128                         vlv_disable_pll(dev_priv, pipe);
7129                 else
7130                         i9xx_disable_pll(old_crtc_state);
7131         }
7132
7133         intel_encoders_post_pll_disable(state, crtc);
7134
7135         if (!IS_GEN(dev_priv, 2))
7136                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7137
7138         if (!dev_priv->display.initial_watermarks)
7139                 intel_update_watermarks(crtc);
7140
7141         /* clock the pipe down to 640x480@60 to potentially save power */
7142         if (IS_I830(dev_priv))
7143                 i830_enable_pipe(dev_priv, pipe);
7144 }
7145
7146 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7147                                         struct drm_modeset_acquire_ctx *ctx)
7148 {
7149         struct intel_encoder *encoder;
7150         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7151         struct intel_bw_state *bw_state =
7152                 to_intel_bw_state(dev_priv->bw_obj.state);
7153         struct intel_crtc_state *crtc_state =
7154                 to_intel_crtc_state(crtc->base.state);
7155         enum intel_display_power_domain domain;
7156         struct intel_plane *plane;
7157         struct drm_atomic_state *state;
7158         struct intel_crtc_state *temp_crtc_state;
7159         enum pipe pipe = crtc->pipe;
7160         u64 domains;
7161         int ret;
7162
7163         if (!crtc_state->hw.active)
7164                 return;
7165
7166         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7167                 const struct intel_plane_state *plane_state =
7168                         to_intel_plane_state(plane->base.state);
7169
7170                 if (plane_state->uapi.visible)
7171                         intel_plane_disable_noatomic(crtc, plane);
7172         }
7173
7174         state = drm_atomic_state_alloc(&dev_priv->drm);
7175         if (!state) {
7176                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7177                               crtc->base.base.id, crtc->base.name);
7178                 return;
7179         }
7180
7181         state->acquire_ctx = ctx;
7182
7183         /* Everything's already locked, -EDEADLK can't happen. */
7184         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7185         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7186
7187         WARN_ON(IS_ERR(temp_crtc_state) || ret);
7188
7189         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7190
7191         drm_atomic_state_put(state);
7192
7193         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7194                       crtc->base.base.id, crtc->base.name);
7195
7196         crtc->active = false;
7197         crtc->base.enabled = false;
7198
7199         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7200         crtc_state->uapi.active = false;
7201         crtc_state->uapi.connector_mask = 0;
7202         crtc_state->uapi.encoder_mask = 0;
7203         intel_crtc_free_hw_state(crtc_state);
7204         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7205
7206         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7207                 encoder->base.crtc = NULL;
7208
7209         intel_fbc_disable(crtc);
7210         intel_update_watermarks(crtc);
7211         intel_disable_shared_dpll(crtc_state);
7212
7213         domains = crtc->enabled_power_domains;
7214         for_each_power_domain(domain, domains)
7215                 intel_display_power_put_unchecked(dev_priv, domain);
7216         crtc->enabled_power_domains = 0;
7217
7218         dev_priv->active_pipes &= ~BIT(pipe);
7219         dev_priv->min_cdclk[pipe] = 0;
7220         dev_priv->min_voltage_level[pipe] = 0;
7221
7222         bw_state->data_rate[pipe] = 0;
7223         bw_state->num_active_planes[pipe] = 0;
7224 }
7225
7226 /*
7227  * turn all crtc's off, but do not adjust state
7228  * This has to be paired with a call to intel_modeset_setup_hw_state.
7229  */
7230 int intel_display_suspend(struct drm_device *dev)
7231 {
7232         struct drm_i915_private *dev_priv = to_i915(dev);
7233         struct drm_atomic_state *state;
7234         int ret;
7235
7236         state = drm_atomic_helper_suspend(dev);
7237         ret = PTR_ERR_OR_ZERO(state);
7238         if (ret)
7239                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7240         else
7241                 dev_priv->modeset_restore_state = state;
7242         return ret;
7243 }
7244
7245 void intel_encoder_destroy(struct drm_encoder *encoder)
7246 {
7247         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7248
7249         drm_encoder_cleanup(encoder);
7250         kfree(intel_encoder);
7251 }
7252
7253 /* Cross check the actual hw state with our own modeset state tracking (and it's
7254  * internal consistency). */
7255 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7256                                          struct drm_connector_state *conn_state)
7257 {
7258         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7259
7260         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7261                       connector->base.base.id,
7262                       connector->base.name);
7263
7264         if (connector->get_hw_state(connector)) {
7265                 struct intel_encoder *encoder = connector->encoder;
7266
7267                 I915_STATE_WARN(!crtc_state,
7268                          "connector enabled without attached crtc\n");
7269
7270                 if (!crtc_state)
7271                         return;
7272
7273                 I915_STATE_WARN(!crtc_state->hw.active,
7274                                 "connector is active, but attached crtc isn't\n");
7275
7276                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7277                         return;
7278
7279                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7280                         "atomic encoder doesn't match attached encoder\n");
7281
7282                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7283                         "attached encoder crtc differs from connector crtc\n");
7284         } else {
7285                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7286                                 "attached crtc is active, but connector isn't\n");
7287                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7288                         "best encoder set without crtc!\n");
7289         }
7290 }
7291
7292 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7293 {
7294         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7295                 return crtc_state->fdi_lanes;
7296
7297         return 0;
7298 }
7299
7300 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7301                                      struct intel_crtc_state *pipe_config)
7302 {
7303         struct drm_i915_private *dev_priv = to_i915(dev);
7304         struct drm_atomic_state *state = pipe_config->uapi.state;
7305         struct intel_crtc *other_crtc;
7306         struct intel_crtc_state *other_crtc_state;
7307
7308         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7309                       pipe_name(pipe), pipe_config->fdi_lanes);
7310         if (pipe_config->fdi_lanes > 4) {
7311                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7312                               pipe_name(pipe), pipe_config->fdi_lanes);
7313                 return -EINVAL;
7314         }
7315
7316         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7317                 if (pipe_config->fdi_lanes > 2) {
7318                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7319                                       pipe_config->fdi_lanes);
7320                         return -EINVAL;
7321                 } else {
7322                         return 0;
7323                 }
7324         }
7325
7326         if (INTEL_NUM_PIPES(dev_priv) == 2)
7327                 return 0;
7328
7329         /* Ivybridge 3 pipe is really complicated */
7330         switch (pipe) {
7331         case PIPE_A:
7332                 return 0;
7333         case PIPE_B:
7334                 if (pipe_config->fdi_lanes <= 2)
7335                         return 0;
7336
7337                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7338                 other_crtc_state =
7339                         intel_atomic_get_crtc_state(state, other_crtc);
7340                 if (IS_ERR(other_crtc_state))
7341                         return PTR_ERR(other_crtc_state);
7342
7343                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7344                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7345                                       pipe_name(pipe), pipe_config->fdi_lanes);
7346                         return -EINVAL;
7347                 }
7348                 return 0;
7349         case PIPE_C:
7350                 if (pipe_config->fdi_lanes > 2) {
7351                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7352                                       pipe_name(pipe), pipe_config->fdi_lanes);
7353                         return -EINVAL;
7354                 }
7355
7356                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7357                 other_crtc_state =
7358                         intel_atomic_get_crtc_state(state, other_crtc);
7359                 if (IS_ERR(other_crtc_state))
7360                         return PTR_ERR(other_crtc_state);
7361
7362                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7363                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7364                         return -EINVAL;
7365                 }
7366                 return 0;
7367         default:
7368                 BUG();
7369         }
7370 }
7371
7372 #define RETRY 1
7373 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7374                                        struct intel_crtc_state *pipe_config)
7375 {
7376         struct drm_device *dev = intel_crtc->base.dev;
7377         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7378         int lane, link_bw, fdi_dotclock, ret;
7379         bool needs_recompute = false;
7380
7381 retry:
7382         /* FDI is a binary signal running at ~2.7GHz, encoding
7383          * each output octet as 10 bits. The actual frequency
7384          * is stored as a divider into a 100MHz clock, and the
7385          * mode pixel clock is stored in units of 1KHz.
7386          * Hence the bw of each lane in terms of the mode signal
7387          * is:
7388          */
7389         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7390
7391         fdi_dotclock = adjusted_mode->crtc_clock;
7392
7393         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7394                                            pipe_config->pipe_bpp);
7395
7396         pipe_config->fdi_lanes = lane;
7397
7398         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7399                                link_bw, &pipe_config->fdi_m_n, false, false);
7400
7401         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7402         if (ret == -EDEADLK)
7403                 return ret;
7404
7405         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7406                 pipe_config->pipe_bpp -= 2*3;
7407                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7408                               pipe_config->pipe_bpp);
7409                 needs_recompute = true;
7410                 pipe_config->bw_constrained = true;
7411
7412                 goto retry;
7413         }
7414
7415         if (needs_recompute)
7416                 return RETRY;
7417
7418         return ret;
7419 }
7420
7421 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7422 {
7423         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7424         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7425
7426         /* IPS only exists on ULT machines and is tied to pipe A. */
7427         if (!hsw_crtc_supports_ips(crtc))
7428                 return false;
7429
7430         if (!i915_modparams.enable_ips)
7431                 return false;
7432
7433         if (crtc_state->pipe_bpp > 24)
7434                 return false;
7435
7436         /*
7437          * We compare against max which means we must take
7438          * the increased cdclk requirement into account when
7439          * calculating the new cdclk.
7440          *
7441          * Should measure whether using a lower cdclk w/o IPS
7442          */
7443         if (IS_BROADWELL(dev_priv) &&
7444             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7445                 return false;
7446
7447         return true;
7448 }
7449
7450 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7451 {
7452         struct drm_i915_private *dev_priv =
7453                 to_i915(crtc_state->uapi.crtc->dev);
7454         struct intel_atomic_state *intel_state =
7455                 to_intel_atomic_state(crtc_state->uapi.state);
7456
7457         if (!hsw_crtc_state_ips_capable(crtc_state))
7458                 return false;
7459
7460         /*
7461          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7462          * enabled and disabled dynamically based on package C states,
7463          * user space can't make reliable use of the CRCs, so let's just
7464          * completely disable it.
7465          */
7466         if (crtc_state->crc_enabled)
7467                 return false;
7468
7469         /* IPS should be fine as long as at least one plane is enabled. */
7470         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7471                 return false;
7472
7473         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7474         if (IS_BROADWELL(dev_priv) &&
7475             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7476                 return false;
7477
7478         return true;
7479 }
7480
7481 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7482 {
7483         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7484
7485         /* GDG double wide on either pipe, otherwise pipe A only */
7486         return INTEL_GEN(dev_priv) < 4 &&
7487                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7488 }
7489
7490 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7491 {
7492         u32 pixel_rate;
7493
7494         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7495
7496         /*
7497          * We only use IF-ID interlacing. If we ever use
7498          * PF-ID we'll need to adjust the pixel_rate here.
7499          */
7500
7501         if (pipe_config->pch_pfit.enabled) {
7502                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7503                 u32 pfit_size = pipe_config->pch_pfit.size;
7504
7505                 pipe_w = pipe_config->pipe_src_w;
7506                 pipe_h = pipe_config->pipe_src_h;
7507
7508                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7509                 pfit_h = pfit_size & 0xFFFF;
7510                 if (pipe_w < pfit_w)
7511                         pipe_w = pfit_w;
7512                 if (pipe_h < pfit_h)
7513                         pipe_h = pfit_h;
7514
7515                 if (WARN_ON(!pfit_w || !pfit_h))
7516                         return pixel_rate;
7517
7518                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7519                                      pfit_w * pfit_h);
7520         }
7521
7522         return pixel_rate;
7523 }
7524
7525 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7526 {
7527         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7528
7529         if (HAS_GMCH(dev_priv))
7530                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7531                 crtc_state->pixel_rate =
7532                         crtc_state->hw.adjusted_mode.crtc_clock;
7533         else
7534                 crtc_state->pixel_rate =
7535                         ilk_pipe_pixel_rate(crtc_state);
7536 }
7537
7538 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7539                                      struct intel_crtc_state *pipe_config)
7540 {
7541         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7542         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7543         int clock_limit = dev_priv->max_dotclk_freq;
7544
7545         if (INTEL_GEN(dev_priv) < 4) {
7546                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7547
7548                 /*
7549                  * Enable double wide mode when the dot clock
7550                  * is > 90% of the (display) core speed.
7551                  */
7552                 if (intel_crtc_supports_double_wide(crtc) &&
7553                     adjusted_mode->crtc_clock > clock_limit) {
7554                         clock_limit = dev_priv->max_dotclk_freq;
7555                         pipe_config->double_wide = true;
7556                 }
7557         }
7558
7559         if (adjusted_mode->crtc_clock > clock_limit) {
7560                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7561                               adjusted_mode->crtc_clock, clock_limit,
7562                               yesno(pipe_config->double_wide));
7563                 return -EINVAL;
7564         }
7565
7566         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7567              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7568              pipe_config->hw.ctm) {
7569                 /*
7570                  * There is only one pipe CSC unit per pipe, and we need that
7571                  * for output conversion from RGB->YCBCR. So if CTM is already
7572                  * applied we can't support YCBCR420 output.
7573                  */
7574                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7575                 return -EINVAL;
7576         }
7577
7578         /*
7579          * Pipe horizontal size must be even in:
7580          * - DVO ganged mode
7581          * - LVDS dual channel mode
7582          * - Double wide pipe
7583          */
7584         if (pipe_config->pipe_src_w & 1) {
7585                 if (pipe_config->double_wide) {
7586                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7587                         return -EINVAL;
7588                 }
7589
7590                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7591                     intel_is_dual_link_lvds(dev_priv)) {
7592                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7593                         return -EINVAL;
7594                 }
7595         }
7596
7597         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7598          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7599          */
7600         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7601                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7602                 return -EINVAL;
7603
7604         intel_crtc_compute_pixel_rate(pipe_config);
7605
7606         if (pipe_config->has_pch_encoder)
7607                 return ironlake_fdi_compute_config(crtc, pipe_config);
7608
7609         return 0;
7610 }
7611
7612 static void
7613 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7614 {
7615         while (*num > DATA_LINK_M_N_MASK ||
7616                *den > DATA_LINK_M_N_MASK) {
7617                 *num >>= 1;
7618                 *den >>= 1;
7619         }
7620 }
7621
7622 static void compute_m_n(unsigned int m, unsigned int n,
7623                         u32 *ret_m, u32 *ret_n,
7624                         bool constant_n)
7625 {
7626         /*
7627          * Several DP dongles in particular seem to be fussy about
7628          * too large link M/N values. Give N value as 0x8000 that
7629          * should be acceptable by specific devices. 0x8000 is the
7630          * specified fixed N value for asynchronous clock mode,
7631          * which the devices expect also in synchronous clock mode.
7632          */
7633         if (constant_n)
7634                 *ret_n = 0x8000;
7635         else
7636                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7637
7638         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7639         intel_reduce_m_n_ratio(ret_m, ret_n);
7640 }
7641
7642 void
7643 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7644                        int pixel_clock, int link_clock,
7645                        struct intel_link_m_n *m_n,
7646                        bool constant_n, bool fec_enable)
7647 {
7648         u32 data_clock = bits_per_pixel * pixel_clock;
7649
7650         if (fec_enable)
7651                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7652
7653         m_n->tu = 64;
7654         compute_m_n(data_clock,
7655                     link_clock * nlanes * 8,
7656                     &m_n->gmch_m, &m_n->gmch_n,
7657                     constant_n);
7658
7659         compute_m_n(pixel_clock, link_clock,
7660                     &m_n->link_m, &m_n->link_n,
7661                     constant_n);
7662 }
7663
7664 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7665 {
7666         /*
7667          * There may be no VBT; and if the BIOS enabled SSC we can
7668          * just keep using it to avoid unnecessary flicker.  Whereas if the
7669          * BIOS isn't using it, don't assume it will work even if the VBT
7670          * indicates as much.
7671          */
7672         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7673                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7674                         DREF_SSC1_ENABLE;
7675
7676                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7677                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7678                                       enableddisabled(bios_lvds_use_ssc),
7679                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7680                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7681                 }
7682         }
7683 }
7684
7685 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7686 {
7687         if (i915_modparams.panel_use_ssc >= 0)
7688                 return i915_modparams.panel_use_ssc != 0;
7689         return dev_priv->vbt.lvds_use_ssc
7690                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7691 }
7692
7693 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7694 {
7695         return (1 << dpll->n) << 16 | dpll->m2;
7696 }
7697
7698 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7699 {
7700         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7701 }
7702
7703 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7704                                      struct intel_crtc_state *crtc_state,
7705                                      struct dpll *reduced_clock)
7706 {
7707         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7708         u32 fp, fp2 = 0;
7709
7710         if (IS_PINEVIEW(dev_priv)) {
7711                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7712                 if (reduced_clock)
7713                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7714         } else {
7715                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7716                 if (reduced_clock)
7717                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7718         }
7719
7720         crtc_state->dpll_hw_state.fp0 = fp;
7721
7722         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7723             reduced_clock) {
7724                 crtc_state->dpll_hw_state.fp1 = fp2;
7725         } else {
7726                 crtc_state->dpll_hw_state.fp1 = fp;
7727         }
7728 }
7729
7730 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7731                 pipe)
7732 {
7733         u32 reg_val;
7734
7735         /*
7736          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7737          * and set it to a reasonable value instead.
7738          */
7739         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7740         reg_val &= 0xffffff00;
7741         reg_val |= 0x00000030;
7742         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7743
7744         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7745         reg_val &= 0x00ffffff;
7746         reg_val |= 0x8c000000;
7747         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7748
7749         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7750         reg_val &= 0xffffff00;
7751         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7752
7753         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7754         reg_val &= 0x00ffffff;
7755         reg_val |= 0xb0000000;
7756         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7757 }
7758
7759 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7760                                          const struct intel_link_m_n *m_n)
7761 {
7762         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7763         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7764         enum pipe pipe = crtc->pipe;
7765
7766         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7767         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7768         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7769         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7770 }
7771
7772 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7773                                  enum transcoder transcoder)
7774 {
7775         if (IS_HASWELL(dev_priv))
7776                 return transcoder == TRANSCODER_EDP;
7777
7778         /*
7779          * Strictly speaking some registers are available before
7780          * gen7, but we only support DRRS on gen7+
7781          */
7782         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7783 }
7784
7785 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7786                                          const struct intel_link_m_n *m_n,
7787                                          const struct intel_link_m_n *m2_n2)
7788 {
7789         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7790         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7791         enum pipe pipe = crtc->pipe;
7792         enum transcoder transcoder = crtc_state->cpu_transcoder;
7793
7794         if (INTEL_GEN(dev_priv) >= 5) {
7795                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7796                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7797                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7798                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7799                 /*
7800                  *  M2_N2 registers are set only if DRRS is supported
7801                  * (to make sure the registers are not unnecessarily accessed).
7802                  */
7803                 if (m2_n2 && crtc_state->has_drrs &&
7804                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7805                         I915_WRITE(PIPE_DATA_M2(transcoder),
7806                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7807                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7808                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7809                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7810                 }
7811         } else {
7812                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7813                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7814                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7815                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7816         }
7817 }
7818
7819 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7820 {
7821         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7822
7823         if (m_n == M1_N1) {
7824                 dp_m_n = &crtc_state->dp_m_n;
7825                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7826         } else if (m_n == M2_N2) {
7827
7828                 /*
7829                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7830                  * needs to be programmed into M1_N1.
7831                  */
7832                 dp_m_n = &crtc_state->dp_m2_n2;
7833         } else {
7834                 DRM_ERROR("Unsupported divider value\n");
7835                 return;
7836         }
7837
7838         if (crtc_state->has_pch_encoder)
7839                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7840         else
7841                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7842 }
7843
7844 static void vlv_compute_dpll(struct intel_crtc *crtc,
7845                              struct intel_crtc_state *pipe_config)
7846 {
7847         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7848                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7849         if (crtc->pipe != PIPE_A)
7850                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7851
7852         /* DPLL not used with DSI, but still need the rest set up */
7853         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7854                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7855                         DPLL_EXT_BUFFER_ENABLE_VLV;
7856
7857         pipe_config->dpll_hw_state.dpll_md =
7858                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7859 }
7860
7861 static void chv_compute_dpll(struct intel_crtc *crtc,
7862                              struct intel_crtc_state *pipe_config)
7863 {
7864         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7865                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7866         if (crtc->pipe != PIPE_A)
7867                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7868
7869         /* DPLL not used with DSI, but still need the rest set up */
7870         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7871                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7872
7873         pipe_config->dpll_hw_state.dpll_md =
7874                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7875 }
7876
7877 static void vlv_prepare_pll(struct intel_crtc *crtc,
7878                             const struct intel_crtc_state *pipe_config)
7879 {
7880         struct drm_device *dev = crtc->base.dev;
7881         struct drm_i915_private *dev_priv = to_i915(dev);
7882         enum pipe pipe = crtc->pipe;
7883         u32 mdiv;
7884         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7885         u32 coreclk, reg_val;
7886
7887         /* Enable Refclk */
7888         I915_WRITE(DPLL(pipe),
7889                    pipe_config->dpll_hw_state.dpll &
7890                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7891
7892         /* No need to actually set up the DPLL with DSI */
7893         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7894                 return;
7895
7896         vlv_dpio_get(dev_priv);
7897
7898         bestn = pipe_config->dpll.n;
7899         bestm1 = pipe_config->dpll.m1;
7900         bestm2 = pipe_config->dpll.m2;
7901         bestp1 = pipe_config->dpll.p1;
7902         bestp2 = pipe_config->dpll.p2;
7903
7904         /* See eDP HDMI DPIO driver vbios notes doc */
7905
7906         /* PLL B needs special handling */
7907         if (pipe == PIPE_B)
7908                 vlv_pllb_recal_opamp(dev_priv, pipe);
7909
7910         /* Set up Tx target for periodic Rcomp update */
7911         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7912
7913         /* Disable target IRef on PLL */
7914         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7915         reg_val &= 0x00ffffff;
7916         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7917
7918         /* Disable fast lock */
7919         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7920
7921         /* Set idtafcrecal before PLL is enabled */
7922         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7923         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7924         mdiv |= ((bestn << DPIO_N_SHIFT));
7925         mdiv |= (1 << DPIO_K_SHIFT);
7926
7927         /*
7928          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7929          * but we don't support that).
7930          * Note: don't use the DAC post divider as it seems unstable.
7931          */
7932         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7933         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7934
7935         mdiv |= DPIO_ENABLE_CALIBRATION;
7936         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7937
7938         /* Set HBR and RBR LPF coefficients */
7939         if (pipe_config->port_clock == 162000 ||
7940             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7941             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7942                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7943                                  0x009f0003);
7944         else
7945                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7946                                  0x00d0000f);
7947
7948         if (intel_crtc_has_dp_encoder(pipe_config)) {
7949                 /* Use SSC source */
7950                 if (pipe == PIPE_A)
7951                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7952                                          0x0df40000);
7953                 else
7954                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7955                                          0x0df70000);
7956         } else { /* HDMI or VGA */
7957                 /* Use bend source */
7958                 if (pipe == PIPE_A)
7959                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7960                                          0x0df70000);
7961                 else
7962                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7963                                          0x0df40000);
7964         }
7965
7966         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7967         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7968         if (intel_crtc_has_dp_encoder(pipe_config))
7969                 coreclk |= 0x01000000;
7970         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7971
7972         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7973
7974         vlv_dpio_put(dev_priv);
7975 }
7976
7977 static void chv_prepare_pll(struct intel_crtc *crtc,
7978                             const struct intel_crtc_state *pipe_config)
7979 {
7980         struct drm_device *dev = crtc->base.dev;
7981         struct drm_i915_private *dev_priv = to_i915(dev);
7982         enum pipe pipe = crtc->pipe;
7983         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7984         u32 loopfilter, tribuf_calcntr;
7985         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7986         u32 dpio_val;
7987         int vco;
7988
7989         /* Enable Refclk and SSC */
7990         I915_WRITE(DPLL(pipe),
7991                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7992
7993         /* No need to actually set up the DPLL with DSI */
7994         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7995                 return;
7996
7997         bestn = pipe_config->dpll.n;
7998         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7999         bestm1 = pipe_config->dpll.m1;
8000         bestm2 = pipe_config->dpll.m2 >> 22;
8001         bestp1 = pipe_config->dpll.p1;
8002         bestp2 = pipe_config->dpll.p2;
8003         vco = pipe_config->dpll.vco;
8004         dpio_val = 0;
8005         loopfilter = 0;
8006
8007         vlv_dpio_get(dev_priv);
8008
8009         /* p1 and p2 divider */
8010         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8011                         5 << DPIO_CHV_S1_DIV_SHIFT |
8012                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8013                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8014                         1 << DPIO_CHV_K_DIV_SHIFT);
8015
8016         /* Feedback post-divider - m2 */
8017         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8018
8019         /* Feedback refclk divider - n and m1 */
8020         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8021                         DPIO_CHV_M1_DIV_BY_2 |
8022                         1 << DPIO_CHV_N_DIV_SHIFT);
8023
8024         /* M2 fraction division */
8025         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8026
8027         /* M2 fraction division enable */
8028         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8029         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8030         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8031         if (bestm2_frac)
8032                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8033         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8034
8035         /* Program digital lock detect threshold */
8036         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8037         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8038                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8039         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8040         if (!bestm2_frac)
8041                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8042         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8043
8044         /* Loop filter */
8045         if (vco == 5400000) {
8046                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8047                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8048                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8049                 tribuf_calcntr = 0x9;
8050         } else if (vco <= 6200000) {
8051                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8052                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8053                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8054                 tribuf_calcntr = 0x9;
8055         } else if (vco <= 6480000) {
8056                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8057                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8058                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8059                 tribuf_calcntr = 0x8;
8060         } else {
8061                 /* Not supported. Apply the same limits as in the max case */
8062                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8063                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8064                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8065                 tribuf_calcntr = 0;
8066         }
8067         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8068
8069         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8070         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8071         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8072         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8073
8074         /* AFC Recal */
8075         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8076                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8077                         DPIO_AFC_RECAL);
8078
8079         vlv_dpio_put(dev_priv);
8080 }
8081
8082 /**
8083  * vlv_force_pll_on - forcibly enable just the PLL
8084  * @dev_priv: i915 private structure
8085  * @pipe: pipe PLL to enable
8086  * @dpll: PLL configuration
8087  *
8088  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8089  * in cases where we need the PLL enabled even when @pipe is not going to
8090  * be enabled.
8091  */
8092 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8093                      const struct dpll *dpll)
8094 {
8095         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8096         struct intel_crtc_state *pipe_config;
8097
8098         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8099         if (!pipe_config)
8100                 return -ENOMEM;
8101
8102         pipe_config->uapi.crtc = &crtc->base;
8103         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8104         pipe_config->pixel_multiplier = 1;
8105         pipe_config->dpll = *dpll;
8106
8107         if (IS_CHERRYVIEW(dev_priv)) {
8108                 chv_compute_dpll(crtc, pipe_config);
8109                 chv_prepare_pll(crtc, pipe_config);
8110                 chv_enable_pll(crtc, pipe_config);
8111         } else {
8112                 vlv_compute_dpll(crtc, pipe_config);
8113                 vlv_prepare_pll(crtc, pipe_config);
8114                 vlv_enable_pll(crtc, pipe_config);
8115         }
8116
8117         kfree(pipe_config);
8118
8119         return 0;
8120 }
8121
8122 /**
8123  * vlv_force_pll_off - forcibly disable just the PLL
8124  * @dev_priv: i915 private structure
8125  * @pipe: pipe PLL to disable
8126  *
8127  * Disable the PLL for @pipe. To be used in cases where we need
8128  * the PLL enabled even when @pipe is not going to be enabled.
8129  */
8130 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8131 {
8132         if (IS_CHERRYVIEW(dev_priv))
8133                 chv_disable_pll(dev_priv, pipe);
8134         else
8135                 vlv_disable_pll(dev_priv, pipe);
8136 }
8137
8138 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8139                               struct intel_crtc_state *crtc_state,
8140                               struct dpll *reduced_clock)
8141 {
8142         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8143         u32 dpll;
8144         struct dpll *clock = &crtc_state->dpll;
8145
8146         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8147
8148         dpll = DPLL_VGA_MODE_DIS;
8149
8150         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8151                 dpll |= DPLLB_MODE_LVDS;
8152         else
8153                 dpll |= DPLLB_MODE_DAC_SERIAL;
8154
8155         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8156             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8157                 dpll |= (crtc_state->pixel_multiplier - 1)
8158                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8159         }
8160
8161         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8162             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8163                 dpll |= DPLL_SDVO_HIGH_SPEED;
8164
8165         if (intel_crtc_has_dp_encoder(crtc_state))
8166                 dpll |= DPLL_SDVO_HIGH_SPEED;
8167
8168         /* compute bitmask from p1 value */
8169         if (IS_PINEVIEW(dev_priv))
8170                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8171         else {
8172                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8173                 if (IS_G4X(dev_priv) && reduced_clock)
8174                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8175         }
8176         switch (clock->p2) {
8177         case 5:
8178                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8179                 break;
8180         case 7:
8181                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8182                 break;
8183         case 10:
8184                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8185                 break;
8186         case 14:
8187                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8188                 break;
8189         }
8190         if (INTEL_GEN(dev_priv) >= 4)
8191                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8192
8193         if (crtc_state->sdvo_tv_clock)
8194                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8195         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8196                  intel_panel_use_ssc(dev_priv))
8197                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8198         else
8199                 dpll |= PLL_REF_INPUT_DREFCLK;
8200
8201         dpll |= DPLL_VCO_ENABLE;
8202         crtc_state->dpll_hw_state.dpll = dpll;
8203
8204         if (INTEL_GEN(dev_priv) >= 4) {
8205                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8206                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8207                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8208         }
8209 }
8210
8211 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8212                               struct intel_crtc_state *crtc_state,
8213                               struct dpll *reduced_clock)
8214 {
8215         struct drm_device *dev = crtc->base.dev;
8216         struct drm_i915_private *dev_priv = to_i915(dev);
8217         u32 dpll;
8218         struct dpll *clock = &crtc_state->dpll;
8219
8220         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8221
8222         dpll = DPLL_VGA_MODE_DIS;
8223
8224         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8225                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8226         } else {
8227                 if (clock->p1 == 2)
8228                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8229                 else
8230                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8231                 if (clock->p2 == 4)
8232                         dpll |= PLL_P2_DIVIDE_BY_4;
8233         }
8234
8235         /*
8236          * Bspec:
8237          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8238          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8239          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8240          *  Enable) must be set to “1” in both the DPLL A Control Register
8241          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8242          *
8243          * For simplicity We simply keep both bits always enabled in
8244          * both DPLLS. The spec says we should disable the DVO 2X clock
8245          * when not needed, but this seems to work fine in practice.
8246          */
8247         if (IS_I830(dev_priv) ||
8248             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8249                 dpll |= DPLL_DVO_2X_MODE;
8250
8251         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8252             intel_panel_use_ssc(dev_priv))
8253                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8254         else
8255                 dpll |= PLL_REF_INPUT_DREFCLK;
8256
8257         dpll |= DPLL_VCO_ENABLE;
8258         crtc_state->dpll_hw_state.dpll = dpll;
8259 }
8260
8261 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8262 {
8263         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8264         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8265         enum pipe pipe = crtc->pipe;
8266         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8267         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8268         u32 crtc_vtotal, crtc_vblank_end;
8269         int vsyncshift = 0;
8270
8271         /* We need to be careful not to changed the adjusted mode, for otherwise
8272          * the hw state checker will get angry at the mismatch. */
8273         crtc_vtotal = adjusted_mode->crtc_vtotal;
8274         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8275
8276         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8277                 /* the chip adds 2 halflines automatically */
8278                 crtc_vtotal -= 1;
8279                 crtc_vblank_end -= 1;
8280
8281                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8282                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8283                 else
8284                         vsyncshift = adjusted_mode->crtc_hsync_start -
8285                                 adjusted_mode->crtc_htotal / 2;
8286                 if (vsyncshift < 0)
8287                         vsyncshift += adjusted_mode->crtc_htotal;
8288         }
8289
8290         if (INTEL_GEN(dev_priv) > 3)
8291                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8292
8293         I915_WRITE(HTOTAL(cpu_transcoder),
8294                    (adjusted_mode->crtc_hdisplay - 1) |
8295                    ((adjusted_mode->crtc_htotal - 1) << 16));
8296         I915_WRITE(HBLANK(cpu_transcoder),
8297                    (adjusted_mode->crtc_hblank_start - 1) |
8298                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8299         I915_WRITE(HSYNC(cpu_transcoder),
8300                    (adjusted_mode->crtc_hsync_start - 1) |
8301                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8302
8303         I915_WRITE(VTOTAL(cpu_transcoder),
8304                    (adjusted_mode->crtc_vdisplay - 1) |
8305                    ((crtc_vtotal - 1) << 16));
8306         I915_WRITE(VBLANK(cpu_transcoder),
8307                    (adjusted_mode->crtc_vblank_start - 1) |
8308                    ((crtc_vblank_end - 1) << 16));
8309         I915_WRITE(VSYNC(cpu_transcoder),
8310                    (adjusted_mode->crtc_vsync_start - 1) |
8311                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8312
8313         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8314          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8315          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8316          * bits. */
8317         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8318             (pipe == PIPE_B || pipe == PIPE_C))
8319                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8320
8321 }
8322
8323 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8324 {
8325         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8326         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8327         enum pipe pipe = crtc->pipe;
8328
8329         /* pipesrc controls the size that is scaled from, which should
8330          * always be the user's requested size.
8331          */
8332         I915_WRITE(PIPESRC(pipe),
8333                    ((crtc_state->pipe_src_w - 1) << 16) |
8334                    (crtc_state->pipe_src_h - 1));
8335 }
8336
8337 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8338 {
8339         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8340         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8341
8342         if (IS_GEN(dev_priv, 2))
8343                 return false;
8344
8345         if (INTEL_GEN(dev_priv) >= 9 ||
8346             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8347                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8348         else
8349                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8350 }
8351
8352 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8353                                    struct intel_crtc_state *pipe_config)
8354 {
8355         struct drm_device *dev = crtc->base.dev;
8356         struct drm_i915_private *dev_priv = to_i915(dev);
8357         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8358         u32 tmp;
8359
8360         tmp = I915_READ(HTOTAL(cpu_transcoder));
8361         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8362         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8363
8364         if (!transcoder_is_dsi(cpu_transcoder)) {
8365                 tmp = I915_READ(HBLANK(cpu_transcoder));
8366                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8367                                                         (tmp & 0xffff) + 1;
8368                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8369                                                 ((tmp >> 16) & 0xffff) + 1;
8370         }
8371         tmp = I915_READ(HSYNC(cpu_transcoder));
8372         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8373         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8374
8375         tmp = I915_READ(VTOTAL(cpu_transcoder));
8376         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8377         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8378
8379         if (!transcoder_is_dsi(cpu_transcoder)) {
8380                 tmp = I915_READ(VBLANK(cpu_transcoder));
8381                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8382                                                         (tmp & 0xffff) + 1;
8383                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8384                                                 ((tmp >> 16) & 0xffff) + 1;
8385         }
8386         tmp = I915_READ(VSYNC(cpu_transcoder));
8387         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8388         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8389
8390         if (intel_pipe_is_interlaced(pipe_config)) {
8391                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8392                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8393                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8394         }
8395 }
8396
8397 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8398                                     struct intel_crtc_state *pipe_config)
8399 {
8400         struct drm_device *dev = crtc->base.dev;
8401         struct drm_i915_private *dev_priv = to_i915(dev);
8402         u32 tmp;
8403
8404         tmp = I915_READ(PIPESRC(crtc->pipe));
8405         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8406         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8407
8408         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8409         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8410 }
8411
8412 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8413                                  struct intel_crtc_state *pipe_config)
8414 {
8415         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8416         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8417         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8418         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8419
8420         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8421         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8422         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8423         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8424
8425         mode->flags = pipe_config->hw.adjusted_mode.flags;
8426         mode->type = DRM_MODE_TYPE_DRIVER;
8427
8428         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8429
8430         mode->hsync = drm_mode_hsync(mode);
8431         mode->vrefresh = drm_mode_vrefresh(mode);
8432         drm_mode_set_name(mode);
8433 }
8434
8435 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8436 {
8437         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8439         u32 pipeconf;
8440
8441         pipeconf = 0;
8442
8443         /* we keep both pipes enabled on 830 */
8444         if (IS_I830(dev_priv))
8445                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8446
8447         if (crtc_state->double_wide)
8448                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8449
8450         /* only g4x and later have fancy bpc/dither controls */
8451         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8452             IS_CHERRYVIEW(dev_priv)) {
8453                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8454                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8455                         pipeconf |= PIPECONF_DITHER_EN |
8456                                     PIPECONF_DITHER_TYPE_SP;
8457
8458                 switch (crtc_state->pipe_bpp) {
8459                 case 18:
8460                         pipeconf |= PIPECONF_6BPC;
8461                         break;
8462                 case 24:
8463                         pipeconf |= PIPECONF_8BPC;
8464                         break;
8465                 case 30:
8466                         pipeconf |= PIPECONF_10BPC;
8467                         break;
8468                 default:
8469                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8470                         BUG();
8471                 }
8472         }
8473
8474         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8475                 if (INTEL_GEN(dev_priv) < 4 ||
8476                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8477                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8478                 else
8479                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8480         } else {
8481                 pipeconf |= PIPECONF_PROGRESSIVE;
8482         }
8483
8484         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8485              crtc_state->limited_color_range)
8486                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8487
8488         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8489
8490         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8491
8492         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8493         POSTING_READ(PIPECONF(crtc->pipe));
8494 }
8495
8496 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8497                                    struct intel_crtc_state *crtc_state)
8498 {
8499         struct drm_device *dev = crtc->base.dev;
8500         struct drm_i915_private *dev_priv = to_i915(dev);
8501         const struct intel_limit *limit;
8502         int refclk = 48000;
8503
8504         memset(&crtc_state->dpll_hw_state, 0,
8505                sizeof(crtc_state->dpll_hw_state));
8506
8507         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8508                 if (intel_panel_use_ssc(dev_priv)) {
8509                         refclk = dev_priv->vbt.lvds_ssc_freq;
8510                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8511                 }
8512
8513                 limit = &intel_limits_i8xx_lvds;
8514         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8515                 limit = &intel_limits_i8xx_dvo;
8516         } else {
8517                 limit = &intel_limits_i8xx_dac;
8518         }
8519
8520         if (!crtc_state->clock_set &&
8521             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8522                                  refclk, NULL, &crtc_state->dpll)) {
8523                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8524                 return -EINVAL;
8525         }
8526
8527         i8xx_compute_dpll(crtc, crtc_state, NULL);
8528
8529         return 0;
8530 }
8531
8532 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8533                                   struct intel_crtc_state *crtc_state)
8534 {
8535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8536         const struct intel_limit *limit;
8537         int refclk = 96000;
8538
8539         memset(&crtc_state->dpll_hw_state, 0,
8540                sizeof(crtc_state->dpll_hw_state));
8541
8542         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8543                 if (intel_panel_use_ssc(dev_priv)) {
8544                         refclk = dev_priv->vbt.lvds_ssc_freq;
8545                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8546                 }
8547
8548                 if (intel_is_dual_link_lvds(dev_priv))
8549                         limit = &intel_limits_g4x_dual_channel_lvds;
8550                 else
8551                         limit = &intel_limits_g4x_single_channel_lvds;
8552         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8553                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8554                 limit = &intel_limits_g4x_hdmi;
8555         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8556                 limit = &intel_limits_g4x_sdvo;
8557         } else {
8558                 /* The option is for other outputs */
8559                 limit = &intel_limits_i9xx_sdvo;
8560         }
8561
8562         if (!crtc_state->clock_set &&
8563             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8564                                 refclk, NULL, &crtc_state->dpll)) {
8565                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8566                 return -EINVAL;
8567         }
8568
8569         i9xx_compute_dpll(crtc, crtc_state, NULL);
8570
8571         return 0;
8572 }
8573
8574 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8575                                   struct intel_crtc_state *crtc_state)
8576 {
8577         struct drm_device *dev = crtc->base.dev;
8578         struct drm_i915_private *dev_priv = to_i915(dev);
8579         const struct intel_limit *limit;
8580         int refclk = 96000;
8581
8582         memset(&crtc_state->dpll_hw_state, 0,
8583                sizeof(crtc_state->dpll_hw_state));
8584
8585         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8586                 if (intel_panel_use_ssc(dev_priv)) {
8587                         refclk = dev_priv->vbt.lvds_ssc_freq;
8588                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8589                 }
8590
8591                 limit = &intel_limits_pineview_lvds;
8592         } else {
8593                 limit = &intel_limits_pineview_sdvo;
8594         }
8595
8596         if (!crtc_state->clock_set &&
8597             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8598                                 refclk, NULL, &crtc_state->dpll)) {
8599                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8600                 return -EINVAL;
8601         }
8602
8603         i9xx_compute_dpll(crtc, crtc_state, NULL);
8604
8605         return 0;
8606 }
8607
8608 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8609                                    struct intel_crtc_state *crtc_state)
8610 {
8611         struct drm_device *dev = crtc->base.dev;
8612         struct drm_i915_private *dev_priv = to_i915(dev);
8613         const struct intel_limit *limit;
8614         int refclk = 96000;
8615
8616         memset(&crtc_state->dpll_hw_state, 0,
8617                sizeof(crtc_state->dpll_hw_state));
8618
8619         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8620                 if (intel_panel_use_ssc(dev_priv)) {
8621                         refclk = dev_priv->vbt.lvds_ssc_freq;
8622                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8623                 }
8624
8625                 limit = &intel_limits_i9xx_lvds;
8626         } else {
8627                 limit = &intel_limits_i9xx_sdvo;
8628         }
8629
8630         if (!crtc_state->clock_set &&
8631             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8632                                  refclk, NULL, &crtc_state->dpll)) {
8633                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8634                 return -EINVAL;
8635         }
8636
8637         i9xx_compute_dpll(crtc, crtc_state, NULL);
8638
8639         return 0;
8640 }
8641
8642 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8643                                   struct intel_crtc_state *crtc_state)
8644 {
8645         int refclk = 100000;
8646         const struct intel_limit *limit = &intel_limits_chv;
8647
8648         memset(&crtc_state->dpll_hw_state, 0,
8649                sizeof(crtc_state->dpll_hw_state));
8650
8651         if (!crtc_state->clock_set &&
8652             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8653                                 refclk, NULL, &crtc_state->dpll)) {
8654                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8655                 return -EINVAL;
8656         }
8657
8658         chv_compute_dpll(crtc, crtc_state);
8659
8660         return 0;
8661 }
8662
8663 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8664                                   struct intel_crtc_state *crtc_state)
8665 {
8666         int refclk = 100000;
8667         const struct intel_limit *limit = &intel_limits_vlv;
8668
8669         memset(&crtc_state->dpll_hw_state, 0,
8670                sizeof(crtc_state->dpll_hw_state));
8671
8672         if (!crtc_state->clock_set &&
8673             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8674                                 refclk, NULL, &crtc_state->dpll)) {
8675                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8676                 return -EINVAL;
8677         }
8678
8679         vlv_compute_dpll(crtc, crtc_state);
8680
8681         return 0;
8682 }
8683
8684 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8685 {
8686         if (IS_I830(dev_priv))
8687                 return false;
8688
8689         return INTEL_GEN(dev_priv) >= 4 ||
8690                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8691 }
8692
8693 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8694                                  struct intel_crtc_state *pipe_config)
8695 {
8696         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8697         u32 tmp;
8698
8699         if (!i9xx_has_pfit(dev_priv))
8700                 return;
8701
8702         tmp = I915_READ(PFIT_CONTROL);
8703         if (!(tmp & PFIT_ENABLE))
8704                 return;
8705
8706         /* Check whether the pfit is attached to our pipe. */
8707         if (INTEL_GEN(dev_priv) < 4) {
8708                 if (crtc->pipe != PIPE_B)
8709                         return;
8710         } else {
8711                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8712                         return;
8713         }
8714
8715         pipe_config->gmch_pfit.control = tmp;
8716         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8717 }
8718
8719 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8720                                struct intel_crtc_state *pipe_config)
8721 {
8722         struct drm_device *dev = crtc->base.dev;
8723         struct drm_i915_private *dev_priv = to_i915(dev);
8724         enum pipe pipe = crtc->pipe;
8725         struct dpll clock;
8726         u32 mdiv;
8727         int refclk = 100000;
8728
8729         /* In case of DSI, DPLL will not be used */
8730         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8731                 return;
8732
8733         vlv_dpio_get(dev_priv);
8734         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8735         vlv_dpio_put(dev_priv);
8736
8737         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8738         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8739         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8740         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8741         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8742
8743         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8744 }
8745
8746 static void
8747 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8748                               struct intel_initial_plane_config *plane_config)
8749 {
8750         struct drm_device *dev = crtc->base.dev;
8751         struct drm_i915_private *dev_priv = to_i915(dev);
8752         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8753         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8754         enum pipe pipe;
8755         u32 val, base, offset;
8756         int fourcc, pixel_format;
8757         unsigned int aligned_height;
8758         struct drm_framebuffer *fb;
8759         struct intel_framebuffer *intel_fb;
8760
8761         if (!plane->get_hw_state(plane, &pipe))
8762                 return;
8763
8764         WARN_ON(pipe != crtc->pipe);
8765
8766         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8767         if (!intel_fb) {
8768                 DRM_DEBUG_KMS("failed to alloc fb\n");
8769                 return;
8770         }
8771
8772         fb = &intel_fb->base;
8773
8774         fb->dev = dev;
8775
8776         val = I915_READ(DSPCNTR(i9xx_plane));
8777
8778         if (INTEL_GEN(dev_priv) >= 4) {
8779                 if (val & DISPPLANE_TILED) {
8780                         plane_config->tiling = I915_TILING_X;
8781                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8782                 }
8783
8784                 if (val & DISPPLANE_ROTATE_180)
8785                         plane_config->rotation = DRM_MODE_ROTATE_180;
8786         }
8787
8788         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8789             val & DISPPLANE_MIRROR)
8790                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8791
8792         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8793         fourcc = i9xx_format_to_fourcc(pixel_format);
8794         fb->format = drm_format_info(fourcc);
8795
8796         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8797                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8798                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8799         } else if (INTEL_GEN(dev_priv) >= 4) {
8800                 if (plane_config->tiling)
8801                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8802                 else
8803                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8804                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8805         } else {
8806                 base = I915_READ(DSPADDR(i9xx_plane));
8807         }
8808         plane_config->base = base;
8809
8810         val = I915_READ(PIPESRC(pipe));
8811         fb->width = ((val >> 16) & 0xfff) + 1;
8812         fb->height = ((val >> 0) & 0xfff) + 1;
8813
8814         val = I915_READ(DSPSTRIDE(i9xx_plane));
8815         fb->pitches[0] = val & 0xffffffc0;
8816
8817         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8818
8819         plane_config->size = fb->pitches[0] * aligned_height;
8820
8821         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8822                       crtc->base.name, plane->base.name, fb->width, fb->height,
8823                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8824                       plane_config->size);
8825
8826         plane_config->fb = intel_fb;
8827 }
8828
8829 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8830                                struct intel_crtc_state *pipe_config)
8831 {
8832         struct drm_device *dev = crtc->base.dev;
8833         struct drm_i915_private *dev_priv = to_i915(dev);
8834         enum pipe pipe = crtc->pipe;
8835         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8836         struct dpll clock;
8837         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8838         int refclk = 100000;
8839
8840         /* In case of DSI, DPLL will not be used */
8841         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8842                 return;
8843
8844         vlv_dpio_get(dev_priv);
8845         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8846         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8847         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8848         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8849         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8850         vlv_dpio_put(dev_priv);
8851
8852         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8853         clock.m2 = (pll_dw0 & 0xff) << 22;
8854         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8855                 clock.m2 |= pll_dw2 & 0x3fffff;
8856         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8857         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8858         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8859
8860         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8861 }
8862
8863 static enum intel_output_format
8864 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8865 {
8866         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8867         u32 tmp;
8868
8869         tmp = I915_READ(PIPEMISC(crtc->pipe));
8870
8871         if (tmp & PIPEMISC_YUV420_ENABLE) {
8872                 /* We support 4:2:0 in full blend mode only */
8873                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8874
8875                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8876         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8877                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8878         } else {
8879                 return INTEL_OUTPUT_FORMAT_RGB;
8880         }
8881 }
8882
8883 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8884 {
8885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8886         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8887         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8888         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8889         u32 tmp;
8890
8891         tmp = I915_READ(DSPCNTR(i9xx_plane));
8892
8893         if (tmp & DISPPLANE_GAMMA_ENABLE)
8894                 crtc_state->gamma_enable = true;
8895
8896         if (!HAS_GMCH(dev_priv) &&
8897             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8898                 crtc_state->csc_enable = true;
8899 }
8900
8901 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8902                                  struct intel_crtc_state *pipe_config)
8903 {
8904         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8905         enum intel_display_power_domain power_domain;
8906         intel_wakeref_t wakeref;
8907         u32 tmp;
8908         bool ret;
8909
8910         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8911         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8912         if (!wakeref)
8913                 return false;
8914
8915         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8916         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8917         pipe_config->shared_dpll = NULL;
8918         pipe_config->master_transcoder = INVALID_TRANSCODER;
8919
8920         ret = false;
8921
8922         tmp = I915_READ(PIPECONF(crtc->pipe));
8923         if (!(tmp & PIPECONF_ENABLE))
8924                 goto out;
8925
8926         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8927             IS_CHERRYVIEW(dev_priv)) {
8928                 switch (tmp & PIPECONF_BPC_MASK) {
8929                 case PIPECONF_6BPC:
8930                         pipe_config->pipe_bpp = 18;
8931                         break;
8932                 case PIPECONF_8BPC:
8933                         pipe_config->pipe_bpp = 24;
8934                         break;
8935                 case PIPECONF_10BPC:
8936                         pipe_config->pipe_bpp = 30;
8937                         break;
8938                 default:
8939                         break;
8940                 }
8941         }
8942
8943         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8944             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8945                 pipe_config->limited_color_range = true;
8946
8947         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8948                 PIPECONF_GAMMA_MODE_SHIFT;
8949
8950         if (IS_CHERRYVIEW(dev_priv))
8951                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8952
8953         i9xx_get_pipe_color_config(pipe_config);
8954         intel_color_get_config(pipe_config);
8955
8956         if (INTEL_GEN(dev_priv) < 4)
8957                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8958
8959         intel_get_pipe_timings(crtc, pipe_config);
8960         intel_get_pipe_src_size(crtc, pipe_config);
8961
8962         i9xx_get_pfit_config(crtc, pipe_config);
8963
8964         if (INTEL_GEN(dev_priv) >= 4) {
8965                 /* No way to read it out on pipes B and C */
8966                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8967                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8968                 else
8969                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8970                 pipe_config->pixel_multiplier =
8971                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8972                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8973                 pipe_config->dpll_hw_state.dpll_md = tmp;
8974         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8975                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8976                 tmp = I915_READ(DPLL(crtc->pipe));
8977                 pipe_config->pixel_multiplier =
8978                         ((tmp & SDVO_MULTIPLIER_MASK)
8979                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8980         } else {
8981                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8982                  * port and will be fixed up in the encoder->get_config
8983                  * function. */
8984                 pipe_config->pixel_multiplier = 1;
8985         }
8986         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8987         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8988                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8989                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8990         } else {
8991                 /* Mask out read-only status bits. */
8992                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8993                                                      DPLL_PORTC_READY_MASK |
8994                                                      DPLL_PORTB_READY_MASK);
8995         }
8996
8997         if (IS_CHERRYVIEW(dev_priv))
8998                 chv_crtc_clock_get(crtc, pipe_config);
8999         else if (IS_VALLEYVIEW(dev_priv))
9000                 vlv_crtc_clock_get(crtc, pipe_config);
9001         else
9002                 i9xx_crtc_clock_get(crtc, pipe_config);
9003
9004         /*
9005          * Normally the dotclock is filled in by the encoder .get_config()
9006          * but in case the pipe is enabled w/o any ports we need a sane
9007          * default.
9008          */
9009         pipe_config->hw.adjusted_mode.crtc_clock =
9010                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9011
9012         ret = true;
9013
9014 out:
9015         intel_display_power_put(dev_priv, power_domain, wakeref);
9016
9017         return ret;
9018 }
9019
9020 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9021 {
9022         struct intel_encoder *encoder;
9023         int i;
9024         u32 val, final;
9025         bool has_lvds = false;
9026         bool has_cpu_edp = false;
9027         bool has_panel = false;
9028         bool has_ck505 = false;
9029         bool can_ssc = false;
9030         bool using_ssc_source = false;
9031
9032         /* We need to take the global config into account */
9033         for_each_intel_encoder(&dev_priv->drm, encoder) {
9034                 switch (encoder->type) {
9035                 case INTEL_OUTPUT_LVDS:
9036                         has_panel = true;
9037                         has_lvds = true;
9038                         break;
9039                 case INTEL_OUTPUT_EDP:
9040                         has_panel = true;
9041                         if (encoder->port == PORT_A)
9042                                 has_cpu_edp = true;
9043                         break;
9044                 default:
9045                         break;
9046                 }
9047         }
9048
9049         if (HAS_PCH_IBX(dev_priv)) {
9050                 has_ck505 = dev_priv->vbt.display_clock_mode;
9051                 can_ssc = has_ck505;
9052         } else {
9053                 has_ck505 = false;
9054                 can_ssc = true;
9055         }
9056
9057         /* Check if any DPLLs are using the SSC source */
9058         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9059                 u32 temp = I915_READ(PCH_DPLL(i));
9060
9061                 if (!(temp & DPLL_VCO_ENABLE))
9062                         continue;
9063
9064                 if ((temp & PLL_REF_INPUT_MASK) ==
9065                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9066                         using_ssc_source = true;
9067                         break;
9068                 }
9069         }
9070
9071         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9072                       has_panel, has_lvds, has_ck505, using_ssc_source);
9073
9074         /* Ironlake: try to setup display ref clock before DPLL
9075          * enabling. This is only under driver's control after
9076          * PCH B stepping, previous chipset stepping should be
9077          * ignoring this setting.
9078          */
9079         val = I915_READ(PCH_DREF_CONTROL);
9080
9081         /* As we must carefully and slowly disable/enable each source in turn,
9082          * compute the final state we want first and check if we need to
9083          * make any changes at all.
9084          */
9085         final = val;
9086         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9087         if (has_ck505)
9088                 final |= DREF_NONSPREAD_CK505_ENABLE;
9089         else
9090                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9091
9092         final &= ~DREF_SSC_SOURCE_MASK;
9093         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9094         final &= ~DREF_SSC1_ENABLE;
9095
9096         if (has_panel) {
9097                 final |= DREF_SSC_SOURCE_ENABLE;
9098
9099                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9100                         final |= DREF_SSC1_ENABLE;
9101
9102                 if (has_cpu_edp) {
9103                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9104                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9105                         else
9106                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9107                 } else
9108                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9109         } else if (using_ssc_source) {
9110                 final |= DREF_SSC_SOURCE_ENABLE;
9111                 final |= DREF_SSC1_ENABLE;
9112         }
9113
9114         if (final == val)
9115                 return;
9116
9117         /* Always enable nonspread source */
9118         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9119
9120         if (has_ck505)
9121                 val |= DREF_NONSPREAD_CK505_ENABLE;
9122         else
9123                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9124
9125         if (has_panel) {
9126                 val &= ~DREF_SSC_SOURCE_MASK;
9127                 val |= DREF_SSC_SOURCE_ENABLE;
9128
9129                 /* SSC must be turned on before enabling the CPU output  */
9130                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9131                         DRM_DEBUG_KMS("Using SSC on panel\n");
9132                         val |= DREF_SSC1_ENABLE;
9133                 } else
9134                         val &= ~DREF_SSC1_ENABLE;
9135
9136                 /* Get SSC going before enabling the outputs */
9137                 I915_WRITE(PCH_DREF_CONTROL, val);
9138                 POSTING_READ(PCH_DREF_CONTROL);
9139                 udelay(200);
9140
9141                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9142
9143                 /* Enable CPU source on CPU attached eDP */
9144                 if (has_cpu_edp) {
9145                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9146                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9147                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9148                         } else
9149                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9150                 } else
9151                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9152
9153                 I915_WRITE(PCH_DREF_CONTROL, val);
9154                 POSTING_READ(PCH_DREF_CONTROL);
9155                 udelay(200);
9156         } else {
9157                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9158
9159                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9160
9161                 /* Turn off CPU output */
9162                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9163
9164                 I915_WRITE(PCH_DREF_CONTROL, val);
9165                 POSTING_READ(PCH_DREF_CONTROL);
9166                 udelay(200);
9167
9168                 if (!using_ssc_source) {
9169                         DRM_DEBUG_KMS("Disabling SSC source\n");
9170
9171                         /* Turn off the SSC source */
9172                         val &= ~DREF_SSC_SOURCE_MASK;
9173                         val |= DREF_SSC_SOURCE_DISABLE;
9174
9175                         /* Turn off SSC1 */
9176                         val &= ~DREF_SSC1_ENABLE;
9177
9178                         I915_WRITE(PCH_DREF_CONTROL, val);
9179                         POSTING_READ(PCH_DREF_CONTROL);
9180                         udelay(200);
9181                 }
9182         }
9183
9184         BUG_ON(val != final);
9185 }
9186
9187 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9188 {
9189         u32 tmp;
9190
9191         tmp = I915_READ(SOUTH_CHICKEN2);
9192         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9193         I915_WRITE(SOUTH_CHICKEN2, tmp);
9194
9195         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9196                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9197                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9198
9199         tmp = I915_READ(SOUTH_CHICKEN2);
9200         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9201         I915_WRITE(SOUTH_CHICKEN2, tmp);
9202
9203         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9204                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9205                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9206 }
9207
9208 /* WaMPhyProgramming:hsw */
9209 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9210 {
9211         u32 tmp;
9212
9213         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9214         tmp &= ~(0xFF << 24);
9215         tmp |= (0x12 << 24);
9216         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9217
9218         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9219         tmp |= (1 << 11);
9220         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9221
9222         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9223         tmp |= (1 << 11);
9224         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9225
9226         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9227         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9228         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9229
9230         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9231         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9232         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9233
9234         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9235         tmp &= ~(7 << 13);
9236         tmp |= (5 << 13);
9237         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9238
9239         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9240         tmp &= ~(7 << 13);
9241         tmp |= (5 << 13);
9242         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9243
9244         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9245         tmp &= ~0xFF;
9246         tmp |= 0x1C;
9247         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9248
9249         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9250         tmp &= ~0xFF;
9251         tmp |= 0x1C;
9252         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9253
9254         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9255         tmp &= ~(0xFF << 16);
9256         tmp |= (0x1C << 16);
9257         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9258
9259         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9260         tmp &= ~(0xFF << 16);
9261         tmp |= (0x1C << 16);
9262         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9263
9264         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9265         tmp |= (1 << 27);
9266         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9267
9268         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9269         tmp |= (1 << 27);
9270         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9271
9272         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9273         tmp &= ~(0xF << 28);
9274         tmp |= (4 << 28);
9275         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9276
9277         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9278         tmp &= ~(0xF << 28);
9279         tmp |= (4 << 28);
9280         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9281 }
9282
9283 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9284  * Programming" based on the parameters passed:
9285  * - Sequence to enable CLKOUT_DP
9286  * - Sequence to enable CLKOUT_DP without spread
9287  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9288  */
9289 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9290                                  bool with_spread, bool with_fdi)
9291 {
9292         u32 reg, tmp;
9293
9294         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9295                 with_spread = true;
9296         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9297             with_fdi, "LP PCH doesn't have FDI\n"))
9298                 with_fdi = false;
9299
9300         mutex_lock(&dev_priv->sb_lock);
9301
9302         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9303         tmp &= ~SBI_SSCCTL_DISABLE;
9304         tmp |= SBI_SSCCTL_PATHALT;
9305         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9306
9307         udelay(24);
9308
9309         if (with_spread) {
9310                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9311                 tmp &= ~SBI_SSCCTL_PATHALT;
9312                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9313
9314                 if (with_fdi) {
9315                         lpt_reset_fdi_mphy(dev_priv);
9316                         lpt_program_fdi_mphy(dev_priv);
9317                 }
9318         }
9319
9320         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9321         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9322         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9323         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9324
9325         mutex_unlock(&dev_priv->sb_lock);
9326 }
9327
9328 /* Sequence to disable CLKOUT_DP */
9329 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9330 {
9331         u32 reg, tmp;
9332
9333         mutex_lock(&dev_priv->sb_lock);
9334
9335         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9336         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9337         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9338         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9339
9340         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9341         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9342                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9343                         tmp |= SBI_SSCCTL_PATHALT;
9344                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9345                         udelay(32);
9346                 }
9347                 tmp |= SBI_SSCCTL_DISABLE;
9348                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9349         }
9350
9351         mutex_unlock(&dev_priv->sb_lock);
9352 }
9353
9354 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9355
9356 static const u16 sscdivintphase[] = {
9357         [BEND_IDX( 50)] = 0x3B23,
9358         [BEND_IDX( 45)] = 0x3B23,
9359         [BEND_IDX( 40)] = 0x3C23,
9360         [BEND_IDX( 35)] = 0x3C23,
9361         [BEND_IDX( 30)] = 0x3D23,
9362         [BEND_IDX( 25)] = 0x3D23,
9363         [BEND_IDX( 20)] = 0x3E23,
9364         [BEND_IDX( 15)] = 0x3E23,
9365         [BEND_IDX( 10)] = 0x3F23,
9366         [BEND_IDX(  5)] = 0x3F23,
9367         [BEND_IDX(  0)] = 0x0025,
9368         [BEND_IDX( -5)] = 0x0025,
9369         [BEND_IDX(-10)] = 0x0125,
9370         [BEND_IDX(-15)] = 0x0125,
9371         [BEND_IDX(-20)] = 0x0225,
9372         [BEND_IDX(-25)] = 0x0225,
9373         [BEND_IDX(-30)] = 0x0325,
9374         [BEND_IDX(-35)] = 0x0325,
9375         [BEND_IDX(-40)] = 0x0425,
9376         [BEND_IDX(-45)] = 0x0425,
9377         [BEND_IDX(-50)] = 0x0525,
9378 };
9379
9380 /*
9381  * Bend CLKOUT_DP
9382  * steps -50 to 50 inclusive, in steps of 5
9383  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9384  * change in clock period = -(steps / 10) * 5.787 ps
9385  */
9386 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9387 {
9388         u32 tmp;
9389         int idx = BEND_IDX(steps);
9390
9391         if (WARN_ON(steps % 5 != 0))
9392                 return;
9393
9394         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9395                 return;
9396
9397         mutex_lock(&dev_priv->sb_lock);
9398
9399         if (steps % 10 != 0)
9400                 tmp = 0xAAAAAAAB;
9401         else
9402                 tmp = 0x00000000;
9403         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9404
9405         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9406         tmp &= 0xffff0000;
9407         tmp |= sscdivintphase[idx];
9408         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9409
9410         mutex_unlock(&dev_priv->sb_lock);
9411 }
9412
9413 #undef BEND_IDX
9414
9415 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9416 {
9417         u32 fuse_strap = I915_READ(FUSE_STRAP);
9418         u32 ctl = I915_READ(SPLL_CTL);
9419
9420         if ((ctl & SPLL_PLL_ENABLE) == 0)
9421                 return false;
9422
9423         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9424             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9425                 return true;
9426
9427         if (IS_BROADWELL(dev_priv) &&
9428             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9429                 return true;
9430
9431         return false;
9432 }
9433
9434 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9435                                enum intel_dpll_id id)
9436 {
9437         u32 fuse_strap = I915_READ(FUSE_STRAP);
9438         u32 ctl = I915_READ(WRPLL_CTL(id));
9439
9440         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9441                 return false;
9442
9443         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9444                 return true;
9445
9446         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9447             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9448             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9449                 return true;
9450
9451         return false;
9452 }
9453
9454 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9455 {
9456         struct intel_encoder *encoder;
9457         bool has_fdi = false;
9458
9459         for_each_intel_encoder(&dev_priv->drm, encoder) {
9460                 switch (encoder->type) {
9461                 case INTEL_OUTPUT_ANALOG:
9462                         has_fdi = true;
9463                         break;
9464                 default:
9465                         break;
9466                 }
9467         }
9468
9469         /*
9470          * The BIOS may have decided to use the PCH SSC
9471          * reference so we must not disable it until the
9472          * relevant PLLs have stopped relying on it. We'll
9473          * just leave the PCH SSC reference enabled in case
9474          * any active PLL is using it. It will get disabled
9475          * after runtime suspend if we don't have FDI.
9476          *
9477          * TODO: Move the whole reference clock handling
9478          * to the modeset sequence proper so that we can
9479          * actually enable/disable/reconfigure these things
9480          * safely. To do that we need to introduce a real
9481          * clock hierarchy. That would also allow us to do
9482          * clock bending finally.
9483          */
9484         dev_priv->pch_ssc_use = 0;
9485
9486         if (spll_uses_pch_ssc(dev_priv)) {
9487                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9488                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9489         }
9490
9491         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9492                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9493                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9494         }
9495
9496         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9497                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9498                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9499         }
9500
9501         if (dev_priv->pch_ssc_use)
9502                 return;
9503
9504         if (has_fdi) {
9505                 lpt_bend_clkout_dp(dev_priv, 0);
9506                 lpt_enable_clkout_dp(dev_priv, true, true);
9507         } else {
9508                 lpt_disable_clkout_dp(dev_priv);
9509         }
9510 }
9511
9512 /*
9513  * Initialize reference clocks when the driver loads
9514  */
9515 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9516 {
9517         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9518                 ironlake_init_pch_refclk(dev_priv);
9519         else if (HAS_PCH_LPT(dev_priv))
9520                 lpt_init_pch_refclk(dev_priv);
9521 }
9522
9523 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9524 {
9525         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9526         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9527         enum pipe pipe = crtc->pipe;
9528         u32 val;
9529
9530         val = 0;
9531
9532         switch (crtc_state->pipe_bpp) {
9533         case 18:
9534                 val |= PIPECONF_6BPC;
9535                 break;
9536         case 24:
9537                 val |= PIPECONF_8BPC;
9538                 break;
9539         case 30:
9540                 val |= PIPECONF_10BPC;
9541                 break;
9542         case 36:
9543                 val |= PIPECONF_12BPC;
9544                 break;
9545         default:
9546                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9547                 BUG();
9548         }
9549
9550         if (crtc_state->dither)
9551                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9552
9553         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9554                 val |= PIPECONF_INTERLACED_ILK;
9555         else
9556                 val |= PIPECONF_PROGRESSIVE;
9557
9558         /*
9559          * This would end up with an odd purple hue over
9560          * the entire display. Make sure we don't do it.
9561          */
9562         WARN_ON(crtc_state->limited_color_range &&
9563                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9564
9565         if (crtc_state->limited_color_range)
9566                 val |= PIPECONF_COLOR_RANGE_SELECT;
9567
9568         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9569                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9570
9571         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9572
9573         val |= PIPECONF_FRAME_START_DELAY(0);
9574
9575         I915_WRITE(PIPECONF(pipe), val);
9576         POSTING_READ(PIPECONF(pipe));
9577 }
9578
9579 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9580 {
9581         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9582         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9583         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9584         u32 val = 0;
9585
9586         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9587                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9588
9589         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9590                 val |= PIPECONF_INTERLACED_ILK;
9591         else
9592                 val |= PIPECONF_PROGRESSIVE;
9593
9594         if (IS_HASWELL(dev_priv) &&
9595             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9596                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9597
9598         I915_WRITE(PIPECONF(cpu_transcoder), val);
9599         POSTING_READ(PIPECONF(cpu_transcoder));
9600 }
9601
9602 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9603 {
9604         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9605         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9606         u32 val = 0;
9607
9608         switch (crtc_state->pipe_bpp) {
9609         case 18:
9610                 val |= PIPEMISC_DITHER_6_BPC;
9611                 break;
9612         case 24:
9613                 val |= PIPEMISC_DITHER_8_BPC;
9614                 break;
9615         case 30:
9616                 val |= PIPEMISC_DITHER_10_BPC;
9617                 break;
9618         case 36:
9619                 val |= PIPEMISC_DITHER_12_BPC;
9620                 break;
9621         default:
9622                 MISSING_CASE(crtc_state->pipe_bpp);
9623                 break;
9624         }
9625
9626         if (crtc_state->dither)
9627                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9628
9629         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9630             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9631                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9632
9633         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9634                 val |= PIPEMISC_YUV420_ENABLE |
9635                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9636
9637         if (INTEL_GEN(dev_priv) >= 11 &&
9638             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9639                                            BIT(PLANE_CURSOR))) == 0)
9640                 val |= PIPEMISC_HDR_MODE_PRECISION;
9641
9642         I915_WRITE(PIPEMISC(crtc->pipe), val);
9643 }
9644
9645 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9646 {
9647         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9648         u32 tmp;
9649
9650         tmp = I915_READ(PIPEMISC(crtc->pipe));
9651
9652         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9653         case PIPEMISC_DITHER_6_BPC:
9654                 return 18;
9655         case PIPEMISC_DITHER_8_BPC:
9656                 return 24;
9657         case PIPEMISC_DITHER_10_BPC:
9658                 return 30;
9659         case PIPEMISC_DITHER_12_BPC:
9660                 return 36;
9661         default:
9662                 MISSING_CASE(tmp);
9663                 return 0;
9664         }
9665 }
9666
9667 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9668 {
9669         /*
9670          * Account for spread spectrum to avoid
9671          * oversubscribing the link. Max center spread
9672          * is 2.5%; use 5% for safety's sake.
9673          */
9674         u32 bps = target_clock * bpp * 21 / 20;
9675         return DIV_ROUND_UP(bps, link_bw * 8);
9676 }
9677
9678 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9679 {
9680         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9681 }
9682
9683 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9684                                   struct intel_crtc_state *crtc_state,
9685                                   struct dpll *reduced_clock)
9686 {
9687         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9688         u32 dpll, fp, fp2;
9689         int factor;
9690
9691         /* Enable autotuning of the PLL clock (if permissible) */
9692         factor = 21;
9693         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9694                 if ((intel_panel_use_ssc(dev_priv) &&
9695                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9696                     (HAS_PCH_IBX(dev_priv) &&
9697                      intel_is_dual_link_lvds(dev_priv)))
9698                         factor = 25;
9699         } else if (crtc_state->sdvo_tv_clock) {
9700                 factor = 20;
9701         }
9702
9703         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9704
9705         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9706                 fp |= FP_CB_TUNE;
9707
9708         if (reduced_clock) {
9709                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9710
9711                 if (reduced_clock->m < factor * reduced_clock->n)
9712                         fp2 |= FP_CB_TUNE;
9713         } else {
9714                 fp2 = fp;
9715         }
9716
9717         dpll = 0;
9718
9719         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9720                 dpll |= DPLLB_MODE_LVDS;
9721         else
9722                 dpll |= DPLLB_MODE_DAC_SERIAL;
9723
9724         dpll |= (crtc_state->pixel_multiplier - 1)
9725                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9726
9727         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9728             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9729                 dpll |= DPLL_SDVO_HIGH_SPEED;
9730
9731         if (intel_crtc_has_dp_encoder(crtc_state))
9732                 dpll |= DPLL_SDVO_HIGH_SPEED;
9733
9734         /*
9735          * The high speed IO clock is only really required for
9736          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9737          * possible to share the DPLL between CRT and HDMI. Enabling
9738          * the clock needlessly does no real harm, except use up a
9739          * bit of power potentially.
9740          *
9741          * We'll limit this to IVB with 3 pipes, since it has only two
9742          * DPLLs and so DPLL sharing is the only way to get three pipes
9743          * driving PCH ports at the same time. On SNB we could do this,
9744          * and potentially avoid enabling the second DPLL, but it's not
9745          * clear if it''s a win or loss power wise. No point in doing
9746          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9747          */
9748         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9749             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9750                 dpll |= DPLL_SDVO_HIGH_SPEED;
9751
9752         /* compute bitmask from p1 value */
9753         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9754         /* also FPA1 */
9755         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9756
9757         switch (crtc_state->dpll.p2) {
9758         case 5:
9759                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9760                 break;
9761         case 7:
9762                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9763                 break;
9764         case 10:
9765                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9766                 break;
9767         case 14:
9768                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9769                 break;
9770         }
9771
9772         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9773             intel_panel_use_ssc(dev_priv))
9774                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9775         else
9776                 dpll |= PLL_REF_INPUT_DREFCLK;
9777
9778         dpll |= DPLL_VCO_ENABLE;
9779
9780         crtc_state->dpll_hw_state.dpll = dpll;
9781         crtc_state->dpll_hw_state.fp0 = fp;
9782         crtc_state->dpll_hw_state.fp1 = fp2;
9783 }
9784
9785 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9786                                        struct intel_crtc_state *crtc_state)
9787 {
9788         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9789         struct intel_atomic_state *state =
9790                 to_intel_atomic_state(crtc_state->uapi.state);
9791         const struct intel_limit *limit;
9792         int refclk = 120000;
9793
9794         memset(&crtc_state->dpll_hw_state, 0,
9795                sizeof(crtc_state->dpll_hw_state));
9796
9797         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9798         if (!crtc_state->has_pch_encoder)
9799                 return 0;
9800
9801         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9802                 if (intel_panel_use_ssc(dev_priv)) {
9803                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9804                                       dev_priv->vbt.lvds_ssc_freq);
9805                         refclk = dev_priv->vbt.lvds_ssc_freq;
9806                 }
9807
9808                 if (intel_is_dual_link_lvds(dev_priv)) {
9809                         if (refclk == 100000)
9810                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9811                         else
9812                                 limit = &intel_limits_ironlake_dual_lvds;
9813                 } else {
9814                         if (refclk == 100000)
9815                                 limit = &intel_limits_ironlake_single_lvds_100m;
9816                         else
9817                                 limit = &intel_limits_ironlake_single_lvds;
9818                 }
9819         } else {
9820                 limit = &intel_limits_ironlake_dac;
9821         }
9822
9823         if (!crtc_state->clock_set &&
9824             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9825                                 refclk, NULL, &crtc_state->dpll)) {
9826                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9827                 return -EINVAL;
9828         }
9829
9830         ironlake_compute_dpll(crtc, crtc_state, NULL);
9831
9832         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9833                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9834                               pipe_name(crtc->pipe));
9835                 return -EINVAL;
9836         }
9837
9838         return 0;
9839 }
9840
9841 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9842                                          struct intel_link_m_n *m_n)
9843 {
9844         struct drm_device *dev = crtc->base.dev;
9845         struct drm_i915_private *dev_priv = to_i915(dev);
9846         enum pipe pipe = crtc->pipe;
9847
9848         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9849         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9850         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9851                 & ~TU_SIZE_MASK;
9852         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9853         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9854                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9855 }
9856
9857 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9858                                          enum transcoder transcoder,
9859                                          struct intel_link_m_n *m_n,
9860                                          struct intel_link_m_n *m2_n2)
9861 {
9862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9863         enum pipe pipe = crtc->pipe;
9864
9865         if (INTEL_GEN(dev_priv) >= 5) {
9866                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9867                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9868                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9869                         & ~TU_SIZE_MASK;
9870                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9871                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9872                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9873
9874                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9875                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9876                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9877                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9878                                         & ~TU_SIZE_MASK;
9879                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9880                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9881                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9882                 }
9883         } else {
9884                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9885                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9886                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9887                         & ~TU_SIZE_MASK;
9888                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9889                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9890                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9891         }
9892 }
9893
9894 void intel_dp_get_m_n(struct intel_crtc *crtc,
9895                       struct intel_crtc_state *pipe_config)
9896 {
9897         if (pipe_config->has_pch_encoder)
9898                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9899         else
9900                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9901                                              &pipe_config->dp_m_n,
9902                                              &pipe_config->dp_m2_n2);
9903 }
9904
9905 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9906                                         struct intel_crtc_state *pipe_config)
9907 {
9908         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9909                                      &pipe_config->fdi_m_n, NULL);
9910 }
9911
9912 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9913                                     struct intel_crtc_state *pipe_config)
9914 {
9915         struct drm_device *dev = crtc->base.dev;
9916         struct drm_i915_private *dev_priv = to_i915(dev);
9917         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9918         u32 ps_ctrl = 0;
9919         int id = -1;
9920         int i;
9921
9922         /* find scaler attached to this pipe */
9923         for (i = 0; i < crtc->num_scalers; i++) {
9924                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9925                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9926                         id = i;
9927                         pipe_config->pch_pfit.enabled = true;
9928                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9929                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9930                         scaler_state->scalers[i].in_use = true;
9931                         break;
9932                 }
9933         }
9934
9935         scaler_state->scaler_id = id;
9936         if (id >= 0) {
9937                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9938         } else {
9939                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9940         }
9941 }
9942
9943 static void
9944 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9945                                  struct intel_initial_plane_config *plane_config)
9946 {
9947         struct drm_device *dev = crtc->base.dev;
9948         struct drm_i915_private *dev_priv = to_i915(dev);
9949         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9950         enum plane_id plane_id = plane->id;
9951         enum pipe pipe;
9952         u32 val, base, offset, stride_mult, tiling, alpha;
9953         int fourcc, pixel_format;
9954         unsigned int aligned_height;
9955         struct drm_framebuffer *fb;
9956         struct intel_framebuffer *intel_fb;
9957
9958         if (!plane->get_hw_state(plane, &pipe))
9959                 return;
9960
9961         WARN_ON(pipe != crtc->pipe);
9962
9963         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9964         if (!intel_fb) {
9965                 DRM_DEBUG_KMS("failed to alloc fb\n");
9966                 return;
9967         }
9968
9969         fb = &intel_fb->base;
9970
9971         fb->dev = dev;
9972
9973         val = I915_READ(PLANE_CTL(pipe, plane_id));
9974
9975         if (INTEL_GEN(dev_priv) >= 11)
9976                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9977         else
9978                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9979
9980         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9981                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9982                 alpha &= PLANE_COLOR_ALPHA_MASK;
9983         } else {
9984                 alpha = val & PLANE_CTL_ALPHA_MASK;
9985         }
9986
9987         fourcc = skl_format_to_fourcc(pixel_format,
9988                                       val & PLANE_CTL_ORDER_RGBX, alpha);
9989         fb->format = drm_format_info(fourcc);
9990
9991         tiling = val & PLANE_CTL_TILED_MASK;
9992         switch (tiling) {
9993         case PLANE_CTL_TILED_LINEAR:
9994                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9995                 break;
9996         case PLANE_CTL_TILED_X:
9997                 plane_config->tiling = I915_TILING_X;
9998                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9999                 break;
10000         case PLANE_CTL_TILED_Y:
10001                 plane_config->tiling = I915_TILING_Y;
10002                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10003                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
10004                 else
10005                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10006                 break;
10007         case PLANE_CTL_TILED_YF:
10008                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10009                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10010                 else
10011                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10012                 break;
10013         default:
10014                 MISSING_CASE(tiling);
10015                 goto error;
10016         }
10017
10018         /*
10019          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10020          * while i915 HW rotation is clockwise, thats why this swapping.
10021          */
10022         switch (val & PLANE_CTL_ROTATE_MASK) {
10023         case PLANE_CTL_ROTATE_0:
10024                 plane_config->rotation = DRM_MODE_ROTATE_0;
10025                 break;
10026         case PLANE_CTL_ROTATE_90:
10027                 plane_config->rotation = DRM_MODE_ROTATE_270;
10028                 break;
10029         case PLANE_CTL_ROTATE_180:
10030                 plane_config->rotation = DRM_MODE_ROTATE_180;
10031                 break;
10032         case PLANE_CTL_ROTATE_270:
10033                 plane_config->rotation = DRM_MODE_ROTATE_90;
10034                 break;
10035         }
10036
10037         if (INTEL_GEN(dev_priv) >= 10 &&
10038             val & PLANE_CTL_FLIP_HORIZONTAL)
10039                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10040
10041         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10042         plane_config->base = base;
10043
10044         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10045
10046         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10047         fb->height = ((val >> 16) & 0xffff) + 1;
10048         fb->width = ((val >> 0) & 0xffff) + 1;
10049
10050         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10051         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10052         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10053
10054         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10055
10056         plane_config->size = fb->pitches[0] * aligned_height;
10057
10058         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10059                       crtc->base.name, plane->base.name, fb->width, fb->height,
10060                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10061                       plane_config->size);
10062
10063         plane_config->fb = intel_fb;
10064         return;
10065
10066 error:
10067         kfree(intel_fb);
10068 }
10069
10070 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10071                                      struct intel_crtc_state *pipe_config)
10072 {
10073         struct drm_device *dev = crtc->base.dev;
10074         struct drm_i915_private *dev_priv = to_i915(dev);
10075         u32 tmp;
10076
10077         tmp = I915_READ(PF_CTL(crtc->pipe));
10078
10079         if (tmp & PF_ENABLE) {
10080                 pipe_config->pch_pfit.enabled = true;
10081                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10082                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10083
10084                 /* We currently do not free assignements of panel fitters on
10085                  * ivb/hsw (since we don't use the higher upscaling modes which
10086                  * differentiates them) so just WARN about this case for now. */
10087                 if (IS_GEN(dev_priv, 7)) {
10088                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10089                                 PF_PIPE_SEL_IVB(crtc->pipe));
10090                 }
10091         }
10092 }
10093
10094 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10095                                      struct intel_crtc_state *pipe_config)
10096 {
10097         struct drm_device *dev = crtc->base.dev;
10098         struct drm_i915_private *dev_priv = to_i915(dev);
10099         enum intel_display_power_domain power_domain;
10100         intel_wakeref_t wakeref;
10101         u32 tmp;
10102         bool ret;
10103
10104         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10105         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10106         if (!wakeref)
10107                 return false;
10108
10109         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10110         pipe_config->shared_dpll = NULL;
10111         pipe_config->master_transcoder = INVALID_TRANSCODER;
10112
10113         ret = false;
10114         tmp = I915_READ(PIPECONF(crtc->pipe));
10115         if (!(tmp & PIPECONF_ENABLE))
10116                 goto out;
10117
10118         switch (tmp & PIPECONF_BPC_MASK) {
10119         case PIPECONF_6BPC:
10120                 pipe_config->pipe_bpp = 18;
10121                 break;
10122         case PIPECONF_8BPC:
10123                 pipe_config->pipe_bpp = 24;
10124                 break;
10125         case PIPECONF_10BPC:
10126                 pipe_config->pipe_bpp = 30;
10127                 break;
10128         case PIPECONF_12BPC:
10129                 pipe_config->pipe_bpp = 36;
10130                 break;
10131         default:
10132                 break;
10133         }
10134
10135         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10136                 pipe_config->limited_color_range = true;
10137
10138         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10139         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10140         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10141                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10142                 break;
10143         default:
10144                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10145                 break;
10146         }
10147
10148         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10149                 PIPECONF_GAMMA_MODE_SHIFT;
10150
10151         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10152
10153         i9xx_get_pipe_color_config(pipe_config);
10154         intel_color_get_config(pipe_config);
10155
10156         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10157                 struct intel_shared_dpll *pll;
10158                 enum intel_dpll_id pll_id;
10159
10160                 pipe_config->has_pch_encoder = true;
10161
10162                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10163                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10164                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10165
10166                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10167
10168                 if (HAS_PCH_IBX(dev_priv)) {
10169                         /*
10170                          * The pipe->pch transcoder and pch transcoder->pll
10171                          * mapping is fixed.
10172                          */
10173                         pll_id = (enum intel_dpll_id) crtc->pipe;
10174                 } else {
10175                         tmp = I915_READ(PCH_DPLL_SEL);
10176                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10177                                 pll_id = DPLL_ID_PCH_PLL_B;
10178                         else
10179                                 pll_id= DPLL_ID_PCH_PLL_A;
10180                 }
10181
10182                 pipe_config->shared_dpll =
10183                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10184                 pll = pipe_config->shared_dpll;
10185
10186                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10187                                                 &pipe_config->dpll_hw_state));
10188
10189                 tmp = pipe_config->dpll_hw_state.dpll;
10190                 pipe_config->pixel_multiplier =
10191                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10192                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10193
10194                 ironlake_pch_clock_get(crtc, pipe_config);
10195         } else {
10196                 pipe_config->pixel_multiplier = 1;
10197         }
10198
10199         intel_get_pipe_timings(crtc, pipe_config);
10200         intel_get_pipe_src_size(crtc, pipe_config);
10201
10202         ironlake_get_pfit_config(crtc, pipe_config);
10203
10204         ret = true;
10205
10206 out:
10207         intel_display_power_put(dev_priv, power_domain, wakeref);
10208
10209         return ret;
10210 }
10211 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10212                                       struct intel_crtc_state *crtc_state)
10213 {
10214         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10215         struct intel_atomic_state *state =
10216                 to_intel_atomic_state(crtc_state->uapi.state);
10217
10218         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10219             INTEL_GEN(dev_priv) >= 11) {
10220                 struct intel_encoder *encoder =
10221                         intel_get_crtc_new_encoder(state, crtc_state);
10222
10223                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10224                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10225                                       pipe_name(crtc->pipe));
10226                         return -EINVAL;
10227                 }
10228         }
10229
10230         return 0;
10231 }
10232
10233 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10234                                    enum port port,
10235                                    struct intel_crtc_state *pipe_config)
10236 {
10237         enum intel_dpll_id id;
10238         u32 temp;
10239
10240         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10241         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10242
10243         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10244                 return;
10245
10246         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10247 }
10248
10249 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10250                                 enum port port,
10251                                 struct intel_crtc_state *pipe_config)
10252 {
10253         enum phy phy = intel_port_to_phy(dev_priv, port);
10254         enum icl_port_dpll_id port_dpll_id;
10255         enum intel_dpll_id id;
10256         u32 temp;
10257
10258         if (intel_phy_is_combo(dev_priv, phy)) {
10259                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10260                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10261                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10262                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10263         } else if (intel_phy_is_tc(dev_priv, phy)) {
10264                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10265
10266                 if (clk_sel == DDI_CLK_SEL_MG) {
10267                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10268                                                                     port));
10269                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10270                 } else {
10271                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10272                         id = DPLL_ID_ICL_TBTPLL;
10273                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10274                 }
10275         } else {
10276                 WARN(1, "Invalid port %x\n", port);
10277                 return;
10278         }
10279
10280         pipe_config->icl_port_dplls[port_dpll_id].pll =
10281                 intel_get_shared_dpll_by_id(dev_priv, id);
10282
10283         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10284 }
10285
10286 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10287                                 enum port port,
10288                                 struct intel_crtc_state *pipe_config)
10289 {
10290         enum intel_dpll_id id;
10291
10292         switch (port) {
10293         case PORT_A:
10294                 id = DPLL_ID_SKL_DPLL0;
10295                 break;
10296         case PORT_B:
10297                 id = DPLL_ID_SKL_DPLL1;
10298                 break;
10299         case PORT_C:
10300                 id = DPLL_ID_SKL_DPLL2;
10301                 break;
10302         default:
10303                 DRM_ERROR("Incorrect port type\n");
10304                 return;
10305         }
10306
10307         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10308 }
10309
10310 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10311                                 enum port port,
10312                                 struct intel_crtc_state *pipe_config)
10313 {
10314         enum intel_dpll_id id;
10315         u32 temp;
10316
10317         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10318         id = temp >> (port * 3 + 1);
10319
10320         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10321                 return;
10322
10323         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10324 }
10325
10326 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10327                                 enum port port,
10328                                 struct intel_crtc_state *pipe_config)
10329 {
10330         enum intel_dpll_id id;
10331         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10332
10333         switch (ddi_pll_sel) {
10334         case PORT_CLK_SEL_WRPLL1:
10335                 id = DPLL_ID_WRPLL1;
10336                 break;
10337         case PORT_CLK_SEL_WRPLL2:
10338                 id = DPLL_ID_WRPLL2;
10339                 break;
10340         case PORT_CLK_SEL_SPLL:
10341                 id = DPLL_ID_SPLL;
10342                 break;
10343         case PORT_CLK_SEL_LCPLL_810:
10344                 id = DPLL_ID_LCPLL_810;
10345                 break;
10346         case PORT_CLK_SEL_LCPLL_1350:
10347                 id = DPLL_ID_LCPLL_1350;
10348                 break;
10349         case PORT_CLK_SEL_LCPLL_2700:
10350                 id = DPLL_ID_LCPLL_2700;
10351                 break;
10352         default:
10353                 MISSING_CASE(ddi_pll_sel);
10354                 /* fall through */
10355         case PORT_CLK_SEL_NONE:
10356                 return;
10357         }
10358
10359         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10360 }
10361
10362 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10363                                      struct intel_crtc_state *pipe_config,
10364                                      u64 *power_domain_mask,
10365                                      intel_wakeref_t *wakerefs)
10366 {
10367         struct drm_device *dev = crtc->base.dev;
10368         struct drm_i915_private *dev_priv = to_i915(dev);
10369         enum intel_display_power_domain power_domain;
10370         unsigned long panel_transcoder_mask = 0;
10371         unsigned long enabled_panel_transcoders = 0;
10372         enum transcoder panel_transcoder;
10373         intel_wakeref_t wf;
10374         u32 tmp;
10375
10376         if (INTEL_GEN(dev_priv) >= 11)
10377                 panel_transcoder_mask |=
10378                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10379
10380         if (HAS_TRANSCODER_EDP(dev_priv))
10381                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10382
10383         /*
10384          * The pipe->transcoder mapping is fixed with the exception of the eDP
10385          * and DSI transcoders handled below.
10386          */
10387         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10388
10389         /*
10390          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10391          * consistency and less surprising code; it's in always on power).
10392          */
10393         for_each_set_bit(panel_transcoder,
10394                          &panel_transcoder_mask,
10395                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10396                 bool force_thru = false;
10397                 enum pipe trans_pipe;
10398
10399                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10400                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10401                         continue;
10402
10403                 /*
10404                  * Log all enabled ones, only use the first one.
10405                  *
10406                  * FIXME: This won't work for two separate DSI displays.
10407                  */
10408                 enabled_panel_transcoders |= BIT(panel_transcoder);
10409                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10410                         continue;
10411
10412                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10413                 default:
10414                         WARN(1, "unknown pipe linked to transcoder %s\n",
10415                              transcoder_name(panel_transcoder));
10416                         /* fall through */
10417                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10418                         force_thru = true;
10419                         /* fall through */
10420                 case TRANS_DDI_EDP_INPUT_A_ON:
10421                         trans_pipe = PIPE_A;
10422                         break;
10423                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10424                         trans_pipe = PIPE_B;
10425                         break;
10426                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10427                         trans_pipe = PIPE_C;
10428                         break;
10429                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
10430                         trans_pipe = PIPE_D;
10431                         break;
10432                 }
10433
10434                 if (trans_pipe == crtc->pipe) {
10435                         pipe_config->cpu_transcoder = panel_transcoder;
10436                         pipe_config->pch_pfit.force_thru = force_thru;
10437                 }
10438         }
10439
10440         /*
10441          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10442          */
10443         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10444                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10445
10446         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10447         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10448
10449         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10450         if (!wf)
10451                 return false;
10452
10453         wakerefs[power_domain] = wf;
10454         *power_domain_mask |= BIT_ULL(power_domain);
10455
10456         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10457
10458         return tmp & PIPECONF_ENABLE;
10459 }
10460
10461 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10462                                          struct intel_crtc_state *pipe_config,
10463                                          u64 *power_domain_mask,
10464                                          intel_wakeref_t *wakerefs)
10465 {
10466         struct drm_device *dev = crtc->base.dev;
10467         struct drm_i915_private *dev_priv = to_i915(dev);
10468         enum intel_display_power_domain power_domain;
10469         enum transcoder cpu_transcoder;
10470         intel_wakeref_t wf;
10471         enum port port;
10472         u32 tmp;
10473
10474         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10475                 if (port == PORT_A)
10476                         cpu_transcoder = TRANSCODER_DSI_A;
10477                 else
10478                         cpu_transcoder = TRANSCODER_DSI_C;
10479
10480                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10481                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10482
10483                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10484                 if (!wf)
10485                         continue;
10486
10487                 wakerefs[power_domain] = wf;
10488                 *power_domain_mask |= BIT_ULL(power_domain);
10489
10490                 /*
10491                  * The PLL needs to be enabled with a valid divider
10492                  * configuration, otherwise accessing DSI registers will hang
10493                  * the machine. See BSpec North Display Engine
10494                  * registers/MIPI[BXT]. We can break out here early, since we
10495                  * need the same DSI PLL to be enabled for both DSI ports.
10496                  */
10497                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10498                         break;
10499
10500                 /* XXX: this works for video mode only */
10501                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10502                 if (!(tmp & DPI_ENABLE))
10503                         continue;
10504
10505                 tmp = I915_READ(MIPI_CTRL(port));
10506                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10507                         continue;
10508
10509                 pipe_config->cpu_transcoder = cpu_transcoder;
10510                 break;
10511         }
10512
10513         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10514 }
10515
10516 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10517                                        struct intel_crtc_state *pipe_config)
10518 {
10519         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10520         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
10521         struct intel_shared_dpll *pll;
10522         enum port port;
10523         u32 tmp;
10524
10525         if (transcoder_is_dsi(cpu_transcoder)) {
10526                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
10527                                                 PORT_A : PORT_B;
10528         } else {
10529                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
10530                 if (INTEL_GEN(dev_priv) >= 12)
10531                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10532                 else
10533                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10534         }
10535
10536         if (INTEL_GEN(dev_priv) >= 11)
10537                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10538         else if (IS_CANNONLAKE(dev_priv))
10539                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10540         else if (IS_GEN9_BC(dev_priv))
10541                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10542         else if (IS_GEN9_LP(dev_priv))
10543                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10544         else
10545                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10546
10547         pll = pipe_config->shared_dpll;
10548         if (pll) {
10549                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10550                                                 &pipe_config->dpll_hw_state));
10551         }
10552
10553         /*
10554          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10555          * DDI E. So just check whether this pipe is wired to DDI E and whether
10556          * the PCH transcoder is on.
10557          */
10558         if (INTEL_GEN(dev_priv) < 9 &&
10559             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10560                 pipe_config->has_pch_encoder = true;
10561
10562                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10563                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10564                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10565
10566                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10567         }
10568 }
10569
10570 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10571                                                  enum transcoder cpu_transcoder)
10572 {
10573         u32 trans_port_sync, master_select;
10574
10575         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10576
10577         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10578                 return INVALID_TRANSCODER;
10579
10580         master_select = trans_port_sync &
10581                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10582         if (master_select == 0)
10583                 return TRANSCODER_EDP;
10584         else
10585                 return master_select - 1;
10586 }
10587
10588 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10589 {
10590         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10591         u32 transcoders;
10592         enum transcoder cpu_transcoder;
10593
10594         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10595                                                                   crtc_state->cpu_transcoder);
10596
10597         transcoders = BIT(TRANSCODER_A) |
10598                 BIT(TRANSCODER_B) |
10599                 BIT(TRANSCODER_C) |
10600                 BIT(TRANSCODER_D);
10601         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10602                 enum intel_display_power_domain power_domain;
10603                 intel_wakeref_t trans_wakeref;
10604
10605                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10606                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10607                                                                    power_domain);
10608
10609                 if (!trans_wakeref)
10610                         continue;
10611
10612                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10613                     crtc_state->cpu_transcoder)
10614                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10615
10616                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10617         }
10618
10619         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10620                 crtc_state->sync_mode_slaves_mask);
10621 }
10622
10623 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10624                                     struct intel_crtc_state *pipe_config)
10625 {
10626         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10627         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10628         enum intel_display_power_domain power_domain;
10629         u64 power_domain_mask;
10630         bool active;
10631
10632         pipe_config->master_transcoder = INVALID_TRANSCODER;
10633
10634         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10635         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10636         if (!wf)
10637                 return false;
10638
10639         wakerefs[power_domain] = wf;
10640         power_domain_mask = BIT_ULL(power_domain);
10641
10642         pipe_config->shared_dpll = NULL;
10643
10644         active = hsw_get_transcoder_state(crtc, pipe_config,
10645                                           &power_domain_mask, wakerefs);
10646
10647         if (IS_GEN9_LP(dev_priv) &&
10648             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10649                                          &power_domain_mask, wakerefs)) {
10650                 WARN_ON(active);
10651                 active = true;
10652         }
10653
10654         if (!active)
10655                 goto out;
10656
10657         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10658             INTEL_GEN(dev_priv) >= 11) {
10659                 haswell_get_ddi_port_state(crtc, pipe_config);
10660                 intel_get_pipe_timings(crtc, pipe_config);
10661         }
10662
10663         intel_get_pipe_src_size(crtc, pipe_config);
10664
10665         if (IS_HASWELL(dev_priv)) {
10666                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10667
10668                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10669                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10670                 else
10671                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10672         } else {
10673                 pipe_config->output_format =
10674                         bdw_get_pipemisc_output_format(crtc);
10675
10676                 /*
10677                  * Currently there is no interface defined to
10678                  * check user preference between RGB/YCBCR444
10679                  * or YCBCR420. So the only possible case for
10680                  * YCBCR444 usage is driving YCBCR420 output
10681                  * with LSPCON, when pipe is configured for
10682                  * YCBCR444 output and LSPCON takes care of
10683                  * downsampling it.
10684                  */
10685                 pipe_config->lspcon_downsampling =
10686                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10687         }
10688
10689         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10690
10691         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10692
10693         if (INTEL_GEN(dev_priv) >= 9) {
10694                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10695
10696                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10697                         pipe_config->gamma_enable = true;
10698
10699                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10700                         pipe_config->csc_enable = true;
10701         } else {
10702                 i9xx_get_pipe_color_config(pipe_config);
10703         }
10704
10705         intel_color_get_config(pipe_config);
10706
10707         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10708         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10709
10710         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10711         if (wf) {
10712                 wakerefs[power_domain] = wf;
10713                 power_domain_mask |= BIT_ULL(power_domain);
10714
10715                 if (INTEL_GEN(dev_priv) >= 9)
10716                         skylake_get_pfit_config(crtc, pipe_config);
10717                 else
10718                         ironlake_get_pfit_config(crtc, pipe_config);
10719         }
10720
10721         if (hsw_crtc_supports_ips(crtc)) {
10722                 if (IS_HASWELL(dev_priv))
10723                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10724                 else {
10725                         /*
10726                          * We cannot readout IPS state on broadwell, set to
10727                          * true so we can set it to a defined state on first
10728                          * commit.
10729                          */
10730                         pipe_config->ips_enabled = true;
10731                 }
10732         }
10733
10734         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10735             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10736                 pipe_config->pixel_multiplier =
10737                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10738         } else {
10739                 pipe_config->pixel_multiplier = 1;
10740         }
10741
10742         if (INTEL_GEN(dev_priv) >= 11 &&
10743             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10744                 icelake_get_trans_port_sync_config(pipe_config);
10745
10746 out:
10747         for_each_power_domain(power_domain, power_domain_mask)
10748                 intel_display_power_put(dev_priv,
10749                                         power_domain, wakerefs[power_domain]);
10750
10751         return active;
10752 }
10753
10754 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10755 {
10756         struct drm_i915_private *dev_priv =
10757                 to_i915(plane_state->uapi.plane->dev);
10758         const struct drm_framebuffer *fb = plane_state->hw.fb;
10759         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10760         u32 base;
10761
10762         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10763                 base = obj->phys_handle->busaddr;
10764         else
10765                 base = intel_plane_ggtt_offset(plane_state);
10766
10767         return base + plane_state->color_plane[0].offset;
10768 }
10769
10770 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10771 {
10772         int x = plane_state->uapi.dst.x1;
10773         int y = plane_state->uapi.dst.y1;
10774         u32 pos = 0;
10775
10776         if (x < 0) {
10777                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10778                 x = -x;
10779         }
10780         pos |= x << CURSOR_X_SHIFT;
10781
10782         if (y < 0) {
10783                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10784                 y = -y;
10785         }
10786         pos |= y << CURSOR_Y_SHIFT;
10787
10788         return pos;
10789 }
10790
10791 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10792 {
10793         const struct drm_mode_config *config =
10794                 &plane_state->uapi.plane->dev->mode_config;
10795         int width = drm_rect_width(&plane_state->uapi.dst);
10796         int height = drm_rect_height(&plane_state->uapi.dst);
10797
10798         return width > 0 && width <= config->cursor_width &&
10799                 height > 0 && height <= config->cursor_height;
10800 }
10801
10802 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10803 {
10804         struct drm_i915_private *dev_priv =
10805                 to_i915(plane_state->uapi.plane->dev);
10806         unsigned int rotation = plane_state->hw.rotation;
10807         int src_x, src_y;
10808         u32 offset;
10809         int ret;
10810
10811         ret = intel_plane_compute_gtt(plane_state);
10812         if (ret)
10813                 return ret;
10814
10815         if (!plane_state->uapi.visible)
10816                 return 0;
10817
10818         src_x = plane_state->uapi.src.x1 >> 16;
10819         src_y = plane_state->uapi.src.y1 >> 16;
10820
10821         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10822         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10823                                                     plane_state, 0);
10824
10825         if (src_x != 0 || src_y != 0) {
10826                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10827                 return -EINVAL;
10828         }
10829
10830         /*
10831          * Put the final coordinates back so that the src
10832          * coordinate checks will see the right values.
10833          */
10834         drm_rect_translate_to(&plane_state->uapi.src,
10835                               src_x << 16, src_y << 16);
10836
10837         /* ILK+ do this automagically in hardware */
10838         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10839                 const struct drm_framebuffer *fb = plane_state->hw.fb;
10840                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10841                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10842
10843                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10844         }
10845
10846         plane_state->color_plane[0].offset = offset;
10847         plane_state->color_plane[0].x = src_x;
10848         plane_state->color_plane[0].y = src_y;
10849
10850         return 0;
10851 }
10852
10853 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10854                               struct intel_plane_state *plane_state)
10855 {
10856         const struct drm_framebuffer *fb = plane_state->hw.fb;
10857         int ret;
10858
10859         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10860                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10861                 return -EINVAL;
10862         }
10863
10864         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10865                                                   &crtc_state->uapi,
10866                                                   DRM_PLANE_HELPER_NO_SCALING,
10867                                                   DRM_PLANE_HELPER_NO_SCALING,
10868                                                   true, true);
10869         if (ret)
10870                 return ret;
10871
10872         /* Use the unclipped src/dst rectangles, which we program to hw */
10873         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10874         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10875
10876         ret = intel_cursor_check_surface(plane_state);
10877         if (ret)
10878                 return ret;
10879
10880         if (!plane_state->uapi.visible)
10881                 return 0;
10882
10883         ret = intel_plane_check_src_coordinates(plane_state);
10884         if (ret)
10885                 return ret;
10886
10887         return 0;
10888 }
10889
10890 static unsigned int
10891 i845_cursor_max_stride(struct intel_plane *plane,
10892                        u32 pixel_format, u64 modifier,
10893                        unsigned int rotation)
10894 {
10895         return 2048;
10896 }
10897
10898 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10899 {
10900         u32 cntl = 0;
10901
10902         if (crtc_state->gamma_enable)
10903                 cntl |= CURSOR_GAMMA_ENABLE;
10904
10905         return cntl;
10906 }
10907
10908 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10909                            const struct intel_plane_state *plane_state)
10910 {
10911         return CURSOR_ENABLE |
10912                 CURSOR_FORMAT_ARGB |
10913                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10914 }
10915
10916 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10917 {
10918         int width = drm_rect_width(&plane_state->uapi.dst);
10919
10920         /*
10921          * 845g/865g are only limited by the width of their cursors,
10922          * the height is arbitrary up to the precision of the register.
10923          */
10924         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10925 }
10926
10927 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10928                              struct intel_plane_state *plane_state)
10929 {
10930         const struct drm_framebuffer *fb = plane_state->hw.fb;
10931         int ret;
10932
10933         ret = intel_check_cursor(crtc_state, plane_state);
10934         if (ret)
10935                 return ret;
10936
10937         /* if we want to turn off the cursor ignore width and height */
10938         if (!fb)
10939                 return 0;
10940
10941         /* Check for which cursor types we support */
10942         if (!i845_cursor_size_ok(plane_state)) {
10943                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10944                           drm_rect_width(&plane_state->uapi.dst),
10945                           drm_rect_height(&plane_state->uapi.dst));
10946                 return -EINVAL;
10947         }
10948
10949         WARN_ON(plane_state->uapi.visible &&
10950                 plane_state->color_plane[0].stride != fb->pitches[0]);
10951
10952         switch (fb->pitches[0]) {
10953         case 256:
10954         case 512:
10955         case 1024:
10956         case 2048:
10957                 break;
10958         default:
10959                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10960                               fb->pitches[0]);
10961                 return -EINVAL;
10962         }
10963
10964         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10965
10966         return 0;
10967 }
10968
10969 static void i845_update_cursor(struct intel_plane *plane,
10970                                const struct intel_crtc_state *crtc_state,
10971                                const struct intel_plane_state *plane_state)
10972 {
10973         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10974         u32 cntl = 0, base = 0, pos = 0, size = 0;
10975         unsigned long irqflags;
10976
10977         if (plane_state && plane_state->uapi.visible) {
10978                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
10979                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
10980
10981                 cntl = plane_state->ctl |
10982                         i845_cursor_ctl_crtc(crtc_state);
10983
10984                 size = (height << 12) | width;
10985
10986                 base = intel_cursor_base(plane_state);
10987                 pos = intel_cursor_position(plane_state);
10988         }
10989
10990         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10991
10992         /* On these chipsets we can only modify the base/size/stride
10993          * whilst the cursor is disabled.
10994          */
10995         if (plane->cursor.base != base ||
10996             plane->cursor.size != size ||
10997             plane->cursor.cntl != cntl) {
10998                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10999                 I915_WRITE_FW(CURBASE(PIPE_A), base);
11000                 I915_WRITE_FW(CURSIZE, size);
11001                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11002                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11003
11004                 plane->cursor.base = base;
11005                 plane->cursor.size = size;
11006                 plane->cursor.cntl = cntl;
11007         } else {
11008                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11009         }
11010
11011         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11012 }
11013
11014 static void i845_disable_cursor(struct intel_plane *plane,
11015                                 const struct intel_crtc_state *crtc_state)
11016 {
11017         i845_update_cursor(plane, crtc_state, NULL);
11018 }
11019
11020 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11021                                      enum pipe *pipe)
11022 {
11023         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11024         enum intel_display_power_domain power_domain;
11025         intel_wakeref_t wakeref;
11026         bool ret;
11027
11028         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11029         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11030         if (!wakeref)
11031                 return false;
11032
11033         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11034
11035         *pipe = PIPE_A;
11036
11037         intel_display_power_put(dev_priv, power_domain, wakeref);
11038
11039         return ret;
11040 }
11041
11042 static unsigned int
11043 i9xx_cursor_max_stride(struct intel_plane *plane,
11044                        u32 pixel_format, u64 modifier,
11045                        unsigned int rotation)
11046 {
11047         return plane->base.dev->mode_config.cursor_width * 4;
11048 }
11049
11050 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11051 {
11052         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11053         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11054         u32 cntl = 0;
11055
11056         if (INTEL_GEN(dev_priv) >= 11)
11057                 return cntl;
11058
11059         if (crtc_state->gamma_enable)
11060                 cntl = MCURSOR_GAMMA_ENABLE;
11061
11062         if (crtc_state->csc_enable)
11063                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11064
11065         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11066                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11067
11068         return cntl;
11069 }
11070
11071 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11072                            const struct intel_plane_state *plane_state)
11073 {
11074         struct drm_i915_private *dev_priv =
11075                 to_i915(plane_state->uapi.plane->dev);
11076         u32 cntl = 0;
11077
11078         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11079                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11080
11081         switch (drm_rect_width(&plane_state->uapi.dst)) {
11082         case 64:
11083                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11084                 break;
11085         case 128:
11086                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11087                 break;
11088         case 256:
11089                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11090                 break;
11091         default:
11092                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11093                 return 0;
11094         }
11095
11096         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11097                 cntl |= MCURSOR_ROTATE_180;
11098
11099         return cntl;
11100 }
11101
11102 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11103 {
11104         struct drm_i915_private *dev_priv =
11105                 to_i915(plane_state->uapi.plane->dev);
11106         int width = drm_rect_width(&plane_state->uapi.dst);
11107         int height = drm_rect_height(&plane_state->uapi.dst);
11108
11109         if (!intel_cursor_size_ok(plane_state))
11110                 return false;
11111
11112         /* Cursor width is limited to a few power-of-two sizes */
11113         switch (width) {
11114         case 256:
11115         case 128:
11116         case 64:
11117                 break;
11118         default:
11119                 return false;
11120         }
11121
11122         /*
11123          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11124          * height from 8 lines up to the cursor width, when the
11125          * cursor is not rotated. Everything else requires square
11126          * cursors.
11127          */
11128         if (HAS_CUR_FBC(dev_priv) &&
11129             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11130                 if (height < 8 || height > width)
11131                         return false;
11132         } else {
11133                 if (height != width)
11134                         return false;
11135         }
11136
11137         return true;
11138 }
11139
11140 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11141                              struct intel_plane_state *plane_state)
11142 {
11143         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11144         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11145         const struct drm_framebuffer *fb = plane_state->hw.fb;
11146         enum pipe pipe = plane->pipe;
11147         int ret;
11148
11149         ret = intel_check_cursor(crtc_state, plane_state);
11150         if (ret)
11151                 return ret;
11152
11153         /* if we want to turn off the cursor ignore width and height */
11154         if (!fb)
11155                 return 0;
11156
11157         /* Check for which cursor types we support */
11158         if (!i9xx_cursor_size_ok(plane_state)) {
11159                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11160                           drm_rect_width(&plane_state->uapi.dst),
11161                           drm_rect_height(&plane_state->uapi.dst));
11162                 return -EINVAL;
11163         }
11164
11165         WARN_ON(plane_state->uapi.visible &&
11166                 plane_state->color_plane[0].stride != fb->pitches[0]);
11167
11168         if (fb->pitches[0] !=
11169             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11170                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11171                               fb->pitches[0],
11172                               drm_rect_width(&plane_state->uapi.dst));
11173                 return -EINVAL;
11174         }
11175
11176         /*
11177          * There's something wrong with the cursor on CHV pipe C.
11178          * If it straddles the left edge of the screen then
11179          * moving it away from the edge or disabling it often
11180          * results in a pipe underrun, and often that can lead to
11181          * dead pipe (constant underrun reported, and it scans
11182          * out just a solid color). To recover from that, the
11183          * display power well must be turned off and on again.
11184          * Refuse the put the cursor into that compromised position.
11185          */
11186         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11187             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11188                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11189                 return -EINVAL;
11190         }
11191
11192         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11193
11194         return 0;
11195 }
11196
11197 static void i9xx_update_cursor(struct intel_plane *plane,
11198                                const struct intel_crtc_state *crtc_state,
11199                                const struct intel_plane_state *plane_state)
11200 {
11201         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11202         enum pipe pipe = plane->pipe;
11203         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11204         unsigned long irqflags;
11205
11206         if (plane_state && plane_state->uapi.visible) {
11207                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11208                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11209
11210                 cntl = plane_state->ctl |
11211                         i9xx_cursor_ctl_crtc(crtc_state);
11212
11213                 if (width != height)
11214                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11215
11216                 base = intel_cursor_base(plane_state);
11217                 pos = intel_cursor_position(plane_state);
11218         }
11219
11220         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11221
11222         /*
11223          * On some platforms writing CURCNTR first will also
11224          * cause CURPOS to be armed by the CURBASE write.
11225          * Without the CURCNTR write the CURPOS write would
11226          * arm itself. Thus we always update CURCNTR before
11227          * CURPOS.
11228          *
11229          * On other platforms CURPOS always requires the
11230          * CURBASE write to arm the update. Additonally
11231          * a write to any of the cursor register will cancel
11232          * an already armed cursor update. Thus leaving out
11233          * the CURBASE write after CURPOS could lead to a
11234          * cursor that doesn't appear to move, or even change
11235          * shape. Thus we always write CURBASE.
11236          *
11237          * The other registers are armed by by the CURBASE write
11238          * except when the plane is getting enabled at which time
11239          * the CURCNTR write arms the update.
11240          */
11241
11242         if (INTEL_GEN(dev_priv) >= 9)
11243                 skl_write_cursor_wm(plane, crtc_state);
11244
11245         if (plane->cursor.base != base ||
11246             plane->cursor.size != fbc_ctl ||
11247             plane->cursor.cntl != cntl) {
11248                 if (HAS_CUR_FBC(dev_priv))
11249                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11250                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11251                 I915_WRITE_FW(CURPOS(pipe), pos);
11252                 I915_WRITE_FW(CURBASE(pipe), base);
11253
11254                 plane->cursor.base = base;
11255                 plane->cursor.size = fbc_ctl;
11256                 plane->cursor.cntl = cntl;
11257         } else {
11258                 I915_WRITE_FW(CURPOS(pipe), pos);
11259                 I915_WRITE_FW(CURBASE(pipe), base);
11260         }
11261
11262         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11263 }
11264
11265 static void i9xx_disable_cursor(struct intel_plane *plane,
11266                                 const struct intel_crtc_state *crtc_state)
11267 {
11268         i9xx_update_cursor(plane, crtc_state, NULL);
11269 }
11270
11271 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11272                                      enum pipe *pipe)
11273 {
11274         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11275         enum intel_display_power_domain power_domain;
11276         intel_wakeref_t wakeref;
11277         bool ret;
11278         u32 val;
11279
11280         /*
11281          * Not 100% correct for planes that can move between pipes,
11282          * but that's only the case for gen2-3 which don't have any
11283          * display power wells.
11284          */
11285         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11286         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11287         if (!wakeref)
11288                 return false;
11289
11290         val = I915_READ(CURCNTR(plane->pipe));
11291
11292         ret = val & MCURSOR_MODE;
11293
11294         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11295                 *pipe = plane->pipe;
11296         else
11297                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11298                         MCURSOR_PIPE_SELECT_SHIFT;
11299
11300         intel_display_power_put(dev_priv, power_domain, wakeref);
11301
11302         return ret;
11303 }
11304
11305 /* VESA 640x480x72Hz mode to set on the pipe */
11306 static const struct drm_display_mode load_detect_mode = {
11307         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11308                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11309 };
11310
11311 struct drm_framebuffer *
11312 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11313                          struct drm_mode_fb_cmd2 *mode_cmd)
11314 {
11315         struct intel_framebuffer *intel_fb;
11316         int ret;
11317
11318         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11319         if (!intel_fb)
11320                 return ERR_PTR(-ENOMEM);
11321
11322         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11323         if (ret)
11324                 goto err;
11325
11326         return &intel_fb->base;
11327
11328 err:
11329         kfree(intel_fb);
11330         return ERR_PTR(ret);
11331 }
11332
11333 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11334                                         struct drm_crtc *crtc)
11335 {
11336         struct drm_plane *plane;
11337         struct drm_plane_state *plane_state;
11338         int ret, i;
11339
11340         ret = drm_atomic_add_affected_planes(state, crtc);
11341         if (ret)
11342                 return ret;
11343
11344         for_each_new_plane_in_state(state, plane, plane_state, i) {
11345                 if (plane_state->crtc != crtc)
11346                         continue;
11347
11348                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11349                 if (ret)
11350                         return ret;
11351
11352                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11353         }
11354
11355         return 0;
11356 }
11357
11358 int intel_get_load_detect_pipe(struct drm_connector *connector,
11359                                struct intel_load_detect_pipe *old,
11360                                struct drm_modeset_acquire_ctx *ctx)
11361 {
11362         struct intel_crtc *intel_crtc;
11363         struct intel_encoder *intel_encoder =
11364                 intel_attached_encoder(connector);
11365         struct drm_crtc *possible_crtc;
11366         struct drm_encoder *encoder = &intel_encoder->base;
11367         struct drm_crtc *crtc = NULL;
11368         struct drm_device *dev = encoder->dev;
11369         struct drm_i915_private *dev_priv = to_i915(dev);
11370         struct drm_mode_config *config = &dev->mode_config;
11371         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11372         struct drm_connector_state *connector_state;
11373         struct intel_crtc_state *crtc_state;
11374         int ret, i = -1;
11375
11376         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11377                       connector->base.id, connector->name,
11378                       encoder->base.id, encoder->name);
11379
11380         old->restore_state = NULL;
11381
11382         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11383
11384         /*
11385          * Algorithm gets a little messy:
11386          *
11387          *   - if the connector already has an assigned crtc, use it (but make
11388          *     sure it's on first)
11389          *
11390          *   - try to find the first unused crtc that can drive this connector,
11391          *     and use that if we find one
11392          */
11393
11394         /* See if we already have a CRTC for this connector */
11395         if (connector->state->crtc) {
11396                 crtc = connector->state->crtc;
11397
11398                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11399                 if (ret)
11400                         goto fail;
11401
11402                 /* Make sure the crtc and connector are running */
11403                 goto found;
11404         }
11405
11406         /* Find an unused one (if possible) */
11407         for_each_crtc(dev, possible_crtc) {
11408                 i++;
11409                 if (!(encoder->possible_crtcs & (1 << i)))
11410                         continue;
11411
11412                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11413                 if (ret)
11414                         goto fail;
11415
11416                 if (possible_crtc->state->enable) {
11417                         drm_modeset_unlock(&possible_crtc->mutex);
11418                         continue;
11419                 }
11420
11421                 crtc = possible_crtc;
11422                 break;
11423         }
11424
11425         /*
11426          * If we didn't find an unused CRTC, don't use any.
11427          */
11428         if (!crtc) {
11429                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11430                 ret = -ENODEV;
11431                 goto fail;
11432         }
11433
11434 found:
11435         intel_crtc = to_intel_crtc(crtc);
11436
11437         state = drm_atomic_state_alloc(dev);
11438         restore_state = drm_atomic_state_alloc(dev);
11439         if (!state || !restore_state) {
11440                 ret = -ENOMEM;
11441                 goto fail;
11442         }
11443
11444         state->acquire_ctx = ctx;
11445         restore_state->acquire_ctx = ctx;
11446
11447         connector_state = drm_atomic_get_connector_state(state, connector);
11448         if (IS_ERR(connector_state)) {
11449                 ret = PTR_ERR(connector_state);
11450                 goto fail;
11451         }
11452
11453         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11454         if (ret)
11455                 goto fail;
11456
11457         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11458         if (IS_ERR(crtc_state)) {
11459                 ret = PTR_ERR(crtc_state);
11460                 goto fail;
11461         }
11462
11463         crtc_state->uapi.active = true;
11464
11465         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11466                                            &load_detect_mode);
11467         if (ret)
11468                 goto fail;
11469
11470         ret = intel_modeset_disable_planes(state, crtc);
11471         if (ret)
11472                 goto fail;
11473
11474         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11475         if (!ret)
11476                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11477         if (!ret)
11478                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11479         if (ret) {
11480                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11481                 goto fail;
11482         }
11483
11484         ret = drm_atomic_commit(state);
11485         if (ret) {
11486                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11487                 goto fail;
11488         }
11489
11490         old->restore_state = restore_state;
11491         drm_atomic_state_put(state);
11492
11493         /* let the connector get through one full cycle before testing */
11494         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11495         return true;
11496
11497 fail:
11498         if (state) {
11499                 drm_atomic_state_put(state);
11500                 state = NULL;
11501         }
11502         if (restore_state) {
11503                 drm_atomic_state_put(restore_state);
11504                 restore_state = NULL;
11505         }
11506
11507         if (ret == -EDEADLK)
11508                 return ret;
11509
11510         return false;
11511 }
11512
11513 void intel_release_load_detect_pipe(struct drm_connector *connector,
11514                                     struct intel_load_detect_pipe *old,
11515                                     struct drm_modeset_acquire_ctx *ctx)
11516 {
11517         struct intel_encoder *intel_encoder =
11518                 intel_attached_encoder(connector);
11519         struct drm_encoder *encoder = &intel_encoder->base;
11520         struct drm_atomic_state *state = old->restore_state;
11521         int ret;
11522
11523         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11524                       connector->base.id, connector->name,
11525                       encoder->base.id, encoder->name);
11526
11527         if (!state)
11528                 return;
11529
11530         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11531         if (ret)
11532                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11533         drm_atomic_state_put(state);
11534 }
11535
11536 static int i9xx_pll_refclk(struct drm_device *dev,
11537                            const struct intel_crtc_state *pipe_config)
11538 {
11539         struct drm_i915_private *dev_priv = to_i915(dev);
11540         u32 dpll = pipe_config->dpll_hw_state.dpll;
11541
11542         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11543                 return dev_priv->vbt.lvds_ssc_freq;
11544         else if (HAS_PCH_SPLIT(dev_priv))
11545                 return 120000;
11546         else if (!IS_GEN(dev_priv, 2))
11547                 return 96000;
11548         else
11549                 return 48000;
11550 }
11551
11552 /* Returns the clock of the currently programmed mode of the given pipe. */
11553 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11554                                 struct intel_crtc_state *pipe_config)
11555 {
11556         struct drm_device *dev = crtc->base.dev;
11557         struct drm_i915_private *dev_priv = to_i915(dev);
11558         enum pipe pipe = crtc->pipe;
11559         u32 dpll = pipe_config->dpll_hw_state.dpll;
11560         u32 fp;
11561         struct dpll clock;
11562         int port_clock;
11563         int refclk = i9xx_pll_refclk(dev, pipe_config);
11564
11565         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11566                 fp = pipe_config->dpll_hw_state.fp0;
11567         else
11568                 fp = pipe_config->dpll_hw_state.fp1;
11569
11570         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11571         if (IS_PINEVIEW(dev_priv)) {
11572                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11573                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11574         } else {
11575                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11576                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11577         }
11578
11579         if (!IS_GEN(dev_priv, 2)) {
11580                 if (IS_PINEVIEW(dev_priv))
11581                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11582                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11583                 else
11584                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11585                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11586
11587                 switch (dpll & DPLL_MODE_MASK) {
11588                 case DPLLB_MODE_DAC_SERIAL:
11589                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11590                                 5 : 10;
11591                         break;
11592                 case DPLLB_MODE_LVDS:
11593                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11594                                 7 : 14;
11595                         break;
11596                 default:
11597                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11598                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11599                         return;
11600                 }
11601
11602                 if (IS_PINEVIEW(dev_priv))
11603                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11604                 else
11605                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11606         } else {
11607                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11608                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11609
11610                 if (is_lvds) {
11611                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11612                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11613
11614                         if (lvds & LVDS_CLKB_POWER_UP)
11615                                 clock.p2 = 7;
11616                         else
11617                                 clock.p2 = 14;
11618                 } else {
11619                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11620                                 clock.p1 = 2;
11621                         else {
11622                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11623                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11624                         }
11625                         if (dpll & PLL_P2_DIVIDE_BY_4)
11626                                 clock.p2 = 4;
11627                         else
11628                                 clock.p2 = 2;
11629                 }
11630
11631                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11632         }
11633
11634         /*
11635          * This value includes pixel_multiplier. We will use
11636          * port_clock to compute adjusted_mode.crtc_clock in the
11637          * encoder's get_config() function.
11638          */
11639         pipe_config->port_clock = port_clock;
11640 }
11641
11642 int intel_dotclock_calculate(int link_freq,
11643                              const struct intel_link_m_n *m_n)
11644 {
11645         /*
11646          * The calculation for the data clock is:
11647          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11648          * But we want to avoid losing precison if possible, so:
11649          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11650          *
11651          * and the link clock is simpler:
11652          * link_clock = (m * link_clock) / n
11653          */
11654
11655         if (!m_n->link_n)
11656                 return 0;
11657
11658         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11659 }
11660
11661 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11662                                    struct intel_crtc_state *pipe_config)
11663 {
11664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11665
11666         /* read out port_clock from the DPLL */
11667         i9xx_crtc_clock_get(crtc, pipe_config);
11668
11669         /*
11670          * In case there is an active pipe without active ports,
11671          * we may need some idea for the dotclock anyway.
11672          * Calculate one based on the FDI configuration.
11673          */
11674         pipe_config->hw.adjusted_mode.crtc_clock =
11675                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11676                                          &pipe_config->fdi_m_n);
11677 }
11678
11679 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
11680                                    struct intel_crtc *crtc)
11681 {
11682         memset(crtc_state, 0, sizeof(*crtc_state));
11683
11684         __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
11685
11686         crtc_state->cpu_transcoder = INVALID_TRANSCODER;
11687         crtc_state->master_transcoder = INVALID_TRANSCODER;
11688         crtc_state->hsw_workaround_pipe = INVALID_PIPE;
11689         crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
11690         crtc_state->scaler_state.scaler_id = -1;
11691 }
11692
11693 /* Returns the currently programmed mode of the given encoder. */
11694 struct drm_display_mode *
11695 intel_encoder_current_mode(struct intel_encoder *encoder)
11696 {
11697         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11698         struct intel_crtc_state *crtc_state;
11699         struct drm_display_mode *mode;
11700         struct intel_crtc *crtc;
11701         enum pipe pipe;
11702
11703         if (!encoder->get_hw_state(encoder, &pipe))
11704                 return NULL;
11705
11706         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11707
11708         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11709         if (!mode)
11710                 return NULL;
11711
11712         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11713         if (!crtc_state) {
11714                 kfree(mode);
11715                 return NULL;
11716         }
11717
11718         intel_crtc_state_reset(crtc_state, crtc);
11719
11720         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11721                 kfree(crtc_state);
11722                 kfree(mode);
11723                 return NULL;
11724         }
11725
11726         encoder->get_config(encoder, crtc_state);
11727
11728         intel_mode_from_pipe_config(mode, crtc_state);
11729
11730         kfree(crtc_state);
11731
11732         return mode;
11733 }
11734
11735 static void intel_crtc_destroy(struct drm_crtc *crtc)
11736 {
11737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11738
11739         drm_crtc_cleanup(crtc);
11740         kfree(intel_crtc);
11741 }
11742
11743 /**
11744  * intel_wm_need_update - Check whether watermarks need updating
11745  * @cur: current plane state
11746  * @new: new plane state
11747  *
11748  * Check current plane state versus the new one to determine whether
11749  * watermarks need to be recalculated.
11750  *
11751  * Returns true or false.
11752  */
11753 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11754                                  struct intel_plane_state *new)
11755 {
11756         /* Update watermarks on tiling or size changes. */
11757         if (new->uapi.visible != cur->uapi.visible)
11758                 return true;
11759
11760         if (!cur->hw.fb || !new->hw.fb)
11761                 return false;
11762
11763         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11764             cur->hw.rotation != new->hw.rotation ||
11765             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11766             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11767             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11768             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11769                 return true;
11770
11771         return false;
11772 }
11773
11774 static bool needs_scaling(const struct intel_plane_state *state)
11775 {
11776         int src_w = drm_rect_width(&state->uapi.src) >> 16;
11777         int src_h = drm_rect_height(&state->uapi.src) >> 16;
11778         int dst_w = drm_rect_width(&state->uapi.dst);
11779         int dst_h = drm_rect_height(&state->uapi.dst);
11780
11781         return (src_w != dst_w || src_h != dst_h);
11782 }
11783
11784 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11785                                     struct intel_crtc_state *crtc_state,
11786                                     const struct intel_plane_state *old_plane_state,
11787                                     struct intel_plane_state *plane_state)
11788 {
11789         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11790         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11791         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11792         bool mode_changed = needs_modeset(crtc_state);
11793         bool was_crtc_enabled = old_crtc_state->hw.active;
11794         bool is_crtc_enabled = crtc_state->hw.active;
11795         bool turn_off, turn_on, visible, was_visible;
11796         int ret;
11797
11798         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11799                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11800                 if (ret)
11801                         return ret;
11802         }
11803
11804         was_visible = old_plane_state->uapi.visible;
11805         visible = plane_state->uapi.visible;
11806
11807         if (!was_crtc_enabled && WARN_ON(was_visible))
11808                 was_visible = false;
11809
11810         /*
11811          * Visibility is calculated as if the crtc was on, but
11812          * after scaler setup everything depends on it being off
11813          * when the crtc isn't active.
11814          *
11815          * FIXME this is wrong for watermarks. Watermarks should also
11816          * be computed as if the pipe would be active. Perhaps move
11817          * per-plane wm computation to the .check_plane() hook, and
11818          * only combine the results from all planes in the current place?
11819          */
11820         if (!is_crtc_enabled) {
11821                 plane_state->uapi.visible = visible = false;
11822                 crtc_state->active_planes &= ~BIT(plane->id);
11823                 crtc_state->data_rate[plane->id] = 0;
11824                 crtc_state->min_cdclk[plane->id] = 0;
11825         }
11826
11827         if (!was_visible && !visible)
11828                 return 0;
11829
11830         turn_off = was_visible && (!visible || mode_changed);
11831         turn_on = visible && (!was_visible || mode_changed);
11832
11833         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11834                          crtc->base.base.id, crtc->base.name,
11835                          plane->base.base.id, plane->base.name,
11836                          was_visible, visible,
11837                          turn_off, turn_on, mode_changed);
11838
11839         if (turn_on) {
11840                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11841                         crtc_state->update_wm_pre = true;
11842
11843                 /* must disable cxsr around plane enable/disable */
11844                 if (plane->id != PLANE_CURSOR)
11845                         crtc_state->disable_cxsr = true;
11846         } else if (turn_off) {
11847                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11848                         crtc_state->update_wm_post = true;
11849
11850                 /* must disable cxsr around plane enable/disable */
11851                 if (plane->id != PLANE_CURSOR)
11852                         crtc_state->disable_cxsr = true;
11853         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11854                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11855                         /* FIXME bollocks */
11856                         crtc_state->update_wm_pre = true;
11857                         crtc_state->update_wm_post = true;
11858                 }
11859         }
11860
11861         if (visible || was_visible)
11862                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11863
11864         /*
11865          * ILK/SNB DVSACNTR/Sprite Enable
11866          * IVB SPR_CTL/Sprite Enable
11867          * "When in Self Refresh Big FIFO mode, a write to enable the
11868          *  plane will be internally buffered and delayed while Big FIFO
11869          *  mode is exiting."
11870          *
11871          * Which means that enabling the sprite can take an extra frame
11872          * when we start in big FIFO mode (LP1+). Thus we need to drop
11873          * down to LP0 and wait for vblank in order to make sure the
11874          * sprite gets enabled on the next vblank after the register write.
11875          * Doing otherwise would risk enabling the sprite one frame after
11876          * we've already signalled flip completion. We can resume LP1+
11877          * once the sprite has been enabled.
11878          *
11879          *
11880          * WaCxSRDisabledForSpriteScaling:ivb
11881          * IVB SPR_SCALE/Scaling Enable
11882          * "Low Power watermarks must be disabled for at least one
11883          *  frame before enabling sprite scaling, and kept disabled
11884          *  until sprite scaling is disabled."
11885          *
11886          * ILK/SNB DVSASCALE/Scaling Enable
11887          * "When in Self Refresh Big FIFO mode, scaling enable will be
11888          *  masked off while Big FIFO mode is exiting."
11889          *
11890          * Despite the w/a only being listed for IVB we assume that
11891          * the ILK/SNB note has similar ramifications, hence we apply
11892          * the w/a on all three platforms.
11893          *
11894          * With experimental results seems this is needed also for primary
11895          * plane, not only sprite plane.
11896          */
11897         if (plane->id != PLANE_CURSOR &&
11898             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11899              IS_IVYBRIDGE(dev_priv)) &&
11900             (turn_on || (!needs_scaling(old_plane_state) &&
11901                          needs_scaling(plane_state))))
11902                 crtc_state->disable_lp_wm = true;
11903
11904         return 0;
11905 }
11906
11907 static bool encoders_cloneable(const struct intel_encoder *a,
11908                                const struct intel_encoder *b)
11909 {
11910         /* masks could be asymmetric, so check both ways */
11911         return a == b || (a->cloneable & (1 << b->type) &&
11912                           b->cloneable & (1 << a->type));
11913 }
11914
11915 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11916                                          struct intel_crtc *crtc,
11917                                          struct intel_encoder *encoder)
11918 {
11919         struct intel_encoder *source_encoder;
11920         struct drm_connector *connector;
11921         struct drm_connector_state *connector_state;
11922         int i;
11923
11924         for_each_new_connector_in_state(state, connector, connector_state, i) {
11925                 if (connector_state->crtc != &crtc->base)
11926                         continue;
11927
11928                 source_encoder =
11929                         to_intel_encoder(connector_state->best_encoder);
11930                 if (!encoders_cloneable(encoder, source_encoder))
11931                         return false;
11932         }
11933
11934         return true;
11935 }
11936
11937 static int icl_add_linked_planes(struct intel_atomic_state *state)
11938 {
11939         struct intel_plane *plane, *linked;
11940         struct intel_plane_state *plane_state, *linked_plane_state;
11941         int i;
11942
11943         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11944                 linked = plane_state->planar_linked_plane;
11945
11946                 if (!linked)
11947                         continue;
11948
11949                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11950                 if (IS_ERR(linked_plane_state))
11951                         return PTR_ERR(linked_plane_state);
11952
11953                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11954                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11955         }
11956
11957         return 0;
11958 }
11959
11960 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11961 {
11962         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11963         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11964         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
11965         struct intel_plane *plane, *linked;
11966         struct intel_plane_state *plane_state;
11967         int i;
11968
11969         if (INTEL_GEN(dev_priv) < 11)
11970                 return 0;
11971
11972         /*
11973          * Destroy all old plane links and make the slave plane invisible
11974          * in the crtc_state->active_planes mask.
11975          */
11976         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11977                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
11978                         continue;
11979
11980                 plane_state->planar_linked_plane = NULL;
11981                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
11982                         crtc_state->active_planes &= ~BIT(plane->id);
11983                         crtc_state->update_planes |= BIT(plane->id);
11984                 }
11985
11986                 plane_state->planar_slave = false;
11987         }
11988
11989         if (!crtc_state->nv12_planes)
11990                 return 0;
11991
11992         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11993                 struct intel_plane_state *linked_state = NULL;
11994
11995                 if (plane->pipe != crtc->pipe ||
11996                     !(crtc_state->nv12_planes & BIT(plane->id)))
11997                         continue;
11998
11999                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12000                         if (!icl_is_nv12_y_plane(linked->id))
12001                                 continue;
12002
12003                         if (crtc_state->active_planes & BIT(linked->id))
12004                                 continue;
12005
12006                         linked_state = intel_atomic_get_plane_state(state, linked);
12007                         if (IS_ERR(linked_state))
12008                                 return PTR_ERR(linked_state);
12009
12010                         break;
12011                 }
12012
12013                 if (!linked_state) {
12014                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
12015                                       hweight8(crtc_state->nv12_planes));
12016
12017                         return -EINVAL;
12018                 }
12019
12020                 plane_state->planar_linked_plane = linked;
12021
12022                 linked_state->planar_slave = true;
12023                 linked_state->planar_linked_plane = plane;
12024                 crtc_state->active_planes |= BIT(linked->id);
12025                 crtc_state->update_planes |= BIT(linked->id);
12026                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
12027
12028                 /* Copy parameters to slave plane */
12029                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12030                 linked_state->color_ctl = plane_state->color_ctl;
12031                 linked_state->color_plane[0] = plane_state->color_plane[0];
12032
12033                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12034                 linked_state->uapi.src = plane_state->uapi.src;
12035                 linked_state->uapi.dst = plane_state->uapi.dst;
12036
12037                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12038                         if (linked->id == PLANE_SPRITE5)
12039                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12040                         else if (linked->id == PLANE_SPRITE4)
12041                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12042                         else
12043                                 MISSING_CASE(linked->id);
12044                 }
12045         }
12046
12047         return 0;
12048 }
12049
12050 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12051 {
12052         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12053         struct intel_atomic_state *state =
12054                 to_intel_atomic_state(new_crtc_state->uapi.state);
12055         const struct intel_crtc_state *old_crtc_state =
12056                 intel_atomic_get_old_crtc_state(state, crtc);
12057
12058         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12059 }
12060
12061 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12062 {
12063         struct drm_crtc *crtc = crtc_state->uapi.crtc;
12064         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12065         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12066         struct drm_connector *master_connector, *connector;
12067         struct drm_connector_state *connector_state;
12068         struct drm_connector_list_iter conn_iter;
12069         struct drm_crtc *master_crtc = NULL;
12070         struct drm_crtc_state *master_crtc_state;
12071         struct intel_crtc_state *master_pipe_config;
12072         int i, tile_group_id;
12073
12074         if (INTEL_GEN(dev_priv) < 11)
12075                 return 0;
12076
12077         /*
12078          * In case of tiled displays there could be one or more slaves but there is
12079          * only one master. Lets make the CRTC used by the connector corresponding
12080          * to the last horizonal and last vertical tile a master/genlock CRTC.
12081          * All the other CRTCs corresponding to other tiles of the same Tile group
12082          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12083          */
12084         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12085                 if (connector_state->crtc != crtc)
12086                         continue;
12087                 if (!connector->has_tile)
12088                         continue;
12089                 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12090                     crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12091                         return 0;
12092                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12093                     connector->tile_v_loc == connector->num_v_tile - 1)
12094                         continue;
12095                 crtc_state->sync_mode_slaves_mask = 0;
12096                 tile_group_id = connector->tile_group->id;
12097                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12098                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12099                         struct drm_connector_state *master_conn_state = NULL;
12100
12101                         if (!master_connector->has_tile)
12102                                 continue;
12103                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12104                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12105                                 continue;
12106                         if (master_connector->tile_group->id != tile_group_id)
12107                                 continue;
12108
12109                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12110                                                                            master_connector);
12111                         if (IS_ERR(master_conn_state)) {
12112                                 drm_connector_list_iter_end(&conn_iter);
12113                                 return PTR_ERR(master_conn_state);
12114                         }
12115                         if (master_conn_state->crtc) {
12116                                 master_crtc = master_conn_state->crtc;
12117                                 break;
12118                         }
12119                 }
12120                 drm_connector_list_iter_end(&conn_iter);
12121
12122                 if (!master_crtc) {
12123                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12124                                       connector_state->crtc->base.id);
12125                         return -EINVAL;
12126                 }
12127
12128                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12129                                                               master_crtc);
12130                 if (IS_ERR(master_crtc_state))
12131                         return PTR_ERR(master_crtc_state);
12132
12133                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12134                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12135                 master_pipe_config->sync_mode_slaves_mask |=
12136                         BIT(crtc_state->cpu_transcoder);
12137                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12138                               transcoder_name(crtc_state->master_transcoder),
12139                               crtc_state->uapi.crtc->base.id,
12140                               master_pipe_config->sync_mode_slaves_mask);
12141         }
12142
12143         return 0;
12144 }
12145
12146 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12147                                    struct intel_crtc *crtc)
12148 {
12149         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12150         struct intel_crtc_state *crtc_state =
12151                 intel_atomic_get_new_crtc_state(state, crtc);
12152         bool mode_changed = needs_modeset(crtc_state);
12153         int ret;
12154
12155         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12156             mode_changed && !crtc_state->hw.active)
12157                 crtc_state->update_wm_post = true;
12158
12159         if (mode_changed && crtc_state->hw.enable &&
12160             dev_priv->display.crtc_compute_clock &&
12161             !WARN_ON(crtc_state->shared_dpll)) {
12162                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12163                 if (ret)
12164                         return ret;
12165         }
12166
12167         /*
12168          * May need to update pipe gamma enable bits
12169          * when C8 planes are getting enabled/disabled.
12170          */
12171         if (c8_planes_changed(crtc_state))
12172                 crtc_state->uapi.color_mgmt_changed = true;
12173
12174         if (mode_changed || crtc_state->update_pipe ||
12175             crtc_state->uapi.color_mgmt_changed) {
12176                 ret = intel_color_check(crtc_state);
12177                 if (ret)
12178                         return ret;
12179         }
12180
12181         ret = 0;
12182         if (dev_priv->display.compute_pipe_wm) {
12183                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12184                 if (ret) {
12185                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12186                         return ret;
12187                 }
12188         }
12189
12190         if (dev_priv->display.compute_intermediate_wm) {
12191                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12192                         return 0;
12193
12194                 /*
12195                  * Calculate 'intermediate' watermarks that satisfy both the
12196                  * old state and the new state.  We can program these
12197                  * immediately.
12198                  */
12199                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12200                 if (ret) {
12201                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12202                         return ret;
12203                 }
12204         }
12205
12206         if (INTEL_GEN(dev_priv) >= 9) {
12207                 if (mode_changed || crtc_state->update_pipe)
12208                         ret = skl_update_scaler_crtc(crtc_state);
12209                 if (!ret)
12210                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12211                                                          crtc_state);
12212         }
12213
12214         if (HAS_IPS(dev_priv))
12215                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12216
12217         return ret;
12218 }
12219
12220 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12221 {
12222         struct intel_connector *connector;
12223         struct drm_connector_list_iter conn_iter;
12224
12225         drm_connector_list_iter_begin(dev, &conn_iter);
12226         for_each_intel_connector_iter(connector, &conn_iter) {
12227                 if (connector->base.state->crtc)
12228                         drm_connector_put(&connector->base);
12229
12230                 if (connector->base.encoder) {
12231                         connector->base.state->best_encoder =
12232                                 connector->base.encoder;
12233                         connector->base.state->crtc =
12234                                 connector->base.encoder->crtc;
12235
12236                         drm_connector_get(&connector->base);
12237                 } else {
12238                         connector->base.state->best_encoder = NULL;
12239                         connector->base.state->crtc = NULL;
12240                 }
12241         }
12242         drm_connector_list_iter_end(&conn_iter);
12243 }
12244
12245 static int
12246 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12247                       struct intel_crtc_state *pipe_config)
12248 {
12249         struct drm_connector *connector = conn_state->connector;
12250         const struct drm_display_info *info = &connector->display_info;
12251         int bpp;
12252
12253         switch (conn_state->max_bpc) {
12254         case 6 ... 7:
12255                 bpp = 6 * 3;
12256                 break;
12257         case 8 ... 9:
12258                 bpp = 8 * 3;
12259                 break;
12260         case 10 ... 11:
12261                 bpp = 10 * 3;
12262                 break;
12263         case 12:
12264                 bpp = 12 * 3;
12265                 break;
12266         default:
12267                 return -EINVAL;
12268         }
12269
12270         if (bpp < pipe_config->pipe_bpp) {
12271                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12272                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12273                               connector->base.id, connector->name,
12274                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12275                               pipe_config->pipe_bpp);
12276
12277                 pipe_config->pipe_bpp = bpp;
12278         }
12279
12280         return 0;
12281 }
12282
12283 static int
12284 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12285                           struct intel_crtc_state *pipe_config)
12286 {
12287         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12288         struct drm_atomic_state *state = pipe_config->uapi.state;
12289         struct drm_connector *connector;
12290         struct drm_connector_state *connector_state;
12291         int bpp, i;
12292
12293         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12294             IS_CHERRYVIEW(dev_priv)))
12295                 bpp = 10*3;
12296         else if (INTEL_GEN(dev_priv) >= 5)
12297                 bpp = 12*3;
12298         else
12299                 bpp = 8*3;
12300
12301         pipe_config->pipe_bpp = bpp;
12302
12303         /* Clamp display bpp to connector max bpp */
12304         for_each_new_connector_in_state(state, connector, connector_state, i) {
12305                 int ret;
12306
12307                 if (connector_state->crtc != &crtc->base)
12308                         continue;
12309
12310                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12311                 if (ret)
12312                         return ret;
12313         }
12314
12315         return 0;
12316 }
12317
12318 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12319 {
12320         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12321                       "type: 0x%x flags: 0x%x\n",
12322                       mode->crtc_clock,
12323                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12324                       mode->crtc_hsync_end, mode->crtc_htotal,
12325                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12326                       mode->crtc_vsync_end, mode->crtc_vtotal,
12327                       mode->type, mode->flags);
12328 }
12329
12330 static inline void
12331 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12332                       const char *id, unsigned int lane_count,
12333                       const struct intel_link_m_n *m_n)
12334 {
12335         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12336                       id, lane_count,
12337                       m_n->gmch_m, m_n->gmch_n,
12338                       m_n->link_m, m_n->link_n, m_n->tu);
12339 }
12340
12341 static void
12342 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12343                      const union hdmi_infoframe *frame)
12344 {
12345         if ((drm_debug & DRM_UT_KMS) == 0)
12346                 return;
12347
12348         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12349 }
12350
12351 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12352
12353 static const char * const output_type_str[] = {
12354         OUTPUT_TYPE(UNUSED),
12355         OUTPUT_TYPE(ANALOG),
12356         OUTPUT_TYPE(DVO),
12357         OUTPUT_TYPE(SDVO),
12358         OUTPUT_TYPE(LVDS),
12359         OUTPUT_TYPE(TVOUT),
12360         OUTPUT_TYPE(HDMI),
12361         OUTPUT_TYPE(DP),
12362         OUTPUT_TYPE(EDP),
12363         OUTPUT_TYPE(DSI),
12364         OUTPUT_TYPE(DDI),
12365         OUTPUT_TYPE(DP_MST),
12366 };
12367
12368 #undef OUTPUT_TYPE
12369
12370 static void snprintf_output_types(char *buf, size_t len,
12371                                   unsigned int output_types)
12372 {
12373         char *str = buf;
12374         int i;
12375
12376         str[0] = '\0';
12377
12378         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12379                 int r;
12380
12381                 if ((output_types & BIT(i)) == 0)
12382                         continue;
12383
12384                 r = snprintf(str, len, "%s%s",
12385                              str != buf ? "," : "", output_type_str[i]);
12386                 if (r >= len)
12387                         break;
12388                 str += r;
12389                 len -= r;
12390
12391                 output_types &= ~BIT(i);
12392         }
12393
12394         WARN_ON_ONCE(output_types != 0);
12395 }
12396
12397 static const char * const output_format_str[] = {
12398         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12399         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12400         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12401         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12402 };
12403
12404 static const char *output_formats(enum intel_output_format format)
12405 {
12406         if (format >= ARRAY_SIZE(output_format_str))
12407                 format = INTEL_OUTPUT_FORMAT_INVALID;
12408         return output_format_str[format];
12409 }
12410
12411 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12412 {
12413         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12414         const struct drm_framebuffer *fb = plane_state->hw.fb;
12415         struct drm_format_name_buf format_name;
12416
12417         if (!fb) {
12418                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12419                               plane->base.base.id, plane->base.name,
12420                               yesno(plane_state->uapi.visible));
12421                 return;
12422         }
12423
12424         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12425                       plane->base.base.id, plane->base.name,
12426                       fb->base.id, fb->width, fb->height,
12427                       drm_get_format_name(fb->format->format, &format_name),
12428                       yesno(plane_state->uapi.visible));
12429         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12430                       plane_state->hw.rotation, plane_state->scaler_id);
12431         if (plane_state->uapi.visible)
12432                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12433                               DRM_RECT_FP_ARG(&plane_state->uapi.src),
12434                               DRM_RECT_ARG(&plane_state->uapi.dst));
12435 }
12436
12437 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12438                                    struct intel_atomic_state *state,
12439                                    const char *context)
12440 {
12441         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12442         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12443         const struct intel_plane_state *plane_state;
12444         struct intel_plane *plane;
12445         char buf[64];
12446         int i;
12447
12448         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12449                       crtc->base.base.id, crtc->base.name,
12450                       yesno(pipe_config->hw.enable), context);
12451
12452         if (!pipe_config->hw.enable)
12453                 goto dump_planes;
12454
12455         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12456         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12457                       yesno(pipe_config->hw.active),
12458                       buf, pipe_config->output_types,
12459                       output_formats(pipe_config->output_format));
12460
12461         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12462                       transcoder_name(pipe_config->cpu_transcoder),
12463                       pipe_config->pipe_bpp, pipe_config->dither);
12464
12465         if (pipe_config->has_pch_encoder)
12466                 intel_dump_m_n_config(pipe_config, "fdi",
12467                                       pipe_config->fdi_lanes,
12468                                       &pipe_config->fdi_m_n);
12469
12470         if (intel_crtc_has_dp_encoder(pipe_config)) {
12471                 intel_dump_m_n_config(pipe_config, "dp m_n",
12472                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12473                 if (pipe_config->has_drrs)
12474                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12475                                               pipe_config->lane_count,
12476                                               &pipe_config->dp_m2_n2);
12477         }
12478
12479         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12480                       pipe_config->has_audio, pipe_config->has_infoframe,
12481                       pipe_config->infoframes.enable);
12482
12483         if (pipe_config->infoframes.enable &
12484             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12485                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12486         if (pipe_config->infoframes.enable &
12487             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12488                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12489         if (pipe_config->infoframes.enable &
12490             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12491                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12492         if (pipe_config->infoframes.enable &
12493             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12494                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12495
12496         DRM_DEBUG_KMS("requested mode:\n");
12497         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12498         DRM_DEBUG_KMS("adjusted mode:\n");
12499         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12500         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12501         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12502                       pipe_config->port_clock,
12503                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12504                       pipe_config->pixel_rate);
12505
12506         if (INTEL_GEN(dev_priv) >= 9)
12507                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12508                               crtc->num_scalers,
12509                               pipe_config->scaler_state.scaler_users,
12510                               pipe_config->scaler_state.scaler_id);
12511
12512         if (HAS_GMCH(dev_priv))
12513                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12514                               pipe_config->gmch_pfit.control,
12515                               pipe_config->gmch_pfit.pgm_ratios,
12516                               pipe_config->gmch_pfit.lvds_border_bits);
12517         else
12518                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12519                               pipe_config->pch_pfit.pos,
12520                               pipe_config->pch_pfit.size,
12521                               enableddisabled(pipe_config->pch_pfit.enabled),
12522                               yesno(pipe_config->pch_pfit.force_thru));
12523
12524         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12525                       pipe_config->ips_enabled, pipe_config->double_wide);
12526
12527         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12528
12529         if (IS_CHERRYVIEW(dev_priv))
12530                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12531                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12532                               pipe_config->gamma_enable, pipe_config->csc_enable);
12533         else
12534                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12535                               pipe_config->csc_mode, pipe_config->gamma_mode,
12536                               pipe_config->gamma_enable, pipe_config->csc_enable);
12537
12538 dump_planes:
12539         if (!state)
12540                 return;
12541
12542         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12543                 if (plane->pipe == crtc->pipe)
12544                         intel_dump_plane_state(plane_state);
12545         }
12546 }
12547
12548 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12549 {
12550         struct drm_device *dev = state->base.dev;
12551         struct drm_connector *connector;
12552         struct drm_connector_list_iter conn_iter;
12553         unsigned int used_ports = 0;
12554         unsigned int used_mst_ports = 0;
12555         bool ret = true;
12556
12557         /*
12558          * We're going to peek into connector->state,
12559          * hence connection_mutex must be held.
12560          */
12561         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12562
12563         /*
12564          * Walk the connector list instead of the encoder
12565          * list to detect the problem on ddi platforms
12566          * where there's just one encoder per digital port.
12567          */
12568         drm_connector_list_iter_begin(dev, &conn_iter);
12569         drm_for_each_connector_iter(connector, &conn_iter) {
12570                 struct drm_connector_state *connector_state;
12571                 struct intel_encoder *encoder;
12572
12573                 connector_state =
12574                         drm_atomic_get_new_connector_state(&state->base,
12575                                                            connector);
12576                 if (!connector_state)
12577                         connector_state = connector->state;
12578
12579                 if (!connector_state->best_encoder)
12580                         continue;
12581
12582                 encoder = to_intel_encoder(connector_state->best_encoder);
12583
12584                 WARN_ON(!connector_state->crtc);
12585
12586                 switch (encoder->type) {
12587                         unsigned int port_mask;
12588                 case INTEL_OUTPUT_DDI:
12589                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12590                                 break;
12591                         /* else, fall through */
12592                 case INTEL_OUTPUT_DP:
12593                 case INTEL_OUTPUT_HDMI:
12594                 case INTEL_OUTPUT_EDP:
12595                         port_mask = 1 << encoder->port;
12596
12597                         /* the same port mustn't appear more than once */
12598                         if (used_ports & port_mask)
12599                                 ret = false;
12600
12601                         used_ports |= port_mask;
12602                         break;
12603                 case INTEL_OUTPUT_DP_MST:
12604                         used_mst_ports |=
12605                                 1 << encoder->port;
12606                         break;
12607                 default:
12608                         break;
12609                 }
12610         }
12611         drm_connector_list_iter_end(&conn_iter);
12612
12613         /* can't mix MST and SST/HDMI on the same port */
12614         if (used_ports & used_mst_ports)
12615                 return false;
12616
12617         return ret;
12618 }
12619
12620 static void
12621 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12622 {
12623         intel_crtc_copy_color_blobs(crtc_state);
12624 }
12625
12626 static void
12627 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12628 {
12629         crtc_state->hw.enable = crtc_state->uapi.enable;
12630         crtc_state->hw.active = crtc_state->uapi.active;
12631         crtc_state->hw.mode = crtc_state->uapi.mode;
12632         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12633         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12634 }
12635
12636 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12637 {
12638         crtc_state->uapi.enable = crtc_state->hw.enable;
12639         crtc_state->uapi.active = crtc_state->hw.active;
12640         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12641
12642         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12643
12644         /* copy color blobs to uapi */
12645         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12646                                   crtc_state->hw.degamma_lut);
12647         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12648                                   crtc_state->hw.gamma_lut);
12649         drm_property_replace_blob(&crtc_state->uapi.ctm,
12650                                   crtc_state->hw.ctm);
12651 }
12652
12653 static int
12654 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12655 {
12656         struct drm_i915_private *dev_priv =
12657                 to_i915(crtc_state->uapi.crtc->dev);
12658         struct intel_crtc_state *saved_state;
12659
12660         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12661         if (!saved_state)
12662                 return -ENOMEM;
12663
12664         /* free the old crtc_state->hw members */
12665         intel_crtc_free_hw_state(crtc_state);
12666
12667         /* FIXME: before the switch to atomic started, a new pipe_config was
12668          * kzalloc'd. Code that depends on any field being zero should be
12669          * fixed, so that the crtc_state can be safely duplicated. For now,
12670          * only fields that are know to not cause problems are preserved. */
12671
12672         saved_state->uapi = crtc_state->uapi;
12673         saved_state->scaler_state = crtc_state->scaler_state;
12674         saved_state->shared_dpll = crtc_state->shared_dpll;
12675         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12676         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12677                sizeof(saved_state->icl_port_dplls));
12678         saved_state->crc_enabled = crtc_state->crc_enabled;
12679         if (IS_G4X(dev_priv) ||
12680             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12681                 saved_state->wm = crtc_state->wm;
12682         /*
12683          * Save the slave bitmask which gets filled for master crtc state during
12684          * slave atomic check call.
12685          */
12686         if (is_trans_port_sync_master(crtc_state))
12687                 saved_state->sync_mode_slaves_mask =
12688                         crtc_state->sync_mode_slaves_mask;
12689
12690         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12691         kfree(saved_state);
12692
12693         intel_crtc_copy_uapi_to_hw_state(crtc_state);
12694
12695         return 0;
12696 }
12697
12698 static int
12699 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12700 {
12701         struct drm_crtc *crtc = pipe_config->uapi.crtc;
12702         struct drm_atomic_state *state = pipe_config->uapi.state;
12703         struct intel_encoder *encoder;
12704         struct drm_connector *connector;
12705         struct drm_connector_state *connector_state;
12706         int base_bpp, ret;
12707         int i;
12708         bool retry = true;
12709
12710         pipe_config->cpu_transcoder =
12711                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12712
12713         /*
12714          * Sanitize sync polarity flags based on requested ones. If neither
12715          * positive or negative polarity is requested, treat this as meaning
12716          * negative polarity.
12717          */
12718         if (!(pipe_config->hw.adjusted_mode.flags &
12719               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12720                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12721
12722         if (!(pipe_config->hw.adjusted_mode.flags &
12723               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12724                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12725
12726         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12727                                         pipe_config);
12728         if (ret)
12729                 return ret;
12730
12731         base_bpp = pipe_config->pipe_bpp;
12732
12733         /*
12734          * Determine the real pipe dimensions. Note that stereo modes can
12735          * increase the actual pipe size due to the frame doubling and
12736          * insertion of additional space for blanks between the frame. This
12737          * is stored in the crtc timings. We use the requested mode to do this
12738          * computation to clearly distinguish it from the adjusted mode, which
12739          * can be changed by the connectors in the below retry loop.
12740          */
12741         drm_mode_get_hv_timing(&pipe_config->hw.mode,
12742                                &pipe_config->pipe_src_w,
12743                                &pipe_config->pipe_src_h);
12744
12745         for_each_new_connector_in_state(state, connector, connector_state, i) {
12746                 if (connector_state->crtc != crtc)
12747                         continue;
12748
12749                 encoder = to_intel_encoder(connector_state->best_encoder);
12750
12751                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12752                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12753                         return -EINVAL;
12754                 }
12755
12756                 /*
12757                  * Determine output_types before calling the .compute_config()
12758                  * hooks so that the hooks can use this information safely.
12759                  */
12760                 if (encoder->compute_output_type)
12761                         pipe_config->output_types |=
12762                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12763                                                                  connector_state));
12764                 else
12765                         pipe_config->output_types |= BIT(encoder->type);
12766         }
12767
12768 encoder_retry:
12769         /* Ensure the port clock defaults are reset when retrying. */
12770         pipe_config->port_clock = 0;
12771         pipe_config->pixel_multiplier = 1;
12772
12773         /* Fill in default crtc timings, allow encoders to overwrite them. */
12774         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12775                               CRTC_STEREO_DOUBLE);
12776
12777         /* Set the crtc_state defaults for trans_port_sync */
12778         pipe_config->master_transcoder = INVALID_TRANSCODER;
12779         ret = icl_add_sync_mode_crtcs(pipe_config);
12780         if (ret) {
12781                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12782                               ret);
12783                 return ret;
12784         }
12785
12786         /* Pass our mode to the connectors and the CRTC to give them a chance to
12787          * adjust it according to limitations or connector properties, and also
12788          * a chance to reject the mode entirely.
12789          */
12790         for_each_new_connector_in_state(state, connector, connector_state, i) {
12791                 if (connector_state->crtc != crtc)
12792                         continue;
12793
12794                 encoder = to_intel_encoder(connector_state->best_encoder);
12795                 ret = encoder->compute_config(encoder, pipe_config,
12796                                               connector_state);
12797                 if (ret < 0) {
12798                         if (ret != -EDEADLK)
12799                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12800                                               ret);
12801                         return ret;
12802                 }
12803         }
12804
12805         /* Set default port clock if not overwritten by the encoder. Needs to be
12806          * done afterwards in case the encoder adjusts the mode. */
12807         if (!pipe_config->port_clock)
12808                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12809                         * pipe_config->pixel_multiplier;
12810
12811         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12812         if (ret == -EDEADLK)
12813                 return ret;
12814         if (ret < 0) {
12815                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12816                 return ret;
12817         }
12818
12819         if (ret == RETRY) {
12820                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12821                         return -EINVAL;
12822
12823                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12824                 retry = false;
12825                 goto encoder_retry;
12826         }
12827
12828         /* Dithering seems to not pass-through bits correctly when it should, so
12829          * only enable it on 6bpc panels and when its not a compliance
12830          * test requesting 6bpc video pattern.
12831          */
12832         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12833                 !pipe_config->dither_force_disable;
12834         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12835                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12836
12837         /*
12838          * Make drm_calc_timestamping_constants in
12839          * drm_atomic_helper_update_legacy_modeset_state() happy
12840          */
12841         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12842
12843         return 0;
12844 }
12845
12846 bool intel_fuzzy_clock_check(int clock1, int clock2)
12847 {
12848         int diff;
12849
12850         if (clock1 == clock2)
12851                 return true;
12852
12853         if (!clock1 || !clock2)
12854                 return false;
12855
12856         diff = abs(clock1 - clock2);
12857
12858         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12859                 return true;
12860
12861         return false;
12862 }
12863
12864 static bool
12865 intel_compare_m_n(unsigned int m, unsigned int n,
12866                   unsigned int m2, unsigned int n2,
12867                   bool exact)
12868 {
12869         if (m == m2 && n == n2)
12870                 return true;
12871
12872         if (exact || !m || !n || !m2 || !n2)
12873                 return false;
12874
12875         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12876
12877         if (n > n2) {
12878                 while (n > n2) {
12879                         m2 <<= 1;
12880                         n2 <<= 1;
12881                 }
12882         } else if (n < n2) {
12883                 while (n < n2) {
12884                         m <<= 1;
12885                         n <<= 1;
12886                 }
12887         }
12888
12889         if (n != n2)
12890                 return false;
12891
12892         return intel_fuzzy_clock_check(m, m2);
12893 }
12894
12895 static bool
12896 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12897                        const struct intel_link_m_n *m2_n2,
12898                        bool exact)
12899 {
12900         return m_n->tu == m2_n2->tu &&
12901                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12902                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12903                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12904                                   m2_n2->link_m, m2_n2->link_n, exact);
12905 }
12906
12907 static bool
12908 intel_compare_infoframe(const union hdmi_infoframe *a,
12909                         const union hdmi_infoframe *b)
12910 {
12911         return memcmp(a, b, sizeof(*a)) == 0;
12912 }
12913
12914 static void
12915 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12916                                bool fastset, const char *name,
12917                                const union hdmi_infoframe *a,
12918                                const union hdmi_infoframe *b)
12919 {
12920         if (fastset) {
12921                 if ((drm_debug & DRM_UT_KMS) == 0)
12922                         return;
12923
12924                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12925                 DRM_DEBUG_KMS("expected:\n");
12926                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12927                 DRM_DEBUG_KMS("found:\n");
12928                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12929         } else {
12930                 DRM_ERROR("mismatch in %s infoframe\n", name);
12931                 DRM_ERROR("expected:\n");
12932                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12933                 DRM_ERROR("found:\n");
12934                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12935         }
12936 }
12937
12938 static void __printf(4, 5)
12939 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12940                      const char *name, const char *format, ...)
12941 {
12942         struct va_format vaf;
12943         va_list args;
12944
12945         va_start(args, format);
12946         vaf.fmt = format;
12947         vaf.va = &args;
12948
12949         if (fastset)
12950                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12951                               crtc->base.base.id, crtc->base.name, name, &vaf);
12952         else
12953                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12954                           crtc->base.base.id, crtc->base.name, name, &vaf);
12955
12956         va_end(args);
12957 }
12958
12959 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12960 {
12961         if (i915_modparams.fastboot != -1)
12962                 return i915_modparams.fastboot;
12963
12964         /* Enable fastboot by default on Skylake and newer */
12965         if (INTEL_GEN(dev_priv) >= 9)
12966                 return true;
12967
12968         /* Enable fastboot by default on VLV and CHV */
12969         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12970                 return true;
12971
12972         /* Disabled by default on all others */
12973         return false;
12974 }
12975
12976 static bool
12977 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
12978                           const struct intel_crtc_state *pipe_config,
12979                           bool fastset)
12980 {
12981         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
12982         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12983         bool ret = true;
12984         u32 bp_gamma = 0;
12985         bool fixup_inherited = fastset &&
12986                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12987                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
12988
12989         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12990                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12991                 ret = false;
12992         }
12993
12994 #define PIPE_CONF_CHECK_X(name) do { \
12995         if (current_config->name != pipe_config->name) { \
12996                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12997                                      "(expected 0x%08x, found 0x%08x)", \
12998                                      current_config->name, \
12999                                      pipe_config->name); \
13000                 ret = false; \
13001         } \
13002 } while (0)
13003
13004 #define PIPE_CONF_CHECK_I(name) do { \
13005         if (current_config->name != pipe_config->name) { \
13006                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13007                                      "(expected %i, found %i)", \
13008                                      current_config->name, \
13009                                      pipe_config->name); \
13010                 ret = false; \
13011         } \
13012 } while (0)
13013
13014 #define PIPE_CONF_CHECK_BOOL(name) do { \
13015         if (current_config->name != pipe_config->name) { \
13016                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13017                                      "(expected %s, found %s)", \
13018                                      yesno(current_config->name), \
13019                                      yesno(pipe_config->name)); \
13020                 ret = false; \
13021         } \
13022 } while (0)
13023
13024 /*
13025  * Checks state where we only read out the enabling, but not the entire
13026  * state itself (like full infoframes or ELD for audio). These states
13027  * require a full modeset on bootup to fix up.
13028  */
13029 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13030         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13031                 PIPE_CONF_CHECK_BOOL(name); \
13032         } else { \
13033                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13034                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13035                                      yesno(current_config->name), \
13036                                      yesno(pipe_config->name)); \
13037                 ret = false; \
13038         } \
13039 } while (0)
13040
13041 #define PIPE_CONF_CHECK_P(name) do { \
13042         if (current_config->name != pipe_config->name) { \
13043                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13044                                      "(expected %p, found %p)", \
13045                                      current_config->name, \
13046                                      pipe_config->name); \
13047                 ret = false; \
13048         } \
13049 } while (0)
13050
13051 #define PIPE_CONF_CHECK_M_N(name) do { \
13052         if (!intel_compare_link_m_n(&current_config->name, \
13053                                     &pipe_config->name,\
13054                                     !fastset)) { \
13055                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13056                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13057                                      "found tu %i, gmch %i/%i link %i/%i)", \
13058                                      current_config->name.tu, \
13059                                      current_config->name.gmch_m, \
13060                                      current_config->name.gmch_n, \
13061                                      current_config->name.link_m, \
13062                                      current_config->name.link_n, \
13063                                      pipe_config->name.tu, \
13064                                      pipe_config->name.gmch_m, \
13065                                      pipe_config->name.gmch_n, \
13066                                      pipe_config->name.link_m, \
13067                                      pipe_config->name.link_n); \
13068                 ret = false; \
13069         } \
13070 } while (0)
13071
13072 /* This is required for BDW+ where there is only one set of registers for
13073  * switching between high and low RR.
13074  * This macro can be used whenever a comparison has to be made between one
13075  * hw state and multiple sw state variables.
13076  */
13077 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13078         if (!intel_compare_link_m_n(&current_config->name, \
13079                                     &pipe_config->name, !fastset) && \
13080             !intel_compare_link_m_n(&current_config->alt_name, \
13081                                     &pipe_config->name, !fastset)) { \
13082                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13083                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13084                                      "or tu %i gmch %i/%i link %i/%i, " \
13085                                      "found tu %i, gmch %i/%i link %i/%i)", \
13086                                      current_config->name.tu, \
13087                                      current_config->name.gmch_m, \
13088                                      current_config->name.gmch_n, \
13089                                      current_config->name.link_m, \
13090                                      current_config->name.link_n, \
13091                                      current_config->alt_name.tu, \
13092                                      current_config->alt_name.gmch_m, \
13093                                      current_config->alt_name.gmch_n, \
13094                                      current_config->alt_name.link_m, \
13095                                      current_config->alt_name.link_n, \
13096                                      pipe_config->name.tu, \
13097                                      pipe_config->name.gmch_m, \
13098                                      pipe_config->name.gmch_n, \
13099                                      pipe_config->name.link_m, \
13100                                      pipe_config->name.link_n); \
13101                 ret = false; \
13102         } \
13103 } while (0)
13104
13105 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13106         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13107                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13108                                      "(%x) (expected %i, found %i)", \
13109                                      (mask), \
13110                                      current_config->name & (mask), \
13111                                      pipe_config->name & (mask)); \
13112                 ret = false; \
13113         } \
13114 } while (0)
13115
13116 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13117         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13118                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13119                                      "(expected %i, found %i)", \
13120                                      current_config->name, \
13121                                      pipe_config->name); \
13122                 ret = false; \
13123         } \
13124 } while (0)
13125
13126 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13127         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13128                                      &pipe_config->infoframes.name)) { \
13129                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13130                                                &current_config->infoframes.name, \
13131                                                &pipe_config->infoframes.name); \
13132                 ret = false; \
13133         } \
13134 } while (0)
13135
13136 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13137         if (current_config->name1 != pipe_config->name1) { \
13138                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13139                                 "(expected %i, found %i, won't compare lut values)", \
13140                                 current_config->name1, \
13141                                 pipe_config->name1); \
13142                 ret = false;\
13143         } else { \
13144                 if (!intel_color_lut_equal(current_config->name2, \
13145                                         pipe_config->name2, pipe_config->name1, \
13146                                         bit_precision)) { \
13147                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13148                                         "hw_state doesn't match sw_state"); \
13149                         ret = false; \
13150                 } \
13151         } \
13152 } while (0)
13153
13154 #define PIPE_CONF_QUIRK(quirk) \
13155         ((current_config->quirks | pipe_config->quirks) & (quirk))
13156
13157         PIPE_CONF_CHECK_I(cpu_transcoder);
13158
13159         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13160         PIPE_CONF_CHECK_I(fdi_lanes);
13161         PIPE_CONF_CHECK_M_N(fdi_m_n);
13162
13163         PIPE_CONF_CHECK_I(lane_count);
13164         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13165
13166         if (INTEL_GEN(dev_priv) < 8) {
13167                 PIPE_CONF_CHECK_M_N(dp_m_n);
13168
13169                 if (current_config->has_drrs)
13170                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13171         } else
13172                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13173
13174         PIPE_CONF_CHECK_X(output_types);
13175
13176         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13177         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13178         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13179         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13180         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13181         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13182
13183         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13184         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13185         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13186         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13187         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13188         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13189
13190         PIPE_CONF_CHECK_I(pixel_multiplier);
13191         PIPE_CONF_CHECK_I(output_format);
13192         PIPE_CONF_CHECK_I(dc3co_exitline);
13193         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13194         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13195             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13196                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13197
13198         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13199         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13200         PIPE_CONF_CHECK_BOOL(has_infoframe);
13201         PIPE_CONF_CHECK_BOOL(fec_enable);
13202
13203         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13204
13205         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13206                               DRM_MODE_FLAG_INTERLACE);
13207
13208         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13209                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13210                                       DRM_MODE_FLAG_PHSYNC);
13211                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13212                                       DRM_MODE_FLAG_NHSYNC);
13213                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13214                                       DRM_MODE_FLAG_PVSYNC);
13215                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13216                                       DRM_MODE_FLAG_NVSYNC);
13217         }
13218
13219         PIPE_CONF_CHECK_X(gmch_pfit.control);
13220         /* pfit ratios are autocomputed by the hw on gen4+ */
13221         if (INTEL_GEN(dev_priv) < 4)
13222                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13223         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13224
13225         /*
13226          * Changing the EDP transcoder input mux
13227          * (A_ONOFF vs. A_ON) requires a full modeset.
13228          */
13229         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13230
13231         if (!fastset) {
13232                 PIPE_CONF_CHECK_I(pipe_src_w);
13233                 PIPE_CONF_CHECK_I(pipe_src_h);
13234
13235                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13236                 if (current_config->pch_pfit.enabled) {
13237                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13238                         PIPE_CONF_CHECK_X(pch_pfit.size);
13239                 }
13240
13241                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13242                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13243
13244                 PIPE_CONF_CHECK_X(gamma_mode);
13245                 if (IS_CHERRYVIEW(dev_priv))
13246                         PIPE_CONF_CHECK_X(cgm_mode);
13247                 else
13248                         PIPE_CONF_CHECK_X(csc_mode);
13249                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13250                 PIPE_CONF_CHECK_BOOL(csc_enable);
13251
13252                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13253                 if (bp_gamma)
13254                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13255
13256         }
13257
13258         PIPE_CONF_CHECK_BOOL(double_wide);
13259
13260         PIPE_CONF_CHECK_P(shared_dpll);
13261         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13262         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13263         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13264         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13265         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13266         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13267         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13268         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13269         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13270         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13271         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13272         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13273         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13274         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13275         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13276         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13277         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13278         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13279         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13280         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13281         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13282         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13283         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13284         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13285         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13286         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13287         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13288         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13289         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13290         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13291         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13292
13293         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13294         PIPE_CONF_CHECK_X(dsi_pll.div);
13295
13296         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13297                 PIPE_CONF_CHECK_I(pipe_bpp);
13298
13299         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13300         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13301
13302         PIPE_CONF_CHECK_I(min_voltage_level);
13303
13304         PIPE_CONF_CHECK_X(infoframes.enable);
13305         PIPE_CONF_CHECK_X(infoframes.gcp);
13306         PIPE_CONF_CHECK_INFOFRAME(avi);
13307         PIPE_CONF_CHECK_INFOFRAME(spd);
13308         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13309         PIPE_CONF_CHECK_INFOFRAME(drm);
13310
13311         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13312         PIPE_CONF_CHECK_I(master_transcoder);
13313
13314         PIPE_CONF_CHECK_I(dsc.compression_enable);
13315         PIPE_CONF_CHECK_I(dsc.dsc_split);
13316         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
13317
13318 #undef PIPE_CONF_CHECK_X
13319 #undef PIPE_CONF_CHECK_I
13320 #undef PIPE_CONF_CHECK_BOOL
13321 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13322 #undef PIPE_CONF_CHECK_P
13323 #undef PIPE_CONF_CHECK_FLAGS
13324 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13325 #undef PIPE_CONF_CHECK_COLOR_LUT
13326 #undef PIPE_CONF_QUIRK
13327
13328         return ret;
13329 }
13330
13331 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13332                                            const struct intel_crtc_state *pipe_config)
13333 {
13334         if (pipe_config->has_pch_encoder) {
13335                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13336                                                             &pipe_config->fdi_m_n);
13337                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13338
13339                 /*
13340                  * FDI already provided one idea for the dotclock.
13341                  * Yell if the encoder disagrees.
13342                  */
13343                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13344                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13345                      fdi_dotclock, dotclock);
13346         }
13347 }
13348
13349 static void verify_wm_state(struct intel_crtc *crtc,
13350                             struct intel_crtc_state *new_crtc_state)
13351 {
13352         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13353         struct skl_hw_state {
13354                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13355                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13356                 struct skl_ddb_allocation ddb;
13357                 struct skl_pipe_wm wm;
13358         } *hw;
13359         struct skl_ddb_allocation *sw_ddb;
13360         struct skl_pipe_wm *sw_wm;
13361         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13362         const enum pipe pipe = crtc->pipe;
13363         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13364
13365         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13366                 return;
13367
13368         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13369         if (!hw)
13370                 return;
13371
13372         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13373         sw_wm = &new_crtc_state->wm.skl.optimal;
13374
13375         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13376
13377         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13378         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13379
13380         if (INTEL_GEN(dev_priv) >= 11 &&
13381             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13382                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13383                           sw_ddb->enabled_slices,
13384                           hw->ddb.enabled_slices);
13385
13386         /* planes */
13387         for_each_universal_plane(dev_priv, pipe, plane) {
13388                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13389
13390                 hw_plane_wm = &hw->wm.planes[plane];
13391                 sw_plane_wm = &sw_wm->planes[plane];
13392
13393                 /* Watermarks */
13394                 for (level = 0; level <= max_level; level++) {
13395                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13396                                                 &sw_plane_wm->wm[level]))
13397                                 continue;
13398
13399                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13400                                   pipe_name(pipe), plane + 1, level,
13401                                   sw_plane_wm->wm[level].plane_en,
13402                                   sw_plane_wm->wm[level].plane_res_b,
13403                                   sw_plane_wm->wm[level].plane_res_l,
13404                                   hw_plane_wm->wm[level].plane_en,
13405                                   hw_plane_wm->wm[level].plane_res_b,
13406                                   hw_plane_wm->wm[level].plane_res_l);
13407                 }
13408
13409                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13410                                          &sw_plane_wm->trans_wm)) {
13411                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13412                                   pipe_name(pipe), plane + 1,
13413                                   sw_plane_wm->trans_wm.plane_en,
13414                                   sw_plane_wm->trans_wm.plane_res_b,
13415                                   sw_plane_wm->trans_wm.plane_res_l,
13416                                   hw_plane_wm->trans_wm.plane_en,
13417                                   hw_plane_wm->trans_wm.plane_res_b,
13418                                   hw_plane_wm->trans_wm.plane_res_l);
13419                 }
13420
13421                 /* DDB */
13422                 hw_ddb_entry = &hw->ddb_y[plane];
13423                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13424
13425                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13426                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13427                                   pipe_name(pipe), plane + 1,
13428                                   sw_ddb_entry->start, sw_ddb_entry->end,
13429                                   hw_ddb_entry->start, hw_ddb_entry->end);
13430                 }
13431         }
13432
13433         /*
13434          * cursor
13435          * If the cursor plane isn't active, we may not have updated it's ddb
13436          * allocation. In that case since the ddb allocation will be updated
13437          * once the plane becomes visible, we can skip this check
13438          */
13439         if (1) {
13440                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13441
13442                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13443                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13444
13445                 /* Watermarks */
13446                 for (level = 0; level <= max_level; level++) {
13447                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13448                                                 &sw_plane_wm->wm[level]))
13449                                 continue;
13450
13451                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13452                                   pipe_name(pipe), level,
13453                                   sw_plane_wm->wm[level].plane_en,
13454                                   sw_plane_wm->wm[level].plane_res_b,
13455                                   sw_plane_wm->wm[level].plane_res_l,
13456                                   hw_plane_wm->wm[level].plane_en,
13457                                   hw_plane_wm->wm[level].plane_res_b,
13458                                   hw_plane_wm->wm[level].plane_res_l);
13459                 }
13460
13461                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13462                                          &sw_plane_wm->trans_wm)) {
13463                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13464                                   pipe_name(pipe),
13465                                   sw_plane_wm->trans_wm.plane_en,
13466                                   sw_plane_wm->trans_wm.plane_res_b,
13467                                   sw_plane_wm->trans_wm.plane_res_l,
13468                                   hw_plane_wm->trans_wm.plane_en,
13469                                   hw_plane_wm->trans_wm.plane_res_b,
13470                                   hw_plane_wm->trans_wm.plane_res_l);
13471                 }
13472
13473                 /* DDB */
13474                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13475                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13476
13477                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13478                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13479                                   pipe_name(pipe),
13480                                   sw_ddb_entry->start, sw_ddb_entry->end,
13481                                   hw_ddb_entry->start, hw_ddb_entry->end);
13482                 }
13483         }
13484
13485         kfree(hw);
13486 }
13487
13488 static void
13489 verify_connector_state(struct intel_atomic_state *state,
13490                        struct intel_crtc *crtc)
13491 {
13492         struct drm_connector *connector;
13493         struct drm_connector_state *new_conn_state;
13494         int i;
13495
13496         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13497                 struct drm_encoder *encoder = connector->encoder;
13498                 struct intel_crtc_state *crtc_state = NULL;
13499
13500                 if (new_conn_state->crtc != &crtc->base)
13501                         continue;
13502
13503                 if (crtc)
13504                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13505
13506                 intel_connector_verify_state(crtc_state, new_conn_state);
13507
13508                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13509                      "connector's atomic encoder doesn't match legacy encoder\n");
13510         }
13511 }
13512
13513 static void
13514 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13515 {
13516         struct intel_encoder *encoder;
13517         struct drm_connector *connector;
13518         struct drm_connector_state *old_conn_state, *new_conn_state;
13519         int i;
13520
13521         for_each_intel_encoder(&dev_priv->drm, encoder) {
13522                 bool enabled = false, found = false;
13523                 enum pipe pipe;
13524
13525                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13526                               encoder->base.base.id,
13527                               encoder->base.name);
13528
13529                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13530                                                    new_conn_state, i) {
13531                         if (old_conn_state->best_encoder == &encoder->base)
13532                                 found = true;
13533
13534                         if (new_conn_state->best_encoder != &encoder->base)
13535                                 continue;
13536                         found = enabled = true;
13537
13538                         I915_STATE_WARN(new_conn_state->crtc !=
13539                                         encoder->base.crtc,
13540                              "connector's crtc doesn't match encoder crtc\n");
13541                 }
13542
13543                 if (!found)
13544                         continue;
13545
13546                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13547                      "encoder's enabled state mismatch "
13548                      "(expected %i, found %i)\n",
13549                      !!encoder->base.crtc, enabled);
13550
13551                 if (!encoder->base.crtc) {
13552                         bool active;
13553
13554                         active = encoder->get_hw_state(encoder, &pipe);
13555                         I915_STATE_WARN(active,
13556                              "encoder detached but still enabled on pipe %c.\n",
13557                              pipe_name(pipe));
13558                 }
13559         }
13560 }
13561
13562 static void
13563 verify_crtc_state(struct intel_crtc *crtc,
13564                   struct intel_crtc_state *old_crtc_state,
13565                   struct intel_crtc_state *new_crtc_state)
13566 {
13567         struct drm_device *dev = crtc->base.dev;
13568         struct drm_i915_private *dev_priv = to_i915(dev);
13569         struct intel_encoder *encoder;
13570         struct intel_crtc_state *pipe_config = old_crtc_state;
13571         struct drm_atomic_state *state = old_crtc_state->uapi.state;
13572         bool active;
13573
13574         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13575         intel_crtc_free_hw_state(old_crtc_state);
13576         intel_crtc_state_reset(old_crtc_state, crtc);
13577         old_crtc_state->uapi.state = state;
13578
13579         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13580
13581         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13582
13583         /* we keep both pipes enabled on 830 */
13584         if (IS_I830(dev_priv))
13585                 active = new_crtc_state->hw.active;
13586
13587         I915_STATE_WARN(new_crtc_state->hw.active != active,
13588                         "crtc active state doesn't match with hw state "
13589                         "(expected %i, found %i)\n",
13590                         new_crtc_state->hw.active, active);
13591
13592         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13593                         "transitional active state does not match atomic hw state "
13594                         "(expected %i, found %i)\n",
13595                         new_crtc_state->hw.active, crtc->active);
13596
13597         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13598                 enum pipe pipe;
13599
13600                 active = encoder->get_hw_state(encoder, &pipe);
13601                 I915_STATE_WARN(active != new_crtc_state->hw.active,
13602                                 "[ENCODER:%i] active %i with crtc active %i\n",
13603                                 encoder->base.base.id, active,
13604                                 new_crtc_state->hw.active);
13605
13606                 I915_STATE_WARN(active && crtc->pipe != pipe,
13607                                 "Encoder connected to wrong pipe %c\n",
13608                                 pipe_name(pipe));
13609
13610                 if (active)
13611                         encoder->get_config(encoder, pipe_config);
13612         }
13613
13614         intel_crtc_compute_pixel_rate(pipe_config);
13615
13616         if (!new_crtc_state->hw.active)
13617                 return;
13618
13619         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13620
13621         if (!intel_pipe_config_compare(new_crtc_state,
13622                                        pipe_config, false)) {
13623                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13624                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13625                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13626         }
13627 }
13628
13629 static void
13630 intel_verify_planes(struct intel_atomic_state *state)
13631 {
13632         struct intel_plane *plane;
13633         const struct intel_plane_state *plane_state;
13634         int i;
13635
13636         for_each_new_intel_plane_in_state(state, plane,
13637                                           plane_state, i)
13638                 assert_plane(plane, plane_state->planar_slave ||
13639                              plane_state->uapi.visible);
13640 }
13641
13642 static void
13643 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13644                          struct intel_shared_dpll *pll,
13645                          struct intel_crtc *crtc,
13646                          struct intel_crtc_state *new_crtc_state)
13647 {
13648         struct intel_dpll_hw_state dpll_hw_state;
13649         unsigned int crtc_mask;
13650         bool active;
13651
13652         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13653
13654         DRM_DEBUG_KMS("%s\n", pll->info->name);
13655
13656         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13657
13658         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13659                 I915_STATE_WARN(!pll->on && pll->active_mask,
13660                      "pll in active use but not on in sw tracking\n");
13661                 I915_STATE_WARN(pll->on && !pll->active_mask,
13662                      "pll is on but not used by any active crtc\n");
13663                 I915_STATE_WARN(pll->on != active,
13664                      "pll on state mismatch (expected %i, found %i)\n",
13665                      pll->on, active);
13666         }
13667
13668         if (!crtc) {
13669                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13670                                 "more active pll users than references: %x vs %x\n",
13671                                 pll->active_mask, pll->state.crtc_mask);
13672
13673                 return;
13674         }
13675
13676         crtc_mask = drm_crtc_mask(&crtc->base);
13677
13678         if (new_crtc_state->hw.active)
13679                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13680                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13681                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13682         else
13683                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13684                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13685                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13686
13687         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13688                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13689                         crtc_mask, pll->state.crtc_mask);
13690
13691         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13692                                           &dpll_hw_state,
13693                                           sizeof(dpll_hw_state)),
13694                         "pll hw state mismatch\n");
13695 }
13696
13697 static void
13698 verify_shared_dpll_state(struct intel_crtc *crtc,
13699                          struct intel_crtc_state *old_crtc_state,
13700                          struct intel_crtc_state *new_crtc_state)
13701 {
13702         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13703
13704         if (new_crtc_state->shared_dpll)
13705                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13706
13707         if (old_crtc_state->shared_dpll &&
13708             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13709                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13710                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13711
13712                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13713                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13714                                 pipe_name(drm_crtc_index(&crtc->base)));
13715                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13716                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13717                                 pipe_name(drm_crtc_index(&crtc->base)));
13718         }
13719 }
13720
13721 static void
13722 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13723                           struct intel_atomic_state *state,
13724                           struct intel_crtc_state *old_crtc_state,
13725                           struct intel_crtc_state *new_crtc_state)
13726 {
13727         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13728                 return;
13729
13730         verify_wm_state(crtc, new_crtc_state);
13731         verify_connector_state(state, crtc);
13732         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13733         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13734 }
13735
13736 static void
13737 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13738 {
13739         int i;
13740
13741         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13742                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13743 }
13744
13745 static void
13746 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13747                               struct intel_atomic_state *state)
13748 {
13749         verify_encoder_state(dev_priv, state);
13750         verify_connector_state(state, NULL);
13751         verify_disabled_dpll_state(dev_priv);
13752 }
13753
13754 static void
13755 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13756 {
13757         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13758         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13759         const struct drm_display_mode *adjusted_mode =
13760                 &crtc_state->hw.adjusted_mode;
13761
13762         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13763
13764         /*
13765          * The scanline counter increments at the leading edge of hsync.
13766          *
13767          * On most platforms it starts counting from vtotal-1 on the
13768          * first active line. That means the scanline counter value is
13769          * always one less than what we would expect. Ie. just after
13770          * start of vblank, which also occurs at start of hsync (on the
13771          * last active line), the scanline counter will read vblank_start-1.
13772          *
13773          * On gen2 the scanline counter starts counting from 1 instead
13774          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13775          * to keep the value positive), instead of adding one.
13776          *
13777          * On HSW+ the behaviour of the scanline counter depends on the output
13778          * type. For DP ports it behaves like most other platforms, but on HDMI
13779          * there's an extra 1 line difference. So we need to add two instead of
13780          * one to the value.
13781          *
13782          * On VLV/CHV DSI the scanline counter would appear to increment
13783          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13784          * that means we can't tell whether we're in vblank or not while
13785          * we're on that particular line. We must still set scanline_offset
13786          * to 1 so that the vblank timestamps come out correct when we query
13787          * the scanline counter from within the vblank interrupt handler.
13788          * However if queried just before the start of vblank we'll get an
13789          * answer that's slightly in the future.
13790          */
13791         if (IS_GEN(dev_priv, 2)) {
13792                 int vtotal;
13793
13794                 vtotal = adjusted_mode->crtc_vtotal;
13795                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13796                         vtotal /= 2;
13797
13798                 crtc->scanline_offset = vtotal - 1;
13799         } else if (HAS_DDI(dev_priv) &&
13800                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13801                 crtc->scanline_offset = 2;
13802         } else {
13803                 crtc->scanline_offset = 1;
13804         }
13805 }
13806
13807 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13808 {
13809         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13810         struct intel_crtc_state *new_crtc_state;
13811         struct intel_crtc *crtc;
13812         int i;
13813
13814         if (!dev_priv->display.crtc_compute_clock)
13815                 return;
13816
13817         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13818                 if (!needs_modeset(new_crtc_state))
13819                         continue;
13820
13821                 intel_release_shared_dplls(state, crtc);
13822         }
13823 }
13824
13825 /*
13826  * This implements the workaround described in the "notes" section of the mode
13827  * set sequence documentation. When going from no pipes or single pipe to
13828  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13829  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13830  */
13831 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13832 {
13833         struct intel_crtc_state *crtc_state;
13834         struct intel_crtc *crtc;
13835         struct intel_crtc_state *first_crtc_state = NULL;
13836         struct intel_crtc_state *other_crtc_state = NULL;
13837         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13838         int i;
13839
13840         /* look at all crtc's that are going to be enabled in during modeset */
13841         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13842                 if (!crtc_state->hw.active ||
13843                     !needs_modeset(crtc_state))
13844                         continue;
13845
13846                 if (first_crtc_state) {
13847                         other_crtc_state = crtc_state;
13848                         break;
13849                 } else {
13850                         first_crtc_state = crtc_state;
13851                         first_pipe = crtc->pipe;
13852                 }
13853         }
13854
13855         /* No workaround needed? */
13856         if (!first_crtc_state)
13857                 return 0;
13858
13859         /* w/a possibly needed, check how many crtc's are already enabled. */
13860         for_each_intel_crtc(state->base.dev, crtc) {
13861                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13862                 if (IS_ERR(crtc_state))
13863                         return PTR_ERR(crtc_state);
13864
13865                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13866
13867                 if (!crtc_state->hw.active ||
13868                     needs_modeset(crtc_state))
13869                         continue;
13870
13871                 /* 2 or more enabled crtcs means no need for w/a */
13872                 if (enabled_pipe != INVALID_PIPE)
13873                         return 0;
13874
13875                 enabled_pipe = crtc->pipe;
13876         }
13877
13878         if (enabled_pipe != INVALID_PIPE)
13879                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13880         else if (other_crtc_state)
13881                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13882
13883         return 0;
13884 }
13885
13886 static int intel_modeset_checks(struct intel_atomic_state *state)
13887 {
13888         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13889         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13890         struct intel_crtc *crtc;
13891         int ret, i;
13892
13893         /* keep the current setting */
13894         if (!state->cdclk.force_min_cdclk_changed)
13895                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13896
13897         state->modeset = true;
13898         state->active_pipes = dev_priv->active_pipes;
13899         state->cdclk.logical = dev_priv->cdclk.logical;
13900         state->cdclk.actual = dev_priv->cdclk.actual;
13901
13902         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13903                                             new_crtc_state, i) {
13904                 if (new_crtc_state->hw.active)
13905                         state->active_pipes |= BIT(crtc->pipe);
13906                 else
13907                         state->active_pipes &= ~BIT(crtc->pipe);
13908
13909                 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13910                         state->active_pipe_changes |= BIT(crtc->pipe);
13911         }
13912
13913         if (state->active_pipe_changes) {
13914                 ret = intel_atomic_lock_global_state(state);
13915                 if (ret)
13916                         return ret;
13917         }
13918
13919         ret = intel_modeset_calc_cdclk(state);
13920         if (ret)
13921                 return ret;
13922
13923         intel_modeset_clear_plls(state);
13924
13925         if (IS_HASWELL(dev_priv))
13926                 return haswell_mode_set_planes_workaround(state);
13927
13928         return 0;
13929 }
13930
13931 /*
13932  * Handle calculation of various watermark data at the end of the atomic check
13933  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13934  * handlers to ensure that all derived state has been updated.
13935  */
13936 static int calc_watermark_data(struct intel_atomic_state *state)
13937 {
13938         struct drm_device *dev = state->base.dev;
13939         struct drm_i915_private *dev_priv = to_i915(dev);
13940
13941         /* Is there platform-specific watermark information to calculate? */
13942         if (dev_priv->display.compute_global_watermarks)
13943                 return dev_priv->display.compute_global_watermarks(state);
13944
13945         return 0;
13946 }
13947
13948 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13949                                      struct intel_crtc_state *new_crtc_state)
13950 {
13951         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13952                 return;
13953
13954         new_crtc_state->uapi.mode_changed = false;
13955         new_crtc_state->update_pipe = true;
13956
13957         /*
13958          * If we're not doing the full modeset we want to
13959          * keep the current M/N values as they may be
13960          * sufficiently different to the computed values
13961          * to cause problems.
13962          *
13963          * FIXME: should really copy more fuzzy state here
13964          */
13965         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
13966         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
13967         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
13968         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
13969 }
13970
13971 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
13972                                           struct intel_crtc *crtc,
13973                                           u8 plane_ids_mask)
13974 {
13975         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13976         struct intel_plane *plane;
13977
13978         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13979                 struct intel_plane_state *plane_state;
13980
13981                 if ((plane_ids_mask & BIT(plane->id)) == 0)
13982                         continue;
13983
13984                 plane_state = intel_atomic_get_plane_state(state, plane);
13985                 if (IS_ERR(plane_state))
13986                         return PTR_ERR(plane_state);
13987         }
13988
13989         return 0;
13990 }
13991
13992 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
13993 {
13994         /* See {hsw,vlv,ivb}_plane_ratio() */
13995         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
13996                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13997                 IS_IVYBRIDGE(dev_priv);
13998 }
13999
14000 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14001                                      bool *need_modeset)
14002 {
14003         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14004         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14005         struct intel_plane_state *plane_state;
14006         struct intel_plane *plane;
14007         struct intel_crtc *crtc;
14008         int i, ret;
14009
14010         ret = icl_add_linked_planes(state);
14011         if (ret)
14012                 return ret;
14013
14014         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14015                 ret = intel_plane_atomic_check(state, plane);
14016                 if (ret) {
14017                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
14018                                          plane->base.base.id, plane->base.name);
14019                         return ret;
14020                 }
14021         }
14022
14023         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14024                                             new_crtc_state, i) {
14025                 u8 old_active_planes, new_active_planes;
14026
14027                 ret = icl_check_nv12_planes(new_crtc_state);
14028                 if (ret)
14029                         return ret;
14030
14031                 /*
14032                  * On some platforms the number of active planes affects
14033                  * the planes' minimum cdclk calculation. Add such planes
14034                  * to the state before we compute the minimum cdclk.
14035                  */
14036                 if (!active_planes_affects_min_cdclk(dev_priv))
14037                         continue;
14038
14039                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14040                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14041
14042                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14043                         continue;
14044
14045                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14046                 if (ret)
14047                         return ret;
14048         }
14049
14050         /*
14051          * active_planes bitmask has been updated, and potentially
14052          * affected planes are part of the state. We can now
14053          * compute the minimum cdclk for each plane.
14054          */
14055         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
14056                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
14057
14058         return 0;
14059 }
14060
14061 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14062 {
14063         struct intel_crtc_state *crtc_state;
14064         struct intel_crtc *crtc;
14065         int i;
14066
14067         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14068                 int ret = intel_crtc_atomic_check(state, crtc);
14069                 if (ret) {
14070                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14071                                          crtc->base.base.id, crtc->base.name);
14072                         return ret;
14073                 }
14074         }
14075
14076         return 0;
14077 }
14078
14079 /**
14080  * intel_atomic_check - validate state object
14081  * @dev: drm device
14082  * @_state: state to validate
14083  */
14084 static int intel_atomic_check(struct drm_device *dev,
14085                               struct drm_atomic_state *_state)
14086 {
14087         struct drm_i915_private *dev_priv = to_i915(dev);
14088         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14089         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14090         struct intel_crtc *crtc;
14091         int ret, i;
14092         bool any_ms = false;
14093
14094         /* Catch I915_MODE_FLAG_INHERITED */
14095         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14096                                             new_crtc_state, i) {
14097                 if (new_crtc_state->hw.mode.private_flags !=
14098                     old_crtc_state->hw.mode.private_flags)
14099                         new_crtc_state->uapi.mode_changed = true;
14100         }
14101
14102         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14103         if (ret)
14104                 goto fail;
14105
14106         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14107                                             new_crtc_state, i) {
14108                 if (!needs_modeset(new_crtc_state)) {
14109                         /* Light copy */
14110                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14111
14112                         continue;
14113                 }
14114
14115                 if (!new_crtc_state->uapi.enable) {
14116                         intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14117
14118                         any_ms = true;
14119                         continue;
14120                 }
14121
14122                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14123                 if (ret)
14124                         goto fail;
14125
14126                 ret = intel_modeset_pipe_config(new_crtc_state);
14127                 if (ret)
14128                         goto fail;
14129
14130                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14131
14132                 if (needs_modeset(new_crtc_state))
14133                         any_ms = true;
14134         }
14135
14136         if (any_ms && !check_digital_port_conflicts(state)) {
14137                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14138                 ret = EINVAL;
14139                 goto fail;
14140         }
14141
14142         ret = drm_dp_mst_atomic_check(&state->base);
14143         if (ret)
14144                 goto fail;
14145
14146         any_ms |= state->cdclk.force_min_cdclk_changed;
14147
14148         ret = intel_atomic_check_planes(state, &any_ms);
14149         if (ret)
14150                 goto fail;
14151
14152         if (any_ms) {
14153                 ret = intel_modeset_checks(state);
14154                 if (ret)
14155                         goto fail;
14156         } else {
14157                 state->cdclk.logical = dev_priv->cdclk.logical;
14158         }
14159
14160         ret = intel_atomic_check_crtcs(state);
14161         if (ret)
14162                 goto fail;
14163
14164         intel_fbc_choose_crtc(dev_priv, state);
14165         ret = calc_watermark_data(state);
14166         if (ret)
14167                 goto fail;
14168
14169         ret = intel_bw_atomic_check(state);
14170         if (ret)
14171                 goto fail;
14172
14173         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14174                                             new_crtc_state, i) {
14175                 if (!needs_modeset(new_crtc_state) &&
14176                     !new_crtc_state->update_pipe)
14177                         continue;
14178
14179                 intel_dump_pipe_config(new_crtc_state, state,
14180                                        needs_modeset(new_crtc_state) ?
14181                                        "[modeset]" : "[fastset]");
14182         }
14183
14184         return 0;
14185
14186  fail:
14187         if (ret == -EDEADLK)
14188                 return ret;
14189
14190         /*
14191          * FIXME would probably be nice to know which crtc specifically
14192          * caused the failure, in cases where we can pinpoint it.
14193          */
14194         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14195                                             new_crtc_state, i)
14196                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14197
14198         return ret;
14199 }
14200
14201 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14202 {
14203         return drm_atomic_helper_prepare_planes(state->base.dev,
14204                                                 &state->base);
14205 }
14206
14207 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14208 {
14209         struct drm_device *dev = crtc->base.dev;
14210         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14211
14212         if (!vblank->max_vblank_count)
14213                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14214
14215         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14216 }
14217
14218 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14219                                   struct intel_crtc_state *crtc_state)
14220 {
14221         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14222
14223         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
14224                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14225
14226         if (crtc_state->has_pch_encoder) {
14227                 enum pipe pch_transcoder =
14228                         intel_crtc_pch_transcoder(crtc);
14229
14230                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14231         }
14232 }
14233
14234 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14235                                const struct intel_crtc_state *new_crtc_state)
14236 {
14237         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14238         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14239
14240         /*
14241          * Update pipe size and adjust fitter if needed: the reason for this is
14242          * that in compute_mode_changes we check the native mode (not the pfit
14243          * mode) to see if we can flip rather than do a full mode set. In the
14244          * fastboot case, we'll flip, but if we don't update the pipesrc and
14245          * pfit state, we'll end up with a big fb scanned out into the wrong
14246          * sized surface.
14247          */
14248         intel_set_pipe_src_size(new_crtc_state);
14249
14250         /* on skylake this is done by detaching scalers */
14251         if (INTEL_GEN(dev_priv) >= 9) {
14252                 skl_detach_scalers(new_crtc_state);
14253
14254                 if (new_crtc_state->pch_pfit.enabled)
14255                         skylake_pfit_enable(new_crtc_state);
14256         } else if (HAS_PCH_SPLIT(dev_priv)) {
14257                 if (new_crtc_state->pch_pfit.enabled)
14258                         ironlake_pfit_enable(new_crtc_state);
14259                 else if (old_crtc_state->pch_pfit.enabled)
14260                         ironlake_pfit_disable(old_crtc_state);
14261         }
14262
14263         if (INTEL_GEN(dev_priv) >= 11)
14264                 icl_set_pipe_chicken(crtc);
14265 }
14266
14267 static void commit_pipe_config(struct intel_atomic_state *state,
14268                                struct intel_crtc_state *old_crtc_state,
14269                                struct intel_crtc_state *new_crtc_state)
14270 {
14271         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14272         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14273         bool modeset = needs_modeset(new_crtc_state);
14274
14275         /*
14276          * During modesets pipe configuration was programmed as the
14277          * CRTC was enabled.
14278          */
14279         if (!modeset) {
14280                 if (new_crtc_state->uapi.color_mgmt_changed ||
14281                     new_crtc_state->update_pipe)
14282                         intel_color_commit(new_crtc_state);
14283
14284                 if (INTEL_GEN(dev_priv) >= 9)
14285                         skl_detach_scalers(new_crtc_state);
14286
14287                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14288                         bdw_set_pipemisc(new_crtc_state);
14289
14290                 if (new_crtc_state->update_pipe)
14291                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14292         }
14293
14294         if (dev_priv->display.atomic_update_watermarks)
14295                 dev_priv->display.atomic_update_watermarks(state, crtc);
14296 }
14297
14298 static void intel_update_crtc(struct intel_crtc *crtc,
14299                               struct intel_atomic_state *state,
14300                               struct intel_crtc_state *old_crtc_state,
14301                               struct intel_crtc_state *new_crtc_state)
14302 {
14303         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14304         bool modeset = needs_modeset(new_crtc_state);
14305         struct intel_plane_state *new_plane_state =
14306                 intel_atomic_get_new_plane_state(state,
14307                                                  to_intel_plane(crtc->base.primary));
14308
14309         if (modeset) {
14310                 intel_crtc_update_active_timings(new_crtc_state);
14311
14312                 dev_priv->display.crtc_enable(state, crtc);
14313
14314                 /* vblanks work again, re-enable pipe CRC. */
14315                 intel_crtc_enable_pipe_crc(crtc);
14316         } else {
14317                 if (new_crtc_state->preload_luts &&
14318                     (new_crtc_state->uapi.color_mgmt_changed ||
14319                      new_crtc_state->update_pipe))
14320                         intel_color_load_luts(new_crtc_state);
14321
14322                 intel_pre_plane_update(state, crtc);
14323
14324                 if (new_crtc_state->update_pipe)
14325                         intel_encoders_update_pipe(state, crtc);
14326         }
14327
14328         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14329                 intel_fbc_disable(crtc);
14330         else if (new_plane_state)
14331                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14332
14333         /* Perform vblank evasion around commit operation */
14334         intel_pipe_update_start(new_crtc_state);
14335
14336         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14337
14338         if (INTEL_GEN(dev_priv) >= 9)
14339                 skl_update_planes_on_crtc(state, crtc);
14340         else
14341                 i9xx_update_planes_on_crtc(state, crtc);
14342
14343         intel_pipe_update_end(new_crtc_state);
14344
14345         /*
14346          * We usually enable FIFO underrun interrupts as part of the
14347          * CRTC enable sequence during modesets.  But when we inherit a
14348          * valid pipe configuration from the BIOS we need to take care
14349          * of enabling them on the CRTC's first fastset.
14350          */
14351         if (new_crtc_state->update_pipe && !modeset &&
14352             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14353                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14354 }
14355
14356 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14357 {
14358         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14359         enum transcoder slave_transcoder;
14360
14361         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14362
14363         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14364         return intel_get_crtc_for_pipe(dev_priv,
14365                                        (enum pipe)slave_transcoder);
14366 }
14367
14368 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14369                                           struct intel_crtc_state *old_crtc_state,
14370                                           struct intel_crtc_state *new_crtc_state,
14371                                           struct intel_crtc *crtc)
14372 {
14373         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14374
14375         intel_crtc_disable_planes(state, crtc);
14376
14377         /*
14378          * We need to disable pipe CRC before disabling the pipe,
14379          * or we race against vblank off.
14380          */
14381         intel_crtc_disable_pipe_crc(crtc);
14382
14383         dev_priv->display.crtc_disable(state, crtc);
14384         crtc->active = false;
14385         intel_fbc_disable(crtc);
14386         intel_disable_shared_dpll(old_crtc_state);
14387
14388         /* FIXME unify this for all platforms */
14389         if (!new_crtc_state->hw.active &&
14390             !HAS_GMCH(dev_priv) &&
14391             dev_priv->display.initial_watermarks)
14392                 dev_priv->display.initial_watermarks(state, crtc);
14393 }
14394
14395 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14396 {
14397         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14398         struct intel_crtc *crtc;
14399         u32 handled = 0;
14400         int i;
14401
14402         /* Only disable port sync slaves */
14403         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14404                                             new_crtc_state, i) {
14405                 if (!needs_modeset(new_crtc_state))
14406                         continue;
14407
14408                 if (!old_crtc_state->hw.active)
14409                         continue;
14410
14411                 /* In case of Transcoder port Sync master slave CRTCs can be
14412                  * assigned in any order and we need to make sure that
14413                  * slave CRTCs are disabled first and then master CRTC since
14414                  * Slave vblanks are masked till Master Vblanks.
14415                  */
14416                 if (!is_trans_port_sync_slave(old_crtc_state))
14417                         continue;
14418
14419                 intel_pre_plane_update(state, crtc);
14420                 intel_old_crtc_state_disables(state, old_crtc_state,
14421                                               new_crtc_state, crtc);
14422                 handled |= BIT(crtc->pipe);
14423         }
14424
14425         /* Disable everything else left on */
14426         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14427                                             new_crtc_state, i) {
14428                 if (!needs_modeset(new_crtc_state) ||
14429                     (handled & BIT(crtc->pipe)))
14430                         continue;
14431
14432                 intel_pre_plane_update(state, crtc);
14433                 if (old_crtc_state->hw.active)
14434                         intel_old_crtc_state_disables(state, old_crtc_state,
14435                                                       new_crtc_state, crtc);
14436         }
14437 }
14438
14439 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14440 {
14441         struct intel_crtc *crtc;
14442         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14443         int i;
14444
14445         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14446                 if (!new_crtc_state->hw.active)
14447                         continue;
14448
14449                 intel_update_crtc(crtc, state, old_crtc_state,
14450                                   new_crtc_state);
14451         }
14452 }
14453
14454 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14455                                               struct intel_atomic_state *state,
14456                                               struct intel_crtc_state *new_crtc_state)
14457 {
14458         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14459
14460         intel_crtc_update_active_timings(new_crtc_state);
14461         dev_priv->display.crtc_enable(state, crtc);
14462         intel_crtc_enable_pipe_crc(crtc);
14463 }
14464
14465 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14466                                        struct intel_atomic_state *state)
14467 {
14468         struct drm_connector *uninitialized_var(conn);
14469         struct drm_connector_state *conn_state;
14470         struct intel_dp *intel_dp;
14471         int i;
14472
14473         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14474                 if (conn_state->crtc == &crtc->base)
14475                         break;
14476         }
14477         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14478         intel_dp_stop_link_train(intel_dp);
14479 }
14480
14481 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14482                                            struct intel_atomic_state *state)
14483 {
14484         struct intel_crtc_state *new_crtc_state =
14485                 intel_atomic_get_new_crtc_state(state, crtc);
14486         struct intel_crtc_state *old_crtc_state =
14487                 intel_atomic_get_old_crtc_state(state, crtc);
14488         struct intel_plane_state *new_plane_state =
14489                 intel_atomic_get_new_plane_state(state,
14490                                                  to_intel_plane(crtc->base.primary));
14491         bool modeset = needs_modeset(new_crtc_state);
14492
14493         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14494                 intel_fbc_disable(crtc);
14495         else if (new_plane_state)
14496                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14497
14498         /* Perform vblank evasion around commit operation */
14499         intel_pipe_update_start(new_crtc_state);
14500         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14501         skl_update_planes_on_crtc(state, crtc);
14502         intel_pipe_update_end(new_crtc_state);
14503
14504         /*
14505          * We usually enable FIFO underrun interrupts as part of the
14506          * CRTC enable sequence during modesets.  But when we inherit a
14507          * valid pipe configuration from the BIOS we need to take care
14508          * of enabling them on the CRTC's first fastset.
14509          */
14510         if (new_crtc_state->update_pipe && !modeset &&
14511             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14512                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14513 }
14514
14515 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14516                                                struct intel_atomic_state *state,
14517                                                struct intel_crtc_state *old_crtc_state,
14518                                                struct intel_crtc_state *new_crtc_state)
14519 {
14520         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14521         struct intel_crtc_state *new_slave_crtc_state =
14522                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14523         struct intel_crtc_state *old_slave_crtc_state =
14524                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14525
14526         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14527                 !old_slave_crtc_state);
14528
14529         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14530                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14531                       slave_crtc->base.name);
14532
14533         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14534          * master is ready
14535          */
14536         intel_crtc_enable_trans_port_sync(slave_crtc,
14537                                           state,
14538                                           new_slave_crtc_state);
14539
14540         /* Enable seq for master with with DP_TP_CTL left Idle */
14541         intel_crtc_enable_trans_port_sync(crtc,
14542                                           state,
14543                                           new_crtc_state);
14544
14545         /* Set Slave's DP_TP_CTL to Normal */
14546         intel_set_dp_tp_ctl_normal(slave_crtc,
14547                                    state);
14548
14549         /* Set Master's DP_TP_CTL To Normal */
14550         usleep_range(200, 400);
14551         intel_set_dp_tp_ctl_normal(crtc,
14552                                    state);
14553
14554         /* Now do the post crtc enable for all master and slaves */
14555         intel_post_crtc_enable_updates(slave_crtc,
14556                                        state);
14557         intel_post_crtc_enable_updates(crtc,
14558                                        state);
14559 }
14560
14561 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14562 {
14563         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14564         struct intel_crtc *crtc;
14565         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14566         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14567         u8 required_slices = state->wm_results.ddb.enabled_slices;
14568         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14569         u8 dirty_pipes = 0;
14570         int i;
14571
14572         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14573                 /* ignore allocations for crtc's that have been turned off. */
14574                 if (!needs_modeset(new_crtc_state) && new_crtc_state->hw.active)
14575                         entries[i] = old_crtc_state->wm.skl.ddb;
14576                 if (new_crtc_state->hw.active)
14577                         dirty_pipes |= BIT(crtc->pipe);
14578         }
14579
14580         /* If 2nd DBuf slice required, enable it here */
14581         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14582                 icl_dbuf_slices_update(dev_priv, required_slices);
14583
14584         /*
14585          * Whenever the number of active pipes changes, we need to make sure we
14586          * update the pipes in the right order so that their ddb allocations
14587          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14588          * cause pipe underruns and other bad stuff.
14589          */
14590         while (dirty_pipes) {
14591                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14592                                                     new_crtc_state, i) {
14593                         enum pipe pipe = crtc->pipe;
14594                         bool modeset = needs_modeset(new_crtc_state);
14595
14596                         if ((dirty_pipes & BIT(pipe)) == 0)
14597                                 continue;
14598
14599                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14600                                                         entries,
14601                                                         INTEL_NUM_PIPES(dev_priv), i))
14602                                 continue;
14603
14604                         entries[i] = new_crtc_state->wm.skl.ddb;
14605                         dirty_pipes &= ~BIT(pipe);
14606
14607                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14608                                 if (is_trans_port_sync_master(new_crtc_state))
14609                                         intel_update_trans_port_sync_crtcs(crtc,
14610                                                                            state,
14611                                                                            old_crtc_state,
14612                                                                            new_crtc_state);
14613                                 else
14614                                         continue;
14615                         } else {
14616                                 intel_update_crtc(crtc, state, old_crtc_state,
14617                                                   new_crtc_state);
14618                         }
14619
14620                         /*
14621                          * If this is an already active pipe, it's DDB changed,
14622                          * and this isn't the last pipe that needs updating
14623                          * then we need to wait for a vblank to pass for the
14624                          * new ddb allocation to take effect.
14625                          */
14626                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14627                                                  &old_crtc_state->wm.skl.ddb) &&
14628                             !modeset && dirty_pipes)
14629                                 intel_wait_for_vblank(dev_priv, pipe);
14630                 }
14631         }
14632
14633         /* If 2nd DBuf slice is no more required disable it */
14634         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14635                 icl_dbuf_slices_update(dev_priv, required_slices);
14636 }
14637
14638 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14639 {
14640         struct intel_atomic_state *state, *next;
14641         struct llist_node *freed;
14642
14643         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14644         llist_for_each_entry_safe(state, next, freed, freed)
14645                 drm_atomic_state_put(&state->base);
14646 }
14647
14648 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14649 {
14650         struct drm_i915_private *dev_priv =
14651                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14652
14653         intel_atomic_helper_free_state(dev_priv);
14654 }
14655
14656 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14657 {
14658         struct wait_queue_entry wait_fence, wait_reset;
14659         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14660
14661         init_wait_entry(&wait_fence, 0);
14662         init_wait_entry(&wait_reset, 0);
14663         for (;;) {
14664                 prepare_to_wait(&intel_state->commit_ready.wait,
14665                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14666                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14667                                               I915_RESET_MODESET),
14668                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14669
14670
14671                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14672                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14673                         break;
14674
14675                 schedule();
14676         }
14677         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14678         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14679                                   I915_RESET_MODESET),
14680                     &wait_reset);
14681 }
14682
14683 static void intel_atomic_cleanup_work(struct work_struct *work)
14684 {
14685         struct drm_atomic_state *state =
14686                 container_of(work, struct drm_atomic_state, commit_work);
14687         struct drm_i915_private *i915 = to_i915(state->dev);
14688
14689         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14690         drm_atomic_helper_commit_cleanup_done(state);
14691         drm_atomic_state_put(state);
14692
14693         intel_atomic_helper_free_state(i915);
14694 }
14695
14696 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14697 {
14698         struct drm_device *dev = state->base.dev;
14699         struct drm_i915_private *dev_priv = to_i915(dev);
14700         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14701         struct intel_crtc *crtc;
14702         u64 put_domains[I915_MAX_PIPES] = {};
14703         intel_wakeref_t wakeref = 0;
14704         int i;
14705
14706         intel_atomic_commit_fence_wait(state);
14707
14708         drm_atomic_helper_wait_for_dependencies(&state->base);
14709
14710         if (state->modeset)
14711                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14712
14713         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14714                                             new_crtc_state, i) {
14715                 if (needs_modeset(new_crtc_state) ||
14716                     new_crtc_state->update_pipe) {
14717
14718                         put_domains[crtc->pipe] =
14719                                 modeset_get_crtc_power_domains(new_crtc_state);
14720                 }
14721         }
14722
14723         intel_commit_modeset_disables(state);
14724
14725         /* FIXME: Eventually get rid of our crtc->config pointer */
14726         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14727                 crtc->config = new_crtc_state;
14728
14729         if (state->modeset) {
14730                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14731
14732                 intel_set_cdclk_pre_plane_update(dev_priv,
14733                                                  &state->cdclk.actual,
14734                                                  &dev_priv->cdclk.actual,
14735                                                  state->cdclk.pipe);
14736
14737                 /*
14738                  * SKL workaround: bspec recommends we disable the SAGV when we
14739                  * have more then one pipe enabled
14740                  */
14741                 if (!intel_can_enable_sagv(state))
14742                         intel_disable_sagv(dev_priv);
14743
14744                 intel_modeset_verify_disabled(dev_priv, state);
14745         }
14746
14747         /* Complete the events for pipes that have now been disabled */
14748         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14749                 bool modeset = needs_modeset(new_crtc_state);
14750
14751                 /* Complete events for now disable pipes here. */
14752                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14753                         spin_lock_irq(&dev->event_lock);
14754                         drm_crtc_send_vblank_event(&crtc->base,
14755                                                    new_crtc_state->uapi.event);
14756                         spin_unlock_irq(&dev->event_lock);
14757
14758                         new_crtc_state->uapi.event = NULL;
14759                 }
14760         }
14761
14762         if (state->modeset)
14763                 intel_encoders_update_prepare(state);
14764
14765         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14766         dev_priv->display.commit_modeset_enables(state);
14767
14768         if (state->modeset) {
14769                 intel_encoders_update_complete(state);
14770
14771                 intel_set_cdclk_post_plane_update(dev_priv,
14772                                                   &state->cdclk.actual,
14773                                                   &dev_priv->cdclk.actual,
14774                                                   state->cdclk.pipe);
14775         }
14776
14777         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14778          * already, but still need the state for the delayed optimization. To
14779          * fix this:
14780          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14781          * - schedule that vblank worker _before_ calling hw_done
14782          * - at the start of commit_tail, cancel it _synchrously
14783          * - switch over to the vblank wait helper in the core after that since
14784          *   we don't need out special handling any more.
14785          */
14786         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14787
14788         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14789                 if (new_crtc_state->hw.active &&
14790                     !needs_modeset(new_crtc_state) &&
14791                     !new_crtc_state->preload_luts &&
14792                     (new_crtc_state->uapi.color_mgmt_changed ||
14793                      new_crtc_state->update_pipe))
14794                         intel_color_load_luts(new_crtc_state);
14795         }
14796
14797         /*
14798          * Now that the vblank has passed, we can go ahead and program the
14799          * optimal watermarks on platforms that need two-step watermark
14800          * programming.
14801          *
14802          * TODO: Move this (and other cleanup) to an async worker eventually.
14803          */
14804         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14805                                             new_crtc_state, i) {
14806                 /*
14807                  * Gen2 reports pipe underruns whenever all planes are disabled.
14808                  * So re-enable underrun reporting after some planes get enabled.
14809                  *
14810                  * We do this before .optimize_watermarks() so that we have a
14811                  * chance of catching underruns with the intermediate watermarks
14812                  * vs. the new plane configuration.
14813                  */
14814                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
14815                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14816
14817                 if (dev_priv->display.optimize_watermarks)
14818                         dev_priv->display.optimize_watermarks(state, crtc);
14819         }
14820
14821         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14822                 intel_post_plane_update(state, crtc);
14823
14824                 if (put_domains[i])
14825                         modeset_put_power_domains(dev_priv, put_domains[i]);
14826
14827                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14828         }
14829
14830         /* Underruns don't always raise interrupts, so check manually */
14831         intel_check_cpu_fifo_underruns(dev_priv);
14832         intel_check_pch_fifo_underruns(dev_priv);
14833
14834         if (state->modeset)
14835                 intel_verify_planes(state);
14836
14837         if (state->modeset && intel_can_enable_sagv(state))
14838                 intel_enable_sagv(dev_priv);
14839
14840         drm_atomic_helper_commit_hw_done(&state->base);
14841
14842         if (state->modeset) {
14843                 /* As one of the primary mmio accessors, KMS has a high
14844                  * likelihood of triggering bugs in unclaimed access. After we
14845                  * finish modesetting, see if an error has been flagged, and if
14846                  * so enable debugging for the next modeset - and hope we catch
14847                  * the culprit.
14848                  */
14849                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14850                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14851         }
14852         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14853
14854         /*
14855          * Defer the cleanup of the old state to a separate worker to not
14856          * impede the current task (userspace for blocking modesets) that
14857          * are executed inline. For out-of-line asynchronous modesets/flips,
14858          * deferring to a new worker seems overkill, but we would place a
14859          * schedule point (cond_resched()) here anyway to keep latencies
14860          * down.
14861          */
14862         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14863         queue_work(system_highpri_wq, &state->base.commit_work);
14864 }
14865
14866 static void intel_atomic_commit_work(struct work_struct *work)
14867 {
14868         struct intel_atomic_state *state =
14869                 container_of(work, struct intel_atomic_state, base.commit_work);
14870
14871         intel_atomic_commit_tail(state);
14872 }
14873
14874 static int __i915_sw_fence_call
14875 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14876                           enum i915_sw_fence_notify notify)
14877 {
14878         struct intel_atomic_state *state =
14879                 container_of(fence, struct intel_atomic_state, commit_ready);
14880
14881         switch (notify) {
14882         case FENCE_COMPLETE:
14883                 /* we do blocking waits in the worker, nothing to do here */
14884                 break;
14885         case FENCE_FREE:
14886                 {
14887                         struct intel_atomic_helper *helper =
14888                                 &to_i915(state->base.dev)->atomic_helper;
14889
14890                         if (llist_add(&state->freed, &helper->free_list))
14891                                 schedule_work(&helper->free_work);
14892                         break;
14893                 }
14894         }
14895
14896         return NOTIFY_DONE;
14897 }
14898
14899 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14900 {
14901         struct intel_plane_state *old_plane_state, *new_plane_state;
14902         struct intel_plane *plane;
14903         int i;
14904
14905         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14906                                              new_plane_state, i)
14907                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14908                                         to_intel_frontbuffer(new_plane_state->hw.fb),
14909                                         plane->frontbuffer_bit);
14910 }
14911
14912 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14913 {
14914         struct intel_crtc *crtc;
14915
14916         for_each_intel_crtc(&dev_priv->drm, crtc)
14917                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14918 }
14919
14920 static int intel_atomic_commit(struct drm_device *dev,
14921                                struct drm_atomic_state *_state,
14922                                bool nonblock)
14923 {
14924         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14925         struct drm_i915_private *dev_priv = to_i915(dev);
14926         int ret = 0;
14927
14928         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14929
14930         drm_atomic_state_get(&state->base);
14931         i915_sw_fence_init(&state->commit_ready,
14932                            intel_atomic_commit_ready);
14933
14934         /*
14935          * The intel_legacy_cursor_update() fast path takes care
14936          * of avoiding the vblank waits for simple cursor
14937          * movement and flips. For cursor on/off and size changes,
14938          * we want to perform the vblank waits so that watermark
14939          * updates happen during the correct frames. Gen9+ have
14940          * double buffered watermarks and so shouldn't need this.
14941          *
14942          * Unset state->legacy_cursor_update before the call to
14943          * drm_atomic_helper_setup_commit() because otherwise
14944          * drm_atomic_helper_wait_for_flip_done() is a noop and
14945          * we get FIFO underruns because we didn't wait
14946          * for vblank.
14947          *
14948          * FIXME doing watermarks and fb cleanup from a vblank worker
14949          * (assuming we had any) would solve these problems.
14950          */
14951         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14952                 struct intel_crtc_state *new_crtc_state;
14953                 struct intel_crtc *crtc;
14954                 int i;
14955
14956                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14957                         if (new_crtc_state->wm.need_postvbl_update ||
14958                             new_crtc_state->update_wm_post)
14959                                 state->base.legacy_cursor_update = false;
14960         }
14961
14962         ret = intel_atomic_prepare_commit(state);
14963         if (ret) {
14964                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14965                 i915_sw_fence_commit(&state->commit_ready);
14966                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14967                 return ret;
14968         }
14969
14970         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14971         if (!ret)
14972                 ret = drm_atomic_helper_swap_state(&state->base, true);
14973
14974         if (ret) {
14975                 i915_sw_fence_commit(&state->commit_ready);
14976
14977                 drm_atomic_helper_cleanup_planes(dev, &state->base);
14978                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14979                 return ret;
14980         }
14981         dev_priv->wm.distrust_bios_wm = false;
14982         intel_shared_dpll_swap_state(state);
14983         intel_atomic_track_fbs(state);
14984
14985         if (state->global_state_changed) {
14986                 assert_global_state_locked(dev_priv);
14987
14988                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
14989                        sizeof(state->min_cdclk));
14990                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
14991                        sizeof(state->min_voltage_level));
14992                 dev_priv->active_pipes = state->active_pipes;
14993                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
14994
14995                 intel_cdclk_swap_state(state);
14996         }
14997
14998         drm_atomic_state_get(&state->base);
14999         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15000
15001         i915_sw_fence_commit(&state->commit_ready);
15002         if (nonblock && state->modeset) {
15003                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15004         } else if (nonblock) {
15005                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15006         } else {
15007                 if (state->modeset)
15008                         flush_workqueue(dev_priv->modeset_wq);
15009                 intel_atomic_commit_tail(state);
15010         }
15011
15012         return 0;
15013 }
15014
15015 struct wait_rps_boost {
15016         struct wait_queue_entry wait;
15017
15018         struct drm_crtc *crtc;
15019         struct i915_request *request;
15020 };
15021
15022 static int do_rps_boost(struct wait_queue_entry *_wait,
15023                         unsigned mode, int sync, void *key)
15024 {
15025         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15026         struct i915_request *rq = wait->request;
15027
15028         /*
15029          * If we missed the vblank, but the request is already running it
15030          * is reasonable to assume that it will complete before the next
15031          * vblank without our intervention, so leave RPS alone.
15032          */
15033         if (!i915_request_started(rq))
15034                 intel_rps_boost(rq);
15035         i915_request_put(rq);
15036
15037         drm_crtc_vblank_put(wait->crtc);
15038
15039         list_del(&wait->wait.entry);
15040         kfree(wait);
15041         return 1;
15042 }
15043
15044 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15045                                        struct dma_fence *fence)
15046 {
15047         struct wait_rps_boost *wait;
15048
15049         if (!dma_fence_is_i915(fence))
15050                 return;
15051
15052         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15053                 return;
15054
15055         if (drm_crtc_vblank_get(crtc))
15056                 return;
15057
15058         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15059         if (!wait) {
15060                 drm_crtc_vblank_put(crtc);
15061                 return;
15062         }
15063
15064         wait->request = to_request(dma_fence_get(fence));
15065         wait->crtc = crtc;
15066
15067         wait->wait.func = do_rps_boost;
15068         wait->wait.flags = 0;
15069
15070         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15071 }
15072
15073 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15074 {
15075         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15076         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15077         struct drm_framebuffer *fb = plane_state->hw.fb;
15078         struct i915_vma *vma;
15079
15080         if (plane->id == PLANE_CURSOR &&
15081             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15082                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15083                 const int align = intel_cursor_alignment(dev_priv);
15084                 int err;
15085
15086                 err = i915_gem_object_attach_phys(obj, align);
15087                 if (err)
15088                         return err;
15089         }
15090
15091         vma = intel_pin_and_fence_fb_obj(fb,
15092                                          &plane_state->view,
15093                                          intel_plane_uses_fence(plane_state),
15094                                          &plane_state->flags);
15095         if (IS_ERR(vma))
15096                 return PTR_ERR(vma);
15097
15098         plane_state->vma = vma;
15099
15100         return 0;
15101 }
15102
15103 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15104 {
15105         struct i915_vma *vma;
15106
15107         vma = fetch_and_zero(&old_plane_state->vma);
15108         if (vma)
15109                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15110 }
15111
15112 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15113 {
15114         struct i915_sched_attr attr = {
15115                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15116         };
15117
15118         i915_gem_object_wait_priority(obj, 0, &attr);
15119 }
15120
15121 /**
15122  * intel_prepare_plane_fb - Prepare fb for usage on plane
15123  * @plane: drm plane to prepare for
15124  * @_new_plane_state: the plane state being prepared
15125  *
15126  * Prepares a framebuffer for usage on a display plane.  Generally this
15127  * involves pinning the underlying object and updating the frontbuffer tracking
15128  * bits.  Some older platforms need special physical address handling for
15129  * cursor planes.
15130  *
15131  * Returns 0 on success, negative error code on failure.
15132  */
15133 int
15134 intel_prepare_plane_fb(struct drm_plane *plane,
15135                        struct drm_plane_state *_new_plane_state)
15136 {
15137         struct intel_plane_state *new_plane_state =
15138                 to_intel_plane_state(_new_plane_state);
15139         struct intel_atomic_state *intel_state =
15140                 to_intel_atomic_state(new_plane_state->uapi.state);
15141         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15142         struct drm_framebuffer *fb = new_plane_state->hw.fb;
15143         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15144         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15145         int ret;
15146
15147         if (old_obj) {
15148                 struct intel_crtc_state *crtc_state =
15149                         intel_atomic_get_new_crtc_state(intel_state,
15150                                                         to_intel_crtc(plane->state->crtc));
15151
15152                 /* Big Hammer, we also need to ensure that any pending
15153                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15154                  * current scanout is retired before unpinning the old
15155                  * framebuffer. Note that we rely on userspace rendering
15156                  * into the buffer attached to the pipe they are waiting
15157                  * on. If not, userspace generates a GPU hang with IPEHR
15158                  * point to the MI_WAIT_FOR_EVENT.
15159                  *
15160                  * This should only fail upon a hung GPU, in which case we
15161                  * can safely continue.
15162                  */
15163                 if (needs_modeset(crtc_state)) {
15164                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15165                                                               old_obj->base.resv, NULL,
15166                                                               false, 0,
15167                                                               GFP_KERNEL);
15168                         if (ret < 0)
15169                                 return ret;
15170                 }
15171         }
15172
15173         if (new_plane_state->uapi.fence) { /* explicit fencing */
15174                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15175                                                     new_plane_state->uapi.fence,
15176                                                     I915_FENCE_TIMEOUT,
15177                                                     GFP_KERNEL);
15178                 if (ret < 0)
15179                         return ret;
15180         }
15181
15182         if (!obj)
15183                 return 0;
15184
15185         ret = i915_gem_object_pin_pages(obj);
15186         if (ret)
15187                 return ret;
15188
15189         ret = intel_plane_pin_fb(new_plane_state);
15190
15191         i915_gem_object_unpin_pages(obj);
15192         if (ret)
15193                 return ret;
15194
15195         fb_obj_bump_render_priority(obj);
15196         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
15197
15198         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15199                 struct dma_fence *fence;
15200
15201                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15202                                                       obj->base.resv, NULL,
15203                                                       false, I915_FENCE_TIMEOUT,
15204                                                       GFP_KERNEL);
15205                 if (ret < 0)
15206                         return ret;
15207
15208                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15209                 if (fence) {
15210                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15211                                                    fence);
15212                         dma_fence_put(fence);
15213                 }
15214         } else {
15215                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15216                                            new_plane_state->uapi.fence);
15217         }
15218
15219         /*
15220          * We declare pageflips to be interactive and so merit a small bias
15221          * towards upclocking to deliver the frame on time. By only changing
15222          * the RPS thresholds to sample more regularly and aim for higher
15223          * clocks we can hopefully deliver low power workloads (like kodi)
15224          * that are not quite steady state without resorting to forcing
15225          * maximum clocks following a vblank miss (see do_rps_boost()).
15226          */
15227         if (!intel_state->rps_interactive) {
15228                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15229                 intel_state->rps_interactive = true;
15230         }
15231
15232         return 0;
15233 }
15234
15235 /**
15236  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15237  * @plane: drm plane to clean up for
15238  * @_old_plane_state: the state from the previous modeset
15239  *
15240  * Cleans up a framebuffer that has just been removed from a plane.
15241  */
15242 void
15243 intel_cleanup_plane_fb(struct drm_plane *plane,
15244                        struct drm_plane_state *_old_plane_state)
15245 {
15246         struct intel_plane_state *old_plane_state =
15247                 to_intel_plane_state(_old_plane_state);
15248         struct intel_atomic_state *intel_state =
15249                 to_intel_atomic_state(old_plane_state->uapi.state);
15250         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15251
15252         if (intel_state->rps_interactive) {
15253                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15254                 intel_state->rps_interactive = false;
15255         }
15256
15257         /* Should only be called after a successful intel_prepare_plane_fb()! */
15258         intel_plane_unpin_fb(old_plane_state);
15259 }
15260
15261 /**
15262  * intel_plane_destroy - destroy a plane
15263  * @plane: plane to destroy
15264  *
15265  * Common destruction function for all types of planes (primary, cursor,
15266  * sprite).
15267  */
15268 void intel_plane_destroy(struct drm_plane *plane)
15269 {
15270         drm_plane_cleanup(plane);
15271         kfree(to_intel_plane(plane));
15272 }
15273
15274 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15275                                             u32 format, u64 modifier)
15276 {
15277         switch (modifier) {
15278         case DRM_FORMAT_MOD_LINEAR:
15279         case I915_FORMAT_MOD_X_TILED:
15280                 break;
15281         default:
15282                 return false;
15283         }
15284
15285         switch (format) {
15286         case DRM_FORMAT_C8:
15287         case DRM_FORMAT_RGB565:
15288         case DRM_FORMAT_XRGB1555:
15289         case DRM_FORMAT_XRGB8888:
15290                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15291                         modifier == I915_FORMAT_MOD_X_TILED;
15292         default:
15293                 return false;
15294         }
15295 }
15296
15297 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15298                                             u32 format, u64 modifier)
15299 {
15300         switch (modifier) {
15301         case DRM_FORMAT_MOD_LINEAR:
15302         case I915_FORMAT_MOD_X_TILED:
15303                 break;
15304         default:
15305                 return false;
15306         }
15307
15308         switch (format) {
15309         case DRM_FORMAT_C8:
15310         case DRM_FORMAT_RGB565:
15311         case DRM_FORMAT_XRGB8888:
15312         case DRM_FORMAT_XBGR8888:
15313         case DRM_FORMAT_ARGB8888:
15314         case DRM_FORMAT_ABGR8888:
15315         case DRM_FORMAT_XRGB2101010:
15316         case DRM_FORMAT_XBGR2101010:
15317         case DRM_FORMAT_ARGB2101010:
15318         case DRM_FORMAT_ABGR2101010:
15319         case DRM_FORMAT_XBGR16161616F:
15320                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15321                         modifier == I915_FORMAT_MOD_X_TILED;
15322         default:
15323                 return false;
15324         }
15325 }
15326
15327 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15328                                               u32 format, u64 modifier)
15329 {
15330         return modifier == DRM_FORMAT_MOD_LINEAR &&
15331                 format == DRM_FORMAT_ARGB8888;
15332 }
15333
15334 static const struct drm_plane_funcs i965_plane_funcs = {
15335         .update_plane = drm_atomic_helper_update_plane,
15336         .disable_plane = drm_atomic_helper_disable_plane,
15337         .destroy = intel_plane_destroy,
15338         .atomic_duplicate_state = intel_plane_duplicate_state,
15339         .atomic_destroy_state = intel_plane_destroy_state,
15340         .format_mod_supported = i965_plane_format_mod_supported,
15341 };
15342
15343 static const struct drm_plane_funcs i8xx_plane_funcs = {
15344         .update_plane = drm_atomic_helper_update_plane,
15345         .disable_plane = drm_atomic_helper_disable_plane,
15346         .destroy = intel_plane_destroy,
15347         .atomic_duplicate_state = intel_plane_duplicate_state,
15348         .atomic_destroy_state = intel_plane_destroy_state,
15349         .format_mod_supported = i8xx_plane_format_mod_supported,
15350 };
15351
15352 static int
15353 intel_legacy_cursor_update(struct drm_plane *_plane,
15354                            struct drm_crtc *_crtc,
15355                            struct drm_framebuffer *fb,
15356                            int crtc_x, int crtc_y,
15357                            unsigned int crtc_w, unsigned int crtc_h,
15358                            u32 src_x, u32 src_y,
15359                            u32 src_w, u32 src_h,
15360                            struct drm_modeset_acquire_ctx *ctx)
15361 {
15362         struct intel_plane *plane = to_intel_plane(_plane);
15363         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15364         struct intel_plane_state *old_plane_state =
15365                 to_intel_plane_state(plane->base.state);
15366         struct intel_plane_state *new_plane_state;
15367         struct intel_crtc_state *crtc_state =
15368                 to_intel_crtc_state(crtc->base.state);
15369         struct intel_crtc_state *new_crtc_state;
15370         int ret;
15371
15372         /*
15373          * When crtc is inactive or there is a modeset pending,
15374          * wait for it to complete in the slowpath
15375          */
15376         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15377             crtc_state->update_pipe)
15378                 goto slow;
15379
15380         /*
15381          * Don't do an async update if there is an outstanding commit modifying
15382          * the plane.  This prevents our async update's changes from getting
15383          * overridden by a previous synchronous update's state.
15384          */
15385         if (old_plane_state->uapi.commit &&
15386             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15387                 goto slow;
15388
15389         /*
15390          * If any parameters change that may affect watermarks,
15391          * take the slowpath. Only changing fb or position should be
15392          * in the fastpath.
15393          */
15394         if (old_plane_state->uapi.crtc != &crtc->base ||
15395             old_plane_state->uapi.src_w != src_w ||
15396             old_plane_state->uapi.src_h != src_h ||
15397             old_plane_state->uapi.crtc_w != crtc_w ||
15398             old_plane_state->uapi.crtc_h != crtc_h ||
15399             !old_plane_state->uapi.fb != !fb)
15400                 goto slow;
15401
15402         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15403         if (!new_plane_state)
15404                 return -ENOMEM;
15405
15406         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15407         if (!new_crtc_state) {
15408                 ret = -ENOMEM;
15409                 goto out_free;
15410         }
15411
15412         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15413
15414         new_plane_state->uapi.src_x = src_x;
15415         new_plane_state->uapi.src_y = src_y;
15416         new_plane_state->uapi.src_w = src_w;
15417         new_plane_state->uapi.src_h = src_h;
15418         new_plane_state->uapi.crtc_x = crtc_x;
15419         new_plane_state->uapi.crtc_y = crtc_y;
15420         new_plane_state->uapi.crtc_w = crtc_w;
15421         new_plane_state->uapi.crtc_h = crtc_h;
15422
15423         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15424                                                   old_plane_state, new_plane_state);
15425         if (ret)
15426                 goto out_free;
15427
15428         ret = intel_plane_pin_fb(new_plane_state);
15429         if (ret)
15430                 goto out_free;
15431
15432         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15433                                 ORIGIN_FLIP);
15434         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15435                                 to_intel_frontbuffer(new_plane_state->hw.fb),
15436                                 plane->frontbuffer_bit);
15437
15438         /* Swap plane state */
15439         plane->base.state = &new_plane_state->uapi;
15440
15441         /*
15442          * We cannot swap crtc_state as it may be in use by an atomic commit or
15443          * page flip that's running simultaneously. If we swap crtc_state and
15444          * destroy the old state, we will cause a use-after-free there.
15445          *
15446          * Only update active_planes, which is needed for our internal
15447          * bookkeeping. Either value will do the right thing when updating
15448          * planes atomically. If the cursor was part of the atomic update then
15449          * we would have taken the slowpath.
15450          */
15451         crtc_state->active_planes = new_crtc_state->active_planes;
15452
15453         if (new_plane_state->uapi.visible)
15454                 intel_update_plane(plane, crtc_state, new_plane_state);
15455         else
15456                 intel_disable_plane(plane, crtc_state);
15457
15458         intel_plane_unpin_fb(old_plane_state);
15459
15460 out_free:
15461         if (new_crtc_state)
15462                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15463         if (ret)
15464                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15465         else
15466                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15467         return ret;
15468
15469 slow:
15470         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15471                                               crtc_x, crtc_y, crtc_w, crtc_h,
15472                                               src_x, src_y, src_w, src_h, ctx);
15473 }
15474
15475 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15476         .update_plane = intel_legacy_cursor_update,
15477         .disable_plane = drm_atomic_helper_disable_plane,
15478         .destroy = intel_plane_destroy,
15479         .atomic_duplicate_state = intel_plane_duplicate_state,
15480         .atomic_destroy_state = intel_plane_destroy_state,
15481         .format_mod_supported = intel_cursor_format_mod_supported,
15482 };
15483
15484 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15485                                enum i9xx_plane_id i9xx_plane)
15486 {
15487         if (!HAS_FBC(dev_priv))
15488                 return false;
15489
15490         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15491                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15492         else if (IS_IVYBRIDGE(dev_priv))
15493                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15494                         i9xx_plane == PLANE_C;
15495         else if (INTEL_GEN(dev_priv) >= 4)
15496                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15497         else
15498                 return i9xx_plane == PLANE_A;
15499 }
15500
15501 static struct intel_plane *
15502 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15503 {
15504         struct intel_plane *plane;
15505         const struct drm_plane_funcs *plane_funcs;
15506         unsigned int supported_rotations;
15507         unsigned int possible_crtcs;
15508         const u32 *formats;
15509         int num_formats;
15510         int ret, zpos;
15511
15512         if (INTEL_GEN(dev_priv) >= 9)
15513                 return skl_universal_plane_create(dev_priv, pipe,
15514                                                   PLANE_PRIMARY);
15515
15516         plane = intel_plane_alloc();
15517         if (IS_ERR(plane))
15518                 return plane;
15519
15520         plane->pipe = pipe;
15521         /*
15522          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15523          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15524          */
15525         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15526                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15527         else
15528                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15529         plane->id = PLANE_PRIMARY;
15530         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15531
15532         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15533         if (plane->has_fbc) {
15534                 struct intel_fbc *fbc = &dev_priv->fbc;
15535
15536                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15537         }
15538
15539         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15540                 formats = vlv_primary_formats;
15541                 num_formats = ARRAY_SIZE(vlv_primary_formats);
15542         } else if (INTEL_GEN(dev_priv) >= 4) {
15543                 /*
15544                  * WaFP16GammaEnabling:ivb
15545                  * "Workaround : When using the 64-bit format, the plane
15546                  *  output on each color channel has one quarter amplitude.
15547                  *  It can be brought up to full amplitude by using pipe
15548                  *  gamma correction or pipe color space conversion to
15549                  *  multiply the plane output by four."
15550                  *
15551                  * There is no dedicated plane gamma for the primary plane,
15552                  * and using the pipe gamma/csc could conflict with other
15553                  * planes, so we choose not to expose fp16 on IVB primary
15554                  * planes. HSW primary planes no longer have this problem.
15555                  */
15556                 if (IS_IVYBRIDGE(dev_priv)) {
15557                         formats = ivb_primary_formats;
15558                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15559                 } else {
15560                         formats = i965_primary_formats;
15561                         num_formats = ARRAY_SIZE(i965_primary_formats);
15562                 }
15563         } else {
15564                 formats = i8xx_primary_formats;
15565                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15566         }
15567
15568         if (INTEL_GEN(dev_priv) >= 4)
15569                 plane_funcs = &i965_plane_funcs;
15570         else
15571                 plane_funcs = &i8xx_plane_funcs;
15572
15573         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15574                 plane->min_cdclk = vlv_plane_min_cdclk;
15575         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15576                 plane->min_cdclk = hsw_plane_min_cdclk;
15577         else if (IS_IVYBRIDGE(dev_priv))
15578                 plane->min_cdclk = ivb_plane_min_cdclk;
15579         else
15580                 plane->min_cdclk = i9xx_plane_min_cdclk;
15581
15582         plane->max_stride = i9xx_plane_max_stride;
15583         plane->update_plane = i9xx_update_plane;
15584         plane->disable_plane = i9xx_disable_plane;
15585         plane->get_hw_state = i9xx_plane_get_hw_state;
15586         plane->check_plane = i9xx_plane_check;
15587
15588         possible_crtcs = BIT(pipe);
15589
15590         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15591                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15592                                                possible_crtcs, plane_funcs,
15593                                                formats, num_formats,
15594                                                i9xx_format_modifiers,
15595                                                DRM_PLANE_TYPE_PRIMARY,
15596                                                "primary %c", pipe_name(pipe));
15597         else
15598                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15599                                                possible_crtcs, plane_funcs,
15600                                                formats, num_formats,
15601                                                i9xx_format_modifiers,
15602                                                DRM_PLANE_TYPE_PRIMARY,
15603                                                "plane %c",
15604                                                plane_name(plane->i9xx_plane));
15605         if (ret)
15606                 goto fail;
15607
15608         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15609                 supported_rotations =
15610                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15611                         DRM_MODE_REFLECT_X;
15612         } else if (INTEL_GEN(dev_priv) >= 4) {
15613                 supported_rotations =
15614                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15615         } else {
15616                 supported_rotations = DRM_MODE_ROTATE_0;
15617         }
15618
15619         if (INTEL_GEN(dev_priv) >= 4)
15620                 drm_plane_create_rotation_property(&plane->base,
15621                                                    DRM_MODE_ROTATE_0,
15622                                                    supported_rotations);
15623
15624         zpos = 0;
15625         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15626
15627         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15628
15629         return plane;
15630
15631 fail:
15632         intel_plane_free(plane);
15633
15634         return ERR_PTR(ret);
15635 }
15636
15637 static struct intel_plane *
15638 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15639                           enum pipe pipe)
15640 {
15641         unsigned int possible_crtcs;
15642         struct intel_plane *cursor;
15643         int ret, zpos;
15644
15645         cursor = intel_plane_alloc();
15646         if (IS_ERR(cursor))
15647                 return cursor;
15648
15649         cursor->pipe = pipe;
15650         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15651         cursor->id = PLANE_CURSOR;
15652         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15653
15654         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15655                 cursor->max_stride = i845_cursor_max_stride;
15656                 cursor->update_plane = i845_update_cursor;
15657                 cursor->disable_plane = i845_disable_cursor;
15658                 cursor->get_hw_state = i845_cursor_get_hw_state;
15659                 cursor->check_plane = i845_check_cursor;
15660         } else {
15661                 cursor->max_stride = i9xx_cursor_max_stride;
15662                 cursor->update_plane = i9xx_update_cursor;
15663                 cursor->disable_plane = i9xx_disable_cursor;
15664                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15665                 cursor->check_plane = i9xx_check_cursor;
15666         }
15667
15668         cursor->cursor.base = ~0;
15669         cursor->cursor.cntl = ~0;
15670
15671         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15672                 cursor->cursor.size = ~0;
15673
15674         possible_crtcs = BIT(pipe);
15675
15676         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15677                                        possible_crtcs, &intel_cursor_plane_funcs,
15678                                        intel_cursor_formats,
15679                                        ARRAY_SIZE(intel_cursor_formats),
15680                                        cursor_format_modifiers,
15681                                        DRM_PLANE_TYPE_CURSOR,
15682                                        "cursor %c", pipe_name(pipe));
15683         if (ret)
15684                 goto fail;
15685
15686         if (INTEL_GEN(dev_priv) >= 4)
15687                 drm_plane_create_rotation_property(&cursor->base,
15688                                                    DRM_MODE_ROTATE_0,
15689                                                    DRM_MODE_ROTATE_0 |
15690                                                    DRM_MODE_ROTATE_180);
15691
15692         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15693         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15694
15695         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15696
15697         return cursor;
15698
15699 fail:
15700         intel_plane_free(cursor);
15701
15702         return ERR_PTR(ret);
15703 }
15704
15705 #define INTEL_CRTC_FUNCS \
15706         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15707         .set_config = drm_atomic_helper_set_config, \
15708         .destroy = intel_crtc_destroy, \
15709         .page_flip = drm_atomic_helper_page_flip, \
15710         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15711         .atomic_destroy_state = intel_crtc_destroy_state, \
15712         .set_crc_source = intel_crtc_set_crc_source, \
15713         .verify_crc_source = intel_crtc_verify_crc_source, \
15714         .get_crc_sources = intel_crtc_get_crc_sources
15715
15716 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15717         INTEL_CRTC_FUNCS,
15718
15719         .get_vblank_counter = g4x_get_vblank_counter,
15720         .enable_vblank = bdw_enable_vblank,
15721         .disable_vblank = bdw_disable_vblank,
15722 };
15723
15724 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15725         INTEL_CRTC_FUNCS,
15726
15727         .get_vblank_counter = g4x_get_vblank_counter,
15728         .enable_vblank = ilk_enable_vblank,
15729         .disable_vblank = ilk_disable_vblank,
15730 };
15731
15732 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15733         INTEL_CRTC_FUNCS,
15734
15735         .get_vblank_counter = g4x_get_vblank_counter,
15736         .enable_vblank = i965_enable_vblank,
15737         .disable_vblank = i965_disable_vblank,
15738 };
15739
15740 static const struct drm_crtc_funcs i965_crtc_funcs = {
15741         INTEL_CRTC_FUNCS,
15742
15743         .get_vblank_counter = i915_get_vblank_counter,
15744         .enable_vblank = i965_enable_vblank,
15745         .disable_vblank = i965_disable_vblank,
15746 };
15747
15748 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15749         INTEL_CRTC_FUNCS,
15750
15751         .get_vblank_counter = i915_get_vblank_counter,
15752         .enable_vblank = i915gm_enable_vblank,
15753         .disable_vblank = i915gm_disable_vblank,
15754 };
15755
15756 static const struct drm_crtc_funcs i915_crtc_funcs = {
15757         INTEL_CRTC_FUNCS,
15758
15759         .get_vblank_counter = i915_get_vblank_counter,
15760         .enable_vblank = i8xx_enable_vblank,
15761         .disable_vblank = i8xx_disable_vblank,
15762 };
15763
15764 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15765         INTEL_CRTC_FUNCS,
15766
15767         /* no hw vblank counter */
15768         .enable_vblank = i8xx_enable_vblank,
15769         .disable_vblank = i8xx_disable_vblank,
15770 };
15771
15772 static struct intel_crtc *intel_crtc_alloc(void)
15773 {
15774         struct intel_crtc_state *crtc_state;
15775         struct intel_crtc *crtc;
15776
15777         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
15778         if (!crtc)
15779                 return ERR_PTR(-ENOMEM);
15780
15781         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15782         if (!crtc_state) {
15783                 kfree(crtc);
15784                 return ERR_PTR(-ENOMEM);
15785         }
15786
15787         intel_crtc_state_reset(crtc_state, crtc);
15788
15789         crtc->base.state = &crtc_state->uapi;
15790         crtc->config = crtc_state;
15791
15792         return crtc;
15793 }
15794
15795 static void intel_crtc_free(struct intel_crtc *crtc)
15796 {
15797         intel_crtc_destroy_state(&crtc->base, crtc->base.state);
15798         kfree(crtc);
15799 }
15800
15801 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15802 {
15803         struct intel_plane *primary, *cursor;
15804         const struct drm_crtc_funcs *funcs;
15805         struct intel_crtc *crtc;
15806         int sprite, ret;
15807
15808         crtc = intel_crtc_alloc();
15809         if (IS_ERR(crtc))
15810                 return PTR_ERR(crtc);
15811
15812         crtc->pipe = pipe;
15813         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
15814
15815         primary = intel_primary_plane_create(dev_priv, pipe);
15816         if (IS_ERR(primary)) {
15817                 ret = PTR_ERR(primary);
15818                 goto fail;
15819         }
15820         crtc->plane_ids_mask |= BIT(primary->id);
15821
15822         for_each_sprite(dev_priv, pipe, sprite) {
15823                 struct intel_plane *plane;
15824
15825                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15826                 if (IS_ERR(plane)) {
15827                         ret = PTR_ERR(plane);
15828                         goto fail;
15829                 }
15830                 crtc->plane_ids_mask |= BIT(plane->id);
15831         }
15832
15833         cursor = intel_cursor_plane_create(dev_priv, pipe);
15834         if (IS_ERR(cursor)) {
15835                 ret = PTR_ERR(cursor);
15836                 goto fail;
15837         }
15838         crtc->plane_ids_mask |= BIT(cursor->id);
15839
15840         if (HAS_GMCH(dev_priv)) {
15841                 if (IS_CHERRYVIEW(dev_priv) ||
15842                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15843                         funcs = &g4x_crtc_funcs;
15844                 else if (IS_GEN(dev_priv, 4))
15845                         funcs = &i965_crtc_funcs;
15846                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15847                         funcs = &i915gm_crtc_funcs;
15848                 else if (IS_GEN(dev_priv, 3))
15849                         funcs = &i915_crtc_funcs;
15850                 else
15851                         funcs = &i8xx_crtc_funcs;
15852         } else {
15853                 if (INTEL_GEN(dev_priv) >= 8)
15854                         funcs = &bdw_crtc_funcs;
15855                 else
15856                         funcs = &ilk_crtc_funcs;
15857         }
15858
15859         ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
15860                                         &primary->base, &cursor->base,
15861                                         funcs, "pipe %c", pipe_name(pipe));
15862         if (ret)
15863                 goto fail;
15864
15865         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15866                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15867         dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
15868
15869         if (INTEL_GEN(dev_priv) < 9) {
15870                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15871
15872                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15873                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15874                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
15875         }
15876
15877         intel_color_init(crtc);
15878
15879         WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe);
15880
15881         return 0;
15882
15883 fail:
15884         intel_crtc_free(crtc);
15885
15886         return ret;
15887 }
15888
15889 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15890                                       struct drm_file *file)
15891 {
15892         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15893         struct drm_crtc *drmmode_crtc;
15894         struct intel_crtc *crtc;
15895
15896         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15897         if (!drmmode_crtc)
15898                 return -ENOENT;
15899
15900         crtc = to_intel_crtc(drmmode_crtc);
15901         pipe_from_crtc_id->pipe = crtc->pipe;
15902
15903         return 0;
15904 }
15905
15906 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15907 {
15908         struct drm_device *dev = encoder->base.dev;
15909         struct intel_encoder *source_encoder;
15910         u32 possible_clones = 0;
15911
15912         for_each_intel_encoder(dev, source_encoder) {
15913                 if (encoders_cloneable(encoder, source_encoder))
15914                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15915         }
15916
15917         return possible_clones;
15918 }
15919
15920 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
15921 {
15922         struct drm_device *dev = encoder->base.dev;
15923         struct intel_crtc *crtc;
15924         u32 possible_crtcs = 0;
15925
15926         for_each_intel_crtc(dev, crtc) {
15927                 if (encoder->pipe_mask & BIT(crtc->pipe))
15928                         possible_crtcs |= drm_crtc_mask(&crtc->base);
15929         }
15930
15931         return possible_crtcs;
15932 }
15933
15934 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
15935 {
15936         if (!IS_MOBILE(dev_priv))
15937                 return false;
15938
15939         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15940                 return false;
15941
15942         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15943                 return false;
15944
15945         return true;
15946 }
15947
15948 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
15949 {
15950         if (INTEL_GEN(dev_priv) >= 9)
15951                 return false;
15952
15953         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15954                 return false;
15955
15956         if (HAS_PCH_LPT_H(dev_priv) &&
15957             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15958                 return false;
15959
15960         /* DDI E can't be used if DDI A requires 4 lanes */
15961         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15962                 return false;
15963
15964         if (!dev_priv->vbt.int_crt_support)
15965                 return false;
15966
15967         return true;
15968 }
15969
15970 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15971 {
15972         int pps_num;
15973         int pps_idx;
15974
15975         if (HAS_DDI(dev_priv))
15976                 return;
15977         /*
15978          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15979          * everywhere where registers can be write protected.
15980          */
15981         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15982                 pps_num = 2;
15983         else
15984                 pps_num = 1;
15985
15986         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15987                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15988
15989                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15990                 I915_WRITE(PP_CONTROL(pps_idx), val);
15991         }
15992 }
15993
15994 static void intel_pps_init(struct drm_i915_private *dev_priv)
15995 {
15996         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15997                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15998         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15999                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16000         else
16001                 dev_priv->pps_mmio_base = PPS_BASE;
16002
16003         intel_pps_unlock_regs_wa(dev_priv);
16004 }
16005
16006 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16007 {
16008         struct intel_encoder *encoder;
16009         bool dpd_is_edp = false;
16010
16011         intel_pps_init(dev_priv);
16012
16013         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16014                 return;
16015
16016         if (INTEL_GEN(dev_priv) >= 12) {
16017                 intel_ddi_init(dev_priv, PORT_A);
16018                 intel_ddi_init(dev_priv, PORT_B);
16019                 intel_ddi_init(dev_priv, PORT_D);
16020                 intel_ddi_init(dev_priv, PORT_E);
16021                 intel_ddi_init(dev_priv, PORT_F);
16022                 intel_ddi_init(dev_priv, PORT_G);
16023                 intel_ddi_init(dev_priv, PORT_H);
16024                 intel_ddi_init(dev_priv, PORT_I);
16025                 icl_dsi_init(dev_priv);
16026         } else if (IS_ELKHARTLAKE(dev_priv)) {
16027                 intel_ddi_init(dev_priv, PORT_A);
16028                 intel_ddi_init(dev_priv, PORT_B);
16029                 intel_ddi_init(dev_priv, PORT_C);
16030                 intel_ddi_init(dev_priv, PORT_D);
16031                 icl_dsi_init(dev_priv);
16032         } else if (IS_GEN(dev_priv, 11)) {
16033                 intel_ddi_init(dev_priv, PORT_A);
16034                 intel_ddi_init(dev_priv, PORT_B);
16035                 intel_ddi_init(dev_priv, PORT_C);
16036                 intel_ddi_init(dev_priv, PORT_D);
16037                 intel_ddi_init(dev_priv, PORT_E);
16038                 /*
16039                  * On some ICL SKUs port F is not present. No strap bits for
16040                  * this, so rely on VBT.
16041                  * Work around broken VBTs on SKUs known to have no port F.
16042                  */
16043                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16044                     intel_bios_is_port_present(dev_priv, PORT_F))
16045                         intel_ddi_init(dev_priv, PORT_F);
16046
16047                 icl_dsi_init(dev_priv);
16048         } else if (IS_GEN9_LP(dev_priv)) {
16049                 /*
16050                  * FIXME: Broxton doesn't support port detection via the
16051                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16052                  * detect the ports.
16053                  */
16054                 intel_ddi_init(dev_priv, PORT_A);
16055                 intel_ddi_init(dev_priv, PORT_B);
16056                 intel_ddi_init(dev_priv, PORT_C);
16057
16058                 vlv_dsi_init(dev_priv);
16059         } else if (HAS_DDI(dev_priv)) {
16060                 int found;
16061
16062                 if (intel_ddi_crt_present(dev_priv))
16063                         intel_crt_init(dev_priv);
16064
16065                 /*
16066                  * Haswell uses DDI functions to detect digital outputs.
16067                  * On SKL pre-D0 the strap isn't connected, so we assume
16068                  * it's there.
16069                  */
16070                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16071                 /* WaIgnoreDDIAStrap: skl */
16072                 if (found || IS_GEN9_BC(dev_priv))
16073                         intel_ddi_init(dev_priv, PORT_A);
16074
16075                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16076                  * register */
16077                 found = I915_READ(SFUSE_STRAP);
16078
16079                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16080                         intel_ddi_init(dev_priv, PORT_B);
16081                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16082                         intel_ddi_init(dev_priv, PORT_C);
16083                 if (found & SFUSE_STRAP_DDID_DETECTED)
16084                         intel_ddi_init(dev_priv, PORT_D);
16085                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16086                         intel_ddi_init(dev_priv, PORT_F);
16087                 /*
16088                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16089                  */
16090                 if (IS_GEN9_BC(dev_priv) &&
16091                     intel_bios_is_port_present(dev_priv, PORT_E))
16092                         intel_ddi_init(dev_priv, PORT_E);
16093
16094         } else if (HAS_PCH_SPLIT(dev_priv)) {
16095                 int found;
16096
16097                 /*
16098                  * intel_edp_init_connector() depends on this completing first,
16099                  * to prevent the registration of both eDP and LVDS and the
16100                  * incorrect sharing of the PPS.
16101                  */
16102                 intel_lvds_init(dev_priv);
16103                 intel_crt_init(dev_priv);
16104
16105                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16106
16107                 if (ilk_has_edp_a(dev_priv))
16108                         intel_dp_init(dev_priv, DP_A, PORT_A);
16109
16110                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16111                         /* PCH SDVOB multiplex with HDMIB */
16112                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16113                         if (!found)
16114                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16115                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16116                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16117                 }
16118
16119                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16120                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16121
16122                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16123                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16124
16125                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16126                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16127
16128                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16129                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16130         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16131                 bool has_edp, has_port;
16132
16133                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16134                         intel_crt_init(dev_priv);
16135
16136                 /*
16137                  * The DP_DETECTED bit is the latched state of the DDC
16138                  * SDA pin at boot. However since eDP doesn't require DDC
16139                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16140                  * eDP ports may have been muxed to an alternate function.
16141                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16142                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16143                  * detect eDP ports.
16144                  *
16145                  * Sadly the straps seem to be missing sometimes even for HDMI
16146                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16147                  * and VBT for the presence of the port. Additionally we can't
16148                  * trust the port type the VBT declares as we've seen at least
16149                  * HDMI ports that the VBT claim are DP or eDP.
16150                  */
16151                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16152                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16153                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16154                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16155                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16156                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16157
16158                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16159                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16160                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16161                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16162                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16163                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16164
16165                 if (IS_CHERRYVIEW(dev_priv)) {
16166                         /*
16167                          * eDP not supported on port D,
16168                          * so no need to worry about it
16169                          */
16170                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16171                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16172                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16173                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16174                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16175                 }
16176
16177                 vlv_dsi_init(dev_priv);
16178         } else if (IS_PINEVIEW(dev_priv)) {
16179                 intel_lvds_init(dev_priv);
16180                 intel_crt_init(dev_priv);
16181         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16182                 bool found = false;
16183
16184                 if (IS_MOBILE(dev_priv))
16185                         intel_lvds_init(dev_priv);
16186
16187                 intel_crt_init(dev_priv);
16188
16189                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16190                         DRM_DEBUG_KMS("probing SDVOB\n");
16191                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16192                         if (!found && IS_G4X(dev_priv)) {
16193                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16194                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16195                         }
16196
16197                         if (!found && IS_G4X(dev_priv))
16198                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16199                 }
16200
16201                 /* Before G4X SDVOC doesn't have its own detect register */
16202
16203                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16204                         DRM_DEBUG_KMS("probing SDVOC\n");
16205                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16206                 }
16207
16208                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16209
16210                         if (IS_G4X(dev_priv)) {
16211                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16212                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16213                         }
16214                         if (IS_G4X(dev_priv))
16215                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16216                 }
16217
16218                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16219                         intel_dp_init(dev_priv, DP_D, PORT_D);
16220
16221                 if (SUPPORTS_TV(dev_priv))
16222                         intel_tv_init(dev_priv);
16223         } else if (IS_GEN(dev_priv, 2)) {
16224                 if (IS_I85X(dev_priv))
16225                         intel_lvds_init(dev_priv);
16226
16227                 intel_crt_init(dev_priv);
16228                 intel_dvo_init(dev_priv);
16229         }
16230
16231         intel_psr_init(dev_priv);
16232
16233         for_each_intel_encoder(&dev_priv->drm, encoder) {
16234                 encoder->base.possible_crtcs =
16235                         intel_encoder_possible_crtcs(encoder);
16236                 encoder->base.possible_clones =
16237                         intel_encoder_possible_clones(encoder);
16238         }
16239
16240         intel_init_pch_refclk(dev_priv);
16241
16242         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16243 }
16244
16245 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16246 {
16247         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16248
16249         drm_framebuffer_cleanup(fb);
16250         intel_frontbuffer_put(intel_fb->frontbuffer);
16251
16252         kfree(intel_fb);
16253 }
16254
16255 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16256                                                 struct drm_file *file,
16257                                                 unsigned int *handle)
16258 {
16259         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16260
16261         if (obj->userptr.mm) {
16262                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16263                 return -EINVAL;
16264         }
16265
16266         return drm_gem_handle_create(file, &obj->base, handle);
16267 }
16268
16269 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16270                                         struct drm_file *file,
16271                                         unsigned flags, unsigned color,
16272                                         struct drm_clip_rect *clips,
16273                                         unsigned num_clips)
16274 {
16275         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16276
16277         i915_gem_object_flush_if_display(obj);
16278         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16279
16280         return 0;
16281 }
16282
16283 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16284         .destroy = intel_user_framebuffer_destroy,
16285         .create_handle = intel_user_framebuffer_create_handle,
16286         .dirty = intel_user_framebuffer_dirty,
16287 };
16288
16289 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16290                                   struct drm_i915_gem_object *obj,
16291                                   struct drm_mode_fb_cmd2 *mode_cmd)
16292 {
16293         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16294         struct drm_framebuffer *fb = &intel_fb->base;
16295         u32 max_stride;
16296         unsigned int tiling, stride;
16297         int ret = -EINVAL;
16298         int i;
16299
16300         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16301         if (!intel_fb->frontbuffer)
16302                 return -ENOMEM;
16303
16304         i915_gem_object_lock(obj);
16305         tiling = i915_gem_object_get_tiling(obj);
16306         stride = i915_gem_object_get_stride(obj);
16307         i915_gem_object_unlock(obj);
16308
16309         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16310                 /*
16311                  * If there's a fence, enforce that
16312                  * the fb modifier and tiling mode match.
16313                  */
16314                 if (tiling != I915_TILING_NONE &&
16315                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16316                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16317                         goto err;
16318                 }
16319         } else {
16320                 if (tiling == I915_TILING_X) {
16321                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16322                 } else if (tiling == I915_TILING_Y) {
16323                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16324                         goto err;
16325                 }
16326         }
16327
16328         if (!drm_any_plane_has_format(&dev_priv->drm,
16329                                       mode_cmd->pixel_format,
16330                                       mode_cmd->modifier[0])) {
16331                 struct drm_format_name_buf format_name;
16332
16333                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16334                               drm_get_format_name(mode_cmd->pixel_format,
16335                                                   &format_name),
16336                               mode_cmd->modifier[0]);
16337                 goto err;
16338         }
16339
16340         /*
16341          * gen2/3 display engine uses the fence if present,
16342          * so the tiling mode must match the fb modifier exactly.
16343          */
16344         if (INTEL_GEN(dev_priv) < 4 &&
16345             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16346                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16347                 goto err;
16348         }
16349
16350         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16351                                          mode_cmd->modifier[0]);
16352         if (mode_cmd->pitches[0] > max_stride) {
16353                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16354                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16355                               "tiled" : "linear",
16356                               mode_cmd->pitches[0], max_stride);
16357                 goto err;
16358         }
16359
16360         /*
16361          * If there's a fence, enforce that
16362          * the fb pitch and fence stride match.
16363          */
16364         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16365                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16366                               mode_cmd->pitches[0], stride);
16367                 goto err;
16368         }
16369
16370         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16371         if (mode_cmd->offsets[0] != 0)
16372                 goto err;
16373
16374         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16375
16376         for (i = 0; i < fb->format->num_planes; i++) {
16377                 u32 stride_alignment;
16378
16379                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16380                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16381                         goto err;
16382                 }
16383
16384                 stride_alignment = intel_fb_stride_alignment(fb, i);
16385
16386                 /*
16387                  * Display WA #0531: skl,bxt,kbl,glk
16388                  *
16389                  * Render decompression and plane width > 3840
16390                  * combined with horizontal panning requires the
16391                  * plane stride to be a multiple of 4. We'll just
16392                  * require the entire fb to accommodate that to avoid
16393                  * potential runtime errors at plane configuration time.
16394                  */
16395                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16396                     is_ccs_modifier(fb->modifier))
16397                         stride_alignment *= 4;
16398
16399                 if (fb->pitches[i] & (stride_alignment - 1)) {
16400                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16401                                       i, fb->pitches[i], stride_alignment);
16402                         goto err;
16403                 }
16404
16405                 fb->obj[i] = &obj->base;
16406         }
16407
16408         ret = intel_fill_fb_info(dev_priv, fb);
16409         if (ret)
16410                 goto err;
16411
16412         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16413         if (ret) {
16414                 DRM_ERROR("framebuffer init failed %d\n", ret);
16415                 goto err;
16416         }
16417
16418         return 0;
16419
16420 err:
16421         intel_frontbuffer_put(intel_fb->frontbuffer);
16422         return ret;
16423 }
16424
16425 static struct drm_framebuffer *
16426 intel_user_framebuffer_create(struct drm_device *dev,
16427                               struct drm_file *filp,
16428                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16429 {
16430         struct drm_framebuffer *fb;
16431         struct drm_i915_gem_object *obj;
16432         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16433
16434         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16435         if (!obj)
16436                 return ERR_PTR(-ENOENT);
16437
16438         fb = intel_framebuffer_create(obj, &mode_cmd);
16439         i915_gem_object_put(obj);
16440
16441         return fb;
16442 }
16443
16444 static void intel_atomic_state_free(struct drm_atomic_state *state)
16445 {
16446         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16447
16448         drm_atomic_state_default_release(state);
16449
16450         i915_sw_fence_fini(&intel_state->commit_ready);
16451
16452         kfree(state);
16453 }
16454
16455 static enum drm_mode_status
16456 intel_mode_valid(struct drm_device *dev,
16457                  const struct drm_display_mode *mode)
16458 {
16459         struct drm_i915_private *dev_priv = to_i915(dev);
16460         int hdisplay_max, htotal_max;
16461         int vdisplay_max, vtotal_max;
16462
16463         /*
16464          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16465          * of DBLSCAN modes to the output's mode list when they detect
16466          * the scaling mode property on the connector. And they don't
16467          * ask the kernel to validate those modes in any way until
16468          * modeset time at which point the client gets a protocol error.
16469          * So in order to not upset those clients we silently ignore the
16470          * DBLSCAN flag on such connectors. For other connectors we will
16471          * reject modes with the DBLSCAN flag in encoder->compute_config().
16472          * And we always reject DBLSCAN modes in connector->mode_valid()
16473          * as we never want such modes on the connector's mode list.
16474          */
16475
16476         if (mode->vscan > 1)
16477                 return MODE_NO_VSCAN;
16478
16479         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16480                 return MODE_H_ILLEGAL;
16481
16482         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16483                            DRM_MODE_FLAG_NCSYNC |
16484                            DRM_MODE_FLAG_PCSYNC))
16485                 return MODE_HSYNC;
16486
16487         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16488                            DRM_MODE_FLAG_PIXMUX |
16489                            DRM_MODE_FLAG_CLKDIV2))
16490                 return MODE_BAD;
16491
16492         /* Transcoder timing limits */
16493         if (INTEL_GEN(dev_priv) >= 11) {
16494                 hdisplay_max = 16384;
16495                 vdisplay_max = 8192;
16496                 htotal_max = 16384;
16497                 vtotal_max = 8192;
16498         } else if (INTEL_GEN(dev_priv) >= 9 ||
16499                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16500                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16501                 vdisplay_max = 4096;
16502                 htotal_max = 8192;
16503                 vtotal_max = 8192;
16504         } else if (INTEL_GEN(dev_priv) >= 3) {
16505                 hdisplay_max = 4096;
16506                 vdisplay_max = 4096;
16507                 htotal_max = 8192;
16508                 vtotal_max = 8192;
16509         } else {
16510                 hdisplay_max = 2048;
16511                 vdisplay_max = 2048;
16512                 htotal_max = 4096;
16513                 vtotal_max = 4096;
16514         }
16515
16516         if (mode->hdisplay > hdisplay_max ||
16517             mode->hsync_start > htotal_max ||
16518             mode->hsync_end > htotal_max ||
16519             mode->htotal > htotal_max)
16520                 return MODE_H_ILLEGAL;
16521
16522         if (mode->vdisplay > vdisplay_max ||
16523             mode->vsync_start > vtotal_max ||
16524             mode->vsync_end > vtotal_max ||
16525             mode->vtotal > vtotal_max)
16526                 return MODE_V_ILLEGAL;
16527
16528         if (INTEL_GEN(dev_priv) >= 5) {
16529                 if (mode->hdisplay < 64 ||
16530                     mode->htotal - mode->hdisplay < 32)
16531                         return MODE_H_ILLEGAL;
16532
16533                 if (mode->vtotal - mode->vdisplay < 5)
16534                         return MODE_V_ILLEGAL;
16535         } else {
16536                 if (mode->htotal - mode->hdisplay < 32)
16537                         return MODE_H_ILLEGAL;
16538
16539                 if (mode->vtotal - mode->vdisplay < 3)
16540                         return MODE_V_ILLEGAL;
16541         }
16542
16543         return MODE_OK;
16544 }
16545
16546 enum drm_mode_status
16547 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16548                                 const struct drm_display_mode *mode)
16549 {
16550         int plane_width_max, plane_height_max;
16551
16552         /*
16553          * intel_mode_valid() should be
16554          * sufficient on older platforms.
16555          */
16556         if (INTEL_GEN(dev_priv) < 9)
16557                 return MODE_OK;
16558
16559         /*
16560          * Most people will probably want a fullscreen
16561          * plane so let's not advertize modes that are
16562          * too big for that.
16563          */
16564         if (INTEL_GEN(dev_priv) >= 11) {
16565                 plane_width_max = 5120;
16566                 plane_height_max = 4320;
16567         } else {
16568                 plane_width_max = 5120;
16569                 plane_height_max = 4096;
16570         }
16571
16572         if (mode->hdisplay > plane_width_max)
16573                 return MODE_H_ILLEGAL;
16574
16575         if (mode->vdisplay > plane_height_max)
16576                 return MODE_V_ILLEGAL;
16577
16578         return MODE_OK;
16579 }
16580
16581 static const struct drm_mode_config_funcs intel_mode_funcs = {
16582         .fb_create = intel_user_framebuffer_create,
16583         .get_format_info = intel_get_format_info,
16584         .output_poll_changed = intel_fbdev_output_poll_changed,
16585         .mode_valid = intel_mode_valid,
16586         .atomic_check = intel_atomic_check,
16587         .atomic_commit = intel_atomic_commit,
16588         .atomic_state_alloc = intel_atomic_state_alloc,
16589         .atomic_state_clear = intel_atomic_state_clear,
16590         .atomic_state_free = intel_atomic_state_free,
16591 };
16592
16593 /**
16594  * intel_init_display_hooks - initialize the display modesetting hooks
16595  * @dev_priv: device private
16596  */
16597 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16598 {
16599         intel_init_cdclk_hooks(dev_priv);
16600
16601         if (INTEL_GEN(dev_priv) >= 9) {
16602                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16603                 dev_priv->display.get_initial_plane_config =
16604                         skylake_get_initial_plane_config;
16605                 dev_priv->display.crtc_compute_clock =
16606                         haswell_crtc_compute_clock;
16607                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16608                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16609         } else if (HAS_DDI(dev_priv)) {
16610                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16611                 dev_priv->display.get_initial_plane_config =
16612                         i9xx_get_initial_plane_config;
16613                 dev_priv->display.crtc_compute_clock =
16614                         haswell_crtc_compute_clock;
16615                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16616                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16617         } else if (HAS_PCH_SPLIT(dev_priv)) {
16618                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16619                 dev_priv->display.get_initial_plane_config =
16620                         i9xx_get_initial_plane_config;
16621                 dev_priv->display.crtc_compute_clock =
16622                         ironlake_crtc_compute_clock;
16623                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16624                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16625         } else if (IS_CHERRYVIEW(dev_priv)) {
16626                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16627                 dev_priv->display.get_initial_plane_config =
16628                         i9xx_get_initial_plane_config;
16629                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16630                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16631                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16632         } else if (IS_VALLEYVIEW(dev_priv)) {
16633                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16634                 dev_priv->display.get_initial_plane_config =
16635                         i9xx_get_initial_plane_config;
16636                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16637                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16638                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16639         } else if (IS_G4X(dev_priv)) {
16640                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16641                 dev_priv->display.get_initial_plane_config =
16642                         i9xx_get_initial_plane_config;
16643                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16644                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16645                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16646         } else if (IS_PINEVIEW(dev_priv)) {
16647                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16648                 dev_priv->display.get_initial_plane_config =
16649                         i9xx_get_initial_plane_config;
16650                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16651                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16652                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16653         } else if (!IS_GEN(dev_priv, 2)) {
16654                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16655                 dev_priv->display.get_initial_plane_config =
16656                         i9xx_get_initial_plane_config;
16657                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16658                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16659                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16660         } else {
16661                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16662                 dev_priv->display.get_initial_plane_config =
16663                         i9xx_get_initial_plane_config;
16664                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16665                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16666                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16667         }
16668
16669         if (IS_GEN(dev_priv, 5)) {
16670                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16671         } else if (IS_GEN(dev_priv, 6)) {
16672                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16673         } else if (IS_IVYBRIDGE(dev_priv)) {
16674                 /* FIXME: detect B0+ stepping and use auto training */
16675                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16676         }
16677
16678         if (INTEL_GEN(dev_priv) >= 9)
16679                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16680         else
16681                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16682
16683 }
16684
16685 void intel_modeset_init_hw(struct drm_i915_private *i915)
16686 {
16687         intel_update_cdclk(i915);
16688         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16689         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16690 }
16691
16692 /*
16693  * Calculate what we think the watermarks should be for the state we've read
16694  * out of the hardware and then immediately program those watermarks so that
16695  * we ensure the hardware settings match our internal state.
16696  *
16697  * We can calculate what we think WM's should be by creating a duplicate of the
16698  * current state (which was constructed during hardware readout) and running it
16699  * through the atomic check code to calculate new watermark values in the
16700  * state object.
16701  */
16702 static void sanitize_watermarks(struct drm_device *dev)
16703 {
16704         struct drm_i915_private *dev_priv = to_i915(dev);
16705         struct drm_atomic_state *state;
16706         struct intel_atomic_state *intel_state;
16707         struct intel_crtc *crtc;
16708         struct intel_crtc_state *crtc_state;
16709         struct drm_modeset_acquire_ctx ctx;
16710         int ret;
16711         int i;
16712
16713         /* Only supported on platforms that use atomic watermark design */
16714         if (!dev_priv->display.optimize_watermarks)
16715                 return;
16716
16717         /*
16718          * We need to hold connection_mutex before calling duplicate_state so
16719          * that the connector loop is protected.
16720          */
16721         drm_modeset_acquire_init(&ctx, 0);
16722 retry:
16723         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16724         if (ret == -EDEADLK) {
16725                 drm_modeset_backoff(&ctx);
16726                 goto retry;
16727         } else if (WARN_ON(ret)) {
16728                 goto fail;
16729         }
16730
16731         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16732         if (WARN_ON(IS_ERR(state)))
16733                 goto fail;
16734
16735         intel_state = to_intel_atomic_state(state);
16736
16737         /*
16738          * Hardware readout is the only time we don't want to calculate
16739          * intermediate watermarks (since we don't trust the current
16740          * watermarks).
16741          */
16742         if (!HAS_GMCH(dev_priv))
16743                 intel_state->skip_intermediate_wm = true;
16744
16745         ret = intel_atomic_check(dev, state);
16746         if (ret) {
16747                 /*
16748                  * If we fail here, it means that the hardware appears to be
16749                  * programmed in a way that shouldn't be possible, given our
16750                  * understanding of watermark requirements.  This might mean a
16751                  * mistake in the hardware readout code or a mistake in the
16752                  * watermark calculations for a given platform.  Raise a WARN
16753                  * so that this is noticeable.
16754                  *
16755                  * If this actually happens, we'll have to just leave the
16756                  * BIOS-programmed watermarks untouched and hope for the best.
16757                  */
16758                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16759                 goto put_state;
16760         }
16761
16762         /* Write calculated watermark values back */
16763         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16764                 crtc_state->wm.need_postvbl_update = true;
16765                 dev_priv->display.optimize_watermarks(intel_state, crtc);
16766
16767                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16768         }
16769
16770 put_state:
16771         drm_atomic_state_put(state);
16772 fail:
16773         drm_modeset_drop_locks(&ctx);
16774         drm_modeset_acquire_fini(&ctx);
16775 }
16776
16777 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16778 {
16779         if (IS_GEN(dev_priv, 5)) {
16780                 u32 fdi_pll_clk =
16781                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16782
16783                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16784         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16785                 dev_priv->fdi_pll_freq = 270000;
16786         } else {
16787                 return;
16788         }
16789
16790         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16791 }
16792
16793 static int intel_initial_commit(struct drm_device *dev)
16794 {
16795         struct drm_atomic_state *state = NULL;
16796         struct drm_modeset_acquire_ctx ctx;
16797         struct intel_crtc *crtc;
16798         int ret = 0;
16799
16800         state = drm_atomic_state_alloc(dev);
16801         if (!state)
16802                 return -ENOMEM;
16803
16804         drm_modeset_acquire_init(&ctx, 0);
16805
16806 retry:
16807         state->acquire_ctx = &ctx;
16808
16809         for_each_intel_crtc(dev, crtc) {
16810                 struct intel_crtc_state *crtc_state =
16811                         intel_atomic_get_crtc_state(state, crtc);
16812
16813                 if (IS_ERR(crtc_state)) {
16814                         ret = PTR_ERR(crtc_state);
16815                         goto out;
16816                 }
16817
16818                 if (crtc_state->hw.active) {
16819                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
16820                         if (ret)
16821                                 goto out;
16822
16823                         /*
16824                          * FIXME hack to force a LUT update to avoid the
16825                          * plane update forcing the pipe gamma on without
16826                          * having a proper LUT loaded. Remove once we
16827                          * have readout for pipe gamma enable.
16828                          */
16829                         crtc_state->uapi.color_mgmt_changed = true;
16830                 }
16831         }
16832
16833         ret = drm_atomic_commit(state);
16834
16835 out:
16836         if (ret == -EDEADLK) {
16837                 drm_atomic_state_clear(state);
16838                 drm_modeset_backoff(&ctx);
16839                 goto retry;
16840         }
16841
16842         drm_atomic_state_put(state);
16843
16844         drm_modeset_drop_locks(&ctx);
16845         drm_modeset_acquire_fini(&ctx);
16846
16847         return ret;
16848 }
16849
16850 static void intel_mode_config_init(struct drm_i915_private *i915)
16851 {
16852         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16853
16854         drm_mode_config_init(&i915->drm);
16855
16856         mode_config->min_width = 0;
16857         mode_config->min_height = 0;
16858
16859         mode_config->preferred_depth = 24;
16860         mode_config->prefer_shadow = 1;
16861
16862         mode_config->allow_fb_modifiers = true;
16863
16864         mode_config->funcs = &intel_mode_funcs;
16865
16866         /*
16867          * Maximum framebuffer dimensions, chosen to match
16868          * the maximum render engine surface size on gen4+.
16869          */
16870         if (INTEL_GEN(i915) >= 7) {
16871                 mode_config->max_width = 16384;
16872                 mode_config->max_height = 16384;
16873         } else if (INTEL_GEN(i915) >= 4) {
16874                 mode_config->max_width = 8192;
16875                 mode_config->max_height = 8192;
16876         } else if (IS_GEN(i915, 3)) {
16877                 mode_config->max_width = 4096;
16878                 mode_config->max_height = 4096;
16879         } else {
16880                 mode_config->max_width = 2048;
16881                 mode_config->max_height = 2048;
16882         }
16883
16884         if (IS_I845G(i915) || IS_I865G(i915)) {
16885                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16886                 mode_config->cursor_height = 1023;
16887         } else if (IS_GEN(i915, 2)) {
16888                 mode_config->cursor_width = 64;
16889                 mode_config->cursor_height = 64;
16890         } else {
16891                 mode_config->cursor_width = 256;
16892                 mode_config->cursor_height = 256;
16893         }
16894 }
16895
16896 int intel_modeset_init(struct drm_i915_private *i915)
16897 {
16898         struct drm_device *dev = &i915->drm;
16899         enum pipe pipe;
16900         struct intel_crtc *crtc;
16901         int ret;
16902
16903         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16904         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16905                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16906
16907         intel_mode_config_init(i915);
16908
16909         ret = intel_bw_init(i915);
16910         if (ret)
16911                 return ret;
16912
16913         init_llist_head(&i915->atomic_helper.free_list);
16914         INIT_WORK(&i915->atomic_helper.free_work,
16915                   intel_atomic_helper_free_state_worker);
16916
16917         intel_init_quirks(i915);
16918
16919         intel_fbc_init(i915);
16920
16921         intel_init_pm(i915);
16922
16923         intel_panel_sanitize_ssc(i915);
16924
16925         intel_gmbus_setup(i915);
16926
16927         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16928                       INTEL_NUM_PIPES(i915),
16929                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
16930
16931         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
16932                 for_each_pipe(i915, pipe) {
16933                         ret = intel_crtc_init(i915, pipe);
16934                         if (ret) {
16935                                 drm_mode_config_cleanup(dev);
16936                                 return ret;
16937                         }
16938                 }
16939         }
16940
16941         intel_shared_dpll_init(dev);
16942         intel_update_fdi_pll_freq(i915);
16943
16944         intel_update_czclk(i915);
16945         intel_modeset_init_hw(i915);
16946
16947         intel_hdcp_component_init(i915);
16948
16949         if (i915->max_cdclk_freq == 0)
16950                 intel_update_max_cdclk(i915);
16951
16952         /* Just disable it once at startup */
16953         intel_vga_disable(i915);
16954         intel_setup_outputs(i915);
16955
16956         drm_modeset_lock_all(dev);
16957         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
16958         drm_modeset_unlock_all(dev);
16959
16960         for_each_intel_crtc(dev, crtc) {
16961                 struct intel_initial_plane_config plane_config = {};
16962
16963                 if (!crtc->active)
16964                         continue;
16965
16966                 /*
16967                  * Note that reserving the BIOS fb up front prevents us
16968                  * from stuffing other stolen allocations like the ring
16969                  * on top.  This prevents some ugliness at boot time, and
16970                  * can even allow for smooth boot transitions if the BIOS
16971                  * fb is large enough for the active pipe configuration.
16972                  */
16973                 i915->display.get_initial_plane_config(crtc, &plane_config);
16974
16975                 /*
16976                  * If the fb is shared between multiple heads, we'll
16977                  * just get the first one.
16978                  */
16979                 intel_find_initial_plane_obj(crtc, &plane_config);
16980         }
16981
16982         /*
16983          * Make sure hardware watermarks really match the state we read out.
16984          * Note that we need to do this after reconstructing the BIOS fb's
16985          * since the watermark calculation done here will use pstate->fb.
16986          */
16987         if (!HAS_GMCH(i915))
16988                 sanitize_watermarks(dev);
16989
16990         /*
16991          * Force all active planes to recompute their states. So that on
16992          * mode_setcrtc after probe, all the intel_plane_state variables
16993          * are already calculated and there is no assert_plane warnings
16994          * during bootup.
16995          */
16996         ret = intel_initial_commit(dev);
16997         if (ret)
16998                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
16999
17000         return 0;
17001 }
17002
17003 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17004 {
17005         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17006         /* 640x480@60Hz, ~25175 kHz */
17007         struct dpll clock = {
17008                 .m1 = 18,
17009                 .m2 = 7,
17010                 .p1 = 13,
17011                 .p2 = 4,
17012                 .n = 2,
17013         };
17014         u32 dpll, fp;
17015         int i;
17016
17017         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
17018
17019         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17020                       pipe_name(pipe), clock.vco, clock.dot);
17021
17022         fp = i9xx_dpll_compute_fp(&clock);
17023         dpll = DPLL_DVO_2X_MODE |
17024                 DPLL_VGA_MODE_DIS |
17025                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17026                 PLL_P2_DIVIDE_BY_4 |
17027                 PLL_REF_INPUT_DREFCLK |
17028                 DPLL_VCO_ENABLE;
17029
17030         I915_WRITE(FP0(pipe), fp);
17031         I915_WRITE(FP1(pipe), fp);
17032
17033         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17034         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17035         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17036         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17037         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17038         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17039         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17040
17041         /*
17042          * Apparently we need to have VGA mode enabled prior to changing
17043          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17044          * dividers, even though the register value does change.
17045          */
17046         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17047         I915_WRITE(DPLL(pipe), dpll);
17048
17049         /* Wait for the clocks to stabilize. */
17050         POSTING_READ(DPLL(pipe));
17051         udelay(150);
17052
17053         /* The pixel multiplier can only be updated once the
17054          * DPLL is enabled and the clocks are stable.
17055          *
17056          * So write it again.
17057          */
17058         I915_WRITE(DPLL(pipe), dpll);
17059
17060         /* We do this three times for luck */
17061         for (i = 0; i < 3 ; i++) {
17062                 I915_WRITE(DPLL(pipe), dpll);
17063                 POSTING_READ(DPLL(pipe));
17064                 udelay(150); /* wait for warmup */
17065         }
17066
17067         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17068         POSTING_READ(PIPECONF(pipe));
17069
17070         intel_wait_for_pipe_scanline_moving(crtc);
17071 }
17072
17073 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17074 {
17075         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17076
17077         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17078                       pipe_name(pipe));
17079
17080         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17081         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17082         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17083         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17084         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17085
17086         I915_WRITE(PIPECONF(pipe), 0);
17087         POSTING_READ(PIPECONF(pipe));
17088
17089         intel_wait_for_pipe_scanline_stopped(crtc);
17090
17091         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17092         POSTING_READ(DPLL(pipe));
17093 }
17094
17095 static void
17096 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17097 {
17098         struct intel_crtc *crtc;
17099
17100         if (INTEL_GEN(dev_priv) >= 4)
17101                 return;
17102
17103         for_each_intel_crtc(&dev_priv->drm, crtc) {
17104                 struct intel_plane *plane =
17105                         to_intel_plane(crtc->base.primary);
17106                 struct intel_crtc *plane_crtc;
17107                 enum pipe pipe;
17108
17109                 if (!plane->get_hw_state(plane, &pipe))
17110                         continue;
17111
17112                 if (pipe == crtc->pipe)
17113                         continue;
17114
17115                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17116                               plane->base.base.id, plane->base.name);
17117
17118                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17119                 intel_plane_disable_noatomic(plane_crtc, plane);
17120         }
17121 }
17122
17123 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17124 {
17125         struct drm_device *dev = crtc->base.dev;
17126         struct intel_encoder *encoder;
17127
17128         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17129                 return true;
17130
17131         return false;
17132 }
17133
17134 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17135 {
17136         struct drm_device *dev = encoder->base.dev;
17137         struct intel_connector *connector;
17138
17139         for_each_connector_on_encoder(dev, &encoder->base, connector)
17140                 return connector;
17141
17142         return NULL;
17143 }
17144
17145 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17146                               enum pipe pch_transcoder)
17147 {
17148         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17149                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17150 }
17151
17152 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17153 {
17154         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17155         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17156         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17157
17158         if (INTEL_GEN(dev_priv) >= 9 ||
17159             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17160                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17161                 u32 val;
17162
17163                 if (transcoder_is_dsi(cpu_transcoder))
17164                         return;
17165
17166                 val = I915_READ(reg);
17167                 val &= ~HSW_FRAME_START_DELAY_MASK;
17168                 val |= HSW_FRAME_START_DELAY(0);
17169                 I915_WRITE(reg, val);
17170         } else {
17171                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17172                 u32 val;
17173
17174                 val = I915_READ(reg);
17175                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17176                 val |= PIPECONF_FRAME_START_DELAY(0);
17177                 I915_WRITE(reg, val);
17178         }
17179
17180         if (!crtc_state->has_pch_encoder)
17181                 return;
17182
17183         if (HAS_PCH_IBX(dev_priv)) {
17184                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17185                 u32 val;
17186
17187                 val = I915_READ(reg);
17188                 val &= ~TRANS_FRAME_START_DELAY_MASK;
17189                 val |= TRANS_FRAME_START_DELAY(0);
17190                 I915_WRITE(reg, val);
17191         } else {
17192                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
17193                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
17194                 u32 val;
17195
17196                 val = I915_READ(reg);
17197                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17198                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17199                 I915_WRITE(reg, val);
17200         }
17201 }
17202
17203 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17204                                 struct drm_modeset_acquire_ctx *ctx)
17205 {
17206         struct drm_device *dev = crtc->base.dev;
17207         struct drm_i915_private *dev_priv = to_i915(dev);
17208         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17209
17210         if (crtc_state->hw.active) {
17211                 struct intel_plane *plane;
17212
17213                 /* Clear any frame start delays used for debugging left by the BIOS */
17214                 intel_sanitize_frame_start_delay(crtc_state);
17215
17216                 /* Disable everything but the primary plane */
17217                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17218                         const struct intel_plane_state *plane_state =
17219                                 to_intel_plane_state(plane->base.state);
17220
17221                         if (plane_state->uapi.visible &&
17222                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17223                                 intel_plane_disable_noatomic(crtc, plane);
17224                 }
17225
17226                 /*
17227                  * Disable any background color set by the BIOS, but enable the
17228                  * gamma and CSC to match how we program our planes.
17229                  */
17230                 if (INTEL_GEN(dev_priv) >= 9)
17231                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17232                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17233                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17234         }
17235
17236         /* Adjust the state of the output pipe according to whether we
17237          * have active connectors/encoders. */
17238         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17239                 intel_crtc_disable_noatomic(crtc, ctx);
17240
17241         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17242                 /*
17243                  * We start out with underrun reporting disabled to avoid races.
17244                  * For correct bookkeeping mark this on active crtcs.
17245                  *
17246                  * Also on gmch platforms we dont have any hardware bits to
17247                  * disable the underrun reporting. Which means we need to start
17248                  * out with underrun reporting disabled also on inactive pipes,
17249                  * since otherwise we'll complain about the garbage we read when
17250                  * e.g. coming up after runtime pm.
17251                  *
17252                  * No protection against concurrent access is required - at
17253                  * worst a fifo underrun happens which also sets this to false.
17254                  */
17255                 crtc->cpu_fifo_underrun_disabled = true;
17256                 /*
17257                  * We track the PCH trancoder underrun reporting state
17258                  * within the crtc. With crtc for pipe A housing the underrun
17259                  * reporting state for PCH transcoder A, crtc for pipe B housing
17260                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17261                  * and marking underrun reporting as disabled for the non-existing
17262                  * PCH transcoders B and C would prevent enabling the south
17263                  * error interrupt (see cpt_can_enable_serr_int()).
17264                  */
17265                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17266                         crtc->pch_fifo_underrun_disabled = true;
17267         }
17268 }
17269
17270 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17271 {
17272         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17273
17274         /*
17275          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17276          * the hardware when a high res displays plugged in. DPLL P
17277          * divider is zero, and the pipe timings are bonkers. We'll
17278          * try to disable everything in that case.
17279          *
17280          * FIXME would be nice to be able to sanitize this state
17281          * without several WARNs, but for now let's take the easy
17282          * road.
17283          */
17284         return IS_GEN(dev_priv, 6) &&
17285                 crtc_state->hw.active &&
17286                 crtc_state->shared_dpll &&
17287                 crtc_state->port_clock == 0;
17288 }
17289
17290 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17291 {
17292         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17293         struct intel_connector *connector;
17294         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17295         struct intel_crtc_state *crtc_state = crtc ?
17296                 to_intel_crtc_state(crtc->base.state) : NULL;
17297
17298         /* We need to check both for a crtc link (meaning that the
17299          * encoder is active and trying to read from a pipe) and the
17300          * pipe itself being active. */
17301         bool has_active_crtc = crtc_state &&
17302                 crtc_state->hw.active;
17303
17304         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17305                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17306                               pipe_name(crtc->pipe));
17307                 has_active_crtc = false;
17308         }
17309
17310         connector = intel_encoder_find_connector(encoder);
17311         if (connector && !has_active_crtc) {
17312                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17313                               encoder->base.base.id,
17314                               encoder->base.name);
17315
17316                 /* Connector is active, but has no active pipe. This is
17317                  * fallout from our resume register restoring. Disable
17318                  * the encoder manually again. */
17319                 if (crtc_state) {
17320                         struct drm_encoder *best_encoder;
17321
17322                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17323                                       encoder->base.base.id,
17324                                       encoder->base.name);
17325
17326                         /* avoid oopsing in case the hooks consult best_encoder */
17327                         best_encoder = connector->base.state->best_encoder;
17328                         connector->base.state->best_encoder = &encoder->base;
17329
17330                         if (encoder->disable)
17331                                 encoder->disable(encoder, crtc_state,
17332                                                  connector->base.state);
17333                         if (encoder->post_disable)
17334                                 encoder->post_disable(encoder, crtc_state,
17335                                                       connector->base.state);
17336
17337                         connector->base.state->best_encoder = best_encoder;
17338                 }
17339                 encoder->base.crtc = NULL;
17340
17341                 /* Inconsistent output/port/pipe state happens presumably due to
17342                  * a bug in one of the get_hw_state functions. Or someplace else
17343                  * in our code, like the register restore mess on resume. Clamp
17344                  * things to off as a safer default. */
17345
17346                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17347                 connector->base.encoder = NULL;
17348         }
17349
17350         /* notify opregion of the sanitized encoder state */
17351         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17352
17353         if (INTEL_GEN(dev_priv) >= 11)
17354                 icl_sanitize_encoder_pll_mapping(encoder);
17355 }
17356
17357 /* FIXME read out full plane state for all planes */
17358 static void readout_plane_state(struct drm_i915_private *dev_priv)
17359 {
17360         struct intel_plane *plane;
17361         struct intel_crtc *crtc;
17362
17363         for_each_intel_plane(&dev_priv->drm, plane) {
17364                 struct intel_plane_state *plane_state =
17365                         to_intel_plane_state(plane->base.state);
17366                 struct intel_crtc_state *crtc_state;
17367                 enum pipe pipe = PIPE_A;
17368                 bool visible;
17369
17370                 visible = plane->get_hw_state(plane, &pipe);
17371
17372                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17373                 crtc_state = to_intel_crtc_state(crtc->base.state);
17374
17375                 intel_set_plane_visible(crtc_state, plane_state, visible);
17376
17377                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17378                               plane->base.base.id, plane->base.name,
17379                               enableddisabled(visible), pipe_name(pipe));
17380         }
17381
17382         for_each_intel_crtc(&dev_priv->drm, crtc) {
17383                 struct intel_crtc_state *crtc_state =
17384                         to_intel_crtc_state(crtc->base.state);
17385
17386                 fixup_active_planes(crtc_state);
17387         }
17388 }
17389
17390 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17391 {
17392         struct drm_i915_private *dev_priv = to_i915(dev);
17393         enum pipe pipe;
17394         struct intel_crtc *crtc;
17395         struct intel_encoder *encoder;
17396         struct intel_connector *connector;
17397         struct drm_connector_list_iter conn_iter;
17398         int i;
17399
17400         dev_priv->active_pipes = 0;
17401
17402         for_each_intel_crtc(dev, crtc) {
17403                 struct intel_crtc_state *crtc_state =
17404                         to_intel_crtc_state(crtc->base.state);
17405
17406                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17407                 intel_crtc_free_hw_state(crtc_state);
17408                 intel_crtc_state_reset(crtc_state, crtc);
17409
17410                 crtc_state->hw.active = crtc_state->hw.enable =
17411                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17412
17413                 crtc->base.enabled = crtc_state->hw.enable;
17414                 crtc->active = crtc_state->hw.active;
17415
17416                 if (crtc_state->hw.active)
17417                         dev_priv->active_pipes |= BIT(crtc->pipe);
17418
17419                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17420                               crtc->base.base.id, crtc->base.name,
17421                               enableddisabled(crtc_state->hw.active));
17422         }
17423
17424         readout_plane_state(dev_priv);
17425
17426         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17427                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17428
17429                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17430                                                         &pll->state.hw_state);
17431
17432                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17433                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17434                         pll->wakeref = intel_display_power_get(dev_priv,
17435                                                                POWER_DOMAIN_DPLL_DC_OFF);
17436                 }
17437
17438                 pll->state.crtc_mask = 0;
17439                 for_each_intel_crtc(dev, crtc) {
17440                         struct intel_crtc_state *crtc_state =
17441                                 to_intel_crtc_state(crtc->base.state);
17442
17443                         if (crtc_state->hw.active &&
17444                             crtc_state->shared_dpll == pll)
17445                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17446                 }
17447                 pll->active_mask = pll->state.crtc_mask;
17448
17449                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17450                               pll->info->name, pll->state.crtc_mask, pll->on);
17451         }
17452
17453         for_each_intel_encoder(dev, encoder) {
17454                 pipe = 0;
17455
17456                 if (encoder->get_hw_state(encoder, &pipe)) {
17457                         struct intel_crtc_state *crtc_state;
17458
17459                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17460                         crtc_state = to_intel_crtc_state(crtc->base.state);
17461
17462                         encoder->base.crtc = &crtc->base;
17463                         encoder->get_config(encoder, crtc_state);
17464                 } else {
17465                         encoder->base.crtc = NULL;
17466                 }
17467
17468                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17469                               encoder->base.base.id, encoder->base.name,
17470                               enableddisabled(encoder->base.crtc),
17471                               pipe_name(pipe));
17472         }
17473
17474         drm_connector_list_iter_begin(dev, &conn_iter);
17475         for_each_intel_connector_iter(connector, &conn_iter) {
17476                 if (connector->get_hw_state(connector)) {
17477                         struct intel_crtc_state *crtc_state;
17478                         struct intel_crtc *crtc;
17479
17480                         connector->base.dpms = DRM_MODE_DPMS_ON;
17481
17482                         encoder = connector->encoder;
17483                         connector->base.encoder = &encoder->base;
17484
17485                         crtc = to_intel_crtc(encoder->base.crtc);
17486                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17487
17488                         if (crtc_state && crtc_state->hw.active) {
17489                                 /*
17490                                  * This has to be done during hardware readout
17491                                  * because anything calling .crtc_disable may
17492                                  * rely on the connector_mask being accurate.
17493                                  */
17494                                 crtc_state->uapi.connector_mask |=
17495                                         drm_connector_mask(&connector->base);
17496                                 crtc_state->uapi.encoder_mask |=
17497                                         drm_encoder_mask(&encoder->base);
17498                         }
17499                 } else {
17500                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17501                         connector->base.encoder = NULL;
17502                 }
17503                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17504                               connector->base.base.id, connector->base.name,
17505                               enableddisabled(connector->base.encoder));
17506         }
17507         drm_connector_list_iter_end(&conn_iter);
17508
17509         for_each_intel_crtc(dev, crtc) {
17510                 struct intel_bw_state *bw_state =
17511                         to_intel_bw_state(dev_priv->bw_obj.state);
17512                 struct intel_crtc_state *crtc_state =
17513                         to_intel_crtc_state(crtc->base.state);
17514                 struct intel_plane *plane;
17515                 int min_cdclk = 0;
17516
17517                 if (crtc_state->hw.active) {
17518                         struct drm_display_mode *mode = &crtc_state->hw.mode;
17519
17520                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17521                                                     crtc_state);
17522
17523                         *mode = crtc_state->hw.adjusted_mode;
17524                         mode->hdisplay = crtc_state->pipe_src_w;
17525                         mode->vdisplay = crtc_state->pipe_src_h;
17526
17527                         /*
17528                          * The initial mode needs to be set in order to keep
17529                          * the atomic core happy. It wants a valid mode if the
17530                          * crtc's enabled, so we do the above call.
17531                          *
17532                          * But we don't set all the derived state fully, hence
17533                          * set a flag to indicate that a full recalculation is
17534                          * needed on the next commit.
17535                          */
17536                         mode->private_flags = I915_MODE_FLAG_INHERITED;
17537
17538                         intel_crtc_compute_pixel_rate(crtc_state);
17539
17540                         intel_crtc_update_active_timings(crtc_state);
17541
17542                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
17543                 }
17544
17545                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17546                         const struct intel_plane_state *plane_state =
17547                                 to_intel_plane_state(plane->base.state);
17548
17549                         /*
17550                          * FIXME don't have the fb yet, so can't
17551                          * use intel_plane_data_rate() :(
17552                          */
17553                         if (plane_state->uapi.visible)
17554                                 crtc_state->data_rate[plane->id] =
17555                                         4 * crtc_state->pixel_rate;
17556                         /*
17557                          * FIXME don't have the fb yet, so can't
17558                          * use plane->min_cdclk() :(
17559                          */
17560                         if (plane_state->uapi.visible && plane->min_cdclk) {
17561                                 if (crtc_state->double_wide ||
17562                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17563                                         crtc_state->min_cdclk[plane->id] =
17564                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17565                                 else
17566                                         crtc_state->min_cdclk[plane->id] =
17567                                                 crtc_state->pixel_rate;
17568                         }
17569                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17570                                       plane->base.base.id, plane->base.name,
17571                                       crtc_state->min_cdclk[plane->id]);
17572                 }
17573
17574                 if (crtc_state->hw.active) {
17575                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17576                         if (WARN_ON(min_cdclk < 0))
17577                                 min_cdclk = 0;
17578                 }
17579
17580                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17581                 dev_priv->min_voltage_level[crtc->pipe] =
17582                         crtc_state->min_voltage_level;
17583
17584                 intel_bw_crtc_update(bw_state, crtc_state);
17585
17586                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17587         }
17588 }
17589
17590 static void
17591 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17592 {
17593         struct intel_encoder *encoder;
17594
17595         for_each_intel_encoder(&dev_priv->drm, encoder) {
17596                 struct intel_crtc_state *crtc_state;
17597
17598                 if (!encoder->get_power_domains)
17599                         continue;
17600
17601                 /*
17602                  * MST-primary and inactive encoders don't have a crtc state
17603                  * and neither of these require any power domain references.
17604                  */
17605                 if (!encoder->base.crtc)
17606                         continue;
17607
17608                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17609                 encoder->get_power_domains(encoder, crtc_state);
17610         }
17611 }
17612
17613 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17614 {
17615         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17616         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17617                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17618                            DARBF_GATING_DIS);
17619
17620         if (IS_HASWELL(dev_priv)) {
17621                 /*
17622                  * WaRsPkgCStateDisplayPMReq:hsw
17623                  * System hang if this isn't done before disabling all planes!
17624                  */
17625                 I915_WRITE(CHICKEN_PAR1_1,
17626                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17627         }
17628 }
17629
17630 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17631                                        enum port port, i915_reg_t hdmi_reg)
17632 {
17633         u32 val = I915_READ(hdmi_reg);
17634
17635         if (val & SDVO_ENABLE ||
17636             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17637                 return;
17638
17639         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17640                       port_name(port));
17641
17642         val &= ~SDVO_PIPE_SEL_MASK;
17643         val |= SDVO_PIPE_SEL(PIPE_A);
17644
17645         I915_WRITE(hdmi_reg, val);
17646 }
17647
17648 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17649                                      enum port port, i915_reg_t dp_reg)
17650 {
17651         u32 val = I915_READ(dp_reg);
17652
17653         if (val & DP_PORT_EN ||
17654             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17655                 return;
17656
17657         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17658                       port_name(port));
17659
17660         val &= ~DP_PIPE_SEL_MASK;
17661         val |= DP_PIPE_SEL(PIPE_A);
17662
17663         I915_WRITE(dp_reg, val);
17664 }
17665
17666 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17667 {
17668         /*
17669          * The BIOS may select transcoder B on some of the PCH
17670          * ports even it doesn't enable the port. This would trip
17671          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17672          * Sanitize the transcoder select bits to prevent that. We
17673          * assume that the BIOS never actually enabled the port,
17674          * because if it did we'd actually have to toggle the port
17675          * on and back off to make the transcoder A select stick
17676          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17677          * intel_disable_sdvo()).
17678          */
17679         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17680         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17681         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17682
17683         /* PCH SDVOB multiplex with HDMIB */
17684         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17685         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17686         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17687 }
17688
17689 /* Scan out the current hw modeset state,
17690  * and sanitizes it to the current state
17691  */
17692 static void
17693 intel_modeset_setup_hw_state(struct drm_device *dev,
17694                              struct drm_modeset_acquire_ctx *ctx)
17695 {
17696         struct drm_i915_private *dev_priv = to_i915(dev);
17697         struct intel_encoder *encoder;
17698         struct intel_crtc *crtc;
17699         intel_wakeref_t wakeref;
17700         int i;
17701
17702         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17703
17704         intel_early_display_was(dev_priv);
17705         intel_modeset_readout_hw_state(dev);
17706
17707         /* HW state is read out, now we need to sanitize this mess. */
17708
17709         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17710         for_each_intel_encoder(dev, encoder) {
17711                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17712
17713                 /* We need to sanitize only the MST primary port. */
17714                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17715                     intel_phy_is_tc(dev_priv, phy))
17716                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17717         }
17718
17719         get_encoder_power_domains(dev_priv);
17720
17721         if (HAS_PCH_IBX(dev_priv))
17722                 ibx_sanitize_pch_ports(dev_priv);
17723
17724         /*
17725          * intel_sanitize_plane_mapping() may need to do vblank
17726          * waits, so we need vblank interrupts restored beforehand.
17727          */
17728         for_each_intel_crtc(&dev_priv->drm, crtc) {
17729                 struct intel_crtc_state *crtc_state =
17730                         to_intel_crtc_state(crtc->base.state);
17731
17732                 drm_crtc_vblank_reset(&crtc->base);
17733
17734                 if (crtc_state->hw.active)
17735                         intel_crtc_vblank_on(crtc_state);
17736         }
17737
17738         intel_sanitize_plane_mapping(dev_priv);
17739
17740         for_each_intel_encoder(dev, encoder)
17741                 intel_sanitize_encoder(encoder);
17742
17743         for_each_intel_crtc(&dev_priv->drm, crtc) {
17744                 struct intel_crtc_state *crtc_state =
17745                         to_intel_crtc_state(crtc->base.state);
17746
17747                 intel_sanitize_crtc(crtc, ctx);
17748                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17749         }
17750
17751         intel_modeset_update_connector_atomic_state(dev);
17752
17753         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17754                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17755
17756                 if (!pll->on || pll->active_mask)
17757                         continue;
17758
17759                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17760                               pll->info->name);
17761
17762                 pll->info->funcs->disable(dev_priv, pll);
17763                 pll->on = false;
17764         }
17765
17766         if (IS_G4X(dev_priv)) {
17767                 g4x_wm_get_hw_state(dev_priv);
17768                 g4x_wm_sanitize(dev_priv);
17769         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17770                 vlv_wm_get_hw_state(dev_priv);
17771                 vlv_wm_sanitize(dev_priv);
17772         } else if (INTEL_GEN(dev_priv) >= 9) {
17773                 skl_wm_get_hw_state(dev_priv);
17774         } else if (HAS_PCH_SPLIT(dev_priv)) {
17775                 ilk_wm_get_hw_state(dev_priv);
17776         }
17777
17778         for_each_intel_crtc(dev, crtc) {
17779                 struct intel_crtc_state *crtc_state =
17780                         to_intel_crtc_state(crtc->base.state);
17781                 u64 put_domains;
17782
17783                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17784                 if (WARN_ON(put_domains))
17785                         modeset_put_power_domains(dev_priv, put_domains);
17786         }
17787
17788         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17789 }
17790
17791 void intel_display_resume(struct drm_device *dev)
17792 {
17793         struct drm_i915_private *dev_priv = to_i915(dev);
17794         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17795         struct drm_modeset_acquire_ctx ctx;
17796         int ret;
17797
17798         dev_priv->modeset_restore_state = NULL;
17799         if (state)
17800                 state->acquire_ctx = &ctx;
17801
17802         drm_modeset_acquire_init(&ctx, 0);
17803
17804         while (1) {
17805                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17806                 if (ret != -EDEADLK)
17807                         break;
17808
17809                 drm_modeset_backoff(&ctx);
17810         }
17811
17812         if (!ret)
17813                 ret = __intel_display_resume(dev, state, &ctx);
17814
17815         intel_enable_ipc(dev_priv);
17816         drm_modeset_drop_locks(&ctx);
17817         drm_modeset_acquire_fini(&ctx);
17818
17819         if (ret)
17820                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17821         if (state)
17822                 drm_atomic_state_put(state);
17823 }
17824
17825 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17826 {
17827         struct intel_connector *connector;
17828         struct drm_connector_list_iter conn_iter;
17829
17830         /* Kill all the work that may have been queued by hpd. */
17831         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17832         for_each_intel_connector_iter(connector, &conn_iter) {
17833                 if (connector->modeset_retry_work.func)
17834                         cancel_work_sync(&connector->modeset_retry_work);
17835                 if (connector->hdcp.shim) {
17836                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17837                         cancel_work_sync(&connector->hdcp.prop_work);
17838                 }
17839         }
17840         drm_connector_list_iter_end(&conn_iter);
17841 }
17842
17843 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17844 {
17845         flush_workqueue(i915->flip_wq);
17846         flush_workqueue(i915->modeset_wq);
17847
17848         flush_work(&i915->atomic_helper.free_work);
17849         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17850
17851         /*
17852          * Interrupts and polling as the first thing to avoid creating havoc.
17853          * Too much stuff here (turning of connectors, ...) would
17854          * experience fancy races otherwise.
17855          */
17856         intel_irq_uninstall(i915);
17857
17858         /*
17859          * Due to the hpd irq storm handling the hotplug work can re-arm the
17860          * poll handlers. Hence disable polling after hpd handling is shut down.
17861          */
17862         intel_hpd_poll_fini(i915);
17863
17864         /*
17865          * MST topology needs to be suspended so we don't have any calls to
17866          * fbdev after it's finalized. MST will be destroyed later as part of
17867          * drm_mode_config_cleanup()
17868          */
17869         intel_dp_mst_suspend(i915);
17870
17871         /* poll work can call into fbdev, hence clean that up afterwards */
17872         intel_fbdev_fini(i915);
17873
17874         intel_unregister_dsm_handler();
17875
17876         intel_fbc_global_disable(i915);
17877
17878         /* flush any delayed tasks or pending work */
17879         flush_scheduled_work();
17880
17881         intel_hdcp_component_fini(i915);
17882
17883         drm_mode_config_cleanup(&i915->drm);
17884
17885         intel_overlay_cleanup(i915);
17886
17887         intel_gmbus_teardown(i915);
17888
17889         destroy_workqueue(i915->flip_wq);
17890         destroy_workqueue(i915->modeset_wq);
17891
17892         intel_fbc_cleanup_cfb(i915);
17893 }
17894
17895 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17896
17897 struct intel_display_error_state {
17898
17899         u32 power_well_driver;
17900
17901         struct intel_cursor_error_state {
17902                 u32 control;
17903                 u32 position;
17904                 u32 base;
17905                 u32 size;
17906         } cursor[I915_MAX_PIPES];
17907
17908         struct intel_pipe_error_state {
17909                 bool power_domain_on;
17910                 u32 source;
17911                 u32 stat;
17912         } pipe[I915_MAX_PIPES];
17913
17914         struct intel_plane_error_state {
17915                 u32 control;
17916                 u32 stride;
17917                 u32 size;
17918                 u32 pos;
17919                 u32 addr;
17920                 u32 surface;
17921                 u32 tile_offset;
17922         } plane[I915_MAX_PIPES];
17923
17924         struct intel_transcoder_error_state {
17925                 bool available;
17926                 bool power_domain_on;
17927                 enum transcoder cpu_transcoder;
17928
17929                 u32 conf;
17930
17931                 u32 htotal;
17932                 u32 hblank;
17933                 u32 hsync;
17934                 u32 vtotal;
17935                 u32 vblank;
17936                 u32 vsync;
17937         } transcoder[5];
17938 };
17939
17940 struct intel_display_error_state *
17941 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17942 {
17943         struct intel_display_error_state *error;
17944         int transcoders[] = {
17945                 TRANSCODER_A,
17946                 TRANSCODER_B,
17947                 TRANSCODER_C,
17948                 TRANSCODER_D,
17949                 TRANSCODER_EDP,
17950         };
17951         int i;
17952
17953         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
17954
17955         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
17956                 return NULL;
17957
17958         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17959         if (error == NULL)
17960                 return NULL;
17961
17962         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17963                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
17964
17965         for_each_pipe(dev_priv, i) {
17966                 error->pipe[i].power_domain_on =
17967                         __intel_display_power_is_enabled(dev_priv,
17968                                                          POWER_DOMAIN_PIPE(i));
17969                 if (!error->pipe[i].power_domain_on)
17970                         continue;
17971
17972                 error->cursor[i].control = I915_READ(CURCNTR(i));
17973                 error->cursor[i].position = I915_READ(CURPOS(i));
17974                 error->cursor[i].base = I915_READ(CURBASE(i));
17975
17976                 error->plane[i].control = I915_READ(DSPCNTR(i));
17977                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17978                 if (INTEL_GEN(dev_priv) <= 3) {
17979                         error->plane[i].size = I915_READ(DSPSIZE(i));
17980                         error->plane[i].pos = I915_READ(DSPPOS(i));
17981                 }
17982                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17983                         error->plane[i].addr = I915_READ(DSPADDR(i));
17984                 if (INTEL_GEN(dev_priv) >= 4) {
17985                         error->plane[i].surface = I915_READ(DSPSURF(i));
17986                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17987                 }
17988
17989                 error->pipe[i].source = I915_READ(PIPESRC(i));
17990
17991                 if (HAS_GMCH(dev_priv))
17992                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17993         }
17994
17995         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17996                 enum transcoder cpu_transcoder = transcoders[i];
17997
17998                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
17999                         continue;
18000
18001                 error->transcoder[i].available = true;
18002                 error->transcoder[i].power_domain_on =
18003                         __intel_display_power_is_enabled(dev_priv,
18004                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18005                 if (!error->transcoder[i].power_domain_on)
18006                         continue;
18007
18008                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18009
18010                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
18011                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
18012                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
18013                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
18014                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
18015                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
18016                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
18017         }
18018
18019         return error;
18020 }
18021
18022 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18023
18024 void
18025 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18026                                 struct intel_display_error_state *error)
18027 {
18028         struct drm_i915_private *dev_priv = m->i915;
18029         int i;
18030
18031         if (!error)
18032                 return;
18033
18034         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18035         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18036                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18037                            error->power_well_driver);
18038         for_each_pipe(dev_priv, i) {
18039                 err_printf(m, "Pipe [%d]:\n", i);
18040                 err_printf(m, "  Power: %s\n",
18041                            onoff(error->pipe[i].power_domain_on));
18042                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18043                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18044
18045                 err_printf(m, "Plane [%d]:\n", i);
18046                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18047                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18048                 if (INTEL_GEN(dev_priv) <= 3) {
18049                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18050                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18051                 }
18052                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18053                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18054                 if (INTEL_GEN(dev_priv) >= 4) {
18055                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18056                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18057                 }
18058
18059                 err_printf(m, "Cursor [%d]:\n", i);
18060                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18061                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18062                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18063         }
18064
18065         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18066                 if (!error->transcoder[i].available)
18067                         continue;
18068
18069                 err_printf(m, "CPU transcoder: %s\n",
18070                            transcoder_name(error->transcoder[i].cpu_transcoder));
18071                 err_printf(m, "  Power: %s\n",
18072                            onoff(error->transcoder[i].power_domain_on));
18073                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18074                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18075                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18076                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18077                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18078                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18079                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18080         }
18081 }
18082
18083 #endif