drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <acpi/video.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34 #include <linux/string_helpers.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/display/drm_dp_helper.h>
  38 #include <drm/drm_atomic.h>
  39 #include <drm/drm_atomic_helper.h>
  40 #include <drm/drm_atomic_uapi.h>
  41 #include <drm/drm_damage_helper.h>
  42 #include <drm/drm_edid.h>
  43 #include <drm/drm_fourcc.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_privacy_screen_consumer.h>
  46 #include <drm/drm_probe_helper.h>
  47 #include <drm/drm_rect.h>
  48
  49 #include "display/intel_audio.h"
  50 #include "display/intel_crt.h"
  51 #include "display/intel_ddi.h"
  52 #include "display/intel_display_debugfs.h"
  53 #include "display/intel_display_power.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dp_mst.h"
  56 #include "display/intel_dpll.h"
  57 #include "display/intel_dpll_mgr.h"
  58 #include "display/intel_drrs.h"
  59 #include "display/intel_dsi.h"
  60 #include "display/intel_dvo.h"
  61 #include "display/intel_fb.h"
  62 #include "display/intel_gmbus.h"
  63 #include "display/intel_hdmi.h"
  64 #include "display/intel_lvds.h"
  65 #include "display/intel_sdvo.h"
  66 #include "display/intel_snps_phy.h"
  67 #include "display/intel_tv.h"
  68 #include "display/intel_vdsc.h"
  69 #include "display/intel_vrr.h"
  70
  71 #include "gem/i915_gem_lmem.h"
  72 #include "gem/i915_gem_object.h"
  73
  74 #include "gt/gen8_ppgtt.h"
  75
  76 #include "g4x_dp.h"
  77 #include "g4x_hdmi.h"
  78 #include "hsw_ips.h"
  79 #include "i915_drv.h"
  80 #include "i915_utils.h"
  81 #include "icl_dsi.h"
  82 #include "intel_acpi.h"
  83 #include "intel_atomic.h"
  84 #include "intel_atomic_plane.h"
  85 #include "intel_bw.h"
  86 #include "intel_cdclk.h"
  87 #include "intel_color.h"
  88 #include "intel_crtc.h"
  89 #include "intel_crtc_state_dump.h"
  90 #include "intel_de.h"
  91 #include "intel_display_types.h"
  92 #include "intel_dmc.h"
  93 #include "intel_dp_link_training.h"
  94 #include "intel_dpt.h"
  95 #include "intel_fbc.h"
  96 #include "intel_fbdev.h"
  97 #include "intel_fdi.h"
  98 #include "intel_fifo_underrun.h"
  99 #include "intel_frontbuffer.h"
 100 #include "intel_hdcp.h"
 101 #include "intel_hotplug.h"
 102 #include "intel_modeset_verify.h"
 103 #include "intel_modeset_setup.h"
 104 #include "intel_overlay.h"
 105 #include "intel_panel.h"
 106 #include "intel_pch_display.h"
 107 #include "intel_pch_refclk.h"
 108 #include "intel_pcode.h"
 109 #include "intel_pipe_crc.h"
 110 #include "intel_plane_initial.h"
 111 #include "intel_pm.h"
 112 #include "intel_pps.h"
 113 #include "intel_psr.h"
 114 #include "intel_quirks.h"
 115 #include "intel_sprite.h"
 116 #include "intel_tc.h"
 117 #include "intel_vga.h"
 118 #include "i9xx_plane.h"
 119 #include "skl_scaler.h"
 120 #include "skl_universal_plane.h"
 121 #include "vlv_dsi.h"
 122 #include "vlv_dsi_pll.h"
 123 #include "vlv_dsi_regs.h"
 124 #include "vlv_sideband.h"
 125
 126 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 127 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 128 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 129 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 130 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 131
 132 /**
 133  * intel_update_watermarks - update FIFO watermark values based on current modes
 134  * @dev_priv: i915 device
 135  *
 136  * Calculate watermark values for the various WM regs based on current mode
 137  * and plane configuration.
 138  *
 139  * There are several cases to deal with here:
 140  *   - normal (i.e. non-self-refresh)
 141  *   - self-refresh (SR) mode
 142  *   - lines are large relative to FIFO size (buffer can hold up to 2)
 143  *   - lines are small relative to FIFO size (buffer can hold more than 2
 144  *     lines), so need to account for TLB latency
 145  *
 146  *   The normal calculation is:
 147  *     watermark = dotclock * bytes per pixel * latency
 148  *   where latency is platform & configuration dependent (we assume pessimal
 149  *   values here).
 150  *
 151  *   The SR calculation is:
 152  *     watermark = (trunc(latency/line time)+1) * surface width *
 153  *       bytes per pixel
 154  *   where
 155  *     line time = htotal / dotclock
 156  *     surface width = hdisplay for normal plane and 64 for cursor
 157  *   and latency is assumed to be high, as above.
 158  *
 159  * The final value programmed to the register should always be rounded up,
 160  * and include an extra 2 entries to account for clock crossings.
 161  *
 162  * We don't use the sprite, so we can ignore that.  And on Crestline we have
 163  * to set the non-SR watermarks to 8.
 164  */
 165 void intel_update_watermarks(struct drm_i915_private *dev_priv)
 166 {
 167         if (dev_priv->display.funcs.wm->update_wm)
 168                 dev_priv->display.funcs.wm->update_wm(dev_priv);
 169 }
 170
 171 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
 172                                  struct intel_crtc *crtc)
 173 {
 174         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 175         if (dev_priv->display.funcs.wm->compute_pipe_wm)
 176                 return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
 177         return 0;
 178 }
 179
 180 static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
 181                                          struct intel_crtc *crtc)
 182 {
 183         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 184         if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
 185                 return 0;
 186         if (drm_WARN_ON(&dev_priv->drm,
 187                         !dev_priv->display.funcs.wm->compute_pipe_wm))
 188                 return 0;
 189         return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
 190 }
 191
 192 static bool intel_initial_watermarks(struct intel_atomic_state *state,
 193                                      struct intel_crtc *crtc)
 194 {
 195         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 196         if (dev_priv->display.funcs.wm->initial_watermarks) {
 197                 dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
 198                 return true;
 199         }
 200         return false;
 201 }
 202
 203 static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
 204                                            struct intel_crtc *crtc)
 205 {
 206         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 207         if (dev_priv->display.funcs.wm->atomic_update_watermarks)
 208                 dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc);
 209 }
 210
 211 static void intel_optimize_watermarks(struct intel_atomic_state *state,
 212                                       struct intel_crtc *crtc)
 213 {
 214         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 215         if (dev_priv->display.funcs.wm->optimize_watermarks)
 216                 dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
 217 }
 218
 219 static int intel_compute_global_watermarks(struct intel_atomic_state *state)
 220 {
 221         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 222         if (dev_priv->display.funcs.wm->compute_global_watermarks)
 223                 return dev_priv->display.funcs.wm->compute_global_watermarks(state);
 224         return 0;
 225 }
 226
 227 /* returns HPLL frequency in kHz */
 228 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 229 {
 230         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 231
 232         /* Obtain SKU information */
 233         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 234                 CCK_FUSE_HPLL_FREQ_MASK;
 235
 236         return vco_freq[hpll_freq] * 1000;
 237 }
 238
 239 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 240                       const char *name, u32 reg, int ref_freq)
 241 {
 242         u32 val;
 243         int divider;
 244
 245         val = vlv_cck_read(dev_priv, reg);
 246         divider = val & CCK_FREQUENCY_VALUES;
 247
 248         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 249                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 250                  "%s change in progress\n", name);
 251
 252         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 253 }
 254
 255 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 256                            const char *name, u32 reg)
 257 {
 258         int hpll;
 259
 260         vlv_cck_get(dev_priv);
 261
 262         if (dev_priv->hpll_freq == 0)
 263                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 264
 265         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 266
 267         vlv_cck_put(dev_priv);
 268
 269         return hpll;
 270 }
 271
 272 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 273 {
 274         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 275                 return;
 276
 277         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 278                                                       CCK_CZ_CLOCK_CONTROL);
 279
 280         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 281                 dev_priv->czclk_freq);
 282 }
 283
 284 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 285 {
 286         return (crtc_state->active_planes &
 287                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 288 }
 289
 290 /* WA Display #0827: Gen9:all */
 291 static void
 292 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 293 {
 294         if (enable)
 295                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 296                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 297         else
 298                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 299                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 300 }
 301
 302 /* Wa_2006604312:icl,ehl */
 303 static void
 304 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 305                        bool enable)
 306 {
 307         if (enable)
 308                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 309                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 310         else
 311                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 312                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 313 }
 314
 315 /* Wa_1604331009:icl,jsl,ehl */
 316 static void
 317 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 318                        bool enable)
 319 {
 320         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 321                      enable ? CURSOR_GATING_DIS : 0);
 322 }
 323
 324 static bool
 325 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 326 {
 327         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 328 }
 329
 330 static bool
 331 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 332 {
 333         return crtc_state->sync_mode_slaves_mask != 0;
 334 }
 335
 336 bool
 337 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 338 {
 339         return is_trans_port_sync_master(crtc_state) ||
 340                 is_trans_port_sync_slave(crtc_state);
 341 }
 342
 343 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 344 {
 345         return ffs(crtc_state->bigjoiner_pipes) - 1;
 346 }
 347
 348 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 349 {
 350         if (crtc_state->bigjoiner_pipes)
 351                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 352         else
 353                 return 0;
 354 }
 355
 356 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 357 {
 358         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 359
 360         return crtc_state->bigjoiner_pipes &&
 361                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 362 }
 363
 364 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 365 {
 366         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 367
 368         return crtc_state->bigjoiner_pipes &&
 369                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 370 }
 371
 372 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 373 {
 374         return hweight8(crtc_state->bigjoiner_pipes);
 375 }
 376
 377 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 378 {
 379         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 380
 381         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 382                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 383         else
 384                 return to_intel_crtc(crtc_state->uapi.crtc);
 385 }
 386
 387 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 388                                     enum pipe pipe)
 389 {
 390         i915_reg_t reg = PIPEDSL(pipe);
 391         u32 line1, line2;
 392
 393         line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 394         msleep(5);
 395         line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 396
 397         return line1 != line2;
 398 }
 399
 400 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
 401 {
 402         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 403         enum pipe pipe = crtc->pipe;
 404
 405         /* Wait for the display line to settle/start moving */
 406         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
 407                 drm_err(&dev_priv->drm,
 408                         "pipe %c scanline %s wait timed out\n",
 409                         pipe_name(pipe), str_on_off(state));
 410 }
 411
 412 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
 413 {
 414         wait_for_pipe_scanline_moving(crtc, false);
 415 }
 416
 417 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
 418 {
 419         wait_for_pipe_scanline_moving(crtc, true);
 420 }
 421
 422 static void
 423 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 424 {
 425         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 426         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 427
 428         if (DISPLAY_VER(dev_priv) >= 4) {
 429                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 430
 431                 /* Wait for the Pipe State to go off */
 432                 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
 433                                             PIPECONF_STATE_ENABLE, 100))
 434                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 435         } else {
 436                 intel_wait_for_pipe_scanline_stopped(crtc);
 437         }
 438 }
 439
 440 void assert_transcoder(struct drm_i915_private *dev_priv,
 441                        enum transcoder cpu_transcoder, bool state)
 442 {
 443         bool cur_state;
 444         enum intel_display_power_domain power_domain;
 445         intel_wakeref_t wakeref;
 446
 447         /* we keep both pipes enabled on 830 */
 448         if (IS_I830(dev_priv))
 449                 state = true;
 450
 451         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 452         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 453         if (wakeref) {
 454                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
 455                 cur_state = !!(val & PIPECONF_ENABLE);
 456
 457                 intel_display_power_put(dev_priv, power_domain, wakeref);
 458         } else {
 459                 cur_state = false;
 460         }
 461
 462         I915_STATE_WARN(cur_state != state,
 463                         "transcoder %s assertion failure (expected %s, current %s)\n",
 464                         transcoder_name(cpu_transcoder),
 465                         str_on_off(state), str_on_off(cur_state));
 466 }
 467
 468 static void assert_plane(struct intel_plane *plane, bool state)
 469 {
 470         enum pipe pipe;
 471         bool cur_state;
 472
 473         cur_state = plane->get_hw_state(plane, &pipe);
 474
 475         I915_STATE_WARN(cur_state != state,
 476                         "%s assertion failure (expected %s, current %s)\n",
 477                         plane->base.name, str_on_off(state),
 478                         str_on_off(cur_state));
 479 }
 480
 481 #define assert_plane_enabled(p) assert_plane(p, true)
 482 #define assert_plane_disabled(p) assert_plane(p, false)
 483
 484 static void assert_planes_disabled(struct intel_crtc *crtc)
 485 {
 486         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 487         struct intel_plane *plane;
 488
 489         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 490                 assert_plane_disabled(plane);
 491 }
 492
 493 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 494                          struct intel_digital_port *dig_port,
 495                          unsigned int expected_mask)
 496 {
 497         u32 port_mask;
 498         i915_reg_t dpll_reg;
 499
 500         switch (dig_port->base.port) {
 501         default:
 502                 MISSING_CASE(dig_port->base.port);
 503                 fallthrough;
 504         case PORT_B:
 505                 port_mask = DPLL_PORTB_READY_MASK;
 506                 dpll_reg = DPLL(0);
 507                 break;
 508         case PORT_C:
 509                 port_mask = DPLL_PORTC_READY_MASK;
 510                 dpll_reg = DPLL(0);
 511                 expected_mask <<= 4;
 512                 break;
 513         case PORT_D:
 514                 port_mask = DPLL_PORTD_READY_MASK;
 515                 dpll_reg = DPIO_PHY_STATUS;
 516                 break;
 517         }
 518
 519         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 520                                        port_mask, expected_mask, 1000))
 521                 drm_WARN(&dev_priv->drm, 1,
 522                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 523                          dig_port->base.base.base.id, dig_port->base.base.name,
 524                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 525                          expected_mask);
 526 }
 527
 528 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 529 {
 530         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 532         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 533         enum pipe pipe = crtc->pipe;
 534         i915_reg_t reg;
 535         u32 val;
 536
 537         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 538
 539         assert_planes_disabled(crtc);
 540
 541         /*
 542          * A pipe without a PLL won't actually be able to drive bits from
 543          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 544          * need the check.
 545          */
 546         if (HAS_GMCH(dev_priv)) {
 547                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 548                         assert_dsi_pll_enabled(dev_priv);
 549                 else
 550                         assert_pll_enabled(dev_priv, pipe);
 551         } else {
 552                 if (new_crtc_state->has_pch_encoder) {
 553                         /* if driving the PCH, we need FDI enabled */
 554                         assert_fdi_rx_pll_enabled(dev_priv,
 555                                                   intel_crtc_pch_transcoder(crtc));
 556                         assert_fdi_tx_pll_enabled(dev_priv,
 557                                                   (enum pipe) cpu_transcoder);
 558                 }
 559                 /* FIXME: assert CPU port conditions for SNB+ */
 560         }
 561
 562         /* Wa_22012358565:adl-p */
 563         if (DISPLAY_VER(dev_priv) == 13)
 564                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 565                              0, PIPE_ARB_USE_PROG_SLOTS);
 566
 567         reg = PIPECONF(cpu_transcoder);
 568         val = intel_de_read(dev_priv, reg);
 569         if (val & PIPECONF_ENABLE) {
 570                 /* we keep both pipes enabled on 830 */
 571                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 572                 return;
 573         }
 574
 575         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
 576         intel_de_posting_read(dev_priv, reg);
 577
 578         /*
 579          * Until the pipe starts PIPEDSL reads will return a stale value,
 580          * which causes an apparent vblank timestamp jump when PIPEDSL
 581          * resets to its proper value. That also messes up the frame count
 582          * when it's derived from the timestamps. So let's wait for the
 583          * pipe to start properly before we call drm_crtc_vblank_on()
 584          */
 585         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 586                 intel_wait_for_pipe_scanline_moving(crtc);
 587 }
 588
 589 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 590 {
 591         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 592         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 593         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 594         enum pipe pipe = crtc->pipe;
 595         i915_reg_t reg;
 596         u32 val;
 597
 598         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 599
 600         /*
 601          * Make sure planes won't keep trying to pump pixels to us,
 602          * or we might hang the display.
 603          */
 604         assert_planes_disabled(crtc);
 605
 606         reg = PIPECONF(cpu_transcoder);
 607         val = intel_de_read(dev_priv, reg);
 608         if ((val & PIPECONF_ENABLE) == 0)
 609                 return;
 610
 611         /*
 612          * Double wide has implications for planes
 613          * so best keep it disabled when not needed.
 614          */
 615         if (old_crtc_state->double_wide)
 616                 val &= ~PIPECONF_DOUBLE_WIDE;
 617
 618         /* Don't disable pipe or pipe PLLs if needed */
 619         if (!IS_I830(dev_priv))
 620                 val &= ~PIPECONF_ENABLE;
 621
 622         if (DISPLAY_VER(dev_priv) >= 12)
 623                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 624                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 625
 626         intel_de_write(dev_priv, reg, val);
 627         if ((val & PIPECONF_ENABLE) == 0)
 628                 intel_wait_for_pipe_off(old_crtc_state);
 629 }
 630
 631 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 632 {
 633         unsigned int size = 0;
 634         int i;
 635
 636         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 637                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 638
 639         return size;
 640 }
 641
 642 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 643 {
 644         unsigned int size = 0;
 645         int i;
 646
 647         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 648                 unsigned int plane_size;
 649
 650                 if (rem_info->plane[i].linear)
 651                         plane_size = rem_info->plane[i].size;
 652                 else
 653                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 654
 655                 if (plane_size == 0)
 656                         continue;
 657
 658                 if (rem_info->plane_alignment)
 659                         size = ALIGN(size, rem_info->plane_alignment);
 660
 661                 size += plane_size;
 662         }
 663
 664         return size;
 665 }
 666
 667 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 668 {
 669         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 670         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 671
 672         return DISPLAY_VER(dev_priv) < 4 ||
 673                 (plane->fbc &&
 674                  plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
 675 }
 676
 677 /*
 678  * Convert the x/y offsets into a linear offset.
 679  * Only valid with 0/180 degree rotation, which is fine since linear
 680  * offset is only used with linear buffers on pre-hsw and tiled buffers
 681  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 682  */
 683 u32 intel_fb_xy_to_linear(int x, int y,
 684                           const struct intel_plane_state *state,
 685                           int color_plane)
 686 {
 687         const struct drm_framebuffer *fb = state->hw.fb;
 688         unsigned int cpp = fb->format->cpp[color_plane];
 689         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 690
 691         return y * pitch + x * cpp;
 692 }
 693
 694 /*
 695  * Add the x/y offsets derived from fb->offsets[] to the user
 696  * specified plane src x/y offsets. The resulting x/y offsets
 697  * specify the start of scanout from the beginning of the gtt mapping.
 698  */
 699 void intel_add_fb_offsets(int *x, int *y,
 700                           const struct intel_plane_state *state,
 701                           int color_plane)
 702
 703 {
 704         *x += state->view.color_plane[color_plane].x;
 705         *y += state->view.color_plane[color_plane].y;
 706 }
 707
 708 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 709                               u32 pixel_format, u64 modifier)
 710 {
 711         struct intel_crtc *crtc;
 712         struct intel_plane *plane;
 713
 714         if (!HAS_DISPLAY(dev_priv))
 715                 return 0;
 716
 717         /*
 718          * We assume the primary plane for pipe A has
 719          * the highest stride limits of them all,
 720          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 721          */
 722         crtc = intel_first_crtc(dev_priv);
 723         if (!crtc)
 724                 return 0;
 725
 726         plane = to_intel_plane(crtc->base.primary);
 727
 728         return plane->max_stride(plane, pixel_format, modifier,
 729                                  DRM_MODE_ROTATE_0);
 730 }
 731
 732 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 733                              struct intel_plane_state *plane_state,
 734                              bool visible)
 735 {
 736         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 737
 738         plane_state->uapi.visible = visible;
 739
 740         if (visible)
 741                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 742         else
 743                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 744 }
 745
 746 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 747 {
 748         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 749         struct drm_plane *plane;
 750
 751         /*
 752          * Active_planes aliases if multiple "primary" or cursor planes
 753          * have been used on the same (or wrong) pipe. plane_mask uses
 754          * unique ids, hence we can use that to reconstruct active_planes.
 755          */
 756         crtc_state->enabled_planes = 0;
 757         crtc_state->active_planes = 0;
 758
 759         drm_for_each_plane_mask(plane, &dev_priv->drm,
 760                                 crtc_state->uapi.plane_mask) {
 761                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 762                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 763         }
 764 }
 765
 766 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 767                                   struct intel_plane *plane)
 768 {
 769         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 770         struct intel_crtc_state *crtc_state =
 771                 to_intel_crtc_state(crtc->base.state);
 772         struct intel_plane_state *plane_state =
 773                 to_intel_plane_state(plane->base.state);
 774
 775         drm_dbg_kms(&dev_priv->drm,
 776                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 777                     plane->base.base.id, plane->base.name,
 778                     crtc->base.base.id, crtc->base.name);
 779
 780         intel_set_plane_visible(crtc_state, plane_state, false);
 781         intel_plane_fixup_bitmasks(crtc_state);
 782         crtc_state->data_rate[plane->id] = 0;
 783         crtc_state->data_rate_y[plane->id] = 0;
 784         crtc_state->rel_data_rate[plane->id] = 0;
 785         crtc_state->rel_data_rate_y[plane->id] = 0;
 786         crtc_state->min_cdclk[plane->id] = 0;
 787
 788         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 789             hsw_ips_disable(crtc_state)) {
 790                 crtc_state->ips_enabled = false;
 791                 intel_crtc_wait_for_next_vblank(crtc);
 792         }
 793
 794         /*
 795          * Vblank time updates from the shadow to live plane control register
 796          * are blocked if the memory self-refresh mode is active at that
 797          * moment. So to make sure the plane gets truly disabled, disable
 798          * first the self-refresh mode. The self-refresh enable bit in turn
 799          * will be checked/applied by the HW only at the next frame start
 800          * event which is after the vblank start event, so we need to have a
 801          * wait-for-vblank between disabling the plane and the pipe.
 802          */
 803         if (HAS_GMCH(dev_priv) &&
 804             intel_set_memory_cxsr(dev_priv, false))
 805                 intel_crtc_wait_for_next_vblank(crtc);
 806
 807         /*
 808          * Gen2 reports pipe underruns whenever all planes are disabled.
 809          * So disable underrun reporting before all the planes get disabled.
 810          */
 811         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 812                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 813
 814         intel_plane_disable_arm(plane, crtc_state);
 815         intel_crtc_wait_for_next_vblank(crtc);
 816 }
 817
 818 unsigned int
 819 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 820 {
 821         int x = 0, y = 0;
 822
 823         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 824                                           plane_state->view.color_plane[0].offset, 0);
 825
 826         return y;
 827 }
 828
 829 static int
 830 __intel_display_resume(struct drm_i915_private *i915,
 831                        struct drm_atomic_state *state,
 832                        struct drm_modeset_acquire_ctx *ctx)
 833 {
 834         struct drm_crtc_state *crtc_state;
 835         struct drm_crtc *crtc;
 836         int i, ret;
 837
 838         intel_modeset_setup_hw_state(i915, ctx);
 839         intel_vga_redisable(i915);
 840
 841         if (!state)
 842                 return 0;
 843
 844         /*
 845          * We've duplicated the state, pointers to the old state are invalid.
 846          *
 847          * Don't attempt to use the old state until we commit the duplicated state.
 848          */
 849         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 850                 /*
 851                  * Force recalculation even if we restore
 852                  * current state. With fast modeset this may not result
 853                  * in a modeset when the state is compatible.
 854                  */
 855                 crtc_state->mode_changed = true;
 856         }
 857
 858         /* ignore any reset values/BIOS leftovers in the WM registers */
 859         if (!HAS_GMCH(i915))
 860                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
 861
 862         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
 863
 864         drm_WARN_ON(&i915->drm, ret == -EDEADLK);
 865
 866         return ret;
 867 }
 868
 869 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 870 {
 871         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
 872                 intel_has_gpu_reset(to_gt(dev_priv)));
 873 }
 874
 875 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
 876 {
 877         struct drm_device *dev = &dev_priv->drm;
 878         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
 879         struct drm_atomic_state *state;
 880         int ret;
 881
 882         if (!HAS_DISPLAY(dev_priv))
 883                 return;
 884
 885         /* reset doesn't touch the display */
 886         if (!dev_priv->params.force_reset_modeset_test &&
 887             !gpu_reset_clobbers_display(dev_priv))
 888                 return;
 889
 890         /* We have a modeset vs reset deadlock, defensively unbreak it. */
 891         set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
 892         smp_mb__after_atomic();
 893         wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
 894
 895         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
 896                 drm_dbg_kms(&dev_priv->drm,
 897                             "Modeset potentially stuck, unbreaking through wedging\n");
 898                 intel_gt_set_wedged(to_gt(dev_priv));
 899         }
 900
 901         /*
 902          * Need mode_config.mutex so that we don't
 903          * trample ongoing ->detect() and whatnot.
 904          */
 905         mutex_lock(&dev->mode_config.mutex);
 906         drm_modeset_acquire_init(ctx, 0);
 907         while (1) {
 908                 ret = drm_modeset_lock_all_ctx(dev, ctx);
 909                 if (ret != -EDEADLK)
 910                         break;
 911
 912                 drm_modeset_backoff(ctx);
 913         }
 914         /*
 915          * Disabling the crtcs gracefully seems nicer. Also the
 916          * g33 docs say we should at least disable all the planes.
 917          */
 918         state = drm_atomic_helper_duplicate_state(dev, ctx);
 919         if (IS_ERR(state)) {
 920                 ret = PTR_ERR(state);
 921                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
 922                         ret);
 923                 return;
 924         }
 925
 926         ret = drm_atomic_helper_disable_all(dev, ctx);
 927         if (ret) {
 928                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
 929                         ret);
 930                 drm_atomic_state_put(state);
 931                 return;
 932         }
 933
 934         dev_priv->modeset_restore_state = state;
 935         state->acquire_ctx = ctx;
 936 }
 937
 938 void intel_display_finish_reset(struct drm_i915_private *i915)
 939 {
 940         struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx;
 941         struct drm_atomic_state *state;
 942         int ret;
 943
 944         if (!HAS_DISPLAY(i915))
 945                 return;
 946
 947         /* reset doesn't touch the display */
 948         if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
 949                 return;
 950
 951         state = fetch_and_zero(&i915->modeset_restore_state);
 952         if (!state)
 953                 goto unlock;
 954
 955         /* reset doesn't touch the display */
 956         if (!gpu_reset_clobbers_display(i915)) {
 957                 /* for testing only restore the display */
 958                 ret = __intel_display_resume(i915, state, ctx);
 959                 if (ret)
 960                         drm_err(&i915->drm,
 961                                 "Restoring old state failed with %i\n", ret);
 962         } else {
 963                 /*
 964                  * The display has been reset as well,
 965                  * so need a full re-initialization.
 966                  */
 967                 intel_pps_unlock_regs_wa(i915);
 968                 intel_modeset_init_hw(i915);
 969                 intel_init_clock_gating(i915);
 970                 intel_hpd_init(i915);
 971
 972                 ret = __intel_display_resume(i915, state, ctx);
 973                 if (ret)
 974                         drm_err(&i915->drm,
 975                                 "Restoring old state failed with %i\n", ret);
 976
 977                 intel_hpd_poll_disable(i915);
 978         }
 979
 980         drm_atomic_state_put(state);
 981 unlock:
 982         drm_modeset_drop_locks(ctx);
 983         drm_modeset_acquire_fini(ctx);
 984         mutex_unlock(&i915->drm.mode_config.mutex);
 985
 986         clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
 987 }
 988
 989 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 990 {
 991         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 992         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 993         enum pipe pipe = crtc->pipe;
 994         u32 tmp;
 995
 996         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 997
 998         /*
 999          * Display WA #1153: icl
1000          * enable hardware to bypass the alpha math
1001          * and rounding for per-pixel values 00 and 0xff
1002          */
1003         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
1004         /*
1005          * Display WA # 1605353570: icl
1006          * Set the pixel rounding bit to 1 for allowing
1007          * passthrough of Frame buffer pixels unmodified
1008          * across pipe
1009          */
1010         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
1011
1012         /*
1013          * Underrun recovery must always be disabled on display 13+.
1014          * DG2 chicken bit meaning is inverted compared to other platforms.
1015          */
1016         if (IS_DG2(dev_priv))
1017                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
1018         else if (DISPLAY_VER(dev_priv) >= 13)
1019                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
1020
1021         /* Wa_14010547955:dg2 */
1022         if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
1023                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
1024
1025         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
1026 }
1027
1028 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
1029 {
1030         struct drm_crtc *crtc;
1031         bool cleanup_done;
1032
1033         drm_for_each_crtc(crtc, &dev_priv->drm) {
1034                 struct drm_crtc_commit *commit;
1035                 spin_lock(&crtc->commit_lock);
1036                 commit = list_first_entry_or_null(&crtc->commit_list,
1037                                                   struct drm_crtc_commit, commit_entry);
1038                 cleanup_done = commit ?
1039                         try_wait_for_completion(&commit->cleanup_done) : true;
1040                 spin_unlock(&crtc->commit_lock);
1041
1042                 if (cleanup_done)
1043                         continue;
1044
1045                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
1046
1047                 return true;
1048         }
1049
1050         return false;
1051 }
1052
1053 /*
1054  * Finds the encoder associated with the given CRTC. This can only be
1055  * used when we know that the CRTC isn't feeding multiple encoders!
1056  */
1057 struct intel_encoder *
1058 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
1059                            const struct intel_crtc_state *crtc_state)
1060 {
1061         const struct drm_connector_state *connector_state;
1062         const struct drm_connector *connector;
1063         struct intel_encoder *encoder = NULL;
1064         struct intel_crtc *master_crtc;
1065         int num_encoders = 0;
1066         int i;
1067
1068         master_crtc = intel_master_crtc(crtc_state);
1069
1070         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
1071                 if (connector_state->crtc != &master_crtc->base)
1072                         continue;
1073
1074                 encoder = to_intel_encoder(connector_state->best_encoder);
1075                 num_encoders++;
1076         }
1077
1078         drm_WARN(encoder->base.dev, num_encoders != 1,
1079                  "%d encoders for pipe %c\n",
1080                  num_encoders, pipe_name(master_crtc->pipe));
1081
1082         return encoder;
1083 }
1084
1085 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
1086                                enum pipe pipe)
1087 {
1088         i915_reg_t dslreg = PIPEDSL(pipe);
1089         u32 temp;
1090
1091         temp = intel_de_read(dev_priv, dslreg);
1092         udelay(500);
1093         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
1094                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
1095                         drm_err(&dev_priv->drm,
1096                                 "mode set failed: pipe %c stuck\n",
1097                                 pipe_name(pipe));
1098         }
1099 }
1100
1101 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
1102 {
1103         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1105         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
1106         enum pipe pipe = crtc->pipe;
1107         int width = drm_rect_width(dst);
1108         int height = drm_rect_height(dst);
1109         int x = dst->x1;
1110         int y = dst->y1;
1111
1112         if (!crtc_state->pch_pfit.enabled)
1113                 return;
1114
1115         /* Force use of hard-coded filter coefficients
1116          * as some pre-programmed values are broken,
1117          * e.g. x201.
1118          */
1119         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
1120                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1121                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
1122         else
1123                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1124                                   PF_FILTER_MED_3x3);
1125         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
1126         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
1127 }
1128
1129 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
1130 {
1131         if (crtc->overlay)
1132                 (void) intel_overlay_switch_off(crtc->overlay);
1133
1134         /* Let userspace switch the overlay on again. In most cases userspace
1135          * has to recompute where to put it anyway.
1136          */
1137 }
1138
1139 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
1140 {
1141         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1142
1143         if (!crtc_state->nv12_planes)
1144                 return false;
1145
1146         /* WA Display #0827: Gen9:all */
1147         if (DISPLAY_VER(dev_priv) == 9)
1148                 return true;
1149
1150         return false;
1151 }
1152
1153 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
1154 {
1155         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1156
1157         /* Wa_2006604312:icl,ehl */
1158         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
1159                 return true;
1160
1161         return false;
1162 }
1163
1164 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
1165 {
1166         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1167
1168         /* Wa_1604331009:icl,jsl,ehl */
1169         if (is_hdr_mode(crtc_state) &&
1170             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1171             DISPLAY_VER(dev_priv) == 11)
1172                 return true;
1173
1174         return false;
1175 }
1176
1177 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1178                                     enum pipe pipe, bool enable)
1179 {
1180         if (DISPLAY_VER(i915) == 9) {
1181                 /*
1182                  * "Plane N strech max must be programmed to 11b (x1)
1183                  *  when Async flips are enabled on that plane."
1184                  */
1185                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1186                              SKL_PLANE1_STRETCH_MAX_MASK,
1187                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1188         } else {
1189                 /* Also needed on HSW/BDW albeit undocumented */
1190                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1191                              HSW_PRI_STRETCH_MAX_MASK,
1192                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1193         }
1194 }
1195
1196 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1197 {
1198         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1199
1200         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1201                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1202 }
1203
1204 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1205                             const struct intel_crtc_state *new_crtc_state)
1206 {
1207         return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
1208                 new_crtc_state->active_planes;
1209 }
1210
1211 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1212                              const struct intel_crtc_state *new_crtc_state)
1213 {
1214         return old_crtc_state->active_planes &&
1215                 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
1216 }
1217
1218 static void intel_post_plane_update(struct intel_atomic_state *state,
1219                                     struct intel_crtc *crtc)
1220 {
1221         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1222         const struct intel_crtc_state *old_crtc_state =
1223                 intel_atomic_get_old_crtc_state(state, crtc);
1224         const struct intel_crtc_state *new_crtc_state =
1225                 intel_atomic_get_new_crtc_state(state, crtc);
1226         enum pipe pipe = crtc->pipe;
1227
1228         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1229
1230         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1231                 intel_update_watermarks(dev_priv);
1232
1233         hsw_ips_post_update(state, crtc);
1234         intel_fbc_post_update(state, crtc);
1235
1236         if (needs_async_flip_vtd_wa(old_crtc_state) &&
1237             !needs_async_flip_vtd_wa(new_crtc_state))
1238                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1239
1240         if (needs_nv12_wa(old_crtc_state) &&
1241             !needs_nv12_wa(new_crtc_state))
1242                 skl_wa_827(dev_priv, pipe, false);
1243
1244         if (needs_scalerclk_wa(old_crtc_state) &&
1245             !needs_scalerclk_wa(new_crtc_state))
1246                 icl_wa_scalerclkgating(dev_priv, pipe, false);
1247
1248         if (needs_cursorclk_wa(old_crtc_state) &&
1249             !needs_cursorclk_wa(new_crtc_state))
1250                 icl_wa_cursorclkgating(dev_priv, pipe, false);
1251
1252         intel_drrs_activate(new_crtc_state);
1253 }
1254
1255 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1256                                         struct intel_crtc *crtc)
1257 {
1258         const struct intel_crtc_state *crtc_state =
1259                 intel_atomic_get_new_crtc_state(state, crtc);
1260         u8 update_planes = crtc_state->update_planes;
1261         const struct intel_plane_state *plane_state;
1262         struct intel_plane *plane;
1263         int i;
1264
1265         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1266                 if (plane->pipe == crtc->pipe &&
1267                     update_planes & BIT(plane->id))
1268                         plane->enable_flip_done(plane);
1269         }
1270 }
1271
1272 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1273                                          struct intel_crtc *crtc)
1274 {
1275         const struct intel_crtc_state *crtc_state =
1276                 intel_atomic_get_new_crtc_state(state, crtc);
1277         u8 update_planes = crtc_state->update_planes;
1278         const struct intel_plane_state *plane_state;
1279         struct intel_plane *plane;
1280         int i;
1281
1282         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1283                 if (plane->pipe == crtc->pipe &&
1284                     update_planes & BIT(plane->id))
1285                         plane->disable_flip_done(plane);
1286         }
1287 }
1288
1289 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1290                                              struct intel_crtc *crtc)
1291 {
1292         const struct intel_crtc_state *old_crtc_state =
1293                 intel_atomic_get_old_crtc_state(state, crtc);
1294         const struct intel_crtc_state *new_crtc_state =
1295                 intel_atomic_get_new_crtc_state(state, crtc);
1296         u8 update_planes = new_crtc_state->update_planes;
1297         const struct intel_plane_state *old_plane_state;
1298         struct intel_plane *plane;
1299         bool need_vbl_wait = false;
1300         int i;
1301
1302         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1303                 if (plane->need_async_flip_disable_wa &&
1304                     plane->pipe == crtc->pipe &&
1305                     update_planes & BIT(plane->id)) {
1306                         /*
1307                          * Apart from the async flip bit we want to
1308                          * preserve the old state for the plane.
1309                          */
1310                         plane->async_flip(plane, old_crtc_state,
1311                                           old_plane_state, false);
1312                         need_vbl_wait = true;
1313                 }
1314         }
1315
1316         if (need_vbl_wait)
1317                 intel_crtc_wait_for_next_vblank(crtc);
1318 }
1319
1320 static void intel_pre_plane_update(struct intel_atomic_state *state,
1321                                    struct intel_crtc *crtc)
1322 {
1323         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1324         const struct intel_crtc_state *old_crtc_state =
1325                 intel_atomic_get_old_crtc_state(state, crtc);
1326         const struct intel_crtc_state *new_crtc_state =
1327                 intel_atomic_get_new_crtc_state(state, crtc);
1328         enum pipe pipe = crtc->pipe;
1329
1330         intel_drrs_deactivate(old_crtc_state);
1331
1332         intel_psr_pre_plane_update(state, crtc);
1333
1334         if (hsw_ips_pre_update(state, crtc))
1335                 intel_crtc_wait_for_next_vblank(crtc);
1336
1337         if (intel_fbc_pre_update(state, crtc))
1338                 intel_crtc_wait_for_next_vblank(crtc);
1339
1340         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1341             needs_async_flip_vtd_wa(new_crtc_state))
1342                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1343
1344         /* Display WA 827 */
1345         if (!needs_nv12_wa(old_crtc_state) &&
1346             needs_nv12_wa(new_crtc_state))
1347                 skl_wa_827(dev_priv, pipe, true);
1348
1349         /* Wa_2006604312:icl,ehl */
1350         if (!needs_scalerclk_wa(old_crtc_state) &&
1351             needs_scalerclk_wa(new_crtc_state))
1352                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1353
1354         /* Wa_1604331009:icl,jsl,ehl */
1355         if (!needs_cursorclk_wa(old_crtc_state) &&
1356             needs_cursorclk_wa(new_crtc_state))
1357                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1358
1359         /*
1360          * Vblank time updates from the shadow to live plane control register
1361          * are blocked if the memory self-refresh mode is active at that
1362          * moment. So to make sure the plane gets truly disabled, disable
1363          * first the self-refresh mode. The self-refresh enable bit in turn
1364          * will be checked/applied by the HW only at the next frame start
1365          * event which is after the vblank start event, so we need to have a
1366          * wait-for-vblank between disabling the plane and the pipe.
1367          */
1368         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1369             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1370                 intel_crtc_wait_for_next_vblank(crtc);
1371
1372         /*
1373          * IVB workaround: must disable low power watermarks for at least
1374          * one frame before enabling scaling.  LP watermarks can be re-enabled
1375          * when scaling is disabled.
1376          *
1377          * WaCxSRDisabledForSpriteScaling:ivb
1378          */
1379         if (old_crtc_state->hw.active &&
1380             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1381                 intel_crtc_wait_for_next_vblank(crtc);
1382
1383         /*
1384          * If we're doing a modeset we don't need to do any
1385          * pre-vblank watermark programming here.
1386          */
1387         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1388                 /*
1389                  * For platforms that support atomic watermarks, program the
1390                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1391                  * will be the intermediate values that are safe for both pre- and
1392                  * post- vblank; when vblank happens, the 'active' values will be set
1393                  * to the final 'target' values and we'll do this again to get the
1394                  * optimal watermarks.  For gen9+ platforms, the values we program here
1395                  * will be the final target values which will get automatically latched
1396                  * at vblank time; no further programming will be necessary.
1397                  *
1398                  * If a platform hasn't been transitioned to atomic watermarks yet,
1399                  * we'll continue to update watermarks the old way, if flags tell
1400                  * us to.
1401                  */
1402                 if (!intel_initial_watermarks(state, crtc))
1403                         if (new_crtc_state->update_wm_pre)
1404                                 intel_update_watermarks(dev_priv);
1405         }
1406
1407         /*
1408          * Gen2 reports pipe underruns whenever all planes are disabled.
1409          * So disable underrun reporting before all the planes get disabled.
1410          *
1411          * We do this after .initial_watermarks() so that we have a
1412          * chance of catching underruns with the intermediate watermarks
1413          * vs. the old plane configuration.
1414          */
1415         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1416                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1417
1418         /*
1419          * WA for platforms where async address update enable bit
1420          * is double buffered and only latched at start of vblank.
1421          */
1422         if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
1423                 intel_crtc_async_flip_disable_wa(state, crtc);
1424 }
1425
1426 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1427                                       struct intel_crtc *crtc)
1428 {
1429         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1430         const struct intel_crtc_state *new_crtc_state =
1431                 intel_atomic_get_new_crtc_state(state, crtc);
1432         unsigned int update_mask = new_crtc_state->update_planes;
1433         const struct intel_plane_state *old_plane_state;
1434         struct intel_plane *plane;
1435         unsigned fb_bits = 0;
1436         int i;
1437
1438         intel_crtc_dpms_overlay_disable(crtc);
1439
1440         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1441                 if (crtc->pipe != plane->pipe ||
1442                     !(update_mask & BIT(plane->id)))
1443                         continue;
1444
1445                 intel_plane_disable_arm(plane, new_crtc_state);
1446
1447                 if (old_plane_state->uapi.visible)
1448                         fb_bits |= plane->frontbuffer_bit;
1449         }
1450
1451         intel_frontbuffer_flip(dev_priv, fb_bits);
1452 }
1453
1454 /*
1455  * intel_connector_primary_encoder - get the primary encoder for a connector
1456  * @connector: connector for which to return the encoder
1457  *
1458  * Returns the primary encoder for a connector. There is a 1:1 mapping from
1459  * all connectors to their encoder, except for DP-MST connectors which have
1460  * both a virtual and a primary encoder. These DP-MST primary encoders can be
1461  * pointed to by as many DP-MST connectors as there are pipes.
1462  */
1463 static struct intel_encoder *
1464 intel_connector_primary_encoder(struct intel_connector *connector)
1465 {
1466         struct intel_encoder *encoder;
1467
1468         if (connector->mst_port)
1469                 return &dp_to_dig_port(connector->mst_port)->base;
1470
1471         encoder = intel_attached_encoder(connector);
1472         drm_WARN_ON(connector->base.dev, !encoder);
1473
1474         return encoder;
1475 }
1476
1477 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1478 {
1479         struct drm_i915_private *i915 = to_i915(state->base.dev);
1480         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1481         struct intel_crtc *crtc;
1482         struct drm_connector_state *new_conn_state;
1483         struct drm_connector *connector;
1484         int i;
1485
1486         /*
1487          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1488          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1489          */
1490         if (i915->display.dpll.mgr) {
1491                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1492                         if (intel_crtc_needs_modeset(new_crtc_state))
1493                                 continue;
1494
1495                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1496                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1497                 }
1498         }
1499
1500         if (!state->modeset)
1501                 return;
1502
1503         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1504                                         i) {
1505                 struct intel_connector *intel_connector;
1506                 struct intel_encoder *encoder;
1507                 struct intel_crtc *crtc;
1508
1509                 if (!intel_connector_needs_modeset(state, connector))
1510                         continue;
1511
1512                 intel_connector = to_intel_connector(connector);
1513                 encoder = intel_connector_primary_encoder(intel_connector);
1514                 if (!encoder->update_prepare)
1515                         continue;
1516
1517                 crtc = new_conn_state->crtc ?
1518                         to_intel_crtc(new_conn_state->crtc) : NULL;
1519                 encoder->update_prepare(state, encoder, crtc);
1520         }
1521 }
1522
1523 static void intel_encoders_update_complete(struct intel_atomic_state *state)
1524 {
1525         struct drm_connector_state *new_conn_state;
1526         struct drm_connector *connector;
1527         int i;
1528
1529         if (!state->modeset)
1530                 return;
1531
1532         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1533                                         i) {
1534                 struct intel_connector *intel_connector;
1535                 struct intel_encoder *encoder;
1536                 struct intel_crtc *crtc;
1537
1538                 if (!intel_connector_needs_modeset(state, connector))
1539                         continue;
1540
1541                 intel_connector = to_intel_connector(connector);
1542                 encoder = intel_connector_primary_encoder(intel_connector);
1543                 if (!encoder->update_complete)
1544                         continue;
1545
1546                 crtc = new_conn_state->crtc ?
1547                         to_intel_crtc(new_conn_state->crtc) : NULL;
1548                 encoder->update_complete(state, encoder, crtc);
1549         }
1550 }
1551
1552 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1553                                           struct intel_crtc *crtc)
1554 {
1555         const struct intel_crtc_state *crtc_state =
1556                 intel_atomic_get_new_crtc_state(state, crtc);
1557         const struct drm_connector_state *conn_state;
1558         struct drm_connector *conn;
1559         int i;
1560
1561         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1562                 struct intel_encoder *encoder =
1563                         to_intel_encoder(conn_state->best_encoder);
1564
1565                 if (conn_state->crtc != &crtc->base)
1566                         continue;
1567
1568                 if (encoder->pre_pll_enable)
1569                         encoder->pre_pll_enable(state, encoder,
1570                                                 crtc_state, conn_state);
1571         }
1572 }
1573
1574 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1575                                       struct intel_crtc *crtc)
1576 {
1577         const struct intel_crtc_state *crtc_state =
1578                 intel_atomic_get_new_crtc_state(state, crtc);
1579         const struct drm_connector_state *conn_state;
1580         struct drm_connector *conn;
1581         int i;
1582
1583         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1584                 struct intel_encoder *encoder =
1585                         to_intel_encoder(conn_state->best_encoder);
1586
1587                 if (conn_state->crtc != &crtc->base)
1588                         continue;
1589
1590                 if (encoder->pre_enable)
1591                         encoder->pre_enable(state, encoder,
1592                                             crtc_state, conn_state);
1593         }
1594 }
1595
1596 static void intel_encoders_enable(struct intel_atomic_state *state,
1597                                   struct intel_crtc *crtc)
1598 {
1599         const struct intel_crtc_state *crtc_state =
1600                 intel_atomic_get_new_crtc_state(state, crtc);
1601         const struct drm_connector_state *conn_state;
1602         struct drm_connector *conn;
1603         int i;
1604
1605         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1606                 struct intel_encoder *encoder =
1607                         to_intel_encoder(conn_state->best_encoder);
1608
1609                 if (conn_state->crtc != &crtc->base)
1610                         continue;
1611
1612                 if (encoder->enable)
1613                         encoder->enable(state, encoder,
1614                                         crtc_state, conn_state);
1615                 intel_opregion_notify_encoder(encoder, true);
1616         }
1617 }
1618
1619 static void intel_encoders_disable(struct intel_atomic_state *state,
1620                                    struct intel_crtc *crtc)
1621 {
1622         const struct intel_crtc_state *old_crtc_state =
1623                 intel_atomic_get_old_crtc_state(state, crtc);
1624         const struct drm_connector_state *old_conn_state;
1625         struct drm_connector *conn;
1626         int i;
1627
1628         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1629                 struct intel_encoder *encoder =
1630                         to_intel_encoder(old_conn_state->best_encoder);
1631
1632                 if (old_conn_state->crtc != &crtc->base)
1633                         continue;
1634
1635                 intel_opregion_notify_encoder(encoder, false);
1636                 if (encoder->disable)
1637                         encoder->disable(state, encoder,
1638                                          old_crtc_state, old_conn_state);
1639         }
1640 }
1641
1642 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1643                                         struct intel_crtc *crtc)
1644 {
1645         const struct intel_crtc_state *old_crtc_state =
1646                 intel_atomic_get_old_crtc_state(state, crtc);
1647         const struct drm_connector_state *old_conn_state;
1648         struct drm_connector *conn;
1649         int i;
1650
1651         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1652                 struct intel_encoder *encoder =
1653                         to_intel_encoder(old_conn_state->best_encoder);
1654
1655                 if (old_conn_state->crtc != &crtc->base)
1656                         continue;
1657
1658                 if (encoder->post_disable)
1659                         encoder->post_disable(state, encoder,
1660                                               old_crtc_state, old_conn_state);
1661         }
1662 }
1663
1664 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1665                                             struct intel_crtc *crtc)
1666 {
1667         const struct intel_crtc_state *old_crtc_state =
1668                 intel_atomic_get_old_crtc_state(state, crtc);
1669         const struct drm_connector_state *old_conn_state;
1670         struct drm_connector *conn;
1671         int i;
1672
1673         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1674                 struct intel_encoder *encoder =
1675                         to_intel_encoder(old_conn_state->best_encoder);
1676
1677                 if (old_conn_state->crtc != &crtc->base)
1678                         continue;
1679
1680                 if (encoder->post_pll_disable)
1681                         encoder->post_pll_disable(state, encoder,
1682                                                   old_crtc_state, old_conn_state);
1683         }
1684 }
1685
1686 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1687                                        struct intel_crtc *crtc)
1688 {
1689         const struct intel_crtc_state *crtc_state =
1690                 intel_atomic_get_new_crtc_state(state, crtc);
1691         const struct drm_connector_state *conn_state;
1692         struct drm_connector *conn;
1693         int i;
1694
1695         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1696                 struct intel_encoder *encoder =
1697                         to_intel_encoder(conn_state->best_encoder);
1698
1699                 if (conn_state->crtc != &crtc->base)
1700                         continue;
1701
1702                 if (encoder->update_pipe)
1703                         encoder->update_pipe(state, encoder,
1704                                              crtc_state, conn_state);
1705         }
1706 }
1707
1708 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1709 {
1710         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1711         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1712
1713         plane->disable_arm(plane, crtc_state);
1714 }
1715
1716 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1717 {
1718         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1719         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1720
1721         if (crtc_state->has_pch_encoder) {
1722                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1723                                                &crtc_state->fdi_m_n);
1724         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1725                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1726                                                &crtc_state->dp_m_n);
1727                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1728                                                &crtc_state->dp_m2_n2);
1729         }
1730
1731         intel_set_transcoder_timings(crtc_state);
1732
1733         ilk_set_pipeconf(crtc_state);
1734 }
1735
1736 static void ilk_crtc_enable(struct intel_atomic_state *state,
1737                             struct intel_crtc *crtc)
1738 {
1739         const struct intel_crtc_state *new_crtc_state =
1740                 intel_atomic_get_new_crtc_state(state, crtc);
1741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1742         enum pipe pipe = crtc->pipe;
1743
1744         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1745                 return;
1746
1747         /*
1748          * Sometimes spurious CPU pipe underruns happen during FDI
1749          * training, at least with VGA+HDMI cloning. Suppress them.
1750          *
1751          * On ILK we get an occasional spurious CPU pipe underruns
1752          * between eDP port A enable and vdd enable. Also PCH port
1753          * enable seems to result in the occasional CPU pipe underrun.
1754          *
1755          * Spurious PCH underruns also occur during PCH enabling.
1756          */
1757         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1758         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1759
1760         ilk_configure_cpu_transcoder(new_crtc_state);
1761
1762         intel_set_pipe_src_size(new_crtc_state);
1763
1764         crtc->active = true;
1765
1766         intel_encoders_pre_enable(state, crtc);
1767
1768         if (new_crtc_state->has_pch_encoder) {
1769                 ilk_pch_pre_enable(state, crtc);
1770         } else {
1771                 assert_fdi_tx_disabled(dev_priv, pipe);
1772                 assert_fdi_rx_disabled(dev_priv, pipe);
1773         }
1774
1775         ilk_pfit_enable(new_crtc_state);
1776
1777         /*
1778          * On ILK+ LUT must be loaded before the pipe is running but with
1779          * clocks enabled
1780          */
1781         intel_color_load_luts(new_crtc_state);
1782         intel_color_commit_noarm(new_crtc_state);
1783         intel_color_commit_arm(new_crtc_state);
1784         /* update DSPCNTR to configure gamma for pipe bottom color */
1785         intel_disable_primary_plane(new_crtc_state);
1786
1787         intel_initial_watermarks(state, crtc);
1788         intel_enable_transcoder(new_crtc_state);
1789
1790         if (new_crtc_state->has_pch_encoder)
1791                 ilk_pch_enable(state, crtc);
1792
1793         intel_crtc_vblank_on(new_crtc_state);
1794
1795         intel_encoders_enable(state, crtc);
1796
1797         if (HAS_PCH_CPT(dev_priv))
1798                 cpt_verify_modeset(dev_priv, pipe);
1799
1800         /*
1801          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1802          * And a second vblank wait is needed at least on ILK with
1803          * some interlaced HDMI modes. Let's do the double wait always
1804          * in case there are more corner cases we don't know about.
1805          */
1806         if (new_crtc_state->has_pch_encoder) {
1807                 intel_crtc_wait_for_next_vblank(crtc);
1808                 intel_crtc_wait_for_next_vblank(crtc);
1809         }
1810         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1811         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1812 }
1813
1814 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1815                                             enum pipe pipe, bool apply)
1816 {
1817         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1818         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1819
1820         if (apply)
1821                 val |= mask;
1822         else
1823                 val &= ~mask;
1824
1825         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1826 }
1827
1828 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1829 {
1830         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1831         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832
1833         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1834                        HSW_LINETIME(crtc_state->linetime) |
1835                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1836 }
1837
1838 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1839 {
1840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
1843         u32 val;
1844
1845         val = intel_de_read(dev_priv, reg);
1846         val &= ~HSW_FRAME_START_DELAY_MASK;
1847         val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
1848         intel_de_write(dev_priv, reg, val);
1849 }
1850
1851 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1852                                          const struct intel_crtc_state *crtc_state)
1853 {
1854         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1855
1856         /*
1857          * Enable sequence steps 1-7 on bigjoiner master
1858          */
1859         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1860                 intel_encoders_pre_pll_enable(state, master_crtc);
1861
1862         if (crtc_state->shared_dpll)
1863                 intel_enable_shared_dpll(crtc_state);
1864
1865         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1866                 intel_encoders_pre_enable(state, master_crtc);
1867 }
1868
1869 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1870 {
1871         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1872         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1873         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1874
1875         if (crtc_state->has_pch_encoder) {
1876                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1877                                                &crtc_state->fdi_m_n);
1878         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1879                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1880                                                &crtc_state->dp_m_n);
1881                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1882                                                &crtc_state->dp_m2_n2);
1883         }
1884
1885         intel_set_transcoder_timings(crtc_state);
1886
1887         if (cpu_transcoder != TRANSCODER_EDP)
1888                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
1889                                crtc_state->pixel_multiplier - 1);
1890
1891         hsw_set_frame_start_delay(crtc_state);
1892
1893         hsw_set_transconf(crtc_state);
1894 }
1895
1896 static void hsw_crtc_enable(struct intel_atomic_state *state,
1897                             struct intel_crtc *crtc)
1898 {
1899         const struct intel_crtc_state *new_crtc_state =
1900                 intel_atomic_get_new_crtc_state(state, crtc);
1901         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1902         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1903         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1904         bool psl_clkgate_wa;
1905
1906         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1907                 return;
1908
1909         if (!new_crtc_state->bigjoiner_pipes) {
1910                 intel_encoders_pre_pll_enable(state, crtc);
1911
1912                 if (new_crtc_state->shared_dpll)
1913                         intel_enable_shared_dpll(new_crtc_state);
1914
1915                 intel_encoders_pre_enable(state, crtc);
1916         } else {
1917                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1918         }
1919
1920         intel_dsc_enable(new_crtc_state);
1921
1922         if (DISPLAY_VER(dev_priv) >= 13)
1923                 intel_uncompressed_joiner_enable(new_crtc_state);
1924
1925         intel_set_pipe_src_size(new_crtc_state);
1926         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1927                 bdw_set_pipemisc(new_crtc_state);
1928
1929         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1930             !transcoder_is_dsi(cpu_transcoder))
1931                 hsw_configure_cpu_transcoder(new_crtc_state);
1932
1933         crtc->active = true;
1934
1935         /* Display WA #1180: WaDisableScalarClockGating: glk */
1936         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1937                 new_crtc_state->pch_pfit.enabled;
1938         if (psl_clkgate_wa)
1939                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1940
1941         if (DISPLAY_VER(dev_priv) >= 9)
1942                 skl_pfit_enable(new_crtc_state);
1943         else
1944                 ilk_pfit_enable(new_crtc_state);
1945
1946         /*
1947          * On ILK+ LUT must be loaded before the pipe is running but with
1948          * clocks enabled
1949          */
1950         intel_color_load_luts(new_crtc_state);
1951         intel_color_commit_noarm(new_crtc_state);
1952         intel_color_commit_arm(new_crtc_state);
1953         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1954         if (DISPLAY_VER(dev_priv) < 9)
1955                 intel_disable_primary_plane(new_crtc_state);
1956
1957         hsw_set_linetime_wm(new_crtc_state);
1958
1959         if (DISPLAY_VER(dev_priv) >= 11)
1960                 icl_set_pipe_chicken(new_crtc_state);
1961
1962         intel_initial_watermarks(state, crtc);
1963
1964         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1965                 intel_crtc_vblank_on(new_crtc_state);
1966
1967         intel_encoders_enable(state, crtc);
1968
1969         if (psl_clkgate_wa) {
1970                 intel_crtc_wait_for_next_vblank(crtc);
1971                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1972         }
1973
1974         /* If we change the relative order between pipe/planes enabling, we need
1975          * to change the workaround. */
1976         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1977         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1978                 struct intel_crtc *wa_crtc;
1979
1980                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1981
1982                 intel_crtc_wait_for_next_vblank(wa_crtc);
1983                 intel_crtc_wait_for_next_vblank(wa_crtc);
1984         }
1985 }
1986
1987 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1988 {
1989         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1991         enum pipe pipe = crtc->pipe;
1992
1993         /* To avoid upsetting the power well on haswell only disable the pfit if
1994          * it's in use. The hw state code will make sure we get this right. */
1995         if (!old_crtc_state->pch_pfit.enabled)
1996                 return;
1997
1998         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1999         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
2000         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
2001 }
2002
2003 static void ilk_crtc_disable(struct intel_atomic_state *state,
2004                              struct intel_crtc *crtc)
2005 {
2006         const struct intel_crtc_state *old_crtc_state =
2007                 intel_atomic_get_old_crtc_state(state, crtc);
2008         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2009         enum pipe pipe = crtc->pipe;
2010
2011         /*
2012          * Sometimes spurious CPU pipe underruns happen when the
2013          * pipe is already disabled, but FDI RX/TX is still enabled.
2014          * Happens at least with VGA+HDMI cloning. Suppress them.
2015          */
2016         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2017         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
2018
2019         intel_encoders_disable(state, crtc);
2020
2021         intel_crtc_vblank_off(old_crtc_state);
2022
2023         intel_disable_transcoder(old_crtc_state);
2024
2025         ilk_pfit_disable(old_crtc_state);
2026
2027         if (old_crtc_state->has_pch_encoder)
2028                 ilk_pch_disable(state, crtc);
2029
2030         intel_encoders_post_disable(state, crtc);
2031
2032         if (old_crtc_state->has_pch_encoder)
2033                 ilk_pch_post_disable(state, crtc);
2034
2035         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2036         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
2037 }
2038
2039 static void hsw_crtc_disable(struct intel_atomic_state *state,
2040                              struct intel_crtc *crtc)
2041 {
2042         const struct intel_crtc_state *old_crtc_state =
2043                 intel_atomic_get_old_crtc_state(state, crtc);
2044
2045         /*
2046          * FIXME collapse everything to one hook.
2047          * Need care with mst->ddi interactions.
2048          */
2049         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
2050                 intel_encoders_disable(state, crtc);
2051                 intel_encoders_post_disable(state, crtc);
2052         }
2053 }
2054
2055 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
2056 {
2057         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2058         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2059
2060         if (!crtc_state->gmch_pfit.control)
2061                 return;
2062
2063         /*
2064          * The panel fitter should only be adjusted whilst the pipe is disabled,
2065          * according to register description and PRM.
2066          */
2067         drm_WARN_ON(&dev_priv->drm,
2068                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
2069         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2070
2071         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
2072                        crtc_state->gmch_pfit.pgm_ratios);
2073         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
2074
2075         /* Border color in case we don't scale up to the full screen. Black by
2076          * default, change to something else for debugging. */
2077         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
2078 }
2079
2080 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
2081 {
2082         if (phy == PHY_NONE)
2083                 return false;
2084         else if (IS_ALDERLAKE_S(dev_priv))
2085                 return phy <= PHY_E;
2086         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
2087                 return phy <= PHY_D;
2088         else if (IS_JSL_EHL(dev_priv))
2089                 return phy <= PHY_C;
2090         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
2091                 return phy <= PHY_B;
2092         else
2093                 /*
2094                  * DG2 outputs labelled as "combo PHY" in the bspec use
2095                  * SNPS PHYs with completely different programming,
2096                  * hence we always return false here.
2097                  */
2098                 return false;
2099 }
2100
2101 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
2102 {
2103         if (IS_DG2(dev_priv))
2104                 /* DG2's "TC1" output uses a SNPS PHY */
2105                 return false;
2106         else if (IS_ALDERLAKE_P(dev_priv))
2107                 return phy >= PHY_F && phy <= PHY_I;
2108         else if (IS_TIGERLAKE(dev_priv))
2109                 return phy >= PHY_D && phy <= PHY_I;
2110         else if (IS_ICELAKE(dev_priv))
2111                 return phy >= PHY_C && phy <= PHY_F;
2112         else
2113                 return false;
2114 }
2115
2116 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
2117 {
2118         if (phy == PHY_NONE)
2119                 return false;
2120         else if (IS_DG2(dev_priv))
2121                 /*
2122                  * All four "combo" ports and the TC1 port (PHY E) use
2123                  * Synopsis PHYs.
2124                  */
2125                 return phy <= PHY_E;
2126
2127         return false;
2128 }
2129
2130 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
2131 {
2132         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
2133                 return PHY_D + port - PORT_D_XELPD;
2134         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
2135                 return PHY_F + port - PORT_TC1;
2136         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
2137                 return PHY_B + port - PORT_TC1;
2138         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
2139                 return PHY_C + port - PORT_TC1;
2140         else if (IS_JSL_EHL(i915) && port == PORT_D)
2141                 return PHY_A;
2142
2143         return PHY_A + port - PORT_A;
2144 }
2145
2146 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
2147 {
2148         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
2149                 return TC_PORT_NONE;
2150
2151         if (DISPLAY_VER(dev_priv) >= 12)
2152                 return TC_PORT_1 + port - PORT_TC1;
2153         else
2154                 return TC_PORT_1 + port - PORT_C;
2155 }
2156
2157 enum intel_display_power_domain
2158 intel_aux_power_domain(struct intel_digital_port *dig_port)
2159 {
2160         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
2161
2162         if (intel_tc_port_in_tbt_alt_mode(dig_port))
2163                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
2164
2165         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
2166 }
2167
2168 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2169                                    struct intel_power_domain_mask *mask)
2170 {
2171         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2172         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2173         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2174         struct drm_encoder *encoder;
2175         enum pipe pipe = crtc->pipe;
2176
2177         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2178
2179         if (!crtc_state->hw.active)
2180                 return;
2181
2182         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
2183         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2184         if (crtc_state->pch_pfit.enabled ||
2185             crtc_state->pch_pfit.force_thru)
2186                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2187
2188         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2189                                   crtc_state->uapi.encoder_mask) {
2190                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2191
2192                 set_bit(intel_encoder->power_domain, mask->bits);
2193         }
2194
2195         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2196                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2197
2198         if (crtc_state->shared_dpll)
2199                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2200
2201         if (crtc_state->dsc.compression_enable)
2202                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2203 }
2204
2205 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2206                                           struct intel_power_domain_mask *old_domains)
2207 {
2208         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2209         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2210         enum intel_display_power_domain domain;
2211         struct intel_power_domain_mask domains, new_domains;
2212
2213         get_crtc_power_domains(crtc_state, &domains);
2214
2215         bitmap_andnot(new_domains.bits,
2216                       domains.bits,
2217                       crtc->enabled_power_domains.mask.bits,
2218                       POWER_DOMAIN_NUM);
2219         bitmap_andnot(old_domains->bits,
2220                       crtc->enabled_power_domains.mask.bits,
2221                       domains.bits,
2222                       POWER_DOMAIN_NUM);
2223
2224         for_each_power_domain(domain, &new_domains)
2225                 intel_display_power_get_in_set(dev_priv,
2226                                                &crtc->enabled_power_domains,
2227                                                domain);
2228 }
2229
2230 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2231                                           struct intel_power_domain_mask *domains)
2232 {
2233         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2234                                             &crtc->enabled_power_domains,
2235                                             domains);
2236 }
2237
2238 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2239 {
2240         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2241         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2242
2243         if (intel_crtc_has_dp_encoder(crtc_state)) {
2244                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2245                                                &crtc_state->dp_m_n);
2246                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2247                                                &crtc_state->dp_m2_n2);
2248         }
2249
2250         intel_set_transcoder_timings(crtc_state);
2251
2252         i9xx_set_pipeconf(crtc_state);
2253 }
2254
2255 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2256                                    struct intel_crtc *crtc)
2257 {
2258         const struct intel_crtc_state *new_crtc_state =
2259                 intel_atomic_get_new_crtc_state(state, crtc);
2260         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2261         enum pipe pipe = crtc->pipe;
2262
2263         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2264                 return;
2265
2266         i9xx_configure_cpu_transcoder(new_crtc_state);
2267
2268         intel_set_pipe_src_size(new_crtc_state);
2269
2270         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2271                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2272                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2273         }
2274
2275         crtc->active = true;
2276
2277         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2278
2279         intel_encoders_pre_pll_enable(state, crtc);
2280
2281         if (IS_CHERRYVIEW(dev_priv))
2282                 chv_enable_pll(new_crtc_state);
2283         else
2284                 vlv_enable_pll(new_crtc_state);
2285
2286         intel_encoders_pre_enable(state, crtc);
2287
2288         i9xx_pfit_enable(new_crtc_state);
2289
2290         intel_color_load_luts(new_crtc_state);
2291         intel_color_commit_noarm(new_crtc_state);
2292         intel_color_commit_arm(new_crtc_state);
2293         /* update DSPCNTR to configure gamma for pipe bottom color */
2294         intel_disable_primary_plane(new_crtc_state);
2295
2296         intel_initial_watermarks(state, crtc);
2297         intel_enable_transcoder(new_crtc_state);
2298
2299         intel_crtc_vblank_on(new_crtc_state);
2300
2301         intel_encoders_enable(state, crtc);
2302 }
2303
2304 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2305                              struct intel_crtc *crtc)
2306 {
2307         const struct intel_crtc_state *new_crtc_state =
2308                 intel_atomic_get_new_crtc_state(state, crtc);
2309         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2310         enum pipe pipe = crtc->pipe;
2311
2312         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2313                 return;
2314
2315         i9xx_configure_cpu_transcoder(new_crtc_state);
2316
2317         intel_set_pipe_src_size(new_crtc_state);
2318
2319         crtc->active = true;
2320
2321         if (DISPLAY_VER(dev_priv) != 2)
2322                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2323
2324         intel_encoders_pre_enable(state, crtc);
2325
2326         i9xx_enable_pll(new_crtc_state);
2327
2328         i9xx_pfit_enable(new_crtc_state);
2329
2330         intel_color_load_luts(new_crtc_state);
2331         intel_color_commit_noarm(new_crtc_state);
2332         intel_color_commit_arm(new_crtc_state);
2333         /* update DSPCNTR to configure gamma for pipe bottom color */
2334         intel_disable_primary_plane(new_crtc_state);
2335
2336         if (!intel_initial_watermarks(state, crtc))
2337                 intel_update_watermarks(dev_priv);
2338         intel_enable_transcoder(new_crtc_state);
2339
2340         intel_crtc_vblank_on(new_crtc_state);
2341
2342         intel_encoders_enable(state, crtc);
2343
2344         /* prevents spurious underruns */
2345         if (DISPLAY_VER(dev_priv) == 2)
2346                 intel_crtc_wait_for_next_vblank(crtc);
2347 }
2348
2349 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2350 {
2351         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2352         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2353
2354         if (!old_crtc_state->gmch_pfit.control)
2355                 return;
2356
2357         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2358
2359         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2360                     intel_de_read(dev_priv, PFIT_CONTROL));
2361         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2362 }
2363
2364 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2365                               struct intel_crtc *crtc)
2366 {
2367         struct intel_crtc_state *old_crtc_state =
2368                 intel_atomic_get_old_crtc_state(state, crtc);
2369         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2370         enum pipe pipe = crtc->pipe;
2371
2372         /*
2373          * On gen2 planes are double buffered but the pipe isn't, so we must
2374          * wait for planes to fully turn off before disabling the pipe.
2375          */
2376         if (DISPLAY_VER(dev_priv) == 2)
2377                 intel_crtc_wait_for_next_vblank(crtc);
2378
2379         intel_encoders_disable(state, crtc);
2380
2381         intel_crtc_vblank_off(old_crtc_state);
2382
2383         intel_disable_transcoder(old_crtc_state);
2384
2385         i9xx_pfit_disable(old_crtc_state);
2386
2387         intel_encoders_post_disable(state, crtc);
2388
2389         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2390                 if (IS_CHERRYVIEW(dev_priv))
2391                         chv_disable_pll(dev_priv, pipe);
2392                 else if (IS_VALLEYVIEW(dev_priv))
2393                         vlv_disable_pll(dev_priv, pipe);
2394                 else
2395                         i9xx_disable_pll(old_crtc_state);
2396         }
2397
2398         intel_encoders_post_pll_disable(state, crtc);
2399
2400         if (DISPLAY_VER(dev_priv) != 2)
2401                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2402
2403         if (!dev_priv->display.funcs.wm->initial_watermarks)
2404                 intel_update_watermarks(dev_priv);
2405
2406         /* clock the pipe down to 640x480@60 to potentially save power */
2407         if (IS_I830(dev_priv))
2408                 i830_enable_pipe(dev_priv, pipe);
2409 }
2410
2411
2412 /*
2413  * turn all crtc's off, but do not adjust state
2414  * This has to be paired with a call to intel_modeset_setup_hw_state.
2415  */
2416 int intel_display_suspend(struct drm_device *dev)
2417 {
2418         struct drm_i915_private *dev_priv = to_i915(dev);
2419         struct drm_atomic_state *state;
2420         int ret;
2421
2422         if (!HAS_DISPLAY(dev_priv))
2423                 return 0;
2424
2425         state = drm_atomic_helper_suspend(dev);
2426         ret = PTR_ERR_OR_ZERO(state);
2427         if (ret)
2428                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2429                         ret);
2430         else
2431                 dev_priv->modeset_restore_state = state;
2432         return ret;
2433 }
2434
2435 void intel_encoder_destroy(struct drm_encoder *encoder)
2436 {
2437         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2438
2439         drm_encoder_cleanup(encoder);
2440         kfree(intel_encoder);
2441 }
2442
2443 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2444 {
2445         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2446
2447         /* GDG double wide on either pipe, otherwise pipe A only */
2448         return DISPLAY_VER(dev_priv) < 4 &&
2449                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2450 }
2451
2452 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2453 {
2454         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2455         struct drm_rect src;
2456
2457         /*
2458          * We only use IF-ID interlacing. If we ever use
2459          * PF-ID we'll need to adjust the pixel_rate here.
2460          */
2461
2462         if (!crtc_state->pch_pfit.enabled)
2463                 return pixel_rate;
2464
2465         drm_rect_init(&src, 0, 0,
2466                       drm_rect_width(&crtc_state->pipe_src) << 16,
2467                       drm_rect_height(&crtc_state->pipe_src) << 16);
2468
2469         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2470                                    pixel_rate);
2471 }
2472
2473 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2474                                          const struct drm_display_mode *timings)
2475 {
2476         mode->hdisplay = timings->crtc_hdisplay;
2477         mode->htotal = timings->crtc_htotal;
2478         mode->hsync_start = timings->crtc_hsync_start;
2479         mode->hsync_end = timings->crtc_hsync_end;
2480
2481         mode->vdisplay = timings->crtc_vdisplay;
2482         mode->vtotal = timings->crtc_vtotal;
2483         mode->vsync_start = timings->crtc_vsync_start;
2484         mode->vsync_end = timings->crtc_vsync_end;
2485
2486         mode->flags = timings->flags;
2487         mode->type = DRM_MODE_TYPE_DRIVER;
2488
2489         mode->clock = timings->crtc_clock;
2490
2491         drm_mode_set_name(mode);
2492 }
2493
2494 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2495 {
2496         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2497
2498         if (HAS_GMCH(dev_priv))
2499                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2500                 crtc_state->pixel_rate =
2501                         crtc_state->hw.pipe_mode.crtc_clock;
2502         else
2503                 crtc_state->pixel_rate =
2504                         ilk_pipe_pixel_rate(crtc_state);
2505 }
2506
2507 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2508                                            struct drm_display_mode *mode)
2509 {
2510         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2511
2512         if (num_pipes < 2)
2513                 return;
2514
2515         mode->crtc_clock /= num_pipes;
2516         mode->crtc_hdisplay /= num_pipes;
2517         mode->crtc_hblank_start /= num_pipes;
2518         mode->crtc_hblank_end /= num_pipes;
2519         mode->crtc_hsync_start /= num_pipes;
2520         mode->crtc_hsync_end /= num_pipes;
2521         mode->crtc_htotal /= num_pipes;
2522 }
2523
2524 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2525                                           struct drm_display_mode *mode)
2526 {
2527         int overlap = crtc_state->splitter.pixel_overlap;
2528         int n = crtc_state->splitter.link_count;
2529
2530         if (!crtc_state->splitter.enable)
2531                 return;
2532
2533         /*
2534          * eDP MSO uses segment timings from EDID for transcoder
2535          * timings, but full mode for everything else.
2536          *
2537          * h_full = (h_segment - pixel_overlap) * link_count
2538          */
2539         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2540         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2541         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2542         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2543         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2544         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2545         mode->crtc_clock *= n;
2546 }
2547
2548 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2549 {
2550         struct drm_display_mode *mode = &crtc_state->hw.mode;
2551         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2552         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2553
2554         /*
2555          * Start with the adjusted_mode crtc timings, which
2556          * have been filled with the transcoder timings.
2557          */
2558         drm_mode_copy(pipe_mode, adjusted_mode);
2559
2560         /* Expand MSO per-segment transcoder timings to full */
2561         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2562
2563         /*
2564          * We want the full numbers in adjusted_mode normal timings,
2565          * adjusted_mode crtc timings are left with the raw transcoder
2566          * timings.
2567          */
2568         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2569
2570         /* Populate the "user" mode with full numbers */
2571         drm_mode_copy(mode, pipe_mode);
2572         intel_mode_from_crtc_timings(mode, mode);
2573         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2574                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2575         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2576
2577         /* Derive per-pipe timings in case bigjoiner is used */
2578         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2579         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2580
2581         intel_crtc_compute_pixel_rate(crtc_state);
2582 }
2583
2584 void intel_encoder_get_config(struct intel_encoder *encoder,
2585                               struct intel_crtc_state *crtc_state)
2586 {
2587         encoder->get_config(encoder, crtc_state);
2588
2589         intel_crtc_readout_derived_state(crtc_state);
2590 }
2591
2592 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2593 {
2594         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2595         int width, height;
2596
2597         if (num_pipes < 2)
2598                 return;
2599
2600         width = drm_rect_width(&crtc_state->pipe_src);
2601         height = drm_rect_height(&crtc_state->pipe_src);
2602
2603         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2604                       width / num_pipes, height);
2605 }
2606
2607 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2608 {
2609         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2610         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2611
2612         intel_bigjoiner_compute_pipe_src(crtc_state);
2613
2614         /*
2615          * Pipe horizontal size must be even in:
2616          * - DVO ganged mode
2617          * - LVDS dual channel mode
2618          * - Double wide pipe
2619          */
2620         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2621                 if (crtc_state->double_wide) {
2622                         drm_dbg_kms(&i915->drm,
2623                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2624                                     crtc->base.base.id, crtc->base.name);
2625                         return -EINVAL;
2626                 }
2627
2628                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2629                     intel_is_dual_link_lvds(i915)) {
2630                         drm_dbg_kms(&i915->drm,
2631                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2632                                     crtc->base.base.id, crtc->base.name);
2633                         return -EINVAL;
2634                 }
2635         }
2636
2637         return 0;
2638 }
2639
2640 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2641 {
2642         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2643         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2644         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2645         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2646         int clock_limit = i915->max_dotclk_freq;
2647
2648         /*
2649          * Start with the adjusted_mode crtc timings, which
2650          * have been filled with the transcoder timings.
2651          */
2652         drm_mode_copy(pipe_mode, adjusted_mode);
2653
2654         /* Expand MSO per-segment transcoder timings to full */
2655         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2656
2657         /* Derive per-pipe timings in case bigjoiner is used */
2658         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2659         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2660
2661         if (DISPLAY_VER(i915) < 4) {
2662                 clock_limit = i915->max_cdclk_freq * 9 / 10;
2663
2664                 /*
2665                  * Enable double wide mode when the dot clock
2666                  * is > 90% of the (display) core speed.
2667                  */
2668                 if (intel_crtc_supports_double_wide(crtc) &&
2669                     pipe_mode->crtc_clock > clock_limit) {
2670                         clock_limit = i915->max_dotclk_freq;
2671                         crtc_state->double_wide = true;
2672                 }
2673         }
2674
2675         if (pipe_mode->crtc_clock > clock_limit) {
2676                 drm_dbg_kms(&i915->drm,
2677                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2678                             crtc->base.base.id, crtc->base.name,
2679                             pipe_mode->crtc_clock, clock_limit,
2680                             str_yes_no(crtc_state->double_wide));
2681                 return -EINVAL;
2682         }
2683
2684         return 0;
2685 }
2686
2687 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2688                                      struct intel_crtc *crtc)
2689 {
2690         struct intel_crtc_state *crtc_state =
2691                 intel_atomic_get_new_crtc_state(state, crtc);
2692         int ret;
2693
2694         ret = intel_crtc_compute_pipe_src(crtc_state);
2695         if (ret)
2696                 return ret;
2697
2698         ret = intel_crtc_compute_pipe_mode(crtc_state);
2699         if (ret)
2700                 return ret;
2701
2702         intel_crtc_compute_pixel_rate(crtc_state);
2703
2704         if (crtc_state->has_pch_encoder)
2705                 return ilk_fdi_compute_config(crtc, crtc_state);
2706
2707         return 0;
2708 }
2709
2710 static void
2711 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2712 {
2713         while (*num > DATA_LINK_M_N_MASK ||
2714                *den > DATA_LINK_M_N_MASK) {
2715                 *num >>= 1;
2716                 *den >>= 1;
2717         }
2718 }
2719
2720 static void compute_m_n(unsigned int m, unsigned int n,
2721                         u32 *ret_m, u32 *ret_n,
2722                         bool constant_n)
2723 {
2724         /*
2725          * Several DP dongles in particular seem to be fussy about
2726          * too large link M/N values. Give N value as 0x8000 that
2727          * should be acceptable by specific devices. 0x8000 is the
2728          * specified fixed N value for asynchronous clock mode,
2729          * which the devices expect also in synchronous clock mode.
2730          */
2731         if (constant_n)
2732                 *ret_n = DP_LINK_CONSTANT_N_VALUE;
2733         else
2734                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2735
2736         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2737         intel_reduce_m_n_ratio(ret_m, ret_n);
2738 }
2739
2740 void
2741 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2742                        int pixel_clock, int link_clock,
2743                        struct intel_link_m_n *m_n,
2744                        bool constant_n, bool fec_enable)
2745 {
2746         u32 data_clock = bits_per_pixel * pixel_clock;
2747
2748         if (fec_enable)
2749                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2750
2751         m_n->tu = 64;
2752         compute_m_n(data_clock,
2753                     link_clock * nlanes * 8,
2754                     &m_n->data_m, &m_n->data_n,
2755                     constant_n);
2756
2757         compute_m_n(pixel_clock, link_clock,
2758                     &m_n->link_m, &m_n->link_n,
2759                     constant_n);
2760 }
2761
2762 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2763 {
2764         /*
2765          * There may be no VBT; and if the BIOS enabled SSC we can
2766          * just keep using it to avoid unnecessary flicker.  Whereas if the
2767          * BIOS isn't using it, don't assume it will work even if the VBT
2768          * indicates as much.
2769          */
2770         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2771                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2772                                                        PCH_DREF_CONTROL) &
2773                         DREF_SSC1_ENABLE;
2774
2775                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2776                         drm_dbg_kms(&dev_priv->drm,
2777                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2778                                     str_enabled_disabled(bios_lvds_use_ssc),
2779                                     str_enabled_disabled(dev_priv->vbt.lvds_use_ssc));
2780                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2781                 }
2782         }
2783 }
2784
2785 void intel_zero_m_n(struct intel_link_m_n *m_n)
2786 {
2787         /* corresponds to 0 register value */
2788         memset(m_n, 0, sizeof(*m_n));
2789         m_n->tu = 1;
2790 }
2791
2792 void intel_set_m_n(struct drm_i915_private *i915,
2793                    const struct intel_link_m_n *m_n,
2794                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2795                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2796 {
2797         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2798         intel_de_write(i915, data_n_reg, m_n->data_n);
2799         intel_de_write(i915, link_m_reg, m_n->link_m);
2800         /*
2801          * On BDW+ writing LINK_N arms the double buffered update
2802          * of all the M/N registers, so it must be written last.
2803          */
2804         intel_de_write(i915, link_n_reg, m_n->link_n);
2805 }
2806
2807 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2808                                     enum transcoder transcoder)
2809 {
2810         if (IS_HASWELL(dev_priv))
2811                 return transcoder == TRANSCODER_EDP;
2812
2813         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2814 }
2815
2816 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2817                                     enum transcoder transcoder,
2818                                     const struct intel_link_m_n *m_n)
2819 {
2820         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2821         enum pipe pipe = crtc->pipe;
2822
2823         if (DISPLAY_VER(dev_priv) >= 5)
2824                 intel_set_m_n(dev_priv, m_n,
2825                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2826                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2827         else
2828                 intel_set_m_n(dev_priv, m_n,
2829                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2830                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2831 }
2832
2833 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2834                                     enum transcoder transcoder,
2835                                     const struct intel_link_m_n *m_n)
2836 {
2837         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2838
2839         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2840                 return;
2841
2842         intel_set_m_n(dev_priv, m_n,
2843                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2844                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2845 }
2846
2847 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2848 {
2849         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2850         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2851         enum pipe pipe = crtc->pipe;
2852         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2853         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2854         u32 crtc_vtotal, crtc_vblank_end;
2855         int vsyncshift = 0;
2856
2857         /* We need to be careful not to changed the adjusted mode, for otherwise
2858          * the hw state checker will get angry at the mismatch. */
2859         crtc_vtotal = adjusted_mode->crtc_vtotal;
2860         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2861
2862         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2863                 /* the chip adds 2 halflines automatically */
2864                 crtc_vtotal -= 1;
2865                 crtc_vblank_end -= 1;
2866
2867                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2868                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2869                 else
2870                         vsyncshift = adjusted_mode->crtc_hsync_start -
2871                                 adjusted_mode->crtc_htotal / 2;
2872                 if (vsyncshift < 0)
2873                         vsyncshift += adjusted_mode->crtc_htotal;
2874         }
2875
2876         if (DISPLAY_VER(dev_priv) > 3)
2877                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
2878                                vsyncshift);
2879
2880         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
2881                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
2882         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
2883                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
2884         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
2885                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
2886
2887         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
2888                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
2889         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
2890                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
2891         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
2892                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
2893
2894         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2895          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2896          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2897          * bits. */
2898         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2899             (pipe == PIPE_B || pipe == PIPE_C))
2900                 intel_de_write(dev_priv, VTOTAL(pipe),
2901                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2902
2903 }
2904
2905 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2906 {
2907         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2908         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2909         int width = drm_rect_width(&crtc_state->pipe_src);
2910         int height = drm_rect_height(&crtc_state->pipe_src);
2911         enum pipe pipe = crtc->pipe;
2912
2913         /* pipesrc controls the size that is scaled from, which should
2914          * always be the user's requested size.
2915          */
2916         intel_de_write(dev_priv, PIPESRC(pipe),
2917                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2918 }
2919
2920 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2921 {
2922         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2923         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2924
2925         if (DISPLAY_VER(dev_priv) == 2)
2926                 return false;
2927
2928         if (DISPLAY_VER(dev_priv) >= 9 ||
2929             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2930                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
2931         else
2932                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
2933 }
2934
2935 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2936                                          struct intel_crtc_state *pipe_config)
2937 {
2938         struct drm_device *dev = crtc->base.dev;
2939         struct drm_i915_private *dev_priv = to_i915(dev);
2940         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2941         u32 tmp;
2942
2943         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
2944         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
2945         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
2946
2947         if (!transcoder_is_dsi(cpu_transcoder)) {
2948                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
2949                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
2950                                                         (tmp & 0xffff) + 1;
2951                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
2952                                                 ((tmp >> 16) & 0xffff) + 1;
2953         }
2954         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
2955         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
2956         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
2957
2958         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
2959         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
2960         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
2961
2962         if (!transcoder_is_dsi(cpu_transcoder)) {
2963                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
2964                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
2965                                                         (tmp & 0xffff) + 1;
2966                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
2967                                                 ((tmp >> 16) & 0xffff) + 1;
2968         }
2969         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
2970         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
2971         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
2972
2973         if (intel_pipe_is_interlaced(pipe_config)) {
2974                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
2975                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
2976                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
2977         }
2978 }
2979
2980 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2981 {
2982         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2983         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2984         enum pipe master_pipe, pipe = crtc->pipe;
2985         int width;
2986
2987         if (num_pipes < 2)
2988                 return;
2989
2990         master_pipe = bigjoiner_master_pipe(crtc_state);
2991         width = drm_rect_width(&crtc_state->pipe_src);
2992
2993         drm_rect_translate_to(&crtc_state->pipe_src,
2994                               (pipe - master_pipe) * width, 0);
2995 }
2996
2997 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2998                                     struct intel_crtc_state *pipe_config)
2999 {
3000         struct drm_device *dev = crtc->base.dev;
3001         struct drm_i915_private *dev_priv = to_i915(dev);
3002         u32 tmp;
3003
3004         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
3005
3006         drm_rect_init(&pipe_config->pipe_src, 0, 0,
3007                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
3008                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
3009
3010         intel_bigjoiner_adjust_pipe_src(pipe_config);
3011 }
3012
3013 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3014 {
3015         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3016         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3017         u32 pipeconf = 0;
3018
3019         /*
3020          * - We keep both pipes enabled on 830
3021          * - During modeset the pipe is still disabled and must remain so
3022          * - During fastset the pipe is already enabled and must remain so
3023          */
3024         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
3025                 pipeconf |= PIPECONF_ENABLE;
3026
3027         if (crtc_state->double_wide)
3028                 pipeconf |= PIPECONF_DOUBLE_WIDE;
3029
3030         /* only g4x and later have fancy bpc/dither controls */
3031         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3032             IS_CHERRYVIEW(dev_priv)) {
3033                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
3034                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
3035                         pipeconf |= PIPECONF_DITHER_EN |
3036                                     PIPECONF_DITHER_TYPE_SP;
3037
3038                 switch (crtc_state->pipe_bpp) {
3039                 default:
3040                         /* Case prevented by intel_choose_pipe_bpp_dither. */
3041                         MISSING_CASE(crtc_state->pipe_bpp);
3042                         fallthrough;
3043                 case 18:
3044                         pipeconf |= PIPECONF_BPC_6;
3045                         break;
3046                 case 24:
3047                         pipeconf |= PIPECONF_BPC_8;
3048                         break;
3049                 case 30:
3050                         pipeconf |= PIPECONF_BPC_10;
3051                         break;
3052                 }
3053         }
3054
3055         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3056                 if (DISPLAY_VER(dev_priv) < 4 ||
3057                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3058                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3059                 else
3060                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
3061         } else {
3062                 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
3063         }
3064
3065         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3066              crtc_state->limited_color_range)
3067                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
3068
3069         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3070
3071         pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3072
3073         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
3074         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
3075 }
3076
3077 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
3078 {
3079         if (IS_I830(dev_priv))
3080                 return false;
3081
3082         return DISPLAY_VER(dev_priv) >= 4 ||
3083                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
3084 }
3085
3086 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
3087 {
3088         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3089         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3090         u32 tmp;
3091
3092         if (!i9xx_has_pfit(dev_priv))
3093                 return;
3094
3095         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
3096         if (!(tmp & PFIT_ENABLE))
3097                 return;
3098
3099         /* Check whether the pfit is attached to our pipe. */
3100         if (DISPLAY_VER(dev_priv) < 4) {
3101                 if (crtc->pipe != PIPE_B)
3102                         return;
3103         } else {
3104                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
3105                         return;
3106         }
3107
3108         crtc_state->gmch_pfit.control = tmp;
3109         crtc_state->gmch_pfit.pgm_ratios =
3110                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
3111 }
3112
3113 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
3114                                struct intel_crtc_state *pipe_config)
3115 {
3116         struct drm_device *dev = crtc->base.dev;
3117         struct drm_i915_private *dev_priv = to_i915(dev);
3118         enum pipe pipe = crtc->pipe;
3119         struct dpll clock;
3120         u32 mdiv;
3121         int refclk = 100000;
3122
3123         /* In case of DSI, DPLL will not be used */
3124         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3125                 return;
3126
3127         vlv_dpio_get(dev_priv);
3128         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
3129         vlv_dpio_put(dev_priv);
3130
3131         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
3132         clock.m2 = mdiv & DPIO_M2DIV_MASK;
3133         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
3134         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
3135         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
3136
3137         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
3138 }
3139
3140 static void chv_crtc_clock_get(struct intel_crtc *crtc,
3141                                struct intel_crtc_state *pipe_config)
3142 {
3143         struct drm_device *dev = crtc->base.dev;
3144         struct drm_i915_private *dev_priv = to_i915(dev);
3145         enum pipe pipe = crtc->pipe;
3146         enum dpio_channel port = vlv_pipe_to_channel(pipe);
3147         struct dpll clock;
3148         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
3149         int refclk = 100000;
3150
3151         /* In case of DSI, DPLL will not be used */
3152         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3153                 return;
3154
3155         vlv_dpio_get(dev_priv);
3156         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
3157         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
3158         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
3159         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
3160         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
3161         vlv_dpio_put(dev_priv);
3162
3163         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
3164         clock.m2 = (pll_dw0 & 0xff) << 22;
3165         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
3166                 clock.m2 |= pll_dw2 & 0x3fffff;
3167         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
3168         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
3169         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
3170
3171         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
3172 }
3173
3174 static enum intel_output_format
3175 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
3176 {
3177         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3178         u32 tmp;
3179
3180         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3181
3182         if (tmp & PIPEMISC_YUV420_ENABLE) {
3183                 /* We support 4:2:0 in full blend mode only */
3184                 drm_WARN_ON(&dev_priv->drm,
3185                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
3186
3187                 return INTEL_OUTPUT_FORMAT_YCBCR420;
3188         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
3189                 return INTEL_OUTPUT_FORMAT_YCBCR444;
3190         } else {
3191                 return INTEL_OUTPUT_FORMAT_RGB;
3192         }
3193 }
3194
3195 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
3196 {
3197         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3198         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3199         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3200         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3201         u32 tmp;
3202
3203         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
3204
3205         if (tmp & DISP_PIPE_GAMMA_ENABLE)
3206                 crtc_state->gamma_enable = true;
3207
3208         if (!HAS_GMCH(dev_priv) &&
3209             tmp & DISP_PIPE_CSC_ENABLE)
3210                 crtc_state->csc_enable = true;
3211 }
3212
3213 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3214                                  struct intel_crtc_state *pipe_config)
3215 {
3216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3217         enum intel_display_power_domain power_domain;
3218         intel_wakeref_t wakeref;
3219         u32 tmp;
3220         bool ret;
3221
3222         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3223         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3224         if (!wakeref)
3225                 return false;
3226
3227         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3228         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3229         pipe_config->shared_dpll = NULL;
3230
3231         ret = false;
3232
3233         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3234         if (!(tmp & PIPECONF_ENABLE))
3235                 goto out;
3236
3237         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3238             IS_CHERRYVIEW(dev_priv)) {
3239                 switch (tmp & PIPECONF_BPC_MASK) {
3240                 case PIPECONF_BPC_6:
3241                         pipe_config->pipe_bpp = 18;
3242                         break;
3243                 case PIPECONF_BPC_8:
3244                         pipe_config->pipe_bpp = 24;
3245                         break;
3246                 case PIPECONF_BPC_10:
3247                         pipe_config->pipe_bpp = 30;
3248                         break;
3249                 default:
3250                         MISSING_CASE(tmp);
3251                         break;
3252                 }
3253         }
3254
3255         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3256             (tmp & PIPECONF_COLOR_RANGE_SELECT))
3257                 pipe_config->limited_color_range = true;
3258
3259         pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
3260
3261         pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3262
3263         if (IS_CHERRYVIEW(dev_priv))
3264                 pipe_config->cgm_mode = intel_de_read(dev_priv,
3265                                                       CGM_PIPE_MODE(crtc->pipe));
3266
3267         i9xx_get_pipe_color_config(pipe_config);
3268         intel_color_get_config(pipe_config);
3269
3270         if (DISPLAY_VER(dev_priv) < 4)
3271                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
3272
3273         intel_get_transcoder_timings(crtc, pipe_config);
3274         intel_get_pipe_src_size(crtc, pipe_config);
3275
3276         i9xx_get_pfit_config(pipe_config);
3277
3278         if (DISPLAY_VER(dev_priv) >= 4) {
3279                 /* No way to read it out on pipes B and C */
3280                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3281                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
3282                 else
3283                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3284                 pipe_config->pixel_multiplier =
3285                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3286                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3287                 pipe_config->dpll_hw_state.dpll_md = tmp;
3288         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3289                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3290                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3291                 pipe_config->pixel_multiplier =
3292                         ((tmp & SDVO_MULTIPLIER_MASK)
3293                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3294         } else {
3295                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3296                  * port and will be fixed up in the encoder->get_config
3297                  * function. */
3298                 pipe_config->pixel_multiplier = 1;
3299         }
3300         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3301                                                         DPLL(crtc->pipe));
3302         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3303                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3304                                                                FP0(crtc->pipe));
3305                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3306                                                                FP1(crtc->pipe));
3307         } else {
3308                 /* Mask out read-only status bits. */
3309                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3310                                                      DPLL_PORTC_READY_MASK |
3311                                                      DPLL_PORTB_READY_MASK);
3312         }
3313
3314         if (IS_CHERRYVIEW(dev_priv))
3315                 chv_crtc_clock_get(crtc, pipe_config);
3316         else if (IS_VALLEYVIEW(dev_priv))
3317                 vlv_crtc_clock_get(crtc, pipe_config);
3318         else
3319                 i9xx_crtc_clock_get(crtc, pipe_config);
3320
3321         /*
3322          * Normally the dotclock is filled in by the encoder .get_config()
3323          * but in case the pipe is enabled w/o any ports we need a sane
3324          * default.
3325          */
3326         pipe_config->hw.adjusted_mode.crtc_clock =
3327                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3328
3329         ret = true;
3330
3331 out:
3332         intel_display_power_put(dev_priv, power_domain, wakeref);
3333
3334         return ret;
3335 }
3336
3337 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3338 {
3339         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3340         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3341         enum pipe pipe = crtc->pipe;
3342         u32 val = 0;
3343
3344         /*
3345          * - During modeset the pipe is still disabled and must remain so
3346          * - During fastset the pipe is already enabled and must remain so
3347          */
3348         if (!intel_crtc_needs_modeset(crtc_state))
3349                 val |= PIPECONF_ENABLE;
3350
3351         switch (crtc_state->pipe_bpp) {
3352         default:
3353                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3354                 MISSING_CASE(crtc_state->pipe_bpp);
3355                 fallthrough;
3356         case 18:
3357                 val |= PIPECONF_BPC_6;
3358                 break;
3359         case 24:
3360                 val |= PIPECONF_BPC_8;
3361                 break;
3362         case 30:
3363                 val |= PIPECONF_BPC_10;
3364                 break;
3365         case 36:
3366                 val |= PIPECONF_BPC_12;
3367                 break;
3368         }
3369
3370         if (crtc_state->dither)
3371                 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3372
3373         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3374                 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3375         else
3376                 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3377
3378         /*
3379          * This would end up with an odd purple hue over
3380          * the entire display. Make sure we don't do it.
3381          */
3382         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3383                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3384
3385         if (crtc_state->limited_color_range &&
3386             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3387                 val |= PIPECONF_COLOR_RANGE_SELECT;
3388
3389         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3390                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
3391
3392         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3393
3394         val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3395         val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3396
3397         intel_de_write(dev_priv, PIPECONF(pipe), val);
3398         intel_de_posting_read(dev_priv, PIPECONF(pipe));
3399 }
3400
3401 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3402 {
3403         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3405         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3406         u32 val = 0;
3407
3408         /*
3409          * - During modeset the pipe is still disabled and must remain so
3410          * - During fastset the pipe is already enabled and must remain so
3411          */
3412         if (!intel_crtc_needs_modeset(crtc_state))
3413                 val |= PIPECONF_ENABLE;
3414
3415         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3416                 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3417
3418         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3419                 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3420         else
3421                 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3422
3423         if (IS_HASWELL(dev_priv) &&
3424             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3425                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
3426
3427         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
3428         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
3429 }
3430
3431 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
3432 {
3433         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3434         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3435         u32 val = 0;
3436
3437         switch (crtc_state->pipe_bpp) {
3438         case 18:
3439                 val |= PIPEMISC_BPC_6;
3440                 break;
3441         case 24:
3442                 val |= PIPEMISC_BPC_8;
3443                 break;
3444         case 30:
3445                 val |= PIPEMISC_BPC_10;
3446                 break;
3447         case 36:
3448                 /* Port output 12BPC defined for ADLP+ */
3449                 if (DISPLAY_VER(dev_priv) > 12)
3450                         val |= PIPEMISC_BPC_12_ADLP;
3451                 break;
3452         default:
3453                 MISSING_CASE(crtc_state->pipe_bpp);
3454                 break;
3455         }
3456
3457         if (crtc_state->dither)
3458                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
3459
3460         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3461             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3462                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
3463
3464         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3465                 val |= PIPEMISC_YUV420_ENABLE |
3466                         PIPEMISC_YUV420_MODE_FULL_BLEND;
3467
3468         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3469                 val |= PIPEMISC_HDR_MODE_PRECISION;
3470
3471         if (DISPLAY_VER(dev_priv) >= 12)
3472                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
3473
3474         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
3475 }
3476
3477 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
3478 {
3479         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3480         u32 tmp;
3481
3482         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3483
3484         switch (tmp & PIPEMISC_BPC_MASK) {
3485         case PIPEMISC_BPC_6:
3486                 return 18;
3487         case PIPEMISC_BPC_8:
3488                 return 24;
3489         case PIPEMISC_BPC_10:
3490                 return 30;
3491         /*
3492          * PORT OUTPUT 12 BPC defined for ADLP+.
3493          *
3494          * TODO:
3495          * For previous platforms with DSI interface, bits 5:7
3496          * are used for storing pipe_bpp irrespective of dithering.
3497          * Since the value of 12 BPC is not defined for these bits
3498          * on older platforms, need to find a workaround for 12 BPC
3499          * MIPI DSI HW readout.
3500          */
3501         case PIPEMISC_BPC_12_ADLP:
3502                 if (DISPLAY_VER(dev_priv) > 12)
3503                         return 36;
3504                 fallthrough;
3505         default:
3506                 MISSING_CASE(tmp);
3507                 return 0;
3508         }
3509 }
3510
3511 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3512 {
3513         /*
3514          * Account for spread spectrum to avoid
3515          * oversubscribing the link. Max center spread
3516          * is 2.5%; use 5% for safety's sake.
3517          */
3518         u32 bps = target_clock * bpp * 21 / 20;
3519         return DIV_ROUND_UP(bps, link_bw * 8);
3520 }
3521
3522 void intel_get_m_n(struct drm_i915_private *i915,
3523                    struct intel_link_m_n *m_n,
3524                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3525                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3526 {
3527         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3528         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3529         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3530         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3531         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3532 }
3533
3534 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3535                                     enum transcoder transcoder,
3536                                     struct intel_link_m_n *m_n)
3537 {
3538         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3539         enum pipe pipe = crtc->pipe;
3540
3541         if (DISPLAY_VER(dev_priv) >= 5)
3542                 intel_get_m_n(dev_priv, m_n,
3543                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3544                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3545         else
3546                 intel_get_m_n(dev_priv, m_n,
3547                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3548                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3549 }
3550
3551 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3552                                     enum transcoder transcoder,
3553                                     struct intel_link_m_n *m_n)
3554 {
3555         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3556
3557         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3558                 return;
3559
3560         intel_get_m_n(dev_priv, m_n,
3561                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3562                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3563 }
3564
3565 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
3566                                   u32 pos, u32 size)
3567 {
3568         drm_rect_init(&crtc_state->pch_pfit.dst,
3569                       pos >> 16, pos & 0xffff,
3570                       size >> 16, size & 0xffff);
3571 }
3572
3573 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
3574 {
3575         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3576         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3577         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
3578         int id = -1;
3579         int i;
3580
3581         /* find scaler attached to this pipe */
3582         for (i = 0; i < crtc->num_scalers; i++) {
3583                 u32 ctl, pos, size;
3584
3585                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
3586                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
3587                         continue;
3588
3589                 id = i;
3590                 crtc_state->pch_pfit.enabled = true;
3591
3592                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
3593                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
3594
3595                 ilk_get_pfit_pos_size(crtc_state, pos, size);
3596
3597                 scaler_state->scalers[i].in_use = true;
3598                 break;
3599         }
3600
3601         scaler_state->scaler_id = id;
3602         if (id >= 0)
3603                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
3604         else
3605                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
3606 }
3607
3608 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3609 {
3610         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3611         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3612         u32 ctl, pos, size;
3613
3614         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3615         if ((ctl & PF_ENABLE) == 0)
3616                 return;
3617
3618         crtc_state->pch_pfit.enabled = true;
3619
3620         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3621         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3622
3623         ilk_get_pfit_pos_size(crtc_state, pos, size);
3624
3625         /*
3626          * We currently do not free assignements of panel fitters on
3627          * ivb/hsw (since we don't use the higher upscaling modes which
3628          * differentiates them) so just WARN about this case for now.
3629          */
3630         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
3631                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
3632 }
3633
3634 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3635                                 struct intel_crtc_state *pipe_config)
3636 {
3637         struct drm_device *dev = crtc->base.dev;
3638         struct drm_i915_private *dev_priv = to_i915(dev);
3639         enum intel_display_power_domain power_domain;
3640         intel_wakeref_t wakeref;
3641         u32 tmp;
3642         bool ret;
3643
3644         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3645         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3646         if (!wakeref)
3647                 return false;
3648
3649         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3650         pipe_config->shared_dpll = NULL;
3651
3652         ret = false;
3653         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3654         if (!(tmp & PIPECONF_ENABLE))
3655                 goto out;
3656
3657         switch (tmp & PIPECONF_BPC_MASK) {
3658         case PIPECONF_BPC_6:
3659                 pipe_config->pipe_bpp = 18;
3660                 break;
3661         case PIPECONF_BPC_8:
3662                 pipe_config->pipe_bpp = 24;
3663                 break;
3664         case PIPECONF_BPC_10:
3665                 pipe_config->pipe_bpp = 30;
3666                 break;
3667         case PIPECONF_BPC_12:
3668                 pipe_config->pipe_bpp = 36;
3669                 break;
3670         default:
3671                 break;
3672         }
3673
3674         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
3675                 pipe_config->limited_color_range = true;
3676
3677         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
3678         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
3679         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
3680                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3681                 break;
3682         default:
3683                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3684                 break;
3685         }
3686
3687         pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
3688
3689         pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3690
3691         pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
3692
3693         pipe_config->csc_mode = intel_de_read(dev_priv,
3694                                               PIPE_CSC_MODE(crtc->pipe));
3695
3696         i9xx_get_pipe_color_config(pipe_config);
3697         intel_color_get_config(pipe_config);
3698
3699         pipe_config->pixel_multiplier = 1;
3700
3701         ilk_pch_get_config(pipe_config);
3702
3703         intel_get_transcoder_timings(crtc, pipe_config);
3704         intel_get_pipe_src_size(crtc, pipe_config);
3705
3706         ilk_get_pfit_config(pipe_config);
3707
3708         ret = true;
3709
3710 out:
3711         intel_display_power_put(dev_priv, power_domain, wakeref);
3712
3713         return ret;
3714 }
3715
3716 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3717 {
3718         if (DISPLAY_VER(i915) >= 12)
3719                 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3720         else if (DISPLAY_VER(i915) >= 11)
3721                 return BIT(PIPE_B) | BIT(PIPE_C);
3722         else
3723                 return 0;
3724 }
3725
3726 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3727                                            enum transcoder cpu_transcoder)
3728 {
3729         enum intel_display_power_domain power_domain;
3730         intel_wakeref_t wakeref;
3731         u32 tmp = 0;
3732
3733         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3734
3735         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3736                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3737
3738         return tmp & TRANS_DDI_FUNC_ENABLE;
3739 }
3740
3741 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3742                                     u8 *master_pipes, u8 *slave_pipes)
3743 {
3744         struct intel_crtc *crtc;
3745
3746         *master_pipes = 0;
3747         *slave_pipes = 0;
3748
3749         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3750                                          bigjoiner_pipes(dev_priv)) {
3751                 enum intel_display_power_domain power_domain;
3752                 enum pipe pipe = crtc->pipe;
3753                 intel_wakeref_t wakeref;
3754
3755                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3756                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3757                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3758
3759                         if (!(tmp & BIG_JOINER_ENABLE))
3760                                 continue;
3761
3762                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3763                                 *master_pipes |= BIT(pipe);
3764                         else
3765                                 *slave_pipes |= BIT(pipe);
3766                 }
3767
3768                 if (DISPLAY_VER(dev_priv) < 13)
3769                         continue;
3770
3771                 power_domain = POWER_DOMAIN_PIPE(pipe);
3772                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3773                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3774
3775                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3776                                 *master_pipes |= BIT(pipe);
3777                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3778                                 *slave_pipes |= BIT(pipe);
3779                 }
3780         }
3781
3782         /* Bigjoiner pipes should always be consecutive master and slave */
3783         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3784                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3785                  *master_pipes, *slave_pipes);
3786 }
3787
3788 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3789 {
3790         if ((slave_pipes & BIT(pipe)) == 0)
3791                 return pipe;
3792
3793         /* ignore everything above our pipe */
3794         master_pipes &= ~GENMASK(7, pipe);
3795
3796         /* highest remaining bit should be our master pipe */
3797         return fls(master_pipes) - 1;
3798 }
3799
3800 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3801 {
3802         enum pipe master_pipe, next_master_pipe;
3803
3804         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3805
3806         if ((master_pipes & BIT(master_pipe)) == 0)
3807                 return 0;
3808
3809         /* ignore our master pipe and everything below it */
3810         master_pipes &= ~GENMASK(master_pipe, 0);
3811         /* make sure a high bit is set for the ffs() */
3812         master_pipes |= BIT(7);
3813         /* lowest remaining bit should be the next master pipe */
3814         next_master_pipe = ffs(master_pipes) - 1;
3815
3816         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3817 }
3818
3819 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3820 {
3821         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3822
3823         if (DISPLAY_VER(i915) >= 11)
3824                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3825
3826         return panel_transcoder_mask;
3827 }
3828
3829 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3830 {
3831         struct drm_device *dev = crtc->base.dev;
3832         struct drm_i915_private *dev_priv = to_i915(dev);
3833         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3834         enum transcoder cpu_transcoder;
3835         u8 master_pipes, slave_pipes;
3836         u8 enabled_transcoders = 0;
3837
3838         /*
3839          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3840          * consistency and less surprising code; it's in always on power).
3841          */
3842         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3843                                        panel_transcoder_mask) {
3844                 enum intel_display_power_domain power_domain;
3845                 intel_wakeref_t wakeref;
3846                 enum pipe trans_pipe;
3847                 u32 tmp = 0;
3848
3849                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3850                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3851                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3852
3853                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3854                         continue;
3855
3856                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3857                 default:
3858                         drm_WARN(dev, 1,
3859                                  "unknown pipe linked to transcoder %s\n",
3860                                  transcoder_name(cpu_transcoder));
3861                         fallthrough;
3862                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3863                 case TRANS_DDI_EDP_INPUT_A_ON:
3864                         trans_pipe = PIPE_A;
3865                         break;
3866                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3867                         trans_pipe = PIPE_B;
3868                         break;
3869                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3870                         trans_pipe = PIPE_C;
3871                         break;
3872                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3873                         trans_pipe = PIPE_D;
3874                         break;
3875                 }
3876
3877                 if (trans_pipe == crtc->pipe)
3878                         enabled_transcoders |= BIT(cpu_transcoder);
3879         }
3880
3881         /* single pipe or bigjoiner master */
3882         cpu_transcoder = (enum transcoder) crtc->pipe;
3883         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3884                 enabled_transcoders |= BIT(cpu_transcoder);
3885
3886         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3887         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3888         if (slave_pipes & BIT(crtc->pipe)) {
3889                 cpu_transcoder = (enum transcoder)
3890                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3891                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3892                         enabled_transcoders |= BIT(cpu_transcoder);
3893         }
3894
3895         return enabled_transcoders;
3896 }
3897
3898 static bool has_edp_transcoders(u8 enabled_transcoders)
3899 {
3900         return enabled_transcoders & BIT(TRANSCODER_EDP);
3901 }
3902
3903 static bool has_dsi_transcoders(u8 enabled_transcoders)
3904 {
3905         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3906                                       BIT(TRANSCODER_DSI_1));
3907 }
3908
3909 static bool has_pipe_transcoders(u8 enabled_transcoders)
3910 {
3911         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3912                                        BIT(TRANSCODER_DSI_0) |
3913                                        BIT(TRANSCODER_DSI_1));
3914 }
3915
3916 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3917                                        u8 enabled_transcoders)
3918 {
3919         /* Only one type of transcoder please */
3920         drm_WARN_ON(&i915->drm,
3921                     has_edp_transcoders(enabled_transcoders) +
3922                     has_dsi_transcoders(enabled_transcoders) +
3923                     has_pipe_transcoders(enabled_transcoders) > 1);
3924
3925         /* Only DSI transcoders can be ganged */
3926         drm_WARN_ON(&i915->drm,
3927                     !has_dsi_transcoders(enabled_transcoders) &&
3928                     !is_power_of_2(enabled_transcoders));
3929 }
3930
3931 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3932                                      struct intel_crtc_state *pipe_config,
3933                                      struct intel_display_power_domain_set *power_domain_set)
3934 {
3935         struct drm_device *dev = crtc->base.dev;
3936         struct drm_i915_private *dev_priv = to_i915(dev);
3937         unsigned long enabled_transcoders;
3938         u32 tmp;
3939
3940         enabled_transcoders = hsw_enabled_transcoders(crtc);
3941         if (!enabled_transcoders)
3942                 return false;
3943
3944         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3945
3946         /*
3947          * With the exception of DSI we should only ever have
3948          * a single enabled transcoder. With DSI let's just
3949          * pick the first one.
3950          */
3951         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3952
3953         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3954                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3955                 return false;
3956
3957         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3958                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3959
3960                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3961                         pipe_config->pch_pfit.force_thru = true;
3962         }
3963
3964         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
3965
3966         return tmp & PIPECONF_ENABLE;
3967 }
3968
3969 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3970                                          struct intel_crtc_state *pipe_config,
3971                                          struct intel_display_power_domain_set *power_domain_set)
3972 {
3973         struct drm_device *dev = crtc->base.dev;
3974         struct drm_i915_private *dev_priv = to_i915(dev);
3975         enum transcoder cpu_transcoder;
3976         enum port port;
3977         u32 tmp;
3978
3979         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3980                 if (port == PORT_A)
3981                         cpu_transcoder = TRANSCODER_DSI_A;
3982                 else
3983                         cpu_transcoder = TRANSCODER_DSI_C;
3984
3985                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3986                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3987                         continue;
3988
3989                 /*
3990                  * The PLL needs to be enabled with a valid divider
3991                  * configuration, otherwise accessing DSI registers will hang
3992                  * the machine. See BSpec North Display Engine
3993                  * registers/MIPI[BXT]. We can break out here early, since we
3994                  * need the same DSI PLL to be enabled for both DSI ports.
3995                  */
3996                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3997                         break;
3998
3999                 /* XXX: this works for video mode only */
4000                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
4001                 if (!(tmp & DPI_ENABLE))
4002                         continue;
4003
4004                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
4005                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
4006                         continue;
4007
4008                 pipe_config->cpu_transcoder = cpu_transcoder;
4009                 break;
4010         }
4011
4012         return transcoder_is_dsi(pipe_config->cpu_transcoder);
4013 }
4014
4015 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
4016 {
4017         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4018         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4019         u8 master_pipes, slave_pipes;
4020         enum pipe pipe = crtc->pipe;
4021
4022         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
4023
4024         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
4025                 return;
4026
4027         crtc_state->bigjoiner_pipes =
4028                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
4029                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
4030 }
4031
4032 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
4033                                 struct intel_crtc_state *pipe_config)
4034 {
4035         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4036         struct intel_display_power_domain_set power_domain_set = { };
4037         bool active;
4038         u32 tmp;
4039
4040         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4041                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
4042                 return false;
4043
4044         pipe_config->shared_dpll = NULL;
4045
4046         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
4047
4048         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4049             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
4050                 drm_WARN_ON(&dev_priv->drm, active);
4051                 active = true;
4052         }
4053
4054         if (!active)
4055                 goto out;
4056
4057         intel_dsc_get_config(pipe_config);
4058         intel_bigjoiner_get_config(pipe_config);
4059
4060         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
4061             DISPLAY_VER(dev_priv) >= 11)
4062                 intel_get_transcoder_timings(crtc, pipe_config);
4063
4064         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
4065                 intel_vrr_get_config(crtc, pipe_config);
4066
4067         intel_get_pipe_src_size(crtc, pipe_config);
4068
4069         if (IS_HASWELL(dev_priv)) {
4070                 u32 tmp = intel_de_read(dev_priv,
4071                                         PIPECONF(pipe_config->cpu_transcoder));
4072
4073                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
4074                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
4075                 else
4076                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
4077         } else {
4078                 pipe_config->output_format =
4079                         bdw_get_pipemisc_output_format(crtc);
4080         }
4081
4082         pipe_config->gamma_mode = intel_de_read(dev_priv,
4083                                                 GAMMA_MODE(crtc->pipe));
4084
4085         pipe_config->csc_mode = intel_de_read(dev_priv,
4086                                               PIPE_CSC_MODE(crtc->pipe));
4087
4088         if (DISPLAY_VER(dev_priv) >= 9) {
4089                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
4090
4091                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
4092                         pipe_config->gamma_enable = true;
4093
4094                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
4095                         pipe_config->csc_enable = true;
4096         } else {
4097                 i9xx_get_pipe_color_config(pipe_config);
4098         }
4099
4100         intel_color_get_config(pipe_config);
4101
4102         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
4103         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
4104         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4105                 pipe_config->ips_linetime =
4106                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
4107
4108         if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4109                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4110                 if (DISPLAY_VER(dev_priv) >= 9)
4111                         skl_get_pfit_config(pipe_config);
4112                 else
4113                         ilk_get_pfit_config(pipe_config);
4114         }
4115
4116         hsw_ips_get_config(pipe_config);
4117
4118         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4119             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4120                 pipe_config->pixel_multiplier =
4121                         intel_de_read(dev_priv,
4122                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
4123         } else {
4124                 pipe_config->pixel_multiplier = 1;
4125         }
4126
4127         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4128                 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder));
4129
4130                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
4131         } else {
4132                 /* no idea if this is correct */
4133                 pipe_config->framestart_delay = 1;
4134         }
4135
4136 out:
4137         intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
4138
4139         return active;
4140 }
4141
4142 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4143 {
4144         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4145         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4146
4147         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
4148                 return false;
4149
4150         crtc_state->hw.active = true;
4151
4152         intel_crtc_readout_derived_state(crtc_state);
4153
4154         return true;
4155 }
4156
4157 /* VESA 640x480x72Hz mode to set on the pipe */
4158 static const struct drm_display_mode load_detect_mode = {
4159         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4160                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4161 };
4162
4163 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
4164                                         struct drm_crtc *crtc)
4165 {
4166         struct drm_plane *plane;
4167         struct drm_plane_state *plane_state;
4168         int ret, i;
4169
4170         ret = drm_atomic_add_affected_planes(state, crtc);
4171         if (ret)
4172                 return ret;
4173
4174         for_each_new_plane_in_state(state, plane, plane_state, i) {
4175                 if (plane_state->crtc != crtc)
4176                         continue;
4177
4178                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
4179                 if (ret)
4180                         return ret;
4181
4182                 drm_atomic_set_fb_for_plane(plane_state, NULL);
4183         }
4184
4185         return 0;
4186 }
4187
4188 int intel_get_load_detect_pipe(struct drm_connector *connector,
4189                                struct intel_load_detect_pipe *old,
4190                                struct drm_modeset_acquire_ctx *ctx)
4191 {
4192         struct intel_encoder *encoder =
4193                 intel_attached_encoder(to_intel_connector(connector));
4194         struct intel_crtc *possible_crtc;
4195         struct intel_crtc *crtc = NULL;
4196         struct drm_device *dev = encoder->base.dev;
4197         struct drm_i915_private *dev_priv = to_i915(dev);
4198         struct drm_mode_config *config = &dev->mode_config;
4199         struct drm_atomic_state *state = NULL, *restore_state = NULL;
4200         struct drm_connector_state *connector_state;
4201         struct intel_crtc_state *crtc_state;
4202         int ret;
4203
4204         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4205                     connector->base.id, connector->name,
4206                     encoder->base.base.id, encoder->base.name);
4207
4208         old->restore_state = NULL;
4209
4210         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
4211
4212         /*
4213          * Algorithm gets a little messy:
4214          *
4215          *   - if the connector already has an assigned crtc, use it (but make
4216          *     sure it's on first)
4217          *
4218          *   - try to find the first unused crtc that can drive this connector,
4219          *     and use that if we find one
4220          */
4221
4222         /* See if we already have a CRTC for this connector */
4223         if (connector->state->crtc) {
4224                 crtc = to_intel_crtc(connector->state->crtc);
4225
4226                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4227                 if (ret)
4228                         goto fail;
4229
4230                 /* Make sure the crtc and connector are running */
4231                 goto found;
4232         }
4233
4234         /* Find an unused one (if possible) */
4235         for_each_intel_crtc(dev, possible_crtc) {
4236                 if (!(encoder->base.possible_crtcs &
4237                       drm_crtc_mask(&possible_crtc->base)))
4238                         continue;
4239
4240                 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
4241                 if (ret)
4242                         goto fail;
4243
4244                 if (possible_crtc->base.state->enable) {
4245                         drm_modeset_unlock(&possible_crtc->base.mutex);
4246                         continue;
4247                 }
4248
4249                 crtc = possible_crtc;
4250                 break;
4251         }
4252
4253         /*
4254          * If we didn't find an unused CRTC, don't use any.
4255          */
4256         if (!crtc) {
4257                 drm_dbg_kms(&dev_priv->drm,
4258                             "no pipe available for load-detect\n");
4259                 ret = -ENODEV;
4260                 goto fail;
4261         }
4262
4263 found:
4264         state = drm_atomic_state_alloc(dev);
4265         restore_state = drm_atomic_state_alloc(dev);
4266         if (!state || !restore_state) {
4267                 ret = -ENOMEM;
4268                 goto fail;
4269         }
4270
4271         state->acquire_ctx = ctx;
4272         restore_state->acquire_ctx = ctx;
4273
4274         connector_state = drm_atomic_get_connector_state(state, connector);
4275         if (IS_ERR(connector_state)) {
4276                 ret = PTR_ERR(connector_state);
4277                 goto fail;
4278         }
4279
4280         ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
4281         if (ret)
4282                 goto fail;
4283
4284         crtc_state = intel_atomic_get_crtc_state(state, crtc);
4285         if (IS_ERR(crtc_state)) {
4286                 ret = PTR_ERR(crtc_state);
4287                 goto fail;
4288         }
4289
4290         crtc_state->uapi.active = true;
4291
4292         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
4293                                            &load_detect_mode);
4294         if (ret)
4295                 goto fail;
4296
4297         ret = intel_modeset_disable_planes(state, &crtc->base);
4298         if (ret)
4299                 goto fail;
4300
4301         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
4302         if (!ret)
4303                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
4304         if (!ret)
4305                 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
4306         if (ret) {
4307                 drm_dbg_kms(&dev_priv->drm,
4308                             "Failed to create a copy of old state to restore: %i\n",
4309                             ret);
4310                 goto fail;
4311         }
4312
4313         ret = drm_atomic_commit(state);
4314         if (ret) {
4315                 drm_dbg_kms(&dev_priv->drm,
4316                             "failed to set mode on load-detect pipe\n");
4317                 goto fail;
4318         }
4319
4320         old->restore_state = restore_state;
4321         drm_atomic_state_put(state);
4322
4323         /* let the connector get through one full cycle before testing */
4324         intel_crtc_wait_for_next_vblank(crtc);
4325
4326         return true;
4327
4328 fail:
4329         if (state) {
4330                 drm_atomic_state_put(state);
4331                 state = NULL;
4332         }
4333         if (restore_state) {
4334                 drm_atomic_state_put(restore_state);
4335                 restore_state = NULL;
4336         }
4337
4338         if (ret == -EDEADLK)
4339                 return ret;
4340
4341         return false;
4342 }
4343
4344 void intel_release_load_detect_pipe(struct drm_connector *connector,
4345                                     struct intel_load_detect_pipe *old,
4346                                     struct drm_modeset_acquire_ctx *ctx)
4347 {
4348         struct intel_encoder *intel_encoder =
4349                 intel_attached_encoder(to_intel_connector(connector));
4350         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
4351         struct drm_encoder *encoder = &intel_encoder->base;
4352         struct drm_atomic_state *state = old->restore_state;
4353         int ret;
4354
4355         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4356                     connector->base.id, connector->name,
4357                     encoder->base.id, encoder->name);
4358
4359         if (!state)
4360                 return;
4361
4362         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4363         if (ret)
4364                 drm_dbg_kms(&i915->drm,
4365                             "Couldn't release load detect pipe: %i\n", ret);
4366         drm_atomic_state_put(state);
4367 }
4368
4369 static int i9xx_pll_refclk(struct drm_device *dev,
4370                            const struct intel_crtc_state *pipe_config)
4371 {
4372         struct drm_i915_private *dev_priv = to_i915(dev);
4373         u32 dpll = pipe_config->dpll_hw_state.dpll;
4374
4375         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
4376                 return dev_priv->vbt.lvds_ssc_freq;
4377         else if (HAS_PCH_SPLIT(dev_priv))
4378                 return 120000;
4379         else if (DISPLAY_VER(dev_priv) != 2)
4380                 return 96000;
4381         else
4382                 return 48000;
4383 }
4384
4385 /* Returns the clock of the currently programmed mode of the given pipe. */
4386 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
4387                          struct intel_crtc_state *pipe_config)
4388 {
4389         struct drm_device *dev = crtc->base.dev;
4390         struct drm_i915_private *dev_priv = to_i915(dev);
4391         u32 dpll = pipe_config->dpll_hw_state.dpll;
4392         u32 fp;
4393         struct dpll clock;
4394         int port_clock;
4395         int refclk = i9xx_pll_refclk(dev, pipe_config);
4396
4397         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4398                 fp = pipe_config->dpll_hw_state.fp0;
4399         else
4400                 fp = pipe_config->dpll_hw_state.fp1;
4401
4402         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4403         if (IS_PINEVIEW(dev_priv)) {
4404                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4405                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4406         } else {
4407                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4408                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4409         }
4410
4411         if (DISPLAY_VER(dev_priv) != 2) {
4412                 if (IS_PINEVIEW(dev_priv))
4413                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4414                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4415                 else
4416                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4417                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4418
4419                 switch (dpll & DPLL_MODE_MASK) {
4420                 case DPLLB_MODE_DAC_SERIAL:
4421                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4422                                 5 : 10;
4423                         break;
4424                 case DPLLB_MODE_LVDS:
4425                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4426                                 7 : 14;
4427                         break;
4428                 default:
4429                         drm_dbg_kms(&dev_priv->drm,
4430                                     "Unknown DPLL mode %08x in programmed "
4431                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
4432                         return;
4433                 }
4434
4435                 if (IS_PINEVIEW(dev_priv))
4436                         port_clock = pnv_calc_dpll_params(refclk, &clock);
4437                 else
4438                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
4439         } else {
4440                 enum pipe lvds_pipe;
4441
4442                 if (IS_I85X(dev_priv) &&
4443                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
4444                     lvds_pipe == crtc->pipe) {
4445                         u32 lvds = intel_de_read(dev_priv, LVDS);
4446
4447                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4448                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4449
4450                         if (lvds & LVDS_CLKB_POWER_UP)
4451                                 clock.p2 = 7;
4452                         else
4453                                 clock.p2 = 14;
4454                 } else {
4455                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4456                                 clock.p1 = 2;
4457                         else {
4458                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4459                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4460                         }
4461                         if (dpll & PLL_P2_DIVIDE_BY_4)
4462                                 clock.p2 = 4;
4463                         else
4464                                 clock.p2 = 2;
4465                 }
4466
4467                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
4468         }
4469
4470         /*
4471          * This value includes pixel_multiplier. We will use
4472          * port_clock to compute adjusted_mode.crtc_clock in the
4473          * encoder's get_config() function.
4474          */
4475         pipe_config->port_clock = port_clock;
4476 }
4477
4478 int intel_dotclock_calculate(int link_freq,
4479                              const struct intel_link_m_n *m_n)
4480 {
4481         /*
4482          * The calculation for the data clock is:
4483          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4484          * But we want to avoid losing precison if possible, so:
4485          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4486          *
4487          * and the link clock is simpler:
4488          * link_clock = (m * link_clock) / n
4489          */
4490
4491         if (!m_n->link_n)
4492                 return 0;
4493
4494         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
4495 }
4496
4497 /* Returns the currently programmed mode of the given encoder. */
4498 struct drm_display_mode *
4499 intel_encoder_current_mode(struct intel_encoder *encoder)
4500 {
4501         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4502         struct intel_crtc_state *crtc_state;
4503         struct drm_display_mode *mode;
4504         struct intel_crtc *crtc;
4505         enum pipe pipe;
4506
4507         if (!encoder->get_hw_state(encoder, &pipe))
4508                 return NULL;
4509
4510         crtc = intel_crtc_for_pipe(dev_priv, pipe);
4511
4512         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4513         if (!mode)
4514                 return NULL;
4515
4516         crtc_state = intel_crtc_state_alloc(crtc);
4517         if (!crtc_state) {
4518                 kfree(mode);
4519                 return NULL;
4520         }
4521
4522         if (!intel_crtc_get_pipe_config(crtc_state)) {
4523                 kfree(crtc_state);
4524                 kfree(mode);
4525                 return NULL;
4526         }
4527
4528         intel_encoder_get_config(encoder, crtc_state);
4529
4530         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4531
4532         kfree(crtc_state);
4533
4534         return mode;
4535 }
4536
4537 static bool encoders_cloneable(const struct intel_encoder *a,
4538                                const struct intel_encoder *b)
4539 {
4540         /* masks could be asymmetric, so check both ways */
4541         return a == b || (a->cloneable & (1 << b->type) &&
4542                           b->cloneable & (1 << a->type));
4543 }
4544
4545 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4546                                          struct intel_crtc *crtc,
4547                                          struct intel_encoder *encoder)
4548 {
4549         struct intel_encoder *source_encoder;
4550         struct drm_connector *connector;
4551         struct drm_connector_state *connector_state;
4552         int i;
4553
4554         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4555                 if (connector_state->crtc != &crtc->base)
4556                         continue;
4557
4558                 source_encoder =
4559                         to_intel_encoder(connector_state->best_encoder);
4560                 if (!encoders_cloneable(encoder, source_encoder))
4561                         return false;
4562         }
4563
4564         return true;
4565 }
4566
4567 static int icl_add_linked_planes(struct intel_atomic_state *state)
4568 {
4569         struct intel_plane *plane, *linked;
4570         struct intel_plane_state *plane_state, *linked_plane_state;
4571         int i;
4572
4573         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4574                 linked = plane_state->planar_linked_plane;
4575
4576                 if (!linked)
4577                         continue;
4578
4579                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4580                 if (IS_ERR(linked_plane_state))
4581                         return PTR_ERR(linked_plane_state);
4582
4583                 drm_WARN_ON(state->base.dev,
4584                             linked_plane_state->planar_linked_plane != plane);
4585                 drm_WARN_ON(state->base.dev,
4586                             linked_plane_state->planar_slave == plane_state->planar_slave);
4587         }
4588
4589         return 0;
4590 }
4591
4592 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4593 {
4594         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4595         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4596         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4597         struct intel_plane *plane, *linked;
4598         struct intel_plane_state *plane_state;
4599         int i;
4600
4601         if (DISPLAY_VER(dev_priv) < 11)
4602                 return 0;
4603
4604         /*
4605          * Destroy all old plane links and make the slave plane invisible
4606          * in the crtc_state->active_planes mask.
4607          */
4608         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4609                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4610                         continue;
4611
4612                 plane_state->planar_linked_plane = NULL;
4613                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4614                         crtc_state->enabled_planes &= ~BIT(plane->id);
4615                         crtc_state->active_planes &= ~BIT(plane->id);
4616                         crtc_state->update_planes |= BIT(plane->id);
4617                         crtc_state->data_rate[plane->id] = 0;
4618                         crtc_state->rel_data_rate[plane->id] = 0;
4619                 }
4620
4621                 plane_state->planar_slave = false;
4622         }
4623
4624         if (!crtc_state->nv12_planes)
4625                 return 0;
4626
4627         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4628                 struct intel_plane_state *linked_state = NULL;
4629
4630                 if (plane->pipe != crtc->pipe ||
4631                     !(crtc_state->nv12_planes & BIT(plane->id)))
4632                         continue;
4633
4634                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4635                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4636                                 continue;
4637
4638                         if (crtc_state->active_planes & BIT(linked->id))
4639                                 continue;
4640
4641                         linked_state = intel_atomic_get_plane_state(state, linked);
4642                         if (IS_ERR(linked_state))
4643                                 return PTR_ERR(linked_state);
4644
4645                         break;
4646                 }
4647
4648                 if (!linked_state) {
4649                         drm_dbg_kms(&dev_priv->drm,
4650                                     "Need %d free Y planes for planar YUV\n",
4651                                     hweight8(crtc_state->nv12_planes));
4652
4653                         return -EINVAL;
4654                 }
4655
4656                 plane_state->planar_linked_plane = linked;
4657
4658                 linked_state->planar_slave = true;
4659                 linked_state->planar_linked_plane = plane;
4660                 crtc_state->enabled_planes |= BIT(linked->id);
4661                 crtc_state->active_planes |= BIT(linked->id);
4662                 crtc_state->update_planes |= BIT(linked->id);
4663                 crtc_state->data_rate[linked->id] =
4664                         crtc_state->data_rate_y[plane->id];
4665                 crtc_state->rel_data_rate[linked->id] =
4666                         crtc_state->rel_data_rate_y[plane->id];
4667                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4668                             linked->base.name, plane->base.name);
4669
4670                 /* Copy parameters to slave plane */
4671                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4672                 linked_state->color_ctl = plane_state->color_ctl;
4673                 linked_state->view = plane_state->view;
4674                 linked_state->decrypt = plane_state->decrypt;
4675
4676                 intel_plane_copy_hw_state(linked_state, plane_state);
4677                 linked_state->uapi.src = plane_state->uapi.src;
4678                 linked_state->uapi.dst = plane_state->uapi.dst;
4679
4680                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4681                         if (linked->id == PLANE_SPRITE5)
4682                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4683                         else if (linked->id == PLANE_SPRITE4)
4684                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4685                         else if (linked->id == PLANE_SPRITE3)
4686                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4687                         else if (linked->id == PLANE_SPRITE2)
4688                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4689                         else
4690                                 MISSING_CASE(linked->id);
4691                 }
4692         }
4693
4694         return 0;
4695 }
4696
4697 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4698 {
4699         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4700         struct intel_atomic_state *state =
4701                 to_intel_atomic_state(new_crtc_state->uapi.state);
4702         const struct intel_crtc_state *old_crtc_state =
4703                 intel_atomic_get_old_crtc_state(state, crtc);
4704
4705         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4706 }
4707
4708 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4709 {
4710         const struct drm_display_mode *pipe_mode =
4711                 &crtc_state->hw.pipe_mode;
4712         int linetime_wm;
4713
4714         if (!crtc_state->hw.enable)
4715                 return 0;
4716
4717         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4718                                         pipe_mode->crtc_clock);
4719
4720         return min(linetime_wm, 0x1ff);
4721 }
4722
4723 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4724                                const struct intel_cdclk_state *cdclk_state)
4725 {
4726         const struct drm_display_mode *pipe_mode =
4727                 &crtc_state->hw.pipe_mode;
4728         int linetime_wm;
4729
4730         if (!crtc_state->hw.enable)
4731                 return 0;
4732
4733         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4734                                         cdclk_state->logical.cdclk);
4735
4736         return min(linetime_wm, 0x1ff);
4737 }
4738
4739 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4740 {
4741         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4743         const struct drm_display_mode *pipe_mode =
4744                 &crtc_state->hw.pipe_mode;
4745         int linetime_wm;
4746
4747         if (!crtc_state->hw.enable)
4748                 return 0;
4749
4750         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4751                                    crtc_state->pixel_rate);
4752
4753         /* Display WA #1135: BXT:ALL GLK:ALL */
4754         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4755             dev_priv->ipc_enabled)
4756                 linetime_wm /= 2;
4757
4758         return min(linetime_wm, 0x1ff);
4759 }
4760
4761 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4762                                    struct intel_crtc *crtc)
4763 {
4764         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4765         struct intel_crtc_state *crtc_state =
4766                 intel_atomic_get_new_crtc_state(state, crtc);
4767         const struct intel_cdclk_state *cdclk_state;
4768
4769         if (DISPLAY_VER(dev_priv) >= 9)
4770                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4771         else
4772                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4773
4774         if (!hsw_crtc_supports_ips(crtc))
4775                 return 0;
4776
4777         cdclk_state = intel_atomic_get_cdclk_state(state);
4778         if (IS_ERR(cdclk_state))
4779                 return PTR_ERR(cdclk_state);
4780
4781         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4782                                                        cdclk_state);
4783
4784         return 0;
4785 }
4786
4787 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4788                                    struct intel_crtc *crtc)
4789 {
4790         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4791         struct intel_crtc_state *crtc_state =
4792                 intel_atomic_get_new_crtc_state(state, crtc);
4793         bool mode_changed = intel_crtc_needs_modeset(crtc_state);
4794         int ret;
4795
4796         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4797             mode_changed && !crtc_state->hw.active)
4798                 crtc_state->update_wm_post = true;
4799
4800         if (mode_changed) {
4801                 ret = intel_dpll_crtc_compute_clock(state, crtc);
4802                 if (ret)
4803                         return ret;
4804
4805                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4806                 if (ret)
4807                         return ret;
4808         }
4809
4810         /*
4811          * May need to update pipe gamma enable bits
4812          * when C8 planes are getting enabled/disabled.
4813          */
4814         if (c8_planes_changed(crtc_state))
4815                 crtc_state->uapi.color_mgmt_changed = true;
4816
4817         if (mode_changed || crtc_state->update_pipe ||
4818             crtc_state->uapi.color_mgmt_changed) {
4819                 ret = intel_color_check(crtc_state);
4820                 if (ret)
4821                         return ret;
4822         }
4823
4824         ret = intel_compute_pipe_wm(state, crtc);
4825         if (ret) {
4826                 drm_dbg_kms(&dev_priv->drm,
4827                             "Target pipe watermarks are invalid\n");
4828                 return ret;
4829         }
4830
4831         /*
4832          * Calculate 'intermediate' watermarks that satisfy both the
4833          * old state and the new state.  We can program these
4834          * immediately.
4835          */
4836         ret = intel_compute_intermediate_wm(state, crtc);
4837         if (ret) {
4838                 drm_dbg_kms(&dev_priv->drm,
4839                             "No valid intermediate pipe watermarks are possible\n");
4840                 return ret;
4841         }
4842
4843         if (DISPLAY_VER(dev_priv) >= 9) {
4844                 if (mode_changed || crtc_state->update_pipe) {
4845                         ret = skl_update_scaler_crtc(crtc_state);
4846                         if (ret)
4847                                 return ret;
4848                 }
4849
4850                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4851                 if (ret)
4852                         return ret;
4853         }
4854
4855         if (HAS_IPS(dev_priv)) {
4856                 ret = hsw_ips_compute_config(state, crtc);
4857                 if (ret)
4858                         return ret;
4859         }
4860
4861         if (DISPLAY_VER(dev_priv) >= 9 ||
4862             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4863                 ret = hsw_compute_linetime_wm(state, crtc);
4864                 if (ret)
4865                         return ret;
4866
4867         }
4868
4869         ret = intel_psr2_sel_fetch_update(state, crtc);
4870         if (ret)
4871                 return ret;
4872
4873         return 0;
4874 }
4875
4876 static int
4877 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4878                       struct intel_crtc_state *crtc_state)
4879 {
4880         struct drm_connector *connector = conn_state->connector;
4881         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4882         const struct drm_display_info *info = &connector->display_info;
4883         int bpp;
4884
4885         switch (conn_state->max_bpc) {
4886         case 6 ... 7:
4887                 bpp = 6 * 3;
4888                 break;
4889         case 8 ... 9:
4890                 bpp = 8 * 3;
4891                 break;
4892         case 10 ... 11:
4893                 bpp = 10 * 3;
4894                 break;
4895         case 12 ... 16:
4896                 bpp = 12 * 3;
4897                 break;
4898         default:
4899                 MISSING_CASE(conn_state->max_bpc);
4900                 return -EINVAL;
4901         }
4902
4903         if (bpp < crtc_state->pipe_bpp) {
4904                 drm_dbg_kms(&i915->drm,
4905                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4906                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4907                             connector->base.id, connector->name,
4908                             bpp, 3 * info->bpc,
4909                             3 * conn_state->max_requested_bpc,
4910                             crtc_state->pipe_bpp);
4911
4912                 crtc_state->pipe_bpp = bpp;
4913         }
4914
4915         return 0;
4916 }
4917
4918 static int
4919 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4920                           struct intel_crtc *crtc)
4921 {
4922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4923         struct intel_crtc_state *crtc_state =
4924                 intel_atomic_get_new_crtc_state(state, crtc);
4925         struct drm_connector *connector;
4926         struct drm_connector_state *connector_state;
4927         int bpp, i;
4928
4929         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4930             IS_CHERRYVIEW(dev_priv)))
4931                 bpp = 10*3;
4932         else if (DISPLAY_VER(dev_priv) >= 5)
4933                 bpp = 12*3;
4934         else
4935                 bpp = 8*3;
4936
4937         crtc_state->pipe_bpp = bpp;
4938
4939         /* Clamp display bpp to connector max bpp */
4940         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4941                 int ret;
4942
4943                 if (connector_state->crtc != &crtc->base)
4944                         continue;
4945
4946                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4947                 if (ret)
4948                         return ret;
4949         }
4950
4951         return 0;
4952 }
4953
4954 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4955 {
4956         struct drm_device *dev = state->base.dev;
4957         struct drm_connector *connector;
4958         struct drm_connector_list_iter conn_iter;
4959         unsigned int used_ports = 0;
4960         unsigned int used_mst_ports = 0;
4961         bool ret = true;
4962
4963         /*
4964          * We're going to peek into connector->state,
4965          * hence connection_mutex must be held.
4966          */
4967         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4968
4969         /*
4970          * Walk the connector list instead of the encoder
4971          * list to detect the problem on ddi platforms
4972          * where there's just one encoder per digital port.
4973          */
4974         drm_connector_list_iter_begin(dev, &conn_iter);
4975         drm_for_each_connector_iter(connector, &conn_iter) {
4976                 struct drm_connector_state *connector_state;
4977                 struct intel_encoder *encoder;
4978
4979                 connector_state =
4980                         drm_atomic_get_new_connector_state(&state->base,
4981                                                            connector);
4982                 if (!connector_state)
4983                         connector_state = connector->state;
4984
4985                 if (!connector_state->best_encoder)
4986                         continue;
4987
4988                 encoder = to_intel_encoder(connector_state->best_encoder);
4989
4990                 drm_WARN_ON(dev, !connector_state->crtc);
4991
4992                 switch (encoder->type) {
4993                 case INTEL_OUTPUT_DDI:
4994                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4995                                 break;
4996                         fallthrough;
4997                 case INTEL_OUTPUT_DP:
4998                 case INTEL_OUTPUT_HDMI:
4999                 case INTEL_OUTPUT_EDP:
5000                         /* the same port mustn't appear more than once */
5001                         if (used_ports & BIT(encoder->port))
5002                                 ret = false;
5003
5004                         used_ports |= BIT(encoder->port);
5005                         break;
5006                 case INTEL_OUTPUT_DP_MST:
5007                         used_mst_ports |=
5008                                 1 << encoder->port;
5009                         break;
5010                 default:
5011                         break;
5012                 }
5013         }
5014         drm_connector_list_iter_end(&conn_iter);
5015
5016         /* can't mix MST and SST/HDMI on the same port */
5017         if (used_ports & used_mst_ports)
5018                 return false;
5019
5020         return ret;
5021 }
5022
5023 static void
5024 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
5025                                            struct intel_crtc *crtc)
5026 {
5027         struct intel_crtc_state *crtc_state =
5028                 intel_atomic_get_new_crtc_state(state, crtc);
5029
5030         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5031
5032         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
5033                                   crtc_state->uapi.degamma_lut);
5034         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
5035                                   crtc_state->uapi.gamma_lut);
5036         drm_property_replace_blob(&crtc_state->hw.ctm,
5037                                   crtc_state->uapi.ctm);
5038 }
5039
5040 static void
5041 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
5042                                          struct intel_crtc *crtc)
5043 {
5044         struct intel_crtc_state *crtc_state =
5045                 intel_atomic_get_new_crtc_state(state, crtc);
5046
5047         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5048
5049         crtc_state->hw.enable = crtc_state->uapi.enable;
5050         crtc_state->hw.active = crtc_state->uapi.active;
5051         drm_mode_copy(&crtc_state->hw.mode,
5052                       &crtc_state->uapi.mode);
5053         drm_mode_copy(&crtc_state->hw.adjusted_mode,
5054                       &crtc_state->uapi.adjusted_mode);
5055         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
5056
5057         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
5058 }
5059
5060 static void
5061 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
5062                                     struct intel_crtc *slave_crtc)
5063 {
5064         struct intel_crtc_state *slave_crtc_state =
5065                 intel_atomic_get_new_crtc_state(state, slave_crtc);
5066         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5067         const struct intel_crtc_state *master_crtc_state =
5068                 intel_atomic_get_new_crtc_state(state, master_crtc);
5069
5070         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
5071                                   master_crtc_state->hw.degamma_lut);
5072         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
5073                                   master_crtc_state->hw.gamma_lut);
5074         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
5075                                   master_crtc_state->hw.ctm);
5076
5077         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
5078 }
5079
5080 static int
5081 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
5082                                   struct intel_crtc *slave_crtc)
5083 {
5084         struct intel_crtc_state *slave_crtc_state =
5085                 intel_atomic_get_new_crtc_state(state, slave_crtc);
5086         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5087         const struct intel_crtc_state *master_crtc_state =
5088                 intel_atomic_get_new_crtc_state(state, master_crtc);
5089         struct intel_crtc_state *saved_state;
5090
5091         WARN_ON(master_crtc_state->bigjoiner_pipes !=
5092                 slave_crtc_state->bigjoiner_pipes);
5093
5094         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
5095         if (!saved_state)
5096                 return -ENOMEM;
5097
5098         /* preserve some things from the slave's original crtc state */
5099         saved_state->uapi = slave_crtc_state->uapi;
5100         saved_state->scaler_state = slave_crtc_state->scaler_state;
5101         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
5102         saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
5103         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
5104
5105         intel_crtc_free_hw_state(slave_crtc_state);
5106         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
5107         kfree(saved_state);
5108
5109         /* Re-init hw state */
5110         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
5111         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
5112         slave_crtc_state->hw.active = master_crtc_state->hw.active;
5113         drm_mode_copy(&slave_crtc_state->hw.mode,
5114                       &master_crtc_state->hw.mode);
5115         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
5116                       &master_crtc_state->hw.pipe_mode);
5117         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
5118                       &master_crtc_state->hw.adjusted_mode);
5119         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
5120
5121         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
5122
5123         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
5124         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
5125         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
5126
5127         WARN_ON(master_crtc_state->bigjoiner_pipes !=
5128                 slave_crtc_state->bigjoiner_pipes);
5129
5130         return 0;
5131 }
5132
5133 static int
5134 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
5135                                  struct intel_crtc *crtc)
5136 {
5137         struct intel_crtc_state *crtc_state =
5138                 intel_atomic_get_new_crtc_state(state, crtc);
5139         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5140         struct intel_crtc_state *saved_state;
5141
5142         saved_state = intel_crtc_state_alloc(crtc);
5143         if (!saved_state)
5144                 return -ENOMEM;
5145
5146         /* free the old crtc_state->hw members */
5147         intel_crtc_free_hw_state(crtc_state);
5148
5149         /* FIXME: before the switch to atomic started, a new pipe_config was
5150          * kzalloc'd. Code that depends on any field being zero should be
5151          * fixed, so that the crtc_state can be safely duplicated. For now,
5152          * only fields that are know to not cause problems are preserved. */
5153
5154         saved_state->uapi = crtc_state->uapi;
5155         saved_state->scaler_state = crtc_state->scaler_state;
5156         saved_state->shared_dpll = crtc_state->shared_dpll;
5157         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
5158         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
5159                sizeof(saved_state->icl_port_dplls));
5160         saved_state->crc_enabled = crtc_state->crc_enabled;
5161         if (IS_G4X(dev_priv) ||
5162             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5163                 saved_state->wm = crtc_state->wm;
5164
5165         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
5166         kfree(saved_state);
5167
5168         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
5169
5170         return 0;
5171 }
5172
5173 static int
5174 intel_modeset_pipe_config(struct intel_atomic_state *state,
5175                           struct intel_crtc *crtc)
5176 {
5177         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5178         struct intel_crtc_state *crtc_state =
5179                 intel_atomic_get_new_crtc_state(state, crtc);
5180         struct drm_connector *connector;
5181         struct drm_connector_state *connector_state;
5182         int pipe_src_w, pipe_src_h;
5183         int base_bpp, ret, i;
5184         bool retry = true;
5185
5186         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
5187
5188         crtc_state->framestart_delay = 1;
5189
5190         /*
5191          * Sanitize sync polarity flags based on requested ones. If neither
5192          * positive or negative polarity is requested, treat this as meaning
5193          * negative polarity.
5194          */
5195         if (!(crtc_state->hw.adjusted_mode.flags &
5196               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
5197                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
5198
5199         if (!(crtc_state->hw.adjusted_mode.flags &
5200               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
5201                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
5202
5203         ret = compute_baseline_pipe_bpp(state, crtc);
5204         if (ret)
5205                 return ret;
5206
5207         base_bpp = crtc_state->pipe_bpp;
5208
5209         /*
5210          * Determine the real pipe dimensions. Note that stereo modes can
5211          * increase the actual pipe size due to the frame doubling and
5212          * insertion of additional space for blanks between the frame. This
5213          * is stored in the crtc timings. We use the requested mode to do this
5214          * computation to clearly distinguish it from the adjusted mode, which
5215          * can be changed by the connectors in the below retry loop.
5216          */
5217         drm_mode_get_hv_timing(&crtc_state->hw.mode,
5218                                &pipe_src_w, &pipe_src_h);
5219         drm_rect_init(&crtc_state->pipe_src, 0, 0,
5220                       pipe_src_w, pipe_src_h);
5221
5222         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5223                 struct intel_encoder *encoder =
5224                         to_intel_encoder(connector_state->best_encoder);
5225
5226                 if (connector_state->crtc != &crtc->base)
5227                         continue;
5228
5229                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
5230                         drm_dbg_kms(&i915->drm,
5231                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
5232                                     encoder->base.base.id, encoder->base.name);
5233                         return -EINVAL;
5234                 }
5235
5236                 /*
5237                  * Determine output_types before calling the .compute_config()
5238                  * hooks so that the hooks can use this information safely.
5239                  */
5240                 if (encoder->compute_output_type)
5241                         crtc_state->output_types |=
5242                                 BIT(encoder->compute_output_type(encoder, crtc_state,
5243                                                                  connector_state));
5244                 else
5245                         crtc_state->output_types |= BIT(encoder->type);
5246         }
5247
5248 encoder_retry:
5249         /* Ensure the port clock defaults are reset when retrying. */
5250         crtc_state->port_clock = 0;
5251         crtc_state->pixel_multiplier = 1;
5252
5253         /* Fill in default crtc timings, allow encoders to overwrite them. */
5254         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5255                               CRTC_STEREO_DOUBLE);
5256
5257         /* Pass our mode to the connectors and the CRTC to give them a chance to
5258          * adjust it according to limitations or connector properties, and also
5259          * a chance to reject the mode entirely.
5260          */
5261         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5262                 struct intel_encoder *encoder =
5263                         to_intel_encoder(connector_state->best_encoder);
5264
5265                 if (connector_state->crtc != &crtc->base)
5266                         continue;
5267
5268                 ret = encoder->compute_config(encoder, crtc_state,
5269                                               connector_state);
5270                 if (ret == -EDEADLK)
5271                         return ret;
5272                 if (ret < 0) {
5273                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5274                                     encoder->base.base.id, encoder->base.name, ret);
5275                         return ret;
5276                 }
5277         }
5278
5279         /* Set default port clock if not overwritten by the encoder. Needs to be
5280          * done afterwards in case the encoder adjusts the mode. */
5281         if (!crtc_state->port_clock)
5282                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5283                         * crtc_state->pixel_multiplier;
5284
5285         ret = intel_crtc_compute_config(state, crtc);
5286         if (ret == -EDEADLK)
5287                 return ret;
5288         if (ret == -EAGAIN) {
5289                 if (drm_WARN(&i915->drm, !retry,
5290                              "[CRTC:%d:%s] loop in pipe configuration computation\n",
5291                              crtc->base.base.id, crtc->base.name))
5292                         return -EINVAL;
5293
5294                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
5295                             crtc->base.base.id, crtc->base.name);
5296                 retry = false;
5297                 goto encoder_retry;
5298         }
5299         if (ret < 0) {
5300                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5301                             crtc->base.base.id, crtc->base.name, ret);
5302                 return ret;
5303         }
5304
5305         /* Dithering seems to not pass-through bits correctly when it should, so
5306          * only enable it on 6bpc panels and when its not a compliance
5307          * test requesting 6bpc video pattern.
5308          */
5309         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5310                 !crtc_state->dither_force_disable;
5311         drm_dbg_kms(&i915->drm,
5312                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5313                     crtc->base.base.id, crtc->base.name,
5314                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5315
5316         return 0;
5317 }
5318
5319 static int
5320 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5321                                struct intel_crtc *crtc)
5322 {
5323         struct intel_crtc_state *crtc_state =
5324                 intel_atomic_get_new_crtc_state(state, crtc);
5325         struct drm_connector_state *conn_state;
5326         struct drm_connector *connector;
5327         int i;
5328
5329         intel_bigjoiner_adjust_pipe_src(crtc_state);
5330
5331         for_each_new_connector_in_state(&state->base, connector,
5332                                         conn_state, i) {
5333                 struct intel_encoder *encoder =
5334                         to_intel_encoder(conn_state->best_encoder);
5335                 int ret;
5336
5337                 if (conn_state->crtc != &crtc->base ||
5338                     !encoder->compute_config_late)
5339                         continue;
5340
5341                 ret = encoder->compute_config_late(encoder, crtc_state,
5342                                                    conn_state);
5343                 if (ret)
5344                         return ret;
5345         }
5346
5347         return 0;
5348 }
5349
5350 bool intel_fuzzy_clock_check(int clock1, int clock2)
5351 {
5352         int diff;
5353
5354         if (clock1 == clock2)
5355                 return true;
5356
5357         if (!clock1 || !clock2)
5358                 return false;
5359
5360         diff = abs(clock1 - clock2);
5361
5362         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5363                 return true;
5364
5365         return false;
5366 }
5367
5368 static bool
5369 intel_compare_m_n(unsigned int m, unsigned int n,
5370                   unsigned int m2, unsigned int n2,
5371                   bool exact)
5372 {
5373         if (m == m2 && n == n2)
5374                 return true;
5375
5376         if (exact || !m || !n || !m2 || !n2)
5377                 return false;
5378
5379         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
5380
5381         if (n > n2) {
5382                 while (n > n2) {
5383                         m2 <<= 1;
5384                         n2 <<= 1;
5385                 }
5386         } else if (n < n2) {
5387                 while (n < n2) {
5388                         m <<= 1;
5389                         n <<= 1;
5390                 }
5391         }
5392
5393         if (n != n2)
5394                 return false;
5395
5396         return intel_fuzzy_clock_check(m, m2);
5397 }
5398
5399 static bool
5400 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5401                        const struct intel_link_m_n *m2_n2,
5402                        bool exact)
5403 {
5404         return m_n->tu == m2_n2->tu &&
5405                 intel_compare_m_n(m_n->data_m, m_n->data_n,
5406                                   m2_n2->data_m, m2_n2->data_n, exact) &&
5407                 intel_compare_m_n(m_n->link_m, m_n->link_n,
5408                                   m2_n2->link_m, m2_n2->link_n, exact);
5409 }
5410
5411 static bool
5412 intel_compare_infoframe(const union hdmi_infoframe *a,
5413                         const union hdmi_infoframe *b)
5414 {
5415         return memcmp(a, b, sizeof(*a)) == 0;
5416 }
5417
5418 static bool
5419 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5420                          const struct drm_dp_vsc_sdp *b)
5421 {
5422         return memcmp(a, b, sizeof(*a)) == 0;
5423 }
5424
5425 static void
5426 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
5427                                bool fastset, const char *name,
5428                                const union hdmi_infoframe *a,
5429                                const union hdmi_infoframe *b)
5430 {
5431         if (fastset) {
5432                 if (!drm_debug_enabled(DRM_UT_KMS))
5433                         return;
5434
5435                 drm_dbg_kms(&dev_priv->drm,
5436                             "fastset mismatch in %s infoframe\n", name);
5437                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5438                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
5439                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5440                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
5441         } else {
5442                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
5443                 drm_err(&dev_priv->drm, "expected:\n");
5444                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
5445                 drm_err(&dev_priv->drm, "found:\n");
5446                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
5447         }
5448 }
5449
5450 static void
5451 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
5452                                 bool fastset, const char *name,
5453                                 const struct drm_dp_vsc_sdp *a,
5454                                 const struct drm_dp_vsc_sdp *b)
5455 {
5456         if (fastset) {
5457                 if (!drm_debug_enabled(DRM_UT_KMS))
5458                         return;
5459
5460                 drm_dbg_kms(&dev_priv->drm,
5461                             "fastset mismatch in %s dp sdp\n", name);
5462                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5463                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
5464                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5465                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
5466         } else {
5467                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
5468                 drm_err(&dev_priv->drm, "expected:\n");
5469                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
5470                 drm_err(&dev_priv->drm, "found:\n");
5471                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
5472         }
5473 }
5474
5475 static void __printf(4, 5)
5476 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
5477                      const char *name, const char *format, ...)
5478 {
5479         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5480         struct va_format vaf;
5481         va_list args;
5482
5483         va_start(args, format);
5484         vaf.fmt = format;
5485         vaf.va = &args;
5486
5487         if (fastset)
5488                 drm_dbg_kms(&i915->drm,
5489                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
5490                             crtc->base.base.id, crtc->base.name, name, &vaf);
5491         else
5492                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
5493                         crtc->base.base.id, crtc->base.name, name, &vaf);
5494
5495         va_end(args);
5496 }
5497
5498 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5499 {
5500         if (dev_priv->params.fastboot != -1)
5501                 return dev_priv->params.fastboot;
5502
5503         /* Enable fastboot by default on Skylake and newer */
5504         if (DISPLAY_VER(dev_priv) >= 9)
5505                 return true;
5506
5507         /* Enable fastboot by default on VLV and CHV */
5508         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5509                 return true;
5510
5511         /* Disabled by default on all others */
5512         return false;
5513 }
5514
5515 bool
5516 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5517                           const struct intel_crtc_state *pipe_config,
5518                           bool fastset)
5519 {
5520         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5521         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5522         bool ret = true;
5523         u32 bp_gamma = 0;
5524         bool fixup_inherited = fastset &&
5525                 current_config->inherited && !pipe_config->inherited;
5526
5527         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5528                 drm_dbg_kms(&dev_priv->drm,
5529                             "initial modeset and fastboot not set\n");
5530                 ret = false;
5531         }
5532
5533 #define PIPE_CONF_CHECK_X(name) do { \
5534         if (current_config->name != pipe_config->name) { \
5535                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5536                                      "(expected 0x%08x, found 0x%08x)", \
5537                                      current_config->name, \
5538                                      pipe_config->name); \
5539                 ret = false; \
5540         } \
5541 } while (0)
5542
5543 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5544         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5545                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5546                                      "(expected 0x%08x, found 0x%08x)", \
5547                                      current_config->name & (mask), \
5548                                      pipe_config->name & (mask)); \
5549                 ret = false; \
5550         } \
5551 } while (0)
5552
5553 #define PIPE_CONF_CHECK_I(name) do { \
5554         if (current_config->name != pipe_config->name) { \
5555                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5556                                      "(expected %i, found %i)", \
5557                                      current_config->name, \
5558                                      pipe_config->name); \
5559                 ret = false; \
5560         } \
5561 } while (0)
5562
5563 #define PIPE_CONF_CHECK_BOOL(name) do { \
5564         if (current_config->name != pipe_config->name) { \
5565                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5566                                      "(expected %s, found %s)", \
5567                                      str_yes_no(current_config->name), \
5568                                      str_yes_no(pipe_config->name)); \
5569                 ret = false; \
5570         } \
5571 } while (0)
5572
5573 /*
5574  * Checks state where we only read out the enabling, but not the entire
5575  * state itself (like full infoframes or ELD for audio). These states
5576  * require a full modeset on bootup to fix up.
5577  */
5578 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5579         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5580                 PIPE_CONF_CHECK_BOOL(name); \
5581         } else { \
5582                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5583                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5584                                      str_yes_no(current_config->name), \
5585                                      str_yes_no(pipe_config->name)); \
5586                 ret = false; \
5587         } \
5588 } while (0)
5589
5590 #define PIPE_CONF_CHECK_P(name) do { \
5591         if (current_config->name != pipe_config->name) { \
5592                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5593                                      "(expected %p, found %p)", \
5594                                      current_config->name, \
5595                                      pipe_config->name); \
5596                 ret = false; \
5597         } \
5598 } while (0)
5599
5600 #define PIPE_CONF_CHECK_M_N(name) do { \
5601         if (!intel_compare_link_m_n(&current_config->name, \
5602                                     &pipe_config->name,\
5603                                     !fastset)) { \
5604                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5605                                      "(expected tu %i data %i/%i link %i/%i, " \
5606                                      "found tu %i, data %i/%i link %i/%i)", \
5607                                      current_config->name.tu, \
5608                                      current_config->name.data_m, \
5609                                      current_config->name.data_n, \
5610                                      current_config->name.link_m, \
5611                                      current_config->name.link_n, \
5612                                      pipe_config->name.tu, \
5613                                      pipe_config->name.data_m, \
5614                                      pipe_config->name.data_n, \
5615                                      pipe_config->name.link_m, \
5616                                      pipe_config->name.link_n); \
5617                 ret = false; \
5618         } \
5619 } while (0)
5620
5621 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5622         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5623         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5624         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5625         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5626         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5627         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5628         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5629         PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5630         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5631         PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5632         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5633         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5634 } while (0)
5635
5636 #define PIPE_CONF_CHECK_RECT(name) do { \
5637         PIPE_CONF_CHECK_I(name.x1); \
5638         PIPE_CONF_CHECK_I(name.x2); \
5639         PIPE_CONF_CHECK_I(name.y1); \
5640         PIPE_CONF_CHECK_I(name.y2); \
5641 } while (0)
5642
5643 /* This is required for BDW+ where there is only one set of registers for
5644  * switching between high and low RR.
5645  * This macro can be used whenever a comparison has to be made between one
5646  * hw state and multiple sw state variables.
5647  */
5648 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
5649         if (!intel_compare_link_m_n(&current_config->name, \
5650                                     &pipe_config->name, !fastset) && \
5651             !intel_compare_link_m_n(&current_config->alt_name, \
5652                                     &pipe_config->name, !fastset)) { \
5653                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5654                                      "(expected tu %i data %i/%i link %i/%i, " \
5655                                      "or tu %i data %i/%i link %i/%i, " \
5656                                      "found tu %i, data %i/%i link %i/%i)", \
5657                                      current_config->name.tu, \
5658                                      current_config->name.data_m, \
5659                                      current_config->name.data_n, \
5660                                      current_config->name.link_m, \
5661                                      current_config->name.link_n, \
5662                                      current_config->alt_name.tu, \
5663                                      current_config->alt_name.data_m, \
5664                                      current_config->alt_name.data_n, \
5665                                      current_config->alt_name.link_m, \
5666                                      current_config->alt_name.link_n, \
5667                                      pipe_config->name.tu, \
5668                                      pipe_config->name.data_m, \
5669                                      pipe_config->name.data_n, \
5670                                      pipe_config->name.link_m, \
5671                                      pipe_config->name.link_n); \
5672                 ret = false; \
5673         } \
5674 } while (0)
5675
5676 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5677         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5678                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5679                                      "(%x) (expected %i, found %i)", \
5680                                      (mask), \
5681                                      current_config->name & (mask), \
5682                                      pipe_config->name & (mask)); \
5683                 ret = false; \
5684         } \
5685 } while (0)
5686
5687 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
5688         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
5689                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5690                                      "(expected %i, found %i)", \
5691                                      current_config->name, \
5692                                      pipe_config->name); \
5693                 ret = false; \
5694         } \
5695 } while (0)
5696
5697 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5698         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5699                                      &pipe_config->infoframes.name)) { \
5700                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5701                                                &current_config->infoframes.name, \
5702                                                &pipe_config->infoframes.name); \
5703                 ret = false; \
5704         } \
5705 } while (0)
5706
5707 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5708         if (!current_config->has_psr && !pipe_config->has_psr && \
5709             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5710                                       &pipe_config->infoframes.name)) { \
5711                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5712                                                 &current_config->infoframes.name, \
5713                                                 &pipe_config->infoframes.name); \
5714                 ret = false; \
5715         } \
5716 } while (0)
5717
5718 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
5719         if (current_config->name1 != pipe_config->name1) { \
5720                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
5721                                 "(expected %i, found %i, won't compare lut values)", \
5722                                 current_config->name1, \
5723                                 pipe_config->name1); \
5724                 ret = false;\
5725         } else { \
5726                 if (!intel_color_lut_equal(current_config->name2, \
5727                                         pipe_config->name2, pipe_config->name1, \
5728                                         bit_precision)) { \
5729                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
5730                                         "hw_state doesn't match sw_state"); \
5731                         ret = false; \
5732                 } \
5733         } \
5734 } while (0)
5735
5736 #define PIPE_CONF_QUIRK(quirk) \
5737         ((current_config->quirks | pipe_config->quirks) & (quirk))
5738
5739         PIPE_CONF_CHECK_I(hw.enable);
5740         PIPE_CONF_CHECK_I(hw.active);
5741
5742         PIPE_CONF_CHECK_I(cpu_transcoder);
5743         PIPE_CONF_CHECK_I(mst_master_transcoder);
5744
5745         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5746         PIPE_CONF_CHECK_I(fdi_lanes);
5747         PIPE_CONF_CHECK_M_N(fdi_m_n);
5748
5749         PIPE_CONF_CHECK_I(lane_count);
5750         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5751
5752         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
5753                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
5754         } else {
5755                 PIPE_CONF_CHECK_M_N(dp_m_n);
5756                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5757         }
5758
5759         PIPE_CONF_CHECK_X(output_types);
5760
5761         PIPE_CONF_CHECK_I(framestart_delay);
5762         PIPE_CONF_CHECK_I(msa_timing_delay);
5763
5764         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5765         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5766
5767         PIPE_CONF_CHECK_I(pixel_multiplier);
5768
5769         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5770                               DRM_MODE_FLAG_INTERLACE);
5771
5772         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5773                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5774                                       DRM_MODE_FLAG_PHSYNC);
5775                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5776                                       DRM_MODE_FLAG_NHSYNC);
5777                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5778                                       DRM_MODE_FLAG_PVSYNC);
5779                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5780                                       DRM_MODE_FLAG_NVSYNC);
5781         }
5782
5783         PIPE_CONF_CHECK_I(output_format);
5784         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5785         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5786             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5787                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5788
5789         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5790         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5791         PIPE_CONF_CHECK_BOOL(has_infoframe);
5792         PIPE_CONF_CHECK_BOOL(fec_enable);
5793
5794         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5795
5796         PIPE_CONF_CHECK_X(gmch_pfit.control);
5797         /* pfit ratios are autocomputed by the hw on gen4+ */
5798         if (DISPLAY_VER(dev_priv) < 4)
5799                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5800         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5801
5802         /*
5803          * Changing the EDP transcoder input mux
5804          * (A_ONOFF vs. A_ON) requires a full modeset.
5805          */
5806         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5807
5808         if (!fastset) {
5809                 PIPE_CONF_CHECK_RECT(pipe_src);
5810
5811                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5812                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5813
5814                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5815                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
5816
5817                 PIPE_CONF_CHECK_X(gamma_mode);
5818                 if (IS_CHERRYVIEW(dev_priv))
5819                         PIPE_CONF_CHECK_X(cgm_mode);
5820                 else
5821                         PIPE_CONF_CHECK_X(csc_mode);
5822                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5823                 PIPE_CONF_CHECK_BOOL(csc_enable);
5824
5825                 PIPE_CONF_CHECK_I(linetime);
5826                 PIPE_CONF_CHECK_I(ips_linetime);
5827
5828                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
5829                 if (bp_gamma)
5830                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
5831
5832                 if (current_config->active_planes) {
5833                         PIPE_CONF_CHECK_BOOL(has_psr);
5834                         PIPE_CONF_CHECK_BOOL(has_psr2);
5835                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5836                         PIPE_CONF_CHECK_I(dc3co_exitline);
5837                 }
5838         }
5839
5840         PIPE_CONF_CHECK_BOOL(double_wide);
5841
5842         if (dev_priv->display.dpll.mgr) {
5843                 PIPE_CONF_CHECK_P(shared_dpll);
5844
5845                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5846                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5847                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5848                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5849                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5850                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5851                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5852                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5853                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5854                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5855                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5856                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5857                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5858                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5859                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5860                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5861                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5862                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5863                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5864                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5865                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5866                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5867                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5868                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5869                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5870                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5871                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5872                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5873                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5874                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5875                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5876                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5877         }
5878
5879         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5880         PIPE_CONF_CHECK_X(dsi_pll.div);
5881
5882         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5883                 PIPE_CONF_CHECK_I(pipe_bpp);
5884
5885         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
5886         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
5887         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5888
5889         PIPE_CONF_CHECK_I(min_voltage_level);
5890
5891         if (current_config->has_psr || pipe_config->has_psr)
5892                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5893                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5894         else
5895                 PIPE_CONF_CHECK_X(infoframes.enable);
5896
5897         PIPE_CONF_CHECK_X(infoframes.gcp);
5898         PIPE_CONF_CHECK_INFOFRAME(avi);
5899         PIPE_CONF_CHECK_INFOFRAME(spd);
5900         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5901         PIPE_CONF_CHECK_INFOFRAME(drm);
5902         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5903
5904         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5905         PIPE_CONF_CHECK_I(master_transcoder);
5906         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5907
5908         PIPE_CONF_CHECK_I(dsc.compression_enable);
5909         PIPE_CONF_CHECK_I(dsc.dsc_split);
5910         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5911
5912         PIPE_CONF_CHECK_BOOL(splitter.enable);
5913         PIPE_CONF_CHECK_I(splitter.link_count);
5914         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5915
5916         PIPE_CONF_CHECK_BOOL(vrr.enable);
5917         PIPE_CONF_CHECK_I(vrr.vmin);
5918         PIPE_CONF_CHECK_I(vrr.vmax);
5919         PIPE_CONF_CHECK_I(vrr.flipline);
5920         PIPE_CONF_CHECK_I(vrr.pipeline_full);
5921         PIPE_CONF_CHECK_I(vrr.guardband);
5922
5923 #undef PIPE_CONF_CHECK_X
5924 #undef PIPE_CONF_CHECK_I
5925 #undef PIPE_CONF_CHECK_BOOL
5926 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5927 #undef PIPE_CONF_CHECK_P
5928 #undef PIPE_CONF_CHECK_FLAGS
5929 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
5930 #undef PIPE_CONF_CHECK_COLOR_LUT
5931 #undef PIPE_CONF_CHECK_TIMINGS
5932 #undef PIPE_CONF_CHECK_RECT
5933 #undef PIPE_CONF_QUIRK
5934
5935         return ret;
5936 }
5937
5938 static void
5939 intel_verify_planes(struct intel_atomic_state *state)
5940 {
5941         struct intel_plane *plane;
5942         const struct intel_plane_state *plane_state;
5943         int i;
5944
5945         for_each_new_intel_plane_in_state(state, plane,
5946                                           plane_state, i)
5947                 assert_plane(plane, plane_state->planar_slave ||
5948                              plane_state->uapi.visible);
5949 }
5950
5951 int intel_modeset_all_pipes(struct intel_atomic_state *state)
5952 {
5953         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5954         struct intel_crtc *crtc;
5955
5956         /*
5957          * Add all pipes to the state, and force
5958          * a modeset on all the active ones.
5959          */
5960         for_each_intel_crtc(&dev_priv->drm, crtc) {
5961                 struct intel_crtc_state *crtc_state;
5962                 int ret;
5963
5964                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5965                 if (IS_ERR(crtc_state))
5966                         return PTR_ERR(crtc_state);
5967
5968                 if (!crtc_state->hw.active ||
5969                     drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
5970                         continue;
5971
5972                 crtc_state->uapi.mode_changed = true;
5973
5974                 ret = drm_atomic_add_affected_connectors(&state->base,
5975                                                          &crtc->base);
5976                 if (ret)
5977                         return ret;
5978
5979                 ret = intel_atomic_add_affected_planes(state, crtc);
5980                 if (ret)
5981                         return ret;
5982
5983                 crtc_state->update_planes |= crtc_state->active_planes;
5984         }
5985
5986         return 0;
5987 }
5988
5989 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
5990 {
5991         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5992         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5993         struct drm_display_mode adjusted_mode;
5994
5995         drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
5996
5997         if (crtc_state->vrr.enable) {
5998                 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
5999                 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
6000                 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
6001                 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
6002         }
6003
6004         drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
6005
6006         crtc->mode_flags = crtc_state->mode_flags;
6007
6008         /*
6009          * The scanline counter increments at the leading edge of hsync.
6010          *
6011          * On most platforms it starts counting from vtotal-1 on the
6012          * first active line. That means the scanline counter value is
6013          * always one less than what we would expect. Ie. just after
6014          * start of vblank, which also occurs at start of hsync (on the
6015          * last active line), the scanline counter will read vblank_start-1.
6016          *
6017          * On gen2 the scanline counter starts counting from 1 instead
6018          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
6019          * to keep the value positive), instead of adding one.
6020          *
6021          * On HSW+ the behaviour of the scanline counter depends on the output
6022          * type. For DP ports it behaves like most other platforms, but on HDMI
6023          * there's an extra 1 line difference. So we need to add two instead of
6024          * one to the value.
6025          *
6026          * On VLV/CHV DSI the scanline counter would appear to increment
6027          * approx. 1/3 of a scanline before start of vblank. Unfortunately
6028          * that means we can't tell whether we're in vblank or not while
6029          * we're on that particular line. We must still set scanline_offset
6030          * to 1 so that the vblank timestamps come out correct when we query
6031          * the scanline counter from within the vblank interrupt handler.
6032          * However if queried just before the start of vblank we'll get an
6033          * answer that's slightly in the future.
6034          */
6035         if (DISPLAY_VER(dev_priv) == 2) {
6036                 int vtotal;
6037
6038                 vtotal = adjusted_mode.crtc_vtotal;
6039                 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6040                         vtotal /= 2;
6041
6042                 crtc->scanline_offset = vtotal - 1;
6043         } else if (HAS_DDI(dev_priv) &&
6044                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
6045                 crtc->scanline_offset = 2;
6046         } else {
6047                 crtc->scanline_offset = 1;
6048         }
6049 }
6050
6051 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
6052 {
6053         struct intel_crtc_state *new_crtc_state;
6054         struct intel_crtc *crtc;
6055         int i;
6056
6057         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6058                 if (!intel_crtc_needs_modeset(new_crtc_state))
6059                         continue;
6060
6061                 intel_release_shared_dplls(state, crtc);
6062         }
6063 }
6064
6065 /*
6066  * This implements the workaround described in the "notes" section of the mode
6067  * set sequence documentation. When going from no pipes or single pipe to
6068  * multiple pipes, and planes are enabled after the pipe, we need to wait at
6069  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
6070  */
6071 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
6072 {
6073         struct intel_crtc_state *crtc_state;
6074         struct intel_crtc *crtc;
6075         struct intel_crtc_state *first_crtc_state = NULL;
6076         struct intel_crtc_state *other_crtc_state = NULL;
6077         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
6078         int i;
6079
6080         /* look at all crtc's that are going to be enabled in during modeset */
6081         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6082                 if (!crtc_state->hw.active ||
6083                     !intel_crtc_needs_modeset(crtc_state))
6084                         continue;
6085
6086                 if (first_crtc_state) {
6087                         other_crtc_state = crtc_state;
6088                         break;
6089                 } else {
6090                         first_crtc_state = crtc_state;
6091                         first_pipe = crtc->pipe;
6092                 }
6093         }
6094
6095         /* No workaround needed? */
6096         if (!first_crtc_state)
6097                 return 0;
6098
6099         /* w/a possibly needed, check how many crtc's are already enabled. */
6100         for_each_intel_crtc(state->base.dev, crtc) {
6101                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6102                 if (IS_ERR(crtc_state))
6103                         return PTR_ERR(crtc_state);
6104
6105                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
6106
6107                 if (!crtc_state->hw.active ||
6108                     intel_crtc_needs_modeset(crtc_state))
6109                         continue;
6110
6111                 /* 2 or more enabled crtcs means no need for w/a */
6112                 if (enabled_pipe != INVALID_PIPE)
6113                         return 0;
6114
6115                 enabled_pipe = crtc->pipe;
6116         }
6117
6118         if (enabled_pipe != INVALID_PIPE)
6119                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
6120         else if (other_crtc_state)
6121                 other_crtc_state->hsw_workaround_pipe = first_pipe;
6122
6123         return 0;
6124 }
6125
6126 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
6127                            u8 active_pipes)
6128 {
6129         const struct intel_crtc_state *crtc_state;
6130         struct intel_crtc *crtc;
6131         int i;
6132
6133         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6134                 if (crtc_state->hw.active)
6135                         active_pipes |= BIT(crtc->pipe);
6136                 else
6137                         active_pipes &= ~BIT(crtc->pipe);
6138         }
6139
6140         return active_pipes;
6141 }
6142
6143 static int intel_modeset_checks(struct intel_atomic_state *state)
6144 {
6145         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6146
6147         state->modeset = true;
6148
6149         if (IS_HASWELL(dev_priv))
6150                 return hsw_mode_set_planes_workaround(state);
6151
6152         return 0;
6153 }
6154
6155 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
6156                                      struct intel_crtc_state *new_crtc_state)
6157 {
6158         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
6159                 return;
6160
6161         new_crtc_state->uapi.mode_changed = false;
6162         new_crtc_state->update_pipe = true;
6163 }
6164
6165 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
6166                                     struct intel_crtc_state *new_crtc_state)
6167 {
6168         /*
6169          * If we're not doing the full modeset we want to
6170          * keep the current M/N values as they may be
6171          * sufficiently different to the computed values
6172          * to cause problems.
6173          *
6174          * FIXME: should really copy more fuzzy state here
6175          */
6176         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
6177         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
6178         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
6179         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
6180 }
6181
6182 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
6183                                           struct intel_crtc *crtc,
6184                                           u8 plane_ids_mask)
6185 {
6186         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6187         struct intel_plane *plane;
6188
6189         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6190                 struct intel_plane_state *plane_state;
6191
6192                 if ((plane_ids_mask & BIT(plane->id)) == 0)
6193                         continue;
6194
6195                 plane_state = intel_atomic_get_plane_state(state, plane);
6196                 if (IS_ERR(plane_state))
6197                         return PTR_ERR(plane_state);
6198         }
6199
6200         return 0;
6201 }
6202
6203 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
6204                                      struct intel_crtc *crtc)
6205 {
6206         const struct intel_crtc_state *old_crtc_state =
6207                 intel_atomic_get_old_crtc_state(state, crtc);
6208         const struct intel_crtc_state *new_crtc_state =
6209                 intel_atomic_get_new_crtc_state(state, crtc);
6210
6211         return intel_crtc_add_planes_to_state(state, crtc,
6212                                               old_crtc_state->enabled_planes |
6213                                               new_crtc_state->enabled_planes);
6214 }
6215
6216 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
6217 {
6218         /* See {hsw,vlv,ivb}_plane_ratio() */
6219         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
6220                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6221                 IS_IVYBRIDGE(dev_priv);
6222 }
6223
6224 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
6225                                            struct intel_crtc *crtc,
6226                                            struct intel_crtc *other)
6227 {
6228         const struct intel_plane_state *plane_state;
6229         struct intel_plane *plane;
6230         u8 plane_ids = 0;
6231         int i;
6232
6233         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6234                 if (plane->pipe == crtc->pipe)
6235                         plane_ids |= BIT(plane->id);
6236         }
6237
6238         return intel_crtc_add_planes_to_state(state, other, plane_ids);
6239 }
6240
6241 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
6242 {
6243         struct drm_i915_private *i915 = to_i915(state->base.dev);
6244         const struct intel_crtc_state *crtc_state;
6245         struct intel_crtc *crtc;
6246         int i;
6247
6248         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6249                 struct intel_crtc *other;
6250
6251                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6252                                                  crtc_state->bigjoiner_pipes) {
6253                         int ret;
6254
6255                         if (crtc == other)
6256                                 continue;
6257
6258                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
6259                         if (ret)
6260                                 return ret;
6261                 }
6262         }
6263
6264         return 0;
6265 }
6266
6267 static int intel_atomic_check_planes(struct intel_atomic_state *state)
6268 {
6269         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6270         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6271         struct intel_plane_state *plane_state;
6272         struct intel_plane *plane;
6273         struct intel_crtc *crtc;
6274         int i, ret;
6275
6276         ret = icl_add_linked_planes(state);
6277         if (ret)
6278                 return ret;
6279
6280         ret = intel_bigjoiner_add_affected_planes(state);
6281         if (ret)
6282                 return ret;
6283
6284         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6285                 ret = intel_plane_atomic_check(state, plane);
6286                 if (ret) {
6287                         drm_dbg_atomic(&dev_priv->drm,
6288                                        "[PLANE:%d:%s] atomic driver check failed\n",
6289                                        plane->base.base.id, plane->base.name);
6290                         return ret;
6291                 }
6292         }
6293
6294         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6295                                             new_crtc_state, i) {
6296                 u8 old_active_planes, new_active_planes;
6297
6298                 ret = icl_check_nv12_planes(new_crtc_state);
6299                 if (ret)
6300                         return ret;
6301
6302                 /*
6303                  * On some platforms the number of active planes affects
6304                  * the planes' minimum cdclk calculation. Add such planes
6305                  * to the state before we compute the minimum cdclk.
6306                  */
6307                 if (!active_planes_affects_min_cdclk(dev_priv))
6308                         continue;
6309
6310                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6311                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6312
6313                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
6314                         continue;
6315
6316                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6317                 if (ret)
6318                         return ret;
6319         }
6320
6321         return 0;
6322 }
6323
6324 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6325 {
6326         struct intel_crtc_state *crtc_state;
6327         struct intel_crtc *crtc;
6328         int i;
6329
6330         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6331                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6332                 int ret;
6333
6334                 ret = intel_crtc_atomic_check(state, crtc);
6335                 if (ret) {
6336                         drm_dbg_atomic(&i915->drm,
6337                                        "[CRTC:%d:%s] atomic driver check failed\n",
6338                                        crtc->base.base.id, crtc->base.name);
6339                         return ret;
6340                 }
6341         }
6342
6343         return 0;
6344 }
6345
6346 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6347                                                u8 transcoders)
6348 {
6349         const struct intel_crtc_state *new_crtc_state;
6350         struct intel_crtc *crtc;
6351         int i;
6352
6353         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6354                 if (new_crtc_state->hw.enable &&
6355                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6356                     intel_crtc_needs_modeset(new_crtc_state))
6357                         return true;
6358         }
6359
6360         return false;
6361 }
6362
6363 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6364                                      u8 pipes)
6365 {
6366         const struct intel_crtc_state *new_crtc_state;
6367         struct intel_crtc *crtc;
6368         int i;
6369
6370         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6371                 if (new_crtc_state->hw.enable &&
6372                     pipes & BIT(crtc->pipe) &&
6373                     intel_crtc_needs_modeset(new_crtc_state))
6374                         return true;
6375         }
6376
6377         return false;
6378 }
6379
6380 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
6381                                         struct intel_crtc *master_crtc)
6382 {
6383         struct drm_i915_private *i915 = to_i915(state->base.dev);
6384         struct intel_crtc_state *master_crtc_state =
6385                 intel_atomic_get_new_crtc_state(state, master_crtc);
6386         struct intel_crtc *slave_crtc;
6387
6388         if (!master_crtc_state->bigjoiner_pipes)
6389                 return 0;
6390
6391         /* sanity check */
6392         if (drm_WARN_ON(&i915->drm,
6393                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
6394                 return -EINVAL;
6395
6396         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
6397                 drm_dbg_kms(&i915->drm,
6398                             "[CRTC:%d:%s] Cannot act as big joiner master "
6399                             "(need 0x%x as pipes, only 0x%x possible)\n",
6400                             master_crtc->base.base.id, master_crtc->base.name,
6401                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
6402                 return -EINVAL;
6403         }
6404
6405         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6406                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6407                 struct intel_crtc_state *slave_crtc_state;
6408                 int ret;
6409
6410                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
6411                 if (IS_ERR(slave_crtc_state))
6412                         return PTR_ERR(slave_crtc_state);
6413
6414                 /* master being enabled, slave was already configured? */
6415                 if (slave_crtc_state->uapi.enable) {
6416                         drm_dbg_kms(&i915->drm,
6417                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
6418                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
6419                                     slave_crtc->base.base.id, slave_crtc->base.name,
6420                                     master_crtc->base.base.id, master_crtc->base.name);
6421                         return -EINVAL;
6422                 }
6423
6424                 /*
6425                  * The state copy logic assumes the master crtc gets processed
6426                  * before the slave crtc during the main compute_config loop.
6427                  * This works because the crtcs are created in pipe order,
6428                  * and the hardware requires master pipe < slave pipe as well.
6429                  * Should that change we need to rethink the logic.
6430                  */
6431                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
6432                             drm_crtc_index(&slave_crtc->base)))
6433                         return -EINVAL;
6434
6435                 drm_dbg_kms(&i915->drm,
6436                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
6437                             slave_crtc->base.base.id, slave_crtc->base.name,
6438                             master_crtc->base.base.id, master_crtc->base.name);
6439
6440                 slave_crtc_state->bigjoiner_pipes =
6441                         master_crtc_state->bigjoiner_pipes;
6442
6443                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
6444                 if (ret)
6445                         return ret;
6446         }
6447
6448         return 0;
6449 }
6450
6451 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
6452                                  struct intel_crtc *master_crtc)
6453 {
6454         struct drm_i915_private *i915 = to_i915(state->base.dev);
6455         struct intel_crtc_state *master_crtc_state =
6456                 intel_atomic_get_new_crtc_state(state, master_crtc);
6457         struct intel_crtc *slave_crtc;
6458
6459         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6460                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6461                 struct intel_crtc_state *slave_crtc_state =
6462                         intel_atomic_get_new_crtc_state(state, slave_crtc);
6463
6464                 slave_crtc_state->bigjoiner_pipes = 0;
6465
6466                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
6467         }
6468
6469         master_crtc_state->bigjoiner_pipes = 0;
6470 }
6471
6472 /**
6473  * DOC: asynchronous flip implementation
6474  *
6475  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6476  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6477  * Correspondingly, support is currently added for primary plane only.
6478  *
6479  * Async flip can only change the plane surface address, so anything else
6480  * changing is rejected from the intel_async_flip_check_hw() function.
6481  * Once this check is cleared, flip done interrupt is enabled using
6482  * the intel_crtc_enable_flip_done() function.
6483  *
6484  * As soon as the surface address register is written, flip done interrupt is
6485  * generated and the requested events are sent to the usersapce in the interrupt
6486  * handler itself. The timestamp and sequence sent during the flip done event
6487  * correspond to the last vblank and have no relation to the actual time when
6488  * the flip done event was sent.
6489  */
6490 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6491                                        struct intel_crtc *crtc)
6492 {
6493         struct drm_i915_private *i915 = to_i915(state->base.dev);
6494         const struct intel_crtc_state *new_crtc_state =
6495                 intel_atomic_get_new_crtc_state(state, crtc);
6496         const struct intel_plane_state *old_plane_state;
6497         struct intel_plane_state *new_plane_state;
6498         struct intel_plane *plane;
6499         int i;
6500
6501         if (!new_crtc_state->uapi.async_flip)
6502                 return 0;
6503
6504         if (!new_crtc_state->uapi.active) {
6505                 drm_dbg_kms(&i915->drm,
6506                             "[CRTC:%d:%s] not active\n",
6507                             crtc->base.base.id, crtc->base.name);
6508                 return -EINVAL;
6509         }
6510
6511         if (intel_crtc_needs_modeset(new_crtc_state)) {
6512                 drm_dbg_kms(&i915->drm,
6513                             "[CRTC:%d:%s] modeset required\n",
6514                             crtc->base.base.id, crtc->base.name);
6515                 return -EINVAL;
6516         }
6517
6518         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6519                                              new_plane_state, i) {
6520                 if (plane->pipe != crtc->pipe)
6521                         continue;
6522
6523                 /*
6524                  * TODO: Async flip is only supported through the page flip IOCTL
6525                  * as of now. So support currently added for primary plane only.
6526                  * Support for other planes on platforms on which supports
6527                  * this(vlv/chv and icl+) should be added when async flip is
6528                  * enabled in the atomic IOCTL path.
6529                  */
6530                 if (!plane->async_flip) {
6531                         drm_dbg_kms(&i915->drm,
6532                                     "[PLANE:%d:%s] async flip not supported\n",
6533                                     plane->base.base.id, plane->base.name);
6534                         return -EINVAL;
6535                 }
6536
6537                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6538                         drm_dbg_kms(&i915->drm,
6539                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6540                                     plane->base.base.id, plane->base.name);
6541                         return -EINVAL;
6542                 }
6543         }
6544
6545         return 0;
6546 }
6547
6548 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6549 {
6550         struct drm_i915_private *i915 = to_i915(state->base.dev);
6551         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6552         const struct intel_plane_state *new_plane_state, *old_plane_state;
6553         struct intel_plane *plane;
6554         int i;
6555
6556         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6557         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6558
6559         if (!new_crtc_state->uapi.async_flip)
6560                 return 0;
6561
6562         if (!new_crtc_state->hw.active) {
6563                 drm_dbg_kms(&i915->drm,
6564                             "[CRTC:%d:%s] not active\n",
6565                             crtc->base.base.id, crtc->base.name);
6566                 return -EINVAL;
6567         }
6568
6569         if (intel_crtc_needs_modeset(new_crtc_state)) {
6570                 drm_dbg_kms(&i915->drm,
6571                             "[CRTC:%d:%s] modeset required\n",
6572                             crtc->base.base.id, crtc->base.name);
6573                 return -EINVAL;
6574         }
6575
6576         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6577                 drm_dbg_kms(&i915->drm,
6578                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6579                             crtc->base.base.id, crtc->base.name);
6580                 return -EINVAL;
6581         }
6582
6583         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6584                                              new_plane_state, i) {
6585                 if (plane->pipe != crtc->pipe)
6586                         continue;
6587
6588                 /*
6589                  * Only async flip capable planes should be in the state
6590                  * if we're really about to ask the hardware to perform
6591                  * an async flip. We should never get this far otherwise.
6592                  */
6593                 if (drm_WARN_ON(&i915->drm,
6594                                 new_crtc_state->do_async_flip && !plane->async_flip))
6595                         return -EINVAL;
6596
6597                 /*
6598                  * Only check async flip capable planes other planes
6599                  * may be involved in the initial commit due to
6600                  * the wm0/ddb optimization.
6601                  *
6602                  * TODO maybe should track which planes actually
6603                  * were requested to do the async flip...
6604                  */
6605                 if (!plane->async_flip)
6606                         continue;
6607
6608                 /*
6609                  * FIXME: This check is kept generic for all platforms.
6610                  * Need to verify this for all gen9 platforms to enable
6611                  * this selectively if required.
6612                  */
6613                 switch (new_plane_state->hw.fb->modifier) {
6614                 case I915_FORMAT_MOD_X_TILED:
6615                 case I915_FORMAT_MOD_Y_TILED:
6616                 case I915_FORMAT_MOD_Yf_TILED:
6617                 case I915_FORMAT_MOD_4_TILED:
6618                         break;
6619                 default:
6620                         drm_dbg_kms(&i915->drm,
6621                                     "[PLANE:%d:%s] Modifier does not support async flips\n",
6622                                     plane->base.base.id, plane->base.name);
6623                         return -EINVAL;
6624                 }
6625
6626                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6627                         drm_dbg_kms(&i915->drm,
6628                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6629                                     plane->base.base.id, plane->base.name);
6630                         return -EINVAL;
6631                 }
6632
6633                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6634                     new_plane_state->view.color_plane[0].mapping_stride) {
6635                         drm_dbg_kms(&i915->drm,
6636                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6637                                     plane->base.base.id, plane->base.name);
6638                         return -EINVAL;
6639                 }
6640
6641                 if (old_plane_state->hw.fb->modifier !=
6642                     new_plane_state->hw.fb->modifier) {
6643                         drm_dbg_kms(&i915->drm,
6644                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6645                                     plane->base.base.id, plane->base.name);
6646                         return -EINVAL;
6647                 }
6648
6649                 if (old_plane_state->hw.fb->format !=
6650                     new_plane_state->hw.fb->format) {
6651                         drm_dbg_kms(&i915->drm,
6652                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6653                                     plane->base.base.id, plane->base.name);
6654                         return -EINVAL;
6655                 }
6656
6657                 if (old_plane_state->hw.rotation !=
6658                     new_plane_state->hw.rotation) {
6659                         drm_dbg_kms(&i915->drm,
6660                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6661                                     plane->base.base.id, plane->base.name);
6662                         return -EINVAL;
6663                 }
6664
6665                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6666                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6667                         drm_dbg_kms(&i915->drm,
6668                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6669                                     plane->base.base.id, plane->base.name);
6670                         return -EINVAL;
6671                 }
6672
6673                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6674                         drm_dbg_kms(&i915->drm,
6675                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6676                                     plane->base.base.id, plane->base.name);
6677                         return -EINVAL;
6678                 }
6679
6680                 if (old_plane_state->hw.pixel_blend_mode !=
6681                     new_plane_state->hw.pixel_blend_mode) {
6682                         drm_dbg_kms(&i915->drm,
6683                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6684                                     plane->base.base.id, plane->base.name);
6685                         return -EINVAL;
6686                 }
6687
6688                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6689                         drm_dbg_kms(&i915->drm,
6690                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6691                                     plane->base.base.id, plane->base.name);
6692                         return -EINVAL;
6693                 }
6694
6695                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6696                         drm_dbg_kms(&i915->drm,
6697                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6698                                     plane->base.base.id, plane->base.name);
6699                         return -EINVAL;
6700                 }
6701
6702                 /* plane decryption is allow to change only in synchronous flips */
6703                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6704                         drm_dbg_kms(&i915->drm,
6705                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6706                                     plane->base.base.id, plane->base.name);
6707                         return -EINVAL;
6708                 }
6709         }
6710
6711         return 0;
6712 }
6713
6714 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6715 {
6716         struct drm_i915_private *i915 = to_i915(state->base.dev);
6717         struct intel_crtc_state *crtc_state;
6718         struct intel_crtc *crtc;
6719         u8 affected_pipes = 0;
6720         u8 modeset_pipes = 0;
6721         int i;
6722
6723         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6724                 affected_pipes |= crtc_state->bigjoiner_pipes;
6725                 if (intel_crtc_needs_modeset(crtc_state))
6726                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6727         }
6728
6729         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6730                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6731                 if (IS_ERR(crtc_state))
6732                         return PTR_ERR(crtc_state);
6733         }
6734
6735         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6736                 int ret;
6737
6738                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6739
6740                 crtc_state->uapi.mode_changed = true;
6741
6742                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6743                 if (ret)
6744                         return ret;
6745
6746                 ret = intel_atomic_add_affected_planes(state, crtc);
6747                 if (ret)
6748                         return ret;
6749         }
6750
6751         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6752                 /* Kill old bigjoiner link, we may re-establish afterwards */
6753                 if (intel_crtc_needs_modeset(crtc_state) &&
6754                     intel_crtc_is_bigjoiner_master(crtc_state))
6755                         kill_bigjoiner_slave(state, crtc);
6756         }
6757
6758         return 0;
6759 }
6760
6761 /**
6762  * intel_atomic_check - validate state object
6763  * @dev: drm device
6764  * @_state: state to validate
6765  */
6766 static int intel_atomic_check(struct drm_device *dev,
6767                               struct drm_atomic_state *_state)
6768 {
6769         struct drm_i915_private *dev_priv = to_i915(dev);
6770         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6771         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6772         struct intel_crtc *crtc;
6773         int ret, i;
6774         bool any_ms = false;
6775
6776         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6777                                             new_crtc_state, i) {
6778                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6779                         new_crtc_state->uapi.mode_changed = true;
6780
6781                 if (new_crtc_state->uapi.scaling_filter !=
6782                     old_crtc_state->uapi.scaling_filter)
6783                         new_crtc_state->uapi.mode_changed = true;
6784         }
6785
6786         intel_vrr_check_modeset(state);
6787
6788         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6789         if (ret)
6790                 goto fail;
6791
6792         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6793                 ret = intel_async_flip_check_uapi(state, crtc);
6794                 if (ret)
6795                         return ret;
6796         }
6797
6798         ret = intel_bigjoiner_add_affected_crtcs(state);
6799         if (ret)
6800                 goto fail;
6801
6802         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6803                                             new_crtc_state, i) {
6804                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6805                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6806                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6807                         else
6808                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6809                         continue;
6810                 }
6811
6812                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6813                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6814                         continue;
6815                 }
6816
6817                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6818                 if (ret)
6819                         goto fail;
6820
6821                 if (!new_crtc_state->hw.enable)
6822                         continue;
6823
6824                 ret = intel_modeset_pipe_config(state, crtc);
6825                 if (ret)
6826                         goto fail;
6827
6828                 ret = intel_atomic_check_bigjoiner(state, crtc);
6829                 if (ret)
6830                         goto fail;
6831         }
6832
6833         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6834                                             new_crtc_state, i) {
6835                 if (!intel_crtc_needs_modeset(new_crtc_state))
6836                         continue;
6837
6838                 ret = intel_modeset_pipe_config_late(state, crtc);
6839                 if (ret)
6840                         goto fail;
6841
6842                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6843         }
6844
6845         /**
6846          * Check if fastset is allowed by external dependencies like other
6847          * pipes and transcoders.
6848          *
6849          * Right now it only forces a fullmodeset when the MST master
6850          * transcoder did not changed but the pipe of the master transcoder
6851          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6852          * in case of port synced crtcs, if one of the synced crtcs
6853          * needs a full modeset, all other synced crtcs should be
6854          * forced a full modeset.
6855          */
6856         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6857                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6858                         continue;
6859
6860                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6861                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6862
6863                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6864                                 new_crtc_state->uapi.mode_changed = true;
6865                                 new_crtc_state->update_pipe = false;
6866                         }
6867                 }
6868
6869                 if (is_trans_port_sync_mode(new_crtc_state)) {
6870                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6871
6872                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6873                                 trans |= BIT(new_crtc_state->master_transcoder);
6874
6875                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6876                                 new_crtc_state->uapi.mode_changed = true;
6877                                 new_crtc_state->update_pipe = false;
6878                         }
6879                 }
6880
6881                 if (new_crtc_state->bigjoiner_pipes) {
6882                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6883                                 new_crtc_state->uapi.mode_changed = true;
6884                                 new_crtc_state->update_pipe = false;
6885                         }
6886                 }
6887         }
6888
6889         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6890                                             new_crtc_state, i) {
6891                 if (intel_crtc_needs_modeset(new_crtc_state)) {
6892                         any_ms = true;
6893                         continue;
6894                 }
6895
6896                 if (!new_crtc_state->update_pipe)
6897                         continue;
6898
6899                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
6900         }
6901
6902         if (any_ms && !check_digital_port_conflicts(state)) {
6903                 drm_dbg_kms(&dev_priv->drm,
6904                             "rejecting conflicting digital port configuration\n");
6905                 ret = -EINVAL;
6906                 goto fail;
6907         }
6908
6909         ret = drm_dp_mst_atomic_check(&state->base);
6910         if (ret)
6911                 goto fail;
6912
6913         ret = intel_atomic_check_planes(state);
6914         if (ret)
6915                 goto fail;
6916
6917         ret = intel_compute_global_watermarks(state);
6918         if (ret)
6919                 goto fail;
6920
6921         ret = intel_bw_atomic_check(state);
6922         if (ret)
6923                 goto fail;
6924
6925         ret = intel_cdclk_atomic_check(state, &any_ms);
6926         if (ret)
6927                 goto fail;
6928
6929         if (intel_any_crtc_needs_modeset(state))
6930                 any_ms = true;
6931
6932         if (any_ms) {
6933                 ret = intel_modeset_checks(state);
6934                 if (ret)
6935                         goto fail;
6936
6937                 ret = intel_modeset_calc_cdclk(state);
6938                 if (ret)
6939                         return ret;
6940
6941                 intel_modeset_clear_plls(state);
6942         }
6943
6944         ret = intel_atomic_check_crtcs(state);
6945         if (ret)
6946                 goto fail;
6947
6948         ret = intel_fbc_atomic_check(state);
6949         if (ret)
6950                 goto fail;
6951
6952         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6953                                             new_crtc_state, i) {
6954                 ret = intel_async_flip_check_hw(state, crtc);
6955                 if (ret)
6956                         goto fail;
6957
6958                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6959                     !new_crtc_state->update_pipe)
6960                         continue;
6961
6962                 intel_crtc_state_dump(new_crtc_state, state,
6963                                       intel_crtc_needs_modeset(new_crtc_state) ?
6964                                       "modeset" : "fastset");
6965         }
6966
6967         return 0;
6968
6969  fail:
6970         if (ret == -EDEADLK)
6971                 return ret;
6972
6973         /*
6974          * FIXME would probably be nice to know which crtc specifically
6975          * caused the failure, in cases where we can pinpoint it.
6976          */
6977         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6978                                             new_crtc_state, i)
6979                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6980
6981         return ret;
6982 }
6983
6984 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6985 {
6986         struct intel_crtc_state *crtc_state;
6987         struct intel_crtc *crtc;
6988         int i, ret;
6989
6990         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6991         if (ret < 0)
6992                 return ret;
6993
6994         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6995                 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6996
6997                 if (mode_changed || crtc_state->update_pipe ||
6998                     crtc_state->uapi.color_mgmt_changed) {
6999                         intel_dsb_prepare(crtc_state);
7000                 }
7001         }
7002
7003         return 0;
7004 }
7005
7006 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
7007                                   struct intel_crtc_state *crtc_state)
7008 {
7009         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7010
7011         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
7012                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7013
7014         if (crtc_state->has_pch_encoder) {
7015                 enum pipe pch_transcoder =
7016                         intel_crtc_pch_transcoder(crtc);
7017
7018                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
7019         }
7020 }
7021
7022 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
7023                                const struct intel_crtc_state *new_crtc_state)
7024 {
7025         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7026         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7027
7028         /*
7029          * Update pipe size and adjust fitter if needed: the reason for this is
7030          * that in compute_mode_changes we check the native mode (not the pfit
7031          * mode) to see if we can flip rather than do a full mode set. In the
7032          * fastboot case, we'll flip, but if we don't update the pipesrc and
7033          * pfit state, we'll end up with a big fb scanned out into the wrong
7034          * sized surface.
7035          */
7036         intel_set_pipe_src_size(new_crtc_state);
7037
7038         /* on skylake this is done by detaching scalers */
7039         if (DISPLAY_VER(dev_priv) >= 9) {
7040                 if (new_crtc_state->pch_pfit.enabled)
7041                         skl_pfit_enable(new_crtc_state);
7042         } else if (HAS_PCH_SPLIT(dev_priv)) {
7043                 if (new_crtc_state->pch_pfit.enabled)
7044                         ilk_pfit_enable(new_crtc_state);
7045                 else if (old_crtc_state->pch_pfit.enabled)
7046                         ilk_pfit_disable(old_crtc_state);
7047         }
7048
7049         /*
7050          * The register is supposedly single buffered so perhaps
7051          * not 100% correct to do this here. But SKL+ calculate
7052          * this based on the adjust pixel rate so pfit changes do
7053          * affect it and so it must be updated for fastsets.
7054          * HSW/BDW only really need this here for fastboot, after
7055          * that the value should not change without a full modeset.
7056          */
7057         if (DISPLAY_VER(dev_priv) >= 9 ||
7058             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7059                 hsw_set_linetime_wm(new_crtc_state);
7060 }
7061
7062 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
7063                                    struct intel_crtc *crtc)
7064 {
7065         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7066         const struct intel_crtc_state *old_crtc_state =
7067                 intel_atomic_get_old_crtc_state(state, crtc);
7068         const struct intel_crtc_state *new_crtc_state =
7069                 intel_atomic_get_new_crtc_state(state, crtc);
7070         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7071
7072         /*
7073          * During modesets pipe configuration was programmed as the
7074          * CRTC was enabled.
7075          */
7076         if (!modeset) {
7077                 if (new_crtc_state->uapi.color_mgmt_changed ||
7078                     new_crtc_state->update_pipe)
7079                         intel_color_commit_arm(new_crtc_state);
7080
7081                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7082                         bdw_set_pipemisc(new_crtc_state);
7083
7084                 if (new_crtc_state->update_pipe)
7085                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
7086         }
7087
7088         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
7089
7090         intel_atomic_update_watermarks(state, crtc);
7091 }
7092
7093 static void commit_pipe_post_planes(struct intel_atomic_state *state,
7094                                     struct intel_crtc *crtc)
7095 {
7096         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7097         const struct intel_crtc_state *new_crtc_state =
7098                 intel_atomic_get_new_crtc_state(state, crtc);
7099
7100         /*
7101          * Disable the scaler(s) after the plane(s) so that we don't
7102          * get a catastrophic underrun even if the two operations
7103          * end up happening in two different frames.
7104          */
7105         if (DISPLAY_VER(dev_priv) >= 9 &&
7106             !intel_crtc_needs_modeset(new_crtc_state))
7107                 skl_detach_scalers(new_crtc_state);
7108 }
7109
7110 static void intel_enable_crtc(struct intel_atomic_state *state,
7111                               struct intel_crtc *crtc)
7112 {
7113         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7114         const struct intel_crtc_state *new_crtc_state =
7115                 intel_atomic_get_new_crtc_state(state, crtc);
7116
7117         if (!intel_crtc_needs_modeset(new_crtc_state))
7118                 return;
7119
7120         intel_crtc_update_active_timings(new_crtc_state);
7121
7122         dev_priv->display.funcs.display->crtc_enable(state, crtc);
7123
7124         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
7125                 return;
7126
7127         /* vblanks work again, re-enable pipe CRC. */
7128         intel_crtc_enable_pipe_crc(crtc);
7129 }
7130
7131 static void intel_update_crtc(struct intel_atomic_state *state,
7132                               struct intel_crtc *crtc)
7133 {
7134         struct drm_i915_private *i915 = to_i915(state->base.dev);
7135         const struct intel_crtc_state *old_crtc_state =
7136                 intel_atomic_get_old_crtc_state(state, crtc);
7137         struct intel_crtc_state *new_crtc_state =
7138                 intel_atomic_get_new_crtc_state(state, crtc);
7139         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7140
7141         if (!modeset) {
7142                 if (new_crtc_state->preload_luts &&
7143                     (new_crtc_state->uapi.color_mgmt_changed ||
7144                      new_crtc_state->update_pipe))
7145                         intel_color_load_luts(new_crtc_state);
7146
7147                 intel_pre_plane_update(state, crtc);
7148
7149                 if (new_crtc_state->update_pipe)
7150                         intel_encoders_update_pipe(state, crtc);
7151
7152                 if (DISPLAY_VER(i915) >= 11 &&
7153                     new_crtc_state->update_pipe)
7154                         icl_set_pipe_chicken(new_crtc_state);
7155         }
7156
7157         intel_fbc_update(state, crtc);
7158
7159         if (!modeset &&
7160             (new_crtc_state->uapi.color_mgmt_changed ||
7161              new_crtc_state->update_pipe))
7162                 intel_color_commit_noarm(new_crtc_state);
7163
7164         intel_crtc_planes_update_noarm(state, crtc);
7165
7166         /* Perform vblank evasion around commit operation */
7167         intel_pipe_update_start(new_crtc_state);
7168
7169         commit_pipe_pre_planes(state, crtc);
7170
7171         intel_crtc_planes_update_arm(state, crtc);
7172
7173         commit_pipe_post_planes(state, crtc);
7174
7175         intel_pipe_update_end(new_crtc_state);
7176
7177         /*
7178          * We usually enable FIFO underrun interrupts as part of the
7179          * CRTC enable sequence during modesets.  But when we inherit a
7180          * valid pipe configuration from the BIOS we need to take care
7181          * of enabling them on the CRTC's first fastset.
7182          */
7183         if (new_crtc_state->update_pipe && !modeset &&
7184             old_crtc_state->inherited)
7185                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
7186 }
7187
7188 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
7189                                           struct intel_crtc_state *old_crtc_state,
7190                                           struct intel_crtc_state *new_crtc_state,
7191                                           struct intel_crtc *crtc)
7192 {
7193         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7194
7195         /*
7196          * We need to disable pipe CRC before disabling the pipe,
7197          * or we race against vblank off.
7198          */
7199         intel_crtc_disable_pipe_crc(crtc);
7200
7201         dev_priv->display.funcs.display->crtc_disable(state, crtc);
7202         crtc->active = false;
7203         intel_fbc_disable(crtc);
7204         intel_disable_shared_dpll(old_crtc_state);
7205
7206         /* FIXME unify this for all platforms */
7207         if (!new_crtc_state->hw.active &&
7208             !HAS_GMCH(dev_priv))
7209                 intel_initial_watermarks(state, crtc);
7210 }
7211
7212 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
7213 {
7214         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7215         struct intel_crtc *crtc;
7216         u32 handled = 0;
7217         int i;
7218
7219         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7220                                             new_crtc_state, i) {
7221                 if (!intel_crtc_needs_modeset(new_crtc_state))
7222                         continue;
7223
7224                 if (!old_crtc_state->hw.active)
7225                         continue;
7226
7227                 intel_pre_plane_update(state, crtc);
7228                 intel_crtc_disable_planes(state, crtc);
7229         }
7230
7231         /* Only disable port sync and MST slaves */
7232         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7233                                             new_crtc_state, i) {
7234                 if (!intel_crtc_needs_modeset(new_crtc_state))
7235                         continue;
7236
7237                 if (!old_crtc_state->hw.active)
7238                         continue;
7239
7240                 /* In case of Transcoder port Sync master slave CRTCs can be
7241                  * assigned in any order and we need to make sure that
7242                  * slave CRTCs are disabled first and then master CRTC since
7243                  * Slave vblanks are masked till Master Vblanks.
7244                  */
7245                 if (!is_trans_port_sync_slave(old_crtc_state) &&
7246                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
7247                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
7248                         continue;
7249
7250                 intel_old_crtc_state_disables(state, old_crtc_state,
7251                                               new_crtc_state, crtc);
7252                 handled |= BIT(crtc->pipe);
7253         }
7254
7255         /* Disable everything else left on */
7256         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7257                                             new_crtc_state, i) {
7258                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
7259                     (handled & BIT(crtc->pipe)))
7260                         continue;
7261
7262                 if (!old_crtc_state->hw.active)
7263                         continue;
7264
7265                 intel_old_crtc_state_disables(state, old_crtc_state,
7266                                               new_crtc_state, crtc);
7267         }
7268 }
7269
7270 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7271 {
7272         struct intel_crtc_state *new_crtc_state;
7273         struct intel_crtc *crtc;
7274         int i;
7275
7276         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7277                 if (!new_crtc_state->hw.active)
7278                         continue;
7279
7280                 intel_enable_crtc(state, crtc);
7281                 intel_update_crtc(state, crtc);
7282         }
7283 }
7284
7285 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7286 {
7287         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7288         struct intel_crtc *crtc;
7289         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7290         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7291         u8 update_pipes = 0, modeset_pipes = 0;
7292         int i;
7293
7294         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7295                 enum pipe pipe = crtc->pipe;
7296
7297                 if (!new_crtc_state->hw.active)
7298                         continue;
7299
7300                 /* ignore allocations for crtc's that have been turned off. */
7301                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
7302                         entries[pipe] = old_crtc_state->wm.skl.ddb;
7303                         update_pipes |= BIT(pipe);
7304                 } else {
7305                         modeset_pipes |= BIT(pipe);
7306                 }
7307         }
7308
7309         /*
7310          * Whenever the number of active pipes changes, we need to make sure we
7311          * update the pipes in the right order so that their ddb allocations
7312          * never overlap with each other between CRTC updates. Otherwise we'll
7313          * cause pipe underruns and other bad stuff.
7314          *
7315          * So first lets enable all pipes that do not need a fullmodeset as
7316          * those don't have any external dependency.
7317          */
7318         while (update_pipes) {
7319                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7320                                                     new_crtc_state, i) {
7321                         enum pipe pipe = crtc->pipe;
7322
7323                         if ((update_pipes & BIT(pipe)) == 0)
7324                                 continue;
7325
7326                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7327                                                         entries, I915_MAX_PIPES, pipe))
7328                                 continue;
7329
7330                         entries[pipe] = new_crtc_state->wm.skl.ddb;
7331                         update_pipes &= ~BIT(pipe);
7332
7333                         intel_update_crtc(state, crtc);
7334
7335                         /*
7336                          * If this is an already active pipe, it's DDB changed,
7337                          * and this isn't the last pipe that needs updating
7338                          * then we need to wait for a vblank to pass for the
7339                          * new ddb allocation to take effect.
7340                          */
7341                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7342                                                  &old_crtc_state->wm.skl.ddb) &&
7343                             (update_pipes | modeset_pipes))
7344                                 intel_crtc_wait_for_next_vblank(crtc);
7345                 }
7346         }
7347
7348         update_pipes = modeset_pipes;
7349
7350         /*
7351          * Enable all pipes that needs a modeset and do not depends on other
7352          * pipes
7353          */
7354         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7355                 enum pipe pipe = crtc->pipe;
7356
7357                 if ((modeset_pipes & BIT(pipe)) == 0)
7358                         continue;
7359
7360                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7361                     is_trans_port_sync_master(new_crtc_state) ||
7362                     intel_crtc_is_bigjoiner_master(new_crtc_state))
7363                         continue;
7364
7365                 modeset_pipes &= ~BIT(pipe);
7366
7367                 intel_enable_crtc(state, crtc);
7368         }
7369
7370         /*
7371          * Then we enable all remaining pipes that depend on other
7372          * pipes: MST slaves and port sync masters, big joiner master
7373          */
7374         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7375                 enum pipe pipe = crtc->pipe;
7376
7377                 if ((modeset_pipes & BIT(pipe)) == 0)
7378                         continue;
7379
7380                 modeset_pipes &= ~BIT(pipe);
7381
7382                 intel_enable_crtc(state, crtc);
7383         }
7384
7385         /*
7386          * Finally we do the plane updates/etc. for all pipes that got enabled.
7387          */
7388         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7389                 enum pipe pipe = crtc->pipe;
7390
7391                 if ((update_pipes & BIT(pipe)) == 0)
7392                         continue;
7393
7394                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7395                                                                         entries, I915_MAX_PIPES, pipe));
7396
7397                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7398                 update_pipes &= ~BIT(pipe);
7399
7400                 intel_update_crtc(state, crtc);
7401         }
7402
7403         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7404         drm_WARN_ON(&dev_priv->drm, update_pipes);
7405 }
7406
7407 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7408 {
7409         struct intel_atomic_state *state, *next;
7410         struct llist_node *freed;
7411
7412         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
7413         llist_for_each_entry_safe(state, next, freed, freed)
7414                 drm_atomic_state_put(&state->base);
7415 }
7416
7417 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
7418 {
7419         struct drm_i915_private *dev_priv =
7420                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
7421
7422         intel_atomic_helper_free_state(dev_priv);
7423 }
7424
7425 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7426 {
7427         struct wait_queue_entry wait_fence, wait_reset;
7428         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7429
7430         init_wait_entry(&wait_fence, 0);
7431         init_wait_entry(&wait_reset, 0);
7432         for (;;) {
7433                 prepare_to_wait(&intel_state->commit_ready.wait,
7434                                 &wait_fence, TASK_UNINTERRUPTIBLE);
7435                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7436                                               I915_RESET_MODESET),
7437                                 &wait_reset, TASK_UNINTERRUPTIBLE);
7438
7439
7440                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7441                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7442                         break;
7443
7444                 schedule();
7445         }
7446         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7447         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7448                                   I915_RESET_MODESET),
7449                     &wait_reset);
7450 }
7451
7452 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
7453 {
7454         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7455         struct intel_crtc *crtc;
7456         int i;
7457
7458         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7459                                             new_crtc_state, i)
7460                 intel_dsb_cleanup(old_crtc_state);
7461 }
7462
7463 static void intel_atomic_cleanup_work(struct work_struct *work)
7464 {
7465         struct intel_atomic_state *state =
7466                 container_of(work, struct intel_atomic_state, base.commit_work);
7467         struct drm_i915_private *i915 = to_i915(state->base.dev);
7468
7469         intel_cleanup_dsbs(state);
7470         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7471         drm_atomic_helper_commit_cleanup_done(&state->base);
7472         drm_atomic_state_put(&state->base);
7473
7474         intel_atomic_helper_free_state(i915);
7475 }
7476
7477 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7478 {
7479         struct drm_i915_private *i915 = to_i915(state->base.dev);
7480         struct intel_plane *plane;
7481         struct intel_plane_state *plane_state;
7482         int i;
7483
7484         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7485                 struct drm_framebuffer *fb = plane_state->hw.fb;
7486                 int cc_plane;
7487                 int ret;
7488
7489                 if (!fb)
7490                         continue;
7491
7492                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7493                 if (cc_plane < 0)
7494                         continue;
7495
7496                 /*
7497                  * The layout of the fast clear color value expected by HW
7498                  * (the DRM ABI requiring this value to be located in fb at
7499                  * offset 0 of cc plane, plane #2 previous generations or
7500                  * plane #1 for flat ccs):
7501                  * - 4 x 4 bytes per-channel value
7502                  *   (in surface type specific float/int format provided by the fb user)
7503                  * - 8 bytes native color value used by the display
7504                  *   (converted/written by GPU during a fast clear operation using the
7505                  *    above per-channel values)
7506                  *
7507                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7508                  * caller made sure that the object is synced wrt. the related color clear value
7509                  * GPU write on it.
7510                  */
7511                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7512                                                      fb->offsets[cc_plane] + 16,
7513                                                      &plane_state->ccval,
7514                                                      sizeof(plane_state->ccval));
7515                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7516                 drm_WARN_ON(&i915->drm, ret);
7517         }
7518 }
7519
7520 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7521 {
7522         struct drm_device *dev = state->base.dev;
7523         struct drm_i915_private *dev_priv = to_i915(dev);
7524         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7525         struct intel_crtc *crtc;
7526         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7527         intel_wakeref_t wakeref = 0;
7528         int i;
7529
7530         intel_atomic_commit_fence_wait(state);
7531
7532         drm_atomic_helper_wait_for_dependencies(&state->base);
7533
7534         if (state->modeset)
7535                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
7536
7537         intel_atomic_prepare_plane_clear_colors(state);
7538
7539         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7540                                             new_crtc_state, i) {
7541                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7542                     new_crtc_state->update_pipe) {
7543                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7544                 }
7545         }
7546
7547         intel_commit_modeset_disables(state);
7548
7549         /* FIXME: Eventually get rid of our crtc->config pointer */
7550         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7551                 crtc->config = new_crtc_state;
7552
7553         if (state->modeset) {
7554                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7555
7556                 intel_set_cdclk_pre_plane_update(state);
7557
7558                 intel_modeset_verify_disabled(dev_priv, state);
7559         }
7560
7561         intel_sagv_pre_plane_update(state);
7562
7563         /* Complete the events for pipes that have now been disabled */
7564         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7565                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7566
7567                 /* Complete events for now disable pipes here. */
7568                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7569                         spin_lock_irq(&dev->event_lock);
7570                         drm_crtc_send_vblank_event(&crtc->base,
7571                                                    new_crtc_state->uapi.event);
7572                         spin_unlock_irq(&dev->event_lock);
7573
7574                         new_crtc_state->uapi.event = NULL;
7575                 }
7576         }
7577
7578         intel_encoders_update_prepare(state);
7579
7580         intel_dbuf_pre_plane_update(state);
7581         intel_mbus_dbox_update(state);
7582
7583         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7584                 if (new_crtc_state->do_async_flip)
7585                         intel_crtc_enable_flip_done(state, crtc);
7586         }
7587
7588         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7589         dev_priv->display.funcs.display->commit_modeset_enables(state);
7590
7591         intel_encoders_update_complete(state);
7592
7593         if (state->modeset)
7594                 intel_set_cdclk_post_plane_update(state);
7595
7596         intel_wait_for_vblank_workers(state);
7597
7598         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7599          * already, but still need the state for the delayed optimization. To
7600          * fix this:
7601          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7602          * - schedule that vblank worker _before_ calling hw_done
7603          * - at the start of commit_tail, cancel it _synchrously
7604          * - switch over to the vblank wait helper in the core after that since
7605          *   we don't need out special handling any more.
7606          */
7607         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7608
7609         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7610                 if (new_crtc_state->do_async_flip)
7611                         intel_crtc_disable_flip_done(state, crtc);
7612         }
7613
7614         /*
7615          * Now that the vblank has passed, we can go ahead and program the
7616          * optimal watermarks on platforms that need two-step watermark
7617          * programming.
7618          *
7619          * TODO: Move this (and other cleanup) to an async worker eventually.
7620          */
7621         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7622                                             new_crtc_state, i) {
7623                 /*
7624                  * Gen2 reports pipe underruns whenever all planes are disabled.
7625                  * So re-enable underrun reporting after some planes get enabled.
7626                  *
7627                  * We do this before .optimize_watermarks() so that we have a
7628                  * chance of catching underruns with the intermediate watermarks
7629                  * vs. the new plane configuration.
7630                  */
7631                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7632                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7633
7634                 intel_optimize_watermarks(state, crtc);
7635         }
7636
7637         intel_dbuf_post_plane_update(state);
7638         intel_psr_post_plane_update(state);
7639
7640         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7641                 intel_post_plane_update(state, crtc);
7642
7643                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7644
7645                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7646
7647                 /*
7648                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7649                  * cleanup. So copy and reset the dsb structure to sync with
7650                  * commit_done and later do dsb cleanup in cleanup_work.
7651                  */
7652                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7653         }
7654
7655         /* Underruns don't always raise interrupts, so check manually */
7656         intel_check_cpu_fifo_underruns(dev_priv);
7657         intel_check_pch_fifo_underruns(dev_priv);
7658
7659         if (state->modeset)
7660                 intel_verify_planes(state);
7661
7662         intel_sagv_post_plane_update(state);
7663
7664         drm_atomic_helper_commit_hw_done(&state->base);
7665
7666         if (state->modeset) {
7667                 /* As one of the primary mmio accessors, KMS has a high
7668                  * likelihood of triggering bugs in unclaimed access. After we
7669                  * finish modesetting, see if an error has been flagged, and if
7670                  * so enable debugging for the next modeset - and hope we catch
7671                  * the culprit.
7672                  */
7673                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7674                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
7675         }
7676         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7677
7678         /*
7679          * Defer the cleanup of the old state to a separate worker to not
7680          * impede the current task (userspace for blocking modesets) that
7681          * are executed inline. For out-of-line asynchronous modesets/flips,
7682          * deferring to a new worker seems overkill, but we would place a
7683          * schedule point (cond_resched()) here anyway to keep latencies
7684          * down.
7685          */
7686         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7687         queue_work(system_highpri_wq, &state->base.commit_work);
7688 }
7689
7690 static void intel_atomic_commit_work(struct work_struct *work)
7691 {
7692         struct intel_atomic_state *state =
7693                 container_of(work, struct intel_atomic_state, base.commit_work);
7694
7695         intel_atomic_commit_tail(state);
7696 }
7697
7698 static int
7699 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7700                           enum i915_sw_fence_notify notify)
7701 {
7702         struct intel_atomic_state *state =
7703                 container_of(fence, struct intel_atomic_state, commit_ready);
7704
7705         switch (notify) {
7706         case FENCE_COMPLETE:
7707                 /* we do blocking waits in the worker, nothing to do here */
7708                 break;
7709         case FENCE_FREE:
7710                 {
7711                         struct intel_atomic_helper *helper =
7712                                 &to_i915(state->base.dev)->atomic_helper;
7713
7714                         if (llist_add(&state->freed, &helper->free_list))
7715                                 schedule_work(&helper->free_work);
7716                         break;
7717                 }
7718         }
7719
7720         return NOTIFY_DONE;
7721 }
7722
7723 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7724 {
7725         struct intel_plane_state *old_plane_state, *new_plane_state;
7726         struct intel_plane *plane;
7727         int i;
7728
7729         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7730                                              new_plane_state, i)
7731                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7732                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7733                                         plane->frontbuffer_bit);
7734 }
7735
7736 static int intel_atomic_commit(struct drm_device *dev,
7737                                struct drm_atomic_state *_state,
7738                                bool nonblock)
7739 {
7740         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7741         struct drm_i915_private *dev_priv = to_i915(dev);
7742         int ret = 0;
7743
7744         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7745
7746         drm_atomic_state_get(&state->base);
7747         i915_sw_fence_init(&state->commit_ready,
7748                            intel_atomic_commit_ready);
7749
7750         /*
7751          * The intel_legacy_cursor_update() fast path takes care
7752          * of avoiding the vblank waits for simple cursor
7753          * movement and flips. For cursor on/off and size changes,
7754          * we want to perform the vblank waits so that watermark
7755          * updates happen during the correct frames. Gen9+ have
7756          * double buffered watermarks and so shouldn't need this.
7757          *
7758          * Unset state->legacy_cursor_update before the call to
7759          * drm_atomic_helper_setup_commit() because otherwise
7760          * drm_atomic_helper_wait_for_flip_done() is a noop and
7761          * we get FIFO underruns because we didn't wait
7762          * for vblank.
7763          *
7764          * FIXME doing watermarks and fb cleanup from a vblank worker
7765          * (assuming we had any) would solve these problems.
7766          */
7767         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7768                 struct intel_crtc_state *new_crtc_state;
7769                 struct intel_crtc *crtc;
7770                 int i;
7771
7772                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7773                         if (new_crtc_state->wm.need_postvbl_update ||
7774                             new_crtc_state->update_wm_post)
7775                                 state->base.legacy_cursor_update = false;
7776         }
7777
7778         ret = intel_atomic_prepare_commit(state);
7779         if (ret) {
7780                 drm_dbg_atomic(&dev_priv->drm,
7781                                "Preparing state failed with %i\n", ret);
7782                 i915_sw_fence_commit(&state->commit_ready);
7783                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7784                 return ret;
7785         }
7786
7787         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7788         if (!ret)
7789                 ret = drm_atomic_helper_swap_state(&state->base, true);
7790         if (!ret)
7791                 intel_atomic_swap_global_state(state);
7792
7793         if (ret) {
7794                 struct intel_crtc_state *new_crtc_state;
7795                 struct intel_crtc *crtc;
7796                 int i;
7797
7798                 i915_sw_fence_commit(&state->commit_ready);
7799
7800                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7801                         intel_dsb_cleanup(new_crtc_state);
7802
7803                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7804                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7805                 return ret;
7806         }
7807         intel_shared_dpll_swap_state(state);
7808         intel_atomic_track_fbs(state);
7809
7810         drm_atomic_state_get(&state->base);
7811         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7812
7813         i915_sw_fence_commit(&state->commit_ready);
7814         if (nonblock && state->modeset) {
7815                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
7816         } else if (nonblock) {
7817                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
7818         } else {
7819                 if (state->modeset)
7820                         flush_workqueue(dev_priv->modeset_wq);
7821                 intel_atomic_commit_tail(state);
7822         }
7823
7824         return 0;
7825 }
7826
7827 /**
7828  * intel_plane_destroy - destroy a plane
7829  * @plane: plane to destroy
7830  *
7831  * Common destruction function for all types of planes (primary, cursor,
7832  * sprite).
7833  */
7834 void intel_plane_destroy(struct drm_plane *plane)
7835 {
7836         drm_plane_cleanup(plane);
7837         kfree(to_intel_plane(plane));
7838 }
7839
7840 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
7841 {
7842         struct intel_plane *plane;
7843
7844         for_each_intel_plane(&dev_priv->drm, plane) {
7845                 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
7846                                                               plane->pipe);
7847
7848                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
7849         }
7850 }
7851
7852
7853 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7854                                       struct drm_file *file)
7855 {
7856         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7857         struct drm_crtc *drmmode_crtc;
7858         struct intel_crtc *crtc;
7859
7860         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7861         if (!drmmode_crtc)
7862                 return -ENOENT;
7863
7864         crtc = to_intel_crtc(drmmode_crtc);
7865         pipe_from_crtc_id->pipe = crtc->pipe;
7866
7867         return 0;
7868 }
7869
7870 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7871 {
7872         struct drm_device *dev = encoder->base.dev;
7873         struct intel_encoder *source_encoder;
7874         u32 possible_clones = 0;
7875
7876         for_each_intel_encoder(dev, source_encoder) {
7877                 if (encoders_cloneable(encoder, source_encoder))
7878                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7879         }
7880
7881         return possible_clones;
7882 }
7883
7884 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7885 {
7886         struct drm_device *dev = encoder->base.dev;
7887         struct intel_crtc *crtc;
7888         u32 possible_crtcs = 0;
7889
7890         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7891                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7892
7893         return possible_crtcs;
7894 }
7895
7896 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7897 {
7898         if (!IS_MOBILE(dev_priv))
7899                 return false;
7900
7901         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7902                 return false;
7903
7904         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7905                 return false;
7906
7907         return true;
7908 }
7909
7910 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7911 {
7912         if (DISPLAY_VER(dev_priv) >= 9)
7913                 return false;
7914
7915         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7916                 return false;
7917
7918         if (HAS_PCH_LPT_H(dev_priv) &&
7919             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7920                 return false;
7921
7922         /* DDI E can't be used if DDI A requires 4 lanes */
7923         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7924                 return false;
7925
7926         if (!dev_priv->vbt.int_crt_support)
7927                 return false;
7928
7929         return true;
7930 }
7931
7932 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
7933 {
7934         struct intel_encoder *encoder;
7935         bool dpd_is_edp = false;
7936
7937         intel_pps_unlock_regs_wa(dev_priv);
7938
7939         if (!HAS_DISPLAY(dev_priv))
7940                 return;
7941
7942         if (IS_DG2(dev_priv)) {
7943                 intel_ddi_init(dev_priv, PORT_A);
7944                 intel_ddi_init(dev_priv, PORT_B);
7945                 intel_ddi_init(dev_priv, PORT_C);
7946                 intel_ddi_init(dev_priv, PORT_D_XELPD);
7947                 intel_ddi_init(dev_priv, PORT_TC1);
7948         } else if (IS_ALDERLAKE_P(dev_priv)) {
7949                 intel_ddi_init(dev_priv, PORT_A);
7950                 intel_ddi_init(dev_priv, PORT_B);
7951                 intel_ddi_init(dev_priv, PORT_TC1);
7952                 intel_ddi_init(dev_priv, PORT_TC2);
7953                 intel_ddi_init(dev_priv, PORT_TC3);
7954                 intel_ddi_init(dev_priv, PORT_TC4);
7955                 icl_dsi_init(dev_priv);
7956         } else if (IS_ALDERLAKE_S(dev_priv)) {
7957                 intel_ddi_init(dev_priv, PORT_A);
7958                 intel_ddi_init(dev_priv, PORT_TC1);
7959                 intel_ddi_init(dev_priv, PORT_TC2);
7960                 intel_ddi_init(dev_priv, PORT_TC3);
7961                 intel_ddi_init(dev_priv, PORT_TC4);
7962         } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7963                 intel_ddi_init(dev_priv, PORT_A);
7964                 intel_ddi_init(dev_priv, PORT_B);
7965                 intel_ddi_init(dev_priv, PORT_TC1);
7966                 intel_ddi_init(dev_priv, PORT_TC2);
7967         } else if (DISPLAY_VER(dev_priv) >= 12) {
7968                 intel_ddi_init(dev_priv, PORT_A);
7969                 intel_ddi_init(dev_priv, PORT_B);
7970                 intel_ddi_init(dev_priv, PORT_TC1);
7971                 intel_ddi_init(dev_priv, PORT_TC2);
7972                 intel_ddi_init(dev_priv, PORT_TC3);
7973                 intel_ddi_init(dev_priv, PORT_TC4);
7974                 intel_ddi_init(dev_priv, PORT_TC5);
7975                 intel_ddi_init(dev_priv, PORT_TC6);
7976                 icl_dsi_init(dev_priv);
7977         } else if (IS_JSL_EHL(dev_priv)) {
7978                 intel_ddi_init(dev_priv, PORT_A);
7979                 intel_ddi_init(dev_priv, PORT_B);
7980                 intel_ddi_init(dev_priv, PORT_C);
7981                 intel_ddi_init(dev_priv, PORT_D);
7982                 icl_dsi_init(dev_priv);
7983         } else if (DISPLAY_VER(dev_priv) == 11) {
7984                 intel_ddi_init(dev_priv, PORT_A);
7985                 intel_ddi_init(dev_priv, PORT_B);
7986                 intel_ddi_init(dev_priv, PORT_C);
7987                 intel_ddi_init(dev_priv, PORT_D);
7988                 intel_ddi_init(dev_priv, PORT_E);
7989                 intel_ddi_init(dev_priv, PORT_F);
7990                 icl_dsi_init(dev_priv);
7991         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7992                 intel_ddi_init(dev_priv, PORT_A);
7993                 intel_ddi_init(dev_priv, PORT_B);
7994                 intel_ddi_init(dev_priv, PORT_C);
7995                 vlv_dsi_init(dev_priv);
7996         } else if (DISPLAY_VER(dev_priv) >= 9) {
7997                 intel_ddi_init(dev_priv, PORT_A);
7998                 intel_ddi_init(dev_priv, PORT_B);
7999                 intel_ddi_init(dev_priv, PORT_C);
8000                 intel_ddi_init(dev_priv, PORT_D);
8001                 intel_ddi_init(dev_priv, PORT_E);
8002         } else if (HAS_DDI(dev_priv)) {
8003                 u32 found;
8004
8005                 if (intel_ddi_crt_present(dev_priv))
8006                         intel_crt_init(dev_priv);
8007
8008                 /* Haswell uses DDI functions to detect digital outputs. */
8009                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
8010                 if (found)
8011                         intel_ddi_init(dev_priv, PORT_A);
8012
8013                 found = intel_de_read(dev_priv, SFUSE_STRAP);
8014                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8015                         intel_ddi_init(dev_priv, PORT_B);
8016                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8017                         intel_ddi_init(dev_priv, PORT_C);
8018                 if (found & SFUSE_STRAP_DDID_DETECTED)
8019                         intel_ddi_init(dev_priv, PORT_D);
8020                 if (found & SFUSE_STRAP_DDIF_DETECTED)
8021                         intel_ddi_init(dev_priv, PORT_F);
8022         } else if (HAS_PCH_SPLIT(dev_priv)) {
8023                 int found;
8024
8025                 /*
8026                  * intel_edp_init_connector() depends on this completing first,
8027                  * to prevent the registration of both eDP and LVDS and the
8028                  * incorrect sharing of the PPS.
8029                  */
8030                 intel_lvds_init(dev_priv);
8031                 intel_crt_init(dev_priv);
8032
8033                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8034
8035                 if (ilk_has_edp_a(dev_priv))
8036                         g4x_dp_init(dev_priv, DP_A, PORT_A);
8037
8038                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
8039                         /* PCH SDVOB multiplex with HDMIB */
8040                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
8041                         if (!found)
8042                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
8043                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
8044                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
8045                 }
8046
8047                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
8048                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
8049
8050                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
8051                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
8052
8053                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
8054                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
8055
8056                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
8057                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
8058         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8059                 bool has_edp, has_port;
8060
8061                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
8062                         intel_crt_init(dev_priv);
8063
8064                 /*
8065                  * The DP_DETECTED bit is the latched state of the DDC
8066                  * SDA pin at boot. However since eDP doesn't require DDC
8067                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
8068                  * eDP ports may have been muxed to an alternate function.
8069                  * Thus we can't rely on the DP_DETECTED bit alone to detect
8070                  * eDP ports. Consult the VBT as well as DP_DETECTED to
8071                  * detect eDP ports.
8072                  *
8073                  * Sadly the straps seem to be missing sometimes even for HDMI
8074                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
8075                  * and VBT for the presence of the port. Additionally we can't
8076                  * trust the port type the VBT declares as we've seen at least
8077                  * HDMI ports that the VBT claim are DP or eDP.
8078                  */
8079                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8080                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
8081                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8082                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8083                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8084                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8085
8086                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8087                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
8088                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8089                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
8090                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
8091                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
8092
8093                 if (IS_CHERRYVIEW(dev_priv)) {
8094                         /*
8095                          * eDP not supported on port D,
8096                          * so no need to worry about it
8097                          */
8098                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
8099                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
8100                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
8101                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
8102                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
8103                 }
8104
8105                 vlv_dsi_init(dev_priv);
8106         } else if (IS_PINEVIEW(dev_priv)) {
8107                 intel_lvds_init(dev_priv);
8108                 intel_crt_init(dev_priv);
8109         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
8110                 bool found = false;
8111
8112                 if (IS_MOBILE(dev_priv))
8113                         intel_lvds_init(dev_priv);
8114
8115                 intel_crt_init(dev_priv);
8116
8117                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8118                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
8119                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
8120                         if (!found && IS_G4X(dev_priv)) {
8121                                 drm_dbg_kms(&dev_priv->drm,
8122                                             "probing HDMI on SDVOB\n");
8123                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
8124                         }
8125
8126                         if (!found && IS_G4X(dev_priv))
8127                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
8128                 }
8129
8130                 /* Before G4X SDVOC doesn't have its own detect register */
8131
8132                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8133                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
8134                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
8135                 }
8136
8137                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
8138
8139                         if (IS_G4X(dev_priv)) {
8140                                 drm_dbg_kms(&dev_priv->drm,
8141                                             "probing HDMI on SDVOC\n");
8142                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
8143                         }
8144                         if (IS_G4X(dev_priv))
8145                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
8146                 }
8147
8148                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
8149                         g4x_dp_init(dev_priv, DP_D, PORT_D);
8150
8151                 if (SUPPORTS_TV(dev_priv))
8152                         intel_tv_init(dev_priv);
8153         } else if (DISPLAY_VER(dev_priv) == 2) {
8154                 if (IS_I85X(dev_priv))
8155                         intel_lvds_init(dev_priv);
8156
8157                 intel_crt_init(dev_priv);
8158                 intel_dvo_init(dev_priv);
8159         }
8160
8161         for_each_intel_encoder(&dev_priv->drm, encoder) {
8162                 encoder->base.possible_crtcs =
8163                         intel_encoder_possible_crtcs(encoder);
8164                 encoder->base.possible_clones =
8165                         intel_encoder_possible_clones(encoder);
8166         }
8167
8168         intel_init_pch_refclk(dev_priv);
8169
8170         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
8171 }
8172
8173 static enum drm_mode_status
8174 intel_mode_valid(struct drm_device *dev,
8175                  const struct drm_display_mode *mode)
8176 {
8177         struct drm_i915_private *dev_priv = to_i915(dev);
8178         int hdisplay_max, htotal_max;
8179         int vdisplay_max, vtotal_max;
8180
8181         /*
8182          * Can't reject DBLSCAN here because Xorg ddxen can add piles
8183          * of DBLSCAN modes to the output's mode list when they detect
8184          * the scaling mode property on the connector. And they don't
8185          * ask the kernel to validate those modes in any way until
8186          * modeset time at which point the client gets a protocol error.
8187          * So in order to not upset those clients we silently ignore the
8188          * DBLSCAN flag on such connectors. For other connectors we will
8189          * reject modes with the DBLSCAN flag in encoder->compute_config().
8190          * And we always reject DBLSCAN modes in connector->mode_valid()
8191          * as we never want such modes on the connector's mode list.
8192          */
8193
8194         if (mode->vscan > 1)
8195                 return MODE_NO_VSCAN;
8196
8197         if (mode->flags & DRM_MODE_FLAG_HSKEW)
8198                 return MODE_H_ILLEGAL;
8199
8200         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8201                            DRM_MODE_FLAG_NCSYNC |
8202                            DRM_MODE_FLAG_PCSYNC))
8203                 return MODE_HSYNC;
8204
8205         if (mode->flags & (DRM_MODE_FLAG_BCAST |
8206                            DRM_MODE_FLAG_PIXMUX |
8207                            DRM_MODE_FLAG_CLKDIV2))
8208                 return MODE_BAD;
8209
8210         /* Transcoder timing limits */
8211         if (DISPLAY_VER(dev_priv) >= 11) {
8212                 hdisplay_max = 16384;
8213                 vdisplay_max = 8192;
8214                 htotal_max = 16384;
8215                 vtotal_max = 8192;
8216         } else if (DISPLAY_VER(dev_priv) >= 9 ||
8217                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8218                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8219                 vdisplay_max = 4096;
8220                 htotal_max = 8192;
8221                 vtotal_max = 8192;
8222         } else if (DISPLAY_VER(dev_priv) >= 3) {
8223                 hdisplay_max = 4096;
8224                 vdisplay_max = 4096;
8225                 htotal_max = 8192;
8226                 vtotal_max = 8192;
8227         } else {
8228                 hdisplay_max = 2048;
8229                 vdisplay_max = 2048;
8230                 htotal_max = 4096;
8231                 vtotal_max = 4096;
8232         }
8233
8234         if (mode->hdisplay > hdisplay_max ||
8235             mode->hsync_start > htotal_max ||
8236             mode->hsync_end > htotal_max ||
8237             mode->htotal > htotal_max)
8238                 return MODE_H_ILLEGAL;
8239
8240         if (mode->vdisplay > vdisplay_max ||
8241             mode->vsync_start > vtotal_max ||
8242             mode->vsync_end > vtotal_max ||
8243             mode->vtotal > vtotal_max)
8244                 return MODE_V_ILLEGAL;
8245
8246         if (DISPLAY_VER(dev_priv) >= 5) {
8247                 if (mode->hdisplay < 64 ||
8248                     mode->htotal - mode->hdisplay < 32)
8249                         return MODE_H_ILLEGAL;
8250
8251                 if (mode->vtotal - mode->vdisplay < 5)
8252                         return MODE_V_ILLEGAL;
8253         } else {
8254                 if (mode->htotal - mode->hdisplay < 32)
8255                         return MODE_H_ILLEGAL;
8256
8257                 if (mode->vtotal - mode->vdisplay < 3)
8258                         return MODE_V_ILLEGAL;
8259         }
8260
8261         /*
8262          * Cantiga+ cannot handle modes with a hsync front porch of 0.
8263          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8264          */
8265         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8266             mode->hsync_start == mode->hdisplay)
8267                 return MODE_H_ILLEGAL;
8268
8269         return MODE_OK;
8270 }
8271
8272 enum drm_mode_status
8273 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8274                                 const struct drm_display_mode *mode,
8275                                 bool bigjoiner)
8276 {
8277         int plane_width_max, plane_height_max;
8278
8279         /*
8280          * intel_mode_valid() should be
8281          * sufficient on older platforms.
8282          */
8283         if (DISPLAY_VER(dev_priv) < 9)
8284                 return MODE_OK;
8285
8286         /*
8287          * Most people will probably want a fullscreen
8288          * plane so let's not advertize modes that are
8289          * too big for that.
8290          */
8291         if (DISPLAY_VER(dev_priv) >= 11) {
8292                 plane_width_max = 5120 << bigjoiner;
8293                 plane_height_max = 4320;
8294         } else {
8295                 plane_width_max = 5120;
8296                 plane_height_max = 4096;
8297         }
8298
8299         if (mode->hdisplay > plane_width_max)
8300                 return MODE_H_ILLEGAL;
8301
8302         if (mode->vdisplay > plane_height_max)
8303                 return MODE_V_ILLEGAL;
8304
8305         return MODE_OK;
8306 }
8307
8308 static const struct drm_mode_config_funcs intel_mode_funcs = {
8309         .fb_create = intel_user_framebuffer_create,
8310         .get_format_info = intel_fb_get_format_info,
8311         .output_poll_changed = intel_fbdev_output_poll_changed,
8312         .mode_valid = intel_mode_valid,
8313         .atomic_check = intel_atomic_check,
8314         .atomic_commit = intel_atomic_commit,
8315         .atomic_state_alloc = intel_atomic_state_alloc,
8316         .atomic_state_clear = intel_atomic_state_clear,
8317         .atomic_state_free = intel_atomic_state_free,
8318 };
8319
8320 static const struct intel_display_funcs skl_display_funcs = {
8321         .get_pipe_config = hsw_get_pipe_config,
8322         .crtc_enable = hsw_crtc_enable,
8323         .crtc_disable = hsw_crtc_disable,
8324         .commit_modeset_enables = skl_commit_modeset_enables,
8325         .get_initial_plane_config = skl_get_initial_plane_config,
8326 };
8327
8328 static const struct intel_display_funcs ddi_display_funcs = {
8329         .get_pipe_config = hsw_get_pipe_config,
8330         .crtc_enable = hsw_crtc_enable,
8331         .crtc_disable = hsw_crtc_disable,
8332         .commit_modeset_enables = intel_commit_modeset_enables,
8333         .get_initial_plane_config = i9xx_get_initial_plane_config,
8334 };
8335
8336 static const struct intel_display_funcs pch_split_display_funcs = {
8337         .get_pipe_config = ilk_get_pipe_config,
8338         .crtc_enable = ilk_crtc_enable,
8339         .crtc_disable = ilk_crtc_disable,
8340         .commit_modeset_enables = intel_commit_modeset_enables,
8341         .get_initial_plane_config = i9xx_get_initial_plane_config,
8342 };
8343
8344 static const struct intel_display_funcs vlv_display_funcs = {
8345         .get_pipe_config = i9xx_get_pipe_config,
8346         .crtc_enable = valleyview_crtc_enable,
8347         .crtc_disable = i9xx_crtc_disable,
8348         .commit_modeset_enables = intel_commit_modeset_enables,
8349         .get_initial_plane_config = i9xx_get_initial_plane_config,
8350 };
8351
8352 static const struct intel_display_funcs i9xx_display_funcs = {
8353         .get_pipe_config = i9xx_get_pipe_config,
8354         .crtc_enable = i9xx_crtc_enable,
8355         .crtc_disable = i9xx_crtc_disable,
8356         .commit_modeset_enables = intel_commit_modeset_enables,
8357         .get_initial_plane_config = i9xx_get_initial_plane_config,
8358 };
8359
8360 /**
8361  * intel_init_display_hooks - initialize the display modesetting hooks
8362  * @dev_priv: device private
8363  */
8364 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8365 {
8366         if (!HAS_DISPLAY(dev_priv))
8367                 return;
8368
8369         intel_init_cdclk_hooks(dev_priv);
8370         intel_audio_hooks_init(dev_priv);
8371
8372         intel_dpll_init_clock_hook(dev_priv);
8373
8374         if (DISPLAY_VER(dev_priv) >= 9) {
8375                 dev_priv->display.funcs.display = &skl_display_funcs;
8376         } else if (HAS_DDI(dev_priv)) {
8377                 dev_priv->display.funcs.display = &ddi_display_funcs;
8378         } else if (HAS_PCH_SPLIT(dev_priv)) {
8379                 dev_priv->display.funcs.display = &pch_split_display_funcs;
8380         } else if (IS_CHERRYVIEW(dev_priv) ||
8381                    IS_VALLEYVIEW(dev_priv)) {
8382                 dev_priv->display.funcs.display = &vlv_display_funcs;
8383         } else {
8384                 dev_priv->display.funcs.display = &i9xx_display_funcs;
8385         }
8386
8387         intel_fdi_init_hook(dev_priv);
8388 }
8389
8390 void intel_modeset_init_hw(struct drm_i915_private *i915)
8391 {
8392         struct intel_cdclk_state *cdclk_state;
8393
8394         if (!HAS_DISPLAY(i915))
8395                 return;
8396
8397         cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
8398
8399         intel_update_cdclk(i915);
8400         intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
8401         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
8402 }
8403
8404 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
8405 {
8406         struct drm_plane *plane;
8407         struct intel_crtc *crtc;
8408
8409         for_each_intel_crtc(state->dev, crtc) {
8410                 struct intel_crtc_state *crtc_state;
8411
8412                 crtc_state = intel_atomic_get_crtc_state(state, crtc);
8413                 if (IS_ERR(crtc_state))
8414                         return PTR_ERR(crtc_state);
8415
8416                 if (crtc_state->hw.active) {
8417                         /*
8418                          * Preserve the inherited flag to avoid
8419                          * taking the full modeset path.
8420                          */
8421                         crtc_state->inherited = true;
8422                 }
8423         }
8424
8425         drm_for_each_plane(plane, state->dev) {
8426                 struct drm_plane_state *plane_state;
8427
8428                 plane_state = drm_atomic_get_plane_state(state, plane);
8429                 if (IS_ERR(plane_state))
8430                         return PTR_ERR(plane_state);
8431         }
8432
8433         return 0;
8434 }
8435
8436 /*
8437  * Calculate what we think the watermarks should be for the state we've read
8438  * out of the hardware and then immediately program those watermarks so that
8439  * we ensure the hardware settings match our internal state.
8440  *
8441  * We can calculate what we think WM's should be by creating a duplicate of the
8442  * current state (which was constructed during hardware readout) and running it
8443  * through the atomic check code to calculate new watermark values in the
8444  * state object.
8445  */
8446 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
8447 {
8448         struct drm_atomic_state *state;
8449         struct intel_atomic_state *intel_state;
8450         struct intel_crtc *crtc;
8451         struct intel_crtc_state *crtc_state;
8452         struct drm_modeset_acquire_ctx ctx;
8453         int ret;
8454         int i;
8455
8456         /* Only supported on platforms that use atomic watermark design */
8457         if (!dev_priv->display.funcs.wm->optimize_watermarks)
8458                 return;
8459
8460         state = drm_atomic_state_alloc(&dev_priv->drm);
8461         if (drm_WARN_ON(&dev_priv->drm, !state))
8462                 return;
8463
8464         intel_state = to_intel_atomic_state(state);
8465
8466         drm_modeset_acquire_init(&ctx, 0);
8467
8468 retry:
8469         state->acquire_ctx = &ctx;
8470
8471         /*
8472          * Hardware readout is the only time we don't want to calculate
8473          * intermediate watermarks (since we don't trust the current
8474          * watermarks).
8475          */
8476         if (!HAS_GMCH(dev_priv))
8477                 intel_state->skip_intermediate_wm = true;
8478
8479         ret = sanitize_watermarks_add_affected(state);
8480         if (ret)
8481                 goto fail;
8482
8483         ret = intel_atomic_check(&dev_priv->drm, state);
8484         if (ret)
8485                 goto fail;
8486
8487         /* Write calculated watermark values back */
8488         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
8489                 crtc_state->wm.need_postvbl_update = true;
8490                 intel_optimize_watermarks(intel_state, crtc);
8491
8492                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
8493         }
8494
8495 fail:
8496         if (ret == -EDEADLK) {
8497                 drm_atomic_state_clear(state);
8498                 drm_modeset_backoff(&ctx);
8499                 goto retry;
8500         }
8501
8502         /*
8503          * If we fail here, it means that the hardware appears to be
8504          * programmed in a way that shouldn't be possible, given our
8505          * understanding of watermark requirements.  This might mean a
8506          * mistake in the hardware readout code or a mistake in the
8507          * watermark calculations for a given platform.  Raise a WARN
8508          * so that this is noticeable.
8509          *
8510          * If this actually happens, we'll have to just leave the
8511          * BIOS-programmed watermarks untouched and hope for the best.
8512          */
8513         drm_WARN(&dev_priv->drm, ret,
8514                  "Could not determine valid watermarks for inherited state\n");
8515
8516         drm_atomic_state_put(state);
8517
8518         drm_modeset_drop_locks(&ctx);
8519         drm_modeset_acquire_fini(&ctx);
8520 }
8521
8522 static int intel_initial_commit(struct drm_device *dev)
8523 {
8524         struct drm_atomic_state *state = NULL;
8525         struct drm_modeset_acquire_ctx ctx;
8526         struct intel_crtc *crtc;
8527         int ret = 0;
8528
8529         state = drm_atomic_state_alloc(dev);
8530         if (!state)
8531                 return -ENOMEM;
8532
8533         drm_modeset_acquire_init(&ctx, 0);
8534
8535 retry:
8536         state->acquire_ctx = &ctx;
8537
8538         for_each_intel_crtc(dev, crtc) {
8539                 struct intel_crtc_state *crtc_state =
8540                         intel_atomic_get_crtc_state(state, crtc);
8541
8542                 if (IS_ERR(crtc_state)) {
8543                         ret = PTR_ERR(crtc_state);
8544                         goto out;
8545                 }
8546
8547                 if (crtc_state->hw.active) {
8548                         struct intel_encoder *encoder;
8549
8550                         /*
8551                          * We've not yet detected sink capabilities
8552                          * (audio,infoframes,etc.) and thus we don't want to
8553                          * force a full state recomputation yet. We want that to
8554                          * happen only for the first real commit from userspace.
8555                          * So preserve the inherited flag for the time being.
8556                          */
8557                         crtc_state->inherited = true;
8558
8559                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8560                         if (ret)
8561                                 goto out;
8562
8563                         /*
8564                          * FIXME hack to force a LUT update to avoid the
8565                          * plane update forcing the pipe gamma on without
8566                          * having a proper LUT loaded. Remove once we
8567                          * have readout for pipe gamma enable.
8568                          */
8569                         crtc_state->uapi.color_mgmt_changed = true;
8570
8571                         for_each_intel_encoder_mask(dev, encoder,
8572                                                     crtc_state->uapi.encoder_mask) {
8573                                 if (encoder->initial_fastset_check &&
8574                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8575                                         ret = drm_atomic_add_affected_connectors(state,
8576                                                                                  &crtc->base);
8577                                         if (ret)
8578                                                 goto out;
8579                                 }
8580                         }
8581                 }
8582         }
8583
8584         ret = drm_atomic_commit(state);
8585
8586 out:
8587         if (ret == -EDEADLK) {
8588                 drm_atomic_state_clear(state);
8589                 drm_modeset_backoff(&ctx);
8590                 goto retry;
8591         }
8592
8593         drm_atomic_state_put(state);
8594
8595         drm_modeset_drop_locks(&ctx);
8596         drm_modeset_acquire_fini(&ctx);
8597
8598         return ret;
8599 }
8600
8601 static void intel_mode_config_init(struct drm_i915_private *i915)
8602 {
8603         struct drm_mode_config *mode_config = &i915->drm.mode_config;
8604
8605         drm_mode_config_init(&i915->drm);
8606         INIT_LIST_HEAD(&i915->global_obj_list);
8607
8608         mode_config->min_width = 0;
8609         mode_config->min_height = 0;
8610
8611         mode_config->preferred_depth = 24;
8612         mode_config->prefer_shadow = 1;
8613
8614         mode_config->funcs = &intel_mode_funcs;
8615
8616         mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
8617
8618         /*
8619          * Maximum framebuffer dimensions, chosen to match
8620          * the maximum render engine surface size on gen4+.
8621          */
8622         if (DISPLAY_VER(i915) >= 7) {
8623                 mode_config->max_width = 16384;
8624                 mode_config->max_height = 16384;
8625         } else if (DISPLAY_VER(i915) >= 4) {
8626                 mode_config->max_width = 8192;
8627                 mode_config->max_height = 8192;
8628         } else if (DISPLAY_VER(i915) == 3) {
8629                 mode_config->max_width = 4096;
8630                 mode_config->max_height = 4096;
8631         } else {
8632                 mode_config->max_width = 2048;
8633                 mode_config->max_height = 2048;
8634         }
8635
8636         if (IS_I845G(i915) || IS_I865G(i915)) {
8637                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
8638                 mode_config->cursor_height = 1023;
8639         } else if (IS_I830(i915) || IS_I85X(i915) ||
8640                    IS_I915G(i915) || IS_I915GM(i915)) {
8641                 mode_config->cursor_width = 64;
8642                 mode_config->cursor_height = 64;
8643         } else {
8644                 mode_config->cursor_width = 256;
8645                 mode_config->cursor_height = 256;
8646         }
8647 }
8648
8649 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
8650 {
8651         intel_atomic_global_obj_cleanup(i915);
8652         drm_mode_config_cleanup(&i915->drm);
8653 }
8654
8655 /* part #1: call before irq install */
8656 int intel_modeset_init_noirq(struct drm_i915_private *i915)
8657 {
8658         int ret;
8659
8660         if (i915_inject_probe_failure(i915))
8661                 return -ENODEV;
8662
8663         if (HAS_DISPLAY(i915)) {
8664                 ret = drm_vblank_init(&i915->drm,
8665                                       INTEL_NUM_PIPES(i915));
8666                 if (ret)
8667                         return ret;
8668         }
8669
8670         intel_bios_init(i915);
8671
8672         ret = intel_vga_register(i915);
8673         if (ret)
8674                 goto cleanup_bios;
8675
8676         /* FIXME: completely on the wrong abstraction layer */
8677         intel_power_domains_init_hw(i915, false);
8678
8679         if (!HAS_DISPLAY(i915))
8680                 return 0;
8681
8682         intel_dmc_ucode_init(i915);
8683
8684         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
8685         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
8686                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
8687
8688         intel_mode_config_init(i915);
8689
8690         ret = intel_cdclk_init(i915);
8691         if (ret)
8692                 goto cleanup_vga_client_pw_domain_dmc;
8693
8694         ret = intel_dbuf_init(i915);
8695         if (ret)
8696                 goto cleanup_vga_client_pw_domain_dmc;
8697
8698         ret = intel_bw_init(i915);
8699         if (ret)
8700                 goto cleanup_vga_client_pw_domain_dmc;
8701
8702         init_llist_head(&i915->atomic_helper.free_list);
8703         INIT_WORK(&i915->atomic_helper.free_work,
8704                   intel_atomic_helper_free_state_worker);
8705
8706         intel_init_quirks(i915);
8707
8708         intel_fbc_init(i915);
8709
8710         return 0;
8711
8712 cleanup_vga_client_pw_domain_dmc:
8713         intel_dmc_ucode_fini(i915);
8714         intel_power_domains_driver_remove(i915);
8715         intel_vga_unregister(i915);
8716 cleanup_bios:
8717         intel_bios_driver_remove(i915);
8718
8719         return ret;
8720 }
8721
8722 /* part #2: call after irq install, but before gem init */
8723 int intel_modeset_init_nogem(struct drm_i915_private *i915)
8724 {
8725         struct drm_device *dev = &i915->drm;
8726         enum pipe pipe;
8727         struct intel_crtc *crtc;
8728         int ret;
8729
8730         if (!HAS_DISPLAY(i915))
8731                 return 0;
8732
8733         intel_init_pm(i915);
8734
8735         intel_panel_sanitize_ssc(i915);
8736
8737         intel_pps_setup(i915);
8738
8739         intel_gmbus_setup(i915);
8740
8741         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
8742                     INTEL_NUM_PIPES(i915),
8743                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
8744
8745         for_each_pipe(i915, pipe) {
8746                 ret = intel_crtc_init(i915, pipe);
8747                 if (ret) {
8748                         intel_mode_config_cleanup(i915);
8749                         return ret;
8750                 }
8751         }
8752
8753         intel_plane_possible_crtcs_init(i915);
8754         intel_shared_dpll_init(i915);
8755         intel_fdi_pll_freq_update(i915);
8756
8757         intel_update_czclk(i915);
8758         intel_modeset_init_hw(i915);
8759         intel_dpll_update_ref_clks(i915);
8760
8761         intel_hdcp_component_init(i915);
8762
8763         if (i915->max_cdclk_freq == 0)
8764                 intel_update_max_cdclk(i915);
8765
8766         /*
8767          * If the platform has HTI, we need to find out whether it has reserved
8768          * any display resources before we create our display outputs.
8769          */
8770         if (INTEL_INFO(i915)->display.has_hti)
8771                 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
8772
8773         /* Just disable it once at startup */
8774         intel_vga_disable(i915);
8775         intel_setup_outputs(i915);
8776
8777         drm_modeset_lock_all(dev);
8778         intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
8779         intel_acpi_assign_connector_fwnodes(i915);
8780         drm_modeset_unlock_all(dev);
8781
8782         for_each_intel_crtc(dev, crtc) {
8783                 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
8784                         continue;
8785                 intel_crtc_initial_plane_config(crtc);
8786         }
8787
8788         /*
8789          * Make sure hardware watermarks really match the state we read out.
8790          * Note that we need to do this after reconstructing the BIOS fb's
8791          * since the watermark calculation done here will use pstate->fb.
8792          */
8793         if (!HAS_GMCH(i915))
8794                 sanitize_watermarks(i915);
8795
8796         return 0;
8797 }
8798
8799 /* part #3: call after gem init */
8800 int intel_modeset_init(struct drm_i915_private *i915)
8801 {
8802         int ret;
8803
8804         if (!HAS_DISPLAY(i915))
8805                 return 0;
8806
8807         /*
8808          * Force all active planes to recompute their states. So that on
8809          * mode_setcrtc after probe, all the intel_plane_state variables
8810          * are already calculated and there is no assert_plane warnings
8811          * during bootup.
8812          */
8813         ret = intel_initial_commit(&i915->drm);
8814         if (ret)
8815                 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
8816
8817         intel_overlay_setup(i915);
8818
8819         ret = intel_fbdev_init(&i915->drm);
8820         if (ret)
8821                 return ret;
8822
8823         /* Only enable hotplug handling once the fbdev is fully set up. */
8824         intel_hpd_init(i915);
8825         intel_hpd_poll_disable(i915);
8826
8827         intel_init_ipc(i915);
8828
8829         return 0;
8830 }
8831
8832 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8833 {
8834         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8835         /* 640x480@60Hz, ~25175 kHz */
8836         struct dpll clock = {
8837                 .m1 = 18,
8838                 .m2 = 7,
8839                 .p1 = 13,
8840                 .p2 = 4,
8841                 .n = 2,
8842         };
8843         u32 dpll, fp;
8844         int i;
8845
8846         drm_WARN_ON(&dev_priv->drm,
8847                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8848
8849         drm_dbg_kms(&dev_priv->drm,
8850                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8851                     pipe_name(pipe), clock.vco, clock.dot);
8852
8853         fp = i9xx_dpll_compute_fp(&clock);
8854         dpll = DPLL_DVO_2X_MODE |
8855                 DPLL_VGA_MODE_DIS |
8856                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8857                 PLL_P2_DIVIDE_BY_4 |
8858                 PLL_REF_INPUT_DREFCLK |
8859                 DPLL_VCO_ENABLE;
8860
8861         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
8862         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
8863         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
8864         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
8865         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
8866         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
8867         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
8868
8869         intel_de_write(dev_priv, FP0(pipe), fp);
8870         intel_de_write(dev_priv, FP1(pipe), fp);
8871
8872         /*
8873          * Apparently we need to have VGA mode enabled prior to changing
8874          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8875          * dividers, even though the register value does change.
8876          */
8877         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8878         intel_de_write(dev_priv, DPLL(pipe), dpll);
8879
8880         /* Wait for the clocks to stabilize. */
8881         intel_de_posting_read(dev_priv, DPLL(pipe));
8882         udelay(150);
8883
8884         /* The pixel multiplier can only be updated once the
8885          * DPLL is enabled and the clocks are stable.
8886          *
8887          * So write it again.
8888          */
8889         intel_de_write(dev_priv, DPLL(pipe), dpll);
8890
8891         /* We do this three times for luck */
8892         for (i = 0; i < 3 ; i++) {
8893                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8894                 intel_de_posting_read(dev_priv, DPLL(pipe));
8895                 udelay(150); /* wait for warmup */
8896         }
8897
8898         intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
8899         intel_de_posting_read(dev_priv, PIPECONF(pipe));
8900
8901         intel_wait_for_pipe_scanline_moving(crtc);
8902 }
8903
8904 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8905 {
8906         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8907
8908         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8909                     pipe_name(pipe));
8910
8911         drm_WARN_ON(&dev_priv->drm,
8912                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8913         drm_WARN_ON(&dev_priv->drm,
8914                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8915         drm_WARN_ON(&dev_priv->drm,
8916                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8917         drm_WARN_ON(&dev_priv->drm,
8918                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8919         drm_WARN_ON(&dev_priv->drm,
8920                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8921
8922         intel_de_write(dev_priv, PIPECONF(pipe), 0);
8923         intel_de_posting_read(dev_priv, PIPECONF(pipe));
8924
8925         intel_wait_for_pipe_scanline_stopped(crtc);
8926
8927         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8928         intel_de_posting_read(dev_priv, DPLL(pipe));
8929 }
8930
8931 void intel_display_resume(struct drm_device *dev)
8932 {
8933         struct drm_i915_private *i915 = to_i915(dev);
8934         struct drm_atomic_state *state = i915->modeset_restore_state;
8935         struct drm_modeset_acquire_ctx ctx;
8936         int ret;
8937
8938         if (!HAS_DISPLAY(i915))
8939                 return;
8940
8941         i915->modeset_restore_state = NULL;
8942         if (state)
8943                 state->acquire_ctx = &ctx;
8944
8945         drm_modeset_acquire_init(&ctx, 0);
8946
8947         while (1) {
8948                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
8949                 if (ret != -EDEADLK)
8950                         break;
8951
8952                 drm_modeset_backoff(&ctx);
8953         }
8954
8955         if (!ret)
8956                 ret = __intel_display_resume(i915, state, &ctx);
8957
8958         intel_enable_ipc(i915);
8959         drm_modeset_drop_locks(&ctx);
8960         drm_modeset_acquire_fini(&ctx);
8961
8962         if (ret)
8963                 drm_err(&i915->drm,
8964                         "Restoring old state failed with %i\n", ret);
8965         if (state)
8966                 drm_atomic_state_put(state);
8967 }
8968
8969 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
8970 {
8971         struct intel_connector *connector;
8972         struct drm_connector_list_iter conn_iter;
8973
8974         /* Kill all the work that may have been queued by hpd. */
8975         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8976         for_each_intel_connector_iter(connector, &conn_iter) {
8977                 if (connector->modeset_retry_work.func)
8978                         cancel_work_sync(&connector->modeset_retry_work);
8979                 if (connector->hdcp.shim) {
8980                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8981                         cancel_work_sync(&connector->hdcp.prop_work);
8982                 }
8983         }
8984         drm_connector_list_iter_end(&conn_iter);
8985 }
8986
8987 /* part #1: call before irq uninstall */
8988 void intel_modeset_driver_remove(struct drm_i915_private *i915)
8989 {
8990         if (!HAS_DISPLAY(i915))
8991                 return;
8992
8993         flush_workqueue(i915->flip_wq);
8994         flush_workqueue(i915->modeset_wq);
8995
8996         flush_work(&i915->atomic_helper.free_work);
8997         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
8998 }
8999
9000 /* part #2: call after irq uninstall */
9001 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
9002 {
9003         if (!HAS_DISPLAY(i915))
9004                 return;
9005
9006         /*
9007          * Due to the hpd irq storm handling the hotplug work can re-arm the
9008          * poll handlers. Hence disable polling after hpd handling is shut down.
9009          */
9010         intel_hpd_poll_fini(i915);
9011
9012         /*
9013          * MST topology needs to be suspended so we don't have any calls to
9014          * fbdev after it's finalized. MST will be destroyed later as part of
9015          * drm_mode_config_cleanup()
9016          */
9017         intel_dp_mst_suspend(i915);
9018
9019         /* poll work can call into fbdev, hence clean that up afterwards */
9020         intel_fbdev_fini(i915);
9021
9022         intel_unregister_dsm_handler();
9023
9024         /* flush any delayed tasks or pending work */
9025         flush_scheduled_work();
9026
9027         intel_hdcp_component_fini(i915);
9028
9029         intel_mode_config_cleanup(i915);
9030
9031         intel_overlay_cleanup(i915);
9032
9033         intel_gmbus_teardown(i915);
9034
9035         destroy_workqueue(i915->flip_wq);
9036         destroy_workqueue(i915->modeset_wq);
9037
9038         intel_fbc_cleanup(i915);
9039 }
9040
9041 /* part #3: call after gem init */
9042 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
9043 {
9044         intel_dmc_ucode_fini(i915);
9045
9046         intel_power_domains_driver_remove(i915);
9047
9048         intel_vga_unregister(i915);
9049
9050         intel_bios_driver_remove(i915);
9051 }
9052
9053 bool intel_modeset_probe_defer(struct pci_dev *pdev)
9054 {
9055         struct drm_privacy_screen *privacy_screen;
9056
9057         /*
9058          * apple-gmux is needed on dual GPU MacBook Pro
9059          * to probe the panel if we're the inactive GPU.
9060          */
9061         if (vga_switcheroo_client_probe_defer(pdev))
9062                 return true;
9063
9064         /* If the LCD panel has a privacy-screen, wait for it */
9065         privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
9066         if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
9067                 return true;
9068
9069         drm_privacy_screen_put(privacy_screen);
9070
9071         return false;
9072 }
9073
9074 void intel_display_driver_register(struct drm_i915_private *i915)
9075 {
9076         if (!HAS_DISPLAY(i915))
9077                 return;
9078
9079         intel_display_debugfs_register(i915);
9080
9081         /* Must be done after probing outputs */
9082         intel_opregion_register(i915);
9083         acpi_video_register();
9084
9085         intel_audio_init(i915);
9086
9087         /*
9088          * Some ports require correctly set-up hpd registers for
9089          * detection to work properly (leading to ghost connected
9090          * connector status), e.g. VGA on gm45.  Hence we can only set
9091          * up the initial fbdev config after hpd irqs are fully
9092          * enabled. We do it last so that the async config cannot run
9093          * before the connectors are registered.
9094          */
9095         intel_fbdev_initial_config_async(&i915->drm);
9096
9097         /*
9098          * We need to coordinate the hotplugs with the asynchronous
9099          * fbdev configuration, for which we use the
9100          * fbdev->async_cookie.
9101          */
9102         drm_kms_helper_poll_init(&i915->drm);
9103 }
9104
9105 void intel_display_driver_unregister(struct drm_i915_private *i915)
9106 {
9107         if (!HAS_DISPLAY(i915))
9108                 return;
9109
9110         intel_fbdev_unregister(i915);
9111         intel_audio_deinit(i915);
9112
9113         /*
9114          * After flushing the fbdev (incl. a late async config which
9115          * will have delayed queuing of a hotplug event), then flush
9116          * the hotplug events.
9117          */
9118         drm_kms_helper_poll_fini(&i915->drm);
9119         drm_atomic_helper_shutdown(&i915->drm);
9120
9121         acpi_video_unregister();
9122         intel_opregion_unregister(i915);
9123 }
9124
9125 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
9126 {
9127         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
9128 }