2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <acpi/video.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/intel-iommu.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/dma-resv.h>
34 #include <linux/slab.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_damage_helper.h>
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_fourcc.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_rect.h>
47 #include "display/intel_audio.h"
48 #include "display/intel_crt.h"
49 #include "display/intel_ddi.h"
50 #include "display/intel_display_debugfs.h"
51 #include "display/intel_dp.h"
52 #include "display/intel_dp_mst.h"
53 #include "display/intel_dpll.h"
54 #include "display/intel_dpll_mgr.h"
55 #include "display/intel_dsi.h"
56 #include "display/intel_dvo.h"
57 #include "display/intel_gmbus.h"
58 #include "display/intel_hdmi.h"
59 #include "display/intel_lvds.h"
60 #include "display/intel_sdvo.h"
61 #include "display/intel_tv.h"
62 #include "display/intel_vdsc.h"
63 #include "display/intel_vrr.h"
65 #include "gem/i915_gem_object.h"
67 #include "gt/intel_rps.h"
70 #include "intel_acpi.h"
71 #include "intel_atomic.h"
72 #include "intel_atomic_plane.h"
74 #include "intel_cdclk.h"
75 #include "intel_color.h"
76 #include "intel_crtc.h"
77 #include "intel_csr.h"
78 #include "intel_display_types.h"
79 #include "intel_dp_link_training.h"
80 #include "intel_fbc.h"
81 #include "intel_fdi.h"
82 #include "intel_fbdev.h"
83 #include "intel_fifo_underrun.h"
84 #include "intel_frontbuffer.h"
85 #include "intel_hdcp.h"
86 #include "intel_hotplug.h"
87 #include "intel_overlay.h"
88 #include "intel_pipe_crc.h"
90 #include "intel_pps.h"
91 #include "intel_psr.h"
92 #include "intel_quirks.h"
93 #include "intel_sideband.h"
94 #include "intel_sprite.h"
96 #include "intel_vga.h"
97 #include "i9xx_plane.h"
98 #include "skl_scaler.h"
99 #include "skl_universal_plane.h"
101 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
102 struct intel_crtc_state *pipe_config);
103 static void ilk_pch_clock_get(struct intel_crtc *crtc,
104 struct intel_crtc_state *pipe_config);
106 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
107 struct drm_i915_gem_object *obj,
108 struct drm_mode_fb_cmd2 *mode_cmd);
109 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
110 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
111 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
112 const struct intel_link_m_n *m_n,
113 const struct intel_link_m_n *m2_n2);
114 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
115 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
116 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
117 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
118 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
119 static void intel_modeset_setup_hw_state(struct drm_device *dev,
120 struct drm_modeset_acquire_ctx *ctx);
122 /* returns HPLL frequency in kHz */
123 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
125 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
127 /* Obtain SKU information */
128 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
129 CCK_FUSE_HPLL_FREQ_MASK;
131 return vco_freq[hpll_freq] * 1000;
134 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
135 const char *name, u32 reg, int ref_freq)
140 val = vlv_cck_read(dev_priv, reg);
141 divider = val & CCK_FREQUENCY_VALUES;
143 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
144 (divider << CCK_FREQUENCY_STATUS_SHIFT),
145 "%s change in progress\n", name);
147 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
150 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
155 vlv_cck_get(dev_priv);
157 if (dev_priv->hpll_freq == 0)
158 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
160 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
162 vlv_cck_put(dev_priv);
167 static void intel_update_czclk(struct drm_i915_private *dev_priv)
169 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
172 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
173 CCK_CZ_CLOCK_CONTROL);
175 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
176 dev_priv->czclk_freq);
179 /* WA Display #0827: Gen9:all */
181 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
184 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
185 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
187 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
188 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
191 /* Wa_2006604312:icl,ehl */
193 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
197 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
198 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
200 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
201 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
205 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
207 return crtc_state->master_transcoder != INVALID_TRANSCODER;
211 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
213 return crtc_state->sync_mode_slaves_mask != 0;
217 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
219 return is_trans_port_sync_master(crtc_state) ||
220 is_trans_port_sync_slave(crtc_state);
223 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
226 i915_reg_t reg = PIPEDSL(pipe);
230 if (IS_GEN(dev_priv, 2))
231 line_mask = DSL_LINEMASK_GEN2;
233 line_mask = DSL_LINEMASK_GEN3;
235 line1 = intel_de_read(dev_priv, reg) & line_mask;
237 line2 = intel_de_read(dev_priv, reg) & line_mask;
239 return line1 != line2;
242 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
244 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
245 enum pipe pipe = crtc->pipe;
247 /* Wait for the display line to settle/start moving */
248 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
249 drm_err(&dev_priv->drm,
250 "pipe %c scanline %s wait timed out\n",
251 pipe_name(pipe), onoff(state));
254 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
256 wait_for_pipe_scanline_moving(crtc, false);
259 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
261 wait_for_pipe_scanline_moving(crtc, true);
265 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
267 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
268 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
270 if (INTEL_GEN(dev_priv) >= 4) {
271 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
272 i915_reg_t reg = PIPECONF(cpu_transcoder);
274 /* Wait for the Pipe State to go off */
275 if (intel_de_wait_for_clear(dev_priv, reg,
276 I965_PIPECONF_ACTIVE, 100))
277 drm_WARN(&dev_priv->drm, 1,
278 "pipe_off wait timed out\n");
280 intel_wait_for_pipe_scanline_stopped(crtc);
284 /* Only for pre-ILK configs */
285 void assert_pll(struct drm_i915_private *dev_priv,
286 enum pipe pipe, bool state)
291 val = intel_de_read(dev_priv, DPLL(pipe));
292 cur_state = !!(val & DPLL_VCO_ENABLE);
293 I915_STATE_WARN(cur_state != state,
294 "PLL state assertion failure (expected %s, current %s)\n",
295 onoff(state), onoff(cur_state));
298 /* XXX: the dsi pll is shared between MIPI DSI ports */
299 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
304 vlv_cck_get(dev_priv);
305 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
306 vlv_cck_put(dev_priv);
308 cur_state = val & DSI_PLL_VCO_EN;
309 I915_STATE_WARN(cur_state != state,
310 "DSI PLL state assertion failure (expected %s, current %s)\n",
311 onoff(state), onoff(cur_state));
314 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
315 enum pipe pipe, bool state)
319 if (HAS_DDI(dev_priv)) {
321 * DDI does not have a specific FDI_TX register.
323 * FDI is never fed from EDP transcoder
324 * so pipe->transcoder cast is fine here.
326 enum transcoder cpu_transcoder = (enum transcoder)pipe;
327 u32 val = intel_de_read(dev_priv,
328 TRANS_DDI_FUNC_CTL(cpu_transcoder));
329 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
331 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
332 cur_state = !!(val & FDI_TX_ENABLE);
334 I915_STATE_WARN(cur_state != state,
335 "FDI TX state assertion failure (expected %s, current %s)\n",
336 onoff(state), onoff(cur_state));
338 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
339 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
341 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
342 enum pipe pipe, bool state)
347 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
348 cur_state = !!(val & FDI_RX_ENABLE);
349 I915_STATE_WARN(cur_state != state,
350 "FDI RX state assertion failure (expected %s, current %s)\n",
351 onoff(state), onoff(cur_state));
353 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
354 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
356 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
361 /* ILK FDI PLL is always enabled */
362 if (IS_GEN(dev_priv, 5))
365 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
366 if (HAS_DDI(dev_priv))
369 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
370 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
373 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
374 enum pipe pipe, bool state)
379 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
380 cur_state = !!(val & FDI_RX_PLL_ENABLE);
381 I915_STATE_WARN(cur_state != state,
382 "FDI RX PLL assertion failure (expected %s, current %s)\n",
383 onoff(state), onoff(cur_state));
386 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
390 enum pipe panel_pipe = INVALID_PIPE;
393 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
396 if (HAS_PCH_SPLIT(dev_priv)) {
399 pp_reg = PP_CONTROL(0);
400 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
403 case PANEL_PORT_SELECT_LVDS:
404 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
406 case PANEL_PORT_SELECT_DPA:
407 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
409 case PANEL_PORT_SELECT_DPC:
410 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
412 case PANEL_PORT_SELECT_DPD:
413 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
416 MISSING_CASE(port_sel);
419 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
420 /* presumably write lock depends on pipe, not port select */
421 pp_reg = PP_CONTROL(pipe);
426 pp_reg = PP_CONTROL(0);
427 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
429 drm_WARN_ON(&dev_priv->drm,
430 port_sel != PANEL_PORT_SELECT_LVDS);
431 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
434 val = intel_de_read(dev_priv, pp_reg);
435 if (!(val & PANEL_POWER_ON) ||
436 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
439 I915_STATE_WARN(panel_pipe == pipe && locked,
440 "panel assertion failure, pipe %c regs locked\n",
444 void assert_pipe(struct drm_i915_private *dev_priv,
445 enum transcoder cpu_transcoder, bool state)
448 enum intel_display_power_domain power_domain;
449 intel_wakeref_t wakeref;
451 /* we keep both pipes enabled on 830 */
452 if (IS_I830(dev_priv))
455 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
456 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
458 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
459 cur_state = !!(val & PIPECONF_ENABLE);
461 intel_display_power_put(dev_priv, power_domain, wakeref);
466 I915_STATE_WARN(cur_state != state,
467 "transcoder %s assertion failure (expected %s, current %s)\n",
468 transcoder_name(cpu_transcoder),
469 onoff(state), onoff(cur_state));
472 static void assert_plane(struct intel_plane *plane, bool state)
477 cur_state = plane->get_hw_state(plane, &pipe);
479 I915_STATE_WARN(cur_state != state,
480 "%s assertion failure (expected %s, current %s)\n",
481 plane->base.name, onoff(state), onoff(cur_state));
484 #define assert_plane_enabled(p) assert_plane(p, true)
485 #define assert_plane_disabled(p) assert_plane(p, false)
487 static void assert_planes_disabled(struct intel_crtc *crtc)
489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
490 struct intel_plane *plane;
492 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
493 assert_plane_disabled(plane);
496 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
502 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
503 enabled = !!(val & TRANS_ENABLE);
504 I915_STATE_WARN(enabled,
505 "transcoder assertion failed, should be off on pipe %c but is still active\n",
509 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
510 enum pipe pipe, enum port port,
516 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
518 I915_STATE_WARN(state && port_pipe == pipe,
519 "PCH DP %c enabled on transcoder %c, should be disabled\n",
520 port_name(port), pipe_name(pipe));
522 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
523 "IBX PCH DP %c still using transcoder B\n",
527 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
528 enum pipe pipe, enum port port,
534 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
536 I915_STATE_WARN(state && port_pipe == pipe,
537 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
538 port_name(port), pipe_name(pipe));
540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
541 "IBX PCH HDMI %c still using transcoder B\n",
545 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
550 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
551 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
552 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
554 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
556 "PCH VGA enabled on transcoder %c, should be disabled\n",
559 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
561 "PCH LVDS enabled on transcoder %c, should be disabled\n",
564 /* PCH SDVOB multiplex with HDMIB */
565 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
566 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
567 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
570 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
571 struct intel_digital_port *dig_port,
572 unsigned int expected_mask)
577 switch (dig_port->base.port) {
579 port_mask = DPLL_PORTB_READY_MASK;
583 port_mask = DPLL_PORTC_READY_MASK;
588 port_mask = DPLL_PORTD_READY_MASK;
589 dpll_reg = DPIO_PHY_STATUS;
595 if (intel_de_wait_for_register(dev_priv, dpll_reg,
596 port_mask, expected_mask, 1000))
597 drm_WARN(&dev_priv->drm, 1,
598 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
599 dig_port->base.base.base.id, dig_port->base.base.name,
600 intel_de_read(dev_priv, dpll_reg) & port_mask,
604 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
606 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
608 enum pipe pipe = crtc->pipe;
610 u32 val, pipeconf_val;
612 /* Make sure PCH DPLL is enabled */
613 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
615 /* FDI must be feeding us bits for PCH ports */
616 assert_fdi_tx_enabled(dev_priv, pipe);
617 assert_fdi_rx_enabled(dev_priv, pipe);
619 if (HAS_PCH_CPT(dev_priv)) {
620 reg = TRANS_CHICKEN2(pipe);
621 val = intel_de_read(dev_priv, reg);
623 * Workaround: Set the timing override bit
624 * before enabling the pch transcoder.
626 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
627 /* Configure frame start delay to match the CPU */
628 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
629 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
630 intel_de_write(dev_priv, reg, val);
633 reg = PCH_TRANSCONF(pipe);
634 val = intel_de_read(dev_priv, reg);
635 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
637 if (HAS_PCH_IBX(dev_priv)) {
638 /* Configure frame start delay to match the CPU */
639 val &= ~TRANS_FRAME_START_DELAY_MASK;
640 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
643 * Make the BPC in transcoder be consistent with
644 * that in pipeconf reg. For HDMI we must use 8bpc
645 * here for both 8bpc and 12bpc.
647 val &= ~PIPECONF_BPC_MASK;
648 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
649 val |= PIPECONF_8BPC;
651 val |= pipeconf_val & PIPECONF_BPC_MASK;
654 val &= ~TRANS_INTERLACE_MASK;
655 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
656 if (HAS_PCH_IBX(dev_priv) &&
657 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
658 val |= TRANS_LEGACY_INTERLACED_ILK;
660 val |= TRANS_INTERLACED;
662 val |= TRANS_PROGRESSIVE;
665 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
666 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
667 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
671 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
672 enum transcoder cpu_transcoder)
674 u32 val, pipeconf_val;
676 /* FDI must be feeding us bits for PCH ports */
677 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
678 assert_fdi_rx_enabled(dev_priv, PIPE_A);
680 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
681 /* Workaround: set timing override bit. */
682 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
683 /* Configure frame start delay to match the CPU */
684 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
685 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
686 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
689 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
692 PIPECONF_INTERLACED_ILK)
693 val |= TRANS_INTERLACED;
695 val |= TRANS_PROGRESSIVE;
697 intel_de_write(dev_priv, LPT_TRANSCONF, val);
698 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
699 TRANS_STATE_ENABLE, 100))
700 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
703 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
709 /* FDI relies on the transcoder */
710 assert_fdi_tx_disabled(dev_priv, pipe);
711 assert_fdi_rx_disabled(dev_priv, pipe);
713 /* Ports must be off as well */
714 assert_pch_ports_disabled(dev_priv, pipe);
716 reg = PCH_TRANSCONF(pipe);
717 val = intel_de_read(dev_priv, reg);
718 val &= ~TRANS_ENABLE;
719 intel_de_write(dev_priv, reg, val);
720 /* wait for PCH transcoder off, transcoder state */
721 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
722 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
725 if (HAS_PCH_CPT(dev_priv)) {
726 /* Workaround: Clear the timing override chicken bit again. */
727 reg = TRANS_CHICKEN2(pipe);
728 val = intel_de_read(dev_priv, reg);
729 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
730 intel_de_write(dev_priv, reg, val);
734 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
738 val = intel_de_read(dev_priv, LPT_TRANSCONF);
739 val &= ~TRANS_ENABLE;
740 intel_de_write(dev_priv, LPT_TRANSCONF, val);
741 /* wait for PCH transcoder off, transcoder state */
742 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
743 TRANS_STATE_ENABLE, 50))
744 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
746 /* Workaround: clear timing override bit. */
747 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
748 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
749 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
752 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
756 if (HAS_PCH_LPT(dev_priv))
762 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
764 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
766 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
767 enum pipe pipe = crtc->pipe;
771 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
773 assert_planes_disabled(crtc);
776 * A pipe without a PLL won't actually be able to drive bits from
777 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
780 if (HAS_GMCH(dev_priv)) {
781 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
782 assert_dsi_pll_enabled(dev_priv);
784 assert_pll_enabled(dev_priv, pipe);
786 if (new_crtc_state->has_pch_encoder) {
787 /* if driving the PCH, we need FDI enabled */
788 assert_fdi_rx_pll_enabled(dev_priv,
789 intel_crtc_pch_transcoder(crtc));
790 assert_fdi_tx_pll_enabled(dev_priv,
791 (enum pipe) cpu_transcoder);
793 /* FIXME: assert CPU port conditions for SNB+ */
796 reg = PIPECONF(cpu_transcoder);
797 val = intel_de_read(dev_priv, reg);
798 if (val & PIPECONF_ENABLE) {
799 /* we keep both pipes enabled on 830 */
800 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
804 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
805 intel_de_posting_read(dev_priv, reg);
808 * Until the pipe starts PIPEDSL reads will return a stale value,
809 * which causes an apparent vblank timestamp jump when PIPEDSL
810 * resets to its proper value. That also messes up the frame count
811 * when it's derived from the timestamps. So let's wait for the
812 * pipe to start properly before we call drm_crtc_vblank_on()
814 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
815 intel_wait_for_pipe_scanline_moving(crtc);
818 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
820 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
821 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
822 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
823 enum pipe pipe = crtc->pipe;
827 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
830 * Make sure planes won't keep trying to pump pixels to us,
831 * or we might hang the display.
833 assert_planes_disabled(crtc);
835 reg = PIPECONF(cpu_transcoder);
836 val = intel_de_read(dev_priv, reg);
837 if ((val & PIPECONF_ENABLE) == 0)
841 * Double wide has implications for planes
842 * so best keep it disabled when not needed.
844 if (old_crtc_state->double_wide)
845 val &= ~PIPECONF_DOUBLE_WIDE;
847 /* Don't disable pipe or pipe PLLs if needed */
848 if (!IS_I830(dev_priv))
849 val &= ~PIPECONF_ENABLE;
851 intel_de_write(dev_priv, reg, val);
852 if ((val & PIPECONF_ENABLE) == 0)
853 intel_wait_for_pipe_off(old_crtc_state);
856 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
858 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
861 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
863 if (is_ccs_modifier(fb->modifier))
864 return is_ccs_plane(fb, plane);
870 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
873 return info->is_yuv &&
874 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
877 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
880 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
885 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
887 struct drm_i915_private *dev_priv = to_i915(fb->dev);
888 unsigned int cpp = fb->format->cpp[color_plane];
890 switch (fb->modifier) {
891 case DRM_FORMAT_MOD_LINEAR:
892 return intel_tile_size(dev_priv);
893 case I915_FORMAT_MOD_X_TILED:
894 if (IS_GEN(dev_priv, 2))
898 case I915_FORMAT_MOD_Y_TILED_CCS:
899 if (is_ccs_plane(fb, color_plane))
902 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
903 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
904 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
905 if (is_ccs_plane(fb, color_plane))
908 case I915_FORMAT_MOD_Y_TILED:
909 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
913 case I915_FORMAT_MOD_Yf_TILED_CCS:
914 if (is_ccs_plane(fb, color_plane))
917 case I915_FORMAT_MOD_Yf_TILED:
933 MISSING_CASE(fb->modifier);
939 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
941 if (is_gen12_ccs_plane(fb, color_plane))
944 return intel_tile_size(to_i915(fb->dev)) /
945 intel_tile_width_bytes(fb, color_plane);
948 /* Return the tile dimensions in pixel units */
949 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
950 unsigned int *tile_width,
951 unsigned int *tile_height)
953 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
954 unsigned int cpp = fb->format->cpp[color_plane];
956 *tile_width = tile_width_bytes / cpp;
957 *tile_height = intel_tile_height(fb, color_plane);
960 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
963 unsigned int tile_width, tile_height;
965 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
967 return fb->pitches[color_plane] * tile_height;
971 intel_fb_align_height(const struct drm_framebuffer *fb,
972 int color_plane, unsigned int height)
974 unsigned int tile_height = intel_tile_height(fb, color_plane);
976 return ALIGN(height, tile_height);
979 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
981 unsigned int size = 0;
984 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
985 size += rot_info->plane[i].width * rot_info->plane[i].height;
990 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
992 unsigned int size = 0;
995 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
996 size += rem_info->plane[i].width * rem_info->plane[i].height;
1002 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
1003 const struct drm_framebuffer *fb,
1004 unsigned int rotation)
1006 view->type = I915_GGTT_VIEW_NORMAL;
1007 if (drm_rotation_90_or_270(rotation)) {
1008 view->type = I915_GGTT_VIEW_ROTATED;
1009 view->rotated = to_intel_framebuffer(fb)->rot_info;
1013 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
1015 if (IS_I830(dev_priv))
1017 else if (IS_I85X(dev_priv))
1019 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1025 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1027 if (INTEL_GEN(dev_priv) >= 9)
1029 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1030 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1032 else if (INTEL_GEN(dev_priv) >= 4)
1038 static bool has_async_flips(struct drm_i915_private *i915)
1040 return INTEL_GEN(i915) >= 5;
1043 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
1046 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1048 /* AUX_DIST needs only 4K alignment */
1049 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
1050 is_ccs_plane(fb, color_plane))
1053 switch (fb->modifier) {
1054 case DRM_FORMAT_MOD_LINEAR:
1055 return intel_linear_alignment(dev_priv);
1056 case I915_FORMAT_MOD_X_TILED:
1057 if (has_async_flips(dev_priv))
1060 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1061 if (is_semiplanar_uv_plane(fb, color_plane))
1062 return intel_tile_row_size(fb, color_plane);
1064 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1065 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1067 case I915_FORMAT_MOD_Y_TILED_CCS:
1068 case I915_FORMAT_MOD_Yf_TILED_CCS:
1069 case I915_FORMAT_MOD_Y_TILED:
1070 if (INTEL_GEN(dev_priv) >= 12 &&
1071 is_semiplanar_uv_plane(fb, color_plane))
1072 return intel_tile_row_size(fb, color_plane);
1074 case I915_FORMAT_MOD_Yf_TILED:
1075 return 1 * 1024 * 1024;
1077 MISSING_CASE(fb->modifier);
1082 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1084 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1085 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1087 return INTEL_GEN(dev_priv) < 4 ||
1089 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
1093 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1094 const struct i915_ggtt_view *view,
1096 unsigned long *out_flags)
1098 struct drm_device *dev = fb->dev;
1099 struct drm_i915_private *dev_priv = to_i915(dev);
1100 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1101 intel_wakeref_t wakeref;
1102 struct i915_vma *vma;
1103 unsigned int pinctl;
1106 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
1107 return ERR_PTR(-EINVAL);
1109 alignment = intel_surf_alignment(fb, 0);
1110 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
1111 return ERR_PTR(-EINVAL);
1113 /* Note that the w/a also requires 64 PTE of padding following the
1114 * bo. We currently fill all unused PTE with the shadow page and so
1115 * we should always have valid PTE following the scanout preventing
1118 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
1119 alignment = 256 * 1024;
1122 * Global gtt pte registers are special registers which actually forward
1123 * writes to a chunk of system memory. Which means that there is no risk
1124 * that the register values disappear as soon as we call
1125 * intel_runtime_pm_put(), so it is correct to wrap only the
1126 * pin/unpin/fence and not more.
1128 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1130 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1133 * Valleyview is definitely limited to scanning out the first
1134 * 512MiB. Lets presume this behaviour was inherited from the
1135 * g4x display engine and that all earlier gen are similarly
1136 * limited. Testing suggests that it is a little more
1137 * complicated than this. For example, Cherryview appears quite
1138 * happy to scanout from anywhere within its global aperture.
1141 if (HAS_GMCH(dev_priv))
1142 pinctl |= PIN_MAPPABLE;
1144 vma = i915_gem_object_pin_to_display_plane(obj,
1145 alignment, view, pinctl);
1149 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
1153 * Install a fence for tiled scan-out. Pre-i965 always needs a
1154 * fence, whereas 965+ only requires a fence if using
1155 * framebuffer compression. For simplicity, we always, when
1156 * possible, install a fence as the cost is not that onerous.
1158 * If we fail to fence the tiled scanout, then either the
1159 * modeset will reject the change (which is highly unlikely as
1160 * the affected systems, all but one, do not have unmappable
1161 * space) or we will not be able to enable full powersaving
1162 * techniques (also likely not to apply due to various limits
1163 * FBC and the like impose on the size of the buffer, which
1164 * presumably we violated anyway with this unmappable buffer).
1165 * Anyway, it is presumably better to stumble onwards with
1166 * something and try to run the system in a "less than optimal"
1167 * mode that matches the user configuration.
1169 ret = i915_vma_pin_fence(vma);
1170 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
1171 i915_vma_unpin(vma);
1176 if (ret == 0 && vma->fence)
1177 *out_flags |= PLANE_HAS_FENCE;
1182 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1183 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1187 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
1189 if (flags & PLANE_HAS_FENCE)
1190 i915_vma_unpin_fence(vma);
1191 i915_vma_unpin(vma);
1195 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
1196 unsigned int rotation)
1198 if (drm_rotation_90_or_270(rotation))
1199 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
1201 return fb->pitches[color_plane];
1205 * Convert the x/y offsets into a linear offset.
1206 * Only valid with 0/180 degree rotation, which is fine since linear
1207 * offset is only used with linear buffers on pre-hsw and tiled buffers
1208 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1210 u32 intel_fb_xy_to_linear(int x, int y,
1211 const struct intel_plane_state *state,
1214 const struct drm_framebuffer *fb = state->hw.fb;
1215 unsigned int cpp = fb->format->cpp[color_plane];
1216 unsigned int pitch = state->color_plane[color_plane].stride;
1218 return y * pitch + x * cpp;
1222 * Add the x/y offsets derived from fb->offsets[] to the user
1223 * specified plane src x/y offsets. The resulting x/y offsets
1224 * specify the start of scanout from the beginning of the gtt mapping.
1226 void intel_add_fb_offsets(int *x, int *y,
1227 const struct intel_plane_state *state,
1231 *x += state->color_plane[color_plane].x;
1232 *y += state->color_plane[color_plane].y;
1235 static u32 intel_adjust_tile_offset(int *x, int *y,
1236 unsigned int tile_width,
1237 unsigned int tile_height,
1238 unsigned int tile_size,
1239 unsigned int pitch_tiles,
1243 unsigned int pitch_pixels = pitch_tiles * tile_width;
1246 WARN_ON(old_offset & (tile_size - 1));
1247 WARN_ON(new_offset & (tile_size - 1));
1248 WARN_ON(new_offset > old_offset);
1250 tiles = (old_offset - new_offset) / tile_size;
1252 *y += tiles / pitch_tiles * tile_height;
1253 *x += tiles % pitch_tiles * tile_width;
1255 /* minimize x in case it got needlessly big */
1256 *y += *x / pitch_pixels * tile_height;
1262 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
1264 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
1265 is_gen12_ccs_plane(fb, color_plane);
1268 static u32 intel_adjust_aligned_offset(int *x, int *y,
1269 const struct drm_framebuffer *fb,
1271 unsigned int rotation,
1273 u32 old_offset, u32 new_offset)
1275 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1276 unsigned int cpp = fb->format->cpp[color_plane];
1278 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
1280 if (!is_surface_linear(fb, color_plane)) {
1281 unsigned int tile_size, tile_width, tile_height;
1282 unsigned int pitch_tiles;
1284 tile_size = intel_tile_size(dev_priv);
1285 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
1287 if (drm_rotation_90_or_270(rotation)) {
1288 pitch_tiles = pitch / tile_height;
1289 swap(tile_width, tile_height);
1291 pitch_tiles = pitch / (tile_width * cpp);
1294 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1295 tile_size, pitch_tiles,
1296 old_offset, new_offset);
1298 old_offset += *y * pitch + *x * cpp;
1300 *y = (old_offset - new_offset) / pitch;
1301 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
1308 * Adjust the tile offset by moving the difference into
1311 u32 intel_plane_adjust_aligned_offset(int *x, int *y,
1312 const struct intel_plane_state *state,
1314 u32 old_offset, u32 new_offset)
1316 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
1318 state->color_plane[color_plane].stride,
1319 old_offset, new_offset);
1323 * Computes the aligned offset to the base tile and adjusts
1324 * x, y. bytes per pixel is assumed to be a power-of-two.
1326 * In the 90/270 rotated case, x and y are assumed
1327 * to be already rotated to match the rotated GTT view, and
1328 * pitch is the tile_height aligned framebuffer height.
1330 * This function is used when computing the derived information
1331 * under intel_framebuffer, so using any of that information
1332 * here is not allowed. Anything under drm_framebuffer can be
1333 * used. This is why the user has to pass in the pitch since it
1334 * is specified in the rotated orientation.
1336 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
1338 const struct drm_framebuffer *fb,
1341 unsigned int rotation,
1344 unsigned int cpp = fb->format->cpp[color_plane];
1345 u32 offset, offset_aligned;
1347 if (!is_surface_linear(fb, color_plane)) {
1348 unsigned int tile_size, tile_width, tile_height;
1349 unsigned int tile_rows, tiles, pitch_tiles;
1351 tile_size = intel_tile_size(dev_priv);
1352 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
1354 if (drm_rotation_90_or_270(rotation)) {
1355 pitch_tiles = pitch / tile_height;
1356 swap(tile_width, tile_height);
1358 pitch_tiles = pitch / (tile_width * cpp);
1361 tile_rows = *y / tile_height;
1364 tiles = *x / tile_width;
1367 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1369 offset_aligned = offset;
1371 offset_aligned = rounddown(offset_aligned, alignment);
1373 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1374 tile_size, pitch_tiles,
1375 offset, offset_aligned);
1377 offset = *y * pitch + *x * cpp;
1378 offset_aligned = offset;
1380 offset_aligned = rounddown(offset_aligned, alignment);
1381 *y = (offset % alignment) / pitch;
1382 *x = ((offset % alignment) - *y * pitch) / cpp;
1388 return offset_aligned;
1391 u32 intel_plane_compute_aligned_offset(int *x, int *y,
1392 const struct intel_plane_state *state,
1395 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
1396 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
1397 const struct drm_framebuffer *fb = state->hw.fb;
1398 unsigned int rotation = state->hw.rotation;
1399 int pitch = state->color_plane[color_plane].stride;
1402 if (intel_plane->id == PLANE_CURSOR)
1403 alignment = intel_cursor_alignment(dev_priv);
1405 alignment = intel_surf_alignment(fb, color_plane);
1407 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
1408 pitch, rotation, alignment);
1411 /* Convert the fb->offset[] into x/y offsets */
1412 static int intel_fb_offset_to_xy(int *x, int *y,
1413 const struct drm_framebuffer *fb,
1416 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1417 unsigned int height;
1420 if (INTEL_GEN(dev_priv) >= 12 &&
1421 is_semiplanar_uv_plane(fb, color_plane))
1422 alignment = intel_tile_row_size(fb, color_plane);
1423 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1424 alignment = intel_tile_size(dev_priv);
1428 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1429 drm_dbg_kms(&dev_priv->drm,
1430 "Misaligned offset 0x%08x for color plane %d\n",
1431 fb->offsets[color_plane], color_plane);
1435 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
1436 height = ALIGN(height, intel_tile_height(fb, color_plane));
1438 /* Catch potential overflows early */
1439 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
1440 fb->offsets[color_plane])) {
1441 drm_dbg_kms(&dev_priv->drm,
1442 "Bad offset 0x%08x or pitch %d for color plane %d\n",
1443 fb->offsets[color_plane], fb->pitches[color_plane],
1451 intel_adjust_aligned_offset(x, y,
1452 fb, color_plane, DRM_MODE_ROTATE_0,
1453 fb->pitches[color_plane],
1454 fb->offsets[color_plane], 0);
1459 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
1461 switch (fb_modifier) {
1462 case I915_FORMAT_MOD_X_TILED:
1463 return I915_TILING_X;
1464 case I915_FORMAT_MOD_Y_TILED:
1465 case I915_FORMAT_MOD_Y_TILED_CCS:
1466 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1467 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1468 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1469 return I915_TILING_Y;
1471 return I915_TILING_NONE;
1476 * From the Sky Lake PRM:
1477 * "The Color Control Surface (CCS) contains the compression status of
1478 * the cache-line pairs. The compression state of the cache-line pair
1479 * is specified by 2 bits in the CCS. Each CCS cache-line represents
1480 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1481 * cache-line-pairs. CCS is always Y tiled."
1483 * Since cache line pairs refers to horizontally adjacent cache lines,
1484 * each cache line in the CCS corresponds to an area of 32x16 cache
1485 * lines on the main surface. Since each pixel is 4 bytes, this gives
1486 * us a ratio of one byte in the CCS for each 8x16 pixels in the
1489 static const struct drm_format_info skl_ccs_formats[] = {
1490 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1491 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1492 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1493 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1494 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1495 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1496 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1497 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1501 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1502 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1503 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1504 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1507 static const struct drm_format_info gen12_ccs_formats[] = {
1508 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1509 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1510 .hsub = 1, .vsub = 1, },
1511 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1512 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1513 .hsub = 1, .vsub = 1, },
1514 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1515 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1516 .hsub = 1, .vsub = 1, .has_alpha = true },
1517 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1518 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1519 .hsub = 1, .vsub = 1, .has_alpha = true },
1520 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
1521 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1522 .hsub = 2, .vsub = 1, .is_yuv = true },
1523 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
1524 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1525 .hsub = 2, .vsub = 1, .is_yuv = true },
1526 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
1527 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1528 .hsub = 2, .vsub = 1, .is_yuv = true },
1529 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
1530 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1531 .hsub = 2, .vsub = 1, .is_yuv = true },
1532 { .format = DRM_FORMAT_NV12, .num_planes = 4,
1533 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
1534 .hsub = 2, .vsub = 2, .is_yuv = true },
1535 { .format = DRM_FORMAT_P010, .num_planes = 4,
1536 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1537 .hsub = 2, .vsub = 2, .is_yuv = true },
1538 { .format = DRM_FORMAT_P012, .num_planes = 4,
1539 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1540 .hsub = 2, .vsub = 2, .is_yuv = true },
1541 { .format = DRM_FORMAT_P016, .num_planes = 4,
1542 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1543 .hsub = 2, .vsub = 2, .is_yuv = true },
1547 * Same as gen12_ccs_formats[] above, but with additional surface used
1548 * to pass Clear Color information in plane 2 with 64 bits of data.
1550 static const struct drm_format_info gen12_ccs_cc_formats[] = {
1551 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
1552 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1553 .hsub = 1, .vsub = 1, },
1554 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
1555 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1556 .hsub = 1, .vsub = 1, },
1557 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
1558 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1559 .hsub = 1, .vsub = 1, .has_alpha = true },
1560 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
1561 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1562 .hsub = 1, .vsub = 1, .has_alpha = true },
1565 static const struct drm_format_info *
1566 lookup_format_info(const struct drm_format_info formats[],
1567 int num_formats, u32 format)
1571 for (i = 0; i < num_formats; i++) {
1572 if (formats[i].format == format)
1579 static const struct drm_format_info *
1580 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
1582 switch (cmd->modifier[0]) {
1583 case I915_FORMAT_MOD_Y_TILED_CCS:
1584 case I915_FORMAT_MOD_Yf_TILED_CCS:
1585 return lookup_format_info(skl_ccs_formats,
1586 ARRAY_SIZE(skl_ccs_formats),
1588 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1589 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1590 return lookup_format_info(gen12_ccs_formats,
1591 ARRAY_SIZE(gen12_ccs_formats),
1593 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1594 return lookup_format_info(gen12_ccs_cc_formats,
1595 ARRAY_SIZE(gen12_ccs_cc_formats),
1602 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
1604 return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
1608 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
1609 u32 pixel_format, u64 modifier)
1611 struct intel_crtc *crtc;
1612 struct intel_plane *plane;
1615 * We assume the primary plane for pipe A has
1616 * the highest stride limits of them all,
1617 * if in case pipe A is disabled, use the first pipe from pipe_mask.
1619 crtc = intel_get_first_crtc(dev_priv);
1623 plane = to_intel_plane(crtc->base.primary);
1625 return plane->max_stride(plane, pixel_format, modifier,
1630 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1631 u32 pixel_format, u64 modifier)
1634 * Arbitrary limit for gen4+ chosen to match the
1635 * render engine max stride.
1637 * The new CCS hash mode makes remapping impossible
1639 if (!is_ccs_modifier(modifier)) {
1640 if (INTEL_GEN(dev_priv) >= 7)
1642 else if (INTEL_GEN(dev_priv) >= 4)
1646 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1650 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1652 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1655 if (is_surface_linear(fb, color_plane)) {
1656 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1661 * To make remapping with linear generally feasible
1662 * we need the stride to be page aligned.
1664 if (fb->pitches[color_plane] > max_stride &&
1665 !is_ccs_modifier(fb->modifier))
1666 return intel_tile_size(dev_priv);
1671 tile_width = intel_tile_width_bytes(fb, color_plane);
1672 if (is_ccs_modifier(fb->modifier)) {
1674 * Display WA #0531: skl,bxt,kbl,glk
1676 * Render decompression and plane width > 3840
1677 * combined with horizontal panning requires the
1678 * plane stride to be a multiple of 4. We'll just
1679 * require the entire fb to accommodate that to avoid
1680 * potential runtime errors at plane configuration time.
1682 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
1685 * The main surface pitch must be padded to a multiple of four
1688 else if (INTEL_GEN(dev_priv) >= 12)
1694 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1696 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1697 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1698 const struct drm_framebuffer *fb = plane_state->hw.fb;
1701 /* We don't want to deal with remapping with cursors */
1702 if (plane->id == PLANE_CURSOR)
1706 * The display engine limits already match/exceed the
1707 * render engine limits, so not much point in remapping.
1708 * Would also need to deal with the fence POT alignment
1709 * and gen2 2KiB GTT tile size.
1711 if (INTEL_GEN(dev_priv) < 4)
1715 * The new CCS hash mode isn't compatible with remapping as
1716 * the virtual address of the pages affects the compressed data.
1718 if (is_ccs_modifier(fb->modifier))
1721 /* Linear needs a page aligned stride for remapping */
1722 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1723 unsigned int alignment = intel_tile_size(dev_priv) - 1;
1725 for (i = 0; i < fb->format->num_planes; i++) {
1726 if (fb->pitches[i] & alignment)
1734 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
1736 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1737 const struct drm_framebuffer *fb = plane_state->hw.fb;
1738 unsigned int rotation = plane_state->hw.rotation;
1739 u32 stride, max_stride;
1742 * No remapping for invisible planes since we don't have
1743 * an actual source viewport to remap.
1745 if (!plane_state->uapi.visible)
1748 if (!intel_plane_can_remap(plane_state))
1752 * FIXME: aux plane limits on gen9+ are
1753 * unclear in Bspec, for now no checking.
1755 stride = intel_fb_pitch(fb, 0, rotation);
1756 max_stride = plane->max_stride(plane, fb->format->format,
1757 fb->modifier, rotation);
1759 return stride > max_stride;
1763 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
1764 const struct drm_framebuffer *fb,
1769 if (color_plane == 0) {
1777 * TODO: Deduct the subsampling from the char block for all CCS
1778 * formats and planes.
1780 if (!is_gen12_ccs_plane(fb, color_plane)) {
1781 *hsub = fb->format->hsub;
1782 *vsub = fb->format->vsub;
1787 main_plane = skl_ccs_to_main_plane(fb, color_plane);
1788 *hsub = drm_format_info_block_width(fb->format, color_plane) /
1789 drm_format_info_block_width(fb->format, main_plane);
1792 * The min stride check in the core framebuffer_check() function
1793 * assumes that format->hsub applies to every plane except for the
1794 * first plane. That's incorrect for the CCS AUX plane of the first
1795 * plane, but for the above check to pass we must define the block
1796 * width with that subsampling applied to it. Adjust the width here
1797 * accordingly, so we can calculate the actual subsampling factor.
1799 if (main_plane == 0)
1800 *hsub *= fb->format->hsub;
1805 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
1807 struct drm_i915_private *i915 = to_i915(fb->dev);
1808 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1811 int tile_width, tile_height;
1815 if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
1818 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
1819 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1822 tile_height *= vsub;
1824 ccs_x = (x * hsub) % tile_width;
1825 ccs_y = (y * vsub) % tile_height;
1827 main_plane = skl_ccs_to_main_plane(fb, ccs_plane);
1828 main_x = intel_fb->normal[main_plane].x % tile_width;
1829 main_y = intel_fb->normal[main_plane].y % tile_height;
1832 * CCS doesn't have its own x/y offset register, so the intra CCS tile
1833 * x/y offsets must match between CCS and the main surface.
1835 if (main_x != ccs_x || main_y != ccs_y) {
1836 drm_dbg_kms(&i915->drm,
1837 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
1840 intel_fb->normal[main_plane].x,
1841 intel_fb->normal[main_plane].y,
1850 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
1852 int main_plane = is_ccs_plane(fb, color_plane) ?
1853 skl_ccs_to_main_plane(fb, color_plane) : 0;
1854 int main_hsub, main_vsub;
1857 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
1858 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
1859 *w = fb->width / main_hsub / hsub;
1860 *h = fb->height / main_vsub / vsub;
1864 * Setup the rotated view for an FB plane and return the size the GTT mapping
1865 * requires for this view.
1868 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
1869 u32 gtt_offset_rotated, int x, int y,
1870 unsigned int width, unsigned int height,
1871 unsigned int tile_size,
1872 unsigned int tile_width, unsigned int tile_height,
1873 struct drm_framebuffer *fb)
1875 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1876 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
1877 unsigned int pitch_tiles;
1880 /* Y or Yf modifiers required for 90/270 rotation */
1881 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1882 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
1885 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
1888 rot_info->plane[plane] = *plane_info;
1890 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
1892 /* rotate the x/y offsets to match the GTT view */
1893 drm_rect_init(&r, x, y, width, height);
1895 plane_info->width * tile_width,
1896 plane_info->height * tile_height,
1897 DRM_MODE_ROTATE_270);
1901 /* rotate the tile dimensions to match the GTT view */
1902 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
1903 swap(tile_width, tile_height);
1906 * We only keep the x/y offsets, so push all of the
1907 * gtt offset into the x/y offsets.
1909 intel_adjust_tile_offset(&x, &y,
1910 tile_width, tile_height,
1911 tile_size, pitch_tiles,
1912 gtt_offset_rotated * tile_size, 0);
1915 * First pixel of the framebuffer from
1916 * the start of the rotated gtt mapping.
1918 intel_fb->rotated[plane].x = x;
1919 intel_fb->rotated[plane].y = y;
1921 return plane_info->width * plane_info->height;
1925 intel_fill_fb_info(struct drm_i915_private *dev_priv,
1926 struct drm_framebuffer *fb)
1928 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1929 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1930 u32 gtt_offset_rotated = 0;
1931 unsigned int max_size = 0;
1932 int i, num_planes = fb->format->num_planes;
1933 unsigned int tile_size = intel_tile_size(dev_priv);
1935 for (i = 0; i < num_planes; i++) {
1936 unsigned int width, height;
1937 unsigned int cpp, size;
1943 * Plane 2 of Render Compression with Clear Color fb modifier
1944 * is consumed by the driver and not passed to DE. Skip the
1945 * arithmetic related to alignment and offset calculation.
1947 if (is_gen12_ccs_cc_plane(fb, i)) {
1948 if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
1954 cpp = fb->format->cpp[i];
1955 intel_fb_plane_dims(&width, &height, fb, i);
1957 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
1959 drm_dbg_kms(&dev_priv->drm,
1960 "bad fb plane %d offset: 0x%x\n",
1965 ret = intel_fb_check_ccs_xy(fb, i, x, y);
1970 * The fence (if used) is aligned to the start of the object
1971 * so having the framebuffer wrap around across the edge of the
1972 * fenced region doesn't really work. We have no API to configure
1973 * the fence start offset within the object (nor could we probably
1974 * on gen2/3). So it's just easier if we just require that the
1975 * fb layout agrees with the fence layout. We already check that the
1976 * fb stride matches the fence stride elsewhere.
1978 if (i == 0 && i915_gem_object_is_tiled(obj) &&
1979 (x + width) * cpp > fb->pitches[i]) {
1980 drm_dbg_kms(&dev_priv->drm,
1981 "bad fb plane %d offset: 0x%x\n",
1987 * First pixel of the framebuffer from
1988 * the start of the normal gtt mapping.
1990 intel_fb->normal[i].x = x;
1991 intel_fb->normal[i].y = y;
1993 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
1997 offset /= tile_size;
1999 if (!is_surface_linear(fb, i)) {
2000 struct intel_remapped_plane_info plane_info;
2001 unsigned int tile_width, tile_height;
2003 intel_tile_dims(fb, i, &tile_width, &tile_height);
2005 plane_info.offset = offset;
2006 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
2008 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
2009 plane_info.height = DIV_ROUND_UP(y + height,
2012 /* how many tiles does this plane need */
2013 size = plane_info.stride * plane_info.height;
2015 * If the plane isn't horizontally tile aligned,
2016 * we need one more tile.
2021 gtt_offset_rotated +=
2022 setup_fb_rotation(i, &plane_info,
2024 x, y, width, height,
2026 tile_width, tile_height,
2029 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2030 x * cpp, tile_size);
2033 /* how many tiles in total needed in the bo */
2034 max_size = max(max_size, offset + size);
2037 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2038 drm_dbg_kms(&dev_priv->drm,
2039 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
2040 mul_u32_u32(max_size, tile_size), obj->base.size);
2048 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2050 struct drm_i915_private *dev_priv =
2051 to_i915(plane_state->uapi.plane->dev);
2052 struct drm_framebuffer *fb = plane_state->hw.fb;
2053 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2054 struct intel_rotation_info *info = &plane_state->view.rotated;
2055 unsigned int rotation = plane_state->hw.rotation;
2056 int i, num_planes = fb->format->num_planes;
2057 unsigned int tile_size = intel_tile_size(dev_priv);
2058 unsigned int src_x, src_y;
2059 unsigned int src_w, src_h;
2062 memset(&plane_state->view, 0, sizeof(plane_state->view));
2063 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2064 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2066 src_x = plane_state->uapi.src.x1 >> 16;
2067 src_y = plane_state->uapi.src.y1 >> 16;
2068 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2069 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2071 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
2073 /* Make src coordinates relative to the viewport */
2074 drm_rect_translate(&plane_state->uapi.src,
2075 -(src_x << 16), -(src_y << 16));
2077 /* Rotate src coordinates to match rotated GTT view */
2078 if (drm_rotation_90_or_270(rotation))
2079 drm_rect_rotate(&plane_state->uapi.src,
2080 src_w << 16, src_h << 16,
2081 DRM_MODE_ROTATE_270);
2083 for (i = 0; i < num_planes; i++) {
2084 unsigned int hsub = i ? fb->format->hsub : 1;
2085 unsigned int vsub = i ? fb->format->vsub : 1;
2086 unsigned int cpp = fb->format->cpp[i];
2087 unsigned int tile_width, tile_height;
2088 unsigned int width, height;
2089 unsigned int pitch_tiles;
2093 intel_tile_dims(fb, i, &tile_width, &tile_height);
2097 width = src_w / hsub;
2098 height = src_h / vsub;
2101 * First pixel of the src viewport from the
2102 * start of the normal gtt mapping.
2104 x += intel_fb->normal[i].x;
2105 y += intel_fb->normal[i].y;
2107 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2108 fb, i, fb->pitches[i],
2109 DRM_MODE_ROTATE_0, tile_size);
2110 offset /= tile_size;
2112 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
2113 info->plane[i].offset = offset;
2114 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2116 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2117 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2119 if (drm_rotation_90_or_270(rotation)) {
2122 /* rotate the x/y offsets to match the GTT view */
2123 drm_rect_init(&r, x, y, width, height);
2125 info->plane[i].width * tile_width,
2126 info->plane[i].height * tile_height,
2127 DRM_MODE_ROTATE_270);
2131 pitch_tiles = info->plane[i].height;
2132 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2134 /* rotate the tile dimensions to match the GTT view */
2135 swap(tile_width, tile_height);
2137 pitch_tiles = info->plane[i].width;
2138 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2142 * We only keep the x/y offsets, so push all of the
2143 * gtt offset into the x/y offsets.
2145 intel_adjust_tile_offset(&x, &y,
2146 tile_width, tile_height,
2147 tile_size, pitch_tiles,
2148 gtt_offset * tile_size, 0);
2150 gtt_offset += info->plane[i].width * info->plane[i].height;
2152 plane_state->color_plane[i].offset = 0;
2153 plane_state->color_plane[i].x = x;
2154 plane_state->color_plane[i].y = y;
2159 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2161 const struct intel_framebuffer *fb =
2162 to_intel_framebuffer(plane_state->hw.fb);
2163 unsigned int rotation = plane_state->hw.rotation;
2169 num_planes = fb->base.format->num_planes;
2171 if (intel_plane_needs_remap(plane_state)) {
2172 intel_plane_remap_gtt(plane_state);
2175 * Sometimes even remapping can't overcome
2176 * the stride limitations :( Can happen with
2177 * big plane sizes and suitably misaligned
2180 return intel_plane_check_stride(plane_state);
2183 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2185 for (i = 0; i < num_planes; i++) {
2186 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2187 plane_state->color_plane[i].offset = 0;
2189 if (drm_rotation_90_or_270(rotation)) {
2190 plane_state->color_plane[i].x = fb->rotated[i].x;
2191 plane_state->color_plane[i].y = fb->rotated[i].y;
2193 plane_state->color_plane[i].x = fb->normal[i].x;
2194 plane_state->color_plane[i].y = fb->normal[i].y;
2198 /* Rotate src coordinates to match rotated GTT view */
2199 if (drm_rotation_90_or_270(rotation))
2200 drm_rect_rotate(&plane_state->uapi.src,
2201 fb->base.width << 16, fb->base.height << 16,
2202 DRM_MODE_ROTATE_270);
2204 return intel_plane_check_stride(plane_state);
2207 static struct i915_vma *
2208 initial_plane_vma(struct drm_i915_private *i915,
2209 struct intel_initial_plane_config *plane_config)
2211 struct drm_i915_gem_object *obj;
2212 struct i915_vma *vma;
2215 if (plane_config->size == 0)
2218 base = round_down(plane_config->base,
2219 I915_GTT_MIN_ALIGNMENT);
2220 size = round_up(plane_config->base + plane_config->size,
2221 I915_GTT_MIN_ALIGNMENT);
2225 * If the FB is too big, just don't use it since fbdev is not very
2226 * important and we should probably use that space with FBC or other
2229 if (size * 2 > i915->stolen_usable_size)
2232 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
2237 * Mark it WT ahead of time to avoid changing the
2238 * cache_level during fbdev initialization. The
2239 * unbind there would get stuck waiting for rcu.
2241 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
2242 I915_CACHE_WT : I915_CACHE_NONE);
2244 switch (plane_config->tiling) {
2245 case I915_TILING_NONE:
2249 obj->tiling_and_stride =
2250 plane_config->fb->base.pitches[0] |
2251 plane_config->tiling;
2254 MISSING_CASE(plane_config->tiling);
2258 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
2262 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
2265 if (i915_gem_object_is_tiled(obj) &&
2266 !i915_vma_is_map_and_fenceable(vma))
2272 i915_gem_object_put(obj);
2277 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2278 struct intel_initial_plane_config *plane_config)
2280 struct drm_device *dev = crtc->base.dev;
2281 struct drm_i915_private *dev_priv = to_i915(dev);
2282 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2283 struct drm_framebuffer *fb = &plane_config->fb->base;
2284 struct i915_vma *vma;
2286 switch (fb->modifier) {
2287 case DRM_FORMAT_MOD_LINEAR:
2288 case I915_FORMAT_MOD_X_TILED:
2289 case I915_FORMAT_MOD_Y_TILED:
2292 drm_dbg(&dev_priv->drm,
2293 "Unsupported modifier for initial FB: 0x%llx\n",
2298 vma = initial_plane_vma(dev_priv, plane_config);
2302 mode_cmd.pixel_format = fb->format->format;
2303 mode_cmd.width = fb->width;
2304 mode_cmd.height = fb->height;
2305 mode_cmd.pitches[0] = fb->pitches[0];
2306 mode_cmd.modifier[0] = fb->modifier;
2307 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2309 if (intel_framebuffer_init(to_intel_framebuffer(fb),
2310 vma->obj, &mode_cmd)) {
2311 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
2315 plane_config->vma = vma;
2324 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2325 struct intel_plane_state *plane_state,
2328 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2330 plane_state->uapi.visible = visible;
2333 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
2335 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
2338 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
2340 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2341 struct drm_plane *plane;
2344 * Active_planes aliases if multiple "primary" or cursor planes
2345 * have been used on the same (or wrong) pipe. plane_mask uses
2346 * unique ids, hence we can use that to reconstruct active_planes.
2348 crtc_state->enabled_planes = 0;
2349 crtc_state->active_planes = 0;
2351 drm_for_each_plane_mask(plane, &dev_priv->drm,
2352 crtc_state->uapi.plane_mask) {
2353 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
2354 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2358 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2359 struct intel_plane *plane)
2361 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2362 struct intel_crtc_state *crtc_state =
2363 to_intel_crtc_state(crtc->base.state);
2364 struct intel_plane_state *plane_state =
2365 to_intel_plane_state(plane->base.state);
2367 drm_dbg_kms(&dev_priv->drm,
2368 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2369 plane->base.base.id, plane->base.name,
2370 crtc->base.base.id, crtc->base.name);
2372 intel_set_plane_visible(crtc_state, plane_state, false);
2373 fixup_plane_bitmasks(crtc_state);
2374 crtc_state->data_rate[plane->id] = 0;
2375 crtc_state->min_cdclk[plane->id] = 0;
2377 if (plane->id == PLANE_PRIMARY)
2378 hsw_disable_ips(crtc_state);
2381 * Vblank time updates from the shadow to live plane control register
2382 * are blocked if the memory self-refresh mode is active at that
2383 * moment. So to make sure the plane gets truly disabled, disable
2384 * first the self-refresh mode. The self-refresh enable bit in turn
2385 * will be checked/applied by the HW only at the next frame start
2386 * event which is after the vblank start event, so we need to have a
2387 * wait-for-vblank between disabling the plane and the pipe.
2389 if (HAS_GMCH(dev_priv) &&
2390 intel_set_memory_cxsr(dev_priv, false))
2391 intel_wait_for_vblank(dev_priv, crtc->pipe);
2394 * Gen2 reports pipe underruns whenever all planes are disabled.
2395 * So disable underrun reporting before all the planes get disabled.
2397 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
2398 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
2400 intel_disable_plane(plane, crtc_state);
2401 intel_wait_for_vblank(dev_priv, crtc->pipe);
2405 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2406 struct intel_initial_plane_config *plane_config)
2408 struct drm_device *dev = intel_crtc->base.dev;
2409 struct drm_i915_private *dev_priv = to_i915(dev);
2411 struct drm_plane *primary = intel_crtc->base.primary;
2412 struct drm_plane_state *plane_state = primary->state;
2413 struct intel_plane *intel_plane = to_intel_plane(primary);
2414 struct intel_plane_state *intel_state =
2415 to_intel_plane_state(plane_state);
2416 struct intel_crtc_state *crtc_state =
2417 to_intel_crtc_state(intel_crtc->base.state);
2418 struct drm_framebuffer *fb;
2419 struct i915_vma *vma;
2421 if (!plane_config->fb)
2424 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2425 fb = &plane_config->fb->base;
2426 vma = plane_config->vma;
2431 * Failed to alloc the obj, check to see if we should share
2432 * an fb with another CRTC instead
2434 for_each_crtc(dev, c) {
2435 struct intel_plane_state *state;
2437 if (c == &intel_crtc->base)
2440 if (!to_intel_crtc_state(c->state)->uapi.active)
2443 state = to_intel_plane_state(c->primary->state);
2447 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2455 * We've failed to reconstruct the BIOS FB. Current display state
2456 * indicates that the primary plane is visible, but has a NULL FB,
2457 * which will lead to problems later if we don't fix it up. The
2458 * simplest solution is to just disable the primary plane now and
2459 * pretend the BIOS never had it enabled.
2461 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2462 if (crtc_state->bigjoiner) {
2463 struct intel_crtc *slave =
2464 crtc_state->bigjoiner_linked_crtc;
2465 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
2471 intel_state->hw.rotation = plane_config->rotation;
2472 intel_fill_fb_ggtt_view(&intel_state->view, fb,
2473 intel_state->hw.rotation);
2474 intel_state->color_plane[0].stride =
2475 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
2477 __i915_vma_pin(vma);
2478 intel_state->vma = i915_vma_get(vma);
2479 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
2481 intel_state->flags |= PLANE_HAS_FENCE;
2483 plane_state->src_x = 0;
2484 plane_state->src_y = 0;
2485 plane_state->src_w = fb->width << 16;
2486 plane_state->src_h = fb->height << 16;
2488 plane_state->crtc_x = 0;
2489 plane_state->crtc_y = 0;
2490 plane_state->crtc_w = fb->width;
2491 plane_state->crtc_h = fb->height;
2493 intel_state->uapi.src = drm_plane_state_src(plane_state);
2494 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
2496 if (plane_config->tiling)
2497 dev_priv->preserve_bios_swizzle = true;
2499 plane_state->fb = fb;
2500 drm_framebuffer_get(fb);
2502 plane_state->crtc = &intel_crtc->base;
2503 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state,
2506 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
2508 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2509 &to_intel_frontbuffer(fb)->bits);
2513 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
2517 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
2518 plane_state->color_plane[0].offset, 0);
2524 __intel_display_resume(struct drm_device *dev,
2525 struct drm_atomic_state *state,
2526 struct drm_modeset_acquire_ctx *ctx)
2528 struct drm_crtc_state *crtc_state;
2529 struct drm_crtc *crtc;
2532 intel_modeset_setup_hw_state(dev, ctx);
2533 intel_vga_redisable(to_i915(dev));
2539 * We've duplicated the state, pointers to the old state are invalid.
2541 * Don't attempt to use the old state until we commit the duplicated state.
2543 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
2545 * Force recalculation even if we restore
2546 * current state. With fast modeset this may not result
2547 * in a modeset when the state is compatible.
2549 crtc_state->mode_changed = true;
2552 /* ignore any reset values/BIOS leftovers in the WM registers */
2553 if (!HAS_GMCH(to_i915(dev)))
2554 to_intel_atomic_state(state)->skip_intermediate_wm = true;
2556 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
2558 drm_WARN_ON(dev, ret == -EDEADLK);
2562 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
2564 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
2565 intel_has_gpu_reset(&dev_priv->gt));
2568 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
2570 struct drm_device *dev = &dev_priv->drm;
2571 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2572 struct drm_atomic_state *state;
2575 if (!HAS_DISPLAY(dev_priv))
2578 /* reset doesn't touch the display */
2579 if (!dev_priv->params.force_reset_modeset_test &&
2580 !gpu_reset_clobbers_display(dev_priv))
2583 /* We have a modeset vs reset deadlock, defensively unbreak it. */
2584 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2585 smp_mb__after_atomic();
2586 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
2588 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
2589 drm_dbg_kms(&dev_priv->drm,
2590 "Modeset potentially stuck, unbreaking through wedging\n");
2591 intel_gt_set_wedged(&dev_priv->gt);
2595 * Need mode_config.mutex so that we don't
2596 * trample ongoing ->detect() and whatnot.
2598 mutex_lock(&dev->mode_config.mutex);
2599 drm_modeset_acquire_init(ctx, 0);
2601 ret = drm_modeset_lock_all_ctx(dev, ctx);
2602 if (ret != -EDEADLK)
2605 drm_modeset_backoff(ctx);
2608 * Disabling the crtcs gracefully seems nicer. Also the
2609 * g33 docs say we should at least disable all the planes.
2611 state = drm_atomic_helper_duplicate_state(dev, ctx);
2612 if (IS_ERR(state)) {
2613 ret = PTR_ERR(state);
2614 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
2619 ret = drm_atomic_helper_disable_all(dev, ctx);
2621 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2623 drm_atomic_state_put(state);
2627 dev_priv->modeset_restore_state = state;
2628 state->acquire_ctx = ctx;
2631 void intel_display_finish_reset(struct drm_i915_private *dev_priv)
2633 struct drm_device *dev = &dev_priv->drm;
2634 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2635 struct drm_atomic_state *state;
2638 if (!HAS_DISPLAY(dev_priv))
2641 /* reset doesn't touch the display */
2642 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
2645 state = fetch_and_zero(&dev_priv->modeset_restore_state);
2649 /* reset doesn't touch the display */
2650 if (!gpu_reset_clobbers_display(dev_priv)) {
2651 /* for testing only restore the display */
2652 ret = __intel_display_resume(dev, state, ctx);
2654 drm_err(&dev_priv->drm,
2655 "Restoring old state failed with %i\n", ret);
2658 * The display has been reset as well,
2659 * so need a full re-initialization.
2661 intel_pps_unlock_regs_wa(dev_priv);
2662 intel_modeset_init_hw(dev_priv);
2663 intel_init_clock_gating(dev_priv);
2664 intel_hpd_init(dev_priv);
2666 ret = __intel_display_resume(dev, state, ctx);
2668 drm_err(&dev_priv->drm,
2669 "Restoring old state failed with %i\n", ret);
2671 intel_hpd_poll_disable(dev_priv);
2674 drm_atomic_state_put(state);
2676 drm_modeset_drop_locks(ctx);
2677 drm_modeset_acquire_fini(ctx);
2678 mutex_unlock(&dev->mode_config.mutex);
2680 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2683 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
2685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2686 enum pipe pipe = crtc->pipe;
2689 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
2692 * Display WA #1153: icl
2693 * enable hardware to bypass the alpha math
2694 * and rounding for per-pixel values 00 and 0xff
2696 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
2698 * Display WA # 1605353570: icl
2699 * Set the pixel rounding bit to 1 for allowing
2700 * passthrough of Frame buffer pixels unmodified
2703 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
2704 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
2707 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
2709 struct drm_crtc *crtc;
2712 drm_for_each_crtc(crtc, &dev_priv->drm) {
2713 struct drm_crtc_commit *commit;
2714 spin_lock(&crtc->commit_lock);
2715 commit = list_first_entry_or_null(&crtc->commit_list,
2716 struct drm_crtc_commit, commit_entry);
2717 cleanup_done = commit ?
2718 try_wait_for_completion(&commit->cleanup_done) : true;
2719 spin_unlock(&crtc->commit_lock);
2724 drm_crtc_wait_one_vblank(crtc);
2732 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
2736 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
2738 mutex_lock(&dev_priv->sb_lock);
2740 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2741 temp |= SBI_SSCCTL_DISABLE;
2742 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2744 mutex_unlock(&dev_priv->sb_lock);
2747 /* Program iCLKIP clock to the desired frequency */
2748 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
2750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2752 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
2753 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2756 lpt_disable_iclkip(dev_priv);
2758 /* The iCLK virtual clock root frequency is in MHz,
2759 * but the adjusted_mode->crtc_clock in in KHz. To get the
2760 * divisors, it is necessary to divide one by another, so we
2761 * convert the virtual clock precision to KHz here for higher
2764 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
2765 u32 iclk_virtual_root_freq = 172800 * 1000;
2766 u32 iclk_pi_range = 64;
2767 u32 desired_divisor;
2769 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2771 divsel = (desired_divisor / iclk_pi_range) - 2;
2772 phaseinc = desired_divisor % iclk_pi_range;
2775 * Near 20MHz is a corner case which is
2776 * out of range for the 7-bit divisor
2782 /* This should not happen with any sane values */
2783 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2784 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2785 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
2786 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2788 drm_dbg_kms(&dev_priv->drm,
2789 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2790 clock, auxdiv, divsel, phasedir, phaseinc);
2792 mutex_lock(&dev_priv->sb_lock);
2794 /* Program SSCDIVINTPHASE6 */
2795 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2796 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2797 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2798 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2799 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2800 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2801 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2802 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2804 /* Program SSCAUXDIV */
2805 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2806 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2807 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2808 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2810 /* Enable modulator and associated divider */
2811 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2812 temp &= ~SBI_SSCCTL_DISABLE;
2813 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2815 mutex_unlock(&dev_priv->sb_lock);
2817 /* Wait for initialization time */
2820 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2823 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
2825 u32 divsel, phaseinc, auxdiv;
2826 u32 iclk_virtual_root_freq = 172800 * 1000;
2827 u32 iclk_pi_range = 64;
2828 u32 desired_divisor;
2831 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
2834 mutex_lock(&dev_priv->sb_lock);
2836 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2837 if (temp & SBI_SSCCTL_DISABLE) {
2838 mutex_unlock(&dev_priv->sb_lock);
2842 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2843 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
2844 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
2845 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
2846 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
2848 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2849 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
2850 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
2852 mutex_unlock(&dev_priv->sb_lock);
2854 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
2856 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2857 desired_divisor << auxdiv);
2860 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
2861 enum pipe pch_transcoder)
2863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2864 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2865 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2867 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
2868 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
2869 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
2870 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
2871 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
2872 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
2874 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
2875 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2876 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
2877 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
2878 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
2879 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
2880 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2881 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
2884 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
2888 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
2889 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
2892 drm_WARN_ON(&dev_priv->drm,
2893 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
2895 drm_WARN_ON(&dev_priv->drm,
2896 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
2899 temp &= ~FDI_BC_BIFURCATION_SELECT;
2901 temp |= FDI_BC_BIFURCATION_SELECT;
2903 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
2904 enable ? "en" : "dis");
2905 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
2906 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
2909 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
2911 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2914 switch (crtc->pipe) {
2918 if (crtc_state->fdi_lanes > 2)
2919 cpt_set_fdi_bc_bifurcation(dev_priv, false);
2921 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2925 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2934 * Finds the encoder associated with the given CRTC. This can only be
2935 * used when we know that the CRTC isn't feeding multiple encoders!
2937 struct intel_encoder *
2938 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
2939 const struct intel_crtc_state *crtc_state)
2941 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2942 const struct drm_connector_state *connector_state;
2943 const struct drm_connector *connector;
2944 struct intel_encoder *encoder = NULL;
2945 int num_encoders = 0;
2948 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
2949 if (connector_state->crtc != &crtc->base)
2952 encoder = to_intel_encoder(connector_state->best_encoder);
2956 drm_WARN(encoder->base.dev, num_encoders != 1,
2957 "%d encoders for pipe %c\n",
2958 num_encoders, pipe_name(crtc->pipe));
2964 * Enable PCH resources required for PCH ports:
2966 * - FDI training & RX/TX
2967 * - update transcoder timings
2968 * - DP transcoding bits
2971 static void ilk_pch_enable(const struct intel_atomic_state *state,
2972 const struct intel_crtc_state *crtc_state)
2974 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2975 struct drm_device *dev = crtc->base.dev;
2976 struct drm_i915_private *dev_priv = to_i915(dev);
2977 enum pipe pipe = crtc->pipe;
2980 assert_pch_transcoder_disabled(dev_priv, pipe);
2982 if (IS_IVYBRIDGE(dev_priv))
2983 ivb_update_fdi_bc_bifurcation(crtc_state);
2985 /* Write the TU size bits before fdi link training, so that error
2986 * detection works. */
2987 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
2988 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2990 /* For PCH output, training FDI link */
2991 dev_priv->display.fdi_link_train(crtc, crtc_state);
2993 /* We need to program the right clock selection before writing the pixel
2994 * mutliplier into the DPLL. */
2995 if (HAS_PCH_CPT(dev_priv)) {
2998 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
2999 temp |= TRANS_DPLL_ENABLE(pipe);
3000 sel = TRANS_DPLLB_SEL(pipe);
3001 if (crtc_state->shared_dpll ==
3002 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
3006 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
3009 /* XXX: pch pll's can be enabled any time before we enable the PCH
3010 * transcoder, and we actually should do this to not upset any PCH
3011 * transcoder that already use the clock when we share it.
3013 * Note that enable_shared_dpll tries to do the right thing, but
3014 * get_shared_dpll unconditionally resets the pll - we need that to have
3015 * the right LVDS enable sequence. */
3016 intel_enable_shared_dpll(crtc_state);
3018 /* set transcoder timing, panel must allow it */
3019 assert_panel_unlocked(dev_priv, pipe);
3020 ilk_pch_transcoder_set_timings(crtc_state, pipe);
3022 intel_fdi_normal_train(crtc);
3024 /* For PCH DP, enable TRANS_DP_CTL */
3025 if (HAS_PCH_CPT(dev_priv) &&
3026 intel_crtc_has_dp_encoder(crtc_state)) {
3027 const struct drm_display_mode *adjusted_mode =
3028 &crtc_state->hw.adjusted_mode;
3029 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3030 i915_reg_t reg = TRANS_DP_CTL(pipe);
3033 temp = intel_de_read(dev_priv, reg);
3034 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3035 TRANS_DP_SYNC_MASK |
3037 temp |= TRANS_DP_OUTPUT_ENABLE;
3038 temp |= bpc << 9; /* same format but at 11:9 */
3040 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
3041 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3042 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
3043 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3045 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
3046 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
3047 temp |= TRANS_DP_PORT_SEL(port);
3049 intel_de_write(dev_priv, reg, temp);
3052 ilk_enable_pch_transcoder(crtc_state);
3055 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
3057 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3058 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3059 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3061 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
3063 lpt_program_iclkip(crtc_state);
3065 /* Set transcoder timing. */
3066 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
3068 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3071 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
3074 i915_reg_t dslreg = PIPEDSL(pipe);
3077 temp = intel_de_read(dev_priv, dslreg);
3079 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
3080 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
3081 drm_err(&dev_priv->drm,
3082 "mode set failed: pipe %c stuck\n",
3087 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
3089 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3091 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
3092 enum pipe pipe = crtc->pipe;
3093 int width = drm_rect_width(dst);
3094 int height = drm_rect_height(dst);
3098 if (!crtc_state->pch_pfit.enabled)
3101 /* Force use of hard-coded filter coefficients
3102 * as some pre-programmed values are broken,
3105 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3106 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
3107 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
3109 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
3111 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
3112 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
3115 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
3117 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3118 struct drm_device *dev = crtc->base.dev;
3119 struct drm_i915_private *dev_priv = to_i915(dev);
3121 if (!crtc_state->ips_enabled)
3125 * We can only enable IPS after we enable a plane and wait for a vblank
3126 * This function is called from post_plane_update, which is run after
3129 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
3131 if (IS_BROADWELL(dev_priv)) {
3132 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
3133 IPS_ENABLE | IPS_PCODE_CONTROL));
3134 /* Quoting Art Runyan: "its not safe to expect any particular
3135 * value in IPS_CTL bit 31 after enabling IPS through the
3136 * mailbox." Moreover, the mailbox may return a bogus state,
3137 * so we need to just enable it and continue on.
3140 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
3141 /* The bit only becomes 1 in the next vblank, so this wait here
3142 * is essentially intel_wait_for_vblank. If we don't have this
3143 * and don't wait for vblanks until the end of crtc_enable, then
3144 * the HW state readout code will complain that the expected
3145 * IPS_CTL value is not the one we read. */
3146 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
3147 drm_err(&dev_priv->drm,
3148 "Timed out waiting for IPS enable\n");
3152 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
3154 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3155 struct drm_device *dev = crtc->base.dev;
3156 struct drm_i915_private *dev_priv = to_i915(dev);
3158 if (!crtc_state->ips_enabled)
3161 if (IS_BROADWELL(dev_priv)) {
3163 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3165 * Wait for PCODE to finish disabling IPS. The BSpec specified
3166 * 42ms timeout value leads to occasional timeouts so use 100ms
3169 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
3170 drm_err(&dev_priv->drm,
3171 "Timed out waiting for IPS disable\n");
3173 intel_de_write(dev_priv, IPS_CTL, 0);
3174 intel_de_posting_read(dev_priv, IPS_CTL);
3177 /* We need to wait for a vblank before we can disable the plane. */
3178 intel_wait_for_vblank(dev_priv, crtc->pipe);
3181 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
3183 if (intel_crtc->overlay)
3184 (void) intel_overlay_switch_off(intel_crtc->overlay);
3186 /* Let userspace switch the overlay on again. In most cases userspace
3187 * has to recompute where to put it anyway.
3191 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
3192 const struct intel_crtc_state *new_crtc_state)
3194 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
3195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3197 if (!old_crtc_state->ips_enabled)
3200 if (intel_crtc_needs_modeset(new_crtc_state))
3204 * Workaround : Do not read or write the pipe palette/gamma data while
3205 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3207 * Disable IPS before we program the LUT.
3209 if (IS_HASWELL(dev_priv) &&
3210 (new_crtc_state->uapi.color_mgmt_changed ||
3211 new_crtc_state->update_pipe) &&
3212 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
3215 return !new_crtc_state->ips_enabled;
3218 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
3219 const struct intel_crtc_state *new_crtc_state)
3221 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
3222 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3224 if (!new_crtc_state->ips_enabled)
3227 if (intel_crtc_needs_modeset(new_crtc_state))
3231 * Workaround : Do not read or write the pipe palette/gamma data while
3232 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3234 * Re-enable IPS after the LUT has been programmed.
3236 if (IS_HASWELL(dev_priv) &&
3237 (new_crtc_state->uapi.color_mgmt_changed ||
3238 new_crtc_state->update_pipe) &&
3239 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
3243 * We can't read out IPS on broadwell, assume the worst and
3244 * forcibly enable IPS on the first fastset.
3246 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
3249 return !old_crtc_state->ips_enabled;
3252 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
3254 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3256 if (!crtc_state->nv12_planes)
3259 /* WA Display #0827: Gen9:all */
3260 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
3266 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
3268 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3270 /* Wa_2006604312:icl,ehl */
3271 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
3277 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
3278 const struct intel_crtc_state *new_crtc_state)
3280 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
3281 new_crtc_state->active_planes;
3284 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
3285 const struct intel_crtc_state *new_crtc_state)
3287 return old_crtc_state->active_planes &&
3288 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
3291 static void intel_post_plane_update(struct intel_atomic_state *state,
3292 struct intel_crtc *crtc)
3294 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3295 const struct intel_crtc_state *old_crtc_state =
3296 intel_atomic_get_old_crtc_state(state, crtc);
3297 const struct intel_crtc_state *new_crtc_state =
3298 intel_atomic_get_new_crtc_state(state, crtc);
3299 enum pipe pipe = crtc->pipe;
3301 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
3303 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
3304 intel_update_watermarks(crtc);
3306 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
3307 hsw_enable_ips(new_crtc_state);
3309 intel_fbc_post_update(state, crtc);
3311 if (needs_nv12_wa(old_crtc_state) &&
3312 !needs_nv12_wa(new_crtc_state))
3313 skl_wa_827(dev_priv, pipe, false);
3315 if (needs_scalerclk_wa(old_crtc_state) &&
3316 !needs_scalerclk_wa(new_crtc_state))
3317 icl_wa_scalerclkgating(dev_priv, pipe, false);
3320 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
3321 struct intel_crtc *crtc)
3323 const struct intel_crtc_state *crtc_state =
3324 intel_atomic_get_new_crtc_state(state, crtc);
3325 u8 update_planes = crtc_state->update_planes;
3326 const struct intel_plane_state *plane_state;
3327 struct intel_plane *plane;
3330 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3331 if (plane->enable_flip_done &&
3332 plane->pipe == crtc->pipe &&
3333 update_planes & BIT(plane->id))
3334 plane->enable_flip_done(plane);
3338 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
3339 struct intel_crtc *crtc)
3341 const struct intel_crtc_state *crtc_state =
3342 intel_atomic_get_new_crtc_state(state, crtc);
3343 u8 update_planes = crtc_state->update_planes;
3344 const struct intel_plane_state *plane_state;
3345 struct intel_plane *plane;
3348 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3349 if (plane->disable_flip_done &&
3350 plane->pipe == crtc->pipe &&
3351 update_planes & BIT(plane->id))
3352 plane->disable_flip_done(plane);
3356 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
3357 struct intel_crtc *crtc)
3359 struct drm_i915_private *i915 = to_i915(state->base.dev);
3360 const struct intel_crtc_state *old_crtc_state =
3361 intel_atomic_get_old_crtc_state(state, crtc);
3362 const struct intel_crtc_state *new_crtc_state =
3363 intel_atomic_get_new_crtc_state(state, crtc);
3364 u8 update_planes = new_crtc_state->update_planes;
3365 const struct intel_plane_state *old_plane_state;
3366 struct intel_plane *plane;
3367 bool need_vbl_wait = false;
3370 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
3371 if (plane->need_async_flip_disable_wa &&
3372 plane->pipe == crtc->pipe &&
3373 update_planes & BIT(plane->id)) {
3375 * Apart from the async flip bit we want to
3376 * preserve the old state for the plane.
3378 plane->async_flip(plane, old_crtc_state,
3379 old_plane_state, false);
3380 need_vbl_wait = true;
3385 intel_wait_for_vblank(i915, crtc->pipe);
3388 static void intel_pre_plane_update(struct intel_atomic_state *state,
3389 struct intel_crtc *crtc)
3391 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3392 const struct intel_crtc_state *old_crtc_state =
3393 intel_atomic_get_old_crtc_state(state, crtc);
3394 const struct intel_crtc_state *new_crtc_state =
3395 intel_atomic_get_new_crtc_state(state, crtc);
3396 enum pipe pipe = crtc->pipe;
3398 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
3399 hsw_disable_ips(old_crtc_state);
3401 if (intel_fbc_pre_update(state, crtc))
3402 intel_wait_for_vblank(dev_priv, pipe);
3404 /* Display WA 827 */
3405 if (!needs_nv12_wa(old_crtc_state) &&
3406 needs_nv12_wa(new_crtc_state))
3407 skl_wa_827(dev_priv, pipe, true);
3409 /* Wa_2006604312:icl,ehl */
3410 if (!needs_scalerclk_wa(old_crtc_state) &&
3411 needs_scalerclk_wa(new_crtc_state))
3412 icl_wa_scalerclkgating(dev_priv, pipe, true);
3415 * Vblank time updates from the shadow to live plane control register
3416 * are blocked if the memory self-refresh mode is active at that
3417 * moment. So to make sure the plane gets truly disabled, disable
3418 * first the self-refresh mode. The self-refresh enable bit in turn
3419 * will be checked/applied by the HW only at the next frame start
3420 * event which is after the vblank start event, so we need to have a
3421 * wait-for-vblank between disabling the plane and the pipe.
3423 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
3424 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
3425 intel_wait_for_vblank(dev_priv, pipe);
3428 * IVB workaround: must disable low power watermarks for at least
3429 * one frame before enabling scaling. LP watermarks can be re-enabled
3430 * when scaling is disabled.
3432 * WaCxSRDisabledForSpriteScaling:ivb
3434 if (old_crtc_state->hw.active &&
3435 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
3436 intel_wait_for_vblank(dev_priv, pipe);
3439 * If we're doing a modeset we don't need to do any
3440 * pre-vblank watermark programming here.
3442 if (!intel_crtc_needs_modeset(new_crtc_state)) {
3444 * For platforms that support atomic watermarks, program the
3445 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
3446 * will be the intermediate values that are safe for both pre- and
3447 * post- vblank; when vblank happens, the 'active' values will be set
3448 * to the final 'target' values and we'll do this again to get the
3449 * optimal watermarks. For gen9+ platforms, the values we program here
3450 * will be the final target values which will get automatically latched
3451 * at vblank time; no further programming will be necessary.
3453 * If a platform hasn't been transitioned to atomic watermarks yet,
3454 * we'll continue to update watermarks the old way, if flags tell
3457 if (dev_priv->display.initial_watermarks)
3458 dev_priv->display.initial_watermarks(state, crtc);
3459 else if (new_crtc_state->update_wm_pre)
3460 intel_update_watermarks(crtc);
3464 * Gen2 reports pipe underruns whenever all planes are disabled.
3465 * So disable underrun reporting before all the planes get disabled.
3467 * We do this after .initial_watermarks() so that we have a
3468 * chance of catching underruns with the intermediate watermarks
3469 * vs. the old plane configuration.
3471 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
3472 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3475 * WA for platforms where async address update enable bit
3476 * is double buffered and only latched at start of vblank.
3478 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
3479 intel_crtc_async_flip_disable_wa(state, crtc);
3482 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
3483 struct intel_crtc *crtc)
3485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3486 const struct intel_crtc_state *new_crtc_state =
3487 intel_atomic_get_new_crtc_state(state, crtc);
3488 unsigned int update_mask = new_crtc_state->update_planes;
3489 const struct intel_plane_state *old_plane_state;
3490 struct intel_plane *plane;
3491 unsigned fb_bits = 0;
3494 intel_crtc_dpms_overlay_disable(crtc);
3496 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
3497 if (crtc->pipe != plane->pipe ||
3498 !(update_mask & BIT(plane->id)))
3501 intel_disable_plane(plane, new_crtc_state);
3503 if (old_plane_state->uapi.visible)
3504 fb_bits |= plane->frontbuffer_bit;
3507 intel_frontbuffer_flip(dev_priv, fb_bits);
3511 * intel_connector_primary_encoder - get the primary encoder for a connector
3512 * @connector: connector for which to return the encoder
3514 * Returns the primary encoder for a connector. There is a 1:1 mapping from
3515 * all connectors to their encoder, except for DP-MST connectors which have
3516 * both a virtual and a primary encoder. These DP-MST primary encoders can be
3517 * pointed to by as many DP-MST connectors as there are pipes.
3519 static struct intel_encoder *
3520 intel_connector_primary_encoder(struct intel_connector *connector)
3522 struct intel_encoder *encoder;
3524 if (connector->mst_port)
3525 return &dp_to_dig_port(connector->mst_port)->base;
3527 encoder = intel_attached_encoder(connector);
3528 drm_WARN_ON(connector->base.dev, !encoder);
3533 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
3535 struct drm_connector_state *new_conn_state;
3536 struct drm_connector *connector;
3539 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3541 struct intel_connector *intel_connector;
3542 struct intel_encoder *encoder;
3543 struct intel_crtc *crtc;
3545 if (!intel_connector_needs_modeset(state, connector))
3548 intel_connector = to_intel_connector(connector);
3549 encoder = intel_connector_primary_encoder(intel_connector);
3550 if (!encoder->update_prepare)
3553 crtc = new_conn_state->crtc ?
3554 to_intel_crtc(new_conn_state->crtc) : NULL;
3555 encoder->update_prepare(state, encoder, crtc);
3559 static void intel_encoders_update_complete(struct intel_atomic_state *state)
3561 struct drm_connector_state *new_conn_state;
3562 struct drm_connector *connector;
3565 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3567 struct intel_connector *intel_connector;
3568 struct intel_encoder *encoder;
3569 struct intel_crtc *crtc;
3571 if (!intel_connector_needs_modeset(state, connector))
3574 intel_connector = to_intel_connector(connector);
3575 encoder = intel_connector_primary_encoder(intel_connector);
3576 if (!encoder->update_complete)
3579 crtc = new_conn_state->crtc ?
3580 to_intel_crtc(new_conn_state->crtc) : NULL;
3581 encoder->update_complete(state, encoder, crtc);
3585 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
3586 struct intel_crtc *crtc)
3588 const struct intel_crtc_state *crtc_state =
3589 intel_atomic_get_new_crtc_state(state, crtc);
3590 const struct drm_connector_state *conn_state;
3591 struct drm_connector *conn;
3594 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3595 struct intel_encoder *encoder =
3596 to_intel_encoder(conn_state->best_encoder);
3598 if (conn_state->crtc != &crtc->base)
3601 if (encoder->pre_pll_enable)
3602 encoder->pre_pll_enable(state, encoder,
3603 crtc_state, conn_state);
3607 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
3608 struct intel_crtc *crtc)
3610 const struct intel_crtc_state *crtc_state =
3611 intel_atomic_get_new_crtc_state(state, crtc);
3612 const struct drm_connector_state *conn_state;
3613 struct drm_connector *conn;
3616 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3617 struct intel_encoder *encoder =
3618 to_intel_encoder(conn_state->best_encoder);
3620 if (conn_state->crtc != &crtc->base)
3623 if (encoder->pre_enable)
3624 encoder->pre_enable(state, encoder,
3625 crtc_state, conn_state);
3629 static void intel_encoders_enable(struct intel_atomic_state *state,
3630 struct intel_crtc *crtc)
3632 const struct intel_crtc_state *crtc_state =
3633 intel_atomic_get_new_crtc_state(state, crtc);
3634 const struct drm_connector_state *conn_state;
3635 struct drm_connector *conn;
3638 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3639 struct intel_encoder *encoder =
3640 to_intel_encoder(conn_state->best_encoder);
3642 if (conn_state->crtc != &crtc->base)
3645 if (encoder->enable)
3646 encoder->enable(state, encoder,
3647 crtc_state, conn_state);
3648 intel_opregion_notify_encoder(encoder, true);
3652 static void intel_encoders_disable(struct intel_atomic_state *state,
3653 struct intel_crtc *crtc)
3655 const struct intel_crtc_state *old_crtc_state =
3656 intel_atomic_get_old_crtc_state(state, crtc);
3657 const struct drm_connector_state *old_conn_state;
3658 struct drm_connector *conn;
3661 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3662 struct intel_encoder *encoder =
3663 to_intel_encoder(old_conn_state->best_encoder);
3665 if (old_conn_state->crtc != &crtc->base)
3668 intel_opregion_notify_encoder(encoder, false);
3669 if (encoder->disable)
3670 encoder->disable(state, encoder,
3671 old_crtc_state, old_conn_state);
3675 static void intel_encoders_post_disable(struct intel_atomic_state *state,
3676 struct intel_crtc *crtc)
3678 const struct intel_crtc_state *old_crtc_state =
3679 intel_atomic_get_old_crtc_state(state, crtc);
3680 const struct drm_connector_state *old_conn_state;
3681 struct drm_connector *conn;
3684 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3685 struct intel_encoder *encoder =
3686 to_intel_encoder(old_conn_state->best_encoder);
3688 if (old_conn_state->crtc != &crtc->base)
3691 if (encoder->post_disable)
3692 encoder->post_disable(state, encoder,
3693 old_crtc_state, old_conn_state);
3697 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
3698 struct intel_crtc *crtc)
3700 const struct intel_crtc_state *old_crtc_state =
3701 intel_atomic_get_old_crtc_state(state, crtc);
3702 const struct drm_connector_state *old_conn_state;
3703 struct drm_connector *conn;
3706 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3707 struct intel_encoder *encoder =
3708 to_intel_encoder(old_conn_state->best_encoder);
3710 if (old_conn_state->crtc != &crtc->base)
3713 if (encoder->post_pll_disable)
3714 encoder->post_pll_disable(state, encoder,
3715 old_crtc_state, old_conn_state);
3719 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
3720 struct intel_crtc *crtc)
3722 const struct intel_crtc_state *crtc_state =
3723 intel_atomic_get_new_crtc_state(state, crtc);
3724 const struct drm_connector_state *conn_state;
3725 struct drm_connector *conn;
3728 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3729 struct intel_encoder *encoder =
3730 to_intel_encoder(conn_state->best_encoder);
3732 if (conn_state->crtc != &crtc->base)
3735 if (encoder->update_pipe)
3736 encoder->update_pipe(state, encoder,
3737 crtc_state, conn_state);
3741 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
3743 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3744 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3746 plane->disable_plane(plane, crtc_state);
3749 static void ilk_crtc_enable(struct intel_atomic_state *state,
3750 struct intel_crtc *crtc)
3752 const struct intel_crtc_state *new_crtc_state =
3753 intel_atomic_get_new_crtc_state(state, crtc);
3754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3755 enum pipe pipe = crtc->pipe;
3757 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3761 * Sometimes spurious CPU pipe underruns happen during FDI
3762 * training, at least with VGA+HDMI cloning. Suppress them.
3764 * On ILK we get an occasional spurious CPU pipe underruns
3765 * between eDP port A enable and vdd enable. Also PCH port
3766 * enable seems to result in the occasional CPU pipe underrun.
3768 * Spurious PCH underruns also occur during PCH enabling.
3770 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3771 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3773 if (new_crtc_state->has_pch_encoder)
3774 intel_prepare_shared_dpll(new_crtc_state);
3776 if (intel_crtc_has_dp_encoder(new_crtc_state))
3777 intel_dp_set_m_n(new_crtc_state, M1_N1);
3779 intel_set_transcoder_timings(new_crtc_state);
3780 intel_set_pipe_src_size(new_crtc_state);
3782 if (new_crtc_state->has_pch_encoder)
3783 intel_cpu_transcoder_set_m_n(new_crtc_state,
3784 &new_crtc_state->fdi_m_n, NULL);
3786 ilk_set_pipeconf(new_crtc_state);
3788 crtc->active = true;
3790 intel_encoders_pre_enable(state, crtc);
3792 if (new_crtc_state->has_pch_encoder) {
3793 /* Note: FDI PLL enabling _must_ be done before we enable the
3794 * cpu pipes, hence this is separate from all the other fdi/pch
3796 ilk_fdi_pll_enable(new_crtc_state);
3798 assert_fdi_tx_disabled(dev_priv, pipe);
3799 assert_fdi_rx_disabled(dev_priv, pipe);
3802 ilk_pfit_enable(new_crtc_state);
3805 * On ILK+ LUT must be loaded before the pipe is running but with
3808 intel_color_load_luts(new_crtc_state);
3809 intel_color_commit(new_crtc_state);
3810 /* update DSPCNTR to configure gamma for pipe bottom color */
3811 intel_disable_primary_plane(new_crtc_state);
3813 if (dev_priv->display.initial_watermarks)
3814 dev_priv->display.initial_watermarks(state, crtc);
3815 intel_enable_pipe(new_crtc_state);
3817 if (new_crtc_state->has_pch_encoder)
3818 ilk_pch_enable(state, new_crtc_state);
3820 intel_crtc_vblank_on(new_crtc_state);
3822 intel_encoders_enable(state, crtc);
3824 if (HAS_PCH_CPT(dev_priv))
3825 cpt_verify_modeset(dev_priv, pipe);
3828 * Must wait for vblank to avoid spurious PCH FIFO underruns.
3829 * And a second vblank wait is needed at least on ILK with
3830 * some interlaced HDMI modes. Let's do the double wait always
3831 * in case there are more corner cases we don't know about.
3833 if (new_crtc_state->has_pch_encoder) {
3834 intel_wait_for_vblank(dev_priv, pipe);
3835 intel_wait_for_vblank(dev_priv, pipe);
3837 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3838 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3841 /* IPS only exists on ULT machines and is tied to pipe A. */
3842 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3844 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
3847 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
3848 enum pipe pipe, bool apply)
3850 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
3851 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
3858 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
3861 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
3863 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3864 enum pipe pipe = crtc->pipe;
3867 val = MBUS_DBOX_A_CREDIT(2);
3869 if (INTEL_GEN(dev_priv) >= 12) {
3870 val |= MBUS_DBOX_BW_CREDIT(2);
3871 val |= MBUS_DBOX_B_CREDIT(12);
3873 val |= MBUS_DBOX_BW_CREDIT(1);
3874 val |= MBUS_DBOX_B_CREDIT(8);
3877 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
3880 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
3882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3883 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3885 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
3886 HSW_LINETIME(crtc_state->linetime) |
3887 HSW_IPS_LINETIME(crtc_state->ips_linetime));
3890 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
3892 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3894 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
3897 val = intel_de_read(dev_priv, reg);
3898 val &= ~HSW_FRAME_START_DELAY_MASK;
3899 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
3900 intel_de_write(dev_priv, reg, val);
3903 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
3904 const struct intel_crtc_state *crtc_state)
3906 struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
3907 struct intel_crtc_state *master_crtc_state;
3908 struct drm_connector_state *conn_state;
3909 struct drm_connector *conn;
3910 struct intel_encoder *encoder = NULL;
3913 if (crtc_state->bigjoiner_slave)
3914 master = crtc_state->bigjoiner_linked_crtc;
3916 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
3918 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3919 if (conn_state->crtc != &master->base)
3922 encoder = to_intel_encoder(conn_state->best_encoder);
3926 if (!crtc_state->bigjoiner_slave) {
3927 /* need to enable VDSC, which we skipped in pre-enable */
3928 intel_dsc_enable(encoder, crtc_state);
3931 * Enable sequence steps 1-7 on bigjoiner master
3933 intel_encoders_pre_pll_enable(state, master);
3934 intel_enable_shared_dpll(master_crtc_state);
3935 intel_encoders_pre_enable(state, master);
3937 /* and DSC on slave */
3938 intel_dsc_enable(NULL, crtc_state);
3942 static void hsw_crtc_enable(struct intel_atomic_state *state,
3943 struct intel_crtc *crtc)
3945 const struct intel_crtc_state *new_crtc_state =
3946 intel_atomic_get_new_crtc_state(state, crtc);
3947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3948 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
3949 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3950 bool psl_clkgate_wa;
3952 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3955 if (!new_crtc_state->bigjoiner) {
3956 intel_encoders_pre_pll_enable(state, crtc);
3958 if (new_crtc_state->shared_dpll)
3959 intel_enable_shared_dpll(new_crtc_state);
3961 intel_encoders_pre_enable(state, crtc);
3963 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
3966 intel_set_pipe_src_size(new_crtc_state);
3967 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
3968 bdw_set_pipemisc(new_crtc_state);
3970 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
3971 intel_set_transcoder_timings(new_crtc_state);
3973 if (cpu_transcoder != TRANSCODER_EDP)
3974 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
3975 new_crtc_state->pixel_multiplier - 1);
3977 if (new_crtc_state->has_pch_encoder)
3978 intel_cpu_transcoder_set_m_n(new_crtc_state,
3979 &new_crtc_state->fdi_m_n, NULL);
3981 hsw_set_frame_start_delay(new_crtc_state);
3984 if (!transcoder_is_dsi(cpu_transcoder))
3985 hsw_set_pipeconf(new_crtc_state);
3987 crtc->active = true;
3989 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
3990 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3991 new_crtc_state->pch_pfit.enabled;
3993 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
3995 if (INTEL_GEN(dev_priv) >= 9)
3996 skl_pfit_enable(new_crtc_state);
3998 ilk_pfit_enable(new_crtc_state);
4001 * On ILK+ LUT must be loaded before the pipe is running but with
4004 intel_color_load_luts(new_crtc_state);
4005 intel_color_commit(new_crtc_state);
4006 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
4007 if (INTEL_GEN(dev_priv) < 9)
4008 intel_disable_primary_plane(new_crtc_state);
4010 hsw_set_linetime_wm(new_crtc_state);
4012 if (INTEL_GEN(dev_priv) >= 11)
4013 icl_set_pipe_chicken(crtc);
4015 if (dev_priv->display.initial_watermarks)
4016 dev_priv->display.initial_watermarks(state, crtc);
4018 if (INTEL_GEN(dev_priv) >= 11)
4019 icl_pipe_mbus_enable(crtc);
4021 if (new_crtc_state->bigjoiner_slave)
4022 intel_crtc_vblank_on(new_crtc_state);
4024 intel_encoders_enable(state, crtc);
4026 if (psl_clkgate_wa) {
4027 intel_wait_for_vblank(dev_priv, pipe);
4028 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
4031 /* If we change the relative order between pipe/planes enabling, we need
4032 * to change the workaround. */
4033 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
4034 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
4035 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
4036 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
4040 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
4042 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4044 enum pipe pipe = crtc->pipe;
4046 /* To avoid upsetting the power well on haswell only disable the pfit if
4047 * it's in use. The hw state code will make sure we get this right. */
4048 if (!old_crtc_state->pch_pfit.enabled)
4051 intel_de_write(dev_priv, PF_CTL(pipe), 0);
4052 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
4053 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
4056 static void ilk_crtc_disable(struct intel_atomic_state *state,
4057 struct intel_crtc *crtc)
4059 const struct intel_crtc_state *old_crtc_state =
4060 intel_atomic_get_old_crtc_state(state, crtc);
4061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4062 enum pipe pipe = crtc->pipe;
4065 * Sometimes spurious CPU pipe underruns happen when the
4066 * pipe is already disabled, but FDI RX/TX is still enabled.
4067 * Happens at least with VGA+HDMI cloning. Suppress them.
4069 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4070 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4072 intel_encoders_disable(state, crtc);
4074 intel_crtc_vblank_off(old_crtc_state);
4076 intel_disable_pipe(old_crtc_state);
4078 ilk_pfit_disable(old_crtc_state);
4080 if (old_crtc_state->has_pch_encoder)
4081 ilk_fdi_disable(crtc);
4083 intel_encoders_post_disable(state, crtc);
4085 if (old_crtc_state->has_pch_encoder) {
4086 ilk_disable_pch_transcoder(dev_priv, pipe);
4088 if (HAS_PCH_CPT(dev_priv)) {
4092 /* disable TRANS_DP_CTL */
4093 reg = TRANS_DP_CTL(pipe);
4094 temp = intel_de_read(dev_priv, reg);
4095 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4096 TRANS_DP_PORT_SEL_MASK);
4097 temp |= TRANS_DP_PORT_SEL_NONE;
4098 intel_de_write(dev_priv, reg, temp);
4100 /* disable DPLL_SEL */
4101 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
4102 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4103 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
4106 ilk_fdi_pll_disable(crtc);
4109 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4110 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4113 static void hsw_crtc_disable(struct intel_atomic_state *state,
4114 struct intel_crtc *crtc)
4117 * FIXME collapse everything to one hook.
4118 * Need care with mst->ddi interactions.
4120 intel_encoders_disable(state, crtc);
4121 intel_encoders_post_disable(state, crtc);
4124 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
4126 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4127 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4129 if (!crtc_state->gmch_pfit.control)
4133 * The panel fitter should only be adjusted whilst the pipe is disabled,
4134 * according to register description and PRM.
4136 drm_WARN_ON(&dev_priv->drm,
4137 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
4138 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
4140 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
4141 crtc_state->gmch_pfit.pgm_ratios);
4142 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
4144 /* Border color in case we don't scale up to the full screen. Black by
4145 * default, change to something else for debugging. */
4146 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
4149 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
4151 if (phy == PHY_NONE)
4153 else if (IS_ALDERLAKE_S(dev_priv))
4154 return phy <= PHY_E;
4155 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
4156 return phy <= PHY_D;
4157 else if (IS_JSL_EHL(dev_priv))
4158 return phy <= PHY_C;
4159 else if (INTEL_GEN(dev_priv) >= 11)
4160 return phy <= PHY_B;
4165 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
4167 if (IS_TIGERLAKE(dev_priv))
4168 return phy >= PHY_D && phy <= PHY_I;
4169 else if (IS_ICELAKE(dev_priv))
4170 return phy >= PHY_C && phy <= PHY_F;
4175 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
4177 if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
4178 return PHY_B + port - PORT_TC1;
4179 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
4180 return PHY_C + port - PORT_TC1;
4181 else if (IS_JSL_EHL(i915) && port == PORT_D)
4184 return PHY_A + port - PORT_A;
4187 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
4189 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
4190 return TC_PORT_NONE;
4192 if (INTEL_GEN(dev_priv) >= 12)
4193 return TC_PORT_1 + port - PORT_TC1;
4195 return TC_PORT_1 + port - PORT_C;
4198 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
4202 return POWER_DOMAIN_PORT_DDI_A_LANES;
4204 return POWER_DOMAIN_PORT_DDI_B_LANES;
4206 return POWER_DOMAIN_PORT_DDI_C_LANES;
4208 return POWER_DOMAIN_PORT_DDI_D_LANES;
4210 return POWER_DOMAIN_PORT_DDI_E_LANES;
4212 return POWER_DOMAIN_PORT_DDI_F_LANES;
4214 return POWER_DOMAIN_PORT_DDI_G_LANES;
4216 return POWER_DOMAIN_PORT_DDI_H_LANES;
4218 return POWER_DOMAIN_PORT_DDI_I_LANES;
4221 return POWER_DOMAIN_PORT_OTHER;
4225 enum intel_display_power_domain
4226 intel_aux_power_domain(struct intel_digital_port *dig_port)
4228 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4229 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
4231 if (intel_phy_is_tc(dev_priv, phy) &&
4232 dig_port->tc_mode == TC_PORT_TBT_ALT) {
4233 switch (dig_port->aux_ch) {
4235 return POWER_DOMAIN_AUX_C_TBT;
4237 return POWER_DOMAIN_AUX_D_TBT;
4239 return POWER_DOMAIN_AUX_E_TBT;
4241 return POWER_DOMAIN_AUX_F_TBT;
4243 return POWER_DOMAIN_AUX_G_TBT;
4245 return POWER_DOMAIN_AUX_H_TBT;
4247 return POWER_DOMAIN_AUX_I_TBT;
4249 MISSING_CASE(dig_port->aux_ch);
4250 return POWER_DOMAIN_AUX_C_TBT;
4254 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
4258 * Converts aux_ch to power_domain without caring about TBT ports for that use
4259 * intel_aux_power_domain()
4261 enum intel_display_power_domain
4262 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
4266 return POWER_DOMAIN_AUX_A;
4268 return POWER_DOMAIN_AUX_B;
4270 return POWER_DOMAIN_AUX_C;
4272 return POWER_DOMAIN_AUX_D;
4274 return POWER_DOMAIN_AUX_E;
4276 return POWER_DOMAIN_AUX_F;
4278 return POWER_DOMAIN_AUX_G;
4280 return POWER_DOMAIN_AUX_H;
4282 return POWER_DOMAIN_AUX_I;
4284 MISSING_CASE(aux_ch);
4285 return POWER_DOMAIN_AUX_A;
4289 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
4291 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4292 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4293 struct drm_encoder *encoder;
4294 enum pipe pipe = crtc->pipe;
4296 enum transcoder transcoder = crtc_state->cpu_transcoder;
4298 if (!crtc_state->hw.active)
4301 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
4302 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
4303 if (crtc_state->pch_pfit.enabled ||
4304 crtc_state->pch_pfit.force_thru)
4305 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4307 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
4308 crtc_state->uapi.encoder_mask) {
4309 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4311 mask |= BIT_ULL(intel_encoder->power_domain);
4314 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
4315 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
4317 if (crtc_state->shared_dpll)
4318 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
4320 if (crtc_state->dsc.compression_enable)
4321 mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
4327 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
4329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4330 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4331 enum intel_display_power_domain domain;
4332 u64 domains, new_domains, old_domains;
4334 domains = get_crtc_power_domains(crtc_state);
4336 new_domains = domains & ~crtc->enabled_power_domains.mask;
4337 old_domains = crtc->enabled_power_domains.mask & ~domains;
4339 for_each_power_domain(domain, new_domains)
4340 intel_display_power_get_in_set(dev_priv,
4341 &crtc->enabled_power_domains,
4347 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
4350 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
4351 &crtc->enabled_power_domains,
4355 static void valleyview_crtc_enable(struct intel_atomic_state *state,
4356 struct intel_crtc *crtc)
4358 const struct intel_crtc_state *new_crtc_state =
4359 intel_atomic_get_new_crtc_state(state, crtc);
4360 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4361 enum pipe pipe = crtc->pipe;
4363 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
4366 if (intel_crtc_has_dp_encoder(new_crtc_state))
4367 intel_dp_set_m_n(new_crtc_state, M1_N1);
4369 intel_set_transcoder_timings(new_crtc_state);
4370 intel_set_pipe_src_size(new_crtc_state);
4372 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
4373 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4374 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
4377 i9xx_set_pipeconf(new_crtc_state);
4379 crtc->active = true;
4381 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4383 intel_encoders_pre_pll_enable(state, crtc);
4385 if (IS_CHERRYVIEW(dev_priv)) {
4386 chv_prepare_pll(crtc, new_crtc_state);
4387 chv_enable_pll(crtc, new_crtc_state);
4389 vlv_prepare_pll(crtc, new_crtc_state);
4390 vlv_enable_pll(crtc, new_crtc_state);
4393 intel_encoders_pre_enable(state, crtc);
4395 i9xx_pfit_enable(new_crtc_state);
4397 intel_color_load_luts(new_crtc_state);
4398 intel_color_commit(new_crtc_state);
4399 /* update DSPCNTR to configure gamma for pipe bottom color */
4400 intel_disable_primary_plane(new_crtc_state);
4402 dev_priv->display.initial_watermarks(state, crtc);
4403 intel_enable_pipe(new_crtc_state);
4405 intel_crtc_vblank_on(new_crtc_state);
4407 intel_encoders_enable(state, crtc);
4410 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
4412 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4415 intel_de_write(dev_priv, FP0(crtc->pipe),
4416 crtc_state->dpll_hw_state.fp0);
4417 intel_de_write(dev_priv, FP1(crtc->pipe),
4418 crtc_state->dpll_hw_state.fp1);
4421 static void i9xx_crtc_enable(struct intel_atomic_state *state,
4422 struct intel_crtc *crtc)
4424 const struct intel_crtc_state *new_crtc_state =
4425 intel_atomic_get_new_crtc_state(state, crtc);
4426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4427 enum pipe pipe = crtc->pipe;
4429 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
4432 i9xx_set_pll_dividers(new_crtc_state);
4434 if (intel_crtc_has_dp_encoder(new_crtc_state))
4435 intel_dp_set_m_n(new_crtc_state, M1_N1);
4437 intel_set_transcoder_timings(new_crtc_state);
4438 intel_set_pipe_src_size(new_crtc_state);
4440 i9xx_set_pipeconf(new_crtc_state);
4442 crtc->active = true;
4444 if (!IS_GEN(dev_priv, 2))
4445 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4447 intel_encoders_pre_enable(state, crtc);
4449 i9xx_enable_pll(crtc, new_crtc_state);
4451 i9xx_pfit_enable(new_crtc_state);
4453 intel_color_load_luts(new_crtc_state);
4454 intel_color_commit(new_crtc_state);
4455 /* update DSPCNTR to configure gamma for pipe bottom color */
4456 intel_disable_primary_plane(new_crtc_state);
4458 if (dev_priv->display.initial_watermarks)
4459 dev_priv->display.initial_watermarks(state, crtc);
4461 intel_update_watermarks(crtc);
4462 intel_enable_pipe(new_crtc_state);
4464 intel_crtc_vblank_on(new_crtc_state);
4466 intel_encoders_enable(state, crtc);
4468 /* prevents spurious underruns */
4469 if (IS_GEN(dev_priv, 2))
4470 intel_wait_for_vblank(dev_priv, pipe);
4473 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
4475 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4478 if (!old_crtc_state->gmch_pfit.control)
4481 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
4483 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
4484 intel_de_read(dev_priv, PFIT_CONTROL));
4485 intel_de_write(dev_priv, PFIT_CONTROL, 0);
4488 static void i9xx_crtc_disable(struct intel_atomic_state *state,
4489 struct intel_crtc *crtc)
4491 struct intel_crtc_state *old_crtc_state =
4492 intel_atomic_get_old_crtc_state(state, crtc);
4493 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4494 enum pipe pipe = crtc->pipe;
4497 * On gen2 planes are double buffered but the pipe isn't, so we must
4498 * wait for planes to fully turn off before disabling the pipe.
4500 if (IS_GEN(dev_priv, 2))
4501 intel_wait_for_vblank(dev_priv, pipe);
4503 intel_encoders_disable(state, crtc);
4505 intel_crtc_vblank_off(old_crtc_state);
4507 intel_disable_pipe(old_crtc_state);
4509 i9xx_pfit_disable(old_crtc_state);
4511 intel_encoders_post_disable(state, crtc);
4513 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
4514 if (IS_CHERRYVIEW(dev_priv))
4515 chv_disable_pll(dev_priv, pipe);
4516 else if (IS_VALLEYVIEW(dev_priv))
4517 vlv_disable_pll(dev_priv, pipe);
4519 i9xx_disable_pll(old_crtc_state);
4522 intel_encoders_post_pll_disable(state, crtc);
4524 if (!IS_GEN(dev_priv, 2))
4525 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4527 if (!dev_priv->display.initial_watermarks)
4528 intel_update_watermarks(crtc);
4530 /* clock the pipe down to 640x480@60 to potentially save power */
4531 if (IS_I830(dev_priv))
4532 i830_enable_pipe(dev_priv, pipe);
4535 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
4536 struct drm_modeset_acquire_ctx *ctx)
4538 struct intel_encoder *encoder;
4539 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4540 struct intel_bw_state *bw_state =
4541 to_intel_bw_state(dev_priv->bw_obj.state);
4542 struct intel_cdclk_state *cdclk_state =
4543 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
4544 struct intel_dbuf_state *dbuf_state =
4545 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
4546 struct intel_crtc_state *crtc_state =
4547 to_intel_crtc_state(crtc->base.state);
4548 struct intel_plane *plane;
4549 struct drm_atomic_state *state;
4550 struct intel_crtc_state *temp_crtc_state;
4551 enum pipe pipe = crtc->pipe;
4554 if (!crtc_state->hw.active)
4557 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
4558 const struct intel_plane_state *plane_state =
4559 to_intel_plane_state(plane->base.state);
4561 if (plane_state->uapi.visible)
4562 intel_plane_disable_noatomic(crtc, plane);
4565 state = drm_atomic_state_alloc(&dev_priv->drm);
4567 drm_dbg_kms(&dev_priv->drm,
4568 "failed to disable [CRTC:%d:%s], out of memory",
4569 crtc->base.base.id, crtc->base.name);
4573 state->acquire_ctx = ctx;
4575 /* Everything's already locked, -EDEADLK can't happen. */
4576 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
4577 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
4579 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
4581 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
4583 drm_atomic_state_put(state);
4585 drm_dbg_kms(&dev_priv->drm,
4586 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
4587 crtc->base.base.id, crtc->base.name);
4589 crtc->active = false;
4590 crtc->base.enabled = false;
4592 drm_WARN_ON(&dev_priv->drm,
4593 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
4594 crtc_state->uapi.active = false;
4595 crtc_state->uapi.connector_mask = 0;
4596 crtc_state->uapi.encoder_mask = 0;
4597 intel_crtc_free_hw_state(crtc_state);
4598 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
4600 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
4601 encoder->base.crtc = NULL;
4603 intel_fbc_disable(crtc);
4604 intel_update_watermarks(crtc);
4605 intel_disable_shared_dpll(crtc_state);
4607 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
4609 dev_priv->active_pipes &= ~BIT(pipe);
4610 cdclk_state->min_cdclk[pipe] = 0;
4611 cdclk_state->min_voltage_level[pipe] = 0;
4612 cdclk_state->active_pipes &= ~BIT(pipe);
4614 dbuf_state->active_pipes &= ~BIT(pipe);
4616 bw_state->data_rate[pipe] = 0;
4617 bw_state->num_active_planes[pipe] = 0;
4621 * turn all crtc's off, but do not adjust state
4622 * This has to be paired with a call to intel_modeset_setup_hw_state.
4624 int intel_display_suspend(struct drm_device *dev)
4626 struct drm_i915_private *dev_priv = to_i915(dev);
4627 struct drm_atomic_state *state;
4630 state = drm_atomic_helper_suspend(dev);
4631 ret = PTR_ERR_OR_ZERO(state);
4633 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4636 dev_priv->modeset_restore_state = state;
4640 void intel_encoder_destroy(struct drm_encoder *encoder)
4642 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4644 drm_encoder_cleanup(encoder);
4645 kfree(intel_encoder);
4648 /* Cross check the actual hw state with our own modeset state tracking (and it's
4649 * internal consistency). */
4650 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
4651 struct drm_connector_state *conn_state)
4653 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4654 struct drm_i915_private *i915 = to_i915(connector->base.dev);
4656 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
4657 connector->base.base.id, connector->base.name);
4659 if (connector->get_hw_state(connector)) {
4660 struct intel_encoder *encoder = intel_attached_encoder(connector);
4662 I915_STATE_WARN(!crtc_state,
4663 "connector enabled without attached crtc\n");
4668 I915_STATE_WARN(!crtc_state->hw.active,
4669 "connector is active, but attached crtc isn't\n");
4671 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
4674 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
4675 "atomic encoder doesn't match attached encoder\n");
4677 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
4678 "attached encoder crtc differs from connector crtc\n");
4680 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
4681 "attached crtc is active, but connector isn't\n");
4682 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
4683 "best encoder set without crtc!\n");
4687 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
4689 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4690 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4692 /* IPS only exists on ULT machines and is tied to pipe A. */
4693 if (!hsw_crtc_supports_ips(crtc))
4696 if (!dev_priv->params.enable_ips)
4699 if (crtc_state->pipe_bpp > 24)
4703 * We compare against max which means we must take
4704 * the increased cdclk requirement into account when
4705 * calculating the new cdclk.
4707 * Should measure whether using a lower cdclk w/o IPS
4709 if (IS_BROADWELL(dev_priv) &&
4710 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
4716 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
4718 struct drm_i915_private *dev_priv =
4719 to_i915(crtc_state->uapi.crtc->dev);
4720 struct intel_atomic_state *state =
4721 to_intel_atomic_state(crtc_state->uapi.state);
4723 crtc_state->ips_enabled = false;
4725 if (!hsw_crtc_state_ips_capable(crtc_state))
4729 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4730 * enabled and disabled dynamically based on package C states,
4731 * user space can't make reliable use of the CRCs, so let's just
4732 * completely disable it.
4734 if (crtc_state->crc_enabled)
4737 /* IPS should be fine as long as at least one plane is enabled. */
4738 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
4741 if (IS_BROADWELL(dev_priv)) {
4742 const struct intel_cdclk_state *cdclk_state;
4744 cdclk_state = intel_atomic_get_cdclk_state(state);
4745 if (IS_ERR(cdclk_state))
4746 return PTR_ERR(cdclk_state);
4748 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
4749 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
4753 crtc_state->ips_enabled = true;
4758 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
4760 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4762 /* GDG double wide on either pipe, otherwise pipe A only */
4763 return INTEL_GEN(dev_priv) < 4 &&
4764 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
4767 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
4769 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
4770 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
4773 * We only use IF-ID interlacing. If we ever use
4774 * PF-ID we'll need to adjust the pixel_rate here.
4777 if (!crtc_state->pch_pfit.enabled)
4780 pipe_w = crtc_state->pipe_src_w;
4781 pipe_h = crtc_state->pipe_src_h;
4783 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
4784 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
4786 if (pipe_w < pfit_w)
4788 if (pipe_h < pfit_h)
4791 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
4792 !pfit_w || !pfit_h))
4795 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
4799 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
4800 const struct drm_display_mode *timings)
4802 mode->hdisplay = timings->crtc_hdisplay;
4803 mode->htotal = timings->crtc_htotal;
4804 mode->hsync_start = timings->crtc_hsync_start;
4805 mode->hsync_end = timings->crtc_hsync_end;
4807 mode->vdisplay = timings->crtc_vdisplay;
4808 mode->vtotal = timings->crtc_vtotal;
4809 mode->vsync_start = timings->crtc_vsync_start;
4810 mode->vsync_end = timings->crtc_vsync_end;
4812 mode->flags = timings->flags;
4813 mode->type = DRM_MODE_TYPE_DRIVER;
4815 mode->clock = timings->crtc_clock;
4817 drm_mode_set_name(mode);
4820 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
4822 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4824 if (HAS_GMCH(dev_priv))
4825 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
4826 crtc_state->pixel_rate =
4827 crtc_state->hw.pipe_mode.crtc_clock;
4829 crtc_state->pixel_rate =
4830 ilk_pipe_pixel_rate(crtc_state);
4833 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
4835 struct drm_display_mode *mode = &crtc_state->hw.mode;
4836 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4837 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4839 drm_mode_copy(pipe_mode, adjusted_mode);
4841 if (crtc_state->bigjoiner) {
4843 * transcoder is programmed to the full mode,
4844 * but pipe timings are half of the transcoder mode
4846 pipe_mode->crtc_hdisplay /= 2;
4847 pipe_mode->crtc_hblank_start /= 2;
4848 pipe_mode->crtc_hblank_end /= 2;
4849 pipe_mode->crtc_hsync_start /= 2;
4850 pipe_mode->crtc_hsync_end /= 2;
4851 pipe_mode->crtc_htotal /= 2;
4852 pipe_mode->crtc_clock /= 2;
4855 if (crtc_state->splitter.enable) {
4856 int n = crtc_state->splitter.link_count;
4857 int overlap = crtc_state->splitter.pixel_overlap;
4860 * eDP MSO uses segment timings from EDID for transcoder
4861 * timings, but full mode for everything else.
4863 * h_full = (h_segment - pixel_overlap) * link_count
4865 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4866 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4867 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4868 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4869 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4870 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4871 pipe_mode->crtc_clock *= n;
4873 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4874 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
4876 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4877 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
4880 intel_crtc_compute_pixel_rate(crtc_state);
4882 drm_mode_copy(mode, adjusted_mode);
4883 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
4884 mode->vdisplay = crtc_state->pipe_src_h;
4887 static void intel_encoder_get_config(struct intel_encoder *encoder,
4888 struct intel_crtc_state *crtc_state)
4890 encoder->get_config(encoder, crtc_state);
4892 intel_crtc_readout_derived_state(crtc_state);
4895 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4896 struct intel_crtc_state *pipe_config)
4898 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4899 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
4900 int clock_limit = dev_priv->max_dotclk_freq;
4902 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
4904 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
4905 if (pipe_config->bigjoiner) {
4906 pipe_mode->crtc_clock /= 2;
4907 pipe_mode->crtc_hdisplay /= 2;
4908 pipe_mode->crtc_hblank_start /= 2;
4909 pipe_mode->crtc_hblank_end /= 2;
4910 pipe_mode->crtc_hsync_start /= 2;
4911 pipe_mode->crtc_hsync_end /= 2;
4912 pipe_mode->crtc_htotal /= 2;
4913 pipe_config->pipe_src_w /= 2;
4916 if (pipe_config->splitter.enable) {
4917 int n = pipe_config->splitter.link_count;
4918 int overlap = pipe_config->splitter.pixel_overlap;
4920 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4921 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4922 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4923 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4924 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4925 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4926 pipe_mode->crtc_clock *= n;
4929 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4931 if (INTEL_GEN(dev_priv) < 4) {
4932 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
4935 * Enable double wide mode when the dot clock
4936 * is > 90% of the (display) core speed.
4938 if (intel_crtc_supports_double_wide(crtc) &&
4939 pipe_mode->crtc_clock > clock_limit) {
4940 clock_limit = dev_priv->max_dotclk_freq;
4941 pipe_config->double_wide = true;
4945 if (pipe_mode->crtc_clock > clock_limit) {
4946 drm_dbg_kms(&dev_priv->drm,
4947 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
4948 pipe_mode->crtc_clock, clock_limit,
4949 yesno(pipe_config->double_wide));
4954 * Pipe horizontal size must be even in:
4956 * - LVDS dual channel mode
4957 * - Double wide pipe
4959 if (pipe_config->pipe_src_w & 1) {
4960 if (pipe_config->double_wide) {
4961 drm_dbg_kms(&dev_priv->drm,
4962 "Odd pipe source width not supported with double wide pipe\n");
4966 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4967 intel_is_dual_link_lvds(dev_priv)) {
4968 drm_dbg_kms(&dev_priv->drm,
4969 "Odd pipe source width not supported with dual link LVDS\n");
4974 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4975 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4977 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
4978 pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
4981 intel_crtc_compute_pixel_rate(pipe_config);
4983 if (pipe_config->has_pch_encoder)
4984 return ilk_fdi_compute_config(crtc, pipe_config);
4990 intel_reduce_m_n_ratio(u32 *num, u32 *den)
4992 while (*num > DATA_LINK_M_N_MASK ||
4993 *den > DATA_LINK_M_N_MASK) {
4999 static void compute_m_n(unsigned int m, unsigned int n,
5000 u32 *ret_m, u32 *ret_n,
5004 * Several DP dongles in particular seem to be fussy about
5005 * too large link M/N values. Give N value as 0x8000 that
5006 * should be acceptable by specific devices. 0x8000 is the
5007 * specified fixed N value for asynchronous clock mode,
5008 * which the devices expect also in synchronous clock mode.
5011 *ret_n = DP_LINK_CONSTANT_N_VALUE;
5013 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5015 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
5016 intel_reduce_m_n_ratio(ret_m, ret_n);
5020 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
5021 int pixel_clock, int link_clock,
5022 struct intel_link_m_n *m_n,
5023 bool constant_n, bool fec_enable)
5025 u32 data_clock = bits_per_pixel * pixel_clock;
5028 data_clock = intel_dp_mode_to_fec_clock(data_clock);
5031 compute_m_n(data_clock,
5032 link_clock * nlanes * 8,
5033 &m_n->gmch_m, &m_n->gmch_n,
5036 compute_m_n(pixel_clock, link_clock,
5037 &m_n->link_m, &m_n->link_n,
5041 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
5044 * There may be no VBT; and if the BIOS enabled SSC we can
5045 * just keep using it to avoid unnecessary flicker. Whereas if the
5046 * BIOS isn't using it, don't assume it will work even if the VBT
5047 * indicates as much.
5049 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5050 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
5054 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
5055 drm_dbg_kms(&dev_priv->drm,
5056 "SSC %s by BIOS, overriding VBT which says %s\n",
5057 enableddisabled(bios_lvds_use_ssc),
5058 enableddisabled(dev_priv->vbt.lvds_use_ssc));
5059 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
5064 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
5065 const struct intel_link_m_n *m_n)
5067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5069 enum pipe pipe = crtc->pipe;
5071 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
5072 TU_SIZE(m_n->tu) | m_n->gmch_m);
5073 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5074 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5075 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5078 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
5079 enum transcoder transcoder)
5081 if (IS_HASWELL(dev_priv))
5082 return transcoder == TRANSCODER_EDP;
5085 * Strictly speaking some registers are available before
5086 * gen7, but we only support DRRS on gen7+
5088 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
5091 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
5092 const struct intel_link_m_n *m_n,
5093 const struct intel_link_m_n *m2_n2)
5095 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5096 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5097 enum pipe pipe = crtc->pipe;
5098 enum transcoder transcoder = crtc_state->cpu_transcoder;
5100 if (INTEL_GEN(dev_priv) >= 5) {
5101 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
5102 TU_SIZE(m_n->tu) | m_n->gmch_m);
5103 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
5105 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
5107 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
5110 * M2_N2 registers are set only if DRRS is supported
5111 * (to make sure the registers are not unnecessarily accessed).
5113 if (m2_n2 && crtc_state->has_drrs &&
5114 transcoder_has_m2_n2(dev_priv, transcoder)) {
5115 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
5116 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5117 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
5119 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
5121 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
5125 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
5126 TU_SIZE(m_n->tu) | m_n->gmch_m);
5127 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5128 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
5129 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
5133 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
5135 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
5136 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
5139 dp_m_n = &crtc_state->dp_m_n;
5140 dp_m2_n2 = &crtc_state->dp_m2_n2;
5141 } else if (m_n == M2_N2) {
5144 * M2_N2 registers are not supported. Hence m2_n2 divider value
5145 * needs to be programmed into M1_N1.
5147 dp_m_n = &crtc_state->dp_m2_n2;
5149 drm_err(&i915->drm, "Unsupported divider value\n");
5153 if (crtc_state->has_pch_encoder)
5154 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
5156 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
5159 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
5161 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5162 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5163 enum pipe pipe = crtc->pipe;
5164 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5165 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
5166 u32 crtc_vtotal, crtc_vblank_end;
5169 /* We need to be careful not to changed the adjusted mode, for otherwise
5170 * the hw state checker will get angry at the mismatch. */
5171 crtc_vtotal = adjusted_mode->crtc_vtotal;
5172 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5174 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5175 /* the chip adds 2 halflines automatically */
5177 crtc_vblank_end -= 1;
5179 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
5180 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5182 vsyncshift = adjusted_mode->crtc_hsync_start -
5183 adjusted_mode->crtc_htotal / 2;
5185 vsyncshift += adjusted_mode->crtc_htotal;
5188 if (INTEL_GEN(dev_priv) > 3)
5189 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
5192 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
5193 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
5194 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
5195 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
5196 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
5197 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
5199 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
5200 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
5201 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
5202 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
5203 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
5204 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
5206 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5207 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5208 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5210 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
5211 (pipe == PIPE_B || pipe == PIPE_C))
5212 intel_de_write(dev_priv, VTOTAL(pipe),
5213 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5217 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
5219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5221 enum pipe pipe = crtc->pipe;
5223 /* pipesrc controls the size that is scaled from, which should
5224 * always be the user's requested size.
5226 intel_de_write(dev_priv, PIPESRC(pipe),
5227 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
5230 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
5232 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5233 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5235 if (IS_GEN(dev_priv, 2))
5238 if (INTEL_GEN(dev_priv) >= 9 ||
5239 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
5240 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
5242 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
5245 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
5246 struct intel_crtc_state *pipe_config)
5248 struct drm_device *dev = crtc->base.dev;
5249 struct drm_i915_private *dev_priv = to_i915(dev);
5250 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5253 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
5254 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5255 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5257 if (!transcoder_is_dsi(cpu_transcoder)) {
5258 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
5259 pipe_config->hw.adjusted_mode.crtc_hblank_start =
5261 pipe_config->hw.adjusted_mode.crtc_hblank_end =
5262 ((tmp >> 16) & 0xffff) + 1;
5264 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
5265 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5266 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5268 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
5269 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5270 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5272 if (!transcoder_is_dsi(cpu_transcoder)) {
5273 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
5274 pipe_config->hw.adjusted_mode.crtc_vblank_start =
5276 pipe_config->hw.adjusted_mode.crtc_vblank_end =
5277 ((tmp >> 16) & 0xffff) + 1;
5279 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
5280 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5281 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5283 if (intel_pipe_is_interlaced(pipe_config)) {
5284 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5285 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
5286 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
5290 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
5291 struct intel_crtc_state *pipe_config)
5293 struct drm_device *dev = crtc->base.dev;
5294 struct drm_i915_private *dev_priv = to_i915(dev);
5297 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
5298 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5299 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5302 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
5304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5305 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5310 /* we keep both pipes enabled on 830 */
5311 if (IS_I830(dev_priv))
5312 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
5314 if (crtc_state->double_wide)
5315 pipeconf |= PIPECONF_DOUBLE_WIDE;
5317 /* only g4x and later have fancy bpc/dither controls */
5318 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5319 IS_CHERRYVIEW(dev_priv)) {
5320 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5321 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
5322 pipeconf |= PIPECONF_DITHER_EN |
5323 PIPECONF_DITHER_TYPE_SP;
5325 switch (crtc_state->pipe_bpp) {
5327 pipeconf |= PIPECONF_6BPC;
5330 pipeconf |= PIPECONF_8BPC;
5333 pipeconf |= PIPECONF_10BPC;
5336 /* Case prevented by intel_choose_pipe_bpp_dither. */
5341 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5342 if (INTEL_GEN(dev_priv) < 4 ||
5343 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
5344 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5346 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5348 pipeconf |= PIPECONF_PROGRESSIVE;
5351 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5352 crtc_state->limited_color_range)
5353 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5355 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
5357 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
5359 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
5360 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
5363 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
5365 if (IS_I830(dev_priv))
5368 return INTEL_GEN(dev_priv) >= 4 ||
5369 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
5372 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
5374 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5375 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5378 if (!i9xx_has_pfit(dev_priv))
5381 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
5382 if (!(tmp & PFIT_ENABLE))
5385 /* Check whether the pfit is attached to our pipe. */
5386 if (INTEL_GEN(dev_priv) < 4) {
5387 if (crtc->pipe != PIPE_B)
5390 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5394 crtc_state->gmch_pfit.control = tmp;
5395 crtc_state->gmch_pfit.pgm_ratios =
5396 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
5399 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5400 struct intel_crtc_state *pipe_config)
5402 struct drm_device *dev = crtc->base.dev;
5403 struct drm_i915_private *dev_priv = to_i915(dev);
5404 enum pipe pipe = crtc->pipe;
5407 int refclk = 100000;
5409 /* In case of DSI, DPLL will not be used */
5410 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
5413 vlv_dpio_get(dev_priv);
5414 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5415 vlv_dpio_put(dev_priv);
5417 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5418 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5419 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5420 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5421 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5423 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
5426 static void chv_crtc_clock_get(struct intel_crtc *crtc,
5427 struct intel_crtc_state *pipe_config)
5429 struct drm_device *dev = crtc->base.dev;
5430 struct drm_i915_private *dev_priv = to_i915(dev);
5431 enum pipe pipe = crtc->pipe;
5432 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5434 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
5435 int refclk = 100000;
5437 /* In case of DSI, DPLL will not be used */
5438 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
5441 vlv_dpio_get(dev_priv);
5442 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
5443 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
5444 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
5445 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
5446 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
5447 vlv_dpio_put(dev_priv);
5449 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
5450 clock.m2 = (pll_dw0 & 0xff) << 22;
5451 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
5452 clock.m2 |= pll_dw2 & 0x3fffff;
5453 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
5454 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
5455 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
5457 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
5460 static enum intel_output_format
5461 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
5463 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5466 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
5468 if (tmp & PIPEMISC_YUV420_ENABLE) {
5469 /* We support 4:2:0 in full blend mode only */
5470 drm_WARN_ON(&dev_priv->drm,
5471 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
5473 return INTEL_OUTPUT_FORMAT_YCBCR420;
5474 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
5475 return INTEL_OUTPUT_FORMAT_YCBCR444;
5477 return INTEL_OUTPUT_FORMAT_RGB;
5481 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
5483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5484 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5486 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
5489 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
5491 if (tmp & DISPPLANE_GAMMA_ENABLE)
5492 crtc_state->gamma_enable = true;
5494 if (!HAS_GMCH(dev_priv) &&
5495 tmp & DISPPLANE_PIPE_CSC_ENABLE)
5496 crtc_state->csc_enable = true;
5499 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5500 struct intel_crtc_state *pipe_config)
5502 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5503 enum intel_display_power_domain power_domain;
5504 intel_wakeref_t wakeref;
5508 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
5509 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
5513 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
5514 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5515 pipe_config->shared_dpll = NULL;
5519 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
5520 if (!(tmp & PIPECONF_ENABLE))
5523 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5524 IS_CHERRYVIEW(dev_priv)) {
5525 switch (tmp & PIPECONF_BPC_MASK) {
5527 pipe_config->pipe_bpp = 18;
5530 pipe_config->pipe_bpp = 24;
5532 case PIPECONF_10BPC:
5533 pipe_config->pipe_bpp = 30;
5540 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5541 (tmp & PIPECONF_COLOR_RANGE_SELECT))
5542 pipe_config->limited_color_range = true;
5544 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
5545 PIPECONF_GAMMA_MODE_SHIFT;
5547 if (IS_CHERRYVIEW(dev_priv))
5548 pipe_config->cgm_mode = intel_de_read(dev_priv,
5549 CGM_PIPE_MODE(crtc->pipe));
5551 i9xx_get_pipe_color_config(pipe_config);
5552 intel_color_get_config(pipe_config);
5554 if (INTEL_GEN(dev_priv) < 4)
5555 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5557 intel_get_transcoder_timings(crtc, pipe_config);
5558 intel_get_pipe_src_size(crtc, pipe_config);
5560 i9xx_get_pfit_config(pipe_config);
5562 if (INTEL_GEN(dev_priv) >= 4) {
5563 /* No way to read it out on pipes B and C */
5564 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
5565 tmp = dev_priv->chv_dpll_md[crtc->pipe];
5567 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
5568 pipe_config->pixel_multiplier =
5569 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5570 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5571 pipe_config->dpll_hw_state.dpll_md = tmp;
5572 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
5573 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
5574 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
5575 pipe_config->pixel_multiplier =
5576 ((tmp & SDVO_MULTIPLIER_MASK)
5577 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5579 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5580 * port and will be fixed up in the encoder->get_config
5582 pipe_config->pixel_multiplier = 1;
5584 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
5586 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
5587 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
5589 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
5592 /* Mask out read-only status bits. */
5593 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5594 DPLL_PORTC_READY_MASK |
5595 DPLL_PORTB_READY_MASK);
5598 if (IS_CHERRYVIEW(dev_priv))
5599 chv_crtc_clock_get(crtc, pipe_config);
5600 else if (IS_VALLEYVIEW(dev_priv))
5601 vlv_crtc_clock_get(crtc, pipe_config);
5603 i9xx_crtc_clock_get(crtc, pipe_config);
5606 * Normally the dotclock is filled in by the encoder .get_config()
5607 * but in case the pipe is enabled w/o any ports we need a sane
5610 pipe_config->hw.adjusted_mode.crtc_clock =
5611 pipe_config->port_clock / pipe_config->pixel_multiplier;
5616 intel_display_power_put(dev_priv, power_domain, wakeref);
5621 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
5623 struct intel_encoder *encoder;
5626 bool has_lvds = false;
5627 bool has_cpu_edp = false;
5628 bool has_panel = false;
5629 bool has_ck505 = false;
5630 bool can_ssc = false;
5631 bool using_ssc_source = false;
5633 /* We need to take the global config into account */
5634 for_each_intel_encoder(&dev_priv->drm, encoder) {
5635 switch (encoder->type) {
5636 case INTEL_OUTPUT_LVDS:
5640 case INTEL_OUTPUT_EDP:
5642 if (encoder->port == PORT_A)
5650 if (HAS_PCH_IBX(dev_priv)) {
5651 has_ck505 = dev_priv->vbt.display_clock_mode;
5652 can_ssc = has_ck505;
5658 /* Check if any DPLLs are using the SSC source */
5659 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
5660 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
5662 if (!(temp & DPLL_VCO_ENABLE))
5665 if ((temp & PLL_REF_INPUT_MASK) ==
5666 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5667 using_ssc_source = true;
5672 drm_dbg_kms(&dev_priv->drm,
5673 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
5674 has_panel, has_lvds, has_ck505, using_ssc_source);
5676 /* Ironlake: try to setup display ref clock before DPLL
5677 * enabling. This is only under driver's control after
5678 * PCH B stepping, previous chipset stepping should be
5679 * ignoring this setting.
5681 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
5683 /* As we must carefully and slowly disable/enable each source in turn,
5684 * compute the final state we want first and check if we need to
5685 * make any changes at all.
5688 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5690 final |= DREF_NONSPREAD_CK505_ENABLE;
5692 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5694 final &= ~DREF_SSC_SOURCE_MASK;
5695 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5696 final &= ~DREF_SSC1_ENABLE;
5699 final |= DREF_SSC_SOURCE_ENABLE;
5701 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5702 final |= DREF_SSC1_ENABLE;
5705 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5706 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5708 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5710 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5711 } else if (using_ssc_source) {
5712 final |= DREF_SSC_SOURCE_ENABLE;
5713 final |= DREF_SSC1_ENABLE;
5719 /* Always enable nonspread source */
5720 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5723 val |= DREF_NONSPREAD_CK505_ENABLE;
5725 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5728 val &= ~DREF_SSC_SOURCE_MASK;
5729 val |= DREF_SSC_SOURCE_ENABLE;
5731 /* SSC must be turned on before enabling the CPU output */
5732 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5733 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
5734 val |= DREF_SSC1_ENABLE;
5736 val &= ~DREF_SSC1_ENABLE;
5738 /* Get SSC going before enabling the outputs */
5739 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5740 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5743 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5745 /* Enable CPU source on CPU attached eDP */
5747 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5748 drm_dbg_kms(&dev_priv->drm,
5749 "Using SSC on eDP\n");
5750 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5752 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5754 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5756 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5757 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5760 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
5762 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5764 /* Turn off CPU output */
5765 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5767 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5768 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5771 if (!using_ssc_source) {
5772 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
5774 /* Turn off the SSC source */
5775 val &= ~DREF_SSC_SOURCE_MASK;
5776 val |= DREF_SSC_SOURCE_DISABLE;
5779 val &= ~DREF_SSC1_ENABLE;
5781 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5782 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5787 BUG_ON(val != final);
5790 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5794 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5795 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5796 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5798 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5799 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5800 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
5802 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5803 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5804 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5806 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5807 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5808 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
5811 /* WaMPhyProgramming:hsw */
5812 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5816 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5817 tmp &= ~(0xFF << 24);
5818 tmp |= (0x12 << 24);
5819 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5821 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5823 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5825 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5827 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5829 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5830 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5831 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5833 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5834 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5835 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5837 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5840 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5842 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5845 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5847 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5850 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5852 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5855 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5857 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5858 tmp &= ~(0xFF << 16);
5859 tmp |= (0x1C << 16);
5860 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5862 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5863 tmp &= ~(0xFF << 16);
5864 tmp |= (0x1C << 16);
5865 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5867 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5869 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5871 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5873 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5875 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5876 tmp &= ~(0xF << 28);
5878 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5880 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5881 tmp &= ~(0xF << 28);
5883 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5886 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5887 * Programming" based on the parameters passed:
5888 * - Sequence to enable CLKOUT_DP
5889 * - Sequence to enable CLKOUT_DP without spread
5890 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5892 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
5893 bool with_spread, bool with_fdi)
5897 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
5898 "FDI requires downspread\n"))
5900 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
5901 with_fdi, "LP PCH doesn't have FDI\n"))
5904 mutex_lock(&dev_priv->sb_lock);
5906 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5907 tmp &= ~SBI_SSCCTL_DISABLE;
5908 tmp |= SBI_SSCCTL_PATHALT;
5909 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5914 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5915 tmp &= ~SBI_SSCCTL_PATHALT;
5916 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5919 lpt_reset_fdi_mphy(dev_priv);
5920 lpt_program_fdi_mphy(dev_priv);
5924 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5925 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5926 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5927 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5929 mutex_unlock(&dev_priv->sb_lock);
5932 /* Sequence to disable CLKOUT_DP */
5933 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
5937 mutex_lock(&dev_priv->sb_lock);
5939 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5940 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5941 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5942 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5944 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5945 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5946 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5947 tmp |= SBI_SSCCTL_PATHALT;
5948 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5951 tmp |= SBI_SSCCTL_DISABLE;
5952 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5955 mutex_unlock(&dev_priv->sb_lock);
5958 #define BEND_IDX(steps) ((50 + (steps)) / 5)
5960 static const u16 sscdivintphase[] = {
5961 [BEND_IDX( 50)] = 0x3B23,
5962 [BEND_IDX( 45)] = 0x3B23,
5963 [BEND_IDX( 40)] = 0x3C23,
5964 [BEND_IDX( 35)] = 0x3C23,
5965 [BEND_IDX( 30)] = 0x3D23,
5966 [BEND_IDX( 25)] = 0x3D23,
5967 [BEND_IDX( 20)] = 0x3E23,
5968 [BEND_IDX( 15)] = 0x3E23,
5969 [BEND_IDX( 10)] = 0x3F23,
5970 [BEND_IDX( 5)] = 0x3F23,
5971 [BEND_IDX( 0)] = 0x0025,
5972 [BEND_IDX( -5)] = 0x0025,
5973 [BEND_IDX(-10)] = 0x0125,
5974 [BEND_IDX(-15)] = 0x0125,
5975 [BEND_IDX(-20)] = 0x0225,
5976 [BEND_IDX(-25)] = 0x0225,
5977 [BEND_IDX(-30)] = 0x0325,
5978 [BEND_IDX(-35)] = 0x0325,
5979 [BEND_IDX(-40)] = 0x0425,
5980 [BEND_IDX(-45)] = 0x0425,
5981 [BEND_IDX(-50)] = 0x0525,
5986 * steps -50 to 50 inclusive, in steps of 5
5987 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
5988 * change in clock period = -(steps / 10) * 5.787 ps
5990 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
5993 int idx = BEND_IDX(steps);
5995 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
5998 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
6001 mutex_lock(&dev_priv->sb_lock);
6003 if (steps % 10 != 0)
6007 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
6009 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
6011 tmp |= sscdivintphase[idx];
6012 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
6014 mutex_unlock(&dev_priv->sb_lock);
6019 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
6021 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
6022 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
6024 if ((ctl & SPLL_PLL_ENABLE) == 0)
6027 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
6028 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
6031 if (IS_BROADWELL(dev_priv) &&
6032 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
6038 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
6039 enum intel_dpll_id id)
6041 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
6042 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
6044 if ((ctl & WRPLL_PLL_ENABLE) == 0)
6047 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
6050 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
6051 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
6052 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
6058 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
6060 struct intel_encoder *encoder;
6061 bool has_fdi = false;
6063 for_each_intel_encoder(&dev_priv->drm, encoder) {
6064 switch (encoder->type) {
6065 case INTEL_OUTPUT_ANALOG:
6074 * The BIOS may have decided to use the PCH SSC
6075 * reference so we must not disable it until the
6076 * relevant PLLs have stopped relying on it. We'll
6077 * just leave the PCH SSC reference enabled in case
6078 * any active PLL is using it. It will get disabled
6079 * after runtime suspend if we don't have FDI.
6081 * TODO: Move the whole reference clock handling
6082 * to the modeset sequence proper so that we can
6083 * actually enable/disable/reconfigure these things
6084 * safely. To do that we need to introduce a real
6085 * clock hierarchy. That would also allow us to do
6086 * clock bending finally.
6088 dev_priv->pch_ssc_use = 0;
6090 if (spll_uses_pch_ssc(dev_priv)) {
6091 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
6092 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
6095 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
6096 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
6097 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
6100 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
6101 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
6102 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
6105 if (dev_priv->pch_ssc_use)
6109 lpt_bend_clkout_dp(dev_priv, 0);
6110 lpt_enable_clkout_dp(dev_priv, true, true);
6112 lpt_disable_clkout_dp(dev_priv);
6117 * Initialize reference clocks when the driver loads
6119 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
6121 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
6122 ilk_init_pch_refclk(dev_priv);
6123 else if (HAS_PCH_LPT(dev_priv))
6124 lpt_init_pch_refclk(dev_priv);
6127 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
6129 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6130 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6131 enum pipe pipe = crtc->pipe;
6136 switch (crtc_state->pipe_bpp) {
6138 val |= PIPECONF_6BPC;
6141 val |= PIPECONF_8BPC;
6144 val |= PIPECONF_10BPC;
6147 val |= PIPECONF_12BPC;
6150 /* Case prevented by intel_choose_pipe_bpp_dither. */
6154 if (crtc_state->dither)
6155 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6157 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6158 val |= PIPECONF_INTERLACED_ILK;
6160 val |= PIPECONF_PROGRESSIVE;
6163 * This would end up with an odd purple hue over
6164 * the entire display. Make sure we don't do it.
6166 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
6167 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
6169 if (crtc_state->limited_color_range &&
6170 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
6171 val |= PIPECONF_COLOR_RANGE_SELECT;
6173 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
6174 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
6176 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
6178 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
6180 intel_de_write(dev_priv, PIPECONF(pipe), val);
6181 intel_de_posting_read(dev_priv, PIPECONF(pipe));
6184 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
6186 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6187 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6188 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
6191 if (IS_HASWELL(dev_priv) && crtc_state->dither)
6192 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6194 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6195 val |= PIPECONF_INTERLACED_ILK;
6197 val |= PIPECONF_PROGRESSIVE;
6199 if (IS_HASWELL(dev_priv) &&
6200 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
6201 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
6203 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
6204 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
6207 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
6209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6213 switch (crtc_state->pipe_bpp) {
6215 val |= PIPEMISC_DITHER_6_BPC;
6218 val |= PIPEMISC_DITHER_8_BPC;
6221 val |= PIPEMISC_DITHER_10_BPC;
6224 val |= PIPEMISC_DITHER_12_BPC;
6227 MISSING_CASE(crtc_state->pipe_bpp);
6231 if (crtc_state->dither)
6232 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6234 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6235 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
6236 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
6238 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
6239 val |= PIPEMISC_YUV420_ENABLE |
6240 PIPEMISC_YUV420_MODE_FULL_BLEND;
6242 if (INTEL_GEN(dev_priv) >= 11 &&
6243 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
6244 BIT(PLANE_CURSOR))) == 0)
6245 val |= PIPEMISC_HDR_MODE_PRECISION;
6247 if (INTEL_GEN(dev_priv) >= 12)
6248 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
6250 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
6253 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
6255 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6258 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
6260 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
6261 case PIPEMISC_DITHER_6_BPC:
6263 case PIPEMISC_DITHER_8_BPC:
6265 case PIPEMISC_DITHER_10_BPC:
6267 case PIPEMISC_DITHER_12_BPC:
6275 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
6278 * Account for spread spectrum to avoid
6279 * oversubscribing the link. Max center spread
6280 * is 2.5%; use 5% for safety's sake.
6282 u32 bps = target_clock * bpp * 21 / 20;
6283 return DIV_ROUND_UP(bps, link_bw * 8);
6286 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6287 struct intel_link_m_n *m_n)
6289 struct drm_device *dev = crtc->base.dev;
6290 struct drm_i915_private *dev_priv = to_i915(dev);
6291 enum pipe pipe = crtc->pipe;
6293 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
6294 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
6295 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
6297 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
6298 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
6299 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6302 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6303 enum transcoder transcoder,
6304 struct intel_link_m_n *m_n,
6305 struct intel_link_m_n *m2_n2)
6307 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6308 enum pipe pipe = crtc->pipe;
6310 if (INTEL_GEN(dev_priv) >= 5) {
6311 m_n->link_m = intel_de_read(dev_priv,
6312 PIPE_LINK_M1(transcoder));
6313 m_n->link_n = intel_de_read(dev_priv,
6314 PIPE_LINK_N1(transcoder));
6315 m_n->gmch_m = intel_de_read(dev_priv,
6316 PIPE_DATA_M1(transcoder))
6318 m_n->gmch_n = intel_de_read(dev_priv,
6319 PIPE_DATA_N1(transcoder));
6320 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
6321 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6323 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
6324 m2_n2->link_m = intel_de_read(dev_priv,
6325 PIPE_LINK_M2(transcoder));
6326 m2_n2->link_n = intel_de_read(dev_priv,
6327 PIPE_LINK_N2(transcoder));
6328 m2_n2->gmch_m = intel_de_read(dev_priv,
6329 PIPE_DATA_M2(transcoder))
6331 m2_n2->gmch_n = intel_de_read(dev_priv,
6332 PIPE_DATA_N2(transcoder));
6333 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
6334 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6337 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
6338 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
6339 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
6341 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
6342 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
6343 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6347 void intel_dp_get_m_n(struct intel_crtc *crtc,
6348 struct intel_crtc_state *pipe_config)
6350 if (pipe_config->has_pch_encoder)
6351 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6353 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6354 &pipe_config->dp_m_n,
6355 &pipe_config->dp_m2_n2);
6358 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
6359 struct intel_crtc_state *pipe_config)
6361 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6362 &pipe_config->fdi_m_n, NULL);
6365 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
6368 drm_rect_init(&crtc_state->pch_pfit.dst,
6369 pos >> 16, pos & 0xffff,
6370 size >> 16, size & 0xffff);
6373 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
6375 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6377 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
6381 /* find scaler attached to this pipe */
6382 for (i = 0; i < crtc->num_scalers; i++) {
6385 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
6386 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
6390 crtc_state->pch_pfit.enabled = true;
6392 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
6393 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
6395 ilk_get_pfit_pos_size(crtc_state, pos, size);
6397 scaler_state->scalers[i].in_use = true;
6401 scaler_state->scaler_id = id;
6403 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
6405 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
6408 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
6410 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6414 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
6415 if ((ctl & PF_ENABLE) == 0)
6418 crtc_state->pch_pfit.enabled = true;
6420 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
6421 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
6423 ilk_get_pfit_pos_size(crtc_state, pos, size);
6426 * We currently do not free assignements of panel fitters on
6427 * ivb/hsw (since we don't use the higher upscaling modes which
6428 * differentiates them) so just WARN about this case for now.
6430 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
6431 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
6434 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
6435 struct intel_crtc_state *pipe_config)
6437 struct drm_device *dev = crtc->base.dev;
6438 struct drm_i915_private *dev_priv = to_i915(dev);
6439 enum intel_display_power_domain power_domain;
6440 intel_wakeref_t wakeref;
6444 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
6445 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
6449 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6450 pipe_config->shared_dpll = NULL;
6453 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
6454 if (!(tmp & PIPECONF_ENABLE))
6457 switch (tmp & PIPECONF_BPC_MASK) {
6459 pipe_config->pipe_bpp = 18;
6462 pipe_config->pipe_bpp = 24;
6464 case PIPECONF_10BPC:
6465 pipe_config->pipe_bpp = 30;
6467 case PIPECONF_12BPC:
6468 pipe_config->pipe_bpp = 36;
6474 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
6475 pipe_config->limited_color_range = true;
6477 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
6478 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
6479 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
6480 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6483 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6487 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
6488 PIPECONF_GAMMA_MODE_SHIFT;
6490 pipe_config->csc_mode = intel_de_read(dev_priv,
6491 PIPE_CSC_MODE(crtc->pipe));
6493 i9xx_get_pipe_color_config(pipe_config);
6494 intel_color_get_config(pipe_config);
6496 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6497 struct intel_shared_dpll *pll;
6498 enum intel_dpll_id pll_id;
6501 pipe_config->has_pch_encoder = true;
6503 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
6504 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6505 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6507 ilk_get_fdi_m_n_config(crtc, pipe_config);
6509 if (HAS_PCH_IBX(dev_priv)) {
6511 * The pipe->pch transcoder and pch transcoder->pll
6514 pll_id = (enum intel_dpll_id) crtc->pipe;
6516 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
6517 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6518 pll_id = DPLL_ID_PCH_PLL_B;
6520 pll_id= DPLL_ID_PCH_PLL_A;
6523 pipe_config->shared_dpll =
6524 intel_get_shared_dpll_by_id(dev_priv, pll_id);
6525 pll = pipe_config->shared_dpll;
6527 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
6528 &pipe_config->dpll_hw_state);
6529 drm_WARN_ON(dev, !pll_active);
6531 tmp = pipe_config->dpll_hw_state.dpll;
6532 pipe_config->pixel_multiplier =
6533 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6534 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6536 ilk_pch_clock_get(crtc, pipe_config);
6538 pipe_config->pixel_multiplier = 1;
6541 intel_get_transcoder_timings(crtc, pipe_config);
6542 intel_get_pipe_src_size(crtc, pipe_config);
6544 ilk_get_pfit_config(pipe_config);
6549 intel_display_power_put(dev_priv, power_domain, wakeref);
6554 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
6555 struct intel_crtc_state *pipe_config,
6556 struct intel_display_power_domain_set *power_domain_set)
6558 struct drm_device *dev = crtc->base.dev;
6559 struct drm_i915_private *dev_priv = to_i915(dev);
6560 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
6561 unsigned long enabled_panel_transcoders = 0;
6562 enum transcoder panel_transcoder;
6565 if (INTEL_GEN(dev_priv) >= 11)
6566 panel_transcoder_mask |=
6567 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
6570 * The pipe->transcoder mapping is fixed with the exception of the eDP
6571 * and DSI transcoders handled below.
6573 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6576 * XXX: Do intel_display_power_get_if_enabled before reading this (for
6577 * consistency and less surprising code; it's in always on power).
6579 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
6580 panel_transcoder_mask) {
6581 bool force_thru = false;
6582 enum pipe trans_pipe;
6584 tmp = intel_de_read(dev_priv,
6585 TRANS_DDI_FUNC_CTL(panel_transcoder));
6586 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6590 * Log all enabled ones, only use the first one.
6592 * FIXME: This won't work for two separate DSI displays.
6594 enabled_panel_transcoders |= BIT(panel_transcoder);
6595 if (enabled_panel_transcoders != BIT(panel_transcoder))
6598 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6601 "unknown pipe linked to transcoder %s\n",
6602 transcoder_name(panel_transcoder));
6604 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6607 case TRANS_DDI_EDP_INPUT_A_ON:
6608 trans_pipe = PIPE_A;
6610 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6611 trans_pipe = PIPE_B;
6613 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6614 trans_pipe = PIPE_C;
6616 case TRANS_DDI_EDP_INPUT_D_ONOFF:
6617 trans_pipe = PIPE_D;
6621 if (trans_pipe == crtc->pipe) {
6622 pipe_config->cpu_transcoder = panel_transcoder;
6623 pipe_config->pch_pfit.force_thru = force_thru;
6628 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
6630 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
6631 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
6633 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6634 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6637 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
6639 return tmp & PIPECONF_ENABLE;
6642 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
6643 struct intel_crtc_state *pipe_config,
6644 struct intel_display_power_domain_set *power_domain_set)
6646 struct drm_device *dev = crtc->base.dev;
6647 struct drm_i915_private *dev_priv = to_i915(dev);
6648 enum transcoder cpu_transcoder;
6652 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
6654 cpu_transcoder = TRANSCODER_DSI_A;
6656 cpu_transcoder = TRANSCODER_DSI_C;
6658 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6659 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6663 * The PLL needs to be enabled with a valid divider
6664 * configuration, otherwise accessing DSI registers will hang
6665 * the machine. See BSpec North Display Engine
6666 * registers/MIPI[BXT]. We can break out here early, since we
6667 * need the same DSI PLL to be enabled for both DSI ports.
6669 if (!bxt_dsi_pll_is_enabled(dev_priv))
6672 /* XXX: this works for video mode only */
6673 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
6674 if (!(tmp & DPI_ENABLE))
6677 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
6678 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
6681 pipe_config->cpu_transcoder = cpu_transcoder;
6685 return transcoder_is_dsi(pipe_config->cpu_transcoder);
6688 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
6689 struct intel_crtc_state *pipe_config)
6691 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6692 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6696 if (transcoder_is_dsi(cpu_transcoder)) {
6697 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
6700 tmp = intel_de_read(dev_priv,
6701 TRANS_DDI_FUNC_CTL(cpu_transcoder));
6702 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6704 if (INTEL_GEN(dev_priv) >= 12)
6705 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6707 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6711 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6712 * DDI E. So just check whether this pipe is wired to DDI E and whether
6713 * the PCH transcoder is on.
6715 if (INTEL_GEN(dev_priv) < 9 &&
6716 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
6717 pipe_config->has_pch_encoder = true;
6719 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
6720 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6721 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6723 ilk_get_fdi_m_n_config(crtc, pipe_config);
6727 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
6728 struct intel_crtc_state *pipe_config)
6730 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6731 struct intel_display_power_domain_set power_domain_set = { };
6735 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6736 POWER_DOMAIN_PIPE(crtc->pipe)))
6739 pipe_config->shared_dpll = NULL;
6741 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
6743 if (IS_GEN9_LP(dev_priv) &&
6744 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
6745 drm_WARN_ON(&dev_priv->drm, active);
6749 intel_dsc_get_config(pipe_config);
6752 /* bigjoiner slave doesn't enable transcoder */
6753 if (!pipe_config->bigjoiner_slave)
6757 pipe_config->pixel_multiplier = 1;
6759 /* we cannot read out most state, so don't bother.. */
6760 pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
6761 } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
6762 INTEL_GEN(dev_priv) >= 11) {
6763 hsw_get_ddi_port_state(crtc, pipe_config);
6764 intel_get_transcoder_timings(crtc, pipe_config);
6767 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
6768 intel_vrr_get_config(crtc, pipe_config);
6770 intel_get_pipe_src_size(crtc, pipe_config);
6772 if (IS_HASWELL(dev_priv)) {
6773 u32 tmp = intel_de_read(dev_priv,
6774 PIPECONF(pipe_config->cpu_transcoder));
6776 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
6777 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6779 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6781 pipe_config->output_format =
6782 bdw_get_pipemisc_output_format(crtc);
6785 pipe_config->gamma_mode = intel_de_read(dev_priv,
6786 GAMMA_MODE(crtc->pipe));
6788 pipe_config->csc_mode = intel_de_read(dev_priv,
6789 PIPE_CSC_MODE(crtc->pipe));
6791 if (INTEL_GEN(dev_priv) >= 9) {
6792 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
6794 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
6795 pipe_config->gamma_enable = true;
6797 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
6798 pipe_config->csc_enable = true;
6800 i9xx_get_pipe_color_config(pipe_config);
6803 intel_color_get_config(pipe_config);
6805 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
6806 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
6807 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6808 pipe_config->ips_linetime =
6809 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
6811 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6812 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
6813 if (INTEL_GEN(dev_priv) >= 9)
6814 skl_get_pfit_config(pipe_config);
6816 ilk_get_pfit_config(pipe_config);
6819 if (hsw_crtc_supports_ips(crtc)) {
6820 if (IS_HASWELL(dev_priv))
6821 pipe_config->ips_enabled = intel_de_read(dev_priv,
6822 IPS_CTL) & IPS_ENABLE;
6825 * We cannot readout IPS state on broadwell, set to
6826 * true so we can set it to a defined state on first
6829 pipe_config->ips_enabled = true;
6833 if (pipe_config->bigjoiner_slave) {
6834 /* Cannot be read out as a slave, set to 0. */
6835 pipe_config->pixel_multiplier = 0;
6836 } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
6837 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
6838 pipe_config->pixel_multiplier =
6839 intel_de_read(dev_priv,
6840 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
6842 pipe_config->pixel_multiplier = 1;
6846 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
6851 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
6853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6854 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6856 if (!i915->display.get_pipe_config(crtc, crtc_state))
6859 crtc_state->hw.active = true;
6861 intel_crtc_readout_derived_state(crtc_state);
6866 /* VESA 640x480x72Hz mode to set on the pipe */
6867 static const struct drm_display_mode load_detect_mode = {
6868 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6869 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6872 struct drm_framebuffer *
6873 intel_framebuffer_create(struct drm_i915_gem_object *obj,
6874 struct drm_mode_fb_cmd2 *mode_cmd)
6876 struct intel_framebuffer *intel_fb;
6879 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6881 return ERR_PTR(-ENOMEM);
6883 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
6887 return &intel_fb->base;
6891 return ERR_PTR(ret);
6894 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
6895 struct drm_crtc *crtc)
6897 struct drm_plane *plane;
6898 struct drm_plane_state *plane_state;
6901 ret = drm_atomic_add_affected_planes(state, crtc);
6905 for_each_new_plane_in_state(state, plane, plane_state, i) {
6906 if (plane_state->crtc != crtc)
6909 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
6913 drm_atomic_set_fb_for_plane(plane_state, NULL);
6919 int intel_get_load_detect_pipe(struct drm_connector *connector,
6920 struct intel_load_detect_pipe *old,
6921 struct drm_modeset_acquire_ctx *ctx)
6923 struct intel_crtc *intel_crtc;
6924 struct intel_encoder *intel_encoder =
6925 intel_attached_encoder(to_intel_connector(connector));
6926 struct drm_crtc *possible_crtc;
6927 struct drm_encoder *encoder = &intel_encoder->base;
6928 struct drm_crtc *crtc = NULL;
6929 struct drm_device *dev = encoder->dev;
6930 struct drm_i915_private *dev_priv = to_i915(dev);
6931 struct drm_mode_config *config = &dev->mode_config;
6932 struct drm_atomic_state *state = NULL, *restore_state = NULL;
6933 struct drm_connector_state *connector_state;
6934 struct intel_crtc_state *crtc_state;
6937 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6938 connector->base.id, connector->name,
6939 encoder->base.id, encoder->name);
6941 old->restore_state = NULL;
6943 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
6946 * Algorithm gets a little messy:
6948 * - if the connector already has an assigned crtc, use it (but make
6949 * sure it's on first)
6951 * - try to find the first unused crtc that can drive this connector,
6952 * and use that if we find one
6955 /* See if we already have a CRTC for this connector */
6956 if (connector->state->crtc) {
6957 crtc = connector->state->crtc;
6959 ret = drm_modeset_lock(&crtc->mutex, ctx);
6963 /* Make sure the crtc and connector are running */
6967 /* Find an unused one (if possible) */
6968 for_each_crtc(dev, possible_crtc) {
6970 if (!(encoder->possible_crtcs & (1 << i)))
6973 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
6977 if (possible_crtc->state->enable) {
6978 drm_modeset_unlock(&possible_crtc->mutex);
6982 crtc = possible_crtc;
6987 * If we didn't find an unused CRTC, don't use any.
6990 drm_dbg_kms(&dev_priv->drm,
6991 "no pipe available for load-detect\n");
6997 intel_crtc = to_intel_crtc(crtc);
6999 state = drm_atomic_state_alloc(dev);
7000 restore_state = drm_atomic_state_alloc(dev);
7001 if (!state || !restore_state) {
7006 state->acquire_ctx = ctx;
7007 restore_state->acquire_ctx = ctx;
7009 connector_state = drm_atomic_get_connector_state(state, connector);
7010 if (IS_ERR(connector_state)) {
7011 ret = PTR_ERR(connector_state);
7015 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
7019 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
7020 if (IS_ERR(crtc_state)) {
7021 ret = PTR_ERR(crtc_state);
7025 crtc_state->uapi.active = true;
7027 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
7032 ret = intel_modeset_disable_planes(state, crtc);
7036 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
7038 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
7040 ret = drm_atomic_add_affected_planes(restore_state, crtc);
7042 drm_dbg_kms(&dev_priv->drm,
7043 "Failed to create a copy of old state to restore: %i\n",
7048 ret = drm_atomic_commit(state);
7050 drm_dbg_kms(&dev_priv->drm,
7051 "failed to set mode on load-detect pipe\n");
7055 old->restore_state = restore_state;
7056 drm_atomic_state_put(state);
7058 /* let the connector get through one full cycle before testing */
7059 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
7064 drm_atomic_state_put(state);
7067 if (restore_state) {
7068 drm_atomic_state_put(restore_state);
7069 restore_state = NULL;
7072 if (ret == -EDEADLK)
7078 void intel_release_load_detect_pipe(struct drm_connector *connector,
7079 struct intel_load_detect_pipe *old,
7080 struct drm_modeset_acquire_ctx *ctx)
7082 struct intel_encoder *intel_encoder =
7083 intel_attached_encoder(to_intel_connector(connector));
7084 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
7085 struct drm_encoder *encoder = &intel_encoder->base;
7086 struct drm_atomic_state *state = old->restore_state;
7089 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7090 connector->base.id, connector->name,
7091 encoder->base.id, encoder->name);
7096 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
7098 drm_dbg_kms(&i915->drm,
7099 "Couldn't release load detect pipe: %i\n", ret);
7100 drm_atomic_state_put(state);
7103 static int i9xx_pll_refclk(struct drm_device *dev,
7104 const struct intel_crtc_state *pipe_config)
7106 struct drm_i915_private *dev_priv = to_i915(dev);
7107 u32 dpll = pipe_config->dpll_hw_state.dpll;
7109 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7110 return dev_priv->vbt.lvds_ssc_freq;
7111 else if (HAS_PCH_SPLIT(dev_priv))
7113 else if (!IS_GEN(dev_priv, 2))
7119 /* Returns the clock of the currently programmed mode of the given pipe. */
7120 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7121 struct intel_crtc_state *pipe_config)
7123 struct drm_device *dev = crtc->base.dev;
7124 struct drm_i915_private *dev_priv = to_i915(dev);
7125 enum pipe pipe = crtc->pipe;
7126 u32 dpll = pipe_config->dpll_hw_state.dpll;
7130 int refclk = i9xx_pll_refclk(dev, pipe_config);
7132 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7133 fp = pipe_config->dpll_hw_state.fp0;
7135 fp = pipe_config->dpll_hw_state.fp1;
7137 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7138 if (IS_PINEVIEW(dev_priv)) {
7139 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7140 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7142 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7143 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7146 if (!IS_GEN(dev_priv, 2)) {
7147 if (IS_PINEVIEW(dev_priv))
7148 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7149 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7151 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7152 DPLL_FPA01_P1_POST_DIV_SHIFT);
7154 switch (dpll & DPLL_MODE_MASK) {
7155 case DPLLB_MODE_DAC_SERIAL:
7156 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7159 case DPLLB_MODE_LVDS:
7160 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7164 drm_dbg_kms(&dev_priv->drm,
7165 "Unknown DPLL mode %08x in programmed "
7166 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7170 if (IS_PINEVIEW(dev_priv))
7171 port_clock = pnv_calc_dpll_params(refclk, &clock);
7173 port_clock = i9xx_calc_dpll_params(refclk, &clock);
7175 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
7177 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7180 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7181 DPLL_FPA01_P1_POST_DIV_SHIFT);
7183 if (lvds & LVDS_CLKB_POWER_UP)
7188 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7191 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7192 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7194 if (dpll & PLL_P2_DIVIDE_BY_4)
7200 port_clock = i9xx_calc_dpll_params(refclk, &clock);
7204 * This value includes pixel_multiplier. We will use
7205 * port_clock to compute adjusted_mode.crtc_clock in the
7206 * encoder's get_config() function.
7208 pipe_config->port_clock = port_clock;
7211 int intel_dotclock_calculate(int link_freq,
7212 const struct intel_link_m_n *m_n)
7215 * The calculation for the data clock is:
7216 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7217 * But we want to avoid losing precison if possible, so:
7218 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7220 * and the link clock is simpler:
7221 * link_clock = (m * link_clock) / n
7227 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
7230 static void ilk_pch_clock_get(struct intel_crtc *crtc,
7231 struct intel_crtc_state *pipe_config)
7233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7235 /* read out port_clock from the DPLL */
7236 i9xx_crtc_clock_get(crtc, pipe_config);
7239 * In case there is an active pipe without active ports,
7240 * we may need some idea for the dotclock anyway.
7241 * Calculate one based on the FDI configuration.
7243 pipe_config->hw.adjusted_mode.crtc_clock =
7244 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
7245 &pipe_config->fdi_m_n);
7248 /* Returns the currently programmed mode of the given encoder. */
7249 struct drm_display_mode *
7250 intel_encoder_current_mode(struct intel_encoder *encoder)
7252 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
7253 struct intel_crtc_state *crtc_state;
7254 struct drm_display_mode *mode;
7255 struct intel_crtc *crtc;
7258 if (!encoder->get_hw_state(encoder, &pipe))
7261 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7263 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7267 crtc_state = intel_crtc_state_alloc(crtc);
7273 if (!intel_crtc_get_pipe_config(crtc_state)) {
7279 intel_encoder_get_config(encoder, crtc_state);
7281 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
7289 * intel_wm_need_update - Check whether watermarks need updating
7290 * @cur: current plane state
7291 * @new: new plane state
7293 * Check current plane state versus the new one to determine whether
7294 * watermarks need to be recalculated.
7296 * Returns true or false.
7298 static bool intel_wm_need_update(const struct intel_plane_state *cur,
7299 struct intel_plane_state *new)
7301 /* Update watermarks on tiling or size changes. */
7302 if (new->uapi.visible != cur->uapi.visible)
7305 if (!cur->hw.fb || !new->hw.fb)
7308 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
7309 cur->hw.rotation != new->hw.rotation ||
7310 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
7311 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
7312 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
7313 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
7319 static bool needs_scaling(const struct intel_plane_state *state)
7321 int src_w = drm_rect_width(&state->uapi.src) >> 16;
7322 int src_h = drm_rect_height(&state->uapi.src) >> 16;
7323 int dst_w = drm_rect_width(&state->uapi.dst);
7324 int dst_h = drm_rect_height(&state->uapi.dst);
7326 return (src_w != dst_w || src_h != dst_h);
7329 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
7330 struct intel_crtc_state *crtc_state,
7331 const struct intel_plane_state *old_plane_state,
7332 struct intel_plane_state *plane_state)
7334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7335 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
7336 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7337 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
7338 bool was_crtc_enabled = old_crtc_state->hw.active;
7339 bool is_crtc_enabled = crtc_state->hw.active;
7340 bool turn_off, turn_on, visible, was_visible;
7343 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
7344 ret = skl_update_scaler_plane(crtc_state, plane_state);
7349 was_visible = old_plane_state->uapi.visible;
7350 visible = plane_state->uapi.visible;
7352 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
7353 was_visible = false;
7356 * Visibility is calculated as if the crtc was on, but
7357 * after scaler setup everything depends on it being off
7358 * when the crtc isn't active.
7360 * FIXME this is wrong for watermarks. Watermarks should also
7361 * be computed as if the pipe would be active. Perhaps move
7362 * per-plane wm computation to the .check_plane() hook, and
7363 * only combine the results from all planes in the current place?
7365 if (!is_crtc_enabled) {
7366 intel_plane_set_invisible(crtc_state, plane_state);
7370 if (!was_visible && !visible)
7373 turn_off = was_visible && (!visible || mode_changed);
7374 turn_on = visible && (!was_visible || mode_changed);
7376 drm_dbg_atomic(&dev_priv->drm,
7377 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
7378 crtc->base.base.id, crtc->base.name,
7379 plane->base.base.id, plane->base.name,
7380 was_visible, visible,
7381 turn_off, turn_on, mode_changed);
7384 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
7385 crtc_state->update_wm_pre = true;
7387 /* must disable cxsr around plane enable/disable */
7388 if (plane->id != PLANE_CURSOR)
7389 crtc_state->disable_cxsr = true;
7390 } else if (turn_off) {
7391 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
7392 crtc_state->update_wm_post = true;
7394 /* must disable cxsr around plane enable/disable */
7395 if (plane->id != PLANE_CURSOR)
7396 crtc_state->disable_cxsr = true;
7397 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
7398 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
7399 /* FIXME bollocks */
7400 crtc_state->update_wm_pre = true;
7401 crtc_state->update_wm_post = true;
7405 if (visible || was_visible)
7406 crtc_state->fb_bits |= plane->frontbuffer_bit;
7409 * ILK/SNB DVSACNTR/Sprite Enable
7410 * IVB SPR_CTL/Sprite Enable
7411 * "When in Self Refresh Big FIFO mode, a write to enable the
7412 * plane will be internally buffered and delayed while Big FIFO
7415 * Which means that enabling the sprite can take an extra frame
7416 * when we start in big FIFO mode (LP1+). Thus we need to drop
7417 * down to LP0 and wait for vblank in order to make sure the
7418 * sprite gets enabled on the next vblank after the register write.
7419 * Doing otherwise would risk enabling the sprite one frame after
7420 * we've already signalled flip completion. We can resume LP1+
7421 * once the sprite has been enabled.
7424 * WaCxSRDisabledForSpriteScaling:ivb
7425 * IVB SPR_SCALE/Scaling Enable
7426 * "Low Power watermarks must be disabled for at least one
7427 * frame before enabling sprite scaling, and kept disabled
7428 * until sprite scaling is disabled."
7430 * ILK/SNB DVSASCALE/Scaling Enable
7431 * "When in Self Refresh Big FIFO mode, scaling enable will be
7432 * masked off while Big FIFO mode is exiting."
7434 * Despite the w/a only being listed for IVB we assume that
7435 * the ILK/SNB note has similar ramifications, hence we apply
7436 * the w/a on all three platforms.
7438 * With experimental results seems this is needed also for primary
7439 * plane, not only sprite plane.
7441 if (plane->id != PLANE_CURSOR &&
7442 (IS_GEN_RANGE(dev_priv, 5, 6) ||
7443 IS_IVYBRIDGE(dev_priv)) &&
7444 (turn_on || (!needs_scaling(old_plane_state) &&
7445 needs_scaling(plane_state))))
7446 crtc_state->disable_lp_wm = true;
7451 static bool encoders_cloneable(const struct intel_encoder *a,
7452 const struct intel_encoder *b)
7454 /* masks could be asymmetric, so check both ways */
7455 return a == b || (a->cloneable & (1 << b->type) &&
7456 b->cloneable & (1 << a->type));
7459 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
7460 struct intel_crtc *crtc,
7461 struct intel_encoder *encoder)
7463 struct intel_encoder *source_encoder;
7464 struct drm_connector *connector;
7465 struct drm_connector_state *connector_state;
7468 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
7469 if (connector_state->crtc != &crtc->base)
7473 to_intel_encoder(connector_state->best_encoder);
7474 if (!encoders_cloneable(encoder, source_encoder))
7481 static int icl_add_linked_planes(struct intel_atomic_state *state)
7483 struct intel_plane *plane, *linked;
7484 struct intel_plane_state *plane_state, *linked_plane_state;
7487 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7488 linked = plane_state->planar_linked_plane;
7493 linked_plane_state = intel_atomic_get_plane_state(state, linked);
7494 if (IS_ERR(linked_plane_state))
7495 return PTR_ERR(linked_plane_state);
7497 drm_WARN_ON(state->base.dev,
7498 linked_plane_state->planar_linked_plane != plane);
7499 drm_WARN_ON(state->base.dev,
7500 linked_plane_state->planar_slave == plane_state->planar_slave);
7506 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
7508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7510 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
7511 struct intel_plane *plane, *linked;
7512 struct intel_plane_state *plane_state;
7515 if (INTEL_GEN(dev_priv) < 11)
7519 * Destroy all old plane links and make the slave plane invisible
7520 * in the crtc_state->active_planes mask.
7522 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7523 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
7526 plane_state->planar_linked_plane = NULL;
7527 if (plane_state->planar_slave && !plane_state->uapi.visible) {
7528 crtc_state->enabled_planes &= ~BIT(plane->id);
7529 crtc_state->active_planes &= ~BIT(plane->id);
7530 crtc_state->update_planes |= BIT(plane->id);
7533 plane_state->planar_slave = false;
7536 if (!crtc_state->nv12_planes)
7539 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7540 struct intel_plane_state *linked_state = NULL;
7542 if (plane->pipe != crtc->pipe ||
7543 !(crtc_state->nv12_planes & BIT(plane->id)))
7546 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
7547 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
7550 if (crtc_state->active_planes & BIT(linked->id))
7553 linked_state = intel_atomic_get_plane_state(state, linked);
7554 if (IS_ERR(linked_state))
7555 return PTR_ERR(linked_state);
7560 if (!linked_state) {
7561 drm_dbg_kms(&dev_priv->drm,
7562 "Need %d free Y planes for planar YUV\n",
7563 hweight8(crtc_state->nv12_planes));
7568 plane_state->planar_linked_plane = linked;
7570 linked_state->planar_slave = true;
7571 linked_state->planar_linked_plane = plane;
7572 crtc_state->enabled_planes |= BIT(linked->id);
7573 crtc_state->active_planes |= BIT(linked->id);
7574 crtc_state->update_planes |= BIT(linked->id);
7575 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
7576 linked->base.name, plane->base.name);
7578 /* Copy parameters to slave plane */
7579 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
7580 linked_state->color_ctl = plane_state->color_ctl;
7581 linked_state->view = plane_state->view;
7582 memcpy(linked_state->color_plane, plane_state->color_plane,
7583 sizeof(linked_state->color_plane));
7585 intel_plane_copy_hw_state(linked_state, plane_state);
7586 linked_state->uapi.src = plane_state->uapi.src;
7587 linked_state->uapi.dst = plane_state->uapi.dst;
7589 if (icl_is_hdr_plane(dev_priv, plane->id)) {
7590 if (linked->id == PLANE_SPRITE5)
7591 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
7592 else if (linked->id == PLANE_SPRITE4)
7593 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
7594 else if (linked->id == PLANE_SPRITE3)
7595 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
7596 else if (linked->id == PLANE_SPRITE2)
7597 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
7599 MISSING_CASE(linked->id);
7606 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
7608 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7609 struct intel_atomic_state *state =
7610 to_intel_atomic_state(new_crtc_state->uapi.state);
7611 const struct intel_crtc_state *old_crtc_state =
7612 intel_atomic_get_old_crtc_state(state, crtc);
7614 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
7617 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
7619 const struct drm_display_mode *pipe_mode =
7620 &crtc_state->hw.pipe_mode;
7623 if (!crtc_state->hw.enable)
7626 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7627 pipe_mode->crtc_clock);
7629 return min(linetime_wm, 0x1ff);
7632 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
7633 const struct intel_cdclk_state *cdclk_state)
7635 const struct drm_display_mode *pipe_mode =
7636 &crtc_state->hw.pipe_mode;
7639 if (!crtc_state->hw.enable)
7642 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7643 cdclk_state->logical.cdclk);
7645 return min(linetime_wm, 0x1ff);
7648 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
7650 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7651 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7652 const struct drm_display_mode *pipe_mode =
7653 &crtc_state->hw.pipe_mode;
7656 if (!crtc_state->hw.enable)
7659 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
7660 crtc_state->pixel_rate);
7662 /* Display WA #1135: BXT:ALL GLK:ALL */
7663 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
7666 return min(linetime_wm, 0x1ff);
7669 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
7670 struct intel_crtc *crtc)
7672 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7673 struct intel_crtc_state *crtc_state =
7674 intel_atomic_get_new_crtc_state(state, crtc);
7675 const struct intel_cdclk_state *cdclk_state;
7677 if (INTEL_GEN(dev_priv) >= 9)
7678 crtc_state->linetime = skl_linetime_wm(crtc_state);
7680 crtc_state->linetime = hsw_linetime_wm(crtc_state);
7682 if (!hsw_crtc_supports_ips(crtc))
7685 cdclk_state = intel_atomic_get_cdclk_state(state);
7686 if (IS_ERR(cdclk_state))
7687 return PTR_ERR(cdclk_state);
7689 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
7695 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
7696 struct intel_crtc *crtc)
7698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7699 struct intel_crtc_state *crtc_state =
7700 intel_atomic_get_new_crtc_state(state, crtc);
7701 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
7704 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
7705 mode_changed && !crtc_state->hw.active)
7706 crtc_state->update_wm_post = true;
7708 if (mode_changed && crtc_state->hw.enable &&
7709 dev_priv->display.crtc_compute_clock &&
7710 !crtc_state->bigjoiner_slave &&
7711 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
7712 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
7718 * May need to update pipe gamma enable bits
7719 * when C8 planes are getting enabled/disabled.
7721 if (c8_planes_changed(crtc_state))
7722 crtc_state->uapi.color_mgmt_changed = true;
7724 if (mode_changed || crtc_state->update_pipe ||
7725 crtc_state->uapi.color_mgmt_changed) {
7726 ret = intel_color_check(crtc_state);
7731 if (dev_priv->display.compute_pipe_wm) {
7732 ret = dev_priv->display.compute_pipe_wm(crtc_state);
7734 drm_dbg_kms(&dev_priv->drm,
7735 "Target pipe watermarks are invalid\n");
7740 if (dev_priv->display.compute_intermediate_wm) {
7741 if (drm_WARN_ON(&dev_priv->drm,
7742 !dev_priv->display.compute_pipe_wm))
7746 * Calculate 'intermediate' watermarks that satisfy both the
7747 * old state and the new state. We can program these
7750 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
7752 drm_dbg_kms(&dev_priv->drm,
7753 "No valid intermediate pipe watermarks are possible\n");
7758 if (INTEL_GEN(dev_priv) >= 9) {
7759 if (mode_changed || crtc_state->update_pipe) {
7760 ret = skl_update_scaler_crtc(crtc_state);
7765 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
7770 if (HAS_IPS(dev_priv)) {
7771 ret = hsw_compute_ips_config(crtc_state);
7776 if (INTEL_GEN(dev_priv) >= 9 ||
7777 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7778 ret = hsw_compute_linetime_wm(state, crtc);
7784 if (!mode_changed) {
7785 ret = intel_psr2_sel_fetch_update(state, crtc);
7793 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
7795 struct intel_connector *connector;
7796 struct drm_connector_list_iter conn_iter;
7798 drm_connector_list_iter_begin(dev, &conn_iter);
7799 for_each_intel_connector_iter(connector, &conn_iter) {
7800 struct drm_connector_state *conn_state = connector->base.state;
7801 struct intel_encoder *encoder =
7802 to_intel_encoder(connector->base.encoder);
7804 if (conn_state->crtc)
7805 drm_connector_put(&connector->base);
7808 struct intel_crtc *crtc =
7809 to_intel_crtc(encoder->base.crtc);
7810 const struct intel_crtc_state *crtc_state =
7811 to_intel_crtc_state(crtc->base.state);
7813 conn_state->best_encoder = &encoder->base;
7814 conn_state->crtc = &crtc->base;
7815 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
7817 drm_connector_get(&connector->base);
7819 conn_state->best_encoder = NULL;
7820 conn_state->crtc = NULL;
7823 drm_connector_list_iter_end(&conn_iter);
7827 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
7828 struct intel_crtc_state *pipe_config)
7830 struct drm_connector *connector = conn_state->connector;
7831 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7832 const struct drm_display_info *info = &connector->display_info;
7835 switch (conn_state->max_bpc) {
7849 MISSING_CASE(conn_state->max_bpc);
7853 if (bpp < pipe_config->pipe_bpp) {
7854 drm_dbg_kms(&i915->drm,
7855 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
7856 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
7857 connector->base.id, connector->name,
7859 3 * conn_state->max_requested_bpc,
7860 pipe_config->pipe_bpp);
7862 pipe_config->pipe_bpp = bpp;
7869 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7870 struct intel_crtc_state *pipe_config)
7872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7873 struct drm_atomic_state *state = pipe_config->uapi.state;
7874 struct drm_connector *connector;
7875 struct drm_connector_state *connector_state;
7878 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7879 IS_CHERRYVIEW(dev_priv)))
7881 else if (INTEL_GEN(dev_priv) >= 5)
7886 pipe_config->pipe_bpp = bpp;
7888 /* Clamp display bpp to connector max bpp */
7889 for_each_new_connector_in_state(state, connector, connector_state, i) {
7892 if (connector_state->crtc != &crtc->base)
7895 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
7903 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
7904 const struct drm_display_mode *mode)
7906 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
7907 "type: 0x%x flags: 0x%x\n",
7909 mode->crtc_hdisplay, mode->crtc_hsync_start,
7910 mode->crtc_hsync_end, mode->crtc_htotal,
7911 mode->crtc_vdisplay, mode->crtc_vsync_start,
7912 mode->crtc_vsync_end, mode->crtc_vtotal,
7913 mode->type, mode->flags);
7917 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
7918 const char *id, unsigned int lane_count,
7919 const struct intel_link_m_n *m_n)
7921 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7923 drm_dbg_kms(&i915->drm,
7924 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7926 m_n->gmch_m, m_n->gmch_n,
7927 m_n->link_m, m_n->link_n, m_n->tu);
7931 intel_dump_infoframe(struct drm_i915_private *dev_priv,
7932 const union hdmi_infoframe *frame)
7934 if (!drm_debug_enabled(DRM_UT_KMS))
7937 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
7941 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
7942 const struct drm_dp_vsc_sdp *vsc)
7944 if (!drm_debug_enabled(DRM_UT_KMS))
7947 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
7950 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
7952 static const char * const output_type_str[] = {
7953 OUTPUT_TYPE(UNUSED),
7954 OUTPUT_TYPE(ANALOG),
7964 OUTPUT_TYPE(DP_MST),
7969 static void snprintf_output_types(char *buf, size_t len,
7970 unsigned int output_types)
7977 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
7980 if ((output_types & BIT(i)) == 0)
7983 r = snprintf(str, len, "%s%s",
7984 str != buf ? "," : "", output_type_str[i]);
7990 output_types &= ~BIT(i);
7993 WARN_ON_ONCE(output_types != 0);
7996 static const char * const output_format_str[] = {
7997 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
7998 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
7999 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
8002 static const char *output_formats(enum intel_output_format format)
8004 if (format >= ARRAY_SIZE(output_format_str))
8006 return output_format_str[format];
8009 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
8011 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
8012 struct drm_i915_private *i915 = to_i915(plane->base.dev);
8013 const struct drm_framebuffer *fb = plane_state->hw.fb;
8014 struct drm_format_name_buf format_name;
8017 drm_dbg_kms(&i915->drm,
8018 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
8019 plane->base.base.id, plane->base.name,
8020 yesno(plane_state->uapi.visible));
8024 drm_dbg_kms(&i915->drm,
8025 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s modifier = 0x%llx, visible: %s\n",
8026 plane->base.base.id, plane->base.name,
8027 fb->base.id, fb->width, fb->height,
8028 drm_get_format_name(fb->format->format, &format_name),
8029 fb->modifier, yesno(plane_state->uapi.visible));
8030 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
8031 plane_state->hw.rotation, plane_state->scaler_id);
8032 if (plane_state->uapi.visible)
8033 drm_dbg_kms(&i915->drm,
8034 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
8035 DRM_RECT_FP_ARG(&plane_state->uapi.src),
8036 DRM_RECT_ARG(&plane_state->uapi.dst));
8039 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
8040 struct intel_atomic_state *state,
8041 const char *context)
8043 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
8044 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8045 const struct intel_plane_state *plane_state;
8046 struct intel_plane *plane;
8050 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
8051 crtc->base.base.id, crtc->base.name,
8052 yesno(pipe_config->hw.enable), context);
8054 if (!pipe_config->hw.enable)
8057 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
8058 drm_dbg_kms(&dev_priv->drm,
8059 "active: %s, output_types: %s (0x%x), output format: %s\n",
8060 yesno(pipe_config->hw.active),
8061 buf, pipe_config->output_types,
8062 output_formats(pipe_config->output_format));
8064 drm_dbg_kms(&dev_priv->drm,
8065 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
8066 transcoder_name(pipe_config->cpu_transcoder),
8067 pipe_config->pipe_bpp, pipe_config->dither);
8069 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
8070 transcoder_name(pipe_config->mst_master_transcoder));
8072 drm_dbg_kms(&dev_priv->drm,
8073 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
8074 transcoder_name(pipe_config->master_transcoder),
8075 pipe_config->sync_mode_slaves_mask);
8077 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
8078 pipe_config->bigjoiner_slave ? "slave" :
8079 pipe_config->bigjoiner ? "master" : "no");
8081 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
8082 enableddisabled(pipe_config->splitter.enable),
8083 pipe_config->splitter.link_count,
8084 pipe_config->splitter.pixel_overlap);
8086 if (pipe_config->has_pch_encoder)
8087 intel_dump_m_n_config(pipe_config, "fdi",
8088 pipe_config->fdi_lanes,
8089 &pipe_config->fdi_m_n);
8091 if (intel_crtc_has_dp_encoder(pipe_config)) {
8092 intel_dump_m_n_config(pipe_config, "dp m_n",
8093 pipe_config->lane_count, &pipe_config->dp_m_n);
8094 if (pipe_config->has_drrs)
8095 intel_dump_m_n_config(pipe_config, "dp m2_n2",
8096 pipe_config->lane_count,
8097 &pipe_config->dp_m2_n2);
8100 drm_dbg_kms(&dev_priv->drm,
8101 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
8102 pipe_config->has_audio, pipe_config->has_infoframe,
8103 pipe_config->infoframes.enable);
8105 if (pipe_config->infoframes.enable &
8106 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
8107 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
8108 pipe_config->infoframes.gcp);
8109 if (pipe_config->infoframes.enable &
8110 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
8111 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
8112 if (pipe_config->infoframes.enable &
8113 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
8114 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
8115 if (pipe_config->infoframes.enable &
8116 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
8117 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
8118 if (pipe_config->infoframes.enable &
8119 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
8120 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
8121 if (pipe_config->infoframes.enable &
8122 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
8123 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
8124 if (pipe_config->infoframes.enable &
8125 intel_hdmi_infoframe_enable(DP_SDP_VSC))
8126 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
8128 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
8129 yesno(pipe_config->vrr.enable),
8130 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
8131 pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
8132 intel_vrr_vmin_vblank_start(pipe_config),
8133 intel_vrr_vmax_vblank_start(pipe_config));
8135 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
8136 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
8137 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
8138 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
8139 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
8140 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
8141 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
8142 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
8143 drm_dbg_kms(&dev_priv->drm,
8144 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
8145 pipe_config->port_clock,
8146 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
8147 pipe_config->pixel_rate);
8149 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
8150 pipe_config->linetime, pipe_config->ips_linetime);
8152 if (INTEL_GEN(dev_priv) >= 9)
8153 drm_dbg_kms(&dev_priv->drm,
8154 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
8156 pipe_config->scaler_state.scaler_users,
8157 pipe_config->scaler_state.scaler_id);
8159 if (HAS_GMCH(dev_priv))
8160 drm_dbg_kms(&dev_priv->drm,
8161 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8162 pipe_config->gmch_pfit.control,
8163 pipe_config->gmch_pfit.pgm_ratios,
8164 pipe_config->gmch_pfit.lvds_border_bits);
8166 drm_dbg_kms(&dev_priv->drm,
8167 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
8168 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
8169 enableddisabled(pipe_config->pch_pfit.enabled),
8170 yesno(pipe_config->pch_pfit.force_thru));
8172 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
8173 pipe_config->ips_enabled, pipe_config->double_wide);
8175 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
8177 if (IS_CHERRYVIEW(dev_priv))
8178 drm_dbg_kms(&dev_priv->drm,
8179 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
8180 pipe_config->cgm_mode, pipe_config->gamma_mode,
8181 pipe_config->gamma_enable, pipe_config->csc_enable);
8183 drm_dbg_kms(&dev_priv->drm,
8184 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
8185 pipe_config->csc_mode, pipe_config->gamma_mode,
8186 pipe_config->gamma_enable, pipe_config->csc_enable);
8188 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
8189 pipe_config->hw.degamma_lut ?
8190 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
8191 pipe_config->hw.gamma_lut ?
8192 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
8198 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
8199 if (plane->pipe == crtc->pipe)
8200 intel_dump_plane_state(plane_state);
8204 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
8206 struct drm_device *dev = state->base.dev;
8207 struct drm_connector *connector;
8208 struct drm_connector_list_iter conn_iter;
8209 unsigned int used_ports = 0;
8210 unsigned int used_mst_ports = 0;
8214 * We're going to peek into connector->state,
8215 * hence connection_mutex must be held.
8217 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
8220 * Walk the connector list instead of the encoder
8221 * list to detect the problem on ddi platforms
8222 * where there's just one encoder per digital port.
8224 drm_connector_list_iter_begin(dev, &conn_iter);
8225 drm_for_each_connector_iter(connector, &conn_iter) {
8226 struct drm_connector_state *connector_state;
8227 struct intel_encoder *encoder;
8230 drm_atomic_get_new_connector_state(&state->base,
8232 if (!connector_state)
8233 connector_state = connector->state;
8235 if (!connector_state->best_encoder)
8238 encoder = to_intel_encoder(connector_state->best_encoder);
8240 drm_WARN_ON(dev, !connector_state->crtc);
8242 switch (encoder->type) {
8243 case INTEL_OUTPUT_DDI:
8244 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
8247 case INTEL_OUTPUT_DP:
8248 case INTEL_OUTPUT_HDMI:
8249 case INTEL_OUTPUT_EDP:
8250 /* the same port mustn't appear more than once */
8251 if (used_ports & BIT(encoder->port))
8254 used_ports |= BIT(encoder->port);
8256 case INTEL_OUTPUT_DP_MST:
8264 drm_connector_list_iter_end(&conn_iter);
8266 /* can't mix MST and SST/HDMI on the same port */
8267 if (used_ports & used_mst_ports)
8274 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
8275 struct intel_crtc_state *crtc_state)
8277 const struct intel_crtc_state *from_crtc_state = crtc_state;
8279 if (crtc_state->bigjoiner_slave) {
8280 from_crtc_state = intel_atomic_get_new_crtc_state(state,
8281 crtc_state->bigjoiner_linked_crtc);
8283 /* No need to copy state if the master state is unchanged */
8284 if (!from_crtc_state)
8288 intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
8292 intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
8293 struct intel_crtc_state *crtc_state)
8295 crtc_state->hw.enable = crtc_state->uapi.enable;
8296 crtc_state->hw.active = crtc_state->uapi.active;
8297 crtc_state->hw.mode = crtc_state->uapi.mode;
8298 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
8299 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
8301 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
8304 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
8306 if (crtc_state->bigjoiner_slave)
8309 crtc_state->uapi.enable = crtc_state->hw.enable;
8310 crtc_state->uapi.active = crtc_state->hw.active;
8311 drm_WARN_ON(crtc_state->uapi.crtc->dev,
8312 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
8314 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
8315 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
8317 /* copy color blobs to uapi */
8318 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
8319 crtc_state->hw.degamma_lut);
8320 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
8321 crtc_state->hw.gamma_lut);
8322 drm_property_replace_blob(&crtc_state->uapi.ctm,
8323 crtc_state->hw.ctm);
8327 copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
8328 const struct intel_crtc_state *from_crtc_state)
8330 struct intel_crtc_state *saved_state;
8331 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8333 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
8337 saved_state->uapi = crtc_state->uapi;
8338 saved_state->scaler_state = crtc_state->scaler_state;
8339 saved_state->shared_dpll = crtc_state->shared_dpll;
8340 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
8341 saved_state->crc_enabled = crtc_state->crc_enabled;
8343 intel_crtc_free_hw_state(crtc_state);
8344 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
8347 /* Re-init hw state */
8348 memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
8349 crtc_state->hw.enable = from_crtc_state->hw.enable;
8350 crtc_state->hw.active = from_crtc_state->hw.active;
8351 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
8352 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
8355 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
8356 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
8357 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
8358 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
8359 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
8360 crtc_state->bigjoiner_slave = true;
8361 crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
8362 crtc_state->has_audio = false;
8368 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
8369 struct intel_crtc_state *crtc_state)
8371 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8372 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8373 struct intel_crtc_state *saved_state;
8375 saved_state = intel_crtc_state_alloc(crtc);
8379 /* free the old crtc_state->hw members */
8380 intel_crtc_free_hw_state(crtc_state);
8382 /* FIXME: before the switch to atomic started, a new pipe_config was
8383 * kzalloc'd. Code that depends on any field being zero should be
8384 * fixed, so that the crtc_state can be safely duplicated. For now,
8385 * only fields that are know to not cause problems are preserved. */
8387 saved_state->uapi = crtc_state->uapi;
8388 saved_state->scaler_state = crtc_state->scaler_state;
8389 saved_state->shared_dpll = crtc_state->shared_dpll;
8390 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
8391 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
8392 sizeof(saved_state->icl_port_dplls));
8393 saved_state->crc_enabled = crtc_state->crc_enabled;
8394 if (IS_G4X(dev_priv) ||
8395 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8396 saved_state->wm = crtc_state->wm;
8398 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
8401 intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
8407 intel_modeset_pipe_config(struct intel_atomic_state *state,
8408 struct intel_crtc_state *pipe_config)
8410 struct drm_crtc *crtc = pipe_config->uapi.crtc;
8411 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
8412 struct drm_connector *connector;
8413 struct drm_connector_state *connector_state;
8414 int base_bpp, ret, i;
8417 pipe_config->cpu_transcoder =
8418 (enum transcoder) to_intel_crtc(crtc)->pipe;
8421 * Sanitize sync polarity flags based on requested ones. If neither
8422 * positive or negative polarity is requested, treat this as meaning
8423 * negative polarity.
8425 if (!(pipe_config->hw.adjusted_mode.flags &
8426 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8427 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8429 if (!(pipe_config->hw.adjusted_mode.flags &
8430 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8431 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8433 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8438 base_bpp = pipe_config->pipe_bpp;
8441 * Determine the real pipe dimensions. Note that stereo modes can
8442 * increase the actual pipe size due to the frame doubling and
8443 * insertion of additional space for blanks between the frame. This
8444 * is stored in the crtc timings. We use the requested mode to do this
8445 * computation to clearly distinguish it from the adjusted mode, which
8446 * can be changed by the connectors in the below retry loop.
8448 drm_mode_get_hv_timing(&pipe_config->hw.mode,
8449 &pipe_config->pipe_src_w,
8450 &pipe_config->pipe_src_h);
8452 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8453 struct intel_encoder *encoder =
8454 to_intel_encoder(connector_state->best_encoder);
8456 if (connector_state->crtc != crtc)
8459 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
8460 drm_dbg_kms(&i915->drm,
8461 "rejecting invalid cloning configuration\n");
8466 * Determine output_types before calling the .compute_config()
8467 * hooks so that the hooks can use this information safely.
8469 if (encoder->compute_output_type)
8470 pipe_config->output_types |=
8471 BIT(encoder->compute_output_type(encoder, pipe_config,
8474 pipe_config->output_types |= BIT(encoder->type);
8478 /* Ensure the port clock defaults are reset when retrying. */
8479 pipe_config->port_clock = 0;
8480 pipe_config->pixel_multiplier = 1;
8482 /* Fill in default crtc timings, allow encoders to overwrite them. */
8483 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
8484 CRTC_STEREO_DOUBLE);
8486 /* Pass our mode to the connectors and the CRTC to give them a chance to
8487 * adjust it according to limitations or connector properties, and also
8488 * a chance to reject the mode entirely.
8490 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8491 struct intel_encoder *encoder =
8492 to_intel_encoder(connector_state->best_encoder);
8494 if (connector_state->crtc != crtc)
8497 ret = encoder->compute_config(encoder, pipe_config,
8500 if (ret != -EDEADLK)
8501 drm_dbg_kms(&i915->drm,
8502 "Encoder config failure: %d\n",
8508 /* Set default port clock if not overwritten by the encoder. Needs to be
8509 * done afterwards in case the encoder adjusts the mode. */
8510 if (!pipe_config->port_clock)
8511 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
8512 * pipe_config->pixel_multiplier;
8514 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8515 if (ret == -EDEADLK)
8518 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
8522 if (ret == I915_DISPLAY_CONFIG_RETRY) {
8523 if (drm_WARN(&i915->drm, !retry,
8524 "loop in pipe configuration computation\n"))
8527 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
8532 /* Dithering seems to not pass-through bits correctly when it should, so
8533 * only enable it on 6bpc panels and when its not a compliance
8534 * test requesting 6bpc video pattern.
8536 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
8537 !pipe_config->dither_force_disable;
8538 drm_dbg_kms(&i915->drm,
8539 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
8540 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8546 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
8548 struct intel_atomic_state *state =
8549 to_intel_atomic_state(crtc_state->uapi.state);
8550 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8551 struct drm_connector_state *conn_state;
8552 struct drm_connector *connector;
8555 for_each_new_connector_in_state(&state->base, connector,
8557 struct intel_encoder *encoder =
8558 to_intel_encoder(conn_state->best_encoder);
8561 if (conn_state->crtc != &crtc->base ||
8562 !encoder->compute_config_late)
8565 ret = encoder->compute_config_late(encoder, crtc_state,
8574 bool intel_fuzzy_clock_check(int clock1, int clock2)
8578 if (clock1 == clock2)
8581 if (!clock1 || !clock2)
8584 diff = abs(clock1 - clock2);
8586 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8593 intel_compare_m_n(unsigned int m, unsigned int n,
8594 unsigned int m2, unsigned int n2,
8597 if (m == m2 && n == n2)
8600 if (exact || !m || !n || !m2 || !n2)
8603 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
8610 } else if (n < n2) {
8620 return intel_fuzzy_clock_check(m, m2);
8624 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
8625 const struct intel_link_m_n *m2_n2,
8628 return m_n->tu == m2_n2->tu &&
8629 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
8630 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
8631 intel_compare_m_n(m_n->link_m, m_n->link_n,
8632 m2_n2->link_m, m2_n2->link_n, exact);
8636 intel_compare_infoframe(const union hdmi_infoframe *a,
8637 const union hdmi_infoframe *b)
8639 return memcmp(a, b, sizeof(*a)) == 0;
8643 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
8644 const struct drm_dp_vsc_sdp *b)
8646 return memcmp(a, b, sizeof(*a)) == 0;
8650 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
8651 bool fastset, const char *name,
8652 const union hdmi_infoframe *a,
8653 const union hdmi_infoframe *b)
8656 if (!drm_debug_enabled(DRM_UT_KMS))
8659 drm_dbg_kms(&dev_priv->drm,
8660 "fastset mismatch in %s infoframe\n", name);
8661 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8662 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
8663 drm_dbg_kms(&dev_priv->drm, "found:\n");
8664 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
8666 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
8667 drm_err(&dev_priv->drm, "expected:\n");
8668 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
8669 drm_err(&dev_priv->drm, "found:\n");
8670 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
8675 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
8676 bool fastset, const char *name,
8677 const struct drm_dp_vsc_sdp *a,
8678 const struct drm_dp_vsc_sdp *b)
8681 if (!drm_debug_enabled(DRM_UT_KMS))
8684 drm_dbg_kms(&dev_priv->drm,
8685 "fastset mismatch in %s dp sdp\n", name);
8686 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8687 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
8688 drm_dbg_kms(&dev_priv->drm, "found:\n");
8689 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
8691 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
8692 drm_err(&dev_priv->drm, "expected:\n");
8693 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
8694 drm_err(&dev_priv->drm, "found:\n");
8695 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
8699 static void __printf(4, 5)
8700 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
8701 const char *name, const char *format, ...)
8703 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
8704 struct va_format vaf;
8707 va_start(args, format);
8712 drm_dbg_kms(&i915->drm,
8713 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
8714 crtc->base.base.id, crtc->base.name, name, &vaf);
8716 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
8717 crtc->base.base.id, crtc->base.name, name, &vaf);
8722 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
8724 if (dev_priv->params.fastboot != -1)
8725 return dev_priv->params.fastboot;
8727 /* Enable fastboot by default on Skylake and newer */
8728 if (INTEL_GEN(dev_priv) >= 9)
8731 /* Enable fastboot by default on VLV and CHV */
8732 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8735 /* Disabled by default on all others */
8740 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
8741 const struct intel_crtc_state *pipe_config,
8744 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
8745 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
8748 bool fixup_inherited = fastset &&
8749 current_config->inherited && !pipe_config->inherited;
8751 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
8752 drm_dbg_kms(&dev_priv->drm,
8753 "initial modeset and fastboot not set\n");
8757 #define PIPE_CONF_CHECK_X(name) do { \
8758 if (current_config->name != pipe_config->name) { \
8759 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8760 "(expected 0x%08x, found 0x%08x)", \
8761 current_config->name, \
8762 pipe_config->name); \
8767 #define PIPE_CONF_CHECK_I(name) do { \
8768 if (current_config->name != pipe_config->name) { \
8769 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8770 "(expected %i, found %i)", \
8771 current_config->name, \
8772 pipe_config->name); \
8777 #define PIPE_CONF_CHECK_BOOL(name) do { \
8778 if (current_config->name != pipe_config->name) { \
8779 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8780 "(expected %s, found %s)", \
8781 yesno(current_config->name), \
8782 yesno(pipe_config->name)); \
8788 * Checks state where we only read out the enabling, but not the entire
8789 * state itself (like full infoframes or ELD for audio). These states
8790 * require a full modeset on bootup to fix up.
8792 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
8793 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
8794 PIPE_CONF_CHECK_BOOL(name); \
8796 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8797 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
8798 yesno(current_config->name), \
8799 yesno(pipe_config->name)); \
8804 #define PIPE_CONF_CHECK_P(name) do { \
8805 if (current_config->name != pipe_config->name) { \
8806 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8807 "(expected %p, found %p)", \
8808 current_config->name, \
8809 pipe_config->name); \
8814 #define PIPE_CONF_CHECK_M_N(name) do { \
8815 if (!intel_compare_link_m_n(¤t_config->name, \
8816 &pipe_config->name,\
8818 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8819 "(expected tu %i gmch %i/%i link %i/%i, " \
8820 "found tu %i, gmch %i/%i link %i/%i)", \
8821 current_config->name.tu, \
8822 current_config->name.gmch_m, \
8823 current_config->name.gmch_n, \
8824 current_config->name.link_m, \
8825 current_config->name.link_n, \
8826 pipe_config->name.tu, \
8827 pipe_config->name.gmch_m, \
8828 pipe_config->name.gmch_n, \
8829 pipe_config->name.link_m, \
8830 pipe_config->name.link_n); \
8835 /* This is required for BDW+ where there is only one set of registers for
8836 * switching between high and low RR.
8837 * This macro can be used whenever a comparison has to be made between one
8838 * hw state and multiple sw state variables.
8840 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
8841 if (!intel_compare_link_m_n(¤t_config->name, \
8842 &pipe_config->name, !fastset) && \
8843 !intel_compare_link_m_n(¤t_config->alt_name, \
8844 &pipe_config->name, !fastset)) { \
8845 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8846 "(expected tu %i gmch %i/%i link %i/%i, " \
8847 "or tu %i gmch %i/%i link %i/%i, " \
8848 "found tu %i, gmch %i/%i link %i/%i)", \
8849 current_config->name.tu, \
8850 current_config->name.gmch_m, \
8851 current_config->name.gmch_n, \
8852 current_config->name.link_m, \
8853 current_config->name.link_n, \
8854 current_config->alt_name.tu, \
8855 current_config->alt_name.gmch_m, \
8856 current_config->alt_name.gmch_n, \
8857 current_config->alt_name.link_m, \
8858 current_config->alt_name.link_n, \
8859 pipe_config->name.tu, \
8860 pipe_config->name.gmch_m, \
8861 pipe_config->name.gmch_n, \
8862 pipe_config->name.link_m, \
8863 pipe_config->name.link_n); \
8868 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
8869 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8870 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8871 "(%x) (expected %i, found %i)", \
8873 current_config->name & (mask), \
8874 pipe_config->name & (mask)); \
8879 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
8880 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8881 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8882 "(expected %i, found %i)", \
8883 current_config->name, \
8884 pipe_config->name); \
8889 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
8890 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
8891 &pipe_config->infoframes.name)) { \
8892 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
8893 ¤t_config->infoframes.name, \
8894 &pipe_config->infoframes.name); \
8899 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
8900 if (!current_config->has_psr && !pipe_config->has_psr && \
8901 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
8902 &pipe_config->infoframes.name)) { \
8903 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
8904 ¤t_config->infoframes.name, \
8905 &pipe_config->infoframes.name); \
8910 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
8911 if (current_config->name1 != pipe_config->name1) { \
8912 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
8913 "(expected %i, found %i, won't compare lut values)", \
8914 current_config->name1, \
8915 pipe_config->name1); \
8918 if (!intel_color_lut_equal(current_config->name2, \
8919 pipe_config->name2, pipe_config->name1, \
8921 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
8922 "hw_state doesn't match sw_state"); \
8928 #define PIPE_CONF_QUIRK(quirk) \
8929 ((current_config->quirks | pipe_config->quirks) & (quirk))
8931 PIPE_CONF_CHECK_I(cpu_transcoder);
8933 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
8934 PIPE_CONF_CHECK_I(fdi_lanes);
8935 PIPE_CONF_CHECK_M_N(fdi_m_n);
8937 PIPE_CONF_CHECK_I(lane_count);
8938 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
8940 if (INTEL_GEN(dev_priv) < 8) {
8941 PIPE_CONF_CHECK_M_N(dp_m_n);
8943 if (current_config->has_drrs)
8944 PIPE_CONF_CHECK_M_N(dp_m2_n2);
8946 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
8948 PIPE_CONF_CHECK_X(output_types);
8950 /* FIXME do the readout properly and get rid of this quirk */
8951 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8952 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
8953 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
8954 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
8955 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
8956 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
8957 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
8959 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
8960 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
8961 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
8962 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
8963 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
8964 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
8966 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
8967 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
8968 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
8969 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
8970 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
8971 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
8973 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
8974 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
8975 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
8976 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
8977 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
8978 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
8980 PIPE_CONF_CHECK_I(pixel_multiplier);
8982 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8983 DRM_MODE_FLAG_INTERLACE);
8985 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8986 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8987 DRM_MODE_FLAG_PHSYNC);
8988 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8989 DRM_MODE_FLAG_NHSYNC);
8990 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8991 DRM_MODE_FLAG_PVSYNC);
8992 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8993 DRM_MODE_FLAG_NVSYNC);
8997 PIPE_CONF_CHECK_I(output_format);
8998 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
8999 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
9000 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
9001 PIPE_CONF_CHECK_BOOL(limited_color_range);
9003 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
9004 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
9005 PIPE_CONF_CHECK_BOOL(has_infoframe);
9006 /* FIXME do the readout properly and get rid of this quirk */
9007 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
9008 PIPE_CONF_CHECK_BOOL(fec_enable);
9010 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
9012 PIPE_CONF_CHECK_X(gmch_pfit.control);
9013 /* pfit ratios are autocomputed by the hw on gen4+ */
9014 if (INTEL_GEN(dev_priv) < 4)
9015 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
9016 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9019 * Changing the EDP transcoder input mux
9020 * (A_ONOFF vs. A_ON) requires a full modeset.
9022 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
9025 PIPE_CONF_CHECK_I(pipe_src_w);
9026 PIPE_CONF_CHECK_I(pipe_src_h);
9028 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
9029 if (current_config->pch_pfit.enabled) {
9030 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
9031 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
9032 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
9033 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
9036 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
9037 /* FIXME do the readout properly and get rid of this quirk */
9038 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
9039 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
9041 PIPE_CONF_CHECK_X(gamma_mode);
9042 if (IS_CHERRYVIEW(dev_priv))
9043 PIPE_CONF_CHECK_X(cgm_mode);
9045 PIPE_CONF_CHECK_X(csc_mode);
9046 PIPE_CONF_CHECK_BOOL(gamma_enable);
9047 PIPE_CONF_CHECK_BOOL(csc_enable);
9049 PIPE_CONF_CHECK_I(linetime);
9050 PIPE_CONF_CHECK_I(ips_linetime);
9052 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
9054 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
9057 PIPE_CONF_CHECK_BOOL(double_wide);
9059 PIPE_CONF_CHECK_P(shared_dpll);
9061 /* FIXME do the readout properly and get rid of this quirk */
9062 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
9063 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9064 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9065 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9066 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9067 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
9068 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
9069 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
9070 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
9071 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
9072 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
9073 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
9074 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
9075 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
9076 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
9077 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
9078 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
9079 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
9080 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
9081 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
9082 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
9083 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
9084 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
9085 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
9086 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
9087 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
9088 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
9089 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
9090 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
9091 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
9092 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
9093 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
9095 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
9096 PIPE_CONF_CHECK_X(dsi_pll.div);
9098 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
9099 PIPE_CONF_CHECK_I(pipe_bpp);
9101 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
9102 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
9103 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9105 PIPE_CONF_CHECK_I(min_voltage_level);
9108 PIPE_CONF_CHECK_X(infoframes.enable);
9109 PIPE_CONF_CHECK_X(infoframes.gcp);
9110 PIPE_CONF_CHECK_INFOFRAME(avi);
9111 PIPE_CONF_CHECK_INFOFRAME(spd);
9112 PIPE_CONF_CHECK_INFOFRAME(hdmi);
9113 PIPE_CONF_CHECK_INFOFRAME(drm);
9114 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
9116 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
9117 PIPE_CONF_CHECK_I(master_transcoder);
9118 PIPE_CONF_CHECK_BOOL(bigjoiner);
9119 PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
9120 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
9122 PIPE_CONF_CHECK_I(dsc.compression_enable);
9123 PIPE_CONF_CHECK_I(dsc.dsc_split);
9124 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
9126 PIPE_CONF_CHECK_BOOL(splitter.enable);
9127 PIPE_CONF_CHECK_I(splitter.link_count);
9128 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
9130 PIPE_CONF_CHECK_I(mst_master_transcoder);
9132 PIPE_CONF_CHECK_BOOL(vrr.enable);
9133 PIPE_CONF_CHECK_I(vrr.vmin);
9134 PIPE_CONF_CHECK_I(vrr.vmax);
9135 PIPE_CONF_CHECK_I(vrr.flipline);
9136 PIPE_CONF_CHECK_I(vrr.pipeline_full);
9138 #undef PIPE_CONF_CHECK_X
9139 #undef PIPE_CONF_CHECK_I
9140 #undef PIPE_CONF_CHECK_BOOL
9141 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
9142 #undef PIPE_CONF_CHECK_P
9143 #undef PIPE_CONF_CHECK_FLAGS
9144 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9145 #undef PIPE_CONF_CHECK_COLOR_LUT
9146 #undef PIPE_CONF_QUIRK
9151 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
9152 const struct intel_crtc_state *pipe_config)
9154 if (pipe_config->has_pch_encoder) {
9155 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9156 &pipe_config->fdi_m_n);
9157 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
9160 * FDI already provided one idea for the dotclock.
9161 * Yell if the encoder disagrees.
9163 drm_WARN(&dev_priv->drm,
9164 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
9165 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9166 fdi_dotclock, dotclock);
9170 static void verify_wm_state(struct intel_crtc *crtc,
9171 struct intel_crtc_state *new_crtc_state)
9173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9174 struct skl_hw_state {
9175 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
9176 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
9177 struct skl_pipe_wm wm;
9179 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
9180 int level, max_level = ilk_wm_max_level(dev_priv);
9181 struct intel_plane *plane;
9182 u8 hw_enabled_slices;
9184 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
9187 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
9191 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
9193 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
9195 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
9197 if (INTEL_GEN(dev_priv) >= 11 &&
9198 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
9199 drm_err(&dev_priv->drm,
9200 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
9201 dev_priv->dbuf.enabled_slices,
9204 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
9205 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
9206 const struct skl_wm_level *hw_wm_level, *sw_wm_level;
9209 for (level = 0; level <= max_level; level++) {
9210 hw_wm_level = &hw->wm.planes[plane->id].wm[level];
9211 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
9213 if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
9216 drm_err(&dev_priv->drm,
9217 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
9218 plane->base.base.id, plane->base.name, level,
9219 sw_wm_level->plane_en,
9220 sw_wm_level->plane_res_b,
9221 sw_wm_level->plane_res_l,
9222 hw_wm_level->plane_en,
9223 hw_wm_level->plane_res_b,
9224 hw_wm_level->plane_res_l);
9227 hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
9228 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
9230 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
9231 drm_err(&dev_priv->drm,
9232 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
9233 plane->base.base.id, plane->base.name,
9234 sw_wm_level->plane_en,
9235 sw_wm_level->plane_res_b,
9236 sw_wm_level->plane_res_l,
9237 hw_wm_level->plane_en,
9238 hw_wm_level->plane_res_b,
9239 hw_wm_level->plane_res_l);
9243 hw_ddb_entry = &hw->ddb_y[plane->id];
9244 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
9246 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
9247 drm_err(&dev_priv->drm,
9248 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
9249 plane->base.base.id, plane->base.name,
9250 sw_ddb_entry->start, sw_ddb_entry->end,
9251 hw_ddb_entry->start, hw_ddb_entry->end);
9259 verify_connector_state(struct intel_atomic_state *state,
9260 struct intel_crtc *crtc)
9262 struct drm_connector *connector;
9263 struct drm_connector_state *new_conn_state;
9266 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
9267 struct drm_encoder *encoder = connector->encoder;
9268 struct intel_crtc_state *crtc_state = NULL;
9270 if (new_conn_state->crtc != &crtc->base)
9274 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
9276 intel_connector_verify_state(crtc_state, new_conn_state);
9278 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
9279 "connector's atomic encoder doesn't match legacy encoder\n");
9284 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
9286 struct intel_encoder *encoder;
9287 struct drm_connector *connector;
9288 struct drm_connector_state *old_conn_state, *new_conn_state;
9291 for_each_intel_encoder(&dev_priv->drm, encoder) {
9292 bool enabled = false, found = false;
9295 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
9296 encoder->base.base.id,
9297 encoder->base.name);
9299 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
9300 new_conn_state, i) {
9301 if (old_conn_state->best_encoder == &encoder->base)
9304 if (new_conn_state->best_encoder != &encoder->base)
9306 found = enabled = true;
9308 I915_STATE_WARN(new_conn_state->crtc !=
9310 "connector's crtc doesn't match encoder crtc\n");
9316 I915_STATE_WARN(!!encoder->base.crtc != enabled,
9317 "encoder's enabled state mismatch "
9318 "(expected %i, found %i)\n",
9319 !!encoder->base.crtc, enabled);
9321 if (!encoder->base.crtc) {
9324 active = encoder->get_hw_state(encoder, &pipe);
9325 I915_STATE_WARN(active,
9326 "encoder detached but still enabled on pipe %c.\n",
9333 verify_crtc_state(struct intel_crtc *crtc,
9334 struct intel_crtc_state *old_crtc_state,
9335 struct intel_crtc_state *new_crtc_state)
9337 struct drm_device *dev = crtc->base.dev;
9338 struct drm_i915_private *dev_priv = to_i915(dev);
9339 struct intel_encoder *encoder;
9340 struct intel_crtc_state *pipe_config = old_crtc_state;
9341 struct drm_atomic_state *state = old_crtc_state->uapi.state;
9342 struct intel_crtc *master = crtc;
9344 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
9345 intel_crtc_free_hw_state(old_crtc_state);
9346 intel_crtc_state_reset(old_crtc_state, crtc);
9347 old_crtc_state->uapi.state = state;
9349 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
9352 pipe_config->hw.enable = new_crtc_state->hw.enable;
9354 intel_crtc_get_pipe_config(pipe_config);
9356 /* we keep both pipes enabled on 830 */
9357 if (IS_I830(dev_priv) && pipe_config->hw.active)
9358 pipe_config->hw.active = new_crtc_state->hw.active;
9360 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
9361 "crtc active state doesn't match with hw state "
9362 "(expected %i, found %i)\n",
9363 new_crtc_state->hw.active, pipe_config->hw.active);
9365 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
9366 "transitional active state does not match atomic hw state "
9367 "(expected %i, found %i)\n",
9368 new_crtc_state->hw.active, crtc->active);
9370 if (new_crtc_state->bigjoiner_slave)
9371 master = new_crtc_state->bigjoiner_linked_crtc;
9373 for_each_encoder_on_crtc(dev, &master->base, encoder) {
9377 active = encoder->get_hw_state(encoder, &pipe);
9378 I915_STATE_WARN(active != new_crtc_state->hw.active,
9379 "[ENCODER:%i] active %i with crtc active %i\n",
9380 encoder->base.base.id, active,
9381 new_crtc_state->hw.active);
9383 I915_STATE_WARN(active && master->pipe != pipe,
9384 "Encoder connected to wrong pipe %c\n",
9388 intel_encoder_get_config(encoder, pipe_config);
9391 if (!new_crtc_state->hw.active)
9394 intel_pipe_config_sanity_check(dev_priv, pipe_config);
9396 if (!intel_pipe_config_compare(new_crtc_state,
9397 pipe_config, false)) {
9398 I915_STATE_WARN(1, "pipe state doesn't match!\n");
9399 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
9400 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
9405 intel_verify_planes(struct intel_atomic_state *state)
9407 struct intel_plane *plane;
9408 const struct intel_plane_state *plane_state;
9411 for_each_new_intel_plane_in_state(state, plane,
9413 assert_plane(plane, plane_state->planar_slave ||
9414 plane_state->uapi.visible);
9418 verify_single_dpll_state(struct drm_i915_private *dev_priv,
9419 struct intel_shared_dpll *pll,
9420 struct intel_crtc *crtc,
9421 struct intel_crtc_state *new_crtc_state)
9423 struct intel_dpll_hw_state dpll_hw_state;
9427 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9429 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
9431 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
9433 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
9434 I915_STATE_WARN(!pll->on && pll->active_mask,
9435 "pll in active use but not on in sw tracking\n");
9436 I915_STATE_WARN(pll->on && !pll->active_mask,
9437 "pll is on but not used by any active pipe\n");
9438 I915_STATE_WARN(pll->on != active,
9439 "pll on state mismatch (expected %i, found %i)\n",
9444 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
9445 "more active pll users than references: 0x%x vs 0x%x\n",
9446 pll->active_mask, pll->state.pipe_mask);
9451 pipe_mask = BIT(crtc->pipe);
9453 if (new_crtc_state->hw.active)
9454 I915_STATE_WARN(!(pll->active_mask & pipe_mask),
9455 "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
9456 pipe_name(crtc->pipe), pll->active_mask);
9458 I915_STATE_WARN(pll->active_mask & pipe_mask,
9459 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
9460 pipe_name(crtc->pipe), pll->active_mask);
9462 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
9463 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
9464 pipe_mask, pll->state.pipe_mask);
9466 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
9468 sizeof(dpll_hw_state)),
9469 "pll hw state mismatch\n");
9473 verify_shared_dpll_state(struct intel_crtc *crtc,
9474 struct intel_crtc_state *old_crtc_state,
9475 struct intel_crtc_state *new_crtc_state)
9477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9479 if (new_crtc_state->shared_dpll)
9480 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
9482 if (old_crtc_state->shared_dpll &&
9483 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
9484 u8 pipe_mask = BIT(crtc->pipe);
9485 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
9487 I915_STATE_WARN(pll->active_mask & pipe_mask,
9488 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
9489 pipe_name(crtc->pipe), pll->active_mask);
9490 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
9491 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
9492 pipe_name(crtc->pipe), pll->state.pipe_mask);
9497 intel_modeset_verify_crtc(struct intel_crtc *crtc,
9498 struct intel_atomic_state *state,
9499 struct intel_crtc_state *old_crtc_state,
9500 struct intel_crtc_state *new_crtc_state)
9502 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
9505 verify_wm_state(crtc, new_crtc_state);
9506 verify_connector_state(state, crtc);
9507 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
9508 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
9512 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
9516 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
9517 verify_single_dpll_state(dev_priv,
9518 &dev_priv->dpll.shared_dplls[i],
9523 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
9524 struct intel_atomic_state *state)
9526 verify_encoder_state(dev_priv, state);
9527 verify_connector_state(state, NULL);
9528 verify_disabled_dpll_state(dev_priv);
9532 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
9534 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9535 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9536 struct drm_display_mode adjusted_mode =
9537 crtc_state->hw.adjusted_mode;
9539 if (crtc_state->vrr.enable) {
9540 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
9541 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
9542 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
9543 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
9546 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
9548 crtc->mode_flags = crtc_state->mode_flags;
9551 * The scanline counter increments at the leading edge of hsync.
9553 * On most platforms it starts counting from vtotal-1 on the
9554 * first active line. That means the scanline counter value is
9555 * always one less than what we would expect. Ie. just after
9556 * start of vblank, which also occurs at start of hsync (on the
9557 * last active line), the scanline counter will read vblank_start-1.
9559 * On gen2 the scanline counter starts counting from 1 instead
9560 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
9561 * to keep the value positive), instead of adding one.
9563 * On HSW+ the behaviour of the scanline counter depends on the output
9564 * type. For DP ports it behaves like most other platforms, but on HDMI
9565 * there's an extra 1 line difference. So we need to add two instead of
9568 * On VLV/CHV DSI the scanline counter would appear to increment
9569 * approx. 1/3 of a scanline before start of vblank. Unfortunately
9570 * that means we can't tell whether we're in vblank or not while
9571 * we're on that particular line. We must still set scanline_offset
9572 * to 1 so that the vblank timestamps come out correct when we query
9573 * the scanline counter from within the vblank interrupt handler.
9574 * However if queried just before the start of vblank we'll get an
9575 * answer that's slightly in the future.
9577 if (IS_GEN(dev_priv, 2)) {
9580 vtotal = adjusted_mode.crtc_vtotal;
9581 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9584 crtc->scanline_offset = vtotal - 1;
9585 } else if (HAS_DDI(dev_priv) &&
9586 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
9587 crtc->scanline_offset = 2;
9589 crtc->scanline_offset = 1;
9593 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
9595 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9596 struct intel_crtc_state *new_crtc_state;
9597 struct intel_crtc *crtc;
9600 if (!dev_priv->display.crtc_compute_clock)
9603 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9604 if (!intel_crtc_needs_modeset(new_crtc_state))
9607 intel_release_shared_dplls(state, crtc);
9612 * This implements the workaround described in the "notes" section of the mode
9613 * set sequence documentation. When going from no pipes or single pipe to
9614 * multiple pipes, and planes are enabled after the pipe, we need to wait at
9615 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
9617 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
9619 struct intel_crtc_state *crtc_state;
9620 struct intel_crtc *crtc;
9621 struct intel_crtc_state *first_crtc_state = NULL;
9622 struct intel_crtc_state *other_crtc_state = NULL;
9623 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
9626 /* look at all crtc's that are going to be enabled in during modeset */
9627 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9628 if (!crtc_state->hw.active ||
9629 !intel_crtc_needs_modeset(crtc_state))
9632 if (first_crtc_state) {
9633 other_crtc_state = crtc_state;
9636 first_crtc_state = crtc_state;
9637 first_pipe = crtc->pipe;
9641 /* No workaround needed? */
9642 if (!first_crtc_state)
9645 /* w/a possibly needed, check how many crtc's are already enabled. */
9646 for_each_intel_crtc(state->base.dev, crtc) {
9647 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9648 if (IS_ERR(crtc_state))
9649 return PTR_ERR(crtc_state);
9651 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
9653 if (!crtc_state->hw.active ||
9654 intel_crtc_needs_modeset(crtc_state))
9657 /* 2 or more enabled crtcs means no need for w/a */
9658 if (enabled_pipe != INVALID_PIPE)
9661 enabled_pipe = crtc->pipe;
9664 if (enabled_pipe != INVALID_PIPE)
9665 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
9666 else if (other_crtc_state)
9667 other_crtc_state->hsw_workaround_pipe = first_pipe;
9672 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
9675 const struct intel_crtc_state *crtc_state;
9676 struct intel_crtc *crtc;
9679 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9680 if (crtc_state->hw.active)
9681 active_pipes |= BIT(crtc->pipe);
9683 active_pipes &= ~BIT(crtc->pipe);
9686 return active_pipes;
9689 static int intel_modeset_checks(struct intel_atomic_state *state)
9691 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9693 state->modeset = true;
9695 if (IS_HASWELL(dev_priv))
9696 return hsw_mode_set_planes_workaround(state);
9702 * Handle calculation of various watermark data at the end of the atomic check
9703 * phase. The code here should be run after the per-crtc and per-plane 'check'
9704 * handlers to ensure that all derived state has been updated.
9706 static int calc_watermark_data(struct intel_atomic_state *state)
9708 struct drm_device *dev = state->base.dev;
9709 struct drm_i915_private *dev_priv = to_i915(dev);
9711 /* Is there platform-specific watermark information to calculate? */
9712 if (dev_priv->display.compute_global_watermarks)
9713 return dev_priv->display.compute_global_watermarks(state);
9718 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
9719 struct intel_crtc_state *new_crtc_state)
9721 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
9724 new_crtc_state->uapi.mode_changed = false;
9725 new_crtc_state->update_pipe = true;
9728 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
9729 struct intel_crtc_state *new_crtc_state)
9732 * If we're not doing the full modeset we want to
9733 * keep the current M/N values as they may be
9734 * sufficiently different to the computed values
9735 * to cause problems.
9737 * FIXME: should really copy more fuzzy state here
9739 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
9740 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
9741 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
9742 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
9745 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
9746 struct intel_crtc *crtc,
9749 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9750 struct intel_plane *plane;
9752 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
9753 struct intel_plane_state *plane_state;
9755 if ((plane_ids_mask & BIT(plane->id)) == 0)
9758 plane_state = intel_atomic_get_plane_state(state, plane);
9759 if (IS_ERR(plane_state))
9760 return PTR_ERR(plane_state);
9766 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
9767 struct intel_crtc *crtc)
9769 const struct intel_crtc_state *old_crtc_state =
9770 intel_atomic_get_old_crtc_state(state, crtc);
9771 const struct intel_crtc_state *new_crtc_state =
9772 intel_atomic_get_new_crtc_state(state, crtc);
9774 return intel_crtc_add_planes_to_state(state, crtc,
9775 old_crtc_state->enabled_planes |
9776 new_crtc_state->enabled_planes);
9779 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
9781 /* See {hsw,vlv,ivb}_plane_ratio() */
9782 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
9783 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9784 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
9787 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
9788 struct intel_crtc *crtc,
9789 struct intel_crtc *other)
9791 const struct intel_plane_state *plane_state;
9792 struct intel_plane *plane;
9796 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9797 if (plane->pipe == crtc->pipe)
9798 plane_ids |= BIT(plane->id);
9801 return intel_crtc_add_planes_to_state(state, other, plane_ids);
9804 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
9806 const struct intel_crtc_state *crtc_state;
9807 struct intel_crtc *crtc;
9810 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9813 if (!crtc_state->bigjoiner)
9816 ret = intel_crtc_add_bigjoiner_planes(state, crtc,
9817 crtc_state->bigjoiner_linked_crtc);
9825 static int intel_atomic_check_planes(struct intel_atomic_state *state)
9827 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9828 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9829 struct intel_plane_state *plane_state;
9830 struct intel_plane *plane;
9831 struct intel_crtc *crtc;
9834 ret = icl_add_linked_planes(state);
9838 ret = intel_bigjoiner_add_affected_planes(state);
9842 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9843 ret = intel_plane_atomic_check(state, plane);
9845 drm_dbg_atomic(&dev_priv->drm,
9846 "[PLANE:%d:%s] atomic driver check failed\n",
9847 plane->base.base.id, plane->base.name);
9852 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9853 new_crtc_state, i) {
9854 u8 old_active_planes, new_active_planes;
9856 ret = icl_check_nv12_planes(new_crtc_state);
9861 * On some platforms the number of active planes affects
9862 * the planes' minimum cdclk calculation. Add such planes
9863 * to the state before we compute the minimum cdclk.
9865 if (!active_planes_affects_min_cdclk(dev_priv))
9868 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9869 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9872 * Not only the number of planes, but if the plane configuration had
9873 * changed might already mean we need to recompute min CDCLK,
9874 * because different planes might consume different amount of Dbuf bandwidth
9875 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
9877 if (old_active_planes == new_active_planes)
9880 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
9888 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
9889 bool *need_cdclk_calc)
9891 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9892 const struct intel_cdclk_state *old_cdclk_state;
9893 const struct intel_cdclk_state *new_cdclk_state;
9894 struct intel_plane_state *plane_state;
9895 struct intel_bw_state *new_bw_state;
9896 struct intel_plane *plane;
9902 * active_planes bitmask has been updated, and potentially
9903 * affected planes are part of the state. We can now
9904 * compute the minimum cdclk for each plane.
9906 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9907 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
9912 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
9913 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
9915 if (new_cdclk_state &&
9916 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
9917 *need_cdclk_calc = true;
9919 ret = dev_priv->display.bw_calc_min_cdclk(state);
9923 new_bw_state = intel_atomic_get_new_bw_state(state);
9925 if (!new_cdclk_state || !new_bw_state)
9928 for_each_pipe(dev_priv, pipe) {
9929 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
9932 * Currently do this change only if we need to increase
9934 if (new_bw_state->min_cdclk > min_cdclk)
9935 *need_cdclk_calc = true;
9941 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
9943 struct intel_crtc_state *crtc_state;
9944 struct intel_crtc *crtc;
9947 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9948 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
9951 ret = intel_crtc_atomic_check(state, crtc);
9953 drm_dbg_atomic(&i915->drm,
9954 "[CRTC:%d:%s] atomic driver check failed\n",
9955 crtc->base.base.id, crtc->base.name);
9963 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
9966 const struct intel_crtc_state *new_crtc_state;
9967 struct intel_crtc *crtc;
9970 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9971 if (new_crtc_state->hw.enable &&
9972 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
9973 intel_crtc_needs_modeset(new_crtc_state))
9980 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
9981 struct intel_crtc *crtc,
9982 struct intel_crtc_state *old_crtc_state,
9983 struct intel_crtc_state *new_crtc_state)
9985 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9986 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
9987 struct intel_crtc *slave, *master;
9989 /* slave being enabled, is master is still claiming this crtc? */
9990 if (old_crtc_state->bigjoiner_slave) {
9992 master = old_crtc_state->bigjoiner_linked_crtc;
9993 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
9994 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state))
9998 if (!new_crtc_state->bigjoiner)
10001 if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
10002 DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
10003 "CRTC + 1 to be used, doesn't exist\n",
10004 crtc->base.base.id, crtc->base.name);
10008 slave = new_crtc_state->bigjoiner_linked_crtc =
10009 intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
10010 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
10012 if (IS_ERR(slave_crtc_state))
10013 return PTR_ERR(slave_crtc_state);
10015 /* master being enabled, slave was already configured? */
10016 if (slave_crtc_state->uapi.enable)
10019 DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
10020 slave->base.base.id, slave->base.name);
10022 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
10025 DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
10026 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
10027 slave->base.base.id, slave->base.name,
10028 master->base.base.id, master->base.name);
10032 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
10033 struct intel_crtc_state *master_crtc_state)
10035 struct intel_crtc_state *slave_crtc_state =
10036 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);
10038 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
10039 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
10040 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
10041 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
10045 * DOC: asynchronous flip implementation
10047 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
10048 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
10049 * Correspondingly, support is currently added for primary plane only.
10051 * Async flip can only change the plane surface address, so anything else
10052 * changing is rejected from the intel_atomic_check_async() function.
10053 * Once this check is cleared, flip done interrupt is enabled using
10054 * the intel_crtc_enable_flip_done() function.
10056 * As soon as the surface address register is written, flip done interrupt is
10057 * generated and the requested events are sent to the usersapce in the interrupt
10058 * handler itself. The timestamp and sequence sent during the flip done event
10059 * correspond to the last vblank and have no relation to the actual time when
10060 * the flip done event was sent.
10062 static int intel_atomic_check_async(struct intel_atomic_state *state)
10064 struct drm_i915_private *i915 = to_i915(state->base.dev);
10065 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10066 const struct intel_plane_state *new_plane_state, *old_plane_state;
10067 struct intel_crtc *crtc;
10068 struct intel_plane *plane;
10071 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10072 new_crtc_state, i) {
10073 if (intel_crtc_needs_modeset(new_crtc_state)) {
10074 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
10078 if (!new_crtc_state->hw.active) {
10079 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
10082 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
10083 drm_dbg_kms(&i915->drm,
10084 "Active planes cannot be changed during async flip\n");
10089 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
10090 new_plane_state, i) {
10092 * TODO: Async flip is only supported through the page flip IOCTL
10093 * as of now. So support currently added for primary plane only.
10094 * Support for other planes on platforms on which supports
10095 * this(vlv/chv and icl+) should be added when async flip is
10096 * enabled in the atomic IOCTL path.
10098 if (!plane->async_flip)
10102 * FIXME: This check is kept generic for all platforms.
10103 * Need to verify this for all gen9 and gen10 platforms to enable
10104 * this selectively if required.
10106 switch (new_plane_state->hw.fb->modifier) {
10107 case I915_FORMAT_MOD_X_TILED:
10108 case I915_FORMAT_MOD_Y_TILED:
10109 case I915_FORMAT_MOD_Yf_TILED:
10112 drm_dbg_kms(&i915->drm,
10113 "Linear memory/CCS does not support async flips\n");
10117 if (old_plane_state->color_plane[0].stride !=
10118 new_plane_state->color_plane[0].stride) {
10119 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
10123 if (old_plane_state->hw.fb->modifier !=
10124 new_plane_state->hw.fb->modifier) {
10125 drm_dbg_kms(&i915->drm,
10126 "Framebuffer modifiers cannot be changed in async flip\n");
10130 if (old_plane_state->hw.fb->format !=
10131 new_plane_state->hw.fb->format) {
10132 drm_dbg_kms(&i915->drm,
10133 "Framebuffer format cannot be changed in async flip\n");
10137 if (old_plane_state->hw.rotation !=
10138 new_plane_state->hw.rotation) {
10139 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
10143 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
10144 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
10145 drm_dbg_kms(&i915->drm,
10146 "Plane size/co-ordinates cannot be changed in async flip\n");
10150 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
10151 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
10155 if (old_plane_state->hw.pixel_blend_mode !=
10156 new_plane_state->hw.pixel_blend_mode) {
10157 drm_dbg_kms(&i915->drm,
10158 "Pixel blend mode cannot be changed in async flip\n");
10162 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
10163 drm_dbg_kms(&i915->drm,
10164 "Color encoding cannot be changed in async flip\n");
10168 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
10169 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
10177 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
10179 struct intel_crtc_state *crtc_state;
10180 struct intel_crtc *crtc;
10183 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10184 struct intel_crtc_state *linked_crtc_state;
10185 struct intel_crtc *linked_crtc;
10188 if (!crtc_state->bigjoiner)
10191 linked_crtc = crtc_state->bigjoiner_linked_crtc;
10192 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);
10193 if (IS_ERR(linked_crtc_state))
10194 return PTR_ERR(linked_crtc_state);
10196 if (!intel_crtc_needs_modeset(crtc_state))
10199 linked_crtc_state->uapi.mode_changed = true;
10201 ret = drm_atomic_add_affected_connectors(&state->base,
10202 &linked_crtc->base);
10206 ret = intel_atomic_add_affected_planes(state, linked_crtc);
10211 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10212 /* Kill old bigjoiner link, we may re-establish afterwards */
10213 if (intel_crtc_needs_modeset(crtc_state) &&
10214 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
10215 kill_bigjoiner_slave(state, crtc_state);
10222 * intel_atomic_check - validate state object
10224 * @_state: state to validate
10226 static int intel_atomic_check(struct drm_device *dev,
10227 struct drm_atomic_state *_state)
10229 struct drm_i915_private *dev_priv = to_i915(dev);
10230 struct intel_atomic_state *state = to_intel_atomic_state(_state);
10231 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10232 struct intel_crtc *crtc;
10234 bool any_ms = false;
10236 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10237 new_crtc_state, i) {
10238 if (new_crtc_state->inherited != old_crtc_state->inherited)
10239 new_crtc_state->uapi.mode_changed = true;
10242 intel_vrr_check_modeset(state);
10244 ret = drm_atomic_helper_check_modeset(dev, &state->base);
10248 ret = intel_bigjoiner_add_affected_crtcs(state);
10252 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10253 new_crtc_state, i) {
10254 if (!intel_crtc_needs_modeset(new_crtc_state)) {
10256 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
10261 if (!new_crtc_state->uapi.enable) {
10262 if (!new_crtc_state->bigjoiner_slave) {
10263 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
10269 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
10273 ret = intel_modeset_pipe_config(state, new_crtc_state);
10277 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
10283 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10284 new_crtc_state, i) {
10285 if (!intel_crtc_needs_modeset(new_crtc_state))
10288 ret = intel_modeset_pipe_config_late(new_crtc_state);
10292 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
10296 * Check if fastset is allowed by external dependencies like other
10297 * pipes and transcoders.
10299 * Right now it only forces a fullmodeset when the MST master
10300 * transcoder did not changed but the pipe of the master transcoder
10301 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
10302 * in case of port synced crtcs, if one of the synced crtcs
10303 * needs a full modeset, all other synced crtcs should be
10304 * forced a full modeset.
10306 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10307 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
10310 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
10311 enum transcoder master = new_crtc_state->mst_master_transcoder;
10313 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
10314 new_crtc_state->uapi.mode_changed = true;
10315 new_crtc_state->update_pipe = false;
10319 if (is_trans_port_sync_mode(new_crtc_state)) {
10320 u8 trans = new_crtc_state->sync_mode_slaves_mask;
10322 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
10323 trans |= BIT(new_crtc_state->master_transcoder);
10325 if (intel_cpu_transcoders_need_modeset(state, trans)) {
10326 new_crtc_state->uapi.mode_changed = true;
10327 new_crtc_state->update_pipe = false;
10331 if (new_crtc_state->bigjoiner) {
10332 struct intel_crtc_state *linked_crtc_state =
10333 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);
10335 if (intel_crtc_needs_modeset(linked_crtc_state)) {
10336 new_crtc_state->uapi.mode_changed = true;
10337 new_crtc_state->update_pipe = false;
10342 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10343 new_crtc_state, i) {
10344 if (intel_crtc_needs_modeset(new_crtc_state)) {
10349 if (!new_crtc_state->update_pipe)
10352 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
10355 if (any_ms && !check_digital_port_conflicts(state)) {
10356 drm_dbg_kms(&dev_priv->drm,
10357 "rejecting conflicting digital port configuration\n");
10362 ret = drm_dp_mst_atomic_check(&state->base);
10366 ret = intel_atomic_check_planes(state);
10370 intel_fbc_choose_crtc(dev_priv, state);
10371 ret = calc_watermark_data(state);
10375 ret = intel_bw_atomic_check(state);
10379 ret = intel_atomic_check_cdclk(state, &any_ms);
10384 ret = intel_modeset_checks(state);
10388 ret = intel_modeset_calc_cdclk(state);
10392 intel_modeset_clear_plls(state);
10395 ret = intel_atomic_check_crtcs(state);
10399 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10400 new_crtc_state, i) {
10401 if (new_crtc_state->uapi.async_flip) {
10402 ret = intel_atomic_check_async(state);
10407 if (!intel_crtc_needs_modeset(new_crtc_state) &&
10408 !new_crtc_state->update_pipe)
10411 intel_dump_pipe_config(new_crtc_state, state,
10412 intel_crtc_needs_modeset(new_crtc_state) ?
10413 "[modeset]" : "[fastset]");
10419 if (ret == -EDEADLK)
10423 * FIXME would probably be nice to know which crtc specifically
10424 * caused the failure, in cases where we can pinpoint it.
10426 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10428 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
10433 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
10435 struct intel_crtc_state *crtc_state;
10436 struct intel_crtc *crtc;
10439 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
10443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10444 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
10446 if (mode_changed || crtc_state->update_pipe ||
10447 crtc_state->uapi.color_mgmt_changed) {
10448 intel_dsb_prepare(crtc_state);
10455 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
10456 struct intel_crtc_state *crtc_state)
10458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10460 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
10461 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10463 if (crtc_state->has_pch_encoder) {
10464 enum pipe pch_transcoder =
10465 intel_crtc_pch_transcoder(crtc);
10467 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
10471 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
10472 const struct intel_crtc_state *new_crtc_state)
10474 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
10475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10478 * Update pipe size and adjust fitter if needed: the reason for this is
10479 * that in compute_mode_changes we check the native mode (not the pfit
10480 * mode) to see if we can flip rather than do a full mode set. In the
10481 * fastboot case, we'll flip, but if we don't update the pipesrc and
10482 * pfit state, we'll end up with a big fb scanned out into the wrong
10485 intel_set_pipe_src_size(new_crtc_state);
10487 /* on skylake this is done by detaching scalers */
10488 if (INTEL_GEN(dev_priv) >= 9) {
10489 skl_detach_scalers(new_crtc_state);
10491 if (new_crtc_state->pch_pfit.enabled)
10492 skl_pfit_enable(new_crtc_state);
10493 } else if (HAS_PCH_SPLIT(dev_priv)) {
10494 if (new_crtc_state->pch_pfit.enabled)
10495 ilk_pfit_enable(new_crtc_state);
10496 else if (old_crtc_state->pch_pfit.enabled)
10497 ilk_pfit_disable(old_crtc_state);
10501 * The register is supposedly single buffered so perhaps
10502 * not 100% correct to do this here. But SKL+ calculate
10503 * this based on the adjust pixel rate so pfit changes do
10504 * affect it and so it must be updated for fastsets.
10505 * HSW/BDW only really need this here for fastboot, after
10506 * that the value should not change without a full modeset.
10508 if (INTEL_GEN(dev_priv) >= 9 ||
10509 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
10510 hsw_set_linetime_wm(new_crtc_state);
10512 if (INTEL_GEN(dev_priv) >= 11)
10513 icl_set_pipe_chicken(crtc);
10516 static void commit_pipe_config(struct intel_atomic_state *state,
10517 struct intel_crtc *crtc)
10519 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10520 const struct intel_crtc_state *old_crtc_state =
10521 intel_atomic_get_old_crtc_state(state, crtc);
10522 const struct intel_crtc_state *new_crtc_state =
10523 intel_atomic_get_new_crtc_state(state, crtc);
10524 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10527 * During modesets pipe configuration was programmed as the
10528 * CRTC was enabled.
10531 if (new_crtc_state->uapi.color_mgmt_changed ||
10532 new_crtc_state->update_pipe)
10533 intel_color_commit(new_crtc_state);
10535 if (INTEL_GEN(dev_priv) >= 9)
10536 skl_detach_scalers(new_crtc_state);
10538 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
10539 bdw_set_pipemisc(new_crtc_state);
10541 if (new_crtc_state->update_pipe)
10542 intel_pipe_fastset(old_crtc_state, new_crtc_state);
10544 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
10547 if (dev_priv->display.atomic_update_watermarks)
10548 dev_priv->display.atomic_update_watermarks(state, crtc);
10551 static void intel_enable_crtc(struct intel_atomic_state *state,
10552 struct intel_crtc *crtc)
10554 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10555 const struct intel_crtc_state *new_crtc_state =
10556 intel_atomic_get_new_crtc_state(state, crtc);
10558 if (!intel_crtc_needs_modeset(new_crtc_state))
10561 intel_crtc_update_active_timings(new_crtc_state);
10563 dev_priv->display.crtc_enable(state, crtc);
10565 if (new_crtc_state->bigjoiner_slave)
10568 /* vblanks work again, re-enable pipe CRC. */
10569 intel_crtc_enable_pipe_crc(crtc);
10572 static void intel_update_crtc(struct intel_atomic_state *state,
10573 struct intel_crtc *crtc)
10575 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10576 const struct intel_crtc_state *old_crtc_state =
10577 intel_atomic_get_old_crtc_state(state, crtc);
10578 struct intel_crtc_state *new_crtc_state =
10579 intel_atomic_get_new_crtc_state(state, crtc);
10580 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10583 if (new_crtc_state->preload_luts &&
10584 (new_crtc_state->uapi.color_mgmt_changed ||
10585 new_crtc_state->update_pipe))
10586 intel_color_load_luts(new_crtc_state);
10588 intel_pre_plane_update(state, crtc);
10590 if (new_crtc_state->update_pipe)
10591 intel_encoders_update_pipe(state, crtc);
10594 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
10595 intel_fbc_disable(crtc);
10597 intel_fbc_enable(state, crtc);
10599 /* Perform vblank evasion around commit operation */
10600 intel_pipe_update_start(new_crtc_state);
10602 commit_pipe_config(state, crtc);
10604 if (INTEL_GEN(dev_priv) >= 9)
10605 skl_update_planes_on_crtc(state, crtc);
10607 i9xx_update_planes_on_crtc(state, crtc);
10609 intel_pipe_update_end(new_crtc_state);
10612 * We usually enable FIFO underrun interrupts as part of the
10613 * CRTC enable sequence during modesets. But when we inherit a
10614 * valid pipe configuration from the BIOS we need to take care
10615 * of enabling them on the CRTC's first fastset.
10617 if (new_crtc_state->update_pipe && !modeset &&
10618 old_crtc_state->inherited)
10619 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
10622 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
10623 struct intel_crtc_state *old_crtc_state,
10624 struct intel_crtc_state *new_crtc_state,
10625 struct intel_crtc *crtc)
10627 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10629 drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
10631 intel_crtc_disable_planes(state, crtc);
10634 * We still need special handling for disabling bigjoiner master
10635 * and slaves since for slave we do not have encoder or plls
10636 * so we dont need to disable those.
10638 if (old_crtc_state->bigjoiner) {
10639 intel_crtc_disable_planes(state,
10640 old_crtc_state->bigjoiner_linked_crtc);
10641 old_crtc_state->bigjoiner_linked_crtc->active = false;
10645 * We need to disable pipe CRC before disabling the pipe,
10646 * or we race against vblank off.
10648 intel_crtc_disable_pipe_crc(crtc);
10650 dev_priv->display.crtc_disable(state, crtc);
10651 crtc->active = false;
10652 intel_fbc_disable(crtc);
10653 intel_disable_shared_dpll(old_crtc_state);
10655 /* FIXME unify this for all platforms */
10656 if (!new_crtc_state->hw.active &&
10657 !HAS_GMCH(dev_priv) &&
10658 dev_priv->display.initial_watermarks)
10659 dev_priv->display.initial_watermarks(state, crtc);
10662 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
10664 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10665 struct intel_crtc *crtc;
10669 /* Only disable port sync and MST slaves */
10670 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10671 new_crtc_state, i) {
10672 if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
10675 if (!old_crtc_state->hw.active)
10678 /* In case of Transcoder port Sync master slave CRTCs can be
10679 * assigned in any order and we need to make sure that
10680 * slave CRTCs are disabled first and then master CRTC since
10681 * Slave vblanks are masked till Master Vblanks.
10683 if (!is_trans_port_sync_slave(old_crtc_state) &&
10684 !intel_dp_mst_is_slave_trans(old_crtc_state))
10687 intel_pre_plane_update(state, crtc);
10688 intel_old_crtc_state_disables(state, old_crtc_state,
10689 new_crtc_state, crtc);
10690 handled |= BIT(crtc->pipe);
10693 /* Disable everything else left on */
10694 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10695 new_crtc_state, i) {
10696 if (!intel_crtc_needs_modeset(new_crtc_state) ||
10697 (handled & BIT(crtc->pipe)) ||
10698 old_crtc_state->bigjoiner_slave)
10701 intel_pre_plane_update(state, crtc);
10702 if (old_crtc_state->bigjoiner) {
10703 struct intel_crtc *slave =
10704 old_crtc_state->bigjoiner_linked_crtc;
10706 intel_pre_plane_update(state, slave);
10709 if (old_crtc_state->hw.active)
10710 intel_old_crtc_state_disables(state, old_crtc_state,
10711 new_crtc_state, crtc);
10715 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
10717 struct intel_crtc_state *new_crtc_state;
10718 struct intel_crtc *crtc;
10721 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10722 if (!new_crtc_state->hw.active)
10725 intel_enable_crtc(state, crtc);
10726 intel_update_crtc(state, crtc);
10730 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
10732 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10733 struct intel_crtc *crtc;
10734 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10735 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
10736 u8 update_pipes = 0, modeset_pipes = 0;
10739 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10740 enum pipe pipe = crtc->pipe;
10742 if (!new_crtc_state->hw.active)
10745 /* ignore allocations for crtc's that have been turned off. */
10746 if (!intel_crtc_needs_modeset(new_crtc_state)) {
10747 entries[pipe] = old_crtc_state->wm.skl.ddb;
10748 update_pipes |= BIT(pipe);
10750 modeset_pipes |= BIT(pipe);
10755 * Whenever the number of active pipes changes, we need to make sure we
10756 * update the pipes in the right order so that their ddb allocations
10757 * never overlap with each other between CRTC updates. Otherwise we'll
10758 * cause pipe underruns and other bad stuff.
10760 * So first lets enable all pipes that do not need a fullmodeset as
10761 * those don't have any external dependency.
10763 while (update_pipes) {
10764 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10765 new_crtc_state, i) {
10766 enum pipe pipe = crtc->pipe;
10768 if ((update_pipes & BIT(pipe)) == 0)
10771 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10772 entries, I915_MAX_PIPES, pipe))
10775 entries[pipe] = new_crtc_state->wm.skl.ddb;
10776 update_pipes &= ~BIT(pipe);
10778 intel_update_crtc(state, crtc);
10781 * If this is an already active pipe, it's DDB changed,
10782 * and this isn't the last pipe that needs updating
10783 * then we need to wait for a vblank to pass for the
10784 * new ddb allocation to take effect.
10786 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
10787 &old_crtc_state->wm.skl.ddb) &&
10788 (update_pipes | modeset_pipes))
10789 intel_wait_for_vblank(dev_priv, pipe);
10793 update_pipes = modeset_pipes;
10796 * Enable all pipes that needs a modeset and do not depends on other
10799 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10800 enum pipe pipe = crtc->pipe;
10802 if ((modeset_pipes & BIT(pipe)) == 0)
10805 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
10806 is_trans_port_sync_master(new_crtc_state) ||
10807 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
10810 modeset_pipes &= ~BIT(pipe);
10812 intel_enable_crtc(state, crtc);
10816 * Then we enable all remaining pipes that depend on other
10817 * pipes: MST slaves and port sync masters, big joiner master
10819 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10820 enum pipe pipe = crtc->pipe;
10822 if ((modeset_pipes & BIT(pipe)) == 0)
10825 modeset_pipes &= ~BIT(pipe);
10827 intel_enable_crtc(state, crtc);
10831 * Finally we do the plane updates/etc. for all pipes that got enabled.
10833 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10834 enum pipe pipe = crtc->pipe;
10836 if ((update_pipes & BIT(pipe)) == 0)
10839 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10840 entries, I915_MAX_PIPES, pipe));
10842 entries[pipe] = new_crtc_state->wm.skl.ddb;
10843 update_pipes &= ~BIT(pipe);
10845 intel_update_crtc(state, crtc);
10848 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
10849 drm_WARN_ON(&dev_priv->drm, update_pipes);
10852 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
10854 struct intel_atomic_state *state, *next;
10855 struct llist_node *freed;
10857 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
10858 llist_for_each_entry_safe(state, next, freed, freed)
10859 drm_atomic_state_put(&state->base);
10862 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
10864 struct drm_i915_private *dev_priv =
10865 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
10867 intel_atomic_helper_free_state(dev_priv);
10870 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
10872 struct wait_queue_entry wait_fence, wait_reset;
10873 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
10875 init_wait_entry(&wait_fence, 0);
10876 init_wait_entry(&wait_reset, 0);
10878 prepare_to_wait(&intel_state->commit_ready.wait,
10879 &wait_fence, TASK_UNINTERRUPTIBLE);
10880 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10881 I915_RESET_MODESET),
10882 &wait_reset, TASK_UNINTERRUPTIBLE);
10885 if (i915_sw_fence_done(&intel_state->commit_ready) ||
10886 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
10891 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
10892 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10893 I915_RESET_MODESET),
10897 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
10899 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10900 struct intel_crtc *crtc;
10903 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10905 intel_dsb_cleanup(old_crtc_state);
10908 static void intel_atomic_cleanup_work(struct work_struct *work)
10910 struct intel_atomic_state *state =
10911 container_of(work, struct intel_atomic_state, base.commit_work);
10912 struct drm_i915_private *i915 = to_i915(state->base.dev);
10914 intel_cleanup_dsbs(state);
10915 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
10916 drm_atomic_helper_commit_cleanup_done(&state->base);
10917 drm_atomic_state_put(&state->base);
10919 intel_atomic_helper_free_state(i915);
10922 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
10924 struct drm_i915_private *i915 = to_i915(state->base.dev);
10925 struct intel_plane *plane;
10926 struct intel_plane_state *plane_state;
10929 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10930 struct drm_framebuffer *fb = plane_state->hw.fb;
10934 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
10938 * The layout of the fast clear color value expected by HW
10939 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
10940 * - 4 x 4 bytes per-channel value
10941 * (in surface type specific float/int format provided by the fb user)
10942 * - 8 bytes native color value used by the display
10943 * (converted/written by GPU during a fast clear operation using the
10944 * above per-channel values)
10946 * The commit's FB prepare hook already ensured that FB obj is pinned and the
10947 * caller made sure that the object is synced wrt. the related color clear value
10950 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
10951 fb->offsets[2] + 16,
10952 &plane_state->ccval,
10953 sizeof(plane_state->ccval));
10954 /* The above could only fail if the FB obj has an unexpected backing store type. */
10955 drm_WARN_ON(&i915->drm, ret);
10959 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
10961 struct drm_device *dev = state->base.dev;
10962 struct drm_i915_private *dev_priv = to_i915(dev);
10963 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10964 struct intel_crtc *crtc;
10965 u64 put_domains[I915_MAX_PIPES] = {};
10966 intel_wakeref_t wakeref = 0;
10969 intel_atomic_commit_fence_wait(state);
10971 drm_atomic_helper_wait_for_dependencies(&state->base);
10973 if (state->modeset)
10974 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
10976 intel_atomic_prepare_plane_clear_colors(state);
10978 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10979 new_crtc_state, i) {
10980 if (intel_crtc_needs_modeset(new_crtc_state) ||
10981 new_crtc_state->update_pipe) {
10983 put_domains[crtc->pipe] =
10984 modeset_get_crtc_power_domains(new_crtc_state);
10988 intel_commit_modeset_disables(state);
10990 /* FIXME: Eventually get rid of our crtc->config pointer */
10991 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10992 crtc->config = new_crtc_state;
10994 if (state->modeset) {
10995 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
10997 intel_set_cdclk_pre_plane_update(state);
10999 intel_modeset_verify_disabled(dev_priv, state);
11002 intel_sagv_pre_plane_update(state);
11004 /* Complete the events for pipes that have now been disabled */
11005 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
11006 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
11008 /* Complete events for now disable pipes here. */
11009 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
11010 spin_lock_irq(&dev->event_lock);
11011 drm_crtc_send_vblank_event(&crtc->base,
11012 new_crtc_state->uapi.event);
11013 spin_unlock_irq(&dev->event_lock);
11015 new_crtc_state->uapi.event = NULL;
11019 if (state->modeset)
11020 intel_encoders_update_prepare(state);
11022 intel_dbuf_pre_plane_update(state);
11024 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
11025 if (new_crtc_state->uapi.async_flip)
11026 intel_crtc_enable_flip_done(state, crtc);
11029 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11030 dev_priv->display.commit_modeset_enables(state);
11032 if (state->modeset) {
11033 intel_encoders_update_complete(state);
11035 intel_set_cdclk_post_plane_update(state);
11038 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
11039 * already, but still need the state for the delayed optimization. To
11041 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
11042 * - schedule that vblank worker _before_ calling hw_done
11043 * - at the start of commit_tail, cancel it _synchrously
11044 * - switch over to the vblank wait helper in the core after that since
11045 * we don't need out special handling any more.
11047 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
11049 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
11050 if (new_crtc_state->uapi.async_flip)
11051 intel_crtc_disable_flip_done(state, crtc);
11053 if (new_crtc_state->hw.active &&
11054 !intel_crtc_needs_modeset(new_crtc_state) &&
11055 !new_crtc_state->preload_luts &&
11056 (new_crtc_state->uapi.color_mgmt_changed ||
11057 new_crtc_state->update_pipe))
11058 intel_color_load_luts(new_crtc_state);
11062 * Now that the vblank has passed, we can go ahead and program the
11063 * optimal watermarks on platforms that need two-step watermark
11066 * TODO: Move this (and other cleanup) to an async worker eventually.
11068 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
11069 new_crtc_state, i) {
11071 * Gen2 reports pipe underruns whenever all planes are disabled.
11072 * So re-enable underrun reporting after some planes get enabled.
11074 * We do this before .optimize_watermarks() so that we have a
11075 * chance of catching underruns with the intermediate watermarks
11076 * vs. the new plane configuration.
11078 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
11079 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
11081 if (dev_priv->display.optimize_watermarks)
11082 dev_priv->display.optimize_watermarks(state, crtc);
11085 intel_dbuf_post_plane_update(state);
11087 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11088 intel_post_plane_update(state, crtc);
11090 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
11092 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
11095 * DSB cleanup is done in cleanup_work aligning with framebuffer
11096 * cleanup. So copy and reset the dsb structure to sync with
11097 * commit_done and later do dsb cleanup in cleanup_work.
11099 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
11102 /* Underruns don't always raise interrupts, so check manually */
11103 intel_check_cpu_fifo_underruns(dev_priv);
11104 intel_check_pch_fifo_underruns(dev_priv);
11106 if (state->modeset)
11107 intel_verify_planes(state);
11109 intel_sagv_post_plane_update(state);
11111 drm_atomic_helper_commit_hw_done(&state->base);
11113 if (state->modeset) {
11114 /* As one of the primary mmio accessors, KMS has a high
11115 * likelihood of triggering bugs in unclaimed access. After we
11116 * finish modesetting, see if an error has been flagged, and if
11117 * so enable debugging for the next modeset - and hope we catch
11120 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
11121 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
11123 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
11126 * Defer the cleanup of the old state to a separate worker to not
11127 * impede the current task (userspace for blocking modesets) that
11128 * are executed inline. For out-of-line asynchronous modesets/flips,
11129 * deferring to a new worker seems overkill, but we would place a
11130 * schedule point (cond_resched()) here anyway to keep latencies
11133 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
11134 queue_work(system_highpri_wq, &state->base.commit_work);
11137 static void intel_atomic_commit_work(struct work_struct *work)
11139 struct intel_atomic_state *state =
11140 container_of(work, struct intel_atomic_state, base.commit_work);
11142 intel_atomic_commit_tail(state);
11145 static int __i915_sw_fence_call
11146 intel_atomic_commit_ready(struct i915_sw_fence *fence,
11147 enum i915_sw_fence_notify notify)
11149 struct intel_atomic_state *state =
11150 container_of(fence, struct intel_atomic_state, commit_ready);
11153 case FENCE_COMPLETE:
11154 /* we do blocking waits in the worker, nothing to do here */
11158 struct intel_atomic_helper *helper =
11159 &to_i915(state->base.dev)->atomic_helper;
11161 if (llist_add(&state->freed, &helper->free_list))
11162 schedule_work(&helper->free_work);
11167 return NOTIFY_DONE;
11170 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
11172 struct intel_plane_state *old_plane_state, *new_plane_state;
11173 struct intel_plane *plane;
11176 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
11177 new_plane_state, i)
11178 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
11179 to_intel_frontbuffer(new_plane_state->hw.fb),
11180 plane->frontbuffer_bit);
11183 static int intel_atomic_commit(struct drm_device *dev,
11184 struct drm_atomic_state *_state,
11187 struct intel_atomic_state *state = to_intel_atomic_state(_state);
11188 struct drm_i915_private *dev_priv = to_i915(dev);
11191 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
11193 drm_atomic_state_get(&state->base);
11194 i915_sw_fence_init(&state->commit_ready,
11195 intel_atomic_commit_ready);
11198 * The intel_legacy_cursor_update() fast path takes care
11199 * of avoiding the vblank waits for simple cursor
11200 * movement and flips. For cursor on/off and size changes,
11201 * we want to perform the vblank waits so that watermark
11202 * updates happen during the correct frames. Gen9+ have
11203 * double buffered watermarks and so shouldn't need this.
11205 * Unset state->legacy_cursor_update before the call to
11206 * drm_atomic_helper_setup_commit() because otherwise
11207 * drm_atomic_helper_wait_for_flip_done() is a noop and
11208 * we get FIFO underruns because we didn't wait
11211 * FIXME doing watermarks and fb cleanup from a vblank worker
11212 * (assuming we had any) would solve these problems.
11214 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
11215 struct intel_crtc_state *new_crtc_state;
11216 struct intel_crtc *crtc;
11219 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
11220 if (new_crtc_state->wm.need_postvbl_update ||
11221 new_crtc_state->update_wm_post)
11222 state->base.legacy_cursor_update = false;
11225 ret = intel_atomic_prepare_commit(state);
11227 drm_dbg_atomic(&dev_priv->drm,
11228 "Preparing state failed with %i\n", ret);
11229 i915_sw_fence_commit(&state->commit_ready);
11230 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
11234 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
11236 ret = drm_atomic_helper_swap_state(&state->base, true);
11238 intel_atomic_swap_global_state(state);
11241 struct intel_crtc_state *new_crtc_state;
11242 struct intel_crtc *crtc;
11245 i915_sw_fence_commit(&state->commit_ready);
11247 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
11248 intel_dsb_cleanup(new_crtc_state);
11250 drm_atomic_helper_cleanup_planes(dev, &state->base);
11251 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
11254 intel_shared_dpll_swap_state(state);
11255 intel_atomic_track_fbs(state);
11257 drm_atomic_state_get(&state->base);
11258 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
11260 i915_sw_fence_commit(&state->commit_ready);
11261 if (nonblock && state->modeset) {
11262 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
11263 } else if (nonblock) {
11264 queue_work(dev_priv->flip_wq, &state->base.commit_work);
11266 if (state->modeset)
11267 flush_workqueue(dev_priv->modeset_wq);
11268 intel_atomic_commit_tail(state);
11274 struct wait_rps_boost {
11275 struct wait_queue_entry wait;
11277 struct drm_crtc *crtc;
11278 struct i915_request *request;
11281 static int do_rps_boost(struct wait_queue_entry *_wait,
11282 unsigned mode, int sync, void *key)
11284 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
11285 struct i915_request *rq = wait->request;
11288 * If we missed the vblank, but the request is already running it
11289 * is reasonable to assume that it will complete before the next
11290 * vblank without our intervention, so leave RPS alone.
11292 if (!i915_request_started(rq))
11293 intel_rps_boost(rq);
11294 i915_request_put(rq);
11296 drm_crtc_vblank_put(wait->crtc);
11298 list_del(&wait->wait.entry);
11303 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
11304 struct dma_fence *fence)
11306 struct wait_rps_boost *wait;
11308 if (!dma_fence_is_i915(fence))
11311 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
11314 if (drm_crtc_vblank_get(crtc))
11317 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
11319 drm_crtc_vblank_put(crtc);
11323 wait->request = to_request(dma_fence_get(fence));
11326 wait->wait.func = do_rps_boost;
11327 wait->wait.flags = 0;
11329 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
11332 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
11334 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11335 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11336 struct drm_framebuffer *fb = plane_state->hw.fb;
11337 struct i915_vma *vma;
11339 if (plane->id == PLANE_CURSOR &&
11340 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
11341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11342 const int align = intel_cursor_alignment(dev_priv);
11345 err = i915_gem_object_attach_phys(obj, align);
11350 vma = intel_pin_and_fence_fb_obj(fb,
11351 &plane_state->view,
11352 intel_plane_uses_fence(plane_state),
11353 &plane_state->flags);
11355 return PTR_ERR(vma);
11357 plane_state->vma = vma;
11362 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
11364 struct i915_vma *vma;
11366 vma = fetch_and_zero(&old_plane_state->vma);
11368 intel_unpin_fb_vma(vma, old_plane_state->flags);
11372 * intel_prepare_plane_fb - Prepare fb for usage on plane
11373 * @_plane: drm plane to prepare for
11374 * @_new_plane_state: the plane state being prepared
11376 * Prepares a framebuffer for usage on a display plane. Generally this
11377 * involves pinning the underlying object and updating the frontbuffer tracking
11378 * bits. Some older platforms need special physical address handling for
11381 * Returns 0 on success, negative error code on failure.
11384 intel_prepare_plane_fb(struct drm_plane *_plane,
11385 struct drm_plane_state *_new_plane_state)
11387 struct i915_sched_attr attr = {
11388 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
11390 struct intel_plane *plane = to_intel_plane(_plane);
11391 struct intel_plane_state *new_plane_state =
11392 to_intel_plane_state(_new_plane_state);
11393 struct intel_atomic_state *state =
11394 to_intel_atomic_state(new_plane_state->uapi.state);
11395 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11396 const struct intel_plane_state *old_plane_state =
11397 intel_atomic_get_old_plane_state(state, plane);
11398 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
11399 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
11403 const struct intel_crtc_state *crtc_state =
11404 intel_atomic_get_new_crtc_state(state,
11405 to_intel_crtc(old_plane_state->hw.crtc));
11407 /* Big Hammer, we also need to ensure that any pending
11408 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
11409 * current scanout is retired before unpinning the old
11410 * framebuffer. Note that we rely on userspace rendering
11411 * into the buffer attached to the pipe they are waiting
11412 * on. If not, userspace generates a GPU hang with IPEHR
11413 * point to the MI_WAIT_FOR_EVENT.
11415 * This should only fail upon a hung GPU, in which case we
11416 * can safely continue.
11418 if (intel_crtc_needs_modeset(crtc_state)) {
11419 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11420 old_obj->base.resv, NULL,
11428 if (new_plane_state->uapi.fence) { /* explicit fencing */
11429 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
11431 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
11432 new_plane_state->uapi.fence,
11433 i915_fence_timeout(dev_priv),
11442 ret = i915_gem_object_pin_pages(obj);
11446 ret = intel_plane_pin_fb(new_plane_state);
11448 i915_gem_object_unpin_pages(obj);
11452 i915_gem_object_wait_priority(obj, 0, &attr);
11453 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
11455 if (!new_plane_state->uapi.fence) { /* implicit fencing */
11456 struct dma_fence *fence;
11458 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11459 obj->base.resv, NULL,
11461 i915_fence_timeout(dev_priv),
11466 fence = dma_resv_get_excl_rcu(obj->base.resv);
11468 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11470 dma_fence_put(fence);
11473 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11474 new_plane_state->uapi.fence);
11478 * We declare pageflips to be interactive and so merit a small bias
11479 * towards upclocking to deliver the frame on time. By only changing
11480 * the RPS thresholds to sample more regularly and aim for higher
11481 * clocks we can hopefully deliver low power workloads (like kodi)
11482 * that are not quite steady state without resorting to forcing
11483 * maximum clocks following a vblank miss (see do_rps_boost()).
11485 if (!state->rps_interactive) {
11486 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
11487 state->rps_interactive = true;
11493 intel_plane_unpin_fb(new_plane_state);
11499 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11500 * @plane: drm plane to clean up for
11501 * @_old_plane_state: the state from the previous modeset
11503 * Cleans up a framebuffer that has just been removed from a plane.
11506 intel_cleanup_plane_fb(struct drm_plane *plane,
11507 struct drm_plane_state *_old_plane_state)
11509 struct intel_plane_state *old_plane_state =
11510 to_intel_plane_state(_old_plane_state);
11511 struct intel_atomic_state *state =
11512 to_intel_atomic_state(old_plane_state->uapi.state);
11513 struct drm_i915_private *dev_priv = to_i915(plane->dev);
11514 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
11519 if (state->rps_interactive) {
11520 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
11521 state->rps_interactive = false;
11524 /* Should only be called after a successful intel_prepare_plane_fb()! */
11525 intel_plane_unpin_fb(old_plane_state);
11529 * intel_plane_destroy - destroy a plane
11530 * @plane: plane to destroy
11532 * Common destruction function for all types of planes (primary, cursor,
11535 void intel_plane_destroy(struct drm_plane *plane)
11537 drm_plane_cleanup(plane);
11538 kfree(to_intel_plane(plane));
11541 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
11543 struct intel_plane *plane;
11545 for_each_intel_plane(&dev_priv->drm, plane) {
11546 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11549 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
11554 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
11555 struct drm_file *file)
11557 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11558 struct drm_crtc *drmmode_crtc;
11559 struct intel_crtc *crtc;
11561 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
11565 crtc = to_intel_crtc(drmmode_crtc);
11566 pipe_from_crtc_id->pipe = crtc->pipe;
11571 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
11573 struct drm_device *dev = encoder->base.dev;
11574 struct intel_encoder *source_encoder;
11575 u32 possible_clones = 0;
11577 for_each_intel_encoder(dev, source_encoder) {
11578 if (encoders_cloneable(encoder, source_encoder))
11579 possible_clones |= drm_encoder_mask(&source_encoder->base);
11582 return possible_clones;
11585 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
11587 struct drm_device *dev = encoder->base.dev;
11588 struct intel_crtc *crtc;
11589 u32 possible_crtcs = 0;
11591 for_each_intel_crtc(dev, crtc) {
11592 if (encoder->pipe_mask & BIT(crtc->pipe))
11593 possible_crtcs |= drm_crtc_mask(&crtc->base);
11596 return possible_crtcs;
11599 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
11601 if (!IS_MOBILE(dev_priv))
11604 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
11607 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
11613 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
11615 if (INTEL_GEN(dev_priv) >= 9)
11618 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
11621 if (HAS_PCH_LPT_H(dev_priv) &&
11622 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
11625 /* DDI E can't be used if DDI A requires 4 lanes */
11626 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
11629 if (!dev_priv->vbt.int_crt_support)
11635 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
11637 struct intel_encoder *encoder;
11638 bool dpd_is_edp = false;
11640 intel_pps_unlock_regs_wa(dev_priv);
11642 if (!HAS_DISPLAY(dev_priv))
11645 if (IS_ALDERLAKE_S(dev_priv)) {
11646 intel_ddi_init(dev_priv, PORT_A);
11647 intel_ddi_init(dev_priv, PORT_TC1);
11648 intel_ddi_init(dev_priv, PORT_TC2);
11649 intel_ddi_init(dev_priv, PORT_TC3);
11650 intel_ddi_init(dev_priv, PORT_TC4);
11651 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
11652 intel_ddi_init(dev_priv, PORT_A);
11653 intel_ddi_init(dev_priv, PORT_B);
11654 intel_ddi_init(dev_priv, PORT_TC1);
11655 intel_ddi_init(dev_priv, PORT_TC2);
11656 } else if (INTEL_GEN(dev_priv) >= 12) {
11657 intel_ddi_init(dev_priv, PORT_A);
11658 intel_ddi_init(dev_priv, PORT_B);
11659 intel_ddi_init(dev_priv, PORT_TC1);
11660 intel_ddi_init(dev_priv, PORT_TC2);
11661 intel_ddi_init(dev_priv, PORT_TC3);
11662 intel_ddi_init(dev_priv, PORT_TC4);
11663 intel_ddi_init(dev_priv, PORT_TC5);
11664 intel_ddi_init(dev_priv, PORT_TC6);
11665 icl_dsi_init(dev_priv);
11666 } else if (IS_JSL_EHL(dev_priv)) {
11667 intel_ddi_init(dev_priv, PORT_A);
11668 intel_ddi_init(dev_priv, PORT_B);
11669 intel_ddi_init(dev_priv, PORT_C);
11670 intel_ddi_init(dev_priv, PORT_D);
11671 icl_dsi_init(dev_priv);
11672 } else if (IS_GEN(dev_priv, 11)) {
11673 intel_ddi_init(dev_priv, PORT_A);
11674 intel_ddi_init(dev_priv, PORT_B);
11675 intel_ddi_init(dev_priv, PORT_C);
11676 intel_ddi_init(dev_priv, PORT_D);
11677 intel_ddi_init(dev_priv, PORT_E);
11679 * On some ICL SKUs port F is not present. No strap bits for
11680 * this, so rely on VBT.
11681 * Work around broken VBTs on SKUs known to have no port F.
11683 if (IS_ICL_WITH_PORT_F(dev_priv) &&
11684 intel_bios_is_port_present(dev_priv, PORT_F))
11685 intel_ddi_init(dev_priv, PORT_F);
11687 icl_dsi_init(dev_priv);
11688 } else if (IS_GEN9_LP(dev_priv)) {
11690 * FIXME: Broxton doesn't support port detection via the
11691 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
11692 * detect the ports.
11694 intel_ddi_init(dev_priv, PORT_A);
11695 intel_ddi_init(dev_priv, PORT_B);
11696 intel_ddi_init(dev_priv, PORT_C);
11698 vlv_dsi_init(dev_priv);
11699 } else if (HAS_DDI(dev_priv)) {
11702 if (intel_ddi_crt_present(dev_priv))
11703 intel_crt_init(dev_priv);
11706 * Haswell uses DDI functions to detect digital outputs.
11707 * On SKL pre-D0 the strap isn't connected. Later SKUs may or
11708 * may not have it - it was supposed to be fixed by the same
11709 * time we stopped using straps. Assume it's there.
11711 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
11712 /* WaIgnoreDDIAStrap: skl */
11713 if (found || IS_GEN9_BC(dev_priv))
11714 intel_ddi_init(dev_priv, PORT_A);
11716 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
11718 if (HAS_PCH_TGP(dev_priv)) {
11719 /* W/A due to lack of STRAP config on TGP PCH*/
11720 found = (SFUSE_STRAP_DDIB_DETECTED |
11721 SFUSE_STRAP_DDIC_DETECTED |
11722 SFUSE_STRAP_DDID_DETECTED);
11724 found = intel_de_read(dev_priv, SFUSE_STRAP);
11727 if (found & SFUSE_STRAP_DDIB_DETECTED)
11728 intel_ddi_init(dev_priv, PORT_B);
11729 if (found & SFUSE_STRAP_DDIC_DETECTED)
11730 intel_ddi_init(dev_priv, PORT_C);
11731 if (found & SFUSE_STRAP_DDID_DETECTED)
11732 intel_ddi_init(dev_priv, PORT_D);
11733 if (found & SFUSE_STRAP_DDIF_DETECTED)
11734 intel_ddi_init(dev_priv, PORT_F);
11736 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
11738 if (IS_GEN9_BC(dev_priv) &&
11739 intel_bios_is_port_present(dev_priv, PORT_E))
11740 intel_ddi_init(dev_priv, PORT_E);
11742 } else if (HAS_PCH_SPLIT(dev_priv)) {
11746 * intel_edp_init_connector() depends on this completing first,
11747 * to prevent the registration of both eDP and LVDS and the
11748 * incorrect sharing of the PPS.
11750 intel_lvds_init(dev_priv);
11751 intel_crt_init(dev_priv);
11753 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
11755 if (ilk_has_edp_a(dev_priv))
11756 intel_dp_init(dev_priv, DP_A, PORT_A);
11758 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
11759 /* PCH SDVOB multiplex with HDMIB */
11760 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
11762 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
11763 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
11764 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
11767 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
11768 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
11770 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
11771 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
11773 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
11774 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
11776 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
11777 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
11778 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11779 bool has_edp, has_port;
11781 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
11782 intel_crt_init(dev_priv);
11785 * The DP_DETECTED bit is the latched state of the DDC
11786 * SDA pin at boot. However since eDP doesn't require DDC
11787 * (no way to plug in a DP->HDMI dongle) the DDC pins for
11788 * eDP ports may have been muxed to an alternate function.
11789 * Thus we can't rely on the DP_DETECTED bit alone to detect
11790 * eDP ports. Consult the VBT as well as DP_DETECTED to
11791 * detect eDP ports.
11793 * Sadly the straps seem to be missing sometimes even for HDMI
11794 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
11795 * and VBT for the presence of the port. Additionally we can't
11796 * trust the port type the VBT declares as we've seen at least
11797 * HDMI ports that the VBT claim are DP or eDP.
11799 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
11800 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
11801 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
11802 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
11803 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
11804 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
11806 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
11807 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
11808 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
11809 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
11810 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
11811 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
11813 if (IS_CHERRYVIEW(dev_priv)) {
11815 * eDP not supported on port D,
11816 * so no need to worry about it
11818 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
11819 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
11820 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
11821 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
11822 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
11825 vlv_dsi_init(dev_priv);
11826 } else if (IS_PINEVIEW(dev_priv)) {
11827 intel_lvds_init(dev_priv);
11828 intel_crt_init(dev_priv);
11829 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
11830 bool found = false;
11832 if (IS_MOBILE(dev_priv))
11833 intel_lvds_init(dev_priv);
11835 intel_crt_init(dev_priv);
11837 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11838 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
11839 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
11840 if (!found && IS_G4X(dev_priv)) {
11841 drm_dbg_kms(&dev_priv->drm,
11842 "probing HDMI on SDVOB\n");
11843 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
11846 if (!found && IS_G4X(dev_priv))
11847 intel_dp_init(dev_priv, DP_B, PORT_B);
11850 /* Before G4X SDVOC doesn't have its own detect register */
11852 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11853 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
11854 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
11857 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
11859 if (IS_G4X(dev_priv)) {
11860 drm_dbg_kms(&dev_priv->drm,
11861 "probing HDMI on SDVOC\n");
11862 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
11864 if (IS_G4X(dev_priv))
11865 intel_dp_init(dev_priv, DP_C, PORT_C);
11868 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
11869 intel_dp_init(dev_priv, DP_D, PORT_D);
11871 if (SUPPORTS_TV(dev_priv))
11872 intel_tv_init(dev_priv);
11873 } else if (IS_GEN(dev_priv, 2)) {
11874 if (IS_I85X(dev_priv))
11875 intel_lvds_init(dev_priv);
11877 intel_crt_init(dev_priv);
11878 intel_dvo_init(dev_priv);
11881 for_each_intel_encoder(&dev_priv->drm, encoder) {
11882 encoder->base.possible_crtcs =
11883 intel_encoder_possible_crtcs(encoder);
11884 encoder->base.possible_clones =
11885 intel_encoder_possible_clones(encoder);
11888 intel_init_pch_refclk(dev_priv);
11890 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
11893 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11895 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11897 drm_framebuffer_cleanup(fb);
11898 intel_frontbuffer_put(intel_fb->frontbuffer);
11903 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11904 struct drm_file *file,
11905 unsigned int *handle)
11907 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11908 struct drm_i915_private *i915 = to_i915(obj->base.dev);
11910 if (obj->userptr.mm) {
11911 drm_dbg(&i915->drm,
11912 "attempting to use a userptr for a framebuffer, denied\n");
11916 return drm_gem_handle_create(file, &obj->base, handle);
11919 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
11920 struct drm_file *file,
11921 unsigned flags, unsigned color,
11922 struct drm_clip_rect *clips,
11923 unsigned num_clips)
11925 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11927 i915_gem_object_flush_if_display(obj);
11928 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
11933 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11934 .destroy = intel_user_framebuffer_destroy,
11935 .create_handle = intel_user_framebuffer_create_handle,
11936 .dirty = intel_user_framebuffer_dirty,
11939 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
11940 struct drm_i915_gem_object *obj,
11941 struct drm_mode_fb_cmd2 *mode_cmd)
11943 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
11944 struct drm_framebuffer *fb = &intel_fb->base;
11946 unsigned int tiling, stride;
11950 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
11951 if (!intel_fb->frontbuffer)
11954 i915_gem_object_lock(obj, NULL);
11955 tiling = i915_gem_object_get_tiling(obj);
11956 stride = i915_gem_object_get_stride(obj);
11957 i915_gem_object_unlock(obj);
11959 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
11961 * If there's a fence, enforce that
11962 * the fb modifier and tiling mode match.
11964 if (tiling != I915_TILING_NONE &&
11965 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11966 drm_dbg_kms(&dev_priv->drm,
11967 "tiling_mode doesn't match fb modifier\n");
11971 if (tiling == I915_TILING_X) {
11972 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
11973 } else if (tiling == I915_TILING_Y) {
11974 drm_dbg_kms(&dev_priv->drm,
11975 "No Y tiling for legacy addfb\n");
11980 if (!drm_any_plane_has_format(&dev_priv->drm,
11981 mode_cmd->pixel_format,
11982 mode_cmd->modifier[0])) {
11983 struct drm_format_name_buf format_name;
11985 drm_dbg_kms(&dev_priv->drm,
11986 "unsupported pixel format %s / modifier 0x%llx\n",
11987 drm_get_format_name(mode_cmd->pixel_format,
11989 mode_cmd->modifier[0]);
11994 * gen2/3 display engine uses the fence if present,
11995 * so the tiling mode must match the fb modifier exactly.
11997 if (INTEL_GEN(dev_priv) < 4 &&
11998 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11999 drm_dbg_kms(&dev_priv->drm,
12000 "tiling_mode must match fb modifier exactly on gen2/3\n");
12004 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
12005 mode_cmd->modifier[0]);
12006 if (mode_cmd->pitches[0] > max_stride) {
12007 drm_dbg_kms(&dev_priv->drm,
12008 "%s pitch (%u) must be at most %d\n",
12009 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
12010 "tiled" : "linear",
12011 mode_cmd->pitches[0], max_stride);
12016 * If there's a fence, enforce that
12017 * the fb pitch and fence stride match.
12019 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
12020 drm_dbg_kms(&dev_priv->drm,
12021 "pitch (%d) must match tiling stride (%d)\n",
12022 mode_cmd->pitches[0], stride);
12026 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12027 if (mode_cmd->offsets[0] != 0) {
12028 drm_dbg_kms(&dev_priv->drm,
12029 "plane 0 offset (0x%08x) must be 0\n",
12030 mode_cmd->offsets[0]);
12034 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
12036 for (i = 0; i < fb->format->num_planes; i++) {
12037 u32 stride_alignment;
12039 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
12040 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
12045 stride_alignment = intel_fb_stride_alignment(fb, i);
12046 if (fb->pitches[i] & (stride_alignment - 1)) {
12047 drm_dbg_kms(&dev_priv->drm,
12048 "plane %d pitch (%d) must be at least %u byte aligned\n",
12049 i, fb->pitches[i], stride_alignment);
12053 if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
12054 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
12056 if (fb->pitches[i] != ccs_aux_stride) {
12057 drm_dbg_kms(&dev_priv->drm,
12058 "ccs aux plane %d pitch (%d) must be %d\n",
12060 fb->pitches[i], ccs_aux_stride);
12065 fb->obj[i] = &obj->base;
12068 ret = intel_fill_fb_info(dev_priv, fb);
12072 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
12074 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
12081 intel_frontbuffer_put(intel_fb->frontbuffer);
12085 static struct drm_framebuffer *
12086 intel_user_framebuffer_create(struct drm_device *dev,
12087 struct drm_file *filp,
12088 const struct drm_mode_fb_cmd2 *user_mode_cmd)
12090 struct drm_framebuffer *fb;
12091 struct drm_i915_gem_object *obj;
12092 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
12094 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
12096 return ERR_PTR(-ENOENT);
12098 fb = intel_framebuffer_create(obj, &mode_cmd);
12099 i915_gem_object_put(obj);
12104 static enum drm_mode_status
12105 intel_mode_valid(struct drm_device *dev,
12106 const struct drm_display_mode *mode)
12108 struct drm_i915_private *dev_priv = to_i915(dev);
12109 int hdisplay_max, htotal_max;
12110 int vdisplay_max, vtotal_max;
12113 * Can't reject DBLSCAN here because Xorg ddxen can add piles
12114 * of DBLSCAN modes to the output's mode list when they detect
12115 * the scaling mode property on the connector. And they don't
12116 * ask the kernel to validate those modes in any way until
12117 * modeset time at which point the client gets a protocol error.
12118 * So in order to not upset those clients we silently ignore the
12119 * DBLSCAN flag on such connectors. For other connectors we will
12120 * reject modes with the DBLSCAN flag in encoder->compute_config().
12121 * And we always reject DBLSCAN modes in connector->mode_valid()
12122 * as we never want such modes on the connector's mode list.
12125 if (mode->vscan > 1)
12126 return MODE_NO_VSCAN;
12128 if (mode->flags & DRM_MODE_FLAG_HSKEW)
12129 return MODE_H_ILLEGAL;
12131 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
12132 DRM_MODE_FLAG_NCSYNC |
12133 DRM_MODE_FLAG_PCSYNC))
12136 if (mode->flags & (DRM_MODE_FLAG_BCAST |
12137 DRM_MODE_FLAG_PIXMUX |
12138 DRM_MODE_FLAG_CLKDIV2))
12141 /* Transcoder timing limits */
12142 if (INTEL_GEN(dev_priv) >= 11) {
12143 hdisplay_max = 16384;
12144 vdisplay_max = 8192;
12145 htotal_max = 16384;
12147 } else if (INTEL_GEN(dev_priv) >= 9 ||
12148 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12149 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
12150 vdisplay_max = 4096;
12153 } else if (INTEL_GEN(dev_priv) >= 3) {
12154 hdisplay_max = 4096;
12155 vdisplay_max = 4096;
12159 hdisplay_max = 2048;
12160 vdisplay_max = 2048;
12165 if (mode->hdisplay > hdisplay_max ||
12166 mode->hsync_start > htotal_max ||
12167 mode->hsync_end > htotal_max ||
12168 mode->htotal > htotal_max)
12169 return MODE_H_ILLEGAL;
12171 if (mode->vdisplay > vdisplay_max ||
12172 mode->vsync_start > vtotal_max ||
12173 mode->vsync_end > vtotal_max ||
12174 mode->vtotal > vtotal_max)
12175 return MODE_V_ILLEGAL;
12177 if (INTEL_GEN(dev_priv) >= 5) {
12178 if (mode->hdisplay < 64 ||
12179 mode->htotal - mode->hdisplay < 32)
12180 return MODE_H_ILLEGAL;
12182 if (mode->vtotal - mode->vdisplay < 5)
12183 return MODE_V_ILLEGAL;
12185 if (mode->htotal - mode->hdisplay < 32)
12186 return MODE_H_ILLEGAL;
12188 if (mode->vtotal - mode->vdisplay < 3)
12189 return MODE_V_ILLEGAL;
12195 enum drm_mode_status
12196 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
12197 const struct drm_display_mode *mode,
12200 int plane_width_max, plane_height_max;
12203 * intel_mode_valid() should be
12204 * sufficient on older platforms.
12206 if (INTEL_GEN(dev_priv) < 9)
12210 * Most people will probably want a fullscreen
12211 * plane so let's not advertize modes that are
12212 * too big for that.
12214 if (INTEL_GEN(dev_priv) >= 11) {
12215 plane_width_max = 5120 << bigjoiner;
12216 plane_height_max = 4320;
12218 plane_width_max = 5120;
12219 plane_height_max = 4096;
12222 if (mode->hdisplay > plane_width_max)
12223 return MODE_H_ILLEGAL;
12225 if (mode->vdisplay > plane_height_max)
12226 return MODE_V_ILLEGAL;
12231 static const struct drm_mode_config_funcs intel_mode_funcs = {
12232 .fb_create = intel_user_framebuffer_create,
12233 .get_format_info = intel_get_format_info,
12234 .output_poll_changed = intel_fbdev_output_poll_changed,
12235 .mode_valid = intel_mode_valid,
12236 .atomic_check = intel_atomic_check,
12237 .atomic_commit = intel_atomic_commit,
12238 .atomic_state_alloc = intel_atomic_state_alloc,
12239 .atomic_state_clear = intel_atomic_state_clear,
12240 .atomic_state_free = intel_atomic_state_free,
12244 * intel_init_display_hooks - initialize the display modesetting hooks
12245 * @dev_priv: device private
12247 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
12249 intel_init_cdclk_hooks(dev_priv);
12250 intel_init_audio_hooks(dev_priv);
12252 intel_dpll_init_clock_hook(dev_priv);
12254 if (INTEL_GEN(dev_priv) >= 9) {
12255 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
12256 dev_priv->display.crtc_enable = hsw_crtc_enable;
12257 dev_priv->display.crtc_disable = hsw_crtc_disable;
12258 } else if (HAS_DDI(dev_priv)) {
12259 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
12260 dev_priv->display.crtc_enable = hsw_crtc_enable;
12261 dev_priv->display.crtc_disable = hsw_crtc_disable;
12262 } else if (HAS_PCH_SPLIT(dev_priv)) {
12263 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
12264 dev_priv->display.crtc_enable = ilk_crtc_enable;
12265 dev_priv->display.crtc_disable = ilk_crtc_disable;
12266 } else if (IS_CHERRYVIEW(dev_priv) ||
12267 IS_VALLEYVIEW(dev_priv)) {
12268 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12269 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12270 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12272 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12273 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12274 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12277 intel_fdi_init_hook(dev_priv);
12279 if (INTEL_GEN(dev_priv) >= 9) {
12280 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
12281 dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
12283 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
12284 dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
12289 void intel_modeset_init_hw(struct drm_i915_private *i915)
12291 struct intel_cdclk_state *cdclk_state =
12292 to_intel_cdclk_state(i915->cdclk.obj.state);
12294 intel_update_cdclk(i915);
12295 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
12296 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
12299 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
12301 struct drm_plane *plane;
12302 struct intel_crtc *crtc;
12304 for_each_intel_crtc(state->dev, crtc) {
12305 struct intel_crtc_state *crtc_state;
12307 crtc_state = intel_atomic_get_crtc_state(state, crtc);
12308 if (IS_ERR(crtc_state))
12309 return PTR_ERR(crtc_state);
12311 if (crtc_state->hw.active) {
12313 * Preserve the inherited flag to avoid
12314 * taking the full modeset path.
12316 crtc_state->inherited = true;
12320 drm_for_each_plane(plane, state->dev) {
12321 struct drm_plane_state *plane_state;
12323 plane_state = drm_atomic_get_plane_state(state, plane);
12324 if (IS_ERR(plane_state))
12325 return PTR_ERR(plane_state);
12332 * Calculate what we think the watermarks should be for the state we've read
12333 * out of the hardware and then immediately program those watermarks so that
12334 * we ensure the hardware settings match our internal state.
12336 * We can calculate what we think WM's should be by creating a duplicate of the
12337 * current state (which was constructed during hardware readout) and running it
12338 * through the atomic check code to calculate new watermark values in the
12341 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
12343 struct drm_atomic_state *state;
12344 struct intel_atomic_state *intel_state;
12345 struct intel_crtc *crtc;
12346 struct intel_crtc_state *crtc_state;
12347 struct drm_modeset_acquire_ctx ctx;
12351 /* Only supported on platforms that use atomic watermark design */
12352 if (!dev_priv->display.optimize_watermarks)
12355 state = drm_atomic_state_alloc(&dev_priv->drm);
12356 if (drm_WARN_ON(&dev_priv->drm, !state))
12359 intel_state = to_intel_atomic_state(state);
12361 drm_modeset_acquire_init(&ctx, 0);
12364 state->acquire_ctx = &ctx;
12367 * Hardware readout is the only time we don't want to calculate
12368 * intermediate watermarks (since we don't trust the current
12371 if (!HAS_GMCH(dev_priv))
12372 intel_state->skip_intermediate_wm = true;
12374 ret = sanitize_watermarks_add_affected(state);
12378 ret = intel_atomic_check(&dev_priv->drm, state);
12382 /* Write calculated watermark values back */
12383 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
12384 crtc_state->wm.need_postvbl_update = true;
12385 dev_priv->display.optimize_watermarks(intel_state, crtc);
12387 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
12391 if (ret == -EDEADLK) {
12392 drm_atomic_state_clear(state);
12393 drm_modeset_backoff(&ctx);
12398 * If we fail here, it means that the hardware appears to be
12399 * programmed in a way that shouldn't be possible, given our
12400 * understanding of watermark requirements. This might mean a
12401 * mistake in the hardware readout code or a mistake in the
12402 * watermark calculations for a given platform. Raise a WARN
12403 * so that this is noticeable.
12405 * If this actually happens, we'll have to just leave the
12406 * BIOS-programmed watermarks untouched and hope for the best.
12408 drm_WARN(&dev_priv->drm, ret,
12409 "Could not determine valid watermarks for inherited state\n");
12411 drm_atomic_state_put(state);
12413 drm_modeset_drop_locks(&ctx);
12414 drm_modeset_acquire_fini(&ctx);
12417 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
12419 if (IS_GEN(dev_priv, 5)) {
12421 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
12423 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
12424 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
12425 dev_priv->fdi_pll_freq = 270000;
12430 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
12433 static int intel_initial_commit(struct drm_device *dev)
12435 struct drm_atomic_state *state = NULL;
12436 struct drm_modeset_acquire_ctx ctx;
12437 struct intel_crtc *crtc;
12440 state = drm_atomic_state_alloc(dev);
12444 drm_modeset_acquire_init(&ctx, 0);
12447 state->acquire_ctx = &ctx;
12449 for_each_intel_crtc(dev, crtc) {
12450 struct intel_crtc_state *crtc_state =
12451 intel_atomic_get_crtc_state(state, crtc);
12453 if (IS_ERR(crtc_state)) {
12454 ret = PTR_ERR(crtc_state);
12458 if (crtc_state->hw.active) {
12459 struct intel_encoder *encoder;
12462 * We've not yet detected sink capabilities
12463 * (audio,infoframes,etc.) and thus we don't want to
12464 * force a full state recomputation yet. We want that to
12465 * happen only for the first real commit from userspace.
12466 * So preserve the inherited flag for the time being.
12468 crtc_state->inherited = true;
12470 ret = drm_atomic_add_affected_planes(state, &crtc->base);
12475 * FIXME hack to force a LUT update to avoid the
12476 * plane update forcing the pipe gamma on without
12477 * having a proper LUT loaded. Remove once we
12478 * have readout for pipe gamma enable.
12480 crtc_state->uapi.color_mgmt_changed = true;
12482 for_each_intel_encoder_mask(dev, encoder,
12483 crtc_state->uapi.encoder_mask) {
12484 if (encoder->initial_fastset_check &&
12485 !encoder->initial_fastset_check(encoder, crtc_state)) {
12486 ret = drm_atomic_add_affected_connectors(state,
12495 ret = drm_atomic_commit(state);
12498 if (ret == -EDEADLK) {
12499 drm_atomic_state_clear(state);
12500 drm_modeset_backoff(&ctx);
12504 drm_atomic_state_put(state);
12506 drm_modeset_drop_locks(&ctx);
12507 drm_modeset_acquire_fini(&ctx);
12512 static void intel_mode_config_init(struct drm_i915_private *i915)
12514 struct drm_mode_config *mode_config = &i915->drm.mode_config;
12516 drm_mode_config_init(&i915->drm);
12517 INIT_LIST_HEAD(&i915->global_obj_list);
12519 mode_config->min_width = 0;
12520 mode_config->min_height = 0;
12522 mode_config->preferred_depth = 24;
12523 mode_config->prefer_shadow = 1;
12525 mode_config->allow_fb_modifiers = true;
12527 mode_config->funcs = &intel_mode_funcs;
12529 mode_config->async_page_flip = has_async_flips(i915);
12532 * Maximum framebuffer dimensions, chosen to match
12533 * the maximum render engine surface size on gen4+.
12535 if (INTEL_GEN(i915) >= 7) {
12536 mode_config->max_width = 16384;
12537 mode_config->max_height = 16384;
12538 } else if (INTEL_GEN(i915) >= 4) {
12539 mode_config->max_width = 8192;
12540 mode_config->max_height = 8192;
12541 } else if (IS_GEN(i915, 3)) {
12542 mode_config->max_width = 4096;
12543 mode_config->max_height = 4096;
12545 mode_config->max_width = 2048;
12546 mode_config->max_height = 2048;
12549 if (IS_I845G(i915) || IS_I865G(i915)) {
12550 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
12551 mode_config->cursor_height = 1023;
12552 } else if (IS_I830(i915) || IS_I85X(i915) ||
12553 IS_I915G(i915) || IS_I915GM(i915)) {
12554 mode_config->cursor_width = 64;
12555 mode_config->cursor_height = 64;
12557 mode_config->cursor_width = 256;
12558 mode_config->cursor_height = 256;
12562 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
12564 intel_atomic_global_obj_cleanup(i915);
12565 drm_mode_config_cleanup(&i915->drm);
12568 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
12570 if (plane_config->fb) {
12571 struct drm_framebuffer *fb = &plane_config->fb->base;
12573 /* We may only have the stub and not a full framebuffer */
12574 if (drm_framebuffer_read_refcount(fb))
12575 drm_framebuffer_put(fb);
12580 if (plane_config->vma)
12581 i915_vma_put(plane_config->vma);
12584 /* part #1: call before irq install */
12585 int intel_modeset_init_noirq(struct drm_i915_private *i915)
12589 if (i915_inject_probe_failure(i915))
12592 if (HAS_DISPLAY(i915)) {
12593 ret = drm_vblank_init(&i915->drm,
12594 INTEL_NUM_PIPES(i915));
12599 intel_bios_init(i915);
12601 ret = intel_vga_register(i915);
12605 /* FIXME: completely on the wrong abstraction layer */
12606 intel_power_domains_init_hw(i915, false);
12608 intel_csr_ucode_init(i915);
12610 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
12611 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
12612 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
12614 i915->framestart_delay = 1; /* 1-4 */
12616 intel_mode_config_init(i915);
12618 ret = intel_cdclk_init(i915);
12620 goto cleanup_vga_client_pw_domain_csr;
12622 ret = intel_dbuf_init(i915);
12624 goto cleanup_vga_client_pw_domain_csr;
12626 ret = intel_bw_init(i915);
12628 goto cleanup_vga_client_pw_domain_csr;
12630 init_llist_head(&i915->atomic_helper.free_list);
12631 INIT_WORK(&i915->atomic_helper.free_work,
12632 intel_atomic_helper_free_state_worker);
12634 intel_init_quirks(i915);
12636 intel_fbc_init(i915);
12640 cleanup_vga_client_pw_domain_csr:
12641 intel_csr_ucode_fini(i915);
12642 intel_power_domains_driver_remove(i915);
12643 intel_vga_unregister(i915);
12645 intel_bios_driver_remove(i915);
12650 /* part #2: call after irq install, but before gem init */
12651 int intel_modeset_init_nogem(struct drm_i915_private *i915)
12653 struct drm_device *dev = &i915->drm;
12655 struct intel_crtc *crtc;
12658 intel_init_pm(i915);
12660 intel_panel_sanitize_ssc(i915);
12662 intel_pps_setup(i915);
12664 intel_gmbus_setup(i915);
12666 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
12667 INTEL_NUM_PIPES(i915),
12668 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
12670 if (HAS_DISPLAY(i915)) {
12671 for_each_pipe(i915, pipe) {
12672 ret = intel_crtc_init(i915, pipe);
12674 intel_mode_config_cleanup(i915);
12680 intel_plane_possible_crtcs_init(i915);
12681 intel_shared_dpll_init(dev);
12682 intel_update_fdi_pll_freq(i915);
12684 intel_update_czclk(i915);
12685 intel_modeset_init_hw(i915);
12686 intel_dpll_update_ref_clks(i915);
12688 intel_hdcp_component_init(i915);
12690 if (i915->max_cdclk_freq == 0)
12691 intel_update_max_cdclk(i915);
12694 * If the platform has HTI, we need to find out whether it has reserved
12695 * any display resources before we create our display outputs.
12697 if (INTEL_INFO(i915)->display.has_hti)
12698 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
12700 /* Just disable it once at startup */
12701 intel_vga_disable(i915);
12702 intel_setup_outputs(i915);
12704 drm_modeset_lock_all(dev);
12705 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
12706 drm_modeset_unlock_all(dev);
12708 for_each_intel_crtc(dev, crtc) {
12709 struct intel_initial_plane_config plane_config = {};
12711 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
12715 * Note that reserving the BIOS fb up front prevents us
12716 * from stuffing other stolen allocations like the ring
12717 * on top. This prevents some ugliness at boot time, and
12718 * can even allow for smooth boot transitions if the BIOS
12719 * fb is large enough for the active pipe configuration.
12721 i915->display.get_initial_plane_config(crtc, &plane_config);
12724 * If the fb is shared between multiple heads, we'll
12725 * just get the first one.
12727 intel_find_initial_plane_obj(crtc, &plane_config);
12729 plane_config_fini(&plane_config);
12733 * Make sure hardware watermarks really match the state we read out.
12734 * Note that we need to do this after reconstructing the BIOS fb's
12735 * since the watermark calculation done here will use pstate->fb.
12737 if (!HAS_GMCH(i915))
12738 sanitize_watermarks(i915);
12743 /* part #3: call after gem init */
12744 int intel_modeset_init(struct drm_i915_private *i915)
12748 if (!HAS_DISPLAY(i915))
12752 * Force all active planes to recompute their states. So that on
12753 * mode_setcrtc after probe, all the intel_plane_state variables
12754 * are already calculated and there is no assert_plane warnings
12757 ret = intel_initial_commit(&i915->drm);
12759 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
12761 intel_overlay_setup(i915);
12763 ret = intel_fbdev_init(&i915->drm);
12767 /* Only enable hotplug handling once the fbdev is fully set up. */
12768 intel_hpd_init(i915);
12769 intel_hpd_poll_disable(i915);
12771 intel_init_ipc(i915);
12776 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12778 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12779 /* 640x480@60Hz, ~25175 kHz */
12780 struct dpll clock = {
12790 drm_WARN_ON(&dev_priv->drm,
12791 i9xx_calc_dpll_params(48000, &clock) != 25154);
12793 drm_dbg_kms(&dev_priv->drm,
12794 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
12795 pipe_name(pipe), clock.vco, clock.dot);
12797 fp = i9xx_dpll_compute_fp(&clock);
12798 dpll = DPLL_DVO_2X_MODE |
12799 DPLL_VGA_MODE_DIS |
12800 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
12801 PLL_P2_DIVIDE_BY_4 |
12802 PLL_REF_INPUT_DREFCLK |
12805 intel_de_write(dev_priv, FP0(pipe), fp);
12806 intel_de_write(dev_priv, FP1(pipe), fp);
12808 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
12809 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
12810 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
12811 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
12812 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
12813 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
12814 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
12817 * Apparently we need to have VGA mode enabled prior to changing
12818 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
12819 * dividers, even though the register value does change.
12821 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
12822 intel_de_write(dev_priv, DPLL(pipe), dpll);
12824 /* Wait for the clocks to stabilize. */
12825 intel_de_posting_read(dev_priv, DPLL(pipe));
12828 /* The pixel multiplier can only be updated once the
12829 * DPLL is enabled and the clocks are stable.
12831 * So write it again.
12833 intel_de_write(dev_priv, DPLL(pipe), dpll);
12835 /* We do this three times for luck */
12836 for (i = 0; i < 3 ; i++) {
12837 intel_de_write(dev_priv, DPLL(pipe), dpll);
12838 intel_de_posting_read(dev_priv, DPLL(pipe));
12839 udelay(150); /* wait for warmup */
12842 intel_de_write(dev_priv, PIPECONF(pipe),
12843 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
12844 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12846 intel_wait_for_pipe_scanline_moving(crtc);
12849 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12851 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12853 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
12856 drm_WARN_ON(&dev_priv->drm,
12857 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
12858 DISPLAY_PLANE_ENABLE);
12859 drm_WARN_ON(&dev_priv->drm,
12860 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
12861 DISPLAY_PLANE_ENABLE);
12862 drm_WARN_ON(&dev_priv->drm,
12863 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
12864 DISPLAY_PLANE_ENABLE);
12865 drm_WARN_ON(&dev_priv->drm,
12866 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
12867 drm_WARN_ON(&dev_priv->drm,
12868 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
12870 intel_de_write(dev_priv, PIPECONF(pipe), 0);
12871 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12873 intel_wait_for_pipe_scanline_stopped(crtc);
12875 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
12876 intel_de_posting_read(dev_priv, DPLL(pipe));
12880 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
12882 struct intel_crtc *crtc;
12884 if (INTEL_GEN(dev_priv) >= 4)
12887 for_each_intel_crtc(&dev_priv->drm, crtc) {
12888 struct intel_plane *plane =
12889 to_intel_plane(crtc->base.primary);
12890 struct intel_crtc *plane_crtc;
12893 if (!plane->get_hw_state(plane, &pipe))
12896 if (pipe == crtc->pipe)
12899 drm_dbg_kms(&dev_priv->drm,
12900 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
12901 plane->base.base.id, plane->base.name);
12903 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12904 intel_plane_disable_noatomic(plane_crtc, plane);
12908 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
12910 struct drm_device *dev = crtc->base.dev;
12911 struct intel_encoder *encoder;
12913 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
12919 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
12921 struct drm_device *dev = encoder->base.dev;
12922 struct intel_connector *connector;
12924 for_each_connector_on_encoder(dev, &encoder->base, connector)
12930 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
12931 enum pipe pch_transcoder)
12933 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
12934 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
12937 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
12939 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12940 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12941 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
12943 if (INTEL_GEN(dev_priv) >= 9 ||
12944 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12945 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
12948 if (transcoder_is_dsi(cpu_transcoder))
12951 val = intel_de_read(dev_priv, reg);
12952 val &= ~HSW_FRAME_START_DELAY_MASK;
12953 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12954 intel_de_write(dev_priv, reg, val);
12956 i915_reg_t reg = PIPECONF(cpu_transcoder);
12959 val = intel_de_read(dev_priv, reg);
12960 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
12961 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12962 intel_de_write(dev_priv, reg, val);
12965 if (!crtc_state->has_pch_encoder)
12968 if (HAS_PCH_IBX(dev_priv)) {
12969 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
12972 val = intel_de_read(dev_priv, reg);
12973 val &= ~TRANS_FRAME_START_DELAY_MASK;
12974 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12975 intel_de_write(dev_priv, reg, val);
12977 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
12978 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
12981 val = intel_de_read(dev_priv, reg);
12982 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
12983 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12984 intel_de_write(dev_priv, reg, val);
12988 static void intel_sanitize_crtc(struct intel_crtc *crtc,
12989 struct drm_modeset_acquire_ctx *ctx)
12991 struct drm_device *dev = crtc->base.dev;
12992 struct drm_i915_private *dev_priv = to_i915(dev);
12993 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
12995 if (crtc_state->hw.active) {
12996 struct intel_plane *plane;
12998 /* Clear any frame start delays used for debugging left by the BIOS */
12999 intel_sanitize_frame_start_delay(crtc_state);
13001 /* Disable everything but the primary plane */
13002 for_each_intel_plane_on_crtc(dev, crtc, plane) {
13003 const struct intel_plane_state *plane_state =
13004 to_intel_plane_state(plane->base.state);
13006 if (plane_state->uapi.visible &&
13007 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
13008 intel_plane_disable_noatomic(crtc, plane);
13012 * Disable any background color set by the BIOS, but enable the
13013 * gamma and CSC to match how we program our planes.
13015 if (INTEL_GEN(dev_priv) >= 9)
13016 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
13017 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
13020 /* Adjust the state of the output pipe according to whether we
13021 * have active connectors/encoders. */
13022 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
13023 !crtc_state->bigjoiner_slave)
13024 intel_crtc_disable_noatomic(crtc, ctx);
13026 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
13028 * We start out with underrun reporting disabled to avoid races.
13029 * For correct bookkeeping mark this on active crtcs.
13031 * Also on gmch platforms we dont have any hardware bits to
13032 * disable the underrun reporting. Which means we need to start
13033 * out with underrun reporting disabled also on inactive pipes,
13034 * since otherwise we'll complain about the garbage we read when
13035 * e.g. coming up after runtime pm.
13037 * No protection against concurrent access is required - at
13038 * worst a fifo underrun happens which also sets this to false.
13040 crtc->cpu_fifo_underrun_disabled = true;
13042 * We track the PCH trancoder underrun reporting state
13043 * within the crtc. With crtc for pipe A housing the underrun
13044 * reporting state for PCH transcoder A, crtc for pipe B housing
13045 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
13046 * and marking underrun reporting as disabled for the non-existing
13047 * PCH transcoders B and C would prevent enabling the south
13048 * error interrupt (see cpt_can_enable_serr_int()).
13050 if (has_pch_trancoder(dev_priv, crtc->pipe))
13051 crtc->pch_fifo_underrun_disabled = true;
13055 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
13057 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
13060 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
13061 * the hardware when a high res displays plugged in. DPLL P
13062 * divider is zero, and the pipe timings are bonkers. We'll
13063 * try to disable everything in that case.
13065 * FIXME would be nice to be able to sanitize this state
13066 * without several WARNs, but for now let's take the easy
13069 return IS_GEN(dev_priv, 6) &&
13070 crtc_state->hw.active &&
13071 crtc_state->shared_dpll &&
13072 crtc_state->port_clock == 0;
13075 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
13078 struct intel_connector *connector;
13079 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
13080 struct intel_crtc_state *crtc_state = crtc ?
13081 to_intel_crtc_state(crtc->base.state) : NULL;
13083 /* We need to check both for a crtc link (meaning that the
13084 * encoder is active and trying to read from a pipe) and the
13085 * pipe itself being active. */
13086 bool has_active_crtc = crtc_state &&
13087 crtc_state->hw.active;
13089 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
13090 drm_dbg_kms(&dev_priv->drm,
13091 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
13092 pipe_name(crtc->pipe));
13093 has_active_crtc = false;
13096 connector = intel_encoder_find_connector(encoder);
13097 if (connector && !has_active_crtc) {
13098 drm_dbg_kms(&dev_priv->drm,
13099 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13100 encoder->base.base.id,
13101 encoder->base.name);
13103 /* Connector is active, but has no active pipe. This is
13104 * fallout from our resume register restoring. Disable
13105 * the encoder manually again. */
13107 struct drm_encoder *best_encoder;
13109 drm_dbg_kms(&dev_priv->drm,
13110 "[ENCODER:%d:%s] manually disabled\n",
13111 encoder->base.base.id,
13112 encoder->base.name);
13114 /* avoid oopsing in case the hooks consult best_encoder */
13115 best_encoder = connector->base.state->best_encoder;
13116 connector->base.state->best_encoder = &encoder->base;
13118 /* FIXME NULL atomic state passed! */
13119 if (encoder->disable)
13120 encoder->disable(NULL, encoder, crtc_state,
13121 connector->base.state);
13122 if (encoder->post_disable)
13123 encoder->post_disable(NULL, encoder, crtc_state,
13124 connector->base.state);
13126 connector->base.state->best_encoder = best_encoder;
13128 encoder->base.crtc = NULL;
13130 /* Inconsistent output/port/pipe state happens presumably due to
13131 * a bug in one of the get_hw_state functions. Or someplace else
13132 * in our code, like the register restore mess on resume. Clamp
13133 * things to off as a safer default. */
13135 connector->base.dpms = DRM_MODE_DPMS_OFF;
13136 connector->base.encoder = NULL;
13139 /* notify opregion of the sanitized encoder state */
13140 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
13142 if (HAS_DDI(dev_priv))
13143 intel_ddi_sanitize_encoder_pll_mapping(encoder);
13146 /* FIXME read out full plane state for all planes */
13147 static void readout_plane_state(struct drm_i915_private *dev_priv)
13149 struct intel_plane *plane;
13150 struct intel_crtc *crtc;
13152 for_each_intel_plane(&dev_priv->drm, plane) {
13153 struct intel_plane_state *plane_state =
13154 to_intel_plane_state(plane->base.state);
13155 struct intel_crtc_state *crtc_state;
13156 enum pipe pipe = PIPE_A;
13159 visible = plane->get_hw_state(plane, &pipe);
13161 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
13162 crtc_state = to_intel_crtc_state(crtc->base.state);
13164 intel_set_plane_visible(crtc_state, plane_state, visible);
13166 drm_dbg_kms(&dev_priv->drm,
13167 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
13168 plane->base.base.id, plane->base.name,
13169 enableddisabled(visible), pipe_name(pipe));
13172 for_each_intel_crtc(&dev_priv->drm, crtc) {
13173 struct intel_crtc_state *crtc_state =
13174 to_intel_crtc_state(crtc->base.state);
13176 fixup_plane_bitmasks(crtc_state);
13180 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13182 struct drm_i915_private *dev_priv = to_i915(dev);
13183 struct intel_cdclk_state *cdclk_state =
13184 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
13185 struct intel_dbuf_state *dbuf_state =
13186 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
13188 struct intel_crtc *crtc;
13189 struct intel_encoder *encoder;
13190 struct intel_connector *connector;
13191 struct drm_connector_list_iter conn_iter;
13192 u8 active_pipes = 0;
13194 for_each_intel_crtc(dev, crtc) {
13195 struct intel_crtc_state *crtc_state =
13196 to_intel_crtc_state(crtc->base.state);
13198 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
13199 intel_crtc_free_hw_state(crtc_state);
13200 intel_crtc_state_reset(crtc_state, crtc);
13202 intel_crtc_get_pipe_config(crtc_state);
13204 crtc_state->hw.enable = crtc_state->hw.active;
13206 crtc->base.enabled = crtc_state->hw.enable;
13207 crtc->active = crtc_state->hw.active;
13209 if (crtc_state->hw.active)
13210 active_pipes |= BIT(crtc->pipe);
13212 drm_dbg_kms(&dev_priv->drm,
13213 "[CRTC:%d:%s] hw state readout: %s\n",
13214 crtc->base.base.id, crtc->base.name,
13215 enableddisabled(crtc_state->hw.active));
13218 dev_priv->active_pipes = cdclk_state->active_pipes =
13219 dbuf_state->active_pipes = active_pipes;
13221 readout_plane_state(dev_priv);
13223 for_each_intel_encoder(dev, encoder) {
13226 if (encoder->get_hw_state(encoder, &pipe)) {
13227 struct intel_crtc_state *crtc_state;
13229 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
13230 crtc_state = to_intel_crtc_state(crtc->base.state);
13232 encoder->base.crtc = &crtc->base;
13233 intel_encoder_get_config(encoder, crtc_state);
13234 if (encoder->sync_state)
13235 encoder->sync_state(encoder, crtc_state);
13237 /* read out to slave crtc as well for bigjoiner */
13238 if (crtc_state->bigjoiner) {
13239 /* encoder should read be linked to bigjoiner master */
13240 WARN_ON(crtc_state->bigjoiner_slave);
13242 crtc = crtc_state->bigjoiner_linked_crtc;
13243 crtc_state = to_intel_crtc_state(crtc->base.state);
13244 intel_encoder_get_config(encoder, crtc_state);
13247 encoder->base.crtc = NULL;
13250 drm_dbg_kms(&dev_priv->drm,
13251 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13252 encoder->base.base.id, encoder->base.name,
13253 enableddisabled(encoder->base.crtc),
13257 intel_dpll_readout_hw_state(dev_priv);
13259 drm_connector_list_iter_begin(dev, &conn_iter);
13260 for_each_intel_connector_iter(connector, &conn_iter) {
13261 if (connector->get_hw_state(connector)) {
13262 struct intel_crtc_state *crtc_state;
13263 struct intel_crtc *crtc;
13265 connector->base.dpms = DRM_MODE_DPMS_ON;
13267 encoder = intel_attached_encoder(connector);
13268 connector->base.encoder = &encoder->base;
13270 crtc = to_intel_crtc(encoder->base.crtc);
13271 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
13273 if (crtc_state && crtc_state->hw.active) {
13275 * This has to be done during hardware readout
13276 * because anything calling .crtc_disable may
13277 * rely on the connector_mask being accurate.
13279 crtc_state->uapi.connector_mask |=
13280 drm_connector_mask(&connector->base);
13281 crtc_state->uapi.encoder_mask |=
13282 drm_encoder_mask(&encoder->base);
13285 connector->base.dpms = DRM_MODE_DPMS_OFF;
13286 connector->base.encoder = NULL;
13288 drm_dbg_kms(&dev_priv->drm,
13289 "[CONNECTOR:%d:%s] hw state readout: %s\n",
13290 connector->base.base.id, connector->base.name,
13291 enableddisabled(connector->base.encoder));
13293 drm_connector_list_iter_end(&conn_iter);
13295 for_each_intel_crtc(dev, crtc) {
13296 struct intel_bw_state *bw_state =
13297 to_intel_bw_state(dev_priv->bw_obj.state);
13298 struct intel_crtc_state *crtc_state =
13299 to_intel_crtc_state(crtc->base.state);
13300 struct intel_plane *plane;
13303 if (crtc_state->bigjoiner_slave)
13306 if (crtc_state->hw.active) {
13308 * The initial mode needs to be set in order to keep
13309 * the atomic core happy. It wants a valid mode if the
13310 * crtc's enabled, so we do the above call.
13312 * But we don't set all the derived state fully, hence
13313 * set a flag to indicate that a full recalculation is
13314 * needed on the next commit.
13316 crtc_state->inherited = true;
13318 intel_crtc_update_active_timings(crtc_state);
13320 intel_crtc_copy_hw_to_uapi_state(crtc_state);
13323 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13324 const struct intel_plane_state *plane_state =
13325 to_intel_plane_state(plane->base.state);
13328 * FIXME don't have the fb yet, so can't
13329 * use intel_plane_data_rate() :(
13331 if (plane_state->uapi.visible)
13332 crtc_state->data_rate[plane->id] =
13333 4 * crtc_state->pixel_rate;
13335 * FIXME don't have the fb yet, so can't
13336 * use plane->min_cdclk() :(
13338 if (plane_state->uapi.visible && plane->min_cdclk) {
13339 if (crtc_state->double_wide ||
13340 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13341 crtc_state->min_cdclk[plane->id] =
13342 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
13344 crtc_state->min_cdclk[plane->id] =
13345 crtc_state->pixel_rate;
13347 drm_dbg_kms(&dev_priv->drm,
13348 "[PLANE:%d:%s] min_cdclk %d kHz\n",
13349 plane->base.base.id, plane->base.name,
13350 crtc_state->min_cdclk[plane->id]);
13353 if (crtc_state->hw.active) {
13354 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
13355 if (drm_WARN_ON(dev, min_cdclk < 0))
13359 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
13360 cdclk_state->min_voltage_level[crtc->pipe] =
13361 crtc_state->min_voltage_level;
13363 intel_bw_crtc_update(bw_state, crtc_state);
13365 intel_pipe_config_sanity_check(dev_priv, crtc_state);
13367 /* discard our incomplete slave state, copy it from master */
13368 if (crtc_state->bigjoiner && crtc_state->hw.active) {
13369 struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
13370 struct intel_crtc_state *slave_crtc_state =
13371 to_intel_crtc_state(slave->base.state);
13373 copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
13374 slave->base.mode = crtc->base.mode;
13376 cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
13377 cdclk_state->min_voltage_level[slave->pipe] =
13378 crtc_state->min_voltage_level;
13380 for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
13381 const struct intel_plane_state *plane_state =
13382 to_intel_plane_state(plane->base.state);
13385 * FIXME don't have the fb yet, so can't
13386 * use intel_plane_data_rate() :(
13388 if (plane_state->uapi.visible)
13389 crtc_state->data_rate[plane->id] =
13390 4 * crtc_state->pixel_rate;
13392 crtc_state->data_rate[plane->id] = 0;
13395 intel_bw_crtc_update(bw_state, slave_crtc_state);
13396 drm_calc_timestamping_constants(&slave->base,
13397 &slave_crtc_state->hw.adjusted_mode);
13403 get_encoder_power_domains(struct drm_i915_private *dev_priv)
13405 struct intel_encoder *encoder;
13407 for_each_intel_encoder(&dev_priv->drm, encoder) {
13408 struct intel_crtc_state *crtc_state;
13410 if (!encoder->get_power_domains)
13414 * MST-primary and inactive encoders don't have a crtc state
13415 * and neither of these require any power domain references.
13417 if (!encoder->base.crtc)
13420 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
13421 encoder->get_power_domains(encoder, crtc_state);
13425 static void intel_early_display_was(struct drm_i915_private *dev_priv)
13428 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
13429 * Also known as Wa_14010480278.
13431 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
13432 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
13433 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
13435 if (IS_HASWELL(dev_priv)) {
13437 * WaRsPkgCStateDisplayPMReq:hsw
13438 * System hang if this isn't done before disabling all planes!
13440 intel_de_write(dev_priv, CHICKEN_PAR1_1,
13441 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
13444 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
13445 /* Display WA #1142:kbl,cfl,cml */
13446 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
13447 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
13448 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
13449 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
13450 KBL_ARB_FILL_SPARE_14);
13454 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
13455 enum port port, i915_reg_t hdmi_reg)
13457 u32 val = intel_de_read(dev_priv, hdmi_reg);
13459 if (val & SDVO_ENABLE ||
13460 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
13463 drm_dbg_kms(&dev_priv->drm,
13464 "Sanitizing transcoder select for HDMI %c\n",
13467 val &= ~SDVO_PIPE_SEL_MASK;
13468 val |= SDVO_PIPE_SEL(PIPE_A);
13470 intel_de_write(dev_priv, hdmi_reg, val);
13473 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
13474 enum port port, i915_reg_t dp_reg)
13476 u32 val = intel_de_read(dev_priv, dp_reg);
13478 if (val & DP_PORT_EN ||
13479 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
13482 drm_dbg_kms(&dev_priv->drm,
13483 "Sanitizing transcoder select for DP %c\n",
13486 val &= ~DP_PIPE_SEL_MASK;
13487 val |= DP_PIPE_SEL(PIPE_A);
13489 intel_de_write(dev_priv, dp_reg, val);
13492 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
13495 * The BIOS may select transcoder B on some of the PCH
13496 * ports even it doesn't enable the port. This would trip
13497 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
13498 * Sanitize the transcoder select bits to prevent that. We
13499 * assume that the BIOS never actually enabled the port,
13500 * because if it did we'd actually have to toggle the port
13501 * on and back off to make the transcoder A select stick
13502 * (see. intel_dp_link_down(), intel_disable_hdmi(),
13503 * intel_disable_sdvo()).
13505 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
13506 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
13507 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
13509 /* PCH SDVOB multiplex with HDMIB */
13510 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
13511 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
13512 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
13515 /* Scan out the current hw modeset state,
13516 * and sanitizes it to the current state
13519 intel_modeset_setup_hw_state(struct drm_device *dev,
13520 struct drm_modeset_acquire_ctx *ctx)
13522 struct drm_i915_private *dev_priv = to_i915(dev);
13523 struct intel_encoder *encoder;
13524 struct intel_crtc *crtc;
13525 intel_wakeref_t wakeref;
13527 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
13529 intel_early_display_was(dev_priv);
13530 intel_modeset_readout_hw_state(dev);
13532 /* HW state is read out, now we need to sanitize this mess. */
13534 /* Sanitize the TypeC port mode upfront, encoders depend on this */
13535 for_each_intel_encoder(dev, encoder) {
13536 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
13538 /* We need to sanitize only the MST primary port. */
13539 if (encoder->type != INTEL_OUTPUT_DP_MST &&
13540 intel_phy_is_tc(dev_priv, phy))
13541 intel_tc_port_sanitize(enc_to_dig_port(encoder));
13544 get_encoder_power_domains(dev_priv);
13546 if (HAS_PCH_IBX(dev_priv))
13547 ibx_sanitize_pch_ports(dev_priv);
13550 * intel_sanitize_plane_mapping() may need to do vblank
13551 * waits, so we need vblank interrupts restored beforehand.
13553 for_each_intel_crtc(&dev_priv->drm, crtc) {
13554 struct intel_crtc_state *crtc_state =
13555 to_intel_crtc_state(crtc->base.state);
13557 drm_crtc_vblank_reset(&crtc->base);
13559 if (crtc_state->hw.active)
13560 intel_crtc_vblank_on(crtc_state);
13563 intel_sanitize_plane_mapping(dev_priv);
13565 for_each_intel_encoder(dev, encoder)
13566 intel_sanitize_encoder(encoder);
13568 for_each_intel_crtc(&dev_priv->drm, crtc) {
13569 struct intel_crtc_state *crtc_state =
13570 to_intel_crtc_state(crtc->base.state);
13572 intel_sanitize_crtc(crtc, ctx);
13573 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
13576 intel_modeset_update_connector_atomic_state(dev);
13578 intel_dpll_sanitize_state(dev_priv);
13580 if (IS_G4X(dev_priv)) {
13581 g4x_wm_get_hw_state(dev_priv);
13582 g4x_wm_sanitize(dev_priv);
13583 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13584 vlv_wm_get_hw_state(dev_priv);
13585 vlv_wm_sanitize(dev_priv);
13586 } else if (INTEL_GEN(dev_priv) >= 9) {
13587 skl_wm_get_hw_state(dev_priv);
13588 } else if (HAS_PCH_SPLIT(dev_priv)) {
13589 ilk_wm_get_hw_state(dev_priv);
13592 for_each_intel_crtc(dev, crtc) {
13593 struct intel_crtc_state *crtc_state =
13594 to_intel_crtc_state(crtc->base.state);
13597 put_domains = modeset_get_crtc_power_domains(crtc_state);
13598 if (drm_WARN_ON(dev, put_domains))
13599 modeset_put_crtc_power_domains(crtc, put_domains);
13602 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
13605 void intel_display_resume(struct drm_device *dev)
13607 struct drm_i915_private *dev_priv = to_i915(dev);
13608 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
13609 struct drm_modeset_acquire_ctx ctx;
13612 dev_priv->modeset_restore_state = NULL;
13614 state->acquire_ctx = &ctx;
13616 drm_modeset_acquire_init(&ctx, 0);
13619 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13620 if (ret != -EDEADLK)
13623 drm_modeset_backoff(&ctx);
13627 ret = __intel_display_resume(dev, state, &ctx);
13629 intel_enable_ipc(dev_priv);
13630 drm_modeset_drop_locks(&ctx);
13631 drm_modeset_acquire_fini(&ctx);
13634 drm_err(&dev_priv->drm,
13635 "Restoring old state failed with %i\n", ret);
13637 drm_atomic_state_put(state);
13640 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
13642 struct intel_connector *connector;
13643 struct drm_connector_list_iter conn_iter;
13645 /* Kill all the work that may have been queued by hpd. */
13646 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
13647 for_each_intel_connector_iter(connector, &conn_iter) {
13648 if (connector->modeset_retry_work.func)
13649 cancel_work_sync(&connector->modeset_retry_work);
13650 if (connector->hdcp.shim) {
13651 cancel_delayed_work_sync(&connector->hdcp.check_work);
13652 cancel_work_sync(&connector->hdcp.prop_work);
13655 drm_connector_list_iter_end(&conn_iter);
13658 /* part #1: call before irq uninstall */
13659 void intel_modeset_driver_remove(struct drm_i915_private *i915)
13661 flush_workqueue(i915->flip_wq);
13662 flush_workqueue(i915->modeset_wq);
13664 flush_work(&i915->atomic_helper.free_work);
13665 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
13668 /* part #2: call after irq uninstall */
13669 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
13672 * Due to the hpd irq storm handling the hotplug work can re-arm the
13673 * poll handlers. Hence disable polling after hpd handling is shut down.
13675 intel_hpd_poll_fini(i915);
13678 * MST topology needs to be suspended so we don't have any calls to
13679 * fbdev after it's finalized. MST will be destroyed later as part of
13680 * drm_mode_config_cleanup()
13682 intel_dp_mst_suspend(i915);
13684 /* poll work can call into fbdev, hence clean that up afterwards */
13685 intel_fbdev_fini(i915);
13687 intel_unregister_dsm_handler();
13689 intel_fbc_global_disable(i915);
13691 /* flush any delayed tasks or pending work */
13692 flush_scheduled_work();
13694 intel_hdcp_component_fini(i915);
13696 intel_mode_config_cleanup(i915);
13698 intel_overlay_cleanup(i915);
13700 intel_gmbus_teardown(i915);
13702 destroy_workqueue(i915->flip_wq);
13703 destroy_workqueue(i915->modeset_wq);
13705 intel_fbc_cleanup_cfb(i915);
13708 /* part #3: call after gem init */
13709 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
13711 intel_csr_ucode_fini(i915);
13713 intel_power_domains_driver_remove(i915);
13715 intel_vga_unregister(i915);
13717 intel_bios_driver_remove(i915);
13720 void intel_display_driver_register(struct drm_i915_private *i915)
13722 if (!HAS_DISPLAY(i915))
13725 intel_display_debugfs_register(i915);
13727 /* Must be done after probing outputs */
13728 intel_opregion_register(i915);
13729 acpi_video_register();
13731 intel_audio_init(i915);
13734 * Some ports require correctly set-up hpd registers for
13735 * detection to work properly (leading to ghost connected
13736 * connector status), e.g. VGA on gm45. Hence we can only set
13737 * up the initial fbdev config after hpd irqs are fully
13738 * enabled. We do it last so that the async config cannot run
13739 * before the connectors are registered.
13741 intel_fbdev_initial_config_async(&i915->drm);
13744 * We need to coordinate the hotplugs with the asynchronous
13745 * fbdev configuration, for which we use the
13746 * fbdev->async_cookie.
13748 drm_kms_helper_poll_init(&i915->drm);
13751 void intel_display_driver_unregister(struct drm_i915_private *i915)
13753 if (!HAS_DISPLAY(i915))
13756 intel_fbdev_unregister(i915);
13757 intel_audio_deinit(i915);
13760 * After flushing the fbdev (incl. a late async config which
13761 * will have delayed queuing of a hotplug event), then flush
13762 * the hotplug events.
13764 drm_kms_helper_poll_fini(&i915->drm);
13765 drm_atomic_helper_shutdown(&i915->drm);
13767 acpi_video_unregister();
13768 intel_opregion_unregister(i915);
13771 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
13773 struct intel_display_error_state {
13775 u32 power_well_driver;
13777 struct intel_cursor_error_state {
13782 } cursor[I915_MAX_PIPES];
13784 struct intel_pipe_error_state {
13785 bool power_domain_on;
13788 } pipe[I915_MAX_PIPES];
13790 struct intel_plane_error_state {
13798 } plane[I915_MAX_PIPES];
13800 struct intel_transcoder_error_state {
13802 bool power_domain_on;
13803 enum transcoder cpu_transcoder;
13816 struct intel_display_error_state *
13817 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
13819 struct intel_display_error_state *error;
13820 int transcoders[] = {
13829 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
13831 if (!HAS_DISPLAY(dev_priv))
13834 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13838 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
13839 error->power_well_driver = intel_de_read(dev_priv,
13840 HSW_PWR_WELL_CTL2);
13842 for_each_pipe(dev_priv, i) {
13843 error->pipe[i].power_domain_on =
13844 __intel_display_power_is_enabled(dev_priv,
13845 POWER_DOMAIN_PIPE(i));
13846 if (!error->pipe[i].power_domain_on)
13849 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
13850 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
13851 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
13853 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
13854 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
13855 if (INTEL_GEN(dev_priv) <= 3) {
13856 error->plane[i].size = intel_de_read(dev_priv,
13858 error->plane[i].pos = intel_de_read(dev_priv,
13861 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
13862 error->plane[i].addr = intel_de_read(dev_priv,
13864 if (INTEL_GEN(dev_priv) >= 4) {
13865 error->plane[i].surface = intel_de_read(dev_priv,
13867 error->plane[i].tile_offset = intel_de_read(dev_priv,
13871 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
13873 if (HAS_GMCH(dev_priv))
13874 error->pipe[i].stat = intel_de_read(dev_priv,
13878 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
13879 enum transcoder cpu_transcoder = transcoders[i];
13881 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
13884 error->transcoder[i].available = true;
13885 error->transcoder[i].power_domain_on =
13886 __intel_display_power_is_enabled(dev_priv,
13887 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13888 if (!error->transcoder[i].power_domain_on)
13891 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13893 error->transcoder[i].conf = intel_de_read(dev_priv,
13894 PIPECONF(cpu_transcoder));
13895 error->transcoder[i].htotal = intel_de_read(dev_priv,
13896 HTOTAL(cpu_transcoder));
13897 error->transcoder[i].hblank = intel_de_read(dev_priv,
13898 HBLANK(cpu_transcoder));
13899 error->transcoder[i].hsync = intel_de_read(dev_priv,
13900 HSYNC(cpu_transcoder));
13901 error->transcoder[i].vtotal = intel_de_read(dev_priv,
13902 VTOTAL(cpu_transcoder));
13903 error->transcoder[i].vblank = intel_de_read(dev_priv,
13904 VBLANK(cpu_transcoder));
13905 error->transcoder[i].vsync = intel_de_read(dev_priv,
13906 VSYNC(cpu_transcoder));
13912 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13915 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13916 struct intel_display_error_state *error)
13918 struct drm_i915_private *dev_priv = m->i915;
13924 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
13925 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
13926 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13927 error->power_well_driver);
13928 for_each_pipe(dev_priv, i) {
13929 err_printf(m, "Pipe [%d]:\n", i);
13930 err_printf(m, " Power: %s\n",
13931 onoff(error->pipe[i].power_domain_on));
13932 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13933 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13935 err_printf(m, "Plane [%d]:\n", i);
13936 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13937 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13938 if (INTEL_GEN(dev_priv) <= 3) {
13939 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13940 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13942 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
13943 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13944 if (INTEL_GEN(dev_priv) >= 4) {
13945 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13946 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13949 err_printf(m, "Cursor [%d]:\n", i);
13950 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13951 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13952 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13955 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
13956 if (!error->transcoder[i].available)
13959 err_printf(m, "CPU transcoder: %s\n",
13960 transcoder_name(error->transcoder[i].cpu_transcoder));
13961 err_printf(m, " Power: %s\n",
13962 onoff(error->transcoder[i].power_domain_on));
13963 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13964 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13965 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13966 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13967 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13968 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13969 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);