drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_backlight.h"
  33 #include "intel_combo_phy.h"
  34 #include "intel_connector.h"
  35 #include "intel_crtc.h"
  36 #include "intel_ddi.h"
  37 #include "intel_ddi_buf_trans.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dp.h"
  41 #include "intel_dp_link_training.h"
  42 #include "intel_dp_mst.h"
  43 #include "intel_dpio_phy.h"
  44 #include "intel_drrs.h"
  45 #include "intel_dsi.h"
  46 #include "intel_fdi.h"
  47 #include "intel_fifo_underrun.h"
  48 #include "intel_gmbus.h"
  49 #include "intel_hdcp.h"
  50 #include "intel_hdmi.h"
  51 #include "intel_hotplug.h"
  52 #include "intel_lspcon.h"
  53 #include "intel_pps.h"
  54 #include "intel_psr.h"
  55 #include "intel_snps_phy.h"
  56 #include "intel_sprite.h"
  57 #include "intel_tc.h"
  58 #include "intel_vdsc.h"
  59 #include "intel_vrr.h"
  60 #include "skl_scaler.h"
  61 #include "skl_universal_plane.h"
  62
  63 static const u8 index_to_dp_signal_levels[] = {
  64         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  68         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  70         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  71         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  72         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  73         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  74 };
  75
  76 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  77                                 const struct intel_crtc_state *crtc_state)
  78 {
  79         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  80         int n_entries, level, default_entry;
  81
  82         n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry);
  83         if (n_entries == 0)
  84                 return 0;
  85         level = intel_bios_hdmi_level_shift(encoder);
  86         if (level < 0)
  87                 level = default_entry;
  88
  89         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
  90                 level = n_entries - 1;
  91
  92         return level;
  93 }
  94
  95 /*
  96  * Starting with Haswell, DDI port buffers must be programmed with correct
  97  * values in advance. This function programs the correct values for
  98  * DP/eDP/FDI use cases.
  99  */
 100 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 101                                 const struct intel_crtc_state *crtc_state)
 102 {
 103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 104         u32 iboost_bit = 0;
 105         int i, n_entries;
 106         enum port port = encoder->port;
 107         const struct intel_ddi_buf_trans *ddi_translations;
 108
 109         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 110         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 111                 return;
 112
 113         /* If we're boosting the current, set bit 31 of trans1 */
 114         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 115             intel_bios_encoder_dp_boost_level(encoder->devdata))
 116                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 117
 118         for (i = 0; i < n_entries; i++) {
 119                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 120                                ddi_translations->entries[i].hsw.trans1 | iboost_bit);
 121                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 122                                ddi_translations->entries[i].hsw.trans2);
 123         }
 124 }
 125
 126 /*
 127  * Starting with Haswell, DDI port buffers must be programmed with correct
 128  * values in advance. This function programs the correct values for
 129  * HDMI/DVI use cases.
 130  */
 131 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 132                                          const struct intel_crtc_state *crtc_state,
 133                                          int level)
 134 {
 135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 136         u32 iboost_bit = 0;
 137         int n_entries;
 138         enum port port = encoder->port;
 139         const struct intel_ddi_buf_trans *ddi_translations;
 140
 141         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 142         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 143                 return;
 144         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 145                 level = n_entries - 1;
 146
 147         /* If we're boosting the current, set bit 31 of trans1 */
 148         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 149             intel_bios_encoder_hdmi_boost_level(encoder->devdata))
 150                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 151
 152         /* Entry 9 is for HDMI: */
 153         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 154                        ddi_translations->entries[level].hsw.trans1 | iboost_bit);
 155         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 156                        ddi_translations->entries[level].hsw.trans2);
 157 }
 158
 159 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 160                              enum port port)
 161 {
 162         if (IS_BROXTON(dev_priv)) {
 163                 udelay(16);
 164                 return;
 165         }
 166
 167         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 168                          DDI_BUF_IS_IDLE), 8))
 169                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 170                         port_name(port));
 171 }
 172
 173 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 174                                       enum port port)
 175 {
 176         int ret;
 177
 178         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 179         if (DISPLAY_VER(dev_priv) < 10) {
 180                 usleep_range(518, 1000);
 181                 return;
 182         }
 183
 184         ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 185                           DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
 186
 187         if (ret)
 188                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 189                         port_name(port));
 190 }
 191
 192 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 193 {
 194         switch (pll->info->id) {
 195         case DPLL_ID_WRPLL1:
 196                 return PORT_CLK_SEL_WRPLL1;
 197         case DPLL_ID_WRPLL2:
 198                 return PORT_CLK_SEL_WRPLL2;
 199         case DPLL_ID_SPLL:
 200                 return PORT_CLK_SEL_SPLL;
 201         case DPLL_ID_LCPLL_810:
 202                 return PORT_CLK_SEL_LCPLL_810;
 203         case DPLL_ID_LCPLL_1350:
 204                 return PORT_CLK_SEL_LCPLL_1350;
 205         case DPLL_ID_LCPLL_2700:
 206                 return PORT_CLK_SEL_LCPLL_2700;
 207         default:
 208                 MISSING_CASE(pll->info->id);
 209                 return PORT_CLK_SEL_NONE;
 210         }
 211 }
 212
 213 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 214                                   const struct intel_crtc_state *crtc_state)
 215 {
 216         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 217         int clock = crtc_state->port_clock;
 218         const enum intel_dpll_id id = pll->info->id;
 219
 220         switch (id) {
 221         default:
 222                 /*
 223                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 224                  * here, so do warn if this get passed in
 225                  */
 226                 MISSING_CASE(id);
 227                 return DDI_CLK_SEL_NONE;
 228         case DPLL_ID_ICL_TBTPLL:
 229                 switch (clock) {
 230                 case 162000:
 231                         return DDI_CLK_SEL_TBT_162;
 232                 case 270000:
 233                         return DDI_CLK_SEL_TBT_270;
 234                 case 540000:
 235                         return DDI_CLK_SEL_TBT_540;
 236                 case 810000:
 237                         return DDI_CLK_SEL_TBT_810;
 238                 default:
 239                         MISSING_CASE(clock);
 240                         return DDI_CLK_SEL_NONE;
 241                 }
 242         case DPLL_ID_ICL_MGPLL1:
 243         case DPLL_ID_ICL_MGPLL2:
 244         case DPLL_ID_ICL_MGPLL3:
 245         case DPLL_ID_ICL_MGPLL4:
 246         case DPLL_ID_TGL_MGPLL5:
 247         case DPLL_ID_TGL_MGPLL6:
 248                 return DDI_CLK_SEL_MG;
 249         }
 250 }
 251
 252 static u32 ddi_buf_phy_link_rate(int port_clock)
 253 {
 254         switch (port_clock) {
 255         case 162000:
 256                 return DDI_BUF_PHY_LINK_RATE(0);
 257         case 216000:
 258                 return DDI_BUF_PHY_LINK_RATE(4);
 259         case 243000:
 260                 return DDI_BUF_PHY_LINK_RATE(5);
 261         case 270000:
 262                 return DDI_BUF_PHY_LINK_RATE(1);
 263         case 324000:
 264                 return DDI_BUF_PHY_LINK_RATE(6);
 265         case 432000:
 266                 return DDI_BUF_PHY_LINK_RATE(7);
 267         case 540000:
 268                 return DDI_BUF_PHY_LINK_RATE(2);
 269         case 810000:
 270                 return DDI_BUF_PHY_LINK_RATE(3);
 271         default:
 272                 MISSING_CASE(port_clock);
 273                 return DDI_BUF_PHY_LINK_RATE(0);
 274         }
 275 }
 276
 277 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 278                                       const struct intel_crtc_state *crtc_state)
 279 {
 280         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 281         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 282         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 283         enum phy phy = intel_port_to_phy(i915, encoder->port);
 284
 285         intel_dp->DP = dig_port->saved_port_bits |
 286                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 287         intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 288
 289         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 290                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 291                 if (dig_port->tc_mode != TC_PORT_TBT_ALT)
 292                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 293         }
 294 }
 295
 296 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 297                                  enum port port)
 298 {
 299         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 300
 301         switch (val) {
 302         case DDI_CLK_SEL_NONE:
 303                 return 0;
 304         case DDI_CLK_SEL_TBT_162:
 305                 return 162000;
 306         case DDI_CLK_SEL_TBT_270:
 307                 return 270000;
 308         case DDI_CLK_SEL_TBT_540:
 309                 return 540000;
 310         case DDI_CLK_SEL_TBT_810:
 311                 return 810000;
 312         default:
 313                 MISSING_CASE(val);
 314                 return 0;
 315         }
 316 }
 317
 318 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 319 {
 320         int dotclock;
 321
 322         if (pipe_config->has_pch_encoder)
 323                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 324                                                     &pipe_config->fdi_m_n);
 325         else if (intel_crtc_has_dp_encoder(pipe_config))
 326                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 327                                                     &pipe_config->dp_m_n);
 328         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 329                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 330         else
 331                 dotclock = pipe_config->port_clock;
 332
 333         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 334             !intel_crtc_has_dp_encoder(pipe_config))
 335                 dotclock *= 2;
 336
 337         if (pipe_config->pixel_multiplier)
 338                 dotclock /= pipe_config->pixel_multiplier;
 339
 340         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 341 }
 342
 343 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 344                           const struct drm_connector_state *conn_state)
 345 {
 346         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 347         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 348         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 349         u32 temp;
 350
 351         if (!intel_crtc_has_dp_encoder(crtc_state))
 352                 return;
 353
 354         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 355
 356         temp = DP_MSA_MISC_SYNC_CLOCK;
 357
 358         switch (crtc_state->pipe_bpp) {
 359         case 18:
 360                 temp |= DP_MSA_MISC_6_BPC;
 361                 break;
 362         case 24:
 363                 temp |= DP_MSA_MISC_8_BPC;
 364                 break;
 365         case 30:
 366                 temp |= DP_MSA_MISC_10_BPC;
 367                 break;
 368         case 36:
 369                 temp |= DP_MSA_MISC_12_BPC;
 370                 break;
 371         default:
 372                 MISSING_CASE(crtc_state->pipe_bpp);
 373                 break;
 374         }
 375
 376         /* nonsense combination */
 377         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 378                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 379
 380         if (crtc_state->limited_color_range)
 381                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 382
 383         /*
 384          * As per DP 1.2 spec section 2.3.4.3 while sending
 385          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 386          * colorspace information.
 387          */
 388         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 389                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 390
 391         /*
 392          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 393          * of Color Encoding Format and Content Color Gamut] while sending
 394          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 395          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 396          */
 397         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 398                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 399
 400         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 401 }
 402
 403 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 404 {
 405         if (master_transcoder == TRANSCODER_EDP)
 406                 return 0;
 407         else
 408                 return master_transcoder + 1;
 409 }
 410
 411 /*
 412  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 413  *
 414  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 415  * intel_ddi_config_transcoder_func().
 416  */
 417 static u32
 418 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 419                                       const struct intel_crtc_state *crtc_state)
 420 {
 421         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 423         enum pipe pipe = crtc->pipe;
 424         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 425         enum port port = encoder->port;
 426         u32 temp;
 427
 428         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 429         temp = TRANS_DDI_FUNC_ENABLE;
 430         if (DISPLAY_VER(dev_priv) >= 12)
 431                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 432         else
 433                 temp |= TRANS_DDI_SELECT_PORT(port);
 434
 435         switch (crtc_state->pipe_bpp) {
 436         case 18:
 437                 temp |= TRANS_DDI_BPC_6;
 438                 break;
 439         case 24:
 440                 temp |= TRANS_DDI_BPC_8;
 441                 break;
 442         case 30:
 443                 temp |= TRANS_DDI_BPC_10;
 444                 break;
 445         case 36:
 446                 temp |= TRANS_DDI_BPC_12;
 447                 break;
 448         default:
 449                 BUG();
 450         }
 451
 452         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 453                 temp |= TRANS_DDI_PVSYNC;
 454         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 455                 temp |= TRANS_DDI_PHSYNC;
 456
 457         if (cpu_transcoder == TRANSCODER_EDP) {
 458                 switch (pipe) {
 459                 case PIPE_A:
 460                         /* On Haswell, can only use the always-on power well for
 461                          * eDP when not using the panel fitter, and when not
 462                          * using motion blur mitigation (which we don't
 463                          * support). */
 464                         if (crtc_state->pch_pfit.force_thru)
 465                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 466                         else
 467                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 468                         break;
 469                 case PIPE_B:
 470                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 471                         break;
 472                 case PIPE_C:
 473                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 474                         break;
 475                 default:
 476                         BUG();
 477                         break;
 478                 }
 479         }
 480
 481         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 482                 if (crtc_state->has_hdmi_sink)
 483                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 484                 else
 485                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 486
 487                 if (crtc_state->hdmi_scrambling)
 488                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 489                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 490                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 491         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 492                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 493                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 494         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 495                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 496                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 497
 498                 if (DISPLAY_VER(dev_priv) >= 12) {
 499                         enum transcoder master;
 500
 501                         master = crtc_state->mst_master_transcoder;
 502                         drm_WARN_ON(&dev_priv->drm,
 503                                     master == INVALID_TRANSCODER);
 504                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 505                 }
 506         } else {
 507                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 508                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 509         }
 510
 511         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 512             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 513                 u8 master_select =
 514                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 515
 516                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 517                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 518         }
 519
 520         return temp;
 521 }
 522
 523 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 524                                       const struct intel_crtc_state *crtc_state)
 525 {
 526         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 527         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 528         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 529
 530         if (DISPLAY_VER(dev_priv) >= 11) {
 531                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 532                 u32 ctl2 = 0;
 533
 534                 if (master_transcoder != INVALID_TRANSCODER) {
 535                         u8 master_select =
 536                                 bdw_trans_port_sync_master_select(master_transcoder);
 537
 538                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 539                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 540                 }
 541
 542                 intel_de_write(dev_priv,
 543                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 544         }
 545
 546         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 547                        intel_ddi_transcoder_func_reg_val_get(encoder,
 548                                                              crtc_state));
 549 }
 550
 551 /*
 552  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 553  * bit.
 554  */
 555 static void
 556 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 557                                  const struct intel_crtc_state *crtc_state)
 558 {
 559         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 561         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 562         u32 ctl;
 563
 564         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 565         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 566         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 567 }
 568
 569 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 570 {
 571         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 573         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 574         u32 ctl;
 575
 576         if (DISPLAY_VER(dev_priv) >= 11)
 577                 intel_de_write(dev_priv,
 578                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 579
 580         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 581
 582         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 583
 584         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 585
 586         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 587                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 588                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 589
 590         if (DISPLAY_VER(dev_priv) >= 12) {
 591                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 592                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 593                                  TRANS_DDI_MODE_SELECT_MASK);
 594                 }
 595         } else {
 596                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 597         }
 598
 599         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 600
 601         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 602             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 603                 drm_dbg_kms(&dev_priv->drm,
 604                             "Quirk Increase DDI disabled time\n");
 605                 /* Quirk time at 100ms for reliable operation */
 606                 msleep(100);
 607         }
 608 }
 609
 610 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 611                                enum transcoder cpu_transcoder,
 612                                bool enable, u32 hdcp_mask)
 613 {
 614         struct drm_device *dev = intel_encoder->base.dev;
 615         struct drm_i915_private *dev_priv = to_i915(dev);
 616         intel_wakeref_t wakeref;
 617         int ret = 0;
 618         u32 tmp;
 619
 620         wakeref = intel_display_power_get_if_enabled(dev_priv,
 621                                                      intel_encoder->power_domain);
 622         if (drm_WARN_ON(dev, !wakeref))
 623                 return -ENXIO;
 624
 625         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 626         if (enable)
 627                 tmp |= hdcp_mask;
 628         else
 629                 tmp &= ~hdcp_mask;
 630         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 631         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 632         return ret;
 633 }
 634
 635 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 636 {
 637         struct drm_device *dev = intel_connector->base.dev;
 638         struct drm_i915_private *dev_priv = to_i915(dev);
 639         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 640         int type = intel_connector->base.connector_type;
 641         enum port port = encoder->port;
 642         enum transcoder cpu_transcoder;
 643         intel_wakeref_t wakeref;
 644         enum pipe pipe = 0;
 645         u32 tmp;
 646         bool ret;
 647
 648         wakeref = intel_display_power_get_if_enabled(dev_priv,
 649                                                      encoder->power_domain);
 650         if (!wakeref)
 651                 return false;
 652
 653         if (!encoder->get_hw_state(encoder, &pipe)) {
 654                 ret = false;
 655                 goto out;
 656         }
 657
 658         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 659                 cpu_transcoder = TRANSCODER_EDP;
 660         else
 661                 cpu_transcoder = (enum transcoder) pipe;
 662
 663         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 664
 665         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 666         case TRANS_DDI_MODE_SELECT_HDMI:
 667         case TRANS_DDI_MODE_SELECT_DVI:
 668                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 669                 break;
 670
 671         case TRANS_DDI_MODE_SELECT_DP_SST:
 672                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 673                       type == DRM_MODE_CONNECTOR_DisplayPort;
 674                 break;
 675
 676         case TRANS_DDI_MODE_SELECT_DP_MST:
 677                 /* if the transcoder is in MST state then
 678                  * connector isn't connected */
 679                 ret = false;
 680                 break;
 681
 682         case TRANS_DDI_MODE_SELECT_FDI:
 683                 ret = type == DRM_MODE_CONNECTOR_VGA;
 684                 break;
 685
 686         default:
 687                 ret = false;
 688                 break;
 689         }
 690
 691 out:
 692         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 693
 694         return ret;
 695 }
 696
 697 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 698                                         u8 *pipe_mask, bool *is_dp_mst)
 699 {
 700         struct drm_device *dev = encoder->base.dev;
 701         struct drm_i915_private *dev_priv = to_i915(dev);
 702         enum port port = encoder->port;
 703         intel_wakeref_t wakeref;
 704         enum pipe p;
 705         u32 tmp;
 706         u8 mst_pipe_mask;
 707
 708         *pipe_mask = 0;
 709         *is_dp_mst = false;
 710
 711         wakeref = intel_display_power_get_if_enabled(dev_priv,
 712                                                      encoder->power_domain);
 713         if (!wakeref)
 714                 return;
 715
 716         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 717         if (!(tmp & DDI_BUF_CTL_ENABLE))
 718                 goto out;
 719
 720         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 721                 tmp = intel_de_read(dev_priv,
 722                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 723
 724                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 725                 default:
 726                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 727                         fallthrough;
 728                 case TRANS_DDI_EDP_INPUT_A_ON:
 729                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 730                         *pipe_mask = BIT(PIPE_A);
 731                         break;
 732                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 733                         *pipe_mask = BIT(PIPE_B);
 734                         break;
 735                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 736                         *pipe_mask = BIT(PIPE_C);
 737                         break;
 738                 }
 739
 740                 goto out;
 741         }
 742
 743         mst_pipe_mask = 0;
 744         for_each_pipe(dev_priv, p) {
 745                 enum transcoder cpu_transcoder = (enum transcoder)p;
 746                 unsigned int port_mask, ddi_select;
 747                 intel_wakeref_t trans_wakeref;
 748
 749                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 750                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 751                 if (!trans_wakeref)
 752                         continue;
 753
 754                 if (DISPLAY_VER(dev_priv) >= 12) {
 755                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 756                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 757                 } else {
 758                         port_mask = TRANS_DDI_PORT_MASK;
 759                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 760                 }
 761
 762                 tmp = intel_de_read(dev_priv,
 763                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 764                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 765                                         trans_wakeref);
 766
 767                 if ((tmp & port_mask) != ddi_select)
 768                         continue;
 769
 770                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
 771                     TRANS_DDI_MODE_SELECT_DP_MST)
 772                         mst_pipe_mask |= BIT(p);
 773
 774                 *pipe_mask |= BIT(p);
 775         }
 776
 777         if (!*pipe_mask)
 778                 drm_dbg_kms(&dev_priv->drm,
 779                             "No pipe for [ENCODER:%d:%s] found\n",
 780                             encoder->base.base.id, encoder->base.name);
 781
 782         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 783                 drm_dbg_kms(&dev_priv->drm,
 784                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 785                             encoder->base.base.id, encoder->base.name,
 786                             *pipe_mask);
 787                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 788         }
 789
 790         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 791                 drm_dbg_kms(&dev_priv->drm,
 792                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 793                             encoder->base.base.id, encoder->base.name,
 794                             *pipe_mask, mst_pipe_mask);
 795         else
 796                 *is_dp_mst = mst_pipe_mask;
 797
 798 out:
 799         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 800                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 801                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 802                             BXT_PHY_LANE_POWERDOWN_ACK |
 803                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 804                         drm_err(&dev_priv->drm,
 805                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 806                                 encoder->base.base.id, encoder->base.name, tmp);
 807         }
 808
 809         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 810 }
 811
 812 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 813                             enum pipe *pipe)
 814 {
 815         u8 pipe_mask;
 816         bool is_mst;
 817
 818         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 819
 820         if (is_mst || !pipe_mask)
 821                 return false;
 822
 823         *pipe = ffs(pipe_mask) - 1;
 824
 825         return true;
 826 }
 827
 828 static enum intel_display_power_domain
 829 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 830 {
 831         /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 832          * DC states enabled at the same time, while for driver initiated AUX
 833          * transfers we need the same AUX IOs to be powered but with DC states
 834          * disabled. Accordingly use the AUX power domain here which leaves DC
 835          * states enabled.
 836          * However, for non-A AUX ports the corresponding non-EDP transcoders
 837          * would have already enabled power well 2 and DC_OFF. This means we can
 838          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 839          * specific AUX_IO reference without powering up any extra wells.
 840          * Note that PSR is enabled only on Port A even though this function
 841          * returns the correct domain for other ports too.
 842          */
 843         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 844                                               intel_aux_power_domain(dig_port);
 845 }
 846
 847 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 848                                         struct intel_crtc_state *crtc_state)
 849 {
 850         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 851         struct intel_digital_port *dig_port;
 852         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 853
 854         /*
 855          * TODO: Add support for MST encoders. Atm, the following should never
 856          * happen since fake-MST encoders don't set their get_power_domains()
 857          * hook.
 858          */
 859         if (drm_WARN_ON(&dev_priv->drm,
 860                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 861                 return;
 862
 863         dig_port = enc_to_dig_port(encoder);
 864
 865         if (!intel_phy_is_tc(dev_priv, phy) ||
 866             dig_port->tc_mode != TC_PORT_TBT_ALT) {
 867                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 868                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 869                                                                    dig_port->ddi_io_power_domain);
 870         }
 871
 872         /*
 873          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 874          * ports.
 875          */
 876         if (intel_crtc_has_dp_encoder(crtc_state) ||
 877             intel_phy_is_tc(dev_priv, phy)) {
 878                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 879                 dig_port->aux_wakeref =
 880                         intel_display_power_get(dev_priv,
 881                                                 intel_ddi_main_link_aux_domain(dig_port));
 882         }
 883 }
 884
 885 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 886                                  const struct intel_crtc_state *crtc_state)
 887 {
 888         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 889         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 890         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 891         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 892         u32 val;
 893
 894         if (cpu_transcoder != TRANSCODER_EDP) {
 895                 if (DISPLAY_VER(dev_priv) >= 13)
 896                         val = TGL_TRANS_CLK_SEL_PORT(phy);
 897                 else if (DISPLAY_VER(dev_priv) >= 12)
 898                         val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 899                 else
 900                         val = TRANS_CLK_SEL_PORT(encoder->port);
 901
 902                 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 903         }
 904 }
 905
 906 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 907 {
 908         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 909         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 910
 911         if (cpu_transcoder != TRANSCODER_EDP) {
 912                 if (DISPLAY_VER(dev_priv) >= 12)
 913                         intel_de_write(dev_priv,
 914                                        TRANS_CLK_SEL(cpu_transcoder),
 915                                        TGL_TRANS_CLK_SEL_DISABLED);
 916                 else
 917                         intel_de_write(dev_priv,
 918                                        TRANS_CLK_SEL(cpu_transcoder),
 919                                        TRANS_CLK_SEL_DISABLED);
 920         }
 921 }
 922
 923 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 924                                 enum port port, u8 iboost)
 925 {
 926         u32 tmp;
 927
 928         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 929         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 930         if (iboost)
 931                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 932         else
 933                 tmp |= BALANCE_LEG_DISABLE(port);
 934         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 935 }
 936
 937 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 938                                const struct intel_crtc_state *crtc_state,
 939                                int level)
 940 {
 941         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 942         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 943         u8 iboost;
 944
 945         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 946                 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
 947         else
 948                 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
 949
 950         if (iboost == 0) {
 951                 const struct intel_ddi_buf_trans *ddi_translations;
 952                 int n_entries;
 953
 954                 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 955                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 956                         return;
 957                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 958                         level = n_entries - 1;
 959
 960                 iboost = ddi_translations->entries[level].hsw.i_boost;
 961         }
 962
 963         /* Make sure that the requested I_boost is valid */
 964         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
 965                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
 966                 return;
 967         }
 968
 969         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
 970
 971         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
 972                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
 973 }
 974
 975 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 976                                     const struct intel_crtc_state *crtc_state,
 977                                     int level)
 978 {
 979         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 980         const struct intel_ddi_buf_trans *ddi_translations;
 981         enum port port = encoder->port;
 982         int n_entries;
 983
 984         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 985         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 986                 return;
 987         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 988                 level = n_entries - 1;
 989
 990         bxt_ddi_phy_set_signal_level(dev_priv, port,
 991                                      ddi_translations->entries[level].bxt.margin,
 992                                      ddi_translations->entries[level].bxt.scale,
 993                                      ddi_translations->entries[level].bxt.enable,
 994                                      ddi_translations->entries[level].bxt.deemphasis);
 995 }
 996
 997 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
 998                                    const struct intel_crtc_state *crtc_state)
 999 {
1000         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1001         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1002         int n_entries;
1003
1004         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1005
1006         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1007                 n_entries = 1;
1008         if (drm_WARN_ON(&dev_priv->drm,
1009                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1010                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1011
1012         return index_to_dp_signal_levels[n_entries - 1] &
1013                 DP_TRAIN_VOLTAGE_SWING_MASK;
1014 }
1015
1016 /*
1017  * We assume that the full set of pre-emphasis values can be
1018  * used on all DDI platforms. Should that change we need to
1019  * rethink this code.
1020  */
1021 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1022 {
1023         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1024 }
1025
1026 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1027                                          const struct intel_crtc_state *crtc_state,
1028                                          int level)
1029 {
1030         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1031         const struct intel_ddi_buf_trans *ddi_translations;
1032         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1033         int n_entries, ln;
1034         u32 val;
1035
1036         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1037         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1038                 return;
1039         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1040                 level = n_entries - 1;
1041
1042         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1043                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1044
1045                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1046                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
1047                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1048                              intel_dp->hobl_active ? val : 0);
1049         }
1050
1051         /* Set PORT_TX_DW5 */
1052         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1053         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1054                   TAP2_DISABLE | TAP3_DISABLE);
1055         val |= SCALING_MODE_SEL(0x2);
1056         val |= RTERM_SELECT(0x6);
1057         val |= TAP3_DISABLE;
1058         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1059
1060         /* Program PORT_TX_DW2 */
1061         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
1062         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1063                  RCOMP_SCALAR_MASK);
1064         val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
1065         val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
1066         /* Program Rcomp scalar for every table entry */
1067         val |= RCOMP_SCALAR(0x98);
1068         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
1069
1070         /* Program PORT_TX_DW4 */
1071         /* We cannot write to GRP. It would overwrite individual loadgen. */
1072         for (ln = 0; ln <= 3; ln++) {
1073                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1074                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1075                          CURSOR_COEFF_MASK);
1076                 val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
1077                 val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
1078                 val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
1079                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1080         }
1081
1082         /* Program PORT_TX_DW7 */
1083         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
1084         val &= ~N_SCALAR_MASK;
1085         val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
1086         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
1087 }
1088
1089 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1090                                               const struct intel_crtc_state *crtc_state,
1091                                               int level)
1092 {
1093         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1094         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1095         int width, rate, ln;
1096         u32 val;
1097
1098         width = crtc_state->lane_count;
1099         rate = crtc_state->port_clock;
1100
1101         /*
1102          * 1. If port type is eDP or DP,
1103          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1104          * else clear to 0b.
1105          */
1106         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
1107         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1108                 val &= ~COMMON_KEEPER_EN;
1109         else
1110                 val |= COMMON_KEEPER_EN;
1111         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1112
1113         /* 2. Program loadgen select */
1114         /*
1115          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1116          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1117          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1118          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1119          */
1120         for (ln = 0; ln <= 3; ln++) {
1121                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1122                 val &= ~LOADGEN_SELECT;
1123
1124                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
1125                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1126                         val |= LOADGEN_SELECT;
1127                 }
1128                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1129         }
1130
1131         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1132         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
1133         val |= SUS_CLOCK_CONFIG;
1134         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
1135
1136         /* 4. Clear training enable to change swing values */
1137         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1138         val &= ~TX_TRAINING_EN;
1139         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1140
1141         /* 5. Program swing and de-emphasis */
1142         icl_ddi_combo_vswing_program(encoder, crtc_state, level);
1143
1144         /* 6. Set training enable to trigger update */
1145         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1146         val |= TX_TRAINING_EN;
1147         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1148 }
1149
1150 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1151                                            const struct intel_crtc_state *crtc_state,
1152                                            int level)
1153 {
1154         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1155         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1156         const struct intel_ddi_buf_trans *ddi_translations;
1157         int n_entries, ln;
1158         u32 val;
1159
1160         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1161                 return;
1162
1163         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1164         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1165                 return;
1166         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1167                 level = n_entries - 1;
1168
1169         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
1170         for (ln = 0; ln < 2; ln++) {
1171                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
1172                 val &= ~CRI_USE_FS32;
1173                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
1174
1175                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
1176                 val &= ~CRI_USE_FS32;
1177                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
1178         }
1179
1180         /* Program MG_TX_SWINGCTRL with values from vswing table */
1181         for (ln = 0; ln < 2; ln++) {
1182                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
1183                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1184                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1185                         ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);
1186                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
1187
1188                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
1189                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1190                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1191                         ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);
1192                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
1193         }
1194
1195         /* Program MG_TX_DRVCTRL with values from vswing table */
1196         for (ln = 0; ln < 2; ln++) {
1197                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
1198                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1199                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1200                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1201                         ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |
1202                         CRI_TXDEEMPH_OVERRIDE_11_6(
1203                                 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |
1204                         CRI_TXDEEMPH_OVERRIDE_EN;
1205                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
1206
1207                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
1208                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1209                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1210                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1211                         ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |
1212                         CRI_TXDEEMPH_OVERRIDE_11_6(
1213                                 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |
1214                         CRI_TXDEEMPH_OVERRIDE_EN;
1215                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
1216
1217                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1218         }
1219
1220         /*
1221          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1222          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1223          * values from table for which TX1 and TX2 enabled.
1224          */
1225         for (ln = 0; ln < 2; ln++) {
1226                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
1227                 if (crtc_state->port_clock < 300000)
1228                         val |= CFG_LOW_RATE_LKREN_EN;
1229                 else
1230                         val &= ~CFG_LOW_RATE_LKREN_EN;
1231                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
1232         }
1233
1234         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1235         for (ln = 0; ln < 2; ln++) {
1236                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
1237                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1238                 if (crtc_state->port_clock <= 500000) {
1239                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1240                 } else {
1241                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1242                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1243                 }
1244                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
1245
1246                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
1247                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1248                 if (crtc_state->port_clock <= 500000) {
1249                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1250                 } else {
1251                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1252                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1253                 }
1254                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
1255         }
1256
1257         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1258         for (ln = 0; ln < 2; ln++) {
1259                 val = intel_de_read(dev_priv,
1260                                     MG_TX1_PISO_READLOAD(ln, tc_port));
1261                 val |= CRI_CALCINIT;
1262                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1263                                val);
1264
1265                 val = intel_de_read(dev_priv,
1266                                     MG_TX2_PISO_READLOAD(ln, tc_port));
1267                 val |= CRI_CALCINIT;
1268                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1269                                val);
1270         }
1271 }
1272
1273 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
1274                                     const struct intel_crtc_state *crtc_state,
1275                                     int level)
1276 {
1277         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1278         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1279
1280         if (intel_phy_is_combo(dev_priv, phy))
1281                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1282         else
1283                 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1284 }
1285
1286 static void
1287 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1288                                 const struct intel_crtc_state *crtc_state,
1289                                 int level)
1290 {
1291         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1292         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1293         const struct intel_ddi_buf_trans *ddi_translations;
1294         u32 val, dpcnt_mask, dpcnt_val;
1295         int n_entries, ln;
1296
1297         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1298                 return;
1299
1300         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1301         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1302                 return;
1303         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1304                 level = n_entries - 1;
1305
1306         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
1307                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1308                       DKL_TX_VSWING_CONTROL_MASK);
1309         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control);
1310         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control);
1311         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control);
1312
1313         for (ln = 0; ln < 2; ln++) {
1314                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1315                                HIP_INDEX_VAL(tc_port, ln));
1316
1317                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1318
1319                 /* All the registers are RMW */
1320                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
1321                 val &= ~dpcnt_mask;
1322                 val |= dpcnt_val;
1323                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
1324
1325                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
1326                 val &= ~dpcnt_mask;
1327                 val |= dpcnt_val;
1328                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
1329
1330                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
1331                 val &= ~DKL_TX_DP20BITMODE;
1332                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
1333
1334                 if ((intel_crtc_has_dp_encoder(crtc_state) &&
1335                      crtc_state->port_clock == 162000) ||
1336                     (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1337                      crtc_state->port_clock == 594000))
1338                         val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1339                 else
1340                         val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1341         }
1342 }
1343
1344 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
1345                                     const struct intel_crtc_state *crtc_state,
1346                                     int level)
1347 {
1348         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1349         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1350
1351         if (intel_phy_is_combo(dev_priv, phy))
1352                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1353         else
1354                 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1355 }
1356
1357 static int translate_signal_level(struct intel_dp *intel_dp,
1358                                   u8 signal_levels)
1359 {
1360         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1361         int i;
1362
1363         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1364                 if (index_to_dp_signal_levels[i] == signal_levels)
1365                         return i;
1366         }
1367
1368         drm_WARN(&i915->drm, 1,
1369                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1370                  signal_levels);
1371
1372         return 0;
1373 }
1374
1375 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1376                               const struct intel_crtc_state *crtc_state)
1377 {
1378         u8 train_set = intel_dp->train_set[0];
1379         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1380                                         DP_TRAIN_PRE_EMPHASIS_MASK);
1381
1382         return translate_signal_level(intel_dp, signal_levels);
1383 }
1384
1385 static void
1386 dg2_set_signal_levels(struct intel_dp *intel_dp,
1387                       const struct intel_crtc_state *crtc_state)
1388 {
1389         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1390         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1391
1392         intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1393 }
1394
1395 static void
1396 tgl_set_signal_levels(struct intel_dp *intel_dp,
1397                       const struct intel_crtc_state *crtc_state)
1398 {
1399         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1400         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1401
1402         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
1403 }
1404
1405 static void
1406 icl_set_signal_levels(struct intel_dp *intel_dp,
1407                       const struct intel_crtc_state *crtc_state)
1408 {
1409         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1410         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1411
1412         icl_ddi_vswing_sequence(encoder, crtc_state, level);
1413 }
1414
1415 static void
1416 bxt_set_signal_levels(struct intel_dp *intel_dp,
1417                       const struct intel_crtc_state *crtc_state)
1418 {
1419         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1420         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1421
1422         bxt_ddi_vswing_sequence(encoder, crtc_state, level);
1423 }
1424
1425 static void
1426 hsw_set_signal_levels(struct intel_dp *intel_dp,
1427                       const struct intel_crtc_state *crtc_state)
1428 {
1429         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1430         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1431         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1432         enum port port = encoder->port;
1433         u32 signal_levels;
1434
1435         signal_levels = DDI_BUF_TRANS_SELECT(level);
1436
1437         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1438                     signal_levels);
1439
1440         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1441         intel_dp->DP |= signal_levels;
1442
1443         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
1444                 skl_ddi_set_iboost(encoder, crtc_state, level);
1445
1446         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1447         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1448 }
1449
1450 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1451                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1452 {
1453         mutex_lock(&i915->dpll.lock);
1454
1455         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1456
1457         /*
1458          * "This step and the step before must be
1459          *  done with separate register writes."
1460          */
1461         intel_de_rmw(i915, reg, clk_off, 0);
1462
1463         mutex_unlock(&i915->dpll.lock);
1464 }
1465
1466 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1467                                    u32 clk_off)
1468 {
1469         mutex_lock(&i915->dpll.lock);
1470
1471         intel_de_rmw(i915, reg, 0, clk_off);
1472
1473         mutex_unlock(&i915->dpll.lock);
1474 }
1475
1476 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1477                                       u32 clk_off)
1478 {
1479         return !(intel_de_read(i915, reg) & clk_off);
1480 }
1481
1482 static struct intel_shared_dpll *
1483 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1484                  u32 clk_sel_mask, u32 clk_sel_shift)
1485 {
1486         enum intel_dpll_id id;
1487
1488         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1489
1490         return intel_get_shared_dpll_by_id(i915, id);
1491 }
1492
1493 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1494                                   const struct intel_crtc_state *crtc_state)
1495 {
1496         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1497         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1498         enum phy phy = intel_port_to_phy(i915, encoder->port);
1499
1500         if (drm_WARN_ON(&i915->drm, !pll))
1501                 return;
1502
1503         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1504                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1505                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1506                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1507 }
1508
1509 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1510 {
1511         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1512         enum phy phy = intel_port_to_phy(i915, encoder->port);
1513
1514         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1515                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1516 }
1517
1518 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1519 {
1520         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1521         enum phy phy = intel_port_to_phy(i915, encoder->port);
1522
1523         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1524                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1525 }
1526
1527 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1528 {
1529         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1530         enum phy phy = intel_port_to_phy(i915, encoder->port);
1531
1532         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1533                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1534                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1535 }
1536
1537 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1538                                  const struct intel_crtc_state *crtc_state)
1539 {
1540         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1541         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1542         enum phy phy = intel_port_to_phy(i915, encoder->port);
1543
1544         if (drm_WARN_ON(&i915->drm, !pll))
1545                 return;
1546
1547         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1548                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1549                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1550                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1551 }
1552
1553 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1554 {
1555         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1556         enum phy phy = intel_port_to_phy(i915, encoder->port);
1557
1558         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1559                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1560 }
1561
1562 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1563 {
1564         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1565         enum phy phy = intel_port_to_phy(i915, encoder->port);
1566
1567         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1568                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1569 }
1570
1571 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1572 {
1573         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1574         enum phy phy = intel_port_to_phy(i915, encoder->port);
1575
1576         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1577                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1578                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1579 }
1580
1581 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1582                                  const struct intel_crtc_state *crtc_state)
1583 {
1584         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1585         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1586         enum phy phy = intel_port_to_phy(i915, encoder->port);
1587
1588         if (drm_WARN_ON(&i915->drm, !pll))
1589                 return;
1590
1591         /*
1592          * If we fail this, something went very wrong: first 2 PLLs should be
1593          * used by first 2 phys and last 2 PLLs by last phys
1594          */
1595         if (drm_WARN_ON(&i915->drm,
1596                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1597                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1598                 return;
1599
1600         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1601                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1602                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1603                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1604 }
1605
1606 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1607 {
1608         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1609         enum phy phy = intel_port_to_phy(i915, encoder->port);
1610
1611         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1612                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1613 }
1614
1615 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1616 {
1617         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1618         enum phy phy = intel_port_to_phy(i915, encoder->port);
1619
1620         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1621                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1622 }
1623
1624 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1625 {
1626         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1627         enum phy phy = intel_port_to_phy(i915, encoder->port);
1628         enum intel_dpll_id id;
1629         u32 val;
1630
1631         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1632         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1633         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1634         id = val;
1635
1636         /*
1637          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1638          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1639          * bit for phy C and D.
1640          */
1641         if (phy >= PHY_C)
1642                 id += DPLL_ID_DG1_DPLL2;
1643
1644         return intel_get_shared_dpll_by_id(i915, id);
1645 }
1646
1647 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1648                                        const struct intel_crtc_state *crtc_state)
1649 {
1650         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1651         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1652         enum phy phy = intel_port_to_phy(i915, encoder->port);
1653
1654         if (drm_WARN_ON(&i915->drm, !pll))
1655                 return;
1656
1657         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1658                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1659                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1660                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1661 }
1662
1663 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1664 {
1665         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1666         enum phy phy = intel_port_to_phy(i915, encoder->port);
1667
1668         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1669                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1670 }
1671
1672 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1673 {
1674         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1675         enum phy phy = intel_port_to_phy(i915, encoder->port);
1676
1677         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1678                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1679 }
1680
1681 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1682 {
1683         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1684         enum phy phy = intel_port_to_phy(i915, encoder->port);
1685
1686         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1687                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1688                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1689 }
1690
1691 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1692                                     const struct intel_crtc_state *crtc_state)
1693 {
1694         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1695         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1696         enum port port = encoder->port;
1697
1698         if (drm_WARN_ON(&i915->drm, !pll))
1699                 return;
1700
1701         /*
1702          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1703          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1704          */
1705         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1706
1707         icl_ddi_combo_enable_clock(encoder, crtc_state);
1708 }
1709
1710 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1711 {
1712         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1713         enum port port = encoder->port;
1714
1715         icl_ddi_combo_disable_clock(encoder);
1716
1717         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1718 }
1719
1720 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1721 {
1722         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1723         enum port port = encoder->port;
1724         u32 tmp;
1725
1726         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1727
1728         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1729                 return false;
1730
1731         return icl_ddi_combo_is_clock_enabled(encoder);
1732 }
1733
1734 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1735                                     const struct intel_crtc_state *crtc_state)
1736 {
1737         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1738         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1739         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1740         enum port port = encoder->port;
1741
1742         if (drm_WARN_ON(&i915->drm, !pll))
1743                 return;
1744
1745         intel_de_write(i915, DDI_CLK_SEL(port),
1746                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1747
1748         mutex_lock(&i915->dpll.lock);
1749
1750         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1751                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1752
1753         mutex_unlock(&i915->dpll.lock);
1754 }
1755
1756 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1757 {
1758         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1759         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1760         enum port port = encoder->port;
1761
1762         mutex_lock(&i915->dpll.lock);
1763
1764         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1765                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1766
1767         mutex_unlock(&i915->dpll.lock);
1768
1769         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1770 }
1771
1772 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1773 {
1774         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1775         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1776         enum port port = encoder->port;
1777         u32 tmp;
1778
1779         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1780
1781         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1782                 return false;
1783
1784         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1785
1786         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1787 }
1788
1789 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1790 {
1791         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1792         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1793         enum port port = encoder->port;
1794         enum intel_dpll_id id;
1795         u32 tmp;
1796
1797         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1798
1799         switch (tmp & DDI_CLK_SEL_MASK) {
1800         case DDI_CLK_SEL_TBT_162:
1801         case DDI_CLK_SEL_TBT_270:
1802         case DDI_CLK_SEL_TBT_540:
1803         case DDI_CLK_SEL_TBT_810:
1804                 id = DPLL_ID_ICL_TBTPLL;
1805                 break;
1806         case DDI_CLK_SEL_MG:
1807                 id = icl_tc_port_to_pll_id(tc_port);
1808                 break;
1809         default:
1810                 MISSING_CASE(tmp);
1811                 fallthrough;
1812         case DDI_CLK_SEL_NONE:
1813                 return NULL;
1814         }
1815
1816         return intel_get_shared_dpll_by_id(i915, id);
1817 }
1818
1819 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1820 {
1821         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1822         enum intel_dpll_id id;
1823
1824         switch (encoder->port) {
1825         case PORT_A:
1826                 id = DPLL_ID_SKL_DPLL0;
1827                 break;
1828         case PORT_B:
1829                 id = DPLL_ID_SKL_DPLL1;
1830                 break;
1831         case PORT_C:
1832                 id = DPLL_ID_SKL_DPLL2;
1833                 break;
1834         default:
1835                 MISSING_CASE(encoder->port);
1836                 return NULL;
1837         }
1838
1839         return intel_get_shared_dpll_by_id(i915, id);
1840 }
1841
1842 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1843                                  const struct intel_crtc_state *crtc_state)
1844 {
1845         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1846         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1847         enum port port = encoder->port;
1848
1849         if (drm_WARN_ON(&i915->drm, !pll))
1850                 return;
1851
1852         mutex_lock(&i915->dpll.lock);
1853
1854         intel_de_rmw(i915, DPLL_CTRL2,
1855                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1856                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1857                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1858                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1859
1860         mutex_unlock(&i915->dpll.lock);
1861 }
1862
1863 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1864 {
1865         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1866         enum port port = encoder->port;
1867
1868         mutex_lock(&i915->dpll.lock);
1869
1870         intel_de_rmw(i915, DPLL_CTRL2,
1871                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1872
1873         mutex_unlock(&i915->dpll.lock);
1874 }
1875
1876 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1877 {
1878         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1879         enum port port = encoder->port;
1880
1881         /*
1882          * FIXME Not sure if the override affects both
1883          * the PLL selection and the CLK_OFF bit.
1884          */
1885         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1886 }
1887
1888 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1889 {
1890         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1891         enum port port = encoder->port;
1892         enum intel_dpll_id id;
1893         u32 tmp;
1894
1895         tmp = intel_de_read(i915, DPLL_CTRL2);
1896
1897         /*
1898          * FIXME Not sure if the override affects both
1899          * the PLL selection and the CLK_OFF bit.
1900          */
1901         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1902                 return NULL;
1903
1904         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1905                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1906
1907         return intel_get_shared_dpll_by_id(i915, id);
1908 }
1909
1910 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1911                           const struct intel_crtc_state *crtc_state)
1912 {
1913         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1914         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1915         enum port port = encoder->port;
1916
1917         if (drm_WARN_ON(&i915->drm, !pll))
1918                 return;
1919
1920         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1921 }
1922
1923 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1924 {
1925         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1926         enum port port = encoder->port;
1927
1928         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1929 }
1930
1931 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1932 {
1933         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1934         enum port port = encoder->port;
1935
1936         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1937 }
1938
1939 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1940 {
1941         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1942         enum port port = encoder->port;
1943         enum intel_dpll_id id;
1944         u32 tmp;
1945
1946         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1947
1948         switch (tmp & PORT_CLK_SEL_MASK) {
1949         case PORT_CLK_SEL_WRPLL1:
1950                 id = DPLL_ID_WRPLL1;
1951                 break;
1952         case PORT_CLK_SEL_WRPLL2:
1953                 id = DPLL_ID_WRPLL2;
1954                 break;
1955         case PORT_CLK_SEL_SPLL:
1956                 id = DPLL_ID_SPLL;
1957                 break;
1958         case PORT_CLK_SEL_LCPLL_810:
1959                 id = DPLL_ID_LCPLL_810;
1960                 break;
1961         case PORT_CLK_SEL_LCPLL_1350:
1962                 id = DPLL_ID_LCPLL_1350;
1963                 break;
1964         case PORT_CLK_SEL_LCPLL_2700:
1965                 id = DPLL_ID_LCPLL_2700;
1966                 break;
1967         default:
1968                 MISSING_CASE(tmp);
1969                 fallthrough;
1970         case PORT_CLK_SEL_NONE:
1971                 return NULL;
1972         }
1973
1974         return intel_get_shared_dpll_by_id(i915, id);
1975 }
1976
1977 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1978                             const struct intel_crtc_state *crtc_state)
1979 {
1980         if (encoder->enable_clock)
1981                 encoder->enable_clock(encoder, crtc_state);
1982 }
1983
1984 static void intel_ddi_disable_clock(struct intel_encoder *encoder)
1985 {
1986         if (encoder->disable_clock)
1987                 encoder->disable_clock(encoder);
1988 }
1989
1990 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1991 {
1992         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1993         u32 port_mask;
1994         bool ddi_clk_needed;
1995
1996         /*
1997          * In case of DP MST, we sanitize the primary encoder only, not the
1998          * virtual ones.
1999          */
2000         if (encoder->type == INTEL_OUTPUT_DP_MST)
2001                 return;
2002
2003         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2004                 u8 pipe_mask;
2005                 bool is_mst;
2006
2007                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2008                 /*
2009                  * In the unlikely case that BIOS enables DP in MST mode, just
2010                  * warn since our MST HW readout is incomplete.
2011                  */
2012                 if (drm_WARN_ON(&i915->drm, is_mst))
2013                         return;
2014         }
2015
2016         port_mask = BIT(encoder->port);
2017         ddi_clk_needed = encoder->base.crtc;
2018
2019         if (encoder->type == INTEL_OUTPUT_DSI) {
2020                 struct intel_encoder *other_encoder;
2021
2022                 port_mask = intel_dsi_encoder_ports(encoder);
2023                 /*
2024                  * Sanity check that we haven't incorrectly registered another
2025                  * encoder using any of the ports of this DSI encoder.
2026                  */
2027                 for_each_intel_encoder(&i915->drm, other_encoder) {
2028                         if (other_encoder == encoder)
2029                                 continue;
2030
2031                         if (drm_WARN_ON(&i915->drm,
2032                                         port_mask & BIT(other_encoder->port)))
2033                                 return;
2034                 }
2035                 /*
2036                  * For DSI we keep the ddi clocks gated
2037                  * except during enable/disable sequence.
2038                  */
2039                 ddi_clk_needed = false;
2040         }
2041
2042         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2043             !encoder->is_clock_enabled(encoder))
2044                 return;
2045
2046         drm_notice(&i915->drm,
2047                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2048                    encoder->base.base.id, encoder->base.name);
2049
2050         encoder->disable_clock(encoder);
2051 }
2052
2053 static void
2054 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2055                        const struct intel_crtc_state *crtc_state)
2056 {
2057         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2058         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2059         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2060         u32 ln0, ln1, pin_assignment;
2061         u8 width;
2062
2063         if (!intel_phy_is_tc(dev_priv, phy) ||
2064             dig_port->tc_mode == TC_PORT_TBT_ALT)
2065                 return;
2066
2067         if (DISPLAY_VER(dev_priv) >= 12) {
2068                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2069                                HIP_INDEX_VAL(tc_port, 0x0));
2070                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2071                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2072                                HIP_INDEX_VAL(tc_port, 0x1));
2073                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2074         } else {
2075                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2076                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2077         }
2078
2079         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2080         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2081
2082         /* DPPATC */
2083         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2084         width = crtc_state->lane_count;
2085
2086         switch (pin_assignment) {
2087         case 0x0:
2088                 drm_WARN_ON(&dev_priv->drm,
2089                             dig_port->tc_mode != TC_PORT_LEGACY);
2090                 if (width == 1) {
2091                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2092                 } else {
2093                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2094                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2095                 }
2096                 break;
2097         case 0x1:
2098                 if (width == 4) {
2099                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2100                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2101                 }
2102                 break;
2103         case 0x2:
2104                 if (width == 2) {
2105                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2106                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2107                 }
2108                 break;
2109         case 0x3:
2110         case 0x5:
2111                 if (width == 1) {
2112                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2113                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2114                 } else {
2115                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2116                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2117                 }
2118                 break;
2119         case 0x4:
2120         case 0x6:
2121                 if (width == 1) {
2122                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2123                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2124                 } else {
2125                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2126                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2127                 }
2128                 break;
2129         default:
2130                 MISSING_CASE(pin_assignment);
2131         }
2132
2133         if (DISPLAY_VER(dev_priv) >= 12) {
2134                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2135                                HIP_INDEX_VAL(tc_port, 0x0));
2136                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2137                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2138                                HIP_INDEX_VAL(tc_port, 0x1));
2139                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2140         } else {
2141                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2142                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2143         }
2144 }
2145
2146 static enum transcoder
2147 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2148 {
2149         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2150                 return crtc_state->mst_master_transcoder;
2151         else
2152                 return crtc_state->cpu_transcoder;
2153 }
2154
2155 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2156                          const struct intel_crtc_state *crtc_state)
2157 {
2158         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2159
2160         if (DISPLAY_VER(dev_priv) >= 12)
2161                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2162         else
2163                 return DP_TP_CTL(encoder->port);
2164 }
2165
2166 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2167                             const struct intel_crtc_state *crtc_state)
2168 {
2169         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2170
2171         if (DISPLAY_VER(dev_priv) >= 12)
2172                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2173         else
2174                 return DP_TP_STATUS(encoder->port);
2175 }
2176
2177 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2178                                                           const struct intel_crtc_state *crtc_state,
2179                                                           bool enable)
2180 {
2181         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2182
2183         if (!crtc_state->vrr.enable)
2184                 return;
2185
2186         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2187                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2188                 drm_dbg_kms(&i915->drm,
2189                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2190                             enabledisable(enable));
2191 }
2192
2193 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2194                                         const struct intel_crtc_state *crtc_state)
2195 {
2196         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2197
2198         if (!crtc_state->fec_enable)
2199                 return;
2200
2201         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2202                 drm_dbg_kms(&i915->drm,
2203                             "Failed to set FEC_READY in the sink\n");
2204 }
2205
2206 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2207                                  const struct intel_crtc_state *crtc_state)
2208 {
2209         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2210         struct intel_dp *intel_dp;
2211         u32 val;
2212
2213         if (!crtc_state->fec_enable)
2214                 return;
2215
2216         intel_dp = enc_to_intel_dp(encoder);
2217         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2218         val |= DP_TP_CTL_FEC_ENABLE;
2219         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2220 }
2221
2222 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2223                                         const struct intel_crtc_state *crtc_state)
2224 {
2225         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2226         struct intel_dp *intel_dp;
2227         u32 val;
2228
2229         if (!crtc_state->fec_enable)
2230                 return;
2231
2232         intel_dp = enc_to_intel_dp(encoder);
2233         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2234         val &= ~DP_TP_CTL_FEC_ENABLE;
2235         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2236         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2237 }
2238
2239 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2240                                      const struct intel_crtc_state *crtc_state)
2241 {
2242         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2243         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2244         enum phy phy = intel_port_to_phy(i915, encoder->port);
2245
2246         if (intel_phy_is_combo(i915, phy)) {
2247                 bool lane_reversal =
2248                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2249
2250                 intel_combo_phy_power_up_lanes(i915, phy, false,
2251                                                crtc_state->lane_count,
2252                                                lane_reversal);
2253         }
2254 }
2255
2256 /* Splitter enable for eDP MSO is limited to certain pipes. */
2257 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2258 {
2259         if (IS_ALDERLAKE_P(i915))
2260                 return BIT(PIPE_A) | BIT(PIPE_B);
2261         else
2262                 return BIT(PIPE_A);
2263 }
2264
2265 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2266                                      struct intel_crtc_state *pipe_config)
2267 {
2268         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2269         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2270         enum pipe pipe = crtc->pipe;
2271         u32 dss1;
2272
2273         if (!HAS_MSO(i915))
2274                 return;
2275
2276         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2277
2278         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2279         if (!pipe_config->splitter.enable)
2280                 return;
2281
2282         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2283                 pipe_config->splitter.enable = false;
2284                 return;
2285         }
2286
2287         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2288         default:
2289                 drm_WARN(&i915->drm, true,
2290                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2291                 fallthrough;
2292         case SPLITTER_CONFIGURATION_2_SEGMENT:
2293                 pipe_config->splitter.link_count = 2;
2294                 break;
2295         case SPLITTER_CONFIGURATION_4_SEGMENT:
2296                 pipe_config->splitter.link_count = 4;
2297                 break;
2298         }
2299
2300         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2301 }
2302
2303 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2304 {
2305         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2306         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2307         enum pipe pipe = crtc->pipe;
2308         u32 dss1 = 0;
2309
2310         if (!HAS_MSO(i915))
2311                 return;
2312
2313         if (crtc_state->splitter.enable) {
2314                 dss1 |= SPLITTER_ENABLE;
2315                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2316                 if (crtc_state->splitter.link_count == 2)
2317                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2318                 else
2319                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2320         }
2321
2322         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2323                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2324                      OVERLAP_PIXELS_MASK, dss1);
2325 }
2326
2327 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
2328                                   struct intel_encoder *encoder,
2329                                   const struct intel_crtc_state *crtc_state,
2330                                   const struct drm_connector_state *conn_state)
2331 {
2332         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2333         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2334         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2335         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2336         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2337         int level = intel_ddi_dp_level(intel_dp, crtc_state);
2338
2339         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2340                                  crtc_state->lane_count);
2341
2342         /*
2343          * 1. Enable Power Wells
2344          *
2345          * This was handled at the beginning of intel_atomic_commit_tail(),
2346          * before we called down into this function.
2347          */
2348
2349         /* 2. Enable Panel Power if PPS is required */
2350         intel_pps_on(intel_dp);
2351
2352         /*
2353          * 3. Enable the port PLL.
2354          */
2355         intel_ddi_enable_clock(encoder, crtc_state);
2356
2357         /* 4. Enable IO power */
2358         if (!intel_phy_is_tc(dev_priv, phy) ||
2359             dig_port->tc_mode != TC_PORT_TBT_ALT)
2360                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2361                                                                    dig_port->ddi_io_power_domain);
2362
2363         /*
2364          * 5. The rest of the below are substeps under the bspec's "Enable and
2365          * Train Display Port" step.  Note that steps that are specific to
2366          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2367          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2368          * us when active_mst_links==0, so any steps designated for "single
2369          * stream or multi-stream master transcoder" can just be performed
2370          * unconditionally here.
2371          */
2372
2373         /*
2374          * 5.a Configure Transcoder Clock Select to direct the Port clock to the
2375          * Transcoder.
2376          */
2377         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2378
2379         /* 5.b Not relevant to i915 for now */
2380
2381         /*
2382          * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2383          * Transport Select
2384          */
2385         intel_ddi_config_transcoder_func(encoder, crtc_state);
2386
2387         /*
2388          * 5.d Configure & enable DP_TP_CTL with link training pattern 1
2389          * selected
2390          *
2391          * This will be handled by the intel_dp_start_link_train() farther
2392          * down this function.
2393          */
2394
2395         /* 5.e Configure voltage swing and related IO settings */
2396         intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2397
2398         /*
2399          * 5.f Configure and enable DDI_BUF_CTL
2400          * 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2401          *     after 1200 us.
2402          *
2403          * We only configure what the register value will be here.  Actual
2404          * enabling happens during link training farther down.
2405          */
2406         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2407
2408         if (!is_mst)
2409                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2410
2411         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2412         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2413         /*
2414          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2415          * in the FEC_CONFIGURATION register to 1 before initiating link
2416          * training
2417          */
2418         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2419         intel_dp_check_frl_training(intel_dp);
2420         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2421
2422         /*
2423          * 5.h Follow DisplayPort specification training sequence (see notes for
2424          *     failure handling)
2425          * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2426          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2427          *     (timeout after 800 us)
2428          */
2429         intel_dp_start_link_train(intel_dp, crtc_state);
2430
2431         /* 5.j Set DP_TP_CTL link training to Normal */
2432         if (!is_trans_port_sync_mode(crtc_state))
2433                 intel_dp_stop_link_train(intel_dp, crtc_state);
2434
2435         /* 5.k Configure and enable FEC if needed */
2436         intel_ddi_enable_fec(encoder, crtc_state);
2437         intel_dsc_enable(encoder, crtc_state);
2438 }
2439
2440 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2441                                   struct intel_encoder *encoder,
2442                                   const struct intel_crtc_state *crtc_state,
2443                                   const struct drm_connector_state *conn_state)
2444 {
2445         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2446         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2447         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2448         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2449         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2450         int level = intel_ddi_dp_level(intel_dp, crtc_state);
2451
2452         intel_dp_set_link_params(intel_dp,
2453                                  crtc_state->port_clock,
2454                                  crtc_state->lane_count);
2455
2456         /*
2457          * 1. Enable Power Wells
2458          *
2459          * This was handled at the beginning of intel_atomic_commit_tail(),
2460          * before we called down into this function.
2461          */
2462
2463         /* 2. Enable Panel Power if PPS is required */
2464         intel_pps_on(intel_dp);
2465
2466         /*
2467          * 3. For non-TBT Type-C ports, set FIA lane count
2468          * (DFLEXDPSP.DPX4TXLATC)
2469          *
2470          * This was done before tgl_ddi_pre_enable_dp by
2471          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2472          */
2473
2474         /*
2475          * 4. Enable the port PLL.
2476          *
2477          * The PLL enabling itself was already done before this function by
2478          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2479          * configure the PLL to port mapping here.
2480          */
2481         intel_ddi_enable_clock(encoder, crtc_state);
2482
2483         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2484         if (!intel_phy_is_tc(dev_priv, phy) ||
2485             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2486                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2487                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2488                                                                    dig_port->ddi_io_power_domain);
2489         }
2490
2491         /* 6. Program DP_MODE */
2492         icl_program_mg_dp_mode(dig_port, crtc_state);
2493
2494         /*
2495          * 7. The rest of the below are substeps under the bspec's "Enable and
2496          * Train Display Port" step.  Note that steps that are specific to
2497          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2498          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2499          * us when active_mst_links==0, so any steps designated for "single
2500          * stream or multi-stream master transcoder" can just be performed
2501          * unconditionally here.
2502          */
2503
2504         /*
2505          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2506          * Transcoder.
2507          */
2508         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2509
2510         /*
2511          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2512          * Transport Select
2513          */
2514         intel_ddi_config_transcoder_func(encoder, crtc_state);
2515
2516         /*
2517          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2518          * selected
2519          *
2520          * This will be handled by the intel_dp_start_link_train() farther
2521          * down this function.
2522          */
2523
2524         /* 7.e Configure voltage swing and related IO settings */
2525         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2526
2527         /*
2528          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2529          * the used lanes of the DDI.
2530          */
2531         intel_ddi_power_up_lanes(encoder, crtc_state);
2532
2533         /*
2534          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2535          */
2536         intel_ddi_mso_configure(crtc_state);
2537
2538         /*
2539          * 7.g Configure and enable DDI_BUF_CTL
2540          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2541          *     after 500 us.
2542          *
2543          * We only configure what the register value will be here.  Actual
2544          * enabling happens during link training farther down.
2545          */
2546         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2547
2548         if (!is_mst)
2549                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2550
2551         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2552         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2553         /*
2554          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2555          * in the FEC_CONFIGURATION register to 1 before initiating link
2556          * training
2557          */
2558         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2559
2560         intel_dp_check_frl_training(intel_dp);
2561         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2562
2563         /*
2564          * 7.i Follow DisplayPort specification training sequence (see notes for
2565          *     failure handling)
2566          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2567          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2568          *     (timeout after 800 us)
2569          */
2570         intel_dp_start_link_train(intel_dp, crtc_state);
2571
2572         /* 7.k Set DP_TP_CTL link training to Normal */
2573         if (!is_trans_port_sync_mode(crtc_state))
2574                 intel_dp_stop_link_train(intel_dp, crtc_state);
2575
2576         /* 7.l Configure and enable FEC if needed */
2577         intel_ddi_enable_fec(encoder, crtc_state);
2578         if (!crtc_state->bigjoiner)
2579                 intel_dsc_enable(encoder, crtc_state);
2580 }
2581
2582 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2583                                   struct intel_encoder *encoder,
2584                                   const struct intel_crtc_state *crtc_state,
2585                                   const struct drm_connector_state *conn_state)
2586 {
2587         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2588         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2589         enum port port = encoder->port;
2590         enum phy phy = intel_port_to_phy(dev_priv, port);
2591         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2592         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2593         int level = intel_ddi_dp_level(intel_dp, crtc_state);
2594
2595         if (DISPLAY_VER(dev_priv) < 11)
2596                 drm_WARN_ON(&dev_priv->drm,
2597                             is_mst && (port == PORT_A || port == PORT_E));
2598         else
2599                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2600
2601         intel_dp_set_link_params(intel_dp,
2602                                  crtc_state->port_clock,
2603                                  crtc_state->lane_count);
2604
2605         intel_pps_on(intel_dp);
2606
2607         intel_ddi_enable_clock(encoder, crtc_state);
2608
2609         if (!intel_phy_is_tc(dev_priv, phy) ||
2610             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2611                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2612                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2613                                                                    dig_port->ddi_io_power_domain);
2614         }
2615
2616         icl_program_mg_dp_mode(dig_port, crtc_state);
2617
2618         if (DISPLAY_VER(dev_priv) >= 11)
2619                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
2620         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2621                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
2622         else
2623                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2624
2625         intel_ddi_power_up_lanes(encoder, crtc_state);
2626
2627         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2628         if (!is_mst)
2629                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2630         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2631         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2632                                               true);
2633         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2634         intel_dp_start_link_train(intel_dp, crtc_state);
2635         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2636             !is_trans_port_sync_mode(crtc_state))
2637                 intel_dp_stop_link_train(intel_dp, crtc_state);
2638
2639         intel_ddi_enable_fec(encoder, crtc_state);
2640
2641         if (!is_mst)
2642                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2643
2644         if (!crtc_state->bigjoiner)
2645                 intel_dsc_enable(encoder, crtc_state);
2646 }
2647
2648 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2649                                     struct intel_encoder *encoder,
2650                                     const struct intel_crtc_state *crtc_state,
2651                                     const struct drm_connector_state *conn_state)
2652 {
2653         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2654
2655         if (IS_DG2(dev_priv))
2656                 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2657         else if (DISPLAY_VER(dev_priv) >= 12)
2658                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2659         else
2660                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2661
2662         /* MST will call a setting of MSA after an allocating of Virtual Channel
2663          * from MST encoder pre_enable callback.
2664          */
2665         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2666                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2667
2668                 intel_dp_set_m_n(crtc_state, M1_N1);
2669         }
2670 }
2671
2672 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2673                                       struct intel_encoder *encoder,
2674                                       const struct intel_crtc_state *crtc_state,
2675                                       const struct drm_connector_state *conn_state)
2676 {
2677         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2678         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2679         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2680
2681         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2682         intel_ddi_enable_clock(encoder, crtc_state);
2683
2684         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2685         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2686                                                            dig_port->ddi_io_power_domain);
2687
2688         icl_program_mg_dp_mode(dig_port, crtc_state);
2689
2690         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2691
2692         dig_port->set_infoframes(encoder,
2693                                  crtc_state->has_infoframe,
2694                                  crtc_state, conn_state);
2695 }
2696
2697 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2698                                  struct intel_encoder *encoder,
2699                                  const struct intel_crtc_state *crtc_state,
2700                                  const struct drm_connector_state *conn_state)
2701 {
2702         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2704         enum pipe pipe = crtc->pipe;
2705
2706         /*
2707          * When called from DP MST code:
2708          * - conn_state will be NULL
2709          * - encoder will be the main encoder (ie. mst->primary)
2710          * - the main connector associated with this port
2711          *   won't be active or linked to a crtc
2712          * - crtc_state will be the state of the first stream to
2713          *   be activated on this port, and it may not be the same
2714          *   stream that will be deactivated last, but each stream
2715          *   should have a state that is identical when it comes to
2716          *   the DP link parameteres
2717          */
2718
2719         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2720
2721         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2722
2723         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2724                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2725                                           conn_state);
2726         } else {
2727                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2728
2729                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2730                                         conn_state);
2731
2732                 /* FIXME precompute everything properly */
2733                 /* FIXME how do we turn infoframes off again? */
2734                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2735                         dig_port->set_infoframes(encoder,
2736                                                  crtc_state->has_infoframe,
2737                                                  crtc_state, conn_state);
2738         }
2739 }
2740
2741 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2742                                   const struct intel_crtc_state *crtc_state)
2743 {
2744         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2745         enum port port = encoder->port;
2746         bool wait = false;
2747         u32 val;
2748
2749         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2750         if (val & DDI_BUF_CTL_ENABLE) {
2751                 val &= ~DDI_BUF_CTL_ENABLE;
2752                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2753                 wait = true;
2754         }
2755
2756         if (intel_crtc_has_dp_encoder(crtc_state)) {
2757                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2758                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2759                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2760                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2761         }
2762
2763         /* Disable FEC in DP Sink */
2764         intel_ddi_disable_fec_state(encoder, crtc_state);
2765
2766         if (wait)
2767                 intel_wait_ddi_buf_idle(dev_priv, port);
2768 }
2769
2770 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2771                                       struct intel_encoder *encoder,
2772                                       const struct intel_crtc_state *old_crtc_state,
2773                                       const struct drm_connector_state *old_conn_state)
2774 {
2775         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2776         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2777         struct intel_dp *intel_dp = &dig_port->dp;
2778         bool is_mst = intel_crtc_has_type(old_crtc_state,
2779                                           INTEL_OUTPUT_DP_MST);
2780         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2781
2782         if (!is_mst)
2783                 intel_dp_set_infoframes(encoder, false,
2784                                         old_crtc_state, old_conn_state);
2785
2786         /*
2787          * Power down sink before disabling the port, otherwise we end
2788          * up getting interrupts from the sink on detecting link loss.
2789          */
2790         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2791
2792         if (DISPLAY_VER(dev_priv) >= 12) {
2793                 if (is_mst) {
2794                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2795                         u32 val;
2796
2797                         val = intel_de_read(dev_priv,
2798                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
2799                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
2800                                  TRANS_DDI_MODE_SELECT_MASK);
2801                         intel_de_write(dev_priv,
2802                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
2803                                        val);
2804                 }
2805         } else {
2806                 if (!is_mst)
2807                         intel_ddi_disable_pipe_clock(old_crtc_state);
2808         }
2809
2810         intel_disable_ddi_buf(encoder, old_crtc_state);
2811
2812         /*
2813          * From TGL spec: "If single stream or multi-stream master transcoder:
2814          * Configure Transcoder Clock select to direct no clock to the
2815          * transcoder"
2816          */
2817         if (DISPLAY_VER(dev_priv) >= 12)
2818                 intel_ddi_disable_pipe_clock(old_crtc_state);
2819
2820         intel_pps_vdd_on(intel_dp);
2821         intel_pps_off(intel_dp);
2822
2823         if (!intel_phy_is_tc(dev_priv, phy) ||
2824             dig_port->tc_mode != TC_PORT_TBT_ALT)
2825                 intel_display_power_put(dev_priv,
2826                                         dig_port->ddi_io_power_domain,
2827                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2828
2829         intel_ddi_disable_clock(encoder);
2830 }
2831
2832 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2833                                         struct intel_encoder *encoder,
2834                                         const struct intel_crtc_state *old_crtc_state,
2835                                         const struct drm_connector_state *old_conn_state)
2836 {
2837         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2838         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2839         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2840
2841         dig_port->set_infoframes(encoder, false,
2842                                  old_crtc_state, old_conn_state);
2843
2844         intel_ddi_disable_pipe_clock(old_crtc_state);
2845
2846         intel_disable_ddi_buf(encoder, old_crtc_state);
2847
2848         intel_display_power_put(dev_priv,
2849                                 dig_port->ddi_io_power_domain,
2850                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2851
2852         intel_ddi_disable_clock(encoder);
2853
2854         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2855 }
2856
2857 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2858                                    struct intel_encoder *encoder,
2859                                    const struct intel_crtc_state *old_crtc_state,
2860                                    const struct drm_connector_state *old_conn_state)
2861 {
2862         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2863         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2864         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2865         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2866
2867         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2868                 intel_crtc_vblank_off(old_crtc_state);
2869
2870                 intel_disable_transcoder(old_crtc_state);
2871
2872                 intel_vrr_disable(old_crtc_state);
2873
2874                 intel_ddi_disable_transcoder_func(old_crtc_state);
2875
2876                 intel_dsc_disable(old_crtc_state);
2877
2878                 if (DISPLAY_VER(dev_priv) >= 9)
2879                         skl_scaler_disable(old_crtc_state);
2880                 else
2881                         ilk_pfit_disable(old_crtc_state);
2882         }
2883
2884         if (old_crtc_state->bigjoiner_linked_crtc) {
2885                 struct intel_atomic_state *state =
2886                         to_intel_atomic_state(old_crtc_state->uapi.state);
2887                 struct intel_crtc *slave =
2888                         old_crtc_state->bigjoiner_linked_crtc;
2889                 const struct intel_crtc_state *old_slave_crtc_state =
2890                         intel_atomic_get_old_crtc_state(state, slave);
2891
2892                 intel_crtc_vblank_off(old_slave_crtc_state);
2893
2894                 intel_dsc_disable(old_slave_crtc_state);
2895                 skl_scaler_disable(old_slave_crtc_state);
2896         }
2897
2898         /*
2899          * When called from DP MST code:
2900          * - old_conn_state will be NULL
2901          * - encoder will be the main encoder (ie. mst->primary)
2902          * - the main connector associated with this port
2903          *   won't be active or linked to a crtc
2904          * - old_crtc_state will be the state of the last stream to
2905          *   be deactivated on this port, and it may not be the same
2906          *   stream that was activated last, but each stream
2907          *   should have a state that is identical when it comes to
2908          *   the DP link parameteres
2909          */
2910
2911         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2912                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2913                                             old_conn_state);
2914         else
2915                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2916                                           old_conn_state);
2917
2918         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2919                 intel_display_power_put(dev_priv,
2920                                         intel_ddi_main_link_aux_domain(dig_port),
2921                                         fetch_and_zero(&dig_port->aux_wakeref));
2922
2923         if (is_tc_port)
2924                 intel_tc_port_put_link(dig_port);
2925 }
2926
2927 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
2928                                 struct intel_encoder *encoder,
2929                                 const struct intel_crtc_state *old_crtc_state,
2930                                 const struct drm_connector_state *old_conn_state)
2931 {
2932         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2933         u32 val;
2934
2935         /*
2936          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2937          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2938          * step 13 is the correct place for it. Step 18 is where it was
2939          * originally before the BUN.
2940          */
2941         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2942         val &= ~FDI_RX_ENABLE;
2943         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2944
2945         intel_disable_ddi_buf(encoder, old_crtc_state);
2946         intel_ddi_disable_clock(encoder);
2947
2948         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
2949         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2950         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2951         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
2952
2953         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2954         val &= ~FDI_PCDCLK;
2955         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2956
2957         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2958         val &= ~FDI_RX_PLL_ENABLE;
2959         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2960 }
2961
2962 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2963                                             struct intel_encoder *encoder,
2964                                             const struct intel_crtc_state *crtc_state)
2965 {
2966         const struct drm_connector_state *conn_state;
2967         struct drm_connector *conn;
2968         int i;
2969
2970         if (!crtc_state->sync_mode_slaves_mask)
2971                 return;
2972
2973         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2974                 struct intel_encoder *slave_encoder =
2975                         to_intel_encoder(conn_state->best_encoder);
2976                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2977                 const struct intel_crtc_state *slave_crtc_state;
2978
2979                 if (!slave_crtc)
2980                         continue;
2981
2982                 slave_crtc_state =
2983                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2984
2985                 if (slave_crtc_state->master_transcoder !=
2986                     crtc_state->cpu_transcoder)
2987                         continue;
2988
2989                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2990                                          slave_crtc_state);
2991         }
2992
2993         usleep_range(200, 400);
2994
2995         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2996                                  crtc_state);
2997 }
2998
2999 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3000                                 struct intel_encoder *encoder,
3001                                 const struct intel_crtc_state *crtc_state,
3002                                 const struct drm_connector_state *conn_state)
3003 {
3004         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3005         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3006         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3007         enum port port = encoder->port;
3008
3009         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3010                 intel_dp_stop_link_train(intel_dp, crtc_state);
3011
3012         intel_edp_backlight_on(crtc_state, conn_state);
3013         intel_psr_enable(intel_dp, crtc_state, conn_state);
3014
3015         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
3016                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3017
3018         intel_drrs_enable(intel_dp, crtc_state);
3019
3020         if (crtc_state->has_audio)
3021                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3022
3023         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3024 }
3025
3026 static i915_reg_t
3027 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3028                                enum port port)
3029 {
3030         static const enum transcoder trans[] = {
3031                 [PORT_A] = TRANSCODER_EDP,
3032                 [PORT_B] = TRANSCODER_A,
3033                 [PORT_C] = TRANSCODER_B,
3034                 [PORT_D] = TRANSCODER_C,
3035                 [PORT_E] = TRANSCODER_A,
3036         };
3037
3038         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3039
3040         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3041                 port = PORT_A;
3042
3043         return CHICKEN_TRANS(trans[port]);
3044 }
3045
3046 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3047                                   struct intel_encoder *encoder,
3048                                   const struct intel_crtc_state *crtc_state,
3049                                   const struct drm_connector_state *conn_state)
3050 {
3051         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3052         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3053         struct drm_connector *connector = conn_state->connector;
3054         int level = intel_ddi_hdmi_level(encoder, crtc_state);
3055         enum port port = encoder->port;
3056
3057         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3058                                                crtc_state->hdmi_high_tmds_clock_ratio,
3059                                                crtc_state->hdmi_scrambling))
3060                 drm_dbg_kms(&dev_priv->drm,
3061                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3062                             connector->base.id, connector->name);
3063
3064         if (IS_DG2(dev_priv))
3065                 intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
3066         else if (DISPLAY_VER(dev_priv) >= 12)
3067                 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3068         else if (DISPLAY_VER(dev_priv) == 11)
3069                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3070         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3071                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3072         else
3073                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level);
3074
3075         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
3076                 skl_ddi_set_iboost(encoder, crtc_state, level);
3077
3078         /* Display WA #1143: skl,kbl,cfl */
3079         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3080                 /*
3081                  * For some reason these chicken bits have been
3082                  * stuffed into a transcoder register, event though
3083                  * the bits affect a specific DDI port rather than
3084                  * a specific transcoder.
3085                  */
3086                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3087                 u32 val;
3088
3089                 val = intel_de_read(dev_priv, reg);
3090
3091                 if (port == PORT_E)
3092                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3093                                 DDIE_TRAINING_OVERRIDE_VALUE;
3094                 else
3095                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3096                                 DDI_TRAINING_OVERRIDE_VALUE;
3097
3098                 intel_de_write(dev_priv, reg, val);
3099                 intel_de_posting_read(dev_priv, reg);
3100
3101                 udelay(1);
3102
3103                 if (port == PORT_E)
3104                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3105                                  DDIE_TRAINING_OVERRIDE_VALUE);
3106                 else
3107                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3108                                  DDI_TRAINING_OVERRIDE_VALUE);
3109
3110                 intel_de_write(dev_priv, reg, val);
3111         }
3112
3113         intel_ddi_power_up_lanes(encoder, crtc_state);
3114
3115         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3116          * are ignored so nothing special needs to be done besides
3117          * enabling the port.
3118          *
3119          * On ADL_P the PHY link rate and lane count must be programmed but
3120          * these are both 0 for HDMI.
3121          */
3122         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3123                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3124
3125         if (crtc_state->has_audio)
3126                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3127 }
3128
3129 static void intel_enable_ddi(struct intel_atomic_state *state,
3130                              struct intel_encoder *encoder,
3131                              const struct intel_crtc_state *crtc_state,
3132                              const struct drm_connector_state *conn_state)
3133 {
3134         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3135
3136         if (!crtc_state->bigjoiner_slave)
3137                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3138
3139         intel_vrr_enable(encoder, crtc_state);
3140
3141         intel_enable_transcoder(crtc_state);
3142
3143         intel_crtc_vblank_on(crtc_state);
3144
3145         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3146                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3147         else
3148                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3149
3150         /* Enable hdcp if it's desired */
3151         if (conn_state->content_protection ==
3152             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3153                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3154                                   crtc_state,
3155                                   (u8)conn_state->hdcp_content_type);
3156 }
3157
3158 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3159                                  struct intel_encoder *encoder,
3160                                  const struct intel_crtc_state *old_crtc_state,
3161                                  const struct drm_connector_state *old_conn_state)
3162 {
3163         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3164
3165         intel_dp->link_trained = false;
3166
3167         intel_edp_backlight_off(old_conn_state);
3168         /* Disable the decompression in DP Sink */
3169         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3170                                               false);
3171         /* Disable Ignore_MSA bit in DP Sink */
3172         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3173                                                       false);
3174 }
3175
3176 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3177                                    struct intel_encoder *encoder,
3178                                    const struct intel_crtc_state *old_crtc_state,
3179                                    const struct drm_connector_state *old_conn_state)
3180 {
3181         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3182         struct drm_connector *connector = old_conn_state->connector;
3183
3184         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3185                                                false, false))
3186                 drm_dbg_kms(&i915->drm,
3187                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3188                             connector->base.id, connector->name);
3189 }
3190
3191 static void intel_pre_disable_ddi(struct intel_atomic_state *state,
3192                                   struct intel_encoder *encoder,
3193                                   const struct intel_crtc_state *old_crtc_state,
3194                                   const struct drm_connector_state *old_conn_state)
3195 {
3196         struct intel_dp *intel_dp;
3197
3198         if (old_crtc_state->has_audio)
3199                 intel_audio_codec_disable(encoder, old_crtc_state,
3200                                           old_conn_state);
3201
3202         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3203                 return;
3204
3205         intel_dp = enc_to_intel_dp(encoder);
3206         intel_drrs_disable(intel_dp, old_crtc_state);
3207         intel_psr_disable(intel_dp, old_crtc_state);
3208 }
3209
3210 static void intel_disable_ddi(struct intel_atomic_state *state,
3211                               struct intel_encoder *encoder,
3212                               const struct intel_crtc_state *old_crtc_state,
3213                               const struct drm_connector_state *old_conn_state)
3214 {
3215         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3216
3217         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3218                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3219                                        old_conn_state);
3220         else
3221                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3222                                      old_conn_state);
3223 }
3224
3225 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3226                                      struct intel_encoder *encoder,
3227                                      const struct intel_crtc_state *crtc_state,
3228                                      const struct drm_connector_state *conn_state)
3229 {
3230         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3231
3232         intel_ddi_set_dp_msa(crtc_state, conn_state);
3233
3234         intel_psr_update(intel_dp, crtc_state, conn_state);
3235         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3236         intel_drrs_update(intel_dp, crtc_state);
3237
3238         intel_backlight_update(state, encoder, crtc_state, conn_state);
3239 }
3240
3241 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3242                            struct intel_encoder *encoder,
3243                            const struct intel_crtc_state *crtc_state,
3244                            const struct drm_connector_state *conn_state)
3245 {
3246
3247         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3248             !intel_encoder_is_mst(encoder))
3249                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3250                                          conn_state);
3251
3252         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3253 }
3254
3255 static void
3256 intel_ddi_update_prepare(struct intel_atomic_state *state,
3257                          struct intel_encoder *encoder,
3258                          struct intel_crtc *crtc)
3259 {
3260         struct intel_crtc_state *crtc_state =
3261                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3262         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3263
3264         drm_WARN_ON(state->base.dev, crtc && crtc->active);
3265
3266         intel_tc_port_get_link(enc_to_dig_port(encoder),
3267                                required_lanes);
3268         if (crtc_state && crtc_state->hw.active)
3269                 intel_update_active_dpll(state, crtc, encoder);
3270 }
3271
3272 static void
3273 intel_ddi_update_complete(struct intel_atomic_state *state,
3274                           struct intel_encoder *encoder,
3275                           struct intel_crtc *crtc)
3276 {
3277         intel_tc_port_put_link(enc_to_dig_port(encoder));
3278 }
3279
3280 static void
3281 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3282                          struct intel_encoder *encoder,
3283                          const struct intel_crtc_state *crtc_state,
3284                          const struct drm_connector_state *conn_state)
3285 {
3286         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3287         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3288         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3289         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3290
3291         if (is_tc_port)
3292                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3293
3294         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3295                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3296                 dig_port->aux_wakeref =
3297                         intel_display_power_get(dev_priv,
3298                                                 intel_ddi_main_link_aux_domain(dig_port));
3299         }
3300
3301         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3302                 /*
3303                  * Program the lane count for static/dynamic connections on
3304                  * Type-C ports.  Skip this step for TBT.
3305                  */
3306                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3307         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3308                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3309                                                 crtc_state->lane_lat_optim_mask);
3310 }
3311
3312 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3313                                            const struct intel_crtc_state *crtc_state)
3314 {
3315         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3316         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3317         enum port port = encoder->port;
3318         u32 dp_tp_ctl, ddi_buf_ctl;
3319         bool wait = false;
3320
3321         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3322
3323         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3324                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3325                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3326                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3327                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3328                         wait = true;
3329                 }
3330
3331                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3332                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3333                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3334                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3335
3336                 if (wait)
3337                         intel_wait_ddi_buf_idle(dev_priv, port);
3338         }
3339
3340         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3341         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3342                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3343         } else {
3344                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3345                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3346                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3347         }
3348         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3349         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3350
3351         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3352         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3353         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3354
3355         intel_wait_ddi_buf_active(dev_priv, port);
3356 }
3357
3358 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3359                                      const struct intel_crtc_state *crtc_state,
3360                                      u8 dp_train_pat)
3361 {
3362         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3363         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3364         u32 temp;
3365
3366         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3367
3368         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3369         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3370         case DP_TRAINING_PATTERN_DISABLE:
3371                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3372                 break;
3373         case DP_TRAINING_PATTERN_1:
3374                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3375                 break;
3376         case DP_TRAINING_PATTERN_2:
3377                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3378                 break;
3379         case DP_TRAINING_PATTERN_3:
3380                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3381                 break;
3382         case DP_TRAINING_PATTERN_4:
3383                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3384                 break;
3385         }
3386
3387         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3388 }
3389
3390 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3391                                           const struct intel_crtc_state *crtc_state)
3392 {
3393         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3394         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3395         enum port port = encoder->port;
3396         u32 val;
3397
3398         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3399         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3400         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3401         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3402
3403         /*
3404          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3405          * reason we need to set idle transmission mode is to work around a HW
3406          * issue where we enable the pipe while not in idle link-training mode.
3407          * In this case there is requirement to wait for a minimum number of
3408          * idle patterns to be sent.
3409          */
3410         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3411                 return;
3412
3413         if (intel_de_wait_for_set(dev_priv,
3414                                   dp_tp_status_reg(encoder, crtc_state),
3415                                   DP_TP_STATUS_IDLE_DONE, 1))
3416                 drm_err(&dev_priv->drm,
3417                         "Timed out waiting for DP idle patterns\n");
3418 }
3419
3420 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3421                                        enum transcoder cpu_transcoder)
3422 {
3423         if (cpu_transcoder == TRANSCODER_EDP)
3424                 return false;
3425
3426         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3427                 return false;
3428
3429         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3430                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3431 }
3432
3433 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3434                                          struct intel_crtc_state *crtc_state)
3435 {
3436         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3437                 crtc_state->min_voltage_level = 2;
3438         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3439                 crtc_state->min_voltage_level = 3;
3440         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3441                 crtc_state->min_voltage_level = 1;
3442 }
3443
3444 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3445                                                      enum transcoder cpu_transcoder)
3446 {
3447         u32 master_select;
3448
3449         if (DISPLAY_VER(dev_priv) >= 11) {
3450                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3451
3452                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3453                         return INVALID_TRANSCODER;
3454
3455                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3456         } else {
3457                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3458
3459                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3460                         return INVALID_TRANSCODER;
3461
3462                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3463         }
3464
3465         if (master_select == 0)
3466                 return TRANSCODER_EDP;
3467         else
3468                 return master_select - 1;
3469 }
3470
3471 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3472 {
3473         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3474         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3475                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3476         enum transcoder cpu_transcoder;
3477
3478         crtc_state->master_transcoder =
3479                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3480
3481         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3482                 enum intel_display_power_domain power_domain;
3483                 intel_wakeref_t trans_wakeref;
3484
3485                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3486                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3487                                                                    power_domain);
3488
3489                 if (!trans_wakeref)
3490                         continue;
3491
3492                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3493                     crtc_state->cpu_transcoder)
3494                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3495
3496                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3497         }
3498
3499         drm_WARN_ON(&dev_priv->drm,
3500                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3501                     crtc_state->sync_mode_slaves_mask);
3502 }
3503
3504 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3505                                     struct intel_crtc_state *pipe_config)
3506 {
3507         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3508         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3509         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3510         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3511         u32 temp, flags = 0;
3512
3513         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3514         if (temp & TRANS_DDI_PHSYNC)
3515                 flags |= DRM_MODE_FLAG_PHSYNC;
3516         else
3517                 flags |= DRM_MODE_FLAG_NHSYNC;
3518         if (temp & TRANS_DDI_PVSYNC)
3519                 flags |= DRM_MODE_FLAG_PVSYNC;
3520         else
3521                 flags |= DRM_MODE_FLAG_NVSYNC;
3522
3523         pipe_config->hw.adjusted_mode.flags |= flags;
3524
3525         switch (temp & TRANS_DDI_BPC_MASK) {
3526         case TRANS_DDI_BPC_6:
3527                 pipe_config->pipe_bpp = 18;
3528                 break;
3529         case TRANS_DDI_BPC_8:
3530                 pipe_config->pipe_bpp = 24;
3531                 break;
3532         case TRANS_DDI_BPC_10:
3533                 pipe_config->pipe_bpp = 30;
3534                 break;
3535         case TRANS_DDI_BPC_12:
3536                 pipe_config->pipe_bpp = 36;
3537                 break;
3538         default:
3539                 break;
3540         }
3541
3542         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3543         case TRANS_DDI_MODE_SELECT_HDMI:
3544                 pipe_config->has_hdmi_sink = true;
3545
3546                 pipe_config->infoframes.enable |=
3547                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3548
3549                 if (pipe_config->infoframes.enable)
3550                         pipe_config->has_infoframe = true;
3551
3552                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3553                         pipe_config->hdmi_scrambling = true;
3554                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3555                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3556                 fallthrough;
3557         case TRANS_DDI_MODE_SELECT_DVI:
3558                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3559                 pipe_config->lane_count = 4;
3560                 break;
3561         case TRANS_DDI_MODE_SELECT_FDI:
3562                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3563                 break;
3564         case TRANS_DDI_MODE_SELECT_DP_SST:
3565                 if (encoder->type == INTEL_OUTPUT_EDP)
3566                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3567                 else
3568                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3569                 pipe_config->lane_count =
3570                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3571                 intel_dp_get_m_n(crtc, pipe_config);
3572
3573                 if (DISPLAY_VER(dev_priv) >= 11) {
3574                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3575
3576                         pipe_config->fec_enable =
3577                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3578
3579                         drm_dbg_kms(&dev_priv->drm,
3580                                     "[ENCODER:%d:%s] Fec status: %u\n",
3581                                     encoder->base.base.id, encoder->base.name,
3582                                     pipe_config->fec_enable);
3583                 }
3584
3585                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3586                         pipe_config->infoframes.enable |=
3587                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3588                 else
3589                         pipe_config->infoframes.enable |=
3590                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3591                 break;
3592         case TRANS_DDI_MODE_SELECT_DP_MST:
3593                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3594                 pipe_config->lane_count =
3595                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3596
3597                 if (DISPLAY_VER(dev_priv) >= 12)
3598                         pipe_config->mst_master_transcoder =
3599                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3600
3601                 intel_dp_get_m_n(crtc, pipe_config);
3602
3603                 pipe_config->infoframes.enable |=
3604                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3605                 break;
3606         default:
3607                 break;
3608         }
3609 }
3610
3611 static void intel_ddi_get_config(struct intel_encoder *encoder,
3612                                  struct intel_crtc_state *pipe_config)
3613 {
3614         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3615         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3616
3617         /* XXX: DSI transcoder paranoia */
3618         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3619                 return;
3620
3621         if (pipe_config->bigjoiner_slave) {
3622                 /* read out pipe settings from master */
3623                 enum transcoder save = pipe_config->cpu_transcoder;
3624
3625                 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
3626                 WARN_ON(pipe_config->output_types);
3627                 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
3628                 intel_ddi_read_func_ctl(encoder, pipe_config);
3629                 pipe_config->cpu_transcoder = save;
3630         } else {
3631                 intel_ddi_read_func_ctl(encoder, pipe_config);
3632         }
3633
3634         intel_ddi_mso_get_config(encoder, pipe_config);
3635
3636         pipe_config->has_audio =
3637                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3638
3639         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3640             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3641                 /*
3642                  * This is a big fat ugly hack.
3643                  *
3644                  * Some machines in UEFI boot mode provide us a VBT that has 18
3645                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3646                  * unknown we fail to light up. Yet the same BIOS boots up with
3647                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3648                  * max, not what it tells us to use.
3649                  *
3650                  * Note: This will still be broken if the eDP panel is not lit
3651                  * up by the BIOS, and thus we can't get the mode at module
3652                  * load.
3653                  */
3654                 drm_dbg_kms(&dev_priv->drm,
3655                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3656                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3657                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3658         }
3659
3660         if (!pipe_config->bigjoiner_slave)
3661                 ddi_dotclock_get(pipe_config);
3662
3663         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3664                 pipe_config->lane_lat_optim_mask =
3665                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3666
3667         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3668
3669         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3670
3671         intel_read_infoframe(encoder, pipe_config,
3672                              HDMI_INFOFRAME_TYPE_AVI,
3673                              &pipe_config->infoframes.avi);
3674         intel_read_infoframe(encoder, pipe_config,
3675                              HDMI_INFOFRAME_TYPE_SPD,
3676                              &pipe_config->infoframes.spd);
3677         intel_read_infoframe(encoder, pipe_config,
3678                              HDMI_INFOFRAME_TYPE_VENDOR,
3679                              &pipe_config->infoframes.hdmi);
3680         intel_read_infoframe(encoder, pipe_config,
3681                              HDMI_INFOFRAME_TYPE_DRM,
3682                              &pipe_config->infoframes.drm);
3683
3684         if (DISPLAY_VER(dev_priv) >= 8)
3685                 bdw_get_trans_port_sync_config(pipe_config);
3686
3687         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3688         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3689
3690         intel_psr_get_config(encoder, pipe_config);
3691 }
3692
3693 void intel_ddi_get_clock(struct intel_encoder *encoder,
3694                          struct intel_crtc_state *crtc_state,
3695                          struct intel_shared_dpll *pll)
3696 {
3697         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3698         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3699         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3700         bool pll_active;
3701
3702         if (drm_WARN_ON(&i915->drm, !pll))
3703                 return;
3704
3705         port_dpll->pll = pll;
3706         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3707         drm_WARN_ON(&i915->drm, !pll_active);
3708
3709         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3710
3711         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3712                                                      &crtc_state->dpll_hw_state);
3713 }
3714
3715 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3716                                 struct intel_crtc_state *crtc_state)
3717 {
3718         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3719         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3720
3721         intel_ddi_get_config(encoder, crtc_state);
3722 }
3723
3724 static void adls_ddi_get_config(struct intel_encoder *encoder,
3725                                 struct intel_crtc_state *crtc_state)
3726 {
3727         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3728         intel_ddi_get_config(encoder, crtc_state);
3729 }
3730
3731 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3732                                struct intel_crtc_state *crtc_state)
3733 {
3734         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3735         intel_ddi_get_config(encoder, crtc_state);
3736 }
3737
3738 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3739                                struct intel_crtc_state *crtc_state)
3740 {
3741         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3742         intel_ddi_get_config(encoder, crtc_state);
3743 }
3744
3745 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3746                                      struct intel_crtc_state *crtc_state)
3747 {
3748         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3749         intel_ddi_get_config(encoder, crtc_state);
3750 }
3751
3752 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3753                                  struct intel_crtc_state *crtc_state,
3754                                  struct intel_shared_dpll *pll)
3755 {
3756         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3757         enum icl_port_dpll_id port_dpll_id;
3758         struct icl_port_dpll *port_dpll;
3759         bool pll_active;
3760
3761         if (drm_WARN_ON(&i915->drm, !pll))
3762                 return;
3763
3764         if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3765                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3766         else
3767                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3768
3769         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3770
3771         port_dpll->pll = pll;
3772         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3773         drm_WARN_ON(&i915->drm, !pll_active);
3774
3775         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3776
3777         if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3778                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3779         else
3780                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3781                                                              &crtc_state->dpll_hw_state);
3782 }
3783
3784 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3785                                   struct intel_crtc_state *crtc_state)
3786 {
3787         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3788         intel_ddi_get_config(encoder, crtc_state);
3789 }
3790
3791 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3792                                struct intel_crtc_state *crtc_state)
3793 {
3794         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3795         intel_ddi_get_config(encoder, crtc_state);
3796 }
3797
3798 static void skl_ddi_get_config(struct intel_encoder *encoder,
3799                                struct intel_crtc_state *crtc_state)
3800 {
3801         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3802         intel_ddi_get_config(encoder, crtc_state);
3803 }
3804
3805 void hsw_ddi_get_config(struct intel_encoder *encoder,
3806                         struct intel_crtc_state *crtc_state)
3807 {
3808         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3809         intel_ddi_get_config(encoder, crtc_state);
3810 }
3811
3812 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3813                                  const struct intel_crtc_state *crtc_state)
3814 {
3815         if (intel_crtc_has_dp_encoder(crtc_state))
3816                 intel_dp_sync_state(encoder, crtc_state);
3817 }
3818
3819 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3820                                             struct intel_crtc_state *crtc_state)
3821 {
3822         if (intel_crtc_has_dp_encoder(crtc_state))
3823                 return intel_dp_initial_fastset_check(encoder, crtc_state);
3824
3825         return true;
3826 }
3827
3828 static enum intel_output_type
3829 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3830                               struct intel_crtc_state *crtc_state,
3831                               struct drm_connector_state *conn_state)
3832 {
3833         switch (conn_state->connector->connector_type) {
3834         case DRM_MODE_CONNECTOR_HDMIA:
3835                 return INTEL_OUTPUT_HDMI;
3836         case DRM_MODE_CONNECTOR_eDP:
3837                 return INTEL_OUTPUT_EDP;
3838         case DRM_MODE_CONNECTOR_DisplayPort:
3839                 return INTEL_OUTPUT_DP;
3840         default:
3841                 MISSING_CASE(conn_state->connector->connector_type);
3842                 return INTEL_OUTPUT_UNUSED;
3843         }
3844 }
3845
3846 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3847                                     struct intel_crtc_state *pipe_config,
3848                                     struct drm_connector_state *conn_state)
3849 {
3850         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3851         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3852         enum port port = encoder->port;
3853         int ret;
3854
3855         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3856                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3857
3858         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3859                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3860         } else {
3861                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3862         }
3863
3864         if (ret)
3865                 return ret;
3866
3867         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3868             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3869                 pipe_config->pch_pfit.force_thru =
3870                         pipe_config->pch_pfit.enabled ||
3871                         pipe_config->crc_enabled;
3872
3873         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3874                 pipe_config->lane_lat_optim_mask =
3875                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3876
3877         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3878
3879         return 0;
3880 }
3881
3882 static bool mode_equal(const struct drm_display_mode *mode1,
3883                        const struct drm_display_mode *mode2)
3884 {
3885         return drm_mode_match(mode1, mode2,
3886                               DRM_MODE_MATCH_TIMINGS |
3887                               DRM_MODE_MATCH_FLAGS |
3888                               DRM_MODE_MATCH_3D_FLAGS) &&
3889                 mode1->clock == mode2->clock; /* we want an exact match */
3890 }
3891
3892 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3893                       const struct intel_link_m_n *m_n_2)
3894 {
3895         return m_n_1->tu == m_n_2->tu &&
3896                 m_n_1->gmch_m == m_n_2->gmch_m &&
3897                 m_n_1->gmch_n == m_n_2->gmch_n &&
3898                 m_n_1->link_m == m_n_2->link_m &&
3899                 m_n_1->link_n == m_n_2->link_n;
3900 }
3901
3902 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3903                                        const struct intel_crtc_state *crtc_state2)
3904 {
3905         return crtc_state1->hw.active && crtc_state2->hw.active &&
3906                 crtc_state1->output_types == crtc_state2->output_types &&
3907                 crtc_state1->output_format == crtc_state2->output_format &&
3908                 crtc_state1->lane_count == crtc_state2->lane_count &&
3909                 crtc_state1->port_clock == crtc_state2->port_clock &&
3910                 mode_equal(&crtc_state1->hw.adjusted_mode,
3911                            &crtc_state2->hw.adjusted_mode) &&
3912                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3913 }
3914
3915 static u8
3916 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3917                                 int tile_group_id)
3918 {
3919         struct drm_connector *connector;
3920         const struct drm_connector_state *conn_state;
3921         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3922         struct intel_atomic_state *state =
3923                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3924         u8 transcoders = 0;
3925         int i;
3926
3927         /*
3928          * We don't enable port sync on BDW due to missing w/as and
3929          * due to not having adjusted the modeset sequence appropriately.
3930          */
3931         if (DISPLAY_VER(dev_priv) < 9)
3932                 return 0;
3933
3934         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3935                 return 0;
3936
3937         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3938                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3939                 const struct intel_crtc_state *crtc_state;
3940
3941                 if (!crtc)
3942                         continue;
3943
3944                 if (!connector->has_tile ||
3945                     connector->tile_group->id !=
3946                     tile_group_id)
3947                         continue;
3948                 crtc_state = intel_atomic_get_new_crtc_state(state,
3949                                                              crtc);
3950                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3951                                                 crtc_state))
3952                         continue;
3953                 transcoders |= BIT(crtc_state->cpu_transcoder);
3954         }
3955
3956         return transcoders;
3957 }
3958
3959 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3960                                          struct intel_crtc_state *crtc_state,
3961                                          struct drm_connector_state *conn_state)
3962 {
3963         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3964         struct drm_connector *connector = conn_state->connector;
3965         u8 port_sync_transcoders = 0;
3966
3967         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3968                     encoder->base.base.id, encoder->base.name,
3969                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3970
3971         if (connector->has_tile)
3972                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3973                                                                         connector->tile_group->id);
3974
3975         /*
3976          * EDP Transcoders cannot be ensalved
3977          * make them a master always when present
3978          */
3979         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3980                 crtc_state->master_transcoder = TRANSCODER_EDP;
3981         else
3982                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3983
3984         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3985                 crtc_state->master_transcoder = INVALID_TRANSCODER;
3986                 crtc_state->sync_mode_slaves_mask =
3987                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3988         }
3989
3990         return 0;
3991 }
3992
3993 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3994 {
3995         struct drm_i915_private *i915 = to_i915(encoder->dev);
3996         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3997
3998         intel_dp_encoder_flush_work(encoder);
3999         intel_display_power_flush_work(i915);
4000
4001         drm_encoder_cleanup(encoder);
4002         if (dig_port)
4003                 kfree(dig_port->hdcp_port_data.streams);
4004         kfree(dig_port);
4005 }
4006
4007 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4008 {
4009         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4010
4011         intel_dp->reset_link_params = true;
4012
4013         intel_pps_encoder_reset(intel_dp);
4014 }
4015
4016 static const struct drm_encoder_funcs intel_ddi_funcs = {
4017         .reset = intel_ddi_encoder_reset,
4018         .destroy = intel_ddi_encoder_destroy,
4019 };
4020
4021 static struct intel_connector *
4022 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4023 {
4024         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4025         struct intel_connector *connector;
4026         enum port port = dig_port->base.port;
4027
4028         connector = intel_connector_alloc();
4029         if (!connector)
4030                 return NULL;
4031
4032         dig_port->dp.output_reg = DDI_BUF_CTL(port);
4033         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4034         dig_port->dp.set_link_train = intel_ddi_set_link_train;
4035         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4036
4037         if (IS_DG2(dev_priv))
4038                 dig_port->dp.set_signal_levels = dg2_set_signal_levels;
4039         else if (DISPLAY_VER(dev_priv) >= 12)
4040                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4041         else if (DISPLAY_VER(dev_priv) >= 11)
4042                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4043         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4044                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4045         else
4046                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4047
4048         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4049         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4050
4051         if (!intel_dp_init_connector(dig_port, connector)) {
4052                 kfree(connector);
4053                 return NULL;
4054         }
4055
4056         return connector;
4057 }
4058
4059 static int modeset_pipe(struct drm_crtc *crtc,
4060                         struct drm_modeset_acquire_ctx *ctx)
4061 {
4062         struct drm_atomic_state *state;
4063         struct drm_crtc_state *crtc_state;
4064         int ret;
4065
4066         state = drm_atomic_state_alloc(crtc->dev);
4067         if (!state)
4068                 return -ENOMEM;
4069
4070         state->acquire_ctx = ctx;
4071
4072         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4073         if (IS_ERR(crtc_state)) {
4074                 ret = PTR_ERR(crtc_state);
4075                 goto out;
4076         }
4077
4078         crtc_state->connectors_changed = true;
4079
4080         ret = drm_atomic_commit(state);
4081 out:
4082         drm_atomic_state_put(state);
4083
4084         return ret;
4085 }
4086
4087 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4088                                  struct drm_modeset_acquire_ctx *ctx)
4089 {
4090         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4091         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4092         struct intel_connector *connector = hdmi->attached_connector;
4093         struct i2c_adapter *adapter =
4094                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4095         struct drm_connector_state *conn_state;
4096         struct intel_crtc_state *crtc_state;
4097         struct intel_crtc *crtc;
4098         u8 config;
4099         int ret;
4100
4101         if (!connector || connector->base.status != connector_status_connected)
4102                 return 0;
4103
4104         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4105                                ctx);
4106         if (ret)
4107                 return ret;
4108
4109         conn_state = connector->base.state;
4110
4111         crtc = to_intel_crtc(conn_state->crtc);
4112         if (!crtc)
4113                 return 0;
4114
4115         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4116         if (ret)
4117                 return ret;
4118
4119         crtc_state = to_intel_crtc_state(crtc->base.state);
4120
4121         drm_WARN_ON(&dev_priv->drm,
4122                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4123
4124         if (!crtc_state->hw.active)
4125                 return 0;
4126
4127         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4128             !crtc_state->hdmi_scrambling)
4129                 return 0;
4130
4131         if (conn_state->commit &&
4132             !try_wait_for_completion(&conn_state->commit->hw_done))
4133                 return 0;
4134
4135         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4136         if (ret < 0) {
4137                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4138                         ret);
4139                 return 0;
4140         }
4141
4142         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4143             crtc_state->hdmi_high_tmds_clock_ratio &&
4144             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4145             crtc_state->hdmi_scrambling)
4146                 return 0;
4147
4148         /*
4149          * HDMI 2.0 says that one should not send scrambled data
4150          * prior to configuring the sink scrambling, and that
4151          * TMDS clock/data transmission should be suspended when
4152          * changing the TMDS clock rate in the sink. So let's
4153          * just do a full modeset here, even though some sinks
4154          * would be perfectly happy if were to just reconfigure
4155          * the SCDC settings on the fly.
4156          */
4157         return modeset_pipe(&crtc->base, ctx);
4158 }
4159
4160 static enum intel_hotplug_state
4161 intel_ddi_hotplug(struct intel_encoder *encoder,
4162                   struct intel_connector *connector)
4163 {
4164         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4165         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4166         struct intel_dp *intel_dp = &dig_port->dp;
4167         enum phy phy = intel_port_to_phy(i915, encoder->port);
4168         bool is_tc = intel_phy_is_tc(i915, phy);
4169         struct drm_modeset_acquire_ctx ctx;
4170         enum intel_hotplug_state state;
4171         int ret;
4172
4173         if (intel_dp->compliance.test_active &&
4174             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4175                 intel_dp_phy_test(encoder);
4176                 /* just do the PHY test and nothing else */
4177                 return INTEL_HOTPLUG_UNCHANGED;
4178         }
4179
4180         state = intel_encoder_hotplug(encoder, connector);
4181
4182         drm_modeset_acquire_init(&ctx, 0);
4183
4184         for (;;) {
4185                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4186                         ret = intel_hdmi_reset_link(encoder, &ctx);
4187                 else
4188                         ret = intel_dp_retrain_link(encoder, &ctx);
4189
4190                 if (ret == -EDEADLK) {
4191                         drm_modeset_backoff(&ctx);
4192                         continue;
4193                 }
4194
4195                 break;
4196         }
4197
4198         drm_modeset_drop_locks(&ctx);
4199         drm_modeset_acquire_fini(&ctx);
4200         drm_WARN(encoder->base.dev, ret,
4201                  "Acquiring modeset locks failed with %i\n", ret);
4202
4203         /*
4204          * Unpowered type-c dongles can take some time to boot and be
4205          * responsible, so here giving some time to those dongles to power up
4206          * and then retrying the probe.
4207          *
4208          * On many platforms the HDMI live state signal is known to be
4209          * unreliable, so we can't use it to detect if a sink is connected or
4210          * not. Instead we detect if it's connected based on whether we can
4211          * read the EDID or not. That in turn has a problem during disconnect,
4212          * since the HPD interrupt may be raised before the DDC lines get
4213          * disconnected (due to how the required length of DDC vs. HPD
4214          * connector pins are specified) and so we'll still be able to get a
4215          * valid EDID. To solve this schedule another detection cycle if this
4216          * time around we didn't detect any change in the sink's connection
4217          * status.
4218          *
4219          * Type-c connectors which get their HPD signal deasserted then
4220          * reasserted, without unplugging/replugging the sink from the
4221          * connector, introduce a delay until the AUX channel communication
4222          * becomes functional. Retry the detection for 5 seconds on type-c
4223          * connectors to account for this delay.
4224          */
4225         if (state == INTEL_HOTPLUG_UNCHANGED &&
4226             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4227             !dig_port->dp.is_mst)
4228                 state = INTEL_HOTPLUG_RETRY;
4229
4230         return state;
4231 }
4232
4233 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4234 {
4235         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4236         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4237
4238         return intel_de_read(dev_priv, SDEISR) & bit;
4239 }
4240
4241 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4242 {
4243         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4244         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4245
4246         return intel_de_read(dev_priv, DEISR) & bit;
4247 }
4248
4249 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4250 {
4251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4252         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4253
4254         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4255 }
4256
4257 static struct intel_connector *
4258 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4259 {
4260         struct intel_connector *connector;
4261         enum port port = dig_port->base.port;
4262
4263         connector = intel_connector_alloc();
4264         if (!connector)
4265                 return NULL;
4266
4267         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4268         intel_hdmi_init_connector(dig_port, connector);
4269
4270         return connector;
4271 }
4272
4273 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4274 {
4275         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4276
4277         if (dig_port->base.port != PORT_A)
4278                 return false;
4279
4280         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4281                 return false;
4282
4283         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4284          *                     supported configuration
4285          */
4286         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4287                 return true;
4288
4289         return false;
4290 }
4291
4292 static int
4293 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4296         enum port port = dig_port->base.port;
4297         int max_lanes = 4;
4298
4299         if (DISPLAY_VER(dev_priv) >= 11)
4300                 return max_lanes;
4301
4302         if (port == PORT_A || port == PORT_E) {
4303                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4304                         max_lanes = port == PORT_A ? 4 : 0;
4305                 else
4306                         /* Both A and E share 2 lanes */
4307                         max_lanes = 2;
4308         }
4309
4310         /*
4311          * Some BIOS might fail to set this bit on port A if eDP
4312          * wasn't lit up at boot.  Force this bit set when needed
4313          * so we use the proper lane count for our calculations.
4314          */
4315         if (intel_ddi_a_force_4_lanes(dig_port)) {
4316                 drm_dbg_kms(&dev_priv->drm,
4317                             "Forcing DDI_A_4_LANES for port A\n");
4318                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4319                 max_lanes = 4;
4320         }
4321
4322         return max_lanes;
4323 }
4324
4325 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4326 {
4327         return i915->hti_state & HDPORT_ENABLED &&
4328                i915->hti_state & HDPORT_DDI_USED(phy);
4329 }
4330
4331 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4332                                   enum port port)
4333 {
4334         if (port >= PORT_D_XELPD)
4335                 return HPD_PORT_D + port - PORT_D_XELPD;
4336         else if (port >= PORT_TC1)
4337                 return HPD_PORT_TC1 + port - PORT_TC1;
4338         else
4339                 return HPD_PORT_A + port - PORT_A;
4340 }
4341
4342 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4343                                 enum port port)
4344 {
4345         if (port >= PORT_TC1)
4346                 return HPD_PORT_C + port - PORT_TC1;
4347         else
4348                 return HPD_PORT_A + port - PORT_A;
4349 }
4350
4351 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4352                                 enum port port)
4353 {
4354         if (port >= PORT_TC1)
4355                 return HPD_PORT_TC1 + port - PORT_TC1;
4356         else
4357                 return HPD_PORT_A + port - PORT_A;
4358 }
4359
4360 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4361                                 enum port port)
4362 {
4363         if (HAS_PCH_TGP(dev_priv))
4364                 return tgl_hpd_pin(dev_priv, port);
4365
4366         if (port >= PORT_TC1)
4367                 return HPD_PORT_C + port - PORT_TC1;
4368         else
4369                 return HPD_PORT_A + port - PORT_A;
4370 }
4371
4372 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4373                                 enum port port)
4374 {
4375         if (port >= PORT_C)
4376                 return HPD_PORT_TC1 + port - PORT_C;
4377         else
4378                 return HPD_PORT_A + port - PORT_A;
4379 }
4380
4381 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4382                                 enum port port)
4383 {
4384         if (port == PORT_D)
4385                 return HPD_PORT_A;
4386
4387         if (HAS_PCH_MCC(dev_priv))
4388                 return icl_hpd_pin(dev_priv, port);
4389
4390         return HPD_PORT_A + port - PORT_A;
4391 }
4392
4393 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4394 {
4395         if (HAS_PCH_TGP(dev_priv))
4396                 return icl_hpd_pin(dev_priv, port);
4397
4398         return HPD_PORT_A + port - PORT_A;
4399 }
4400
4401 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4402 {
4403         if (DISPLAY_VER(i915) >= 12)
4404                 return port >= PORT_TC1;
4405         else if (DISPLAY_VER(i915) >= 11)
4406                 return port >= PORT_C;
4407         else
4408                 return false;
4409 }
4410
4411 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4412 {
4413         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4414         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4415         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4416         enum phy phy = intel_port_to_phy(i915, encoder->port);
4417
4418         intel_dp_encoder_suspend(encoder);
4419
4420         if (!intel_phy_is_tc(i915, phy))
4421                 return;
4422
4423         intel_tc_port_disconnect_phy(dig_port);
4424 }
4425
4426 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4427 {
4428         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4429         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4430         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4431         enum phy phy = intel_port_to_phy(i915, encoder->port);
4432
4433         intel_dp_encoder_shutdown(encoder);
4434
4435         if (!intel_phy_is_tc(i915, phy))
4436                 return;
4437
4438         intel_tc_port_disconnect_phy(dig_port);
4439 }
4440
4441 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4442 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4443
4444 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4445 {
4446         struct intel_digital_port *dig_port;
4447         struct intel_encoder *encoder;
4448         const struct intel_bios_encoder_data *devdata;
4449         bool init_hdmi, init_dp;
4450         enum phy phy = intel_port_to_phy(dev_priv, port);
4451
4452         /*
4453          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4454          * have taken over some of the PHYs and made them unavailable to the
4455          * driver.  In that case we should skip initializing the corresponding
4456          * outputs.
4457          */
4458         if (hti_uses_phy(dev_priv, phy)) {
4459                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4460                             port_name(port), phy_name(phy));
4461                 return;
4462         }
4463
4464         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4465         if (!devdata) {
4466                 drm_dbg_kms(&dev_priv->drm,
4467                             "VBT says port %c is not present\n",
4468                             port_name(port));
4469                 return;
4470         }
4471
4472         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4473                 intel_bios_encoder_supports_hdmi(devdata);
4474         init_dp = intel_bios_encoder_supports_dp(devdata);
4475
4476         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4477                 /*
4478                  * Lspcon device needs to be driven with DP connector
4479                  * with special detection sequence. So make sure DP
4480                  * is initialized before lspcon.
4481                  */
4482                 init_dp = true;
4483                 init_hdmi = false;
4484                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4485                             port_name(port));
4486         }
4487
4488         if (!init_dp && !init_hdmi) {
4489                 drm_dbg_kms(&dev_priv->drm,
4490                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4491                             port_name(port));
4492                 return;
4493         }
4494
4495         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4496         if (!dig_port)
4497                 return;
4498
4499         encoder = &dig_port->base;
4500         encoder->devdata = devdata;
4501
4502         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4503                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4504                                  DRM_MODE_ENCODER_TMDS,
4505                                  "DDI %c/PHY %c",
4506                                  port_name(port - PORT_D_XELPD + PORT_D),
4507                                  phy_name(phy));
4508         } else if (DISPLAY_VER(dev_priv) >= 12) {
4509                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4510
4511                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4512                                  DRM_MODE_ENCODER_TMDS,
4513                                  "DDI %s%c/PHY %s%c",
4514                                  port >= PORT_TC1 ? "TC" : "",
4515                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4516                                  tc_port != TC_PORT_NONE ? "TC" : "",
4517                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4518         } else if (DISPLAY_VER(dev_priv) >= 11) {
4519                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4520
4521                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4522                                  DRM_MODE_ENCODER_TMDS,
4523                                  "DDI %c%s/PHY %s%c",
4524                                  port_name(port),
4525                                  port >= PORT_C ? " (TC)" : "",
4526                                  tc_port != TC_PORT_NONE ? "TC" : "",
4527                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4528         } else {
4529                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4530                                  DRM_MODE_ENCODER_TMDS,
4531                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4532         }
4533
4534         mutex_init(&dig_port->hdcp_mutex);
4535         dig_port->num_hdcp_streams = 0;
4536
4537         encoder->hotplug = intel_ddi_hotplug;
4538         encoder->compute_output_type = intel_ddi_compute_output_type;
4539         encoder->compute_config = intel_ddi_compute_config;
4540         encoder->compute_config_late = intel_ddi_compute_config_late;
4541         encoder->enable = intel_enable_ddi;
4542         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4543         encoder->pre_enable = intel_ddi_pre_enable;
4544         encoder->pre_disable = intel_pre_disable_ddi;
4545         encoder->disable = intel_disable_ddi;
4546         encoder->post_disable = intel_ddi_post_disable;
4547         encoder->update_pipe = intel_ddi_update_pipe;
4548         encoder->get_hw_state = intel_ddi_get_hw_state;
4549         encoder->sync_state = intel_ddi_sync_state;
4550         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4551         encoder->suspend = intel_ddi_encoder_suspend;
4552         encoder->shutdown = intel_ddi_encoder_shutdown;
4553         encoder->get_power_domains = intel_ddi_get_power_domains;
4554
4555         encoder->type = INTEL_OUTPUT_DDI;
4556         encoder->power_domain = intel_port_to_power_domain(port);
4557         encoder->port = port;
4558         encoder->cloneable = 0;
4559         encoder->pipe_mask = ~0;
4560
4561         if (IS_DG2(dev_priv)) {
4562                 encoder->enable_clock = intel_mpllb_enable;
4563                 encoder->disable_clock = intel_mpllb_disable;
4564                 encoder->get_config = dg2_ddi_get_config;
4565         } else if (IS_ALDERLAKE_S(dev_priv)) {
4566                 encoder->enable_clock = adls_ddi_enable_clock;
4567                 encoder->disable_clock = adls_ddi_disable_clock;
4568                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4569                 encoder->get_config = adls_ddi_get_config;
4570         } else if (IS_ROCKETLAKE(dev_priv)) {
4571                 encoder->enable_clock = rkl_ddi_enable_clock;
4572                 encoder->disable_clock = rkl_ddi_disable_clock;
4573                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4574                 encoder->get_config = rkl_ddi_get_config;
4575         } else if (IS_DG1(dev_priv)) {
4576                 encoder->enable_clock = dg1_ddi_enable_clock;
4577                 encoder->disable_clock = dg1_ddi_disable_clock;
4578                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4579                 encoder->get_config = dg1_ddi_get_config;
4580         } else if (IS_JSL_EHL(dev_priv)) {
4581                 if (intel_ddi_is_tc(dev_priv, port)) {
4582                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4583                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4584                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4585                         encoder->get_config = icl_ddi_combo_get_config;
4586                 } else {
4587                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4588                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4589                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4590                         encoder->get_config = icl_ddi_combo_get_config;
4591                 }
4592         } else if (DISPLAY_VER(dev_priv) >= 11) {
4593                 if (intel_ddi_is_tc(dev_priv, port)) {
4594                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4595                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4596                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4597                         encoder->get_config = icl_ddi_tc_get_config;
4598                 } else {
4599                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4600                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4601                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4602                         encoder->get_config = icl_ddi_combo_get_config;
4603                 }
4604         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4605                 /* BXT/GLK have fixed PLL->port mapping */
4606                 encoder->get_config = bxt_ddi_get_config;
4607         } else if (DISPLAY_VER(dev_priv) == 9) {
4608                 encoder->enable_clock = skl_ddi_enable_clock;
4609                 encoder->disable_clock = skl_ddi_disable_clock;
4610                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4611                 encoder->get_config = skl_ddi_get_config;
4612         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4613                 encoder->enable_clock = hsw_ddi_enable_clock;
4614                 encoder->disable_clock = hsw_ddi_disable_clock;
4615                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4616                 encoder->get_config = hsw_ddi_get_config;
4617         }
4618
4619         intel_ddi_buf_trans_init(encoder);
4620
4621         if (DISPLAY_VER(dev_priv) >= 13)
4622                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4623         else if (IS_DG1(dev_priv))
4624                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4625         else if (IS_ROCKETLAKE(dev_priv))
4626                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4627         else if (DISPLAY_VER(dev_priv) >= 12)
4628                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4629         else if (IS_JSL_EHL(dev_priv))
4630                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4631         else if (DISPLAY_VER(dev_priv) == 11)
4632                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4633         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4634                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4635         else
4636                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4637
4638         if (DISPLAY_VER(dev_priv) >= 11)
4639                 dig_port->saved_port_bits =
4640                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4641                         & DDI_BUF_PORT_REVERSAL;
4642         else
4643                 dig_port->saved_port_bits =
4644                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4645                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4646
4647         if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4648                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4649
4650         dig_port->dp.output_reg = INVALID_MMIO_REG;
4651         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4652         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4653
4654         if (intel_phy_is_tc(dev_priv, phy)) {
4655                 bool is_legacy =
4656                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4657                         !intel_bios_encoder_supports_tbt(devdata);
4658
4659                 intel_tc_port_init(dig_port, is_legacy);
4660
4661                 encoder->update_prepare = intel_ddi_update_prepare;
4662                 encoder->update_complete = intel_ddi_update_complete;
4663         }
4664
4665         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4666         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4667                                               port - PORT_A;
4668
4669         if (init_dp) {
4670                 if (!intel_ddi_init_dp_connector(dig_port))
4671                         goto err;
4672
4673                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4674
4675                 if (dig_port->dp.mso_link_count)
4676                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4677         }
4678
4679         /* In theory we don't need the encoder->type check, but leave it just in
4680          * case we have some really bad VBTs... */
4681         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4682                 if (!intel_ddi_init_hdmi_connector(dig_port))
4683                         goto err;
4684         }
4685
4686         if (DISPLAY_VER(dev_priv) >= 11) {
4687                 if (intel_phy_is_tc(dev_priv, phy))
4688                         dig_port->connected = intel_tc_port_connected;
4689                 else
4690                         dig_port->connected = lpt_digital_port_connected;
4691         } else if (DISPLAY_VER(dev_priv) >= 8) {
4692                 if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4693                     IS_BROXTON(dev_priv))
4694                         dig_port->connected = bdw_digital_port_connected;
4695                 else
4696                         dig_port->connected = lpt_digital_port_connected;
4697         } else {
4698                 if (port == PORT_A)
4699                         dig_port->connected = hsw_digital_port_connected;
4700                 else
4701                         dig_port->connected = lpt_digital_port_connected;
4702         }
4703
4704         intel_infoframe_init(dig_port);
4705
4706         return;
4707
4708 err:
4709         drm_encoder_cleanup(&encoder->base);
4710         kfree(dig_port);
4711 }