drivers/gpu/drm/i915/display/intel_cursor.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5 #include <linux/kernel.h>
   6
   7 #include <drm/drm_atomic_helper.h>
   8 #include <drm/drm_atomic_uapi.h>
   9 #include <drm/drm_blend.h>
  10 #include <drm/drm_damage_helper.h>
  11 #include <drm/drm_fourcc.h>
  12
  13 #include "i915_reg.h"
  14 #include "intel_atomic.h"
  15 #include "intel_atomic_plane.h"
  16 #include "intel_cursor.h"
  17 #include "intel_de.h"
  18 #include "intel_display.h"
  19 #include "intel_display_types.h"
  20 #include "intel_fb.h"
  21 #include "intel_fb_pin.h"
  22 #include "intel_frontbuffer.h"
  23 #include "intel_psr.h"
  24 #include "intel_psr_regs.h"
  25 #include "intel_vblank.h"
  26 #include "skl_watermark.h"
  27
  28 #include "gem/i915_gem_object.h"
  29
  30 /* Cursor formats */
  31 static const u32 intel_cursor_formats[] = {
  32         DRM_FORMAT_ARGB8888,
  33 };
  34
  35 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
  36 {
  37         struct drm_i915_private *dev_priv =
  38                 to_i915(plane_state->uapi.plane->dev);
  39         const struct drm_framebuffer *fb = plane_state->hw.fb;
  40         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  41         u32 base;
  42
  43         if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
  44                 base = i915_gem_object_get_dma_address(obj, 0);
  45         else
  46                 base = intel_plane_ggtt_offset(plane_state);
  47
  48         return base + plane_state->view.color_plane[0].offset;
  49 }
  50
  51 static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,
  52                                  const struct intel_plane_state *plane_state,
  53                                  bool early_tpt)
  54 {
  55         int x = plane_state->uapi.dst.x1;
  56         int y = plane_state->uapi.dst.y1;
  57         u32 pos = 0;
  58
  59         /*
  60          * Formula from Bspec:
  61          * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode
  62          * select setting> + 1, CUR_POS Y Position - Update region Y position
  63          */
  64         if (early_tpt)
  65                 y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,
  66                         y - crtc_state->psr2_su_area.y1);
  67
  68         if (x < 0) {
  69                 pos |= CURSOR_POS_X_SIGN;
  70                 x = -x;
  71         }
  72         pos |= CURSOR_POS_X(x);
  73
  74         if (y < 0) {
  75                 pos |= CURSOR_POS_Y_SIGN;
  76                 y = -y;
  77         }
  78         pos |= CURSOR_POS_Y(y);
  79
  80         return pos;
  81 }
  82
  83 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
  84 {
  85         const struct drm_mode_config *config =
  86                 &plane_state->uapi.plane->dev->mode_config;
  87         int width = drm_rect_width(&plane_state->uapi.dst);
  88         int height = drm_rect_height(&plane_state->uapi.dst);
  89
  90         return width > 0 && width <= config->cursor_width &&
  91                 height > 0 && height <= config->cursor_height;
  92 }
  93
  94 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
  95 {
  96         struct drm_i915_private *dev_priv =
  97                 to_i915(plane_state->uapi.plane->dev);
  98         unsigned int rotation = plane_state->hw.rotation;
  99         int src_x, src_y;
 100         u32 offset;
 101         int ret;
 102
 103         ret = intel_plane_compute_gtt(plane_state);
 104         if (ret)
 105                 return ret;
 106
 107         if (!plane_state->uapi.visible)
 108                 return 0;
 109
 110         src_x = plane_state->uapi.src.x1 >> 16;
 111         src_y = plane_state->uapi.src.y1 >> 16;
 112
 113         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 114         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
 115                                                     plane_state, 0);
 116
 117         if (src_x != 0 || src_y != 0) {
 118                 drm_dbg_kms(&dev_priv->drm,
 119                             "Arbitrary cursor panning not supported\n");
 120                 return -EINVAL;
 121         }
 122
 123         /*
 124          * Put the final coordinates back so that the src
 125          * coordinate checks will see the right values.
 126          */
 127         drm_rect_translate_to(&plane_state->uapi.src,
 128                               src_x << 16, src_y << 16);
 129
 130         /* ILK+ do this automagically in hardware */
 131         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
 132                 const struct drm_framebuffer *fb = plane_state->hw.fb;
 133                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 134                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 135
 136                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
 137         }
 138
 139         plane_state->view.color_plane[0].offset = offset;
 140         plane_state->view.color_plane[0].x = src_x;
 141         plane_state->view.color_plane[0].y = src_y;
 142
 143         return 0;
 144 }
 145
 146 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 147                               struct intel_plane_state *plane_state)
 148 {
 149         const struct drm_framebuffer *fb = plane_state->hw.fb;
 150         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 151         const struct drm_rect src = plane_state->uapi.src;
 152         const struct drm_rect dst = plane_state->uapi.dst;
 153         int ret;
 154
 155         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
 156                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
 157                 return -EINVAL;
 158         }
 159
 160         ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
 161                                                 DRM_PLANE_NO_SCALING,
 162                                                 DRM_PLANE_NO_SCALING,
 163                                                 true);
 164         if (ret)
 165                 return ret;
 166
 167         /* Use the unclipped src/dst rectangles, which we program to hw */
 168         plane_state->uapi.src = src;
 169         plane_state->uapi.dst = dst;
 170
 171         /* final plane coordinates will be relative to the plane's pipe */
 172         drm_rect_translate(&plane_state->uapi.dst,
 173                            -crtc_state->pipe_src.x1,
 174                            -crtc_state->pipe_src.y1);
 175
 176         ret = intel_cursor_check_surface(plane_state);
 177         if (ret)
 178                 return ret;
 179
 180         if (!plane_state->uapi.visible)
 181                 return 0;
 182
 183         ret = intel_plane_check_src_coordinates(plane_state);
 184         if (ret)
 185                 return ret;
 186
 187         return 0;
 188 }
 189
 190 static unsigned int
 191 i845_cursor_max_stride(struct intel_plane *plane,
 192                        u32 pixel_format, u64 modifier,
 193                        unsigned int rotation)
 194 {
 195         return 2048;
 196 }
 197
 198 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 199 {
 200         u32 cntl = 0;
 201
 202         if (crtc_state->gamma_enable)
 203                 cntl |= CURSOR_PIPE_GAMMA_ENABLE;
 204
 205         return cntl;
 206 }
 207
 208 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
 209                            const struct intel_plane_state *plane_state)
 210 {
 211         return CURSOR_ENABLE |
 212                 CURSOR_FORMAT_ARGB |
 213                 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
 214 }
 215
 216 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
 217 {
 218         int width = drm_rect_width(&plane_state->uapi.dst);
 219
 220         /*
 221          * 845g/865g are only limited by the width of their cursors,
 222          * the height is arbitrary up to the precision of the register.
 223          */
 224         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
 225 }
 226
 227 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
 228                              struct intel_plane_state *plane_state)
 229 {
 230         const struct drm_framebuffer *fb = plane_state->hw.fb;
 231         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 232         int ret;
 233
 234         ret = intel_check_cursor(crtc_state, plane_state);
 235         if (ret)
 236                 return ret;
 237
 238         /* if we want to turn off the cursor ignore width and height */
 239         if (!fb)
 240                 return 0;
 241
 242         /* Check for which cursor types we support */
 243         if (!i845_cursor_size_ok(plane_state)) {
 244                 drm_dbg_kms(&i915->drm,
 245                             "Cursor dimension %dx%d not supported\n",
 246                             drm_rect_width(&plane_state->uapi.dst),
 247                             drm_rect_height(&plane_state->uapi.dst));
 248                 return -EINVAL;
 249         }
 250
 251         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
 252                     plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
 253
 254         switch (fb->pitches[0]) {
 255         case 256:
 256         case 512:
 257         case 1024:
 258         case 2048:
 259                 break;
 260         default:
 261                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
 262                              fb->pitches[0]);
 263                 return -EINVAL;
 264         }
 265
 266         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
 267
 268         return 0;
 269 }
 270
 271 /* TODO: split into noarm+arm pair */
 272 static void i845_cursor_update_arm(struct intel_plane *plane,
 273                                    const struct intel_crtc_state *crtc_state,
 274                                    const struct intel_plane_state *plane_state)
 275 {
 276         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 277         u32 cntl = 0, base = 0, pos = 0, size = 0;
 278
 279         if (plane_state && plane_state->uapi.visible) {
 280                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
 281                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
 282
 283                 cntl = plane_state->ctl |
 284                         i845_cursor_ctl_crtc(crtc_state);
 285
 286                 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
 287
 288                 base = intel_cursor_base(plane_state);
 289                 pos = intel_cursor_position(crtc_state, plane_state, false);
 290         }
 291
 292         /* On these chipsets we can only modify the base/size/stride
 293          * whilst the cursor is disabled.
 294          */
 295         if (plane->cursor.base != base ||
 296             plane->cursor.size != size ||
 297             plane->cursor.cntl != cntl) {
 298                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
 299                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
 300                 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
 301                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
 302                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
 303
 304                 plane->cursor.base = base;
 305                 plane->cursor.size = size;
 306                 plane->cursor.cntl = cntl;
 307         } else {
 308                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
 309         }
 310 }
 311
 312 static void i845_cursor_disable_arm(struct intel_plane *plane,
 313                                     const struct intel_crtc_state *crtc_state)
 314 {
 315         i845_cursor_update_arm(plane, crtc_state, NULL);
 316 }
 317
 318 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
 319                                      enum pipe *pipe)
 320 {
 321         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 322         enum intel_display_power_domain power_domain;
 323         intel_wakeref_t wakeref;
 324         bool ret;
 325
 326         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
 327         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 328         if (!wakeref)
 329                 return false;
 330
 331         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 332
 333         *pipe = PIPE_A;
 334
 335         intel_display_power_put(dev_priv, power_domain, wakeref);
 336
 337         return ret;
 338 }
 339
 340 static unsigned int
 341 i9xx_cursor_max_stride(struct intel_plane *plane,
 342                        u32 pixel_format, u64 modifier,
 343                        unsigned int rotation)
 344 {
 345         return plane->base.dev->mode_config.cursor_width * 4;
 346 }
 347
 348 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 349 {
 350         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 351         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 352         u32 cntl = 0;
 353
 354         if (DISPLAY_VER(dev_priv) >= 11)
 355                 return cntl;
 356
 357         if (crtc_state->gamma_enable)
 358                 cntl = MCURSOR_PIPE_GAMMA_ENABLE;
 359
 360         if (crtc_state->csc_enable)
 361                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
 362
 363         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 364                 cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
 365
 366         return cntl;
 367 }
 368
 369 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 370                            const struct intel_plane_state *plane_state)
 371 {
 372         struct drm_i915_private *dev_priv =
 373                 to_i915(plane_state->uapi.plane->dev);
 374         u32 cntl = 0;
 375
 376         if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
 377                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
 378
 379         switch (drm_rect_width(&plane_state->uapi.dst)) {
 380         case 64:
 381                 cntl |= MCURSOR_MODE_64_ARGB_AX;
 382                 break;
 383         case 128:
 384                 cntl |= MCURSOR_MODE_128_ARGB_AX;
 385                 break;
 386         case 256:
 387                 cntl |= MCURSOR_MODE_256_ARGB_AX;
 388                 break;
 389         default:
 390                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
 391                 return 0;
 392         }
 393
 394         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
 395                 cntl |= MCURSOR_ROTATE_180;
 396
 397         /* Wa_22012358565:adl-p */
 398         if (DISPLAY_VER(dev_priv) == 13)
 399                 cntl |= MCURSOR_ARB_SLOTS(1);
 400
 401         return cntl;
 402 }
 403
 404 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
 405 {
 406         struct drm_i915_private *dev_priv =
 407                 to_i915(plane_state->uapi.plane->dev);
 408         int width = drm_rect_width(&plane_state->uapi.dst);
 409         int height = drm_rect_height(&plane_state->uapi.dst);
 410
 411         if (!intel_cursor_size_ok(plane_state))
 412                 return false;
 413
 414         /* Cursor width is limited to a few power-of-two sizes */
 415         switch (width) {
 416         case 256:
 417         case 128:
 418         case 64:
 419                 break;
 420         default:
 421                 return false;
 422         }
 423
 424         /*
 425          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
 426          * height from 8 lines up to the cursor width, when the
 427          * cursor is not rotated. Everything else requires square
 428          * cursors.
 429          */
 430         if (HAS_CUR_FBC(dev_priv) &&
 431             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
 432                 if (height < 8 || height > width)
 433                         return false;
 434         } else {
 435                 if (height != width)
 436                         return false;
 437         }
 438
 439         return true;
 440 }
 441
 442 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
 443                              struct intel_plane_state *plane_state)
 444 {
 445         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 446         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 447         const struct drm_framebuffer *fb = plane_state->hw.fb;
 448         enum pipe pipe = plane->pipe;
 449         int ret;
 450
 451         ret = intel_check_cursor(crtc_state, plane_state);
 452         if (ret)
 453                 return ret;
 454
 455         /* if we want to turn off the cursor ignore width and height */
 456         if (!fb)
 457                 return 0;
 458
 459         /* Check for which cursor types we support */
 460         if (!i9xx_cursor_size_ok(plane_state)) {
 461                 drm_dbg(&dev_priv->drm,
 462                         "Cursor dimension %dx%d not supported\n",
 463                         drm_rect_width(&plane_state->uapi.dst),
 464                         drm_rect_height(&plane_state->uapi.dst));
 465                 return -EINVAL;
 466         }
 467
 468         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
 469                     plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
 470
 471         if (fb->pitches[0] !=
 472             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
 473                 drm_dbg_kms(&dev_priv->drm,
 474                             "Invalid cursor stride (%u) (cursor width %d)\n",
 475                             fb->pitches[0],
 476                             drm_rect_width(&plane_state->uapi.dst));
 477                 return -EINVAL;
 478         }
 479
 480         /*
 481          * There's something wrong with the cursor on CHV pipe C.
 482          * If it straddles the left edge of the screen then
 483          * moving it away from the edge or disabling it often
 484          * results in a pipe underrun, and often that can lead to
 485          * dead pipe (constant underrun reported, and it scans
 486          * out just a solid color). To recover from that, the
 487          * display power well must be turned off and on again.
 488          * Refuse the put the cursor into that compromised position.
 489          */
 490         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
 491             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
 492                 drm_dbg_kms(&dev_priv->drm,
 493                             "CHV cursor C not allowed to straddle the left screen edge\n");
 494                 return -EINVAL;
 495         }
 496
 497         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
 498
 499         return 0;
 500 }
 501
 502 static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
 503                                               const struct intel_crtc_state *crtc_state)
 504 {
 505         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 506         enum pipe pipe = plane->pipe;
 507
 508         if (!crtc_state->enable_psr2_sel_fetch)
 509                 return;
 510
 511         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
 512 }
 513
 514 static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
 515                                              const struct intel_crtc_state *crtc_state,
 516                                              const struct intel_plane_state *plane_state)
 517 {
 518         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 519         enum pipe pipe = plane->pipe;
 520
 521         if (!crtc_state->enable_psr2_sel_fetch)
 522                 return;
 523
 524         if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {
 525                 if (crtc_state->enable_psr2_su_region_et) {
 526                         u32 val = intel_cursor_position(crtc_state, plane_state,
 527                                 true);
 528                         intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val);
 529                 }
 530
 531                 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
 532                                   plane_state->ctl);
 533         } else {
 534                 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
 535         }
 536 }
 537
 538 /* TODO: split into noarm+arm pair */
 539 static void i9xx_cursor_update_arm(struct intel_plane *plane,
 540                                    const struct intel_crtc_state *crtc_state,
 541                                    const struct intel_plane_state *plane_state)
 542 {
 543         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 544         enum pipe pipe = plane->pipe;
 545         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
 546
 547         if (plane_state && plane_state->uapi.visible) {
 548                 int width = drm_rect_width(&plane_state->uapi.dst);
 549                 int height = drm_rect_height(&plane_state->uapi.dst);
 550
 551                 cntl = plane_state->ctl |
 552                         i9xx_cursor_ctl_crtc(crtc_state);
 553
 554                 if (width != height)
 555                         fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
 556
 557                 base = intel_cursor_base(plane_state);
 558                 pos = intel_cursor_position(crtc_state, plane_state, false);
 559         }
 560
 561         /*
 562          * On some platforms writing CURCNTR first will also
 563          * cause CURPOS to be armed by the CURBASE write.
 564          * Without the CURCNTR write the CURPOS write would
 565          * arm itself. Thus we always update CURCNTR before
 566          * CURPOS.
 567          *
 568          * On other platforms CURPOS always requires the
 569          * CURBASE write to arm the update. Additonally
 570          * a write to any of the cursor register will cancel
 571          * an already armed cursor update. Thus leaving out
 572          * the CURBASE write after CURPOS could lead to a
 573          * cursor that doesn't appear to move, or even change
 574          * shape. Thus we always write CURBASE.
 575          *
 576          * The other registers are armed by the CURBASE write
 577          * except when the plane is getting enabled at which time
 578          * the CURCNTR write arms the update.
 579          */
 580
 581         if (DISPLAY_VER(dev_priv) >= 9)
 582                 skl_write_cursor_wm(plane, crtc_state);
 583
 584         if (plane_state)
 585                 i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,
 586                                                  plane_state);
 587         else
 588                 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
 589
 590         if (plane->cursor.base != base ||
 591             plane->cursor.size != fbc_ctl ||
 592             plane->cursor.cntl != cntl) {
 593                 if (HAS_CUR_FBC(dev_priv))
 594                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
 595                                           fbc_ctl);
 596                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
 597                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
 598                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
 599
 600                 plane->cursor.base = base;
 601                 plane->cursor.size = fbc_ctl;
 602                 plane->cursor.cntl = cntl;
 603         } else {
 604                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
 605                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
 606         }
 607 }
 608
 609 static void i9xx_cursor_disable_arm(struct intel_plane *plane,
 610                                     const struct intel_crtc_state *crtc_state)
 611 {
 612         i9xx_cursor_update_arm(plane, crtc_state, NULL);
 613 }
 614
 615 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
 616                                      enum pipe *pipe)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 619         enum intel_display_power_domain power_domain;
 620         intel_wakeref_t wakeref;
 621         bool ret;
 622         u32 val;
 623
 624         /*
 625          * Not 100% correct for planes that can move between pipes,
 626          * but that's only the case for gen2-3 which don't have any
 627          * display power wells.
 628          */
 629         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 630         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 631         if (!wakeref)
 632                 return false;
 633
 634         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
 635
 636         ret = val & MCURSOR_MODE_MASK;
 637
 638         if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
 639                 *pipe = plane->pipe;
 640         else
 641                 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
 642
 643         intel_display_power_put(dev_priv, power_domain, wakeref);
 644
 645         return ret;
 646 }
 647
 648 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
 649                                               u32 format, u64 modifier)
 650 {
 651         if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
 652                 return false;
 653
 654         return format == DRM_FORMAT_ARGB8888;
 655 }
 656
 657 static int
 658 intel_legacy_cursor_update(struct drm_plane *_plane,
 659                            struct drm_crtc *_crtc,
 660                            struct drm_framebuffer *fb,
 661                            int crtc_x, int crtc_y,
 662                            unsigned int crtc_w, unsigned int crtc_h,
 663                            u32 src_x, u32 src_y,
 664                            u32 src_w, u32 src_h,
 665                            struct drm_modeset_acquire_ctx *ctx)
 666 {
 667         struct intel_plane *plane = to_intel_plane(_plane);
 668         struct intel_crtc *crtc = to_intel_crtc(_crtc);
 669         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 670         struct intel_plane_state *old_plane_state =
 671                 to_intel_plane_state(plane->base.state);
 672         struct intel_plane_state *new_plane_state;
 673         struct intel_crtc_state *crtc_state =
 674                 to_intel_crtc_state(crtc->base.state);
 675         struct intel_crtc_state *new_crtc_state;
 676         struct intel_vblank_evade_ctx evade;
 677         int ret;
 678
 679         /*
 680          * When crtc is inactive or there is a modeset pending,
 681          * wait for it to complete in the slowpath.
 682          * PSR2 selective fetch also requires the slow path as
 683          * PSR2 plane and transcoder registers can only be updated during
 684          * vblank.
 685          *
 686          * FIXME bigjoiner fastpath would be good
 687          */
 688         if (!crtc_state->hw.active ||
 689             intel_crtc_needs_modeset(crtc_state) ||
 690             intel_crtc_needs_fastset(crtc_state) ||
 691             crtc_state->bigjoiner_pipes)
 692                 goto slow;
 693
 694         /*
 695          * Don't do an async update if there is an outstanding commit modifying
 696          * the plane.  This prevents our async update's changes from getting
 697          * overridden by a previous synchronous update's state.
 698          */
 699         if (old_plane_state->uapi.commit &&
 700             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
 701                 goto slow;
 702
 703         /*
 704          * If any parameters change that may affect watermarks,
 705          * take the slowpath. Only changing fb or position should be
 706          * in the fastpath.
 707          */
 708         if (old_plane_state->uapi.crtc != &crtc->base ||
 709             old_plane_state->uapi.src_w != src_w ||
 710             old_plane_state->uapi.src_h != src_h ||
 711             old_plane_state->uapi.crtc_w != crtc_w ||
 712             old_plane_state->uapi.crtc_h != crtc_h ||
 713             !old_plane_state->uapi.fb != !fb)
 714                 goto slow;
 715
 716         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
 717         if (!new_plane_state)
 718                 return -ENOMEM;
 719
 720         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
 721         if (!new_crtc_state) {
 722                 ret = -ENOMEM;
 723                 goto out_free;
 724         }
 725
 726         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
 727
 728         new_plane_state->uapi.src_x = src_x;
 729         new_plane_state->uapi.src_y = src_y;
 730         new_plane_state->uapi.src_w = src_w;
 731         new_plane_state->uapi.src_h = src_h;
 732         new_plane_state->uapi.crtc_x = crtc_x;
 733         new_plane_state->uapi.crtc_y = crtc_y;
 734         new_plane_state->uapi.crtc_w = crtc_w;
 735         new_plane_state->uapi.crtc_h = crtc_h;
 736
 737         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
 738
 739         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
 740                                                   old_plane_state, new_plane_state);
 741         if (ret)
 742                 goto out_free;
 743
 744         ret = intel_plane_pin_fb(new_plane_state);
 745         if (ret)
 746                 goto out_free;
 747
 748         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
 749                                 ORIGIN_CURSOR_UPDATE);
 750         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
 751                                 to_intel_frontbuffer(new_plane_state->hw.fb),
 752                                 plane->frontbuffer_bit);
 753
 754         /* Swap plane state */
 755         plane->base.state = &new_plane_state->uapi;
 756
 757         /*
 758          * We cannot swap crtc_state as it may be in use by an atomic commit or
 759          * page flip that's running simultaneously. If we swap crtc_state and
 760          * destroy the old state, we will cause a use-after-free there.
 761          *
 762          * Only update active_planes, which is needed for our internal
 763          * bookkeeping. Either value will do the right thing when updating
 764          * planes atomically. If the cursor was part of the atomic update then
 765          * we would have taken the slowpath.
 766          */
 767         crtc_state->active_planes = new_crtc_state->active_planes;
 768
 769         intel_vblank_evade_init(crtc_state, crtc_state, &evade);
 770
 771         intel_psr_lock(crtc_state);
 772
 773         if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) {
 774                 /*
 775                  * TODO: maybe check if we're still in PSR
 776                  * and skip the vblank evasion entirely?
 777                  */
 778                 intel_psr_wait_for_idle_locked(crtc_state);
 779
 780                 local_irq_disable();
 781
 782                 intel_vblank_evade(&evade);
 783
 784                 drm_crtc_vblank_put(&crtc->base);
 785         } else {
 786                 local_irq_disable();
 787         }
 788
 789         if (new_plane_state->uapi.visible) {
 790                 intel_plane_update_noarm(plane, crtc_state, new_plane_state);
 791                 intel_plane_update_arm(plane, crtc_state, new_plane_state);
 792         } else {
 793                 intel_plane_disable_arm(plane, crtc_state);
 794         }
 795
 796         local_irq_enable();
 797
 798         intel_psr_unlock(crtc_state);
 799
 800         intel_plane_unpin_fb(old_plane_state);
 801
 802 out_free:
 803         if (new_crtc_state)
 804                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
 805         if (ret)
 806                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
 807         else
 808                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
 809         return ret;
 810
 811 slow:
 812         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
 813                                               crtc_x, crtc_y, crtc_w, crtc_h,
 814                                               src_x, src_y, src_w, src_h, ctx);
 815 }
 816
 817 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
 818         .update_plane = intel_legacy_cursor_update,
 819         .disable_plane = drm_atomic_helper_disable_plane,
 820         .destroy = intel_plane_destroy,
 821         .atomic_duplicate_state = intel_plane_duplicate_state,
 822         .atomic_destroy_state = intel_plane_destroy_state,
 823         .format_mod_supported = intel_cursor_format_mod_supported,
 824 };
 825
 826 struct intel_plane *
 827 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 828                           enum pipe pipe)
 829 {
 830         struct intel_plane *cursor;
 831         int ret, zpos;
 832         u64 *modifiers;
 833
 834         cursor = intel_plane_alloc();
 835         if (IS_ERR(cursor))
 836                 return cursor;
 837
 838         cursor->pipe = pipe;
 839         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
 840         cursor->id = PLANE_CURSOR;
 841         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
 842
 843         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
 844                 cursor->max_stride = i845_cursor_max_stride;
 845                 cursor->update_arm = i845_cursor_update_arm;
 846                 cursor->disable_arm = i845_cursor_disable_arm;
 847                 cursor->get_hw_state = i845_cursor_get_hw_state;
 848                 cursor->check_plane = i845_check_cursor;
 849         } else {
 850                 cursor->max_stride = i9xx_cursor_max_stride;
 851                 cursor->update_arm = i9xx_cursor_update_arm;
 852                 cursor->disable_arm = i9xx_cursor_disable_arm;
 853                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
 854                 cursor->check_plane = i9xx_check_cursor;
 855         }
 856
 857         cursor->cursor.base = ~0;
 858         cursor->cursor.cntl = ~0;
 859
 860         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
 861                 cursor->cursor.size = ~0;
 862
 863         modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
 864
 865         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
 866                                        0, &intel_cursor_plane_funcs,
 867                                        intel_cursor_formats,
 868                                        ARRAY_SIZE(intel_cursor_formats),
 869                                        modifiers,
 870                                        DRM_PLANE_TYPE_CURSOR,
 871                                        "cursor %c", pipe_name(pipe));
 872
 873         kfree(modifiers);
 874
 875         if (ret)
 876                 goto fail;
 877
 878         if (DISPLAY_VER(dev_priv) >= 4)
 879                 drm_plane_create_rotation_property(&cursor->base,
 880                                                    DRM_MODE_ROTATE_0,
 881                                                    DRM_MODE_ROTATE_0 |
 882                                                    DRM_MODE_ROTATE_180);
 883
 884         zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
 885         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
 886
 887         if (DISPLAY_VER(dev_priv) >= 12)
 888                 drm_plane_enable_fb_damage_clips(&cursor->base);
 889
 890         intel_plane_helper_add(cursor);
 891
 892         return cursor;
 893
 894 fail:
 895         intel_plane_free(cursor);
 896
 897         return ERR_PTR(ret);
 898 }